1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs
{
54 int add
; /* cost of an add instruction */
55 int lea
; /* cost of a lea instruction */
56 int shift_var
; /* variable shift costs */
57 int shift_const
; /* constant shift costs */
58 int mult_init
; /* cost of starting a multiply */
59 int mult_bit
; /* cost of multiply per each bit set */
60 int divide
; /* cost of a divide/mod */
61 int large_insn
; /* insns larger than this cost more */
62 int move_ratio
; /* The threshold of number of scalar
63 memory-to-memory move insns. */
64 int movzbl_load
; /* cost of loading using movzbl */
65 int int_load
[3]; /* cost of loading integer registers
66 in QImode, HImode and SImode relative
67 to reg-reg move (2). */
68 int int_store
[3]; /* cost of storing integer register
69 in QImode, HImode and SImode */
70 int fp_move
; /* cost of reg,reg fld/fst */
71 int fp_load
[3]; /* cost of loading FP register
72 in SFmode, DFmode and XFmode */
73 int fp_store
[3]; /* cost of storing FP register
74 in SFmode, DFmode and XFmode */
75 int mmx_move
; /* cost of moving MMX register. */
76 int mmx_load
[2]; /* cost of loading MMX register
77 in SImode and DImode */
78 int mmx_store
[2]; /* cost of storing MMX register
79 in SImode and DImode */
80 int sse_move
; /* cost of moving SSE register. */
81 int sse_load
[3]; /* cost of loading SSE register
82 in SImode, DImode and TImode*/
83 int sse_store
[3]; /* cost of storing SSE register
84 in SImode, DImode and TImode*/
85 int mmxsse_to_integer
; /* cost of moving mmxsse register to
86 integer and vice versa. */
89 extern struct processor_costs
*ix86_cost
;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags
;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #define TARGET_CPU_DEFAULT 0
103 /* Masks for the -m switches */
104 #define MASK_80387 0x00000001 /* Hardware floating point */
105 #define MASK_RTD 0x00000002 /* Use ret that pops args */
106 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
107 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
108 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
109 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
110 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
111 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
112 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
113 #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
114 #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
115 #define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
116 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
117 #define MASK_MMX 0x00010000 /* Support MMX regs/builtins */
118 #define MASK_SSE 0x00020000 /* Support SSE regs/builtins */
119 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
120 #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
121 #define MASK_MIX_SSE_I387 0x00100000 /* Mix SSE and i387 instructions */
122 #define MASK_64BIT 0x00200000 /* Produce 64bit code */
123 #define MASK_NO_RED_ZONE 0x00400000 /* Do not use red zone */
125 /* Temporary codegen switches */
126 #define MASK_INTEL_SYNTAX 0x00000200
127 #define MASK_DEBUG_ARG 0x00000400 /* function_arg */
128 #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */
130 /* Use the floating point instructions */
131 #define TARGET_80387 (target_flags & MASK_80387)
133 /* Compile using ret insn that pops args.
134 This will not work unless you use prototypes at least
135 for all functions that can take varying numbers of args. */
136 #define TARGET_RTD (target_flags & MASK_RTD)
138 /* Align doubles to a two word boundary. This breaks compatibility with
139 the published ABI's for structures containing doubles, but produces
140 faster code on the pentium. */
141 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
143 /* Use push instructions to save outgoing args. */
144 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
146 /* Accumulate stack adjustments to prologue/epilogue. */
147 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
148 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
150 /* Put uninitialized locals into bss, not data.
151 Meaningful only on svr3. */
152 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
154 /* Use IEEE floating point comparisons. These handle correctly the cases
155 where the result of a comparison is unordered. Normally SIGFPE is
156 generated in such cases, in which case this isn't needed. */
157 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
159 /* Functions that return a floating point value may return that value
160 in the 387 FPU or in 386 integer registers. If set, this flag causes
161 the 387 to be used, which is compatible with most calling conventions. */
162 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
164 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
165 This mode wastes cache, but avoid missaligned data accesses and simplifies
166 address calculations. */
167 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
169 /* Disable generation of FP sin, cos and sqrt operations for 387.
170 This is because FreeBSD lacks these in the math-emulator-code */
171 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
173 /* Don't create frame pointers for leaf functions */
174 #define TARGET_OMIT_LEAF_FRAME_POINTER \
175 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
177 /* Debug GO_IF_LEGITIMATE_ADDRESS */
178 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
180 /* Debug FUNCTION_ARG macros */
181 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
183 /* 64bit Sledgehammer mode */
184 #define TARGET_64BIT (target_flags & MASK_64BIT)
186 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
187 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
188 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
189 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
190 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
191 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
192 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
194 #define CPUMASK (1 << ix86_cpu)
195 extern const int x86_use_leave
, x86_push_memory
, x86_zero_extend_with_and
;
196 extern const int x86_use_bit_test
, x86_cmove
, x86_deep_branch
;
197 extern const int x86_unroll_strlen
;
198 extern const int x86_double_with_add
, x86_partial_reg_stall
, x86_movx
;
199 extern const int x86_use_loop
, x86_use_fiop
, x86_use_mov0
;
200 extern const int x86_use_cltd
, x86_read_modify_write
;
201 extern const int x86_read_modify
, x86_split_long_moves
;
202 extern const int x86_promote_QImode
, x86_single_stringop
;
203 extern const int x86_himode_math
, x86_qimode_math
, x86_promote_qi_regs
;
204 extern const int x86_promote_hi_regs
, x86_integer_DFmode_moves
;
205 extern const int x86_add_esp_4
, x86_add_esp_8
, x86_sub_esp_4
, x86_sub_esp_8
;
206 extern const int x86_partial_reg_dependency
, x86_memory_mismatch_stall
;
208 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
209 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
210 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
211 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
212 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
213 /* For sane SSE instruction set generation we need fcomi instruction. It is
214 safe to enable all CMOVE instructions. */
215 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
216 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
217 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
218 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
219 #define TARGET_MOVX (x86_movx & CPUMASK)
220 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
221 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
222 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
223 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
224 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
225 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
226 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
227 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
228 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
229 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
230 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
231 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
232 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
233 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
234 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
235 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
236 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
237 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
238 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
239 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
240 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
242 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
244 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
245 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
247 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
249 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
250 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
251 #define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
252 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
254 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
256 #define TARGET_SWITCHES \
257 { { "80387", MASK_80387, N_("Use hardware fp") }, \
258 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
259 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
260 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
261 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
262 { "386", 0, N_("Same as -mcpu=i386") }, \
263 { "486", 0, N_("Same as -mcpu=i486") }, \
264 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
265 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
267 N_("Alternate calling convention") }, \
268 { "no-rtd", -MASK_RTD, \
269 N_("Use normal calling convention") }, \
270 { "align-double", MASK_ALIGN_DOUBLE, \
271 N_("Align some doubles on dword boundary") }, \
272 { "no-align-double", -MASK_ALIGN_DOUBLE, \
273 N_("Align doubles on word boundary") }, \
274 { "svr3-shlib", MASK_SVR3_SHLIB, \
275 N_("Uninitialized locals in .bss") }, \
276 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
277 N_("Uninitialized locals in .data") }, \
278 { "ieee-fp", MASK_IEEE_FP, \
279 N_("Use IEEE math for fp comparisons") }, \
280 { "no-ieee-fp", -MASK_IEEE_FP, \
281 N_("Do not use IEEE math for fp comparisons") }, \
282 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
283 N_("Return values of functions in FPU registers") }, \
284 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
285 N_("Do not return values of functions in FPU registers")}, \
286 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
287 N_("Do not generate sin, cos, sqrt for FPU") }, \
288 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
289 N_("Generate sin, cos, sqrt for FPU")}, \
290 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
291 N_("Omit the frame pointer in leaf functions") }, \
292 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
293 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
294 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
295 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
296 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
297 { "stack-arg-probe", MASK_STACK_PROBE, \
298 N_("Enable stack probing") }, \
299 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
300 { "windows", 0, 0 /* undocumented */ }, \
301 { "dll", 0, 0 /* undocumented */ }, \
302 { "intel-syntax", MASK_INTEL_SYNTAX, \
303 N_("Emit Intel syntax assembler opcodes") }, \
304 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
305 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
306 N_("Align destination of the string operations") }, \
307 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
308 N_("Do not align destination of the string operations") }, \
309 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
310 N_("Inline all known string operations") }, \
311 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
312 N_("Do not inline all known string operations") }, \
313 { "push-args", -MASK_NO_PUSH_ARGS, \
314 N_("Use push instructions to save outgoing arguments") }, \
315 { "no-push-args", MASK_NO_PUSH_ARGS, \
316 N_("Do not use push instructions to save outgoing arguments") }, \
317 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
318 N_("Use push instructions to save outgoing arguments") }, \
319 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
320 N_("Do not use push instructions to save outgoing arguments") }, \
321 { "mmx", MASK_MMX, N_("Support MMX builtins") }, \
322 { "no-mmx", -MASK_MMX, \
323 N_("Do not support MMX builtins") }, \
325 N_("Support MMX and SSE builtins and code generation") }, \
326 { "no-sse", -MASK_SSE, \
327 N_("Do not support MMX and SSE builtins and code generation") }, \
328 { "sse2", MASK_SSE2, \
329 N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
330 { "no-sse2", -MASK_SSE2, \
331 N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
332 { "mix-sse-i387", MASK_MIX_SSE_I387, \
333 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
334 { "nomix-sse-i387", -MASK_MIX_SSE_I387, \
335 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
336 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
337 N_("sizeof(long double) is 16.") }, \
338 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
339 N_("sizeof(long double) is 12.") }, \
340 { "64", MASK_64BIT, \
341 N_("Generate 64bit x86-64 code") }, \
342 { "32", -MASK_64BIT, \
343 N_("Generate 32bit i386 code") }, \
344 { "red-zone", -MASK_NO_RED_ZONE, \
345 N_("Use red-zone in the x86-64 code") }, \
346 { "no-red-zone", MASK_NO_RED_ZONE, \
347 N_("do not use red-zone in the x86-64 code") }, \
349 { "", TARGET_DEFAULT, 0 }}
351 #ifdef TARGET_64BIT_DEFAULT
352 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
354 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
357 /* Which processor to schedule for. The cpu attribute defines a list that
358 mirrors this list, so changes to i386.md must be made at the same time. */
362 PROCESSOR_I386
, /* 80386 */
363 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
365 PROCESSOR_PENTIUMPRO
,
372 extern enum processor_type ix86_cpu
;
374 extern int ix86_arch
;
376 /* This macro is similar to `TARGET_SWITCHES' but defines names of
377 command options that have values. Its definition is an
378 initializer with a subgrouping for each command option.
380 Each subgrouping contains a string constant, that defines the
381 fixed part of the option name, and the address of a variable. The
382 variable, type `char *', is set to the variable part of the given
383 option if the fixed part matches. The actual option name is made
384 by appending `-m' to the specified name. */
385 #define TARGET_OPTIONS \
386 { { "cpu=", &ix86_cpu_string, \
387 N_("Schedule code for given CPU")}, \
388 { "arch=", &ix86_arch_string, \
389 N_("Generate code for given CPU")}, \
390 { "regparm=", &ix86_regparm_string, \
391 N_("Number of registers used to pass integer arguments") }, \
392 { "align-loops=", &ix86_align_loops_string, \
393 N_("Loop code aligned to this power of 2") }, \
394 { "align-jumps=", &ix86_align_jumps_string, \
395 N_("Jump targets are aligned to this power of 2") }, \
396 { "align-functions=", &ix86_align_funcs_string, \
397 N_("Function starts are aligned to this power of 2") }, \
398 { "preferred-stack-boundary=", \
399 &ix86_preferred_stack_boundary_string, \
400 N_("Attempt to keep stack aligned to this power of 2") }, \
401 { "branch-cost=", &ix86_branch_cost_string, \
402 N_("Branches are this expensive (1-5, arbitrary units)") }, \
403 { "cmodel=", &ix86_cmodel_string, \
404 N_("Use given x86-64 code model") }, \
408 /* Sometimes certain combinations of command options do not make
409 sense on a particular target machine. You can define a macro
410 `OVERRIDE_OPTIONS' to take account of this. This macro, if
411 defined, is executed once just after all the command options have
414 Don't use this macro to turn on various extra optimizations for
415 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
417 #define OVERRIDE_OPTIONS override_options ()
419 /* These are meant to be redefined in the host dependent files */
420 #define SUBTARGET_SWITCHES
421 #define SUBTARGET_OPTIONS
423 /* Define this to change the optimizations performed by default. */
424 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
426 /* Specs for the compiler proper */
429 #define CC1_CPU_SPEC "\
432 %n`-mpentium' is deprecated. Use `-march' or `-mcpu' instead.\n} \
434 %n`-mpentium' is deprecated. Use `-march' or `-mcpu' instead.\n} \
435 %{mpentium:-mcpu=pentium \
436 %n`-mpentium' is deprecated. Use `-march' or `-mcpu' instead.\n} \
437 %{mpentiumpro:-mcpu=pentiumpro \
438 %n`-mpentiumpro' is deprecated. Use `-march' or `-mcpu' instead.\n}}"
441 #ifndef CPP_CPU_DEFAULT_SPEC
442 #if TARGET_CPU_DEFAULT == 1
443 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
445 #if TARGET_CPU_DEFAULT == 2
446 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
448 #if TARGET_CPU_DEFAULT == 3
449 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
451 #if TARGET_CPU_DEFAULT == 4
452 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
454 #if TARGET_CPU_DEFAULT == 5
455 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
457 #if TARGET_CPU_DEFAULT == 6
458 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
460 #ifndef CPP_CPU_DEFAULT_SPEC
461 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
463 #endif /* CPP_CPU_DEFAULT_SPEC */
466 #define CPP_CPU_SPEC "\
467 -Acpu=i386 -Amachine=i386 \
468 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 -D__i386__ \
469 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
470 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
471 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
472 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
473 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
474 -D__pentiumpro -D__pentiumpro__ \
475 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
476 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
477 %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
478 %{mpentium4=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
479 %{m386|mcpu=i386:-D__tune_i386__ }\
480 %{m486|mcpu=i486:-D__tune_i486__ }\
481 %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_i586__ -D__tune_pentium__ }\
482 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_i686__ -D__tune_pentiumpro__ }\
483 %{mcpu=k6:-D__tune_k6__ }\
484 %{mcpu=athlon:-D__tune_athlon__ }\
485 %{mcpu=pentium4:-D__tune_pentium4__ }\
486 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
490 #define CC1_SPEC "%(cc1_cpu) "
493 /* This macro defines names of additional specifications to put in the
494 specs that can be used in various specifications like CC1_SPEC. Its
495 definition is an initializer with a subgrouping for each command option.
497 Each subgrouping contains a string constant, that defines the
498 specification name, and a string constant that used by the GNU CC driver
501 Do not define this macro if it does not need to do anything. */
503 #ifndef SUBTARGET_EXTRA_SPECS
504 #define SUBTARGET_EXTRA_SPECS
507 #define EXTRA_SPECS \
508 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
509 { "cpp_cpu", CPP_CPU_SPEC }, \
510 { "cc1_cpu", CC1_CPU_SPEC }, \
511 SUBTARGET_EXTRA_SPECS
513 /* target machine storage layout */
515 /* Define for XFmode or TFmode extended real floating point support.
516 This will automatically cause REAL_ARITHMETIC to be defined.
518 The XFmode is specified by i386 ABI, while TFmode may be faster
519 due to alignment and simplifications in the address calculations.
521 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
522 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
524 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
526 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
528 /* Tell real.c that this is the 80-bit Intel extended float format
529 packaged in a 128-bit or 96bit entity. */
530 #define INTEL_EXTENDED_IEEE_FORMAT
533 #define SHORT_TYPE_SIZE 16
534 #define INT_TYPE_SIZE 32
535 #define FLOAT_TYPE_SIZE 32
536 #define LONG_TYPE_SIZE BITS_PER_WORD
537 #define MAX_WCHAR_TYPE_SIZE 32
538 #define MAX_LONG_TYPE_SIZE 64
539 #define DOUBLE_TYPE_SIZE 64
540 #define LONG_LONG_TYPE_SIZE 64
542 /* Define if you don't want extended real, but do want to use the
543 software floating point emulator for REAL_ARITHMETIC and
544 decimal <-> binary conversion. */
545 /* #define REAL_ARITHMETIC */
547 /* Define this if most significant byte of a word is the lowest numbered. */
548 /* That is true on the 80386. */
550 #define BITS_BIG_ENDIAN 0
552 /* Define this if most significant byte of a word is the lowest numbered. */
553 /* That is not true on the 80386. */
554 #define BYTES_BIG_ENDIAN 0
556 /* Define this if most significant word of a multiword number is the lowest
558 /* Not true for 80386 */
559 #define WORDS_BIG_ENDIAN 0
561 /* number of bits in an addressable storage unit */
562 #define BITS_PER_UNIT 8
564 /* Width in bits of a "word", which is the contents of a machine register.
565 Note that this is not necessarily the width of data type `int';
566 if using 16-bit ints on a 80386, this would still be 32.
567 But on a machine with 16-bit registers, this would be 16. */
568 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
569 #define MAX_BITS_PER_WORD 64
571 /* Width of a word, in units (bytes). */
572 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
573 #define MIN_UNITS_PER_WORD 4
575 /* Width in bits of a pointer.
576 See also the macro `Pmode' defined below. */
577 #define POINTER_SIZE BITS_PER_WORD
579 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
580 #define PARM_BOUNDARY BITS_PER_WORD
582 /* Boundary (in *bits*) on which stack pointer should be aligned. */
583 #define STACK_BOUNDARY BITS_PER_WORD
585 /* Boundary (in *bits*) on which the stack pointer preferrs to be
586 aligned; the compiler cannot rely on having this alignment. */
587 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
589 /* Allocation boundary for the code of a function. */
590 #define FUNCTION_BOUNDARY \
591 (1 << ((ix86_align_funcs >= 0 ? ix86_align_funcs : -ix86_align_funcs) + 3))
593 /* Alignment of field after `int : 0' in a structure. */
595 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
597 /* Minimum size in bits of the largest boundary to which any
598 and all fundamental data types supported by the hardware
599 might need to be aligned. No data type wants to be aligned
602 Pentium+ preferrs DFmode values to be alignmed to 64 bit boundary
603 and Pentium Pro XFmode values at 128 bit boundaries. */
605 #define BIGGEST_ALIGNMENT 128
607 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
608 #define ALIGN_MODE_128(MODE) \
609 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
610 || (MODE) == V4SFmode || (MODE) == V4SImode)
612 /* The published ABIs say that doubles should be aligned on word
613 boundaries, so lower the aligment for structure fields unless
614 -malign-double is set. */
615 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
616 constant. Use the smaller value in that context. */
617 #ifndef IN_TARGET_LIBS
618 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
620 #define BIGGEST_FIELD_ALIGNMENT 32
623 /* If defined, a C expression to compute the alignment given to a
624 constant that is being placed in memory. EXP is the constant
625 and ALIGN is the alignment that the object would ordinarily have.
626 The value of this macro is used instead of that alignment to align
629 If this macro is not defined, then ALIGN is used.
631 The typical use of this macro is to increase alignment for string
632 constants to be word aligned so that `strcpy' calls that copy
633 constants can be done inline. */
635 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
637 /* If defined, a C expression to compute the alignment for a static
638 variable. TYPE is the data type, and ALIGN is the alignment that
639 the object would ordinarily have. The value of this macro is used
640 instead of that alignment to align the object.
642 If this macro is not defined, then ALIGN is used.
644 One use of this macro is to increase alignment of medium-size
645 data to make it all fit in fewer cache lines. Another is to
646 cause character arrays to be word-aligned so that `strcpy' calls
647 that copy constants to character arrays can be done inline. */
649 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
651 /* If defined, a C expression to compute the alignment for a local
652 variable. TYPE is the data type, and ALIGN is the alignment that
653 the object would ordinarily have. The value of this macro is used
654 instead of that alignment to align the object.
656 If this macro is not defined, then ALIGN is used.
658 One use of this macro is to increase alignment of medium-size
659 data to make it all fit in fewer cache lines. */
661 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
663 /* Set this non-zero if move instructions will actually fail to work
664 when given unaligned data. */
665 #define STRICT_ALIGNMENT 0
667 /* If bit field type is int, don't let it cross an int,
668 and give entire struct the alignment of an int. */
669 /* Required on the 386 since it doesn't have bitfield insns. */
670 #define PCC_BITFIELD_TYPE_MATTERS 1
672 /* Align loop starts for optimal branching. */
673 #define LOOP_ALIGN(LABEL) \
674 (ix86_align_loops < 0 ? -ix86_align_loops : ix86_align_loops)
675 #define LOOP_ALIGN_MAX_SKIP \
676 (ix86_align_loops < -3 ? (1<<(-ix86_align_loops-1))-1 : 0)
678 /* This is how to align an instruction for optimal branching. */
679 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
680 (ix86_align_jumps < 0 ? -ix86_align_jumps : ix86_align_jumps)
681 #define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP \
682 (ix86_align_jumps < -3 ? (1<<(-ix86_align_jumps-1))-1 : 0)
684 /* Standard register usage. */
686 /* This processor has special stack-like registers. See reg-stack.c
690 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
691 || mode==XFmode || mode==TFmode)
693 /* Number of actual hardware registers.
694 The hardware registers are assigned numbers for the compiler
695 from 0 to just below FIRST_PSEUDO_REGISTER.
696 All registers that the compiler knows about must be given numbers,
697 even those that are not normally considered general registers.
699 In the 80386 we give the 8 general purpose registers the numbers 0-7.
700 We number the floating point registers 8-15.
701 Note that registers 0-7 can be accessed as a short or int,
702 while only 0-3 may be used with byte `mov' instructions.
704 Reg 16 does not correspond to any hardware register, but instead
705 appears in the RTL as an argument pointer prior to reload, and is
706 eliminated during reloading in favor of either the stack or frame
709 #define FIRST_PSEUDO_REGISTER 53
711 /* Number of hardware registers that go into the DWARF-2 unwind info.
712 If not defined, equals FIRST_PSEUDO_REGISTER. */
714 #define DWARF_FRAME_REGISTERS 17
716 /* 1 for registers that have pervasive standard uses
717 and are not available for the register allocator.
718 On the 80386, the stack pointer is such, as is the arg pointer.
720 The value is an mask - bit 1 is set for fixed registers
721 for 32bit target, while 2 is set for fixed registers for 64bit.
722 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
724 #define FIXED_REGISTERS \
725 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
726 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
727 /*arg,flags,fpsr,dir,frame*/ \
729 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
730 0, 0, 0, 0, 0, 0, 0, 0, \
731 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
732 0, 0, 0, 0, 0, 0, 0, 0, \
733 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
734 1, 1, 1, 1, 1, 1, 1, 1, \
735 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
736 1, 1, 1, 1, 1, 1, 1, 1}
739 /* 1 for registers not available across function calls.
740 These must include the FIXED_REGISTERS and also any
741 registers that can be used without being saved.
742 The latter must include the registers where values are returned
743 and the register where structure-value addresses are passed.
744 Aside from that, you can include as many other registers as you like.
746 The value is an mask - bit 1 is set for call used
747 for 32bit target, while 2 is set for call used for 64bit.
748 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
750 #define CALL_USED_REGISTERS \
751 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
752 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
753 /*arg,flags,fpsr,dir,frame*/ \
755 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
756 3, 3, 3, 3, 3, 3, 3, 3, \
757 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
758 3, 3, 3, 3, 3, 3, 3, 3, \
759 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
760 3, 3, 3, 3, 1, 1, 1, 1, \
761 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
762 3, 3, 3, 3, 3, 3, 3, 3} \
764 /* Order in which to allocate registers. Each register must be
765 listed once, even those in FIXED_REGISTERS. List frame pointer
766 late and fixed registers last. Note that, in general, we prefer
767 registers listed in CALL_USED_REGISTERS, keeping the others
768 available for storage of persistent values.
770 Three different versions of REG_ALLOC_ORDER have been tried:
772 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
773 but slower code on simple functions returning values in eax.
775 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
776 perl 4.036 due to not being able to create a DImode register (to hold a 2
779 If the order is eax, edx, ecx, ... it produces better code for simple
780 functions, and a slightly slower compiler. Users complained about the code
781 generated by allocating edx first, so restore the 'natural' order of things. */
783 #define REG_ALLOC_ORDER \
786 /* bx,si,di,bp,sp,*/ \
790 /*r12,r15,r14,r13*/ \
792 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
793 21, 22, 23, 24, 25, 26, 27, 28, \
794 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
795 45, 46, 47, 48, 49, 50, 51, 52, \
796 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
797 8, 9, 10, 11, 12, 13, 14, 15, \
798 /*,arg,cc,fpsr,dir,frame*/ \
800 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
801 29, 30, 31, 32, 33, 34, 35, 36 }
803 /* Macro to conditionally modify fixed_regs/call_used_regs. */
804 #define CONDITIONAL_REGISTER_USAGE \
807 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
809 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
810 call_used_regs[i] = (call_used_regs[i] \
811 & (TARGET_64BIT ? 2 : 1)) != 0; \
815 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
816 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
821 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
822 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
823 fixed_regs[i] = call_used_regs[i] = 1; \
828 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
829 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
830 fixed_regs[i] = call_used_regs[i] = 1; \
832 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
836 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
837 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
838 if (TEST_HARD_REG_BIT (x, i)) \
839 fixed_regs[i] = call_used_regs[i] = 1; \
843 /* Return number of consecutive hard regs needed starting at reg REGNO
844 to hold something of mode MODE.
845 This is ordinarily the length in words of a value of mode MODE
846 but can be less for certain modes in special long registers.
848 Actually there are no two word move instructions for consecutive
849 registers. And only registers 0-3 may have mov byte instructions
853 #define HARD_REGNO_NREGS(REGNO, MODE) \
854 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) ? 1 \
857 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
859 #define VALID_SSE_REG_MODE(MODE) \
860 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
861 || (MODE) == SFmode || (TARGET_SSE2 && (MODE) == DFmode))
863 #define VALID_MMX_REG_MODE(MODE) \
864 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
865 || (MODE) == V2SImode || (MODE) == SImode)
867 #define VECTOR_MODE_SUPPORTED_P(MODE) \
868 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
869 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 : 0)
871 #define VALID_FP_MODE_P(mode) \
872 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
873 || (!TARGET_64BIT && (mode) == XFmode) \
874 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
875 || (!TARGET_64BIT && (mode) == XCmode))
877 #define VALID_INT_MODE_P(mode) \
878 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
879 || (mode) == DImode \
880 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
881 || (mode) == CDImode)
883 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
885 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
886 ix86_hard_regno_mode_ok (REGNO, MODE)
888 /* Value is 1 if it is a good idea to tie two pseudo registers
889 when one has mode MODE1 and one has mode MODE2.
890 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
891 for any hard reg, then this must be 0 for correct output. */
893 #define MODES_TIEABLE_P(MODE1, MODE2) \
894 ((MODE1) == (MODE2) \
895 || (((MODE1) == HImode || (MODE1) == SImode \
896 || ((MODE1) == QImode \
897 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
898 || ((MODE1) == DImode && TARGET_64BIT)) \
899 && ((MODE2) == HImode || (MODE2) == SImode \
900 || ((MODE1) == QImode \
901 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
902 || ((MODE2) == DImode && TARGET_64BIT))))
905 /* Specify the modes required to caller save a given hard regno.
906 We do this on i386 to prevent flags from being saved at all.
908 Kill any attempts to combine saving of modes. */
910 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
911 (CC_REGNO_P (REGNO) ? VOIDmode \
912 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
913 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
914 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
915 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
917 /* Specify the registers used for certain standard purposes.
918 The values of these macros are register numbers. */
920 /* on the 386 the pc register is %eip, and is not usable as a general
921 register. The ordinary mov instructions won't work */
922 /* #define PC_REGNUM */
924 /* Register to use for pushing function arguments. */
925 #define STACK_POINTER_REGNUM 7
927 /* Base register for access to local variables of the function. */
928 #define HARD_FRAME_POINTER_REGNUM 6
930 /* Base register for access to local variables of the function. */
931 #define FRAME_POINTER_REGNUM 20
933 /* First floating point reg */
934 #define FIRST_FLOAT_REG 8
936 /* First & last stack-like regs */
937 #define FIRST_STACK_REG FIRST_FLOAT_REG
938 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
942 #define DIRFLAG_REG 19
944 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
945 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
947 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
948 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
950 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
951 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
953 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
954 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
956 /* Value should be nonzero if functions must have frame pointers.
957 Zero means the frame pointer need not be set up (and parms
958 may be accessed via the stack pointer) in functions that seem suitable.
959 This is computed in `reload', in reload1.c. */
960 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
962 /* Override this in other tm.h files to cope with various OS losage
963 requiring a frame pointer. */
964 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
965 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
968 /* Make sure we can access arbitrary call frames. */
969 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
971 /* Base register for access to arguments of the function. */
972 #define ARG_POINTER_REGNUM 16
974 /* Register in which static-chain is passed to a function.
975 We do use ECX as static chain register for 32 bit ABI. On the
976 64bit ABI, ECX is an argument register, so we use R10 instead. */
977 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
979 /* Register to hold the addressing base for position independent
980 code access to data items.
981 We don't use PIC pointer for 64bit mode. Define the regnum to
982 dummy value to prevent gcc from pesimizing code dealing with EBX.
984 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
986 /* Register in which address to store a structure value
987 arrives in the function. On the 386, the prologue
988 copies this from the stack to register %eax. */
989 #define STRUCT_VALUE_INCOMING 0
991 /* Place in which caller passes the structure value address.
992 0 means push the value on the stack like an argument. */
993 #define STRUCT_VALUE 0
995 /* A C expression which can inhibit the returning of certain function
996 values in registers, based on the type of value. A nonzero value
997 says to return the function value in memory, just as large
998 structures are always returned. Here TYPE will be a C expression
999 of type `tree', representing the data type of the value.
1001 Note that values of mode `BLKmode' must be explicitly handled by
1002 this macro. Also, the option `-fpcc-struct-return' takes effect
1003 regardless of this macro. On most systems, it is possible to
1004 leave the macro undefined; this causes a default definition to be
1005 used, whose value is the constant 1 for `BLKmode' values, and 0
1008 Do not use this macro to indicate that structures and unions
1009 should always be returned in memory. You should instead use
1010 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1012 #define RETURN_IN_MEMORY(TYPE) \
1013 ((TYPE_MODE (TYPE) == BLKmode) \
1014 || (VECTOR_MODE_P (TYPE_MODE (TYPE)) && int_size_in_bytes (TYPE) == 8)\
1015 || (int_size_in_bytes (TYPE) > 12 && TYPE_MODE (TYPE) != TImode \
1016 && TYPE_MODE (TYPE) != TFmode && ! VECTOR_MODE_P (TYPE_MODE (TYPE))))
1019 /* Define the classes of registers for register constraints in the
1020 machine description. Also define ranges of constants.
1022 One of the classes must always be named ALL_REGS and include all hard regs.
1023 If there is more than one class, another class must be named NO_REGS
1024 and contain no registers.
1026 The name GENERAL_REGS must be the name of a class (or an alias for
1027 another name such as ALL_REGS). This is the class of registers
1028 that is allowed by "g" or "r" in a register constraint.
1029 Also, registers outside this class are allocated only when
1030 instructions express preferences for them.
1032 The classes must be numbered in nondecreasing order; that is,
1033 a larger-numbered class must never be contained completely
1034 in a smaller-numbered class.
1036 For any two classes, it is very desirable that there be another
1037 class that represents their union.
1039 It might seem that class BREG is unnecessary, since no useful 386
1040 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1041 and the "b" register constraint is useful in asms for syscalls.
1043 The flags and fpsr registers are in no class. */
1048 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
1049 AD_REGS
, /* %eax/%edx for DImode */
1050 Q_REGS
, /* %eax %ebx %ecx %edx */
1051 NON_Q_REGS
, /* %esi %edi %ebp %esp */
1052 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1053 LEGACY_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1054 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1055 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
1065 ALL_REGS
, LIM_REG_CLASSES
1068 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1070 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1071 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1072 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1073 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1074 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1075 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1077 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1079 /* Give names of register classes as strings for dump file. */
1081 #define REG_CLASS_NAMES \
1083 "AREG", "DREG", "CREG", "BREG", \
1086 "Q_REGS", "NON_Q_REGS", \
1090 "FP_TOP_REG", "FP_SECOND_REG", \
1094 "FP_TOP_SSE_REGS", \
1095 "FP_SECOND_SSE_REGS", \
1099 "FLOAT_INT_SSE_REGS", \
1102 /* Define which registers fit in which classes.
1103 This is an initializer for a vector of HARD_REG_SET
1104 of length N_REG_CLASSES. */
1106 #define REG_CLASS_CONTENTS \
1108 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1109 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1110 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1111 { 0x03, 0x0 }, /* AD_REGS */ \
1112 { 0x0f, 0x0 }, /* Q_REGS */ \
1113 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1114 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1115 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1116 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1117 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1118 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1119 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1120 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1121 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1122 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1123 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1124 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1125 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1126 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1127 { 0xffffffff,0x1fffff } \
1130 /* The same information, inverted:
1131 Return the class number of the smallest class containing
1132 reg number REGNO. This could be a conditional expression
1133 or could index an array. */
1135 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1137 /* When defined, the compiler allows registers explicitly used in the
1138 rtl to be used as spill registers but prevents the compiler from
1139 extending the lifetime of these registers. */
1141 #define SMALL_REGISTER_CLASSES 1
1143 #define QI_REG_P(X) \
1144 (REG_P (X) && REGNO (X) < 4)
1146 #define GENERAL_REGNO_P(n) \
1147 ((n) < 8 || REX_INT_REGNO_P (n))
1149 #define GENERAL_REG_P(X) \
1150 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1152 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1154 #define NON_QI_REG_P(X) \
1155 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1157 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1158 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1160 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1161 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1162 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1163 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1165 #define SSE_REGNO_P(n) \
1166 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1167 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1169 #define SSE_REGNO(n) \
1170 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1171 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1173 #define SSE_FLOAT_MODE_P(m) \
1174 ((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1176 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1177 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1179 #define STACK_REG_P(xop) (REG_P (xop) && \
1180 REGNO (xop) >= FIRST_STACK_REG && \
1181 REGNO (xop) <= LAST_STACK_REG)
1183 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1185 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1187 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1188 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1190 /* Indicate whether hard register numbered REG_NO should be converted
1192 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1193 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1195 /* The class value for index registers, and the one for base regs. */
1197 #define INDEX_REG_CLASS INDEX_REGS
1198 #define BASE_REG_CLASS GENERAL_REGS
1200 /* Get reg_class from a letter such as appears in the machine description. */
1202 #define REG_CLASS_FROM_LETTER(C) \
1203 ((C) == 'r' ? GENERAL_REGS : \
1204 (C) == 'R' ? LEGACY_REGS : \
1205 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1206 (C) == 'Q' ? Q_REGS : \
1207 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1210 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1213 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1216 (C) == 'a' ? AREG : \
1217 (C) == 'b' ? BREG : \
1218 (C) == 'c' ? CREG : \
1219 (C) == 'd' ? DREG : \
1220 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1221 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1222 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1223 (C) == 'A' ? AD_REGS : \
1224 (C) == 'D' ? DIREG : \
1225 (C) == 'S' ? SIREG : NO_REGS)
1227 /* The letters I, J, K, L and M in a register constraint string
1228 can be used to stand for particular ranges of immediate operands.
1229 This macro defines what the ranges are.
1230 C is the letter, and VALUE is a constant value.
1231 Return 1 if VALUE is in the range specified by C.
1233 I is for non-DImode shifts.
1234 J is for DImode shifts.
1235 K is for signed imm8 operands.
1236 L is for andsi as zero-extending move.
1237 M is for shifts that can be executed by the "lea" opcode.
1238 N is for immedaite operands for out/in instructions (0-255)
1241 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1242 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1243 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1244 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1245 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1246 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1247 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1250 /* Similar, but for floating constants, and defining letters G and H.
1251 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1252 TARGET_387 isn't set, because the stack register converter may need to
1253 load 0.0 into the function value register. */
1255 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1256 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1257 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1259 /* A C expression that defines the optional machine-dependent
1260 constraint letters that can be used to segregate specific types of
1261 operands, usually memory references, for the target machine. Any
1262 letter that is not elsewhere defined and not matched by
1263 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1266 If it is required for a particular target machine, it should
1267 return 1 if VALUE corresponds to the operand type represented by
1268 the constraint letter C. If C is not defined as an extra
1269 constraint, the value returned should be 0 regardless of VALUE. */
1271 #define EXTRA_CONSTRAINT(VALUE, C) \
1272 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1273 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1276 /* Place additional restrictions on the register class to use when it
1277 is necessary to be able to hold a value of mode MODE in a reload
1278 register for which class CLASS would ordinarily be used. */
1280 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1281 ((MODE) == QImode && !TARGET_64BIT \
1282 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1285 /* Given an rtx X being reloaded into a reg required to be
1286 in class CLASS, return the class of reg to actually use.
1287 In general this is just CLASS; but on some machines
1288 in some cases it is preferable to use a more restrictive class.
1289 On the 80386 series, we prevent floating constants from being
1290 reloaded into floating registers (since no move-insn can do that)
1291 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1293 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1294 QImode must go into class Q_REGS.
1295 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1296 movdf to do mem-to-mem moves through integer regs. */
1298 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1299 ix86_preferred_reload_class (X, CLASS)
1301 /* If we are copying between general and FP registers, we need a memory
1302 location. The same is true for SSE and MMX registers. */
1303 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1304 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1306 /* QImode spills from non-QI registers need a scratch. This does not
1307 happen often -- the only example so far requires an uninitialized
1310 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1311 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1314 /* Return the maximum number of consecutive registers
1315 needed to represent mode MODE in a register of class CLASS. */
1316 /* On the 80386, this is the size of MODE in words,
1317 except in the FP regs, where a single reg is always enough. */
1318 #define CLASS_MAX_NREGS(CLASS, MODE) \
1319 (FLOAT_CLASS_P (CLASS) || SSE_CLASS_P (CLASS) || MMX_CLASS_P (CLASS) \
1321 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1323 /* A C expression whose value is nonzero if pseudos that have been
1324 assigned to registers of class CLASS would likely be spilled
1325 because registers of CLASS are needed for spill registers.
1327 The default value of this macro returns 1 if CLASS has exactly one
1328 register and zero otherwise. On most machines, this default
1329 should be used. Only define this macro to some other expression
1330 if pseudo allocated by `local-alloc.c' end up in memory because
1331 their hard registers were needed for spill registers. If this
1332 macro returns nonzero for those classes, those pseudos will only
1333 be allocated by `global.c', which knows how to reallocate the
1334 pseudo to another register. If there would not be another
1335 register available for reallocation, you should not change the
1336 definition of this macro since the only effect of such a
1337 definition would be to slow down register allocation. */
1339 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1340 (((CLASS) == AREG) \
1341 || ((CLASS) == DREG) \
1342 || ((CLASS) == CREG) \
1343 || ((CLASS) == BREG) \
1344 || ((CLASS) == AD_REGS) \
1345 || ((CLASS) == SIREG) \
1346 || ((CLASS) == DIREG))
1348 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1349 to automatically clobber for all asms.
1351 We do this in the new i386 backend to maintain source compatibility
1352 with the old cc0-based compiler. */
1354 #define MD_ASM_CLOBBERS(CLOBBERS) \
1356 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1357 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1358 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1361 /* Stack layout; function entry, exit and calling. */
1363 /* Define this if pushing a word on the stack
1364 makes the stack pointer a smaller address. */
1365 #define STACK_GROWS_DOWNWARD
1367 /* Define this if the nominal address of the stack frame
1368 is at the high-address end of the local variables;
1369 that is, each additional local variable allocated
1370 goes at a more negative offset in the frame. */
1371 #define FRAME_GROWS_DOWNWARD
1373 /* Offset within stack frame to start allocating local variables at.
1374 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1375 first local allocated. Otherwise, it is the offset to the BEGINNING
1376 of the first local allocated. */
1377 #define STARTING_FRAME_OFFSET 0
1379 /* If we generate an insn to push BYTES bytes,
1380 this says how many the stack pointer really advances by.
1381 On 386 pushw decrements by exactly 2 no matter what the position was.
1382 On the 386 there is no pushb; we use pushw instead, and this
1383 has the effect of rounding up to 2.
1385 For 64bit ABI we round up to 8 bytes.
1388 #define PUSH_ROUNDING(BYTES) \
1390 ? (((BYTES) + 7) & (-8)) \
1391 : (((BYTES) + 1) & (-2)))
1393 /* If defined, the maximum amount of space required for outgoing arguments will
1394 be computed and placed into the variable
1395 `current_function_outgoing_args_size'. No space will be pushed onto the
1396 stack for each call; instead, the function prologue should increase the stack
1397 frame size by this amount. */
1399 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1401 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1402 instructions to pass outgoing arguments. */
1404 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1406 /* Offset of first parameter from the argument pointer register value. */
1407 #define FIRST_PARM_OFFSET(FNDECL) 0
1409 /* Define this macro if functions should assume that stack space has been
1410 allocated for arguments even when their values are passed in registers.
1412 The value of this macro is the size, in bytes, of the area reserved for
1413 arguments passed in registers for the function represented by FNDECL.
1415 This space can be allocated by the caller, or be a part of the
1416 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1418 #define REG_PARM_STACK_SPACE(FNDECL) 0
1420 /* Define as a C expression that evaluates to nonzero if we do not know how
1421 to pass TYPE solely in registers. The file expr.h defines a
1422 definition that is usually appropriate, refer to expr.h for additional
1423 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1424 computed in the stack and then loaded into a register. */
1425 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1427 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1428 || TREE_ADDRESSABLE (TYPE) \
1429 || ((MODE) == TImode) \
1430 || ((MODE) == BLKmode \
1431 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1432 && 0 == (int_size_in_bytes (TYPE) \
1433 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1434 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1435 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1437 /* Value is the number of bytes of arguments automatically
1438 popped when returning from a subroutine call.
1439 FUNDECL is the declaration node of the function (as a tree),
1440 FUNTYPE is the data type of the function (as a tree),
1441 or for a library call it is an identifier node for the subroutine name.
1442 SIZE is the number of bytes of arguments passed on the stack.
1444 On the 80386, the RTD insn may be used to pop them if the number
1445 of args is fixed, but if the number is variable then the caller
1446 must pop them all. RTD can't be used for library calls now
1447 because the library is compiled with the Unix compiler.
1448 Use of RTD is a selectable option, since it is incompatible with
1449 standard Unix calling sequences. If the option is not selected,
1450 the caller must always pop the args.
1452 The attribute stdcall is equivalent to RTD on a per module basis. */
1454 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1455 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1457 /* Define how to find the value returned by a function.
1458 VALTYPE is the data type of the value (as a tree).
1459 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1460 otherwise, FUNC is 0. */
1461 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1462 gen_rtx_REG (TYPE_MODE (VALTYPE), \
1463 VALUE_REGNO (TYPE_MODE (VALTYPE)))
1465 /* Define how to find the value returned by a library function
1466 assuming the value has mode MODE. */
1468 #define LIBCALL_VALUE(MODE) \
1469 gen_rtx_REG (MODE, VALUE_REGNO (MODE))
1471 /* Define the size of the result block used for communication between
1472 untyped_call and untyped_return. The block contains a DImode value
1473 followed by the block used by fnsave and frstor. */
1475 #define APPLY_RESULT_SIZE (8+108)
1477 /* 1 if N is a possible register number for function argument passing. */
1478 #define FUNCTION_ARG_REGNO_P(N) ((N) < REGPARM_MAX)
1480 /* Define a data type for recording info about an argument list
1481 during the scan of that argument list. This data type should
1482 hold all necessary information about the function itself
1483 and about the args processed so far, enough to enable macros
1484 such as FUNCTION_ARG to determine where the next arg should go. */
1486 typedef struct ix86_args
{
1487 int words
; /* # words passed so far */
1488 int nregs
; /* # registers available for passing */
1489 int regno
; /* next available register number */
1490 int sse_words
; /* # sse words passed so far */
1491 int sse_nregs
; /* # sse registers available for passing */
1492 int sse_regno
; /* next available sse register number */
1495 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1496 for a call to a function whose data type is FNTYPE.
1497 For a library call, FNTYPE is 0. */
1499 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1500 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1502 /* Update the data in CUM to advance over an argument
1503 of mode MODE and data type TYPE.
1504 (TYPE is null for libcalls where that information may not be available.) */
1506 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1507 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1509 /* Define where to put the arguments to a function.
1510 Value is zero to push the argument on the stack,
1511 or a hard register in which to store the argument.
1513 MODE is the argument's machine mode.
1514 TYPE is the data type of the argument (as a tree).
1515 This is null for libcalls where that information may
1517 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1518 the preceding args and about the function being called.
1519 NAMED is nonzero if this argument is a named parameter
1520 (otherwise it is an extra parameter matching an ellipsis). */
1522 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1523 (function_arg (&CUM, MODE, TYPE, NAMED))
1525 /* For an arg passed partly in registers and partly in memory,
1526 this is the number of registers used.
1527 For args passed entirely in registers or entirely in memory, zero. */
1529 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1531 /* If PIC, we cannot make sibling calls to global functions
1532 because the PLT requires %ebx live.
1533 If we are returning floats on the register stack, we cannot make
1534 sibling calls to functions that return floats. (The stack adjust
1535 instruction will wind up after the sibcall jump, and not be executed.) */
1536 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1538 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1539 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1540 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1541 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1543 /* This macro is invoked at the end of compilation. It is used here to
1544 output code for -fpic that will load the return address into %ebx. */
1547 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1549 /* Output assembler code to FILE to increment profiler label # LABELNO
1550 for profiling a function entry. */
1552 #define FUNCTION_PROFILER(FILE, LABELNO) \
1556 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1557 LPREFIX, (LABELNO)); \
1558 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1562 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1563 fprintf (FILE, "\tcall\t_mcount\n"); \
1568 /* There are three profiling modes for basic blocks available.
1569 The modes are selected at compile time by using the options
1570 -a or -ax of the gnu compiler.
1571 The variable `profile_block_flag' will be set according to the
1574 profile_block_flag == 0, no option used:
1578 profile_block_flag == 1, -a option used.
1580 Count frequency of execution of every basic block.
1582 profile_block_flag == 2, -ax option used.
1584 Generate code to allow several different profiling modes at run time.
1585 Available modes are:
1586 Produce a trace of all basic blocks.
1587 Count frequency of jump instructions executed.
1588 In every mode it is possible to start profiling upon entering
1589 certain functions and to disable profiling of some other functions.
1591 The result of basic-block profiling will be written to a file `bb.out'.
1592 If the -ax option is used parameters for the profiling will be read
1597 /* The following macro shall output assembler code to FILE
1598 to initialize basic-block profiling. */
1600 #undef FUNCTION_BLOCK_PROFILER
1601 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1602 ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL)
1604 /* The following macro shall output assembler code to FILE
1605 to increment a counter associated with basic block number BLOCKNO. */
1607 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1608 ix86_output_block_profiler (FILE, BLOCKNO)
1610 /* The following macro shall output rtl for the epilogue
1611 to indicate a return from function during basic-block profiling.
1613 If profiling_block_flag == 2:
1615 Output assembler code to call function `__bb_trace_ret'.
1617 Note that function `__bb_trace_ret' must not change the
1618 machine state, especially the flag register. To grant
1619 this, you must output code to save and restore registers
1620 either in this macro or in the macros MACHINE_STATE_SAVE
1621 and MACHINE_STATE_RESTORE. The last two macros will be
1622 used in the function `__bb_trace_ret', so you must make
1623 sure that the function prologue does not change any
1624 register prior to saving it with MACHINE_STATE_SAVE.
1626 else if profiling_block_flag != 0:
1628 The macro will not be used, so it need not distinguish
1632 #define FUNCTION_BLOCK_PROFILER_EXIT \
1633 emit_call_insn (gen_call (gen_rtx_MEM (QImode, \
1634 gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \
1635 const0_rtx, constm1_rtx))
1637 /* The function `__bb_trace_func' is called in every basic block
1638 and is not allowed to change the machine state. Saving (restoring)
1639 the state can either be done in the BLOCK_PROFILER macro,
1640 before calling function (rsp. after returning from function)
1641 `__bb_trace_func', or it can be done inside the function by
1642 defining the macros:
1644 MACHINE_STATE_SAVE(ID)
1645 MACHINE_STATE_RESTORE(ID)
1647 In the latter case care must be taken, that the prologue code
1648 of function `__bb_trace_func' does not already change the
1649 state prior to saving it with MACHINE_STATE_SAVE.
1651 The parameter `ID' is a string identifying a unique macro use.
1653 On the i386 the initialization code at the begin of
1654 function `__bb_trace_func' contains a `sub' instruction
1655 therefore we handle save and restore of the flag register
1656 in the BLOCK_PROFILER macro.
1658 Note that ebx, esi, and edi are callee-save, so we don't have to
1659 preserve them explicitly. */
1661 #define MACHINE_STATE_SAVE(ID) \
1663 register int eax_ __asm__("eax"); \
1664 register int ecx_ __asm__("ecx"); \
1665 register int edx_ __asm__("edx"); \
1666 __asm__ __volatile__ ("\
1670 : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
1673 #define MACHINE_STATE_RESTORE(ID) \
1675 register int eax_ __asm__("eax"); \
1676 register int ecx_ __asm__("ecx"); \
1677 register int edx_ __asm__("edx"); \
1678 __asm__ __volatile__ ("\
1682 : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
1685 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1686 the stack pointer does not matter. The value is tested only in
1687 functions that have frame pointers.
1688 No definition is equivalent to always zero. */
1689 /* Note on the 386 it might be more efficient not to define this since
1690 we have to restore it ourselves from the frame pointer, in order to
1693 #define EXIT_IGNORE_STACK 1
1695 /* Output assembler code for a block containing the constant parts
1696 of a trampoline, leaving space for the variable parts. */
1698 /* On the 386, the trampoline contains two instructions:
1701 The trampoline is generated entirely at runtime. The operand of JMP
1702 is the address of FUNCTION relative to the instruction following the
1703 JMP (which is 5 bytes long). */
1705 /* Length in units of the trampoline for entering a nested function. */
1707 #define TRAMPOLINE_SIZE 10
1709 /* Emit RTL insns to initialize the variable parts of a trampoline.
1710 FNADDR is an RTX for the address of the function's pure code.
1711 CXT is an RTX for the static chain value for the function. */
1713 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1715 /* Compute offset from the end of the jmp to the target function. */ \
1716 rtx disp = expand_binop (SImode, sub_optab, FNADDR, \
1717 plus_constant (TRAMP, 10), \
1718 NULL_RTX, 1, OPTAB_DIRECT); \
1719 emit_move_insn (gen_rtx_MEM (QImode, TRAMP), GEN_INT (0xb9)); \
1720 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 1)), CXT); \
1721 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 5)), GEN_INT (0xe9));\
1722 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 6)), disp); \
1725 /* Definitions for register eliminations.
1727 This is an array of structures. Each structure initializes one pair
1728 of eliminable registers. The "from" register number is given first,
1729 followed by "to". Eliminations of the same "from" register are listed
1730 in order of preference.
1732 There are two registers that can always be eliminated on the i386.
1733 The frame pointer and the arg pointer can be replaced by either the
1734 hard frame pointer or to the stack pointer, depending upon the
1735 circumstances. The hard frame pointer is not used before reload and
1736 so it is not eligible for elimination. */
1738 #define ELIMINABLE_REGS \
1739 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1740 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1741 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1742 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1744 /* Given FROM and TO register numbers, say whether this elimination is
1745 allowed. Frame pointer elimination is automatically handled.
1747 All other eliminations are valid. */
1749 #define CAN_ELIMINATE(FROM, TO) \
1750 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1752 /* Define the offset between two registers, one to be eliminated, and the other
1753 its replacement, at the start of a routine. */
1755 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1756 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1758 /* Addressing modes, and classification of registers for them. */
1760 /* #define HAVE_POST_INCREMENT 0 */
1761 /* #define HAVE_POST_DECREMENT 0 */
1763 /* #define HAVE_PRE_DECREMENT 0 */
1764 /* #define HAVE_PRE_INCREMENT 0 */
1766 /* Macros to check register numbers against specific register classes. */
1768 /* These assume that REGNO is a hard or pseudo reg number.
1769 They give nonzero only if REGNO is a hard reg of the suitable class
1770 or a pseudo reg currently allocated to a suitable hard reg.
1771 Since they use reg_renumber, they are safe only once reg_renumber
1772 has been allocated, which happens in local-alloc.c. */
1774 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1775 ((REGNO) < STACK_POINTER_REGNUM \
1776 || (REGNO >= FIRST_REX_INT_REG \
1777 && (REGNO) <= LAST_REX_INT_REG) \
1778 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1779 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1780 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1782 #define REGNO_OK_FOR_BASE_P(REGNO) \
1783 ((REGNO) <= STACK_POINTER_REGNUM \
1784 || (REGNO) == ARG_POINTER_REGNUM \
1785 || (REGNO) == FRAME_POINTER_REGNUM \
1786 || (REGNO >= FIRST_REX_INT_REG \
1787 && (REGNO) <= LAST_REX_INT_REG) \
1788 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1789 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1790 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1792 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1793 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1795 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1796 and check its validity for a certain class.
1797 We have two alternate definitions for each of them.
1798 The usual definition accepts all pseudo regs; the other rejects
1799 them unless they have been allocated suitable hard regs.
1800 The symbol REG_OK_STRICT causes the latter definition to be used.
1802 Most source files want to accept pseudo regs in the hope that
1803 they will get allocated to the class that the insn wants them to be in.
1804 Source files for reload pass need to be strict.
1805 After reload, it makes no difference, since pseudo regs have
1806 been eliminated by then. */
1809 /* Non strict versions, pseudos are ok */
1810 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1811 (REGNO (X) < STACK_POINTER_REGNUM \
1812 || (REGNO (X) >= FIRST_REX_INT_REG \
1813 && REGNO (X) <= LAST_REX_INT_REG) \
1814 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1816 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1817 (REGNO (X) <= STACK_POINTER_REGNUM \
1818 || REGNO (X) == ARG_POINTER_REGNUM \
1819 || REGNO (X) == FRAME_POINTER_REGNUM \
1820 || (REGNO (X) >= FIRST_REX_INT_REG \
1821 && REGNO (X) <= LAST_REX_INT_REG) \
1822 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1824 /* Strict versions, hard registers only */
1825 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1826 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1828 #ifndef REG_OK_STRICT
1829 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1830 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1833 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1834 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1837 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1838 that is a valid memory address for an instruction.
1839 The MODE argument is the machine mode for the MEM expression
1840 that wants to use this address.
1842 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1843 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1845 See legitimize_pic_address in i386.c for details as to what
1846 constitutes a legitimate address when -fpic is used. */
1848 #define MAX_REGS_PER_ADDRESS 2
1850 #define CONSTANT_ADDRESS_P(X) \
1851 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1852 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1853 || GET_CODE (X) == CONST_DOUBLE)
1855 /* Nonzero if the constant value X is a legitimate general operand.
1856 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1858 #define LEGITIMATE_CONSTANT_P(X) 1
1860 #ifdef REG_OK_STRICT
1861 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1863 if (legitimate_address_p (MODE, X, 1)) \
1868 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1870 if (legitimate_address_p (MODE, X, 0)) \
1876 /* If defined, a C expression to determine the base term of address X.
1877 This macro is used in only one place: `find_base_term' in alias.c.
1879 It is always safe for this macro to not be defined. It exists so
1880 that alias analysis can understand machine-dependent addresses.
1882 The typical use of this macro is to handle addresses containing
1883 a label_ref or symbol_ref within an UNSPEC. */
1885 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1887 /* Try machine-dependent ways of modifying an illegitimate address
1888 to be legitimate. If we find one, return the new, valid address.
1889 This macro is used in only one place: `memory_address' in explow.c.
1891 OLDX is the address as it was before break_out_memory_refs was called.
1892 In some cases it is useful to look at this to decide what needs to be done.
1894 MODE and WIN are passed so that this macro can use
1895 GO_IF_LEGITIMATE_ADDRESS.
1897 It is always safe for this macro to do nothing. It exists to recognize
1898 opportunities to optimize the output.
1900 For the 80386, we handle X+REG by loading X into a register R and
1901 using R+REG. R will go in a general reg and indexing will be used.
1902 However, if REG is a broken-out memory address or multiplication,
1903 nothing needs to be done because REG can certainly go in a general reg.
1905 When -fpic is used, special handling is needed for symbolic references.
1906 See comments by legitimize_pic_address in i386.c for details. */
1908 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1910 (X) = legitimize_address (X, OLDX, MODE); \
1911 if (memory_address_p (MODE, X)) \
1915 #define REWRITE_ADDRESS(x) rewrite_address(x)
1917 /* Nonzero if the constant value X is a legitimate general operand
1918 when generating PIC code. It is given that flag_pic is on and
1919 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1921 #define LEGITIMATE_PIC_OPERAND_P(X) \
1922 (! SYMBOLIC_CONST (X) \
1923 || legitimate_pic_address_disp_p (X))
1925 #define SYMBOLIC_CONST(X) \
1926 (GET_CODE (X) == SYMBOL_REF \
1927 || GET_CODE (X) == LABEL_REF \
1928 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1930 /* Go to LABEL if ADDR (a legitimate address expression)
1931 has an effect that depends on the machine mode it is used for.
1932 On the 80386, only postdecrement and postincrement address depend thus
1933 (the amount of decrement or increment being the length of the operand). */
1934 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1935 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
1937 /* Codes for all the SSE/MMX builtins. */
1949 IX86_BUILTIN_CMPEQPS
,
1950 IX86_BUILTIN_CMPLTPS
,
1951 IX86_BUILTIN_CMPLEPS
,
1952 IX86_BUILTIN_CMPGTPS
,
1953 IX86_BUILTIN_CMPGEPS
,
1954 IX86_BUILTIN_CMPNEQPS
,
1955 IX86_BUILTIN_CMPNLTPS
,
1956 IX86_BUILTIN_CMPNLEPS
,
1957 IX86_BUILTIN_CMPNGTPS
,
1958 IX86_BUILTIN_CMPNGEPS
,
1959 IX86_BUILTIN_CMPORDPS
,
1960 IX86_BUILTIN_CMPUNORDPS
,
1961 IX86_BUILTIN_CMPNEPS
,
1962 IX86_BUILTIN_CMPEQSS
,
1963 IX86_BUILTIN_CMPLTSS
,
1964 IX86_BUILTIN_CMPLESS
,
1965 IX86_BUILTIN_CMPGTSS
,
1966 IX86_BUILTIN_CMPGESS
,
1967 IX86_BUILTIN_CMPNEQSS
,
1968 IX86_BUILTIN_CMPNLTSS
,
1969 IX86_BUILTIN_CMPNLESS
,
1970 IX86_BUILTIN_CMPNGTSS
,
1971 IX86_BUILTIN_CMPNGESS
,
1972 IX86_BUILTIN_CMPORDSS
,
1973 IX86_BUILTIN_CMPUNORDSS
,
1974 IX86_BUILTIN_CMPNESS
,
1976 IX86_BUILTIN_COMIEQSS
,
1977 IX86_BUILTIN_COMILTSS
,
1978 IX86_BUILTIN_COMILESS
,
1979 IX86_BUILTIN_COMIGTSS
,
1980 IX86_BUILTIN_COMIGESS
,
1981 IX86_BUILTIN_COMINEQSS
,
1982 IX86_BUILTIN_UCOMIEQSS
,
1983 IX86_BUILTIN_UCOMILTSS
,
1984 IX86_BUILTIN_UCOMILESS
,
1985 IX86_BUILTIN_UCOMIGTSS
,
1986 IX86_BUILTIN_UCOMIGESS
,
1987 IX86_BUILTIN_UCOMINEQSS
,
1989 IX86_BUILTIN_CVTPI2PS
,
1990 IX86_BUILTIN_CVTPS2PI
,
1991 IX86_BUILTIN_CVTSI2SS
,
1992 IX86_BUILTIN_CVTSS2SI
,
1993 IX86_BUILTIN_CVTTPS2PI
,
1994 IX86_BUILTIN_CVTTSS2SI
,
1995 IX86_BUILTIN_M_FROM_INT
,
1996 IX86_BUILTIN_M_TO_INT
,
2003 IX86_BUILTIN_LOADAPS
,
2004 IX86_BUILTIN_LOADUPS
,
2005 IX86_BUILTIN_STOREAPS
,
2006 IX86_BUILTIN_STOREUPS
,
2007 IX86_BUILTIN_LOADSS
,
2008 IX86_BUILTIN_STORESS
,
2011 IX86_BUILTIN_MOVHLPS
,
2012 IX86_BUILTIN_MOVLHPS
,
2013 IX86_BUILTIN_LOADHPS
,
2014 IX86_BUILTIN_LOADLPS
,
2015 IX86_BUILTIN_STOREHPS
,
2016 IX86_BUILTIN_STORELPS
,
2018 IX86_BUILTIN_MASKMOVQ
,
2019 IX86_BUILTIN_MOVMSKPS
,
2020 IX86_BUILTIN_PMOVMSKB
,
2022 IX86_BUILTIN_MOVNTPS
,
2023 IX86_BUILTIN_MOVNTQ
,
2025 IX86_BUILTIN_PACKSSWB
,
2026 IX86_BUILTIN_PACKSSDW
,
2027 IX86_BUILTIN_PACKUSWB
,
2032 IX86_BUILTIN_PADDSB
,
2033 IX86_BUILTIN_PADDSW
,
2034 IX86_BUILTIN_PADDUSB
,
2035 IX86_BUILTIN_PADDUSW
,
2039 IX86_BUILTIN_PSUBSB
,
2040 IX86_BUILTIN_PSUBSW
,
2041 IX86_BUILTIN_PSUBUSB
,
2042 IX86_BUILTIN_PSUBUSW
,
2052 IX86_BUILTIN_PCMPEQB
,
2053 IX86_BUILTIN_PCMPEQW
,
2054 IX86_BUILTIN_PCMPEQD
,
2055 IX86_BUILTIN_PCMPGTB
,
2056 IX86_BUILTIN_PCMPGTW
,
2057 IX86_BUILTIN_PCMPGTD
,
2059 IX86_BUILTIN_PEXTRW
,
2060 IX86_BUILTIN_PINSRW
,
2062 IX86_BUILTIN_PMADDWD
,
2064 IX86_BUILTIN_PMAXSW
,
2065 IX86_BUILTIN_PMAXUB
,
2066 IX86_BUILTIN_PMINSW
,
2067 IX86_BUILTIN_PMINUB
,
2069 IX86_BUILTIN_PMULHUW
,
2070 IX86_BUILTIN_PMULHW
,
2071 IX86_BUILTIN_PMULLW
,
2073 IX86_BUILTIN_PSADBW
,
2074 IX86_BUILTIN_PSHUFW
,
2084 IX86_BUILTIN_PSLLWI
,
2085 IX86_BUILTIN_PSLLDI
,
2086 IX86_BUILTIN_PSLLQI
,
2087 IX86_BUILTIN_PSRAWI
,
2088 IX86_BUILTIN_PSRADI
,
2089 IX86_BUILTIN_PSRLWI
,
2090 IX86_BUILTIN_PSRLDI
,
2091 IX86_BUILTIN_PSRLQI
,
2093 IX86_BUILTIN_PUNPCKHBW
,
2094 IX86_BUILTIN_PUNPCKHWD
,
2095 IX86_BUILTIN_PUNPCKHDQ
,
2096 IX86_BUILTIN_PUNPCKLBW
,
2097 IX86_BUILTIN_PUNPCKLWD
,
2098 IX86_BUILTIN_PUNPCKLDQ
,
2100 IX86_BUILTIN_SHUFPS
,
2104 IX86_BUILTIN_RSQRTPS
,
2105 IX86_BUILTIN_RSQRTSS
,
2106 IX86_BUILTIN_SQRTPS
,
2107 IX86_BUILTIN_SQRTSS
,
2109 IX86_BUILTIN_UNPCKHPS
,
2110 IX86_BUILTIN_UNPCKLPS
,
2113 IX86_BUILTIN_ANDNPS
,
2118 IX86_BUILTIN_LDMXCSR
,
2119 IX86_BUILTIN_STMXCSR
,
2120 IX86_BUILTIN_SFENCE
,
2121 IX86_BUILTIN_PREFETCH
,
2123 /* Composite builtins, expand to more than one insn. */
2124 IX86_BUILTIN_SETPS1
,
2127 IX86_BUILTIN_SETRPS
,
2128 IX86_BUILTIN_LOADPS1
,
2129 IX86_BUILTIN_LOADRPS
,
2130 IX86_BUILTIN_STOREPS1
,
2131 IX86_BUILTIN_STORERPS
,
2133 IX86_BUILTIN_MMX_ZERO
,
2138 /* Initialize the target-specific builtin functions. Only do something
2139 if TARGET_MMX is nonzero; we take care in ix86_init_builtins not to
2140 enable any SSE builtins if TARGET_SSE is zero. */
2141 #define MD_INIT_BUILTINS \
2145 ix86_init_builtins (); \
2149 /* Expand a target-specific builtin function. */
2150 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
2151 ix86_expand_builtin (EXP, TARGET, SUBTARGET, MODE, IGNORE)
2153 /* Define this macro if references to a symbol must be treated
2154 differently depending on something about the variable or
2155 function named by the symbol (such as what section it is in).
2157 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2158 so that we may access it directly in the GOT. */
2160 #define ENCODE_SECTION_INFO(DECL) \
2165 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2166 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2168 if (GET_CODE (rtl) == MEM) \
2170 if (TARGET_DEBUG_ADDR \
2171 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2173 fprintf (stderr, "Encode %s, public = %d\n", \
2174 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2175 TREE_PUBLIC (DECL)); \
2178 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2179 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2180 || ! TREE_PUBLIC (DECL)); \
2186 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2187 codes once the function is being compiled into assembly code, but
2188 not before. (It is not done before, because in the case of
2189 compiling an inline function, it would lead to multiple PIC
2190 prologues being included in functions which used inline functions
2191 and were compiled to assembly language.) */
2193 #define FINALIZE_PIC \
2196 current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
2201 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2202 with arguments ARGS is a valid machine specific attribute for DECL.
2203 The attributes in ATTRIBUTES have previously been assigned to DECL. */
2205 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
2206 (ix86_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
2208 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2209 with arguments ARGS is a valid machine specific attribute for TYPE.
2210 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2212 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2213 (ix86_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2215 /* If defined, a C expression whose value is zero if the attributes on
2216 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2217 two if they are nearly compatible (which causes a warning to be
2220 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2221 (ix86_comp_type_attributes (TYPE1, TYPE2))
2223 /* If defined, a C statement that assigns default attributes to newly
2226 /* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */
2228 /* Max number of args passed in registers. If this is more than 3, we will
2229 have problems with ebx (register #4), since it is a caller save register and
2230 is also used as the pic register in ELF. So for now, don't allow more than
2231 3 registers to be passed in registers. */
2233 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2235 #define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
2238 /* Specify the machine mode that this machine uses
2239 for the index in the tablejump instruction. */
2240 #define CASE_VECTOR_MODE Pmode
2242 /* Define as C expression which evaluates to nonzero if the tablejump
2243 instruction expects the table to contain offsets from the address of the
2245 Do not define this if the table should contain absolute addresses. */
2246 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2248 /* Specify the tree operation to be used to convert reals to integers.
2249 This should be changed to take advantage of fist --wfs ??
2251 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2253 /* This is the kind of divide that is easiest to do in the general case. */
2254 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2256 /* Define this as 1 if `char' should by default be signed; else as 0. */
2257 #define DEFAULT_SIGNED_CHAR 1
2259 /* Max number of bytes we can move from memory to memory
2260 in one reasonably fast instruction. */
2263 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2264 move efficiently, as opposed to MOVE_MAX which is the maximum
2265 number of bytes we can move with a single instruction. */
2266 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2268 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2269 move-instruction pairs, we will do a movstr or libcall instead.
2270 Increasing the value will always make code faster, but eventually
2271 incurs high cost in increased code size.
2273 If you don't define this, a reasonable default is used. */
2275 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2277 /* Define if shifts truncate the shift count
2278 which implies one can omit a sign-extension or zero-extension
2279 of a shift count. */
2280 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2282 /* #define SHIFT_COUNT_TRUNCATED */
2284 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2285 is done just by pretending it is already truncated. */
2286 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2288 /* We assume that the store-condition-codes instructions store 0 for false
2289 and some other value for true. This is the value stored for true. */
2291 #define STORE_FLAG_VALUE 1
2293 /* When a prototype says `char' or `short', really pass an `int'.
2294 (The 386 can't easily push less than an int.) */
2296 #define PROMOTE_PROTOTYPES 1
2298 /* A macro to update M and UNSIGNEDP when an object whose type is
2299 TYPE and which has the specified mode and signedness is to be
2300 stored in a register. This macro is only called when TYPE is a
2303 On i386 it is sometimes usefull to promote HImode and QImode
2304 quantities to SImode. The choice depends on target type. */
2306 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2307 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2308 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2311 /* Specify the machine mode that pointers have.
2312 After generation of rtl, the compiler makes no further distinction
2313 between pointers and any other objects of this machine mode. */
2314 #define Pmode (TARGET_64BIT ? DImode : SImode)
2316 /* A function address in a call instruction
2317 is a byte address (for indexing purposes)
2318 so give the MEM rtx a byte's mode. */
2319 #define FUNCTION_MODE QImode
2321 /* A part of a C `switch' statement that describes the relative costs
2322 of constant RTL expressions. It must contain `case' labels for
2323 expression codes `const_int', `const', `symbol_ref', `label_ref'
2324 and `const_double'. Each case must ultimately reach a `return'
2325 statement to return the relative cost of the use of that kind of
2326 constant value in an expression. The cost may depend on the
2327 precise value of the constant, which is available for examination
2328 in X, and the rtx code of the expression in which it is contained,
2329 found in OUTER_CODE.
2331 CODE is the expression code--redundant, since it can be obtained
2332 with `GET_CODE (X)'. */
2334 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2336 return (unsigned) INTVAL (RTX) < 256 ? 0 : 1; \
2340 return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 1; \
2342 case CONST_DOUBLE: \
2345 if (GET_MODE (RTX) == VOIDmode) \
2348 code = standard_80387_constant_p (RTX); \
2349 return code == 1 ? 0 : \
2354 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2355 #define TOPLEVEL_COSTS_N_INSNS(N) \
2356 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2358 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2359 This can be used, for example, to indicate how costly a multiply
2360 instruction is. In writing this macro, you can use the construct
2361 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2362 instructions. OUTER_CODE is the code of the expression in which X
2365 This macro is optional; do not define it if the default cost
2366 assumptions are adequate for the target machine. */
2368 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2370 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2371 && GET_MODE (XEXP (X, 0)) == SImode) \
2373 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2375 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2376 if (value == 2 || value == 3) \
2377 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2379 /* fall through */ \
2385 if (GET_MODE (XEXP (X, 0)) == DImode) \
2387 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2389 if (INTVAL (XEXP (X, 1)) > 32) \
2390 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2392 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2396 if (GET_CODE (XEXP (X, 1)) == AND) \
2397 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2399 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2404 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2405 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2407 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2412 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2414 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2417 while (value != 0) \
2423 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2424 + nbits * ix86_cost->mult_bit); \
2426 else /* This is arbitrary */ \
2427 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2428 + 7 * ix86_cost->mult_bit); \
2434 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2437 if (GET_CODE (XEXP (X, 0)) == PLUS \
2438 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2439 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2440 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2442 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \
2443 if (val == 2 || val == 4 || val == 8) \
2445 return (COSTS_N_INSNS (ix86_cost->lea) \
2446 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2447 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2448 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2451 else if (GET_CODE (XEXP (X, 0)) == MULT \
2452 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2454 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2455 if (val == 2 || val == 4 || val == 8) \
2457 return (COSTS_N_INSNS (ix86_cost->lea) \
2458 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2459 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2462 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2464 return (COSTS_N_INSNS (ix86_cost->lea) \
2465 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2466 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2467 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2470 /* fall through */ \
2475 if (GET_MODE (X) == DImode) \
2476 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2477 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2478 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2479 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2480 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2482 /* fall through */ \
2485 if (GET_MODE (X) == DImode) \
2486 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2487 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2493 /* An expression giving the cost of an addressing mode that contains
2494 ADDRESS. If not defined, the cost is computed from the ADDRESS
2495 expression and the `CONST_COSTS' values.
2497 For most CISC machines, the default cost is a good approximation
2498 of the true cost of the addressing mode. However, on RISC
2499 machines, all instructions normally have the same length and
2500 execution time. Hence all addresses will have equal costs.
2502 In cases where more than one form of an address is known, the form
2503 with the lowest cost will be used. If multiple forms have the
2504 same, lowest, cost, the one that is the most complex will be used.
2506 For example, suppose an address that is equal to the sum of a
2507 register and a constant is used twice in the same basic block.
2508 When this macro is not defined, the address will be computed in a
2509 register and memory references will be indirect through that
2510 register. On machines where the cost of the addressing mode
2511 containing the sum is no higher than that of a simple indirect
2512 reference, this will produce an additional instruction and
2513 possibly require an additional register. Proper specification of
2514 this macro eliminates this overhead for such machines.
2516 Similar use of this macro is made in strength reduction of loops.
2518 ADDRESS need not be valid as an address. In such a case, the cost
2519 is not relevant and can be any value; invalid addresses need not be
2520 assigned a different cost.
2522 On machines where an address involving more than one register is as
2523 cheap as an address computation involving only one register,
2524 defining `ADDRESS_COST' to reflect this can cause two registers to
2525 be live over a region of code where only one would have been if
2526 `ADDRESS_COST' were not defined in that manner. This effect should
2527 be considered in the definition of this macro. Equivalent costs
2528 should probably only be given to addresses with different numbers
2529 of registers on machines with lots of registers.
2531 This macro will normally either not be defined or be defined as a
2534 For i386, it is better to use a complex address than let gcc copy
2535 the address into a reg and make a new pseudo. But not if the address
2536 requires to two regs - that would mean more pseudos with longer
2539 #define ADDRESS_COST(RTX) \
2540 ix86_address_cost (RTX)
2542 /* A C expression for the cost of moving data from a register in class FROM to
2543 one in class TO. The classes are expressed using the enumeration values
2544 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2545 interpreted relative to that.
2547 It is not required that the cost always equal 2 when FROM is the same as TO;
2548 on some machines it is expensive to move between registers if they are not
2549 general registers. */
2551 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2552 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2554 /* A C expression for the cost of moving data of mode M between a
2555 register and memory. A value of 2 is the default; this cost is
2556 relative to those in `REGISTER_MOVE_COST'.
2558 If moving between registers and memory is more expensive than
2559 between two registers, you should define this macro to express the
2562 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2563 ix86_memory_move_cost (MODE, CLASS, IN)
2565 /* A C expression for the cost of a branch instruction. A value of 1
2566 is the default; other values are interpreted relative to that. */
2568 #define BRANCH_COST ix86_branch_cost
2570 /* Define this macro as a C expression which is nonzero if accessing
2571 less than a word of memory (i.e. a `char' or a `short') is no
2572 faster than accessing a word of memory, i.e., if such access
2573 require more than one instruction or if there is no difference in
2574 cost between byte and (aligned) word loads.
2576 When this macro is not defined, the compiler will access a field by
2577 finding the smallest containing object; when it is defined, a
2578 fullword load will be used if alignment permits. Unless bytes
2579 accesses are faster than word accesses, using word accesses is
2580 preferable since it may eliminate subsequent memory access if
2581 subsequent accesses occur to other fields in the same word of the
2582 structure, but to different bytes. */
2584 #define SLOW_BYTE_ACCESS 0
2586 /* Nonzero if access to memory by shorts is slow and undesirable. */
2587 #define SLOW_SHORT_ACCESS 0
2589 /* Define this macro if zero-extension (of a `char' or `short' to an
2590 `int') can be done faster if the destination is a register that is
2593 If you define this macro, you must have instruction patterns that
2594 recognize RTL structures like this:
2596 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2598 and likewise for `HImode'. */
2600 /* #define SLOW_ZERO_EXTEND */
2602 /* Define this macro to be the value 1 if unaligned accesses have a
2603 cost many times greater than aligned accesses, for example if they
2604 are emulated in a trap handler.
2606 When this macro is non-zero, the compiler will act as if
2607 `STRICT_ALIGNMENT' were non-zero when generating code for block
2608 moves. This can cause significantly more instructions to be
2609 produced. Therefore, do not set this macro non-zero if unaligned
2610 accesses only add a cycle or two to the time for a memory access.
2612 If the value of this macro is always zero, it need not be defined. */
2614 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2616 /* Define this macro to inhibit strength reduction of memory
2617 addresses. (On some machines, such strength reduction seems to do
2618 harm rather than good.) */
2620 /* #define DONT_REDUCE_ADDR */
2622 /* Define this macro if it is as good or better to call a constant
2623 function address than to call an address kept in a register.
2625 Desirable on the 386 because a CALL with a constant address is
2626 faster than one with a register address. */
2628 #define NO_FUNCTION_CSE
2630 /* Define this macro if it is as good or better for a function to call
2631 itself with an explicit address than to call an address kept in a
2634 #define NO_RECURSIVE_FUNCTION_CSE
2636 /* A C statement (sans semicolon) to update the integer variable COST
2637 based on the relationship between INSN that is dependent on
2638 DEP_INSN through the dependence LINK. The default is to make no
2639 adjustment to COST. This can be used for example to specify to
2640 the scheduler that an output- or anti-dependence does not incur
2641 the same cost as a data-dependence. */
2643 #define ADJUST_COST(insn,link,dep_insn,cost) \
2644 (cost) = ix86_adjust_cost(insn, link, dep_insn, cost)
2646 #define ISSUE_RATE \
2649 #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE, MAX_READY) \
2650 ix86_sched_init (DUMP, SCHED_VERBOSE)
2652 #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
2653 (CIM) = ix86_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK)
2655 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
2656 ((CAN_ISSUE_MORE) = \
2657 ix86_variable_issue (DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE))
2659 /* Add any extra modes needed to represent the condition code.
2661 For the i386, we need separate modes when floating-point
2662 equality comparisons are being done.
2664 Add CCNO to indicate comparisons against zero that requires
2665 Overflow flag to be unset. Sign bit test is used instead and
2666 thus can be used to form "a&b>0" type of tests.
2668 Add CCGC to indicate comparisons agains zero that allows
2669 unspecified garbage in the Carry flag. This mode is used
2670 by inc/dec instructions.
2672 Add CCGOC to indicate comparisons agains zero that allows
2673 unspecified garbage in the Carry and Overflow flag. This
2674 mode is used to simulate comparisons of (a-b) and (a+b)
2675 against zero using sub/cmp/add operations.
2677 Add CCZ to indicate that only the Zero flag is valid. */
2679 #define EXTRA_CC_MODES \
2680 CC(CCGCmode, "CCGC") \
2681 CC(CCGOCmode, "CCGOC") \
2682 CC(CCNOmode, "CCNO") \
2683 CC(CCZmode, "CCZ") \
2684 CC(CCFPmode, "CCFP") \
2685 CC(CCFPUmode, "CCFPU")
2687 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2688 return the mode to be used for the comparison.
2690 For floating-point equality comparisons, CCFPEQmode should be used.
2691 VOIDmode should be used in all other cases.
2693 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2694 possible, to allow for more combinations. */
2696 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2698 /* Return non-zero if MODE implies a floating point inequality can be
2701 #define REVERSIBLE_CC_MODE(MODE) 1
2703 /* A C expression whose value is reversed condition code of the CODE for
2704 comparison done in CC_MODE mode. */
2705 #define REVERSE_CONDITION(CODE, MODE) \
2706 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2707 : reverse_condition_maybe_unordered (CODE))
2710 /* Control the assembler format that we output, to the extent
2711 this does not vary between assemblers. */
2713 /* How to refer to registers in assembler output.
2714 This sequence is indexed by compiler's hard-register-number (see above). */
2716 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2717 For non floating point regs, the following are the HImode names.
2719 For float regs, the stack top is sometimes referred to as "%st(0)"
2720 instead of just "%st". PRINT_REG handles this with the "y" code. */
2722 #define HI_REGISTER_NAMES \
2723 {"ax","dx","cx","bx","si","di","bp","sp", \
2724 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2725 "flags","fpsr", "dirflag", "frame" }
2727 #undef HI_REGISTER_NAMES
2728 #define HI_REGISTER_NAMES \
2729 {"ax","dx","cx","bx","si","di","bp","sp", \
2730 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2731 "flags","fpsr", "dirflag", "frame", \
2732 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2733 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2734 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2735 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2737 #define REGISTER_NAMES HI_REGISTER_NAMES
2739 /* Table of additional register names to use in user input. */
2741 #define ADDITIONAL_REGISTER_NAMES \
2742 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2743 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2744 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2745 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2746 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2747 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2748 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2749 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2751 /* Note we are omitting these since currently I don't know how
2752 to get gcc to use these, since they want the same but different
2753 number as al, and ax.
2756 #define QI_REGISTER_NAMES \
2757 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2759 /* These parallel the array above, and can be used to access bits 8:15
2760 of regs 0 through 3. */
2762 #define QI_HIGH_REGISTER_NAMES \
2763 {"ah", "dh", "ch", "bh", }
2765 #define MMX_REGISTER_NAMES \
2766 {0,0,0,0,0,0,0,0,"mm0","mm1","mm2","mm3","mm4","mm5","mm6","mm7"}
2768 /* How to renumber registers for dbx and gdb. */
2770 #define DBX_REGISTER_NUMBER(n) \
2771 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2773 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2774 extern int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
];
2775 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2777 /* Before the prologue, RA is at 0(%esp). */
2778 #define INCOMING_RETURN_ADDR_RTX \
2779 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2781 /* After the prologue, RA is at -4(AP) in the current frame. */
2782 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2784 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2785 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2787 /* PC is dbx register 8; let's use that column for RA. */
2788 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2790 /* Before the prologue, the top of the frame is at 4(%esp). */
2791 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2793 /* Describe how we implement __builtin_eh_return. */
2794 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2795 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2797 /* This is how to output the definition of a user-level label named NAME,
2798 such as the label on a static function or variable NAME. */
2800 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2801 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2803 /* This is how to output an assembler line defining a `double' constant. */
2805 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2807 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2808 fprintf (FILE, "%s\t0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2811 /* This is how to output a `long double' extended real constant. */
2813 #undef ASM_OUTPUT_LONG_DOUBLE
2814 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2816 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2817 if (TARGET_128BIT_LONG_DOUBLE) \
2818 fprintf (FILE, "%s\t0x%lx,0x%lx,0x%lx,0x0\n", ASM_LONG, l[0], l[1], l[2]); \
2820 fprintf (FILE, "%s\t0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2823 /* This is how to output an assembler line defining a `float' constant. */
2825 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2827 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2828 fprintf ((FILE), "%s\t0x%lx\n", ASM_LONG, l); \
2831 /* Store in OUTPUT a string (made with alloca) containing
2832 an assembler-name for a local static variable named NAME.
2833 LABELNO is an integer which is different for each call. */
2835 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2836 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2837 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2839 /* This is how to output an assembler line defining an `int' constant. */
2841 #define ASM_OUTPUT_INT(FILE,VALUE) \
2842 ( fprintf (FILE, "%s\t", ASM_LONG), \
2843 output_addr_const (FILE,(VALUE)), \
2846 /* Likewise for `char' and `short' constants. */
2847 /* is this supposed to do align too?? */
2849 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2850 ( fprintf (FILE, "%s\t", ASM_SHORT), \
2851 output_addr_const (FILE,(VALUE)), \
2854 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2855 ( fprintf (FILE, "%s", ASM_BYTE_OP), \
2856 output_addr_const (FILE, (VALUE)), \
2859 /* This is how to output an assembler line for a numeric constant byte. */
2861 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2862 asm_fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (VALUE))
2864 /* This is how to output an insn to push a register on the stack.
2865 It need not be very fast code. */
2867 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2868 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2870 /* This is how to output an insn to pop a register from the stack.
2871 It need not be very fast code. */
2873 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2874 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2876 /* This is how to output an element of a case-vector that is absolute.
2879 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2880 fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE)
2882 /* This is how to output an element of a case-vector that is relative.
2883 We don't use these on the 386 yet, because the ATT assembler can't do
2884 forward reference the differences.
2887 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2888 fprintf (FILE, "\t%s\t%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
2890 /* A C statement that outputs an address constant appropriate to
2891 for DWARF debugging. */
2893 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2894 i386_dwarf_output_addr_const((FILE),(X))
2896 /* Either simplify a location expression, or return the original. */
2898 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2899 i386_simplify_dwarf_addr(X)
2901 /* Define the parentheses used to group arithmetic operations
2902 in assembler code. */
2904 #define ASM_OPEN_PAREN ""
2905 #define ASM_CLOSE_PAREN ""
2907 /* Define results of standard character escape sequences. */
2908 #define TARGET_BELL 007
2909 #define TARGET_BS 010
2910 #define TARGET_TAB 011
2911 #define TARGET_NEWLINE 012
2912 #define TARGET_VT 013
2913 #define TARGET_FF 014
2914 #define TARGET_CR 015
2916 /* Print operand X (an rtx) in assembler syntax to file FILE.
2917 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2918 The CODE z takes the size of operand from the following digit, and
2919 outputs b,w,or l respectively.
2921 On the 80386, we use several such letters:
2922 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
2923 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
2924 R -- print the prefix for register names.
2925 z -- print the opcode suffix for the size of the current operand.
2926 * -- print a star (in certain assembler syntax)
2927 A -- print an absolute memory reference.
2928 P -- if PIC, print an @PLT suffix.
2929 X -- don't print any sort of PIC '@' suffix for a symbol.
2930 s -- ??? something to do with double shifts. not actually used, afaik.
2931 C -- print a conditional move suffix corresponding to the op code.
2932 c -- likewise, but reverse the condition.
2933 F,f -- likewise, but for floating-point. */
2935 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2938 /* Print the name of a register based on its machine mode and number.
2939 If CODE is 'w', pretend the mode is HImode.
2940 If CODE is 'b', pretend the mode is QImode.
2941 If CODE is 'k', pretend the mode is SImode.
2942 If CODE is 'd', pretend the mode is DImode.
2943 If CODE is 'h', pretend the reg is the `high' byte register.
2944 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2946 #define PRINT_REG(X, CODE, FILE) \
2947 print_reg (X, CODE, FILE)
2949 #define PRINT_OPERAND(FILE, X, CODE) \
2950 print_operand (FILE, X, CODE)
2952 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2953 print_operand_address (FILE, ADDR)
2955 /* Print the name of a register for based on its machine mode and number.
2956 This macro is used to print debugging output.
2957 This macro is different from PRINT_REG in that it may be used in
2958 programs that are not linked with aux-output.o. */
2960 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2961 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2962 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2963 fprintf (FILE, "%d ", REGNO (X)); \
2964 if (REGNO (X) == FLAGS_REG) \
2965 { fputs ("flags", FILE); break; } \
2966 if (REGNO (X) == DIRFLAG_REG) \
2967 { fputs ("dirflag", FILE); break; } \
2968 if (REGNO (X) == FPSR_REG) \
2969 { fputs ("fpsr", FILE); break; } \
2970 if (REGNO (X) == ARG_POINTER_REGNUM) \
2971 { fputs ("argp", FILE); break; } \
2972 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2973 { fputs ("frame", FILE); break; } \
2974 if (STACK_TOP_P (X)) \
2975 { fputs ("st(0)", FILE); break; } \
2977 { fputs (hi_name[REGNO(X)], FILE); break; } \
2978 if (REX_INT_REG_P (X)) \
2980 switch (GET_MODE_SIZE (GET_MODE (X))) \
2984 fprintf (FILE, "r%i", REGNO (X) \
2985 - FIRST_REX_INT_REG + 8); \
2988 fprintf (FILE, "r%id", REGNO (X) \
2989 - FIRST_REX_INT_REG + 8); \
2992 fprintf (FILE, "r%iw", REGNO (X) \
2993 - FIRST_REX_INT_REG + 8); \
2996 fprintf (FILE, "r%ib", REGNO (X) \
2997 - FIRST_REX_INT_REG + 8); \
3002 switch (GET_MODE_SIZE (GET_MODE (X))) \
3005 fputs ("r", FILE); \
3006 fputs (hi_name[REGNO (X)], FILE); \
3009 fputs ("e", FILE); \
3011 fputs (hi_name[REGNO (X)], FILE); \
3014 fputs (qi_name[REGNO (X)], FILE); \
3019 /* Routines in libgcc that return floats must return them in an fp reg,
3020 just as other functions do which return such values.
3021 These macros make that happen. */
3023 #define FLOAT_VALUE_TYPE float
3024 #define INTIFY(FLOATVAL) FLOATVAL
3026 /* a letter which is not needed by the normal asm syntax, which
3027 we can use for operand syntax in the extended asm */
3029 #define ASM_OPERAND_LETTER '#'
3030 #define RET return ""
3031 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3033 /* Define the codes that are matched by predicates in i386.c. */
3035 #define PREDICATE_CODES \
3036 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3037 SYMBOL_REF, LABEL_REF, CONST}}, \
3038 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3039 SYMBOL_REF, LABEL_REF, CONST}}, \
3040 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3041 SYMBOL_REF, LABEL_REF, CONST}}, \
3042 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3043 SYMBOL_REF, LABEL_REF, CONST}}, \
3044 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3045 SYMBOL_REF, LABEL_REF, CONST}}, \
3046 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3047 SYMBOL_REF, LABEL_REF, CONST}}, \
3048 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3049 SYMBOL_REF, LABEL_REF}}, \
3050 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3051 {"const_int_1_operand", {CONST_INT}}, \
3052 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3053 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3054 LABEL_REF, SUBREG, REG, MEM}}, \
3055 {"pic_symbolic_operand", {CONST}}, \
3056 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3057 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3058 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3059 {"const1_operand", {CONST_INT}}, \
3060 {"const248_operand", {CONST_INT}}, \
3061 {"incdec_operand", {CONST_INT}}, \
3062 {"mmx_reg_operand", {REG}}, \
3063 {"reg_no_sp_operand", {SUBREG, REG}}, \
3064 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3065 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3066 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3067 {"q_regs_operand", {SUBREG, REG}}, \
3068 {"non_q_regs_operand", {SUBREG, REG}}, \
3069 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3070 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3071 GE, UNGE, LTGT, UNEQ}}, \
3072 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3073 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3075 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3076 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3077 UNGE, UNGT, LTGT, UNEQ }}, \
3078 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3079 {"ext_register_operand", {SUBREG, REG}}, \
3080 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3081 {"mult_operator", {MULT}}, \
3082 {"div_operator", {DIV}}, \
3083 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3084 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3085 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3086 LSHIFTRT, ROTATERT}}, \
3087 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3088 {"memory_displacement_operand", {MEM}}, \
3089 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3090 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3091 {"long_memory_operand", {MEM}},
3093 /* A list of predicates that do special things with modes, and so
3094 should not elicit warnings for VOIDmode match_operand. */
3096 #define SPECIAL_MODE_PREDICATES \
3097 "ext_register_operand",
3099 /* CM_32 is used by 32bit ABI
3100 CM_SMALL is small model assuming that all code and data fits in the first
3101 31bits of address space.
3102 CM_KERNEL is model assuming that all code and data fits in the negative
3103 31bits of address space.
3104 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3105 space. Size of data is unlimited.
3106 CM_LARGE is model making no assumptions about size of particular sections.
3108 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3109 tables first in 31bits of address space.
3120 /* Size of the RED_ZONE area. */
3121 #define RED_ZONE_SIZE 128
3122 /* Reserved area of the red zone for temporaries. */
3123 #define RED_ZONE_RESERVE 8
3124 /* Valud of -mcmodel specified by user. */
3125 extern const char *ix86_cmodel_string
;
3126 extern enum cmodel ix86_cmodel
;
3128 /* Variables in i386.c */
3129 extern const char *ix86_cpu_string
; /* for -mcpu=<xxx> */
3130 extern const char *ix86_arch_string
; /* for -march=<xxx> */
3131 extern const char *ix86_regparm_string
; /* # registers to use to pass args */
3132 extern const char *ix86_align_loops_string
; /* power of two alignment for loops */
3133 extern const char *ix86_align_jumps_string
; /* power of two alignment for non-loop jumps */
3134 extern const char *ix86_align_funcs_string
; /* power of two alignment for functions */
3135 extern const char *ix86_preferred_stack_boundary_string
;/* power of two alignment for stack boundary */
3136 extern const char *ix86_branch_cost_string
; /* values 1-5: see jump.c */
3137 extern int ix86_regparm
; /* ix86_regparm_string as a number */
3138 extern int ix86_align_loops
; /* power of two alignment for loops */
3139 extern int ix86_align_jumps
; /* power of two alignment for non-loop jumps */
3140 extern int ix86_align_funcs
; /* power of two alignment for functions */
3141 extern int ix86_preferred_stack_boundary
; /* preferred stack boundary alignment in bits */
3142 extern int ix86_branch_cost
; /* values 1-5: see jump.c */
3143 extern const char * const hi_reg_name
[]; /* names for 16 bit regs */
3144 extern const char * const qi_reg_name
[]; /* names for 8 bit regs (low) */
3145 extern const char * const qi_high_reg_name
[]; /* names for 8 bit regs (high) */
3146 extern enum reg_class
const regclass_map
[]; /* smalled class containing REGNO */
3147 extern struct rtx_def
*ix86_compare_op0
; /* operand 0 for comparisons */
3148 extern struct rtx_def
*ix86_compare_op1
; /* operand 1 for comparisons */