1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs
{
40 const int add
; /* cost of an add instruction */
41 const int lea
; /* cost of a lea instruction */
42 const int shift_var
; /* variable shift costs */
43 const int shift_const
; /* constant shift costs */
44 const int mult_init
; /* cost of starting a multiply */
45 const int mult_bit
; /* cost of multiply per each bit set */
46 const int divide
; /* cost of a divide/mod */
47 int movsx
; /* The cost of movsx operation. */
48 int movzx
; /* The cost of movzx operation. */
49 const int large_insn
; /* insns larger than this cost more */
50 const int move_ratio
; /* The threshold of number of scalar
51 memory-to-memory move insns. */
52 const int movzbl_load
; /* cost of loading using movzbl */
53 const int int_load
[3]; /* cost of loading integer registers
54 in QImode, HImode and SImode relative
55 to reg-reg move (2). */
56 const int int_store
[3]; /* cost of storing integer register
57 in QImode, HImode and SImode */
58 const int fp_move
; /* cost of reg,reg fld/fst */
59 const int fp_load
[3]; /* cost of loading FP register
60 in SFmode, DFmode and XFmode */
61 const int fp_store
[3]; /* cost of storing FP register
62 in SFmode, DFmode and XFmode */
63 const int mmx_move
; /* cost of moving MMX register. */
64 const int mmx_load
[2]; /* cost of loading MMX register
65 in SImode and DImode */
66 const int mmx_store
[2]; /* cost of storing MMX register
67 in SImode and DImode */
68 const int sse_move
; /* cost of moving SSE register. */
69 const int sse_load
[3]; /* cost of loading SSE register
70 in SImode, DImode and TImode*/
71 const int sse_store
[3]; /* cost of storing SSE register
72 in SImode, DImode and TImode*/
73 const int mmxsse_to_integer
; /* cost of moving mmxsse register to
74 integer and vice versa. */
75 const int prefetch_block
; /* bytes moved to cache for prefetch. */
76 const int simultaneous_prefetches
; /* number of parallel prefetch
80 extern const struct processor_costs
*ix86_cost
;
82 /* Run-time compilation parameters selecting different hardware subsets. */
84 extern int target_flags
;
86 /* Macros used in the machine description to test the flags. */
88 /* configure can arrange to make this 2, to force a 486. */
90 #ifndef TARGET_CPU_DEFAULT
91 #define TARGET_CPU_DEFAULT 0
94 /* Masks for the -m switches */
95 #define MASK_80387 0x00000001 /* Hardware floating point */
96 #define MASK_RTD 0x00000002 /* Use ret that pops args */
97 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
98 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
99 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
100 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
101 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
102 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
103 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
104 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
105 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
106 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
107 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
108 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
109 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
110 #define MASK_MMX_SET 0x00008000
111 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
112 #define MASK_SSE_SET 0x00020000
113 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
114 #define MASK_SSE2_SET 0x00080000
115 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
116 #define MASK_3DNOW_SET 0x00200000
117 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
118 #define MASK_3DNOW_A_SET 0x00800000
119 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
120 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
121 /* ... overlap with subtarget options starts by 0x04000000. */
122 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
124 /* Use the floating point instructions */
125 #define TARGET_80387 (target_flags & MASK_80387)
127 /* Compile using ret insn that pops args.
128 This will not work unless you use prototypes at least
129 for all functions that can take varying numbers of args. */
130 #define TARGET_RTD (target_flags & MASK_RTD)
132 /* Align doubles to a two word boundary. This breaks compatibility with
133 the published ABI's for structures containing doubles, but produces
134 faster code on the pentium. */
135 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
137 /* Use push instructions to save outgoing args. */
138 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
140 /* Accumulate stack adjustments to prologue/epilogue. */
141 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
142 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
144 /* Put uninitialized locals into bss, not data.
145 Meaningful only on svr3. */
146 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
148 /* Use IEEE floating point comparisons. These handle correctly the cases
149 where the result of a comparison is unordered. Normally SIGFPE is
150 generated in such cases, in which case this isn't needed. */
151 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
153 /* Functions that return a floating point value may return that value
154 in the 387 FPU or in 386 integer registers. If set, this flag causes
155 the 387 to be used, which is compatible with most calling conventions. */
156 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
158 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
159 This mode wastes cache, but avoid misaligned data accesses and simplifies
160 address calculations. */
161 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
163 /* Disable generation of FP sin, cos and sqrt operations for 387.
164 This is because FreeBSD lacks these in the math-emulator-code */
165 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
167 /* Don't create frame pointers for leaf functions */
168 #define TARGET_OMIT_LEAF_FRAME_POINTER \
169 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
171 /* Debug GO_IF_LEGITIMATE_ADDRESS */
172 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
174 /* Debug FUNCTION_ARG macros */
175 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
177 /* 64bit Sledgehammer mode */
178 #ifdef TARGET_BI_ARCH
179 #define TARGET_64BIT (target_flags & MASK_64BIT)
181 #if TARGET_64BIT_DEFAULT
182 #define TARGET_64BIT 1
184 #define TARGET_64BIT 0
188 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
189 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
190 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
191 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
192 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
193 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
194 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
196 #define CPUMASK (1 << ix86_cpu)
197 extern const int x86_use_leave
, x86_push_memory
, x86_zero_extend_with_and
;
198 extern const int x86_use_bit_test
, x86_cmove
, x86_deep_branch
;
199 extern const int x86_branch_hints
, x86_unroll_strlen
;
200 extern const int x86_double_with_add
, x86_partial_reg_stall
, x86_movx
;
201 extern const int x86_use_loop
, x86_use_fiop
, x86_use_mov0
;
202 extern const int x86_use_cltd
, x86_read_modify_write
;
203 extern const int x86_read_modify
, x86_split_long_moves
;
204 extern const int x86_promote_QImode
, x86_single_stringop
, x86_fast_prefix
;
205 extern const int x86_himode_math
, x86_qimode_math
, x86_promote_qi_regs
;
206 extern const int x86_promote_hi_regs
, x86_integer_DFmode_moves
;
207 extern const int x86_add_esp_4
, x86_add_esp_8
, x86_sub_esp_4
, x86_sub_esp_8
;
208 extern const int x86_partial_reg_dependency
, x86_memory_mismatch_stall
;
209 extern const int x86_accumulate_outgoing_args
, x86_prologue_using_move
;
210 extern const int x86_epilogue_using_move
, x86_decompose_lea
;
211 extern const int x86_arch_always_fancy_math_387
, x86_shift1
;
212 extern int x86_prefetch_sse
;
214 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
215 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
216 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
217 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
218 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
219 /* For sane SSE instruction set generation we need fcomi instruction. It is
220 safe to enable all CMOVE instructions. */
221 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
222 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
223 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
224 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
225 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
226 #define TARGET_MOVX (x86_movx & CPUMASK)
227 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
228 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
229 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
230 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
231 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
232 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
233 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
234 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
235 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
236 #define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK)
237 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
238 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
239 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
240 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
241 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
242 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
243 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
244 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
245 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
246 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
247 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
248 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
249 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
250 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
251 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
252 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
253 #define TARGET_SHIFT1 (x86_shift1 & CPUMASK)
255 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
257 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
258 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
260 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
262 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
263 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
264 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
265 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
266 && (ix86_fpmath & FPMATH_387))
267 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
268 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
269 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
271 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
273 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
274 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
276 /* WARNING: Do not mark empty strings for translation, as calling
277 gettext on an empty string does NOT return an empty
281 #define TARGET_SWITCHES \
282 { { "80387", MASK_80387, N_("Use hardware fp") }, \
283 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
284 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
285 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
286 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
287 { "386", 0, "" /*Deprecated.*/}, \
288 { "486", 0, "" /*Deprecated.*/}, \
289 { "pentium", 0, "" /*Deprecated.*/}, \
290 { "pentiumpro", 0, "" /*Deprecated.*/}, \
291 { "intel-syntax", 0, "" /*Deprecated.*/}, \
292 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
294 N_("Alternate calling convention") }, \
295 { "no-rtd", -MASK_RTD, \
296 N_("Use normal calling convention") }, \
297 { "align-double", MASK_ALIGN_DOUBLE, \
298 N_("Align some doubles on dword boundary") }, \
299 { "no-align-double", -MASK_ALIGN_DOUBLE, \
300 N_("Align doubles on word boundary") }, \
301 { "svr3-shlib", MASK_SVR3_SHLIB, \
302 N_("Uninitialized locals in .bss") }, \
303 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
304 N_("Uninitialized locals in .data") }, \
305 { "ieee-fp", MASK_IEEE_FP, \
306 N_("Use IEEE math for fp comparisons") }, \
307 { "no-ieee-fp", -MASK_IEEE_FP, \
308 N_("Do not use IEEE math for fp comparisons") }, \
309 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
310 N_("Return values of functions in FPU registers") }, \
311 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
312 N_("Do not return values of functions in FPU registers")}, \
313 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
314 N_("Do not generate sin, cos, sqrt for FPU") }, \
315 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
316 N_("Generate sin, cos, sqrt for FPU")}, \
317 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
318 N_("Omit the frame pointer in leaf functions") }, \
319 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
320 { "stack-arg-probe", MASK_STACK_PROBE, \
321 N_("Enable stack probing") }, \
322 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
323 { "windows", 0, 0 /* undocumented */ }, \
324 { "dll", 0, 0 /* undocumented */ }, \
325 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
326 N_("Align destination of the string operations") }, \
327 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
328 N_("Do not align destination of the string operations") }, \
329 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
330 N_("Inline all known string operations") }, \
331 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
332 N_("Do not inline all known string operations") }, \
333 { "push-args", -MASK_NO_PUSH_ARGS, \
334 N_("Use push instructions to save outgoing arguments") }, \
335 { "no-push-args", MASK_NO_PUSH_ARGS, \
336 N_("Do not use push instructions to save outgoing arguments") }, \
337 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
338 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
339 N_("Use push instructions to save outgoing arguments") }, \
340 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
341 N_("Do not use push instructions to save outgoing arguments") }, \
342 { "mmx", MASK_MMX | MASK_MMX_SET, \
343 N_("Support MMX built-in functions") }, \
344 { "no-mmx", -MASK_MMX, \
345 N_("Do not support MMX built-in functions") }, \
346 { "no-mmx", MASK_MMX_SET, "" }, \
347 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
348 N_("Support 3DNow! built-in functions") }, \
349 { "no-3dnow", -MASK_3DNOW, "" }, \
350 { "no-3dnow", MASK_3DNOW_SET, \
351 N_("Do not support 3DNow! built-in functions") }, \
352 { "sse", MASK_SSE | MASK_SSE_SET, \
353 N_("Support MMX and SSE built-in functions and code generation") }, \
354 { "no-sse", -MASK_SSE, "" }, \
355 { "no-sse", MASK_SSE_SET, \
356 N_("Do not support MMX and SSE built-in functions and code generation") },\
357 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
358 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
359 { "no-sse2", -MASK_SSE2, "" }, \
360 { "no-sse2", MASK_SSE2_SET, \
361 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
362 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
363 N_("sizeof(long double) is 16") }, \
364 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
365 N_("sizeof(long double) is 12") }, \
366 { "64", MASK_64BIT, \
367 N_("Generate 64bit x86-64 code") }, \
368 { "32", -MASK_64BIT, \
369 N_("Generate 32bit i386 code") }, \
370 { "red-zone", -MASK_NO_RED_ZONE, \
371 N_("Use red-zone in the x86-64 code") }, \
372 { "no-red-zone", MASK_NO_RED_ZONE, \
373 N_("Do not use red-zone in the x86-64 code") }, \
375 { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }}
377 #ifndef TARGET_64BIT_DEFAULT
378 #define TARGET_64BIT_DEFAULT 0
381 /* Once GDB has been enhanced to deal with functions without frame
382 pointers, we can change this to allow for elimination of
383 the frame pointer in leaf functions. */
384 #define TARGET_DEFAULT 0
386 /* This macro is similar to `TARGET_SWITCHES' but defines names of
387 command options that have values. Its definition is an
388 initializer with a subgrouping for each command option.
390 Each subgrouping contains a string constant, that defines the
391 fixed part of the option name, and the address of a variable. The
392 variable, type `char *', is set to the variable part of the given
393 option if the fixed part matches. The actual option name is made
394 by appending `-m' to the specified name. */
395 #define TARGET_OPTIONS \
396 { { "cpu=", &ix86_cpu_string, \
397 N_("Schedule code for given CPU")}, \
398 { "fpmath=", &ix86_fpmath_string, \
399 N_("Generate floating point mathematics using given instruction set")},\
400 { "arch=", &ix86_arch_string, \
401 N_("Generate code for given CPU")}, \
402 { "regparm=", &ix86_regparm_string, \
403 N_("Number of registers used to pass integer arguments") }, \
404 { "align-loops=", &ix86_align_loops_string, \
405 N_("Loop code aligned to this power of 2") }, \
406 { "align-jumps=", &ix86_align_jumps_string, \
407 N_("Jump targets are aligned to this power of 2") }, \
408 { "align-functions=", &ix86_align_funcs_string, \
409 N_("Function starts are aligned to this power of 2") }, \
410 { "preferred-stack-boundary=", \
411 &ix86_preferred_stack_boundary_string, \
412 N_("Attempt to keep stack aligned to this power of 2") }, \
413 { "branch-cost=", &ix86_branch_cost_string, \
414 N_("Branches are this expensive (1-5, arbitrary units)") }, \
415 { "cmodel=", &ix86_cmodel_string, \
416 N_("Use given x86-64 code model") }, \
417 { "debug-arg", &ix86_debug_arg_string, \
418 "" /* Undocumented. */ }, \
419 { "debug-addr", &ix86_debug_addr_string, \
420 "" /* Undocumented. */ }, \
421 { "asm=", &ix86_asm_string, \
422 N_("Use given assembler dialect") }, \
423 { "tls-dialect=", &ix86_tls_dialect_string, \
424 N_("Use given thread-local storage dialect") }, \
428 /* Sometimes certain combinations of command options do not make
429 sense on a particular target machine. You can define a macro
430 `OVERRIDE_OPTIONS' to take account of this. This macro, if
431 defined, is executed once just after all the command options have
434 Don't use this macro to turn on various extra optimizations for
435 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
437 #define OVERRIDE_OPTIONS override_options ()
439 /* These are meant to be redefined in the host dependent files */
440 #define SUBTARGET_SWITCHES
441 #define SUBTARGET_OPTIONS
443 /* Define this to change the optimizations performed by default. */
444 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
445 optimization_options ((LEVEL), (SIZE))
447 /* Specs for the compiler proper */
450 #define CC1_CPU_SPEC "\
453 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
455 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
456 %{mpentium:-mcpu=pentium \
457 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
458 %{mpentiumpro:-mcpu=pentiumpro \
459 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
460 %{mintel-syntax:-masm=intel \
461 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
462 %{mno-intel-syntax:-masm=att \
463 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
466 /* Target CPU builtins. */
467 #define TARGET_CPU_CPP_BUILTINS() \
470 size_t arch_len = strlen (ix86_arch_string); \
471 size_t cpu_len = strlen (ix86_cpu_string); \
472 int last_arch_char = ix86_arch_string[arch_len - 1]; \
473 int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \
477 builtin_assert ("cpu=x86_64"); \
478 builtin_assert ("machine=x86_64"); \
479 builtin_define ("__x86_64"); \
480 builtin_define ("__x86_64__"); \
484 builtin_assert ("cpu=i386"); \
485 builtin_assert ("machine=i386"); \
486 builtin_define_std ("i386"); \
489 /* Built-ins based on -mcpu= (or -march= if no \
492 builtin_define ("__tune_i386__"); \
493 else if (TARGET_486) \
494 builtin_define ("__tune_i486__"); \
495 else if (TARGET_PENTIUM) \
497 builtin_define ("__tune_i586__"); \
498 builtin_define ("__tune_pentium__"); \
499 if (last_cpu_char == 'x') \
500 builtin_define ("__tune_pentium_mmx__"); \
502 else if (TARGET_PENTIUMPRO) \
504 builtin_define ("__tune_i686__"); \
505 builtin_define ("__tune_pentiumpro__"); \
507 else if (TARGET_K6) \
509 builtin_define ("__tune_k6__"); \
510 if (last_cpu_char == '2') \
511 builtin_define ("__tune_k6_2__"); \
512 else if (last_cpu_char == '3') \
513 builtin_define ("__tune_k6_3__"); \
515 else if (TARGET_ATHLON) \
517 builtin_define ("__tune_athlon__"); \
518 /* Only plain "athlon" lacks SSE. */ \
519 if (last_cpu_char != 'n') \
520 builtin_define ("__tune_athlon_sse__"); \
522 else if (TARGET_PENTIUM4) \
523 builtin_define ("__tune_pentium4__"); \
526 builtin_define ("__MMX__"); \
528 builtin_define ("__3dNOW__"); \
529 if (TARGET_3DNOW_A) \
530 builtin_define ("__3dNOW_A__"); \
532 builtin_define ("__SSE__"); \
534 builtin_define ("__SSE2__"); \
536 /* Built-ins based on -march=. */ \
537 if (ix86_arch == PROCESSOR_I486) \
539 builtin_define ("__i486"); \
540 builtin_define ("__i486__"); \
542 else if (ix86_arch == PROCESSOR_PENTIUM) \
544 builtin_define ("__i586"); \
545 builtin_define ("__i586__"); \
546 builtin_define ("__pentium"); \
547 builtin_define ("__pentium__"); \
548 if (last_arch_char == 'x') \
549 builtin_define ("__pentium_mmx__"); \
551 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
553 builtin_define ("__i686"); \
554 builtin_define ("__i686__"); \
555 builtin_define ("__pentiumpro"); \
556 builtin_define ("__pentiumpro__"); \
558 else if (ix86_arch == PROCESSOR_K6) \
561 builtin_define ("__k6"); \
562 builtin_define ("__k6__"); \
563 if (last_arch_char == '2') \
564 builtin_define ("__k6_2__"); \
565 else if (last_arch_char == '3') \
566 builtin_define ("__k6_3__"); \
568 else if (ix86_arch == PROCESSOR_ATHLON) \
570 builtin_define ("__athlon"); \
571 builtin_define ("__athlon__"); \
572 /* Only plain "athlon" lacks SSE. */ \
573 if (last_arch_char != 'n') \
574 builtin_define ("__athlon_sse__"); \
576 else if (ix86_arch == PROCESSOR_PENTIUM4) \
578 builtin_define ("__pentium4"); \
579 builtin_define ("__pentium4__"); \
584 #define TARGET_CPU_DEFAULT_i386 0
585 #define TARGET_CPU_DEFAULT_i486 1
586 #define TARGET_CPU_DEFAULT_pentium 2
587 #define TARGET_CPU_DEFAULT_pentium_mmx 3
588 #define TARGET_CPU_DEFAULT_pentiumpro 4
589 #define TARGET_CPU_DEFAULT_pentium2 5
590 #define TARGET_CPU_DEFAULT_pentium3 6
591 #define TARGET_CPU_DEFAULT_pentium4 7
592 #define TARGET_CPU_DEFAULT_k6 8
593 #define TARGET_CPU_DEFAULT_k6_2 9
594 #define TARGET_CPU_DEFAULT_k6_3 10
595 #define TARGET_CPU_DEFAULT_athlon 11
596 #define TARGET_CPU_DEFAULT_athlon_sse 12
598 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
599 "pentiumpro", "pentium2", "pentium3", \
600 "pentium4", "k6", "k6-2", "k6-3",\
601 "athlon", "athlon-4"}
604 #define CC1_SPEC "%(cc1_cpu) "
607 /* This macro defines names of additional specifications to put in the
608 specs that can be used in various specifications like CC1_SPEC. Its
609 definition is an initializer with a subgrouping for each command option.
611 Each subgrouping contains a string constant, that defines the
612 specification name, and a string constant that used by the GNU CC driver
615 Do not define this macro if it does not need to do anything. */
617 #ifndef SUBTARGET_EXTRA_SPECS
618 #define SUBTARGET_EXTRA_SPECS
621 #define EXTRA_SPECS \
622 { "cc1_cpu", CC1_CPU_SPEC }, \
623 SUBTARGET_EXTRA_SPECS
625 /* target machine storage layout */
627 /* Define for XFmode or TFmode extended real floating point support.
628 The XFmode is specified by i386 ABI, while TFmode may be faster
629 due to alignment and simplifications in the address calculations.
631 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
632 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
634 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
636 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
638 /* Tell real.c that this is the 80-bit Intel extended float format
639 packaged in a 128-bit or 96bit entity. */
640 #define INTEL_EXTENDED_IEEE_FORMAT 1
643 #define SHORT_TYPE_SIZE 16
644 #define INT_TYPE_SIZE 32
645 #define FLOAT_TYPE_SIZE 32
646 #define LONG_TYPE_SIZE BITS_PER_WORD
647 #define MAX_WCHAR_TYPE_SIZE 32
648 #define DOUBLE_TYPE_SIZE 64
649 #define LONG_LONG_TYPE_SIZE 64
651 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
652 #define MAX_BITS_PER_WORD 64
653 #define MAX_LONG_TYPE_SIZE 64
655 #define MAX_BITS_PER_WORD 32
656 #define MAX_LONG_TYPE_SIZE 32
659 /* Define this if most significant byte of a word is the lowest numbered. */
660 /* That is true on the 80386. */
662 #define BITS_BIG_ENDIAN 0
664 /* Define this if most significant byte of a word is the lowest numbered. */
665 /* That is not true on the 80386. */
666 #define BYTES_BIG_ENDIAN 0
668 /* Define this if most significant word of a multiword number is the lowest
670 /* Not true for 80386 */
671 #define WORDS_BIG_ENDIAN 0
673 /* Width of a word, in units (bytes). */
674 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
675 #define MIN_UNITS_PER_WORD 4
677 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
678 #define PARM_BOUNDARY BITS_PER_WORD
680 /* Boundary (in *bits*) on which stack pointer should be aligned. */
681 #define STACK_BOUNDARY BITS_PER_WORD
683 /* Boundary (in *bits*) on which the stack pointer preferrs to be
684 aligned; the compiler cannot rely on having this alignment. */
685 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
687 /* As of July 2001, many runtimes to not align the stack properly when
688 entering main. This causes expand_main_function to forcably align
689 the stack, which results in aligned frames for functions called from
690 main, though it does nothing for the alignment of main itself. */
691 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
692 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
694 /* Allocation boundary for the code of a function. */
695 #define FUNCTION_BOUNDARY 16
697 /* Alignment of field after `int : 0' in a structure. */
699 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
701 /* Minimum size in bits of the largest boundary to which any
702 and all fundamental data types supported by the hardware
703 might need to be aligned. No data type wants to be aligned
706 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
707 and Pentium Pro XFmode values at 128 bit boundaries. */
709 #define BIGGEST_ALIGNMENT 128
711 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
712 #define ALIGN_MODE_128(MODE) \
713 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
714 || (MODE) == V4SFmode || (MODE) == V4SImode)
716 /* The published ABIs say that doubles should be aligned on word
717 boundaries, so lower the aligment for structure fields unless
718 -malign-double is set. */
720 /* ??? Blah -- this macro is used directly by libobjc. Since it
721 supports no vector modes, cut out the complexity and fall back
722 on BIGGEST_FIELD_ALIGNMENT. */
723 #ifdef IN_TARGET_LIBS
724 #define BIGGEST_FIELD_ALIGNMENT 32
726 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
727 x86_field_alignment (FIELD, COMPUTED)
730 /* If defined, a C expression to compute the alignment given to a
731 constant that is being placed in memory. EXP is the constant
732 and ALIGN is the alignment that the object would ordinarily have.
733 The value of this macro is used instead of that alignment to align
736 If this macro is not defined, then ALIGN is used.
738 The typical use of this macro is to increase alignment for string
739 constants to be word aligned so that `strcpy' calls that copy
740 constants can be done inline. */
742 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
744 /* If defined, a C expression to compute the alignment for a static
745 variable. TYPE is the data type, and ALIGN is the alignment that
746 the object would ordinarily have. The value of this macro is used
747 instead of that alignment to align the object.
749 If this macro is not defined, then ALIGN is used.
751 One use of this macro is to increase alignment of medium-size
752 data to make it all fit in fewer cache lines. Another is to
753 cause character arrays to be word-aligned so that `strcpy' calls
754 that copy constants to character arrays can be done inline. */
756 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
758 /* If defined, a C expression to compute the alignment for a local
759 variable. TYPE is the data type, and ALIGN is the alignment that
760 the object would ordinarily have. The value of this macro is used
761 instead of that alignment to align the object.
763 If this macro is not defined, then ALIGN is used.
765 One use of this macro is to increase alignment of medium-size
766 data to make it all fit in fewer cache lines. */
768 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
770 /* If defined, a C expression that gives the alignment boundary, in
771 bits, of an argument with the specified mode and type. If it is
772 not defined, `PARM_BOUNDARY' is used for all arguments. */
774 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
775 ix86_function_arg_boundary ((MODE), (TYPE))
777 /* Set this non-zero if move instructions will actually fail to work
778 when given unaligned data. */
779 #define STRICT_ALIGNMENT 0
781 /* If bit field type is int, don't let it cross an int,
782 and give entire struct the alignment of an int. */
783 /* Required on the 386 since it doesn't have bitfield insns. */
784 #define PCC_BITFIELD_TYPE_MATTERS 1
786 /* Standard register usage. */
788 /* This processor has special stack-like registers. See reg-stack.c
792 #define IS_STACK_MODE(MODE) \
793 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
796 /* Number of actual hardware registers.
797 The hardware registers are assigned numbers for the compiler
798 from 0 to just below FIRST_PSEUDO_REGISTER.
799 All registers that the compiler knows about must be given numbers,
800 even those that are not normally considered general registers.
802 In the 80386 we give the 8 general purpose registers the numbers 0-7.
803 We number the floating point registers 8-15.
804 Note that registers 0-7 can be accessed as a short or int,
805 while only 0-3 may be used with byte `mov' instructions.
807 Reg 16 does not correspond to any hardware register, but instead
808 appears in the RTL as an argument pointer prior to reload, and is
809 eliminated during reloading in favor of either the stack or frame
812 #define FIRST_PSEUDO_REGISTER 53
814 /* Number of hardware registers that go into the DWARF-2 unwind info.
815 If not defined, equals FIRST_PSEUDO_REGISTER. */
817 #define DWARF_FRAME_REGISTERS 17
819 /* 1 for registers that have pervasive standard uses
820 and are not available for the register allocator.
821 On the 80386, the stack pointer is such, as is the arg pointer.
823 The value is an mask - bit 1 is set for fixed registers
824 for 32bit target, while 2 is set for fixed registers for 64bit.
825 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
827 #define FIXED_REGISTERS \
828 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
829 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
830 /*arg,flags,fpsr,dir,frame*/ \
832 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
833 0, 0, 0, 0, 0, 0, 0, 0, \
834 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
835 0, 0, 0, 0, 0, 0, 0, 0, \
836 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
837 1, 1, 1, 1, 1, 1, 1, 1, \
838 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
839 1, 1, 1, 1, 1, 1, 1, 1}
842 /* 1 for registers not available across function calls.
843 These must include the FIXED_REGISTERS and also any
844 registers that can be used without being saved.
845 The latter must include the registers where values are returned
846 and the register where structure-value addresses are passed.
847 Aside from that, you can include as many other registers as you like.
849 The value is an mask - bit 1 is set for call used
850 for 32bit target, while 2 is set for call used for 64bit.
851 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
853 #define CALL_USED_REGISTERS \
854 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
855 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
856 /*arg,flags,fpsr,dir,frame*/ \
858 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
859 3, 3, 3, 3, 3, 3, 3, 3, \
860 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
861 3, 3, 3, 3, 3, 3, 3, 3, \
862 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
863 3, 3, 3, 3, 1, 1, 1, 1, \
864 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
865 3, 3, 3, 3, 3, 3, 3, 3} \
867 /* Order in which to allocate registers. Each register must be
868 listed once, even those in FIXED_REGISTERS. List frame pointer
869 late and fixed registers last. Note that, in general, we prefer
870 registers listed in CALL_USED_REGISTERS, keeping the others
871 available for storage of persistent values.
873 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
874 so this is just empty initializer for array. */
876 #define REG_ALLOC_ORDER \
877 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
878 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
879 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
882 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
883 to be rearranged based on a particular function. When using sse math,
884 we want to allocase SSE before x87 registers and vice vera. */
886 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
889 /* Macro to conditionally modify fixed_regs/call_used_regs. */
890 #define CONDITIONAL_REGISTER_USAGE \
893 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
895 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
896 call_used_regs[i] = (call_used_regs[i] \
897 & (TARGET_64BIT ? 2 : 1)) != 0; \
899 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
901 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
902 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
907 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
908 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
909 fixed_regs[i] = call_used_regs[i] = 1; \
914 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
915 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
916 fixed_regs[i] = call_used_regs[i] = 1; \
918 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
922 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
923 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
924 if (TEST_HARD_REG_BIT (x, i)) \
925 fixed_regs[i] = call_used_regs[i] = 1; \
929 /* Return number of consecutive hard regs needed starting at reg REGNO
930 to hold something of mode MODE.
931 This is ordinarily the length in words of a value of mode MODE
932 but can be less for certain modes in special long registers.
934 Actually there are no two word move instructions for consecutive
935 registers. And only registers 0-3 may have mov byte instructions
939 #define HARD_REGNO_NREGS(REGNO, MODE) \
940 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
941 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
942 : ((MODE) == TFmode \
943 ? (TARGET_64BIT ? 2 : 3) \
945 ? (TARGET_64BIT ? 4 : 6) \
946 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
948 #define VALID_SSE2_REG_MODE(MODE) \
949 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
950 || (MODE) == V2DImode)
952 #define VALID_SSE_REG_MODE(MODE) \
953 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
954 || (MODE) == SFmode \
955 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
956 || VALID_SSE2_REG_MODE (MODE) \
957 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
959 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
960 ((MODE) == V2SFmode || (MODE) == SFmode)
962 #define VALID_MMX_REG_MODE(MODE) \
963 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
964 || (MODE) == V2SImode || (MODE) == SImode)
966 #define VECTOR_MODE_SUPPORTED_P(MODE) \
967 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
968 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
969 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
971 #define VALID_FP_MODE_P(MODE) \
972 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
973 || (!TARGET_64BIT && (MODE) == XFmode) \
974 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
975 || (!TARGET_64BIT && (MODE) == XCmode))
977 #define VALID_INT_MODE_P(MODE) \
978 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
979 || (MODE) == DImode \
980 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
981 || (MODE) == CDImode \
982 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
984 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
986 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
987 ix86_hard_regno_mode_ok ((REGNO), (MODE))
989 /* Value is 1 if it is a good idea to tie two pseudo registers
990 when one has mode MODE1 and one has mode MODE2.
991 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
992 for any hard reg, then this must be 0 for correct output. */
994 #define MODES_TIEABLE_P(MODE1, MODE2) \
995 ((MODE1) == (MODE2) \
996 || (((MODE1) == HImode || (MODE1) == SImode \
997 || ((MODE1) == QImode \
998 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
999 || ((MODE1) == DImode && TARGET_64BIT)) \
1000 && ((MODE2) == HImode || (MODE2) == SImode \
1001 || ((MODE1) == QImode \
1002 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1003 || ((MODE2) == DImode && TARGET_64BIT))))
1006 /* Specify the modes required to caller save a given hard regno.
1007 We do this on i386 to prevent flags from being saved at all.
1009 Kill any attempts to combine saving of modes. */
1011 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1012 (CC_REGNO_P (REGNO) ? VOIDmode \
1013 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1014 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1015 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1016 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1018 /* Specify the registers used for certain standard purposes.
1019 The values of these macros are register numbers. */
1021 /* on the 386 the pc register is %eip, and is not usable as a general
1022 register. The ordinary mov instructions won't work */
1023 /* #define PC_REGNUM */
1025 /* Register to use for pushing function arguments. */
1026 #define STACK_POINTER_REGNUM 7
1028 /* Base register for access to local variables of the function. */
1029 #define HARD_FRAME_POINTER_REGNUM 6
1031 /* Base register for access to local variables of the function. */
1032 #define FRAME_POINTER_REGNUM 20
1034 /* First floating point reg */
1035 #define FIRST_FLOAT_REG 8
1037 /* First & last stack-like regs */
1038 #define FIRST_STACK_REG FIRST_FLOAT_REG
1039 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1041 #define FLAGS_REG 17
1043 #define DIRFLAG_REG 19
1045 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1046 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1048 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1049 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1051 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1052 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1054 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1055 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1057 /* Value should be nonzero if functions must have frame pointers.
1058 Zero means the frame pointer need not be set up (and parms
1059 may be accessed via the stack pointer) in functions that seem suitable.
1060 This is computed in `reload', in reload1.c. */
1061 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1063 /* Override this in other tm.h files to cope with various OS losage
1064 requiring a frame pointer. */
1065 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1066 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1069 /* Make sure we can access arbitrary call frames. */
1070 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1072 /* Base register for access to arguments of the function. */
1073 #define ARG_POINTER_REGNUM 16
1075 /* Register in which static-chain is passed to a function.
1076 We do use ECX as static chain register for 32 bit ABI. On the
1077 64bit ABI, ECX is an argument register, so we use R10 instead. */
1078 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1080 /* Register to hold the addressing base for position independent
1081 code access to data items. We don't use PIC pointer for 64bit
1082 mode. Define the regnum to dummy value to prevent gcc from
1083 pessimizing code dealing with EBX.
1085 To avoid clobbering a call-saved register unnecessarily, we renumber
1086 the pic register when possible. The change is visible after the
1087 prologue has been emitted. */
1089 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1091 #define PIC_OFFSET_TABLE_REGNUM \
1092 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1093 : reload_completed ? REGNO (pic_offset_table_rtx) \
1094 : REAL_PIC_OFFSET_TABLE_REGNUM)
1096 /* Register in which address to store a structure value
1097 arrives in the function. On the 386, the prologue
1098 copies this from the stack to register %eax. */
1099 #define STRUCT_VALUE_INCOMING 0
1101 /* Place in which caller passes the structure value address.
1102 0 means push the value on the stack like an argument. */
1103 #define STRUCT_VALUE 0
1105 /* A C expression which can inhibit the returning of certain function
1106 values in registers, based on the type of value. A nonzero value
1107 says to return the function value in memory, just as large
1108 structures are always returned. Here TYPE will be a C expression
1109 of type `tree', representing the data type of the value.
1111 Note that values of mode `BLKmode' must be explicitly handled by
1112 this macro. Also, the option `-fpcc-struct-return' takes effect
1113 regardless of this macro. On most systems, it is possible to
1114 leave the macro undefined; this causes a default definition to be
1115 used, whose value is the constant 1 for `BLKmode' values, and 0
1118 Do not use this macro to indicate that structures and unions
1119 should always be returned in memory. You should instead use
1120 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1122 #define RETURN_IN_MEMORY(TYPE) \
1123 ix86_return_in_memory (TYPE)
1126 /* Define the classes of registers for register constraints in the
1127 machine description. Also define ranges of constants.
1129 One of the classes must always be named ALL_REGS and include all hard regs.
1130 If there is more than one class, another class must be named NO_REGS
1131 and contain no registers.
1133 The name GENERAL_REGS must be the name of a class (or an alias for
1134 another name such as ALL_REGS). This is the class of registers
1135 that is allowed by "g" or "r" in a register constraint.
1136 Also, registers outside this class are allocated only when
1137 instructions express preferences for them.
1139 The classes must be numbered in nondecreasing order; that is,
1140 a larger-numbered class must never be contained completely
1141 in a smaller-numbered class.
1143 For any two classes, it is very desirable that there be another
1144 class that represents their union.
1146 It might seem that class BREG is unnecessary, since no useful 386
1147 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1148 and the "b" register constraint is useful in asms for syscalls.
1150 The flags and fpsr registers are in no class. */
1155 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
1156 AD_REGS
, /* %eax/%edx for DImode */
1157 Q_REGS
, /* %eax %ebx %ecx %edx */
1158 NON_Q_REGS
, /* %esi %edi %ebp %esp */
1159 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1160 LEGACY_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1161 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1162 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
1172 ALL_REGS
, LIM_REG_CLASSES
1175 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1177 #define INTEGER_CLASS_P(CLASS) \
1178 reg_class_subset_p ((CLASS), GENERAL_REGS)
1179 #define FLOAT_CLASS_P(CLASS) \
1180 reg_class_subset_p ((CLASS), FLOAT_REGS)
1181 #define SSE_CLASS_P(CLASS) \
1182 reg_class_subset_p ((CLASS), SSE_REGS)
1183 #define MMX_CLASS_P(CLASS) \
1184 reg_class_subset_p ((CLASS), MMX_REGS)
1185 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1186 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1187 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1188 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1189 #define MAYBE_SSE_CLASS_P(CLASS) \
1190 reg_classes_intersect_p (SSE_REGS, (CLASS))
1191 #define MAYBE_MMX_CLASS_P(CLASS) \
1192 reg_classes_intersect_p (MMX_REGS, (CLASS))
1194 #define Q_CLASS_P(CLASS) \
1195 reg_class_subset_p ((CLASS), Q_REGS)
1197 /* Give names of register classes as strings for dump file. */
1199 #define REG_CLASS_NAMES \
1201 "AREG", "DREG", "CREG", "BREG", \
1204 "Q_REGS", "NON_Q_REGS", \
1208 "FP_TOP_REG", "FP_SECOND_REG", \
1212 "FP_TOP_SSE_REGS", \
1213 "FP_SECOND_SSE_REGS", \
1217 "FLOAT_INT_SSE_REGS", \
1220 /* Define which registers fit in which classes.
1221 This is an initializer for a vector of HARD_REG_SET
1222 of length N_REG_CLASSES. */
1224 #define REG_CLASS_CONTENTS \
1226 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1227 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1228 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1229 { 0x03, 0x0 }, /* AD_REGS */ \
1230 { 0x0f, 0x0 }, /* Q_REGS */ \
1231 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1232 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1233 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1234 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1235 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1236 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1237 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1238 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1239 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1240 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1241 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1242 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1243 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1244 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1245 { 0xffffffff,0x1fffff } \
1248 /* The same information, inverted:
1249 Return the class number of the smallest class containing
1250 reg number REGNO. This could be a conditional expression
1251 or could index an array. */
1253 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1255 /* When defined, the compiler allows registers explicitly used in the
1256 rtl to be used as spill registers but prevents the compiler from
1257 extending the lifetime of these registers. */
1259 #define SMALL_REGISTER_CLASSES 1
1261 #define QI_REG_P(X) \
1262 (REG_P (X) && REGNO (X) < 4)
1264 #define GENERAL_REGNO_P(N) \
1265 ((N) < 8 || REX_INT_REGNO_P (N))
1267 #define GENERAL_REG_P(X) \
1268 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1270 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1272 #define NON_QI_REG_P(X) \
1273 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1275 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1276 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1278 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1279 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1280 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1281 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1283 #define SSE_REGNO_P(N) \
1284 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1285 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1287 #define SSE_REGNO(N) \
1288 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1289 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1291 #define SSE_FLOAT_MODE_P(MODE) \
1292 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1294 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1295 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1297 #define STACK_REG_P(XOP) \
1299 REGNO (XOP) >= FIRST_STACK_REG && \
1300 REGNO (XOP) <= LAST_STACK_REG)
1302 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1304 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1306 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1307 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1309 /* Indicate whether hard register numbered REG_NO should be converted
1311 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1312 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1314 /* The class value for index registers, and the one for base regs. */
1316 #define INDEX_REG_CLASS INDEX_REGS
1317 #define BASE_REG_CLASS GENERAL_REGS
1319 /* Get reg_class from a letter such as appears in the machine description. */
1321 #define REG_CLASS_FROM_LETTER(C) \
1322 ((C) == 'r' ? GENERAL_REGS : \
1323 (C) == 'R' ? LEGACY_REGS : \
1324 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1325 (C) == 'Q' ? Q_REGS : \
1326 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1329 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1332 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1335 (C) == 'a' ? AREG : \
1336 (C) == 'b' ? BREG : \
1337 (C) == 'c' ? CREG : \
1338 (C) == 'd' ? DREG : \
1339 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1340 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1341 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1342 (C) == 'A' ? AD_REGS : \
1343 (C) == 'D' ? DIREG : \
1344 (C) == 'S' ? SIREG : NO_REGS)
1346 /* The letters I, J, K, L and M in a register constraint string
1347 can be used to stand for particular ranges of immediate operands.
1348 This macro defines what the ranges are.
1349 C is the letter, and VALUE is a constant value.
1350 Return 1 if VALUE is in the range specified by C.
1352 I is for non-DImode shifts.
1353 J is for DImode shifts.
1354 K is for signed imm8 operands.
1355 L is for andsi as zero-extending move.
1356 M is for shifts that can be executed by the "lea" opcode.
1357 N is for immedaite operands for out/in instructions (0-255)
1360 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1361 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1362 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1363 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1364 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1365 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1366 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1369 /* Similar, but for floating constants, and defining letters G and H.
1370 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1371 TARGET_387 isn't set, because the stack register converter may need to
1372 load 0.0 into the function value register. */
1374 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1375 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1376 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1378 /* A C expression that defines the optional machine-dependent
1379 constraint letters that can be used to segregate specific types of
1380 operands, usually memory references, for the target machine. Any
1381 letter that is not elsewhere defined and not matched by
1382 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1385 If it is required for a particular target machine, it should
1386 return 1 if VALUE corresponds to the operand type represented by
1387 the constraint letter C. If C is not defined as an extra
1388 constraint, the value returned should be 0 regardless of VALUE. */
1390 #define EXTRA_CONSTRAINT(VALUE, C) \
1391 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1392 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1395 /* Place additional restrictions on the register class to use when it
1396 is necessary to be able to hold a value of mode MODE in a reload
1397 register for which class CLASS would ordinarily be used. */
1399 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1400 ((MODE) == QImode && !TARGET_64BIT \
1401 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1402 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1405 /* Given an rtx X being reloaded into a reg required to be
1406 in class CLASS, return the class of reg to actually use.
1407 In general this is just CLASS; but on some machines
1408 in some cases it is preferable to use a more restrictive class.
1409 On the 80386 series, we prevent floating constants from being
1410 reloaded into floating registers (since no move-insn can do that)
1411 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1413 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1414 QImode must go into class Q_REGS.
1415 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1416 movdf to do mem-to-mem moves through integer regs. */
1418 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1419 ix86_preferred_reload_class ((X), (CLASS))
1421 /* If we are copying between general and FP registers, we need a memory
1422 location. The same is true for SSE and MMX registers. */
1423 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1424 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1426 /* QImode spills from non-QI registers need a scratch. This does not
1427 happen often -- the only example so far requires an uninitialized
1430 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1431 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1432 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1435 /* Return the maximum number of consecutive registers
1436 needed to represent mode MODE in a register of class CLASS. */
1437 /* On the 80386, this is the size of MODE in words,
1438 except in the FP regs, where a single reg is always enough.
1439 The TFmodes are really just 80bit values, so we use only 3 registers
1440 to hold them, instead of 4, as the size would suggest.
1442 #define CLASS_MAX_NREGS(CLASS, MODE) \
1443 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1444 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1445 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1446 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1448 /* A C expression whose value is nonzero if pseudos that have been
1449 assigned to registers of class CLASS would likely be spilled
1450 because registers of CLASS are needed for spill registers.
1452 The default value of this macro returns 1 if CLASS has exactly one
1453 register and zero otherwise. On most machines, this default
1454 should be used. Only define this macro to some other expression
1455 if pseudo allocated by `local-alloc.c' end up in memory because
1456 their hard registers were needed for spill registers. If this
1457 macro returns nonzero for those classes, those pseudos will only
1458 be allocated by `global.c', which knows how to reallocate the
1459 pseudo to another register. If there would not be another
1460 register available for reallocation, you should not change the
1461 definition of this macro since the only effect of such a
1462 definition would be to slow down register allocation. */
1464 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1465 (((CLASS) == AREG) \
1466 || ((CLASS) == DREG) \
1467 || ((CLASS) == CREG) \
1468 || ((CLASS) == BREG) \
1469 || ((CLASS) == AD_REGS) \
1470 || ((CLASS) == SIREG) \
1471 || ((CLASS) == DIREG))
1473 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1474 to automatically clobber for all asms.
1476 We do this in the new i386 backend to maintain source compatibility
1477 with the old cc0-based compiler. */
1479 #define MD_ASM_CLOBBERS(CLOBBERS) \
1481 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1483 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1485 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1489 /* Stack layout; function entry, exit and calling. */
1491 /* Define this if pushing a word on the stack
1492 makes the stack pointer a smaller address. */
1493 #define STACK_GROWS_DOWNWARD
1495 /* Define this if the nominal address of the stack frame
1496 is at the high-address end of the local variables;
1497 that is, each additional local variable allocated
1498 goes at a more negative offset in the frame. */
1499 #define FRAME_GROWS_DOWNWARD
1501 /* Offset within stack frame to start allocating local variables at.
1502 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1503 first local allocated. Otherwise, it is the offset to the BEGINNING
1504 of the first local allocated. */
1505 #define STARTING_FRAME_OFFSET 0
1507 /* If we generate an insn to push BYTES bytes,
1508 this says how many the stack pointer really advances by.
1509 On 386 pushw decrements by exactly 2 no matter what the position was.
1510 On the 386 there is no pushb; we use pushw instead, and this
1511 has the effect of rounding up to 2.
1513 For 64bit ABI we round up to 8 bytes.
1516 #define PUSH_ROUNDING(BYTES) \
1518 ? (((BYTES) + 7) & (-8)) \
1519 : (((BYTES) + 1) & (-2)))
1521 /* If defined, the maximum amount of space required for outgoing arguments will
1522 be computed and placed into the variable
1523 `current_function_outgoing_args_size'. No space will be pushed onto the
1524 stack for each call; instead, the function prologue should increase the stack
1525 frame size by this amount. */
1527 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1529 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1530 instructions to pass outgoing arguments. */
1532 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1534 /* Offset of first parameter from the argument pointer register value. */
1535 #define FIRST_PARM_OFFSET(FNDECL) 0
1537 /* Define this macro if functions should assume that stack space has been
1538 allocated for arguments even when their values are passed in registers.
1540 The value of this macro is the size, in bytes, of the area reserved for
1541 arguments passed in registers for the function represented by FNDECL.
1543 This space can be allocated by the caller, or be a part of the
1544 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1546 #define REG_PARM_STACK_SPACE(FNDECL) 0
1548 /* Define as a C expression that evaluates to nonzero if we do not know how
1549 to pass TYPE solely in registers. The file expr.h defines a
1550 definition that is usually appropriate, refer to expr.h for additional
1551 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1552 computed in the stack and then loaded into a register. */
1553 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1555 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1556 || TREE_ADDRESSABLE (TYPE) \
1557 || ((MODE) == TImode) \
1558 || ((MODE) == BLKmode \
1560 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1561 && 0 == (int_size_in_bytes (TYPE) \
1562 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1563 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1564 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1566 /* Value is the number of bytes of arguments automatically
1567 popped when returning from a subroutine call.
1568 FUNDECL is the declaration node of the function (as a tree),
1569 FUNTYPE is the data type of the function (as a tree),
1570 or for a library call it is an identifier node for the subroutine name.
1571 SIZE is the number of bytes of arguments passed on the stack.
1573 On the 80386, the RTD insn may be used to pop them if the number
1574 of args is fixed, but if the number is variable then the caller
1575 must pop them all. RTD can't be used for library calls now
1576 because the library is compiled with the Unix compiler.
1577 Use of RTD is a selectable option, since it is incompatible with
1578 standard Unix calling sequences. If the option is not selected,
1579 the caller must always pop the args.
1581 The attribute stdcall is equivalent to RTD on a per module basis. */
1583 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1584 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1586 /* Define how to find the value returned by a function.
1587 VALTYPE is the data type of the value (as a tree).
1588 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1589 otherwise, FUNC is 0. */
1590 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1591 ix86_function_value (VALTYPE)
1593 #define FUNCTION_VALUE_REGNO_P(N) \
1594 ix86_function_value_regno_p (N)
1596 /* Define how to find the value returned by a library function
1597 assuming the value has mode MODE. */
1599 #define LIBCALL_VALUE(MODE) \
1600 ix86_libcall_value (MODE)
1602 /* Define the size of the result block used for communication between
1603 untyped_call and untyped_return. The block contains a DImode value
1604 followed by the block used by fnsave and frstor. */
1606 #define APPLY_RESULT_SIZE (8+108)
1608 /* 1 if N is a possible register number for function argument passing. */
1609 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1611 /* Define a data type for recording info about an argument list
1612 during the scan of that argument list. This data type should
1613 hold all necessary information about the function itself
1614 and about the args processed so far, enough to enable macros
1615 such as FUNCTION_ARG to determine where the next arg should go. */
1617 typedef struct ix86_args
{
1618 int words
; /* # words passed so far */
1619 int nregs
; /* # registers available for passing */
1620 int regno
; /* next available register number */
1621 int sse_words
; /* # sse words passed so far */
1622 int sse_nregs
; /* # sse registers available for passing */
1623 int sse_regno
; /* next available sse register number */
1624 int maybe_vaarg
; /* true for calls to possibly vardic fncts. */
1627 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1628 for a call to a function whose data type is FNTYPE.
1629 For a library call, FNTYPE is 0. */
1631 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1632 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1634 /* Update the data in CUM to advance over an argument
1635 of mode MODE and data type TYPE.
1636 (TYPE is null for libcalls where that information may not be available.) */
1638 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1639 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1641 /* Define where to put the arguments to a function.
1642 Value is zero to push the argument on the stack,
1643 or a hard register in which to store the argument.
1645 MODE is the argument's machine mode.
1646 TYPE is the data type of the argument (as a tree).
1647 This is null for libcalls where that information may
1649 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1650 the preceding args and about the function being called.
1651 NAMED is nonzero if this argument is a named parameter
1652 (otherwise it is an extra parameter matching an ellipsis). */
1654 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1655 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1657 /* For an arg passed partly in registers and partly in memory,
1658 this is the number of registers used.
1659 For args passed entirely in registers or entirely in memory, zero. */
1661 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1663 /* If PIC, we cannot make sibling calls to global functions
1664 because the PLT requires %ebx live.
1665 If we are returning floats on the register stack, we cannot make
1666 sibling calls to functions that return floats. (The stack adjust
1667 instruction will wind up after the sibcall jump, and not be executed.) */
1668 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1670 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1671 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1672 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1673 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1675 /* Perform any needed actions needed for a function that is receiving a
1676 variable number of arguments.
1680 MODE and TYPE are the mode and type of the current parameter.
1682 PRETEND_SIZE is a variable that should be set to the amount of stack
1683 that must be pushed by the prolog to pretend that our caller pushed
1686 Normally, this macro will push all remaining incoming registers on the
1687 stack and set PRETEND_SIZE to the length of the registers pushed. */
1689 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1690 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1693 /* Define the `__builtin_va_list' type for the ABI. */
1694 #define BUILD_VA_LIST_TYPE(VALIST) \
1695 ((VALIST) = ix86_build_va_list ())
1697 /* Implement `va_start' for varargs and stdarg. */
1698 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1699 ix86_va_start (VALIST, NEXTARG)
1701 /* Implement `va_arg'. */
1702 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1703 ix86_va_arg ((VALIST), (TYPE))
1705 /* This macro is invoked at the end of compilation. It is used here to
1706 output code for -fpic that will load the return address into %ebx. */
1709 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1711 /* Output assembler code to FILE to increment profiler label # LABELNO
1712 for profiling a function entry. */
1714 #define FUNCTION_PROFILER(FILE, LABELNO) \
1718 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1719 LPREFIX, (LABELNO)); \
1720 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1724 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1725 fprintf ((FILE), "\tcall\t_mcount\n"); \
1729 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1730 the stack pointer does not matter. The value is tested only in
1731 functions that have frame pointers.
1732 No definition is equivalent to always zero. */
1733 /* Note on the 386 it might be more efficient not to define this since
1734 we have to restore it ourselves from the frame pointer, in order to
1737 #define EXIT_IGNORE_STACK 1
1739 /* Output assembler code for a block containing the constant parts
1740 of a trampoline, leaving space for the variable parts. */
1742 /* On the 386, the trampoline contains two instructions:
1745 The trampoline is generated entirely at runtime. The operand of JMP
1746 is the address of FUNCTION relative to the instruction following the
1747 JMP (which is 5 bytes long). */
1749 /* Length in units of the trampoline for entering a nested function. */
1751 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1753 /* Emit RTL insns to initialize the variable parts of a trampoline.
1754 FNADDR is an RTX for the address of the function's pure code.
1755 CXT is an RTX for the static chain value for the function. */
1757 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1758 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1760 /* Definitions for register eliminations.
1762 This is an array of structures. Each structure initializes one pair
1763 of eliminable registers. The "from" register number is given first,
1764 followed by "to". Eliminations of the same "from" register are listed
1765 in order of preference.
1767 There are two registers that can always be eliminated on the i386.
1768 The frame pointer and the arg pointer can be replaced by either the
1769 hard frame pointer or to the stack pointer, depending upon the
1770 circumstances. The hard frame pointer is not used before reload and
1771 so it is not eligible for elimination. */
1773 #define ELIMINABLE_REGS \
1774 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1775 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1776 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1777 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1779 /* Given FROM and TO register numbers, say whether this elimination is
1780 allowed. Frame pointer elimination is automatically handled.
1782 All other eliminations are valid. */
1784 #define CAN_ELIMINATE(FROM, TO) \
1785 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1787 /* Define the offset between two registers, one to be eliminated, and the other
1788 its replacement, at the start of a routine. */
1790 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1791 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1793 /* Addressing modes, and classification of registers for them. */
1795 /* #define HAVE_POST_INCREMENT 0 */
1796 /* #define HAVE_POST_DECREMENT 0 */
1798 /* #define HAVE_PRE_DECREMENT 0 */
1799 /* #define HAVE_PRE_INCREMENT 0 */
1801 /* Macros to check register numbers against specific register classes. */
1803 /* These assume that REGNO is a hard or pseudo reg number.
1804 They give nonzero only if REGNO is a hard reg of the suitable class
1805 or a pseudo reg currently allocated to a suitable hard reg.
1806 Since they use reg_renumber, they are safe only once reg_renumber
1807 has been allocated, which happens in local-alloc.c. */
1809 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1810 ((REGNO) < STACK_POINTER_REGNUM \
1811 || (REGNO >= FIRST_REX_INT_REG \
1812 && (REGNO) <= LAST_REX_INT_REG) \
1813 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1814 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1815 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1817 #define REGNO_OK_FOR_BASE_P(REGNO) \
1818 ((REGNO) <= STACK_POINTER_REGNUM \
1819 || (REGNO) == ARG_POINTER_REGNUM \
1820 || (REGNO) == FRAME_POINTER_REGNUM \
1821 || (REGNO >= FIRST_REX_INT_REG \
1822 && (REGNO) <= LAST_REX_INT_REG) \
1823 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1824 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1825 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1827 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1828 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1829 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1830 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1832 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1833 and check its validity for a certain class.
1834 We have two alternate definitions for each of them.
1835 The usual definition accepts all pseudo regs; the other rejects
1836 them unless they have been allocated suitable hard regs.
1837 The symbol REG_OK_STRICT causes the latter definition to be used.
1839 Most source files want to accept pseudo regs in the hope that
1840 they will get allocated to the class that the insn wants them to be in.
1841 Source files for reload pass need to be strict.
1842 After reload, it makes no difference, since pseudo regs have
1843 been eliminated by then. */
1846 /* Non strict versions, pseudos are ok */
1847 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1848 (REGNO (X) < STACK_POINTER_REGNUM \
1849 || (REGNO (X) >= FIRST_REX_INT_REG \
1850 && REGNO (X) <= LAST_REX_INT_REG) \
1851 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1853 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1854 (REGNO (X) <= STACK_POINTER_REGNUM \
1855 || REGNO (X) == ARG_POINTER_REGNUM \
1856 || REGNO (X) == FRAME_POINTER_REGNUM \
1857 || (REGNO (X) >= FIRST_REX_INT_REG \
1858 && REGNO (X) <= LAST_REX_INT_REG) \
1859 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1861 /* Strict versions, hard registers only */
1862 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1863 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1865 #ifndef REG_OK_STRICT
1866 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1867 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1870 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1871 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1874 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1875 that is a valid memory address for an instruction.
1876 The MODE argument is the machine mode for the MEM expression
1877 that wants to use this address.
1879 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1880 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1882 See legitimize_pic_address in i386.c for details as to what
1883 constitutes a legitimate address when -fpic is used. */
1885 #define MAX_REGS_PER_ADDRESS 2
1887 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1889 /* Nonzero if the constant value X is a legitimate general operand.
1890 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1892 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1894 #ifdef REG_OK_STRICT
1895 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1897 if (legitimate_address_p ((MODE), (X), 1)) \
1902 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1904 if (legitimate_address_p ((MODE), (X), 0)) \
1910 /* If defined, a C expression to determine the base term of address X.
1911 This macro is used in only one place: `find_base_term' in alias.c.
1913 It is always safe for this macro to not be defined. It exists so
1914 that alias analysis can understand machine-dependent addresses.
1916 The typical use of this macro is to handle addresses containing
1917 a label_ref or symbol_ref within an UNSPEC. */
1919 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1921 /* Try machine-dependent ways of modifying an illegitimate address
1922 to be legitimate. If we find one, return the new, valid address.
1923 This macro is used in only one place: `memory_address' in explow.c.
1925 OLDX is the address as it was before break_out_memory_refs was called.
1926 In some cases it is useful to look at this to decide what needs to be done.
1928 MODE and WIN are passed so that this macro can use
1929 GO_IF_LEGITIMATE_ADDRESS.
1931 It is always safe for this macro to do nothing. It exists to recognize
1932 opportunities to optimize the output.
1934 For the 80386, we handle X+REG by loading X into a register R and
1935 using R+REG. R will go in a general reg and indexing will be used.
1936 However, if REG is a broken-out memory address or multiplication,
1937 nothing needs to be done because REG can certainly go in a general reg.
1939 When -fpic is used, special handling is needed for symbolic references.
1940 See comments by legitimize_pic_address in i386.c for details. */
1942 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1944 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1945 if (memory_address_p ((MODE), (X))) \
1949 #define REWRITE_ADDRESS(X) rewrite_address (X)
1951 /* Nonzero if the constant value X is a legitimate general operand
1952 when generating PIC code. It is given that flag_pic is on and
1953 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1955 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1957 #define SYMBOLIC_CONST(X) \
1958 (GET_CODE (X) == SYMBOL_REF \
1959 || GET_CODE (X) == LABEL_REF \
1960 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1962 /* Go to LABEL if ADDR (a legitimate address expression)
1963 has an effect that depends on the machine mode it is used for.
1964 On the 80386, only postdecrement and postincrement address depend thus
1965 (the amount of decrement or increment being the length of the operand). */
1966 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1968 if (GET_CODE (ADDR) == POST_INC \
1969 || GET_CODE (ADDR) == POST_DEC) \
1973 /* Codes for all the SSE/MMX builtins. */
1985 IX86_BUILTIN_CMPEQPS
,
1986 IX86_BUILTIN_CMPLTPS
,
1987 IX86_BUILTIN_CMPLEPS
,
1988 IX86_BUILTIN_CMPGTPS
,
1989 IX86_BUILTIN_CMPGEPS
,
1990 IX86_BUILTIN_CMPNEQPS
,
1991 IX86_BUILTIN_CMPNLTPS
,
1992 IX86_BUILTIN_CMPNLEPS
,
1993 IX86_BUILTIN_CMPNGTPS
,
1994 IX86_BUILTIN_CMPNGEPS
,
1995 IX86_BUILTIN_CMPORDPS
,
1996 IX86_BUILTIN_CMPUNORDPS
,
1997 IX86_BUILTIN_CMPNEPS
,
1998 IX86_BUILTIN_CMPEQSS
,
1999 IX86_BUILTIN_CMPLTSS
,
2000 IX86_BUILTIN_CMPLESS
,
2001 IX86_BUILTIN_CMPGTSS
,
2002 IX86_BUILTIN_CMPGESS
,
2003 IX86_BUILTIN_CMPNEQSS
,
2004 IX86_BUILTIN_CMPNLTSS
,
2005 IX86_BUILTIN_CMPNLESS
,
2006 IX86_BUILTIN_CMPNGTSS
,
2007 IX86_BUILTIN_CMPNGESS
,
2008 IX86_BUILTIN_CMPORDSS
,
2009 IX86_BUILTIN_CMPUNORDSS
,
2010 IX86_BUILTIN_CMPNESS
,
2012 IX86_BUILTIN_COMIEQSS
,
2013 IX86_BUILTIN_COMILTSS
,
2014 IX86_BUILTIN_COMILESS
,
2015 IX86_BUILTIN_COMIGTSS
,
2016 IX86_BUILTIN_COMIGESS
,
2017 IX86_BUILTIN_COMINEQSS
,
2018 IX86_BUILTIN_UCOMIEQSS
,
2019 IX86_BUILTIN_UCOMILTSS
,
2020 IX86_BUILTIN_UCOMILESS
,
2021 IX86_BUILTIN_UCOMIGTSS
,
2022 IX86_BUILTIN_UCOMIGESS
,
2023 IX86_BUILTIN_UCOMINEQSS
,
2025 IX86_BUILTIN_CVTPI2PS
,
2026 IX86_BUILTIN_CVTPS2PI
,
2027 IX86_BUILTIN_CVTSI2SS
,
2028 IX86_BUILTIN_CVTSS2SI
,
2029 IX86_BUILTIN_CVTTPS2PI
,
2030 IX86_BUILTIN_CVTTSS2SI
,
2037 IX86_BUILTIN_LOADAPS
,
2038 IX86_BUILTIN_LOADUPS
,
2039 IX86_BUILTIN_STOREAPS
,
2040 IX86_BUILTIN_STOREUPS
,
2041 IX86_BUILTIN_LOADSS
,
2042 IX86_BUILTIN_STORESS
,
2045 IX86_BUILTIN_MOVHLPS
,
2046 IX86_BUILTIN_MOVLHPS
,
2047 IX86_BUILTIN_LOADHPS
,
2048 IX86_BUILTIN_LOADLPS
,
2049 IX86_BUILTIN_STOREHPS
,
2050 IX86_BUILTIN_STORELPS
,
2052 IX86_BUILTIN_MASKMOVQ
,
2053 IX86_BUILTIN_MOVMSKPS
,
2054 IX86_BUILTIN_PMOVMSKB
,
2056 IX86_BUILTIN_MOVNTPS
,
2057 IX86_BUILTIN_MOVNTQ
,
2059 IX86_BUILTIN_PACKSSWB
,
2060 IX86_BUILTIN_PACKSSDW
,
2061 IX86_BUILTIN_PACKUSWB
,
2066 IX86_BUILTIN_PADDSB
,
2067 IX86_BUILTIN_PADDSW
,
2068 IX86_BUILTIN_PADDUSB
,
2069 IX86_BUILTIN_PADDUSW
,
2073 IX86_BUILTIN_PSUBSB
,
2074 IX86_BUILTIN_PSUBSW
,
2075 IX86_BUILTIN_PSUBUSB
,
2076 IX86_BUILTIN_PSUBUSW
,
2086 IX86_BUILTIN_PCMPEQB
,
2087 IX86_BUILTIN_PCMPEQW
,
2088 IX86_BUILTIN_PCMPEQD
,
2089 IX86_BUILTIN_PCMPGTB
,
2090 IX86_BUILTIN_PCMPGTW
,
2091 IX86_BUILTIN_PCMPGTD
,
2093 IX86_BUILTIN_PEXTRW
,
2094 IX86_BUILTIN_PINSRW
,
2096 IX86_BUILTIN_PMADDWD
,
2098 IX86_BUILTIN_PMAXSW
,
2099 IX86_BUILTIN_PMAXUB
,
2100 IX86_BUILTIN_PMINSW
,
2101 IX86_BUILTIN_PMINUB
,
2103 IX86_BUILTIN_PMULHUW
,
2104 IX86_BUILTIN_PMULHW
,
2105 IX86_BUILTIN_PMULLW
,
2107 IX86_BUILTIN_PSADBW
,
2108 IX86_BUILTIN_PSHUFW
,
2118 IX86_BUILTIN_PSLLWI
,
2119 IX86_BUILTIN_PSLLDI
,
2120 IX86_BUILTIN_PSLLQI
,
2121 IX86_BUILTIN_PSRAWI
,
2122 IX86_BUILTIN_PSRADI
,
2123 IX86_BUILTIN_PSRLWI
,
2124 IX86_BUILTIN_PSRLDI
,
2125 IX86_BUILTIN_PSRLQI
,
2127 IX86_BUILTIN_PUNPCKHBW
,
2128 IX86_BUILTIN_PUNPCKHWD
,
2129 IX86_BUILTIN_PUNPCKHDQ
,
2130 IX86_BUILTIN_PUNPCKLBW
,
2131 IX86_BUILTIN_PUNPCKLWD
,
2132 IX86_BUILTIN_PUNPCKLDQ
,
2134 IX86_BUILTIN_SHUFPS
,
2138 IX86_BUILTIN_RSQRTPS
,
2139 IX86_BUILTIN_RSQRTSS
,
2140 IX86_BUILTIN_SQRTPS
,
2141 IX86_BUILTIN_SQRTSS
,
2143 IX86_BUILTIN_UNPCKHPS
,
2144 IX86_BUILTIN_UNPCKLPS
,
2147 IX86_BUILTIN_ANDNPS
,
2152 IX86_BUILTIN_LDMXCSR
,
2153 IX86_BUILTIN_STMXCSR
,
2154 IX86_BUILTIN_SFENCE
,
2156 /* 3DNow! Original */
2158 IX86_BUILTIN_PAVGUSB
,
2162 IX86_BUILTIN_PFCMPEQ
,
2163 IX86_BUILTIN_PFCMPGE
,
2164 IX86_BUILTIN_PFCMPGT
,
2169 IX86_BUILTIN_PFRCPIT1
,
2170 IX86_BUILTIN_PFRCPIT2
,
2171 IX86_BUILTIN_PFRSQIT1
,
2172 IX86_BUILTIN_PFRSQRT
,
2174 IX86_BUILTIN_PFSUBR
,
2176 IX86_BUILTIN_PMULHRW
,
2178 /* 3DNow! Athlon Extensions */
2180 IX86_BUILTIN_PFNACC
,
2181 IX86_BUILTIN_PFPNACC
,
2183 IX86_BUILTIN_PSWAPDSI
,
2184 IX86_BUILTIN_PSWAPDSF
,
2186 IX86_BUILTIN_SSE_ZERO
,
2187 IX86_BUILTIN_MMX_ZERO
,
2199 IX86_BUILTIN_CMPEQPD
,
2200 IX86_BUILTIN_CMPLTPD
,
2201 IX86_BUILTIN_CMPLEPD
,
2202 IX86_BUILTIN_CMPGTPD
,
2203 IX86_BUILTIN_CMPGEPD
,
2204 IX86_BUILTIN_CMPNEQPD
,
2205 IX86_BUILTIN_CMPNLTPD
,
2206 IX86_BUILTIN_CMPNLEPD
,
2207 IX86_BUILTIN_CMPNGTPD
,
2208 IX86_BUILTIN_CMPNGEPD
,
2209 IX86_BUILTIN_CMPORDPD
,
2210 IX86_BUILTIN_CMPUNORDPD
,
2211 IX86_BUILTIN_CMPNEPD
,
2212 IX86_BUILTIN_CMPEQSD
,
2213 IX86_BUILTIN_CMPLTSD
,
2214 IX86_BUILTIN_CMPLESD
,
2215 IX86_BUILTIN_CMPGTSD
,
2216 IX86_BUILTIN_CMPGESD
,
2217 IX86_BUILTIN_CMPNEQSD
,
2218 IX86_BUILTIN_CMPNLTSD
,
2219 IX86_BUILTIN_CMPNLESD
,
2220 IX86_BUILTIN_CMPNGTSD
,
2221 IX86_BUILTIN_CMPNGESD
,
2222 IX86_BUILTIN_CMPORDSD
,
2223 IX86_BUILTIN_CMPUNORDSD
,
2224 IX86_BUILTIN_CMPNESD
,
2226 IX86_BUILTIN_COMIEQSD
,
2227 IX86_BUILTIN_COMILTSD
,
2228 IX86_BUILTIN_COMILESD
,
2229 IX86_BUILTIN_COMIGTSD
,
2230 IX86_BUILTIN_COMIGESD
,
2231 IX86_BUILTIN_COMINEQSD
,
2232 IX86_BUILTIN_UCOMIEQSD
,
2233 IX86_BUILTIN_UCOMILTSD
,
2234 IX86_BUILTIN_UCOMILESD
,
2235 IX86_BUILTIN_UCOMIGTSD
,
2236 IX86_BUILTIN_UCOMIGESD
,
2237 IX86_BUILTIN_UCOMINEQSD
,
2245 IX86_BUILTIN_ANDNPD
,
2249 IX86_BUILTIN_SQRTPD
,
2250 IX86_BUILTIN_SQRTSD
,
2252 IX86_BUILTIN_UNPCKHPD
,
2253 IX86_BUILTIN_UNPCKLPD
,
2255 IX86_BUILTIN_SHUFPD
,
2257 IX86_BUILTIN_LOADAPD
,
2258 IX86_BUILTIN_LOADUPD
,
2259 IX86_BUILTIN_STOREAPD
,
2260 IX86_BUILTIN_STOREUPD
,
2261 IX86_BUILTIN_LOADSD
,
2262 IX86_BUILTIN_STORESD
,
2265 IX86_BUILTIN_LOADHPD
,
2266 IX86_BUILTIN_LOADLPD
,
2267 IX86_BUILTIN_STOREHPD
,
2268 IX86_BUILTIN_STORELPD
,
2270 IX86_BUILTIN_CVTDQ2PD
,
2271 IX86_BUILTIN_CVTDQ2PS
,
2273 IX86_BUILTIN_CVTPD2DQ
,
2274 IX86_BUILTIN_CVTPD2PI
,
2275 IX86_BUILTIN_CVTPD2PS
,
2276 IX86_BUILTIN_CVTTPD2DQ
,
2277 IX86_BUILTIN_CVTTPD2PI
,
2279 IX86_BUILTIN_CVTPI2PD
,
2280 IX86_BUILTIN_CVTSI2SD
,
2282 IX86_BUILTIN_CVTSD2SI
,
2283 IX86_BUILTIN_CVTSD2SS
,
2284 IX86_BUILTIN_CVTSS2SD
,
2285 IX86_BUILTIN_CVTTSD2SI
,
2287 IX86_BUILTIN_CVTPS2DQ
,
2288 IX86_BUILTIN_CVTPS2PD
,
2289 IX86_BUILTIN_CVTTPS2DQ
,
2291 IX86_BUILTIN_MOVNTI
,
2292 IX86_BUILTIN_MOVNTPD
,
2293 IX86_BUILTIN_MOVNTDQ
,
2295 IX86_BUILTIN_SETPD1
,
2298 IX86_BUILTIN_SETRPD
,
2299 IX86_BUILTIN_LOADPD1
,
2300 IX86_BUILTIN_LOADRPD
,
2301 IX86_BUILTIN_STOREPD1
,
2302 IX86_BUILTIN_STORERPD
,
2305 IX86_BUILTIN_MASKMOVDQU
,
2306 IX86_BUILTIN_MOVMSKPD
,
2307 IX86_BUILTIN_PMOVMSKB128
,
2308 IX86_BUILTIN_MOVQ2DQ
,
2310 IX86_BUILTIN_PACKSSWB128
,
2311 IX86_BUILTIN_PACKSSDW128
,
2312 IX86_BUILTIN_PACKUSWB128
,
2314 IX86_BUILTIN_PADDB128
,
2315 IX86_BUILTIN_PADDW128
,
2316 IX86_BUILTIN_PADDD128
,
2317 IX86_BUILTIN_PADDQ128
,
2318 IX86_BUILTIN_PADDSB128
,
2319 IX86_BUILTIN_PADDSW128
,
2320 IX86_BUILTIN_PADDUSB128
,
2321 IX86_BUILTIN_PADDUSW128
,
2322 IX86_BUILTIN_PSUBB128
,
2323 IX86_BUILTIN_PSUBW128
,
2324 IX86_BUILTIN_PSUBD128
,
2325 IX86_BUILTIN_PSUBQ128
,
2326 IX86_BUILTIN_PSUBSB128
,
2327 IX86_BUILTIN_PSUBSW128
,
2328 IX86_BUILTIN_PSUBUSB128
,
2329 IX86_BUILTIN_PSUBUSW128
,
2331 IX86_BUILTIN_PAND128
,
2332 IX86_BUILTIN_PANDN128
,
2333 IX86_BUILTIN_POR128
,
2334 IX86_BUILTIN_PXOR128
,
2336 IX86_BUILTIN_PAVGB128
,
2337 IX86_BUILTIN_PAVGW128
,
2339 IX86_BUILTIN_PCMPEQB128
,
2340 IX86_BUILTIN_PCMPEQW128
,
2341 IX86_BUILTIN_PCMPEQD128
,
2342 IX86_BUILTIN_PCMPGTB128
,
2343 IX86_BUILTIN_PCMPGTW128
,
2344 IX86_BUILTIN_PCMPGTD128
,
2346 IX86_BUILTIN_PEXTRW128
,
2347 IX86_BUILTIN_PINSRW128
,
2349 IX86_BUILTIN_PMADDWD128
,
2351 IX86_BUILTIN_PMAXSW128
,
2352 IX86_BUILTIN_PMAXUB128
,
2353 IX86_BUILTIN_PMINSW128
,
2354 IX86_BUILTIN_PMINUB128
,
2356 IX86_BUILTIN_PMULUDQ
,
2357 IX86_BUILTIN_PMULUDQ128
,
2358 IX86_BUILTIN_PMULHUW128
,
2359 IX86_BUILTIN_PMULHW128
,
2360 IX86_BUILTIN_PMULLW128
,
2362 IX86_BUILTIN_PSADBW128
,
2363 IX86_BUILTIN_PSHUFHW
,
2364 IX86_BUILTIN_PSHUFLW
,
2365 IX86_BUILTIN_PSHUFD
,
2367 IX86_BUILTIN_PSLLW128
,
2368 IX86_BUILTIN_PSLLD128
,
2369 IX86_BUILTIN_PSLLQ128
,
2370 IX86_BUILTIN_PSRAW128
,
2371 IX86_BUILTIN_PSRAD128
,
2372 IX86_BUILTIN_PSRLW128
,
2373 IX86_BUILTIN_PSRLD128
,
2374 IX86_BUILTIN_PSRLQ128
,
2375 IX86_BUILTIN_PSLLWI128
,
2376 IX86_BUILTIN_PSLLDI128
,
2377 IX86_BUILTIN_PSLLQI128
,
2378 IX86_BUILTIN_PSRAWI128
,
2379 IX86_BUILTIN_PSRADI128
,
2380 IX86_BUILTIN_PSRLWI128
,
2381 IX86_BUILTIN_PSRLDI128
,
2382 IX86_BUILTIN_PSRLQI128
,
2384 IX86_BUILTIN_PUNPCKHBW128
,
2385 IX86_BUILTIN_PUNPCKHWD128
,
2386 IX86_BUILTIN_PUNPCKHDQ128
,
2387 IX86_BUILTIN_PUNPCKLBW128
,
2388 IX86_BUILTIN_PUNPCKLWD128
,
2389 IX86_BUILTIN_PUNPCKLDQ128
,
2391 IX86_BUILTIN_CLFLUSH
,
2392 IX86_BUILTIN_MFENCE
,
2393 IX86_BUILTIN_LFENCE
,
2398 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
2399 #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding
2401 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2403 const char *xname = (NAME); \
2404 if (xname[0] == '%') \
2406 if (xname[0] == '*') \
2409 fputs (user_label_prefix, FILE); \
2410 fputs (xname, FILE); \
2413 /* Max number of args passed in registers. If this is more than 3, we will
2414 have problems with ebx (register #4), since it is a caller save register and
2415 is also used as the pic register in ELF. So for now, don't allow more than
2416 3 registers to be passed in registers. */
2418 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2420 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2423 /* Specify the machine mode that this machine uses
2424 for the index in the tablejump instruction. */
2425 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2427 /* Define as C expression which evaluates to nonzero if the tablejump
2428 instruction expects the table to contain offsets from the address of the
2430 Do not define this if the table should contain absolute addresses. */
2431 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2433 /* Define this as 1 if `char' should by default be signed; else as 0. */
2434 #define DEFAULT_SIGNED_CHAR 1
2436 /* Number of bytes moved into a data cache for a single prefetch operation. */
2437 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2439 /* Number of prefetch operations that can be done in parallel. */
2440 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2442 /* Max number of bytes we can move from memory to memory
2443 in one reasonably fast instruction. */
2446 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2447 move efficiently, as opposed to MOVE_MAX which is the maximum
2448 number of bytes we can move with a single instruction. */
2449 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2451 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2452 move-instruction pairs, we will do a movstr or libcall instead.
2453 Increasing the value will always make code faster, but eventually
2454 incurs high cost in increased code size.
2456 If you don't define this, a reasonable default is used. */
2458 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2460 /* Define if shifts truncate the shift count
2461 which implies one can omit a sign-extension or zero-extension
2462 of a shift count. */
2463 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2465 /* #define SHIFT_COUNT_TRUNCATED */
2467 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2468 is done just by pretending it is already truncated. */
2469 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2471 /* We assume that the store-condition-codes instructions store 0 for false
2472 and some other value for true. This is the value stored for true. */
2474 #define STORE_FLAG_VALUE 1
2476 /* When a prototype says `char' or `short', really pass an `int'.
2477 (The 386 can't easily push less than an int.) */
2479 #define PROMOTE_PROTOTYPES 1
2481 /* A macro to update M and UNSIGNEDP when an object whose type is
2482 TYPE and which has the specified mode and signedness is to be
2483 stored in a register. This macro is only called when TYPE is a
2486 On i386 it is sometimes useful to promote HImode and QImode
2487 quantities to SImode. The choice depends on target type. */
2489 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2491 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2492 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2496 /* Specify the machine mode that pointers have.
2497 After generation of rtl, the compiler makes no further distinction
2498 between pointers and any other objects of this machine mode. */
2499 #define Pmode (TARGET_64BIT ? DImode : SImode)
2501 /* A function address in a call instruction
2502 is a byte address (for indexing purposes)
2503 so give the MEM rtx a byte's mode. */
2504 #define FUNCTION_MODE QImode
2506 /* A part of a C `switch' statement that describes the relative costs
2507 of constant RTL expressions. It must contain `case' labels for
2508 expression codes `const_int', `const', `symbol_ref', `label_ref'
2509 and `const_double'. Each case must ultimately reach a `return'
2510 statement to return the relative cost of the use of that kind of
2511 constant value in an expression. The cost may depend on the
2512 precise value of the constant, which is available for examination
2513 in X, and the rtx code of the expression in which it is contained,
2514 found in OUTER_CODE.
2516 CODE is the expression code--redundant, since it can be obtained
2517 with `GET_CODE (X)'. */
2519 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2524 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2526 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2528 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2530 case CONST_DOUBLE: \
2531 if (GET_MODE (RTX) == VOIDmode) \
2533 switch (standard_80387_constant_p (RTX)) \
2540 /* Start with (MEM (SYMBOL_REF)), since that's where \
2541 it'll probably end up. Add a penalty for size. */ \
2542 return (COSTS_N_INSNS (1) + (flag_pic != 0) \
2543 + (GET_MODE (RTX) == SFmode ? 0 \
2544 : GET_MODE (RTX) == DFmode ? 1 : 2)); \
2547 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2548 #define TOPLEVEL_COSTS_N_INSNS(N) \
2549 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2551 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2552 This can be used, for example, to indicate how costly a multiply
2553 instruction is. In writing this macro, you can use the construct
2554 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2555 instructions. OUTER_CODE is the code of the expression in which X
2558 This macro is optional; do not define it if the default cost
2559 assumptions are adequate for the target machine. */
2561 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2563 /* The zero extensions is often completely free on x86_64, so make \
2564 it as cheap as possible. */ \
2565 if (TARGET_64BIT && GET_MODE (X) == DImode \
2566 && GET_MODE (XEXP (X, 0)) == SImode) \
2568 total = 1; goto egress_rtx_costs; \
2571 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2572 ix86_cost->add : ix86_cost->movzx); \
2575 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2578 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2579 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2581 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2583 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2584 if ((value == 2 || value == 3) \
2585 && !TARGET_DECOMPOSE_LEA \
2586 && ix86_cost->lea <= ix86_cost->shift_const) \
2587 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2589 /* fall through */ \
2595 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2597 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2599 if (INTVAL (XEXP (X, 1)) > 32) \
2600 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2602 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2606 if (GET_CODE (XEXP (X, 1)) == AND) \
2607 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2609 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2614 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2615 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2617 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2622 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2624 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2627 while (value != 0) \
2633 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2634 + nbits * ix86_cost->mult_bit); \
2636 else /* This is arbitrary */ \
2637 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2638 + 7 * ix86_cost->mult_bit); \
2644 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2647 if (!TARGET_DECOMPOSE_LEA \
2648 && INTEGRAL_MODE_P (GET_MODE (X)) \
2649 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2651 if (GET_CODE (XEXP (X, 0)) == PLUS \
2652 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2653 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2654 && CONSTANT_P (XEXP (X, 1))) \
2656 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2657 if (val == 2 || val == 4 || val == 8) \
2659 return (COSTS_N_INSNS (ix86_cost->lea) \
2660 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2662 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2664 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2667 else if (GET_CODE (XEXP (X, 0)) == MULT \
2668 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2670 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2671 if (val == 2 || val == 4 || val == 8) \
2673 return (COSTS_N_INSNS (ix86_cost->lea) \
2674 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2676 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2679 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2681 return (COSTS_N_INSNS (ix86_cost->lea) \
2682 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2683 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2684 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2688 /* fall through */ \
2693 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2694 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2695 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2696 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2697 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2698 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2700 /* fall through */ \
2703 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2704 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2705 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2707 case FLOAT_EXTEND: \
2708 if (!TARGET_SSE_MATH \
2709 || !VALID_SSE_REG_MODE (GET_MODE (X))) \
2710 TOPLEVEL_COSTS_N_INSNS (0); \
2717 /* An expression giving the cost of an addressing mode that contains
2718 ADDRESS. If not defined, the cost is computed from the ADDRESS
2719 expression and the `CONST_COSTS' values.
2721 For most CISC machines, the default cost is a good approximation
2722 of the true cost of the addressing mode. However, on RISC
2723 machines, all instructions normally have the same length and
2724 execution time. Hence all addresses will have equal costs.
2726 In cases where more than one form of an address is known, the form
2727 with the lowest cost will be used. If multiple forms have the
2728 same, lowest, cost, the one that is the most complex will be used.
2730 For example, suppose an address that is equal to the sum of a
2731 register and a constant is used twice in the same basic block.
2732 When this macro is not defined, the address will be computed in a
2733 register and memory references will be indirect through that
2734 register. On machines where the cost of the addressing mode
2735 containing the sum is no higher than that of a simple indirect
2736 reference, this will produce an additional instruction and
2737 possibly require an additional register. Proper specification of
2738 this macro eliminates this overhead for such machines.
2740 Similar use of this macro is made in strength reduction of loops.
2742 ADDRESS need not be valid as an address. In such a case, the cost
2743 is not relevant and can be any value; invalid addresses need not be
2744 assigned a different cost.
2746 On machines where an address involving more than one register is as
2747 cheap as an address computation involving only one register,
2748 defining `ADDRESS_COST' to reflect this can cause two registers to
2749 be live over a region of code where only one would have been if
2750 `ADDRESS_COST' were not defined in that manner. This effect should
2751 be considered in the definition of this macro. Equivalent costs
2752 should probably only be given to addresses with different numbers
2753 of registers on machines with lots of registers.
2755 This macro will normally either not be defined or be defined as a
2758 For i386, it is better to use a complex address than let gcc copy
2759 the address into a reg and make a new pseudo. But not if the address
2760 requires to two regs - that would mean more pseudos with longer
2763 #define ADDRESS_COST(RTX) \
2764 ix86_address_cost (RTX)
2766 /* A C expression for the cost of moving data from a register in class FROM to
2767 one in class TO. The classes are expressed using the enumeration values
2768 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2769 interpreted relative to that.
2771 It is not required that the cost always equal 2 when FROM is the same as TO;
2772 on some machines it is expensive to move between registers if they are not
2773 general registers. */
2775 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2776 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2778 /* A C expression for the cost of moving data of mode M between a
2779 register and memory. A value of 2 is the default; this cost is
2780 relative to those in `REGISTER_MOVE_COST'.
2782 If moving between registers and memory is more expensive than
2783 between two registers, you should define this macro to express the
2786 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2787 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2789 /* A C expression for the cost of a branch instruction. A value of 1
2790 is the default; other values are interpreted relative to that. */
2792 #define BRANCH_COST ix86_branch_cost
2794 /* Define this macro as a C expression which is nonzero if accessing
2795 less than a word of memory (i.e. a `char' or a `short') is no
2796 faster than accessing a word of memory, i.e., if such access
2797 require more than one instruction or if there is no difference in
2798 cost between byte and (aligned) word loads.
2800 When this macro is not defined, the compiler will access a field by
2801 finding the smallest containing object; when it is defined, a
2802 fullword load will be used if alignment permits. Unless bytes
2803 accesses are faster than word accesses, using word accesses is
2804 preferable since it may eliminate subsequent memory access if
2805 subsequent accesses occur to other fields in the same word of the
2806 structure, but to different bytes. */
2808 #define SLOW_BYTE_ACCESS 0
2810 /* Nonzero if access to memory by shorts is slow and undesirable. */
2811 #define SLOW_SHORT_ACCESS 0
2813 /* Define this macro to be the value 1 if unaligned accesses have a
2814 cost many times greater than aligned accesses, for example if they
2815 are emulated in a trap handler.
2817 When this macro is non-zero, the compiler will act as if
2818 `STRICT_ALIGNMENT' were non-zero when generating code for block
2819 moves. This can cause significantly more instructions to be
2820 produced. Therefore, do not set this macro non-zero if unaligned
2821 accesses only add a cycle or two to the time for a memory access.
2823 If the value of this macro is always zero, it need not be defined. */
2825 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2827 /* Define this macro to inhibit strength reduction of memory
2828 addresses. (On some machines, such strength reduction seems to do
2829 harm rather than good.) */
2831 /* #define DONT_REDUCE_ADDR */
2833 /* Define this macro if it is as good or better to call a constant
2834 function address than to call an address kept in a register.
2836 Desirable on the 386 because a CALL with a constant address is
2837 faster than one with a register address. */
2839 #define NO_FUNCTION_CSE
2841 /* Define this macro if it is as good or better for a function to call
2842 itself with an explicit address than to call an address kept in a
2845 #define NO_RECURSIVE_FUNCTION_CSE
2847 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2848 return the mode to be used for the comparison.
2850 For floating-point equality comparisons, CCFPEQmode should be used.
2851 VOIDmode should be used in all other cases.
2853 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2854 possible, to allow for more combinations. */
2856 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2858 /* Return non-zero if MODE implies a floating point inequality can be
2861 #define REVERSIBLE_CC_MODE(MODE) 1
2863 /* A C expression whose value is reversed condition code of the CODE for
2864 comparison done in CC_MODE mode. */
2865 #define REVERSE_CONDITION(CODE, MODE) \
2866 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2867 : reverse_condition_maybe_unordered (CODE))
2870 /* Control the assembler format that we output, to the extent
2871 this does not vary between assemblers. */
2873 /* How to refer to registers in assembler output.
2874 This sequence is indexed by compiler's hard-register-number (see above). */
2876 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2877 For non floating point regs, the following are the HImode names.
2879 For float regs, the stack top is sometimes referred to as "%st(0)"
2880 instead of just "%st". PRINT_REG handles this with the "y" code. */
2882 #undef HI_REGISTER_NAMES
2883 #define HI_REGISTER_NAMES \
2884 {"ax","dx","cx","bx","si","di","bp","sp", \
2885 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2886 "flags","fpsr", "dirflag", "frame", \
2887 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2888 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2889 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2890 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2892 #define REGISTER_NAMES HI_REGISTER_NAMES
2894 /* Table of additional register names to use in user input. */
2896 #define ADDITIONAL_REGISTER_NAMES \
2897 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2898 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2899 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2900 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2901 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2902 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2903 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2904 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2906 /* Note we are omitting these since currently I don't know how
2907 to get gcc to use these, since they want the same but different
2908 number as al, and ax.
2911 #define QI_REGISTER_NAMES \
2912 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2914 /* These parallel the array above, and can be used to access bits 8:15
2915 of regs 0 through 3. */
2917 #define QI_HIGH_REGISTER_NAMES \
2918 {"ah", "dh", "ch", "bh", }
2920 /* How to renumber registers for dbx and gdb. */
2922 #define DBX_REGISTER_NUMBER(N) \
2923 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2925 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2926 extern int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
];
2927 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2929 /* Before the prologue, RA is at 0(%esp). */
2930 #define INCOMING_RETURN_ADDR_RTX \
2931 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2933 /* After the prologue, RA is at -4(AP) in the current frame. */
2934 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2936 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2937 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2939 /* PC is dbx register 8; let's use that column for RA. */
2940 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2942 /* Before the prologue, the top of the frame is at 4(%esp). */
2943 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2945 /* Describe how we implement __builtin_eh_return. */
2946 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2947 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2950 /* Select a format to encode pointers in exception handling data. CODE
2951 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2952 true if the symbol may be affected by dynamic relocations.
2954 ??? All x86 object file formats are capable of representing this.
2955 After all, the relocation needed is the same as for the call insn.
2956 Whether or not a particular assembler allows us to enter such, I
2957 guess we'll have to see. */
2958 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2960 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2963 /* This is how to output the definition of a user-level label named NAME,
2964 such as the label on a static function or variable NAME. */
2966 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2967 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2969 /* Store in OUTPUT a string (made with alloca) containing
2970 an assembler-name for a local static variable named NAME.
2971 LABELNO is an integer which is different for each call. */
2973 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2974 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2975 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2977 /* This is how to output an insn to push a register on the stack.
2978 It need not be very fast code. */
2980 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2981 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
2983 /* This is how to output an insn to pop a register from the stack.
2984 It need not be very fast code. */
2986 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2987 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
2989 /* This is how to output an element of a case-vector that is absolute. */
2991 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2992 ix86_output_addr_vec_elt ((FILE), (VALUE))
2994 /* This is how to output an element of a case-vector that is relative. */
2996 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2997 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2999 /* Under some conditions we need jump tables in the text section, because
3000 the assembler cannot handle label differences between sections. */
3002 #define JUMP_TABLES_IN_TEXT_SECTION \
3003 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
3005 /* A C statement that outputs an address constant appropriate to
3006 for DWARF debugging. */
3008 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
3009 i386_dwarf_output_addr_const ((FILE), (X))
3011 /* Either simplify a location expression, or return the original. */
3013 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
3014 i386_simplify_dwarf_addr (X)
3016 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
3017 and switch back. For x86 we do this only to save a few bytes that
3018 would otherwise be unused in the text section. */
3019 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3020 asm (SECTION_OP "\n\t" \
3021 "call " USER_LABEL_PREFIX #FUNC "\n" \
3022 TEXT_SECTION_ASM_OP);
3024 /* Print operand X (an rtx) in assembler syntax to file FILE.
3025 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3026 Effect of various CODE letters is described in i386.c near
3027 print_operand function. */
3029 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
3030 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
3032 /* Print the name of a register based on its machine mode and number.
3033 If CODE is 'w', pretend the mode is HImode.
3034 If CODE is 'b', pretend the mode is QImode.
3035 If CODE is 'k', pretend the mode is SImode.
3036 If CODE is 'q', pretend the mode is DImode.
3037 If CODE is 'h', pretend the reg is the `high' byte register.
3038 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3040 #define PRINT_REG(X, CODE, FILE) \
3041 print_reg ((X), (CODE), (FILE))
3043 #define PRINT_OPERAND(FILE, X, CODE) \
3044 print_operand ((FILE), (X), (CODE))
3046 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3047 print_operand_address ((FILE), (ADDR))
3049 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
3051 if (! output_addr_const_extra (FILE, (X))) \
3055 /* Print the name of a register for based on its machine mode and number.
3056 This macro is used to print debugging output.
3057 This macro is different from PRINT_REG in that it may be used in
3058 programs that are not linked with aux-output.o. */
3060 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3061 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3062 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3063 fprintf ((FILE), "%d ", REGNO (X)); \
3064 if (REGNO (X) == FLAGS_REG) \
3065 { fputs ("flags", (FILE)); break; } \
3066 if (REGNO (X) == DIRFLAG_REG) \
3067 { fputs ("dirflag", (FILE)); break; } \
3068 if (REGNO (X) == FPSR_REG) \
3069 { fputs ("fpsr", (FILE)); break; } \
3070 if (REGNO (X) == ARG_POINTER_REGNUM) \
3071 { fputs ("argp", (FILE)); break; } \
3072 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3073 { fputs ("frame", (FILE)); break; } \
3074 if (STACK_TOP_P (X)) \
3075 { fputs ("st(0)", (FILE)); break; } \
3077 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
3078 if (REX_INT_REG_P (X)) \
3080 switch (GET_MODE_SIZE (GET_MODE (X))) \
3084 fprintf ((FILE), "r%i", REGNO (X) \
3085 - FIRST_REX_INT_REG + 8); \
3088 fprintf ((FILE), "r%id", REGNO (X) \
3089 - FIRST_REX_INT_REG + 8); \
3092 fprintf ((FILE), "r%iw", REGNO (X) \
3093 - FIRST_REX_INT_REG + 8); \
3096 fprintf ((FILE), "r%ib", REGNO (X) \
3097 - FIRST_REX_INT_REG + 8); \
3102 switch (GET_MODE_SIZE (GET_MODE (X))) \
3105 fputs ("r", (FILE)); \
3106 fputs (hi_name[REGNO (X)], (FILE)); \
3109 fputs ("e", (FILE)); \
3111 fputs (hi_name[REGNO (X)], (FILE)); \
3114 fputs (qi_name[REGNO (X)], (FILE)); \
3119 /* a letter which is not needed by the normal asm syntax, which
3120 we can use for operand syntax in the extended asm */
3122 #define ASM_OPERAND_LETTER '#'
3123 #define RET return ""
3124 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3126 /* Define the codes that are matched by predicates in i386.c. */
3128 #define PREDICATE_CODES \
3129 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3130 SYMBOL_REF, LABEL_REF, CONST}}, \
3131 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3132 SYMBOL_REF, LABEL_REF, CONST}}, \
3133 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3134 SYMBOL_REF, LABEL_REF, CONST}}, \
3135 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3136 SYMBOL_REF, LABEL_REF, CONST}}, \
3137 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3138 SYMBOL_REF, LABEL_REF, CONST}}, \
3139 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3140 SYMBOL_REF, LABEL_REF, CONST}}, \
3141 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3142 SYMBOL_REF, LABEL_REF}}, \
3143 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3144 {"const_int_1_operand", {CONST_INT}}, \
3145 {"const_int_1_31_operand", {CONST_INT}}, \
3146 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3147 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3148 LABEL_REF, SUBREG, REG, MEM}}, \
3149 {"pic_symbolic_operand", {CONST}}, \
3150 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3151 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3152 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3153 {"const1_operand", {CONST_INT}}, \
3154 {"const248_operand", {CONST_INT}}, \
3155 {"incdec_operand", {CONST_INT}}, \
3156 {"mmx_reg_operand", {REG}}, \
3157 {"reg_no_sp_operand", {SUBREG, REG}}, \
3158 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3159 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3160 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3161 {"q_regs_operand", {SUBREG, REG}}, \
3162 {"non_q_regs_operand", {SUBREG, REG}}, \
3163 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3164 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3165 GE, UNGE, LTGT, UNEQ}}, \
3166 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3167 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3169 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3170 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3171 UNGE, UNGT, LTGT, UNEQ }}, \
3172 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3173 {"ext_register_operand", {SUBREG, REG}}, \
3174 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3175 {"mult_operator", {MULT}}, \
3176 {"div_operator", {DIV}}, \
3177 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3178 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3179 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3180 LSHIFTRT, ROTATERT}}, \
3181 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3182 {"memory_displacement_operand", {MEM}}, \
3183 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3184 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3185 {"long_memory_operand", {MEM}}, \
3186 {"tls_symbolic_operand", {SYMBOL_REF}}, \
3187 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3188 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3189 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
3190 {"local_exec_symbolic_operand", {SYMBOL_REF}},
3192 /* A list of predicates that do special things with modes, and so
3193 should not elicit warnings for VOIDmode match_operand. */
3195 #define SPECIAL_MODE_PREDICATES \
3196 "ext_register_operand",
3198 /* Which processor to schedule for. The cpu attribute defines a list that
3199 mirrors this list, so changes to i386.md must be made at the same time. */
3203 PROCESSOR_I386
, /* 80386 */
3204 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
3206 PROCESSOR_PENTIUMPRO
,
3213 extern enum processor_type ix86_cpu
;
3214 extern const char *ix86_cpu_string
;
3216 extern enum processor_type ix86_arch
;
3217 extern const char *ix86_arch_string
;
3225 extern enum fpmath_unit ix86_fpmath
;
3226 extern const char *ix86_fpmath_string
;
3234 extern enum tls_dialect ix86_tls_dialect
;
3235 extern const char *ix86_tls_dialect_string
;
3238 CM_32
, /* The traditional 32-bit ABI. */
3239 CM_SMALL
, /* Assumes all code and data fits in the low 31 bits. */
3240 CM_KERNEL
, /* Assumes all code and data fits in the high 31 bits. */
3241 CM_MEDIUM
, /* Assumes code fits in the low 31 bits; data unlimited. */
3242 CM_LARGE
, /* No assumptions. */
3243 CM_SMALL_PIC
/* Assumes code+data+got/plt fits in a 31 bit region. */
3246 extern enum cmodel ix86_cmodel
;
3247 extern const char *ix86_cmodel_string
;
3249 /* Size of the RED_ZONE area. */
3250 #define RED_ZONE_SIZE 128
3251 /* Reserved area of the red zone for temporaries. */
3252 #define RED_ZONE_RESERVE 8
3259 extern const char *ix86_asm_string
;
3260 extern enum asm_dialect ix86_asm_dialect
;
3262 extern int ix86_regparm
;
3263 extern const char *ix86_regparm_string
;
3265 extern int ix86_preferred_stack_boundary
;
3266 extern const char *ix86_preferred_stack_boundary_string
;
3268 extern int ix86_branch_cost
;
3269 extern const char *ix86_branch_cost_string
;
3271 extern const char *ix86_debug_arg_string
;
3272 extern const char *ix86_debug_addr_string
;
3274 /* Obsoleted by -f options. Remove before 3.2 ships. */
3275 extern const char *ix86_align_loops_string
;
3276 extern const char *ix86_align_jumps_string
;
3277 extern const char *ix86_align_funcs_string
;
3279 /* Smallest class containing REGNO. */
3280 extern enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
];
3282 extern rtx ix86_compare_op0
; /* operand 0 for comparisons */
3283 extern rtx ix86_compare_op1
; /* operand 1 for comparisons */
3285 /* To properly truncate FP values into integers, we need to set i387 control
3286 word. We can't emit proper mode switching code before reload, as spills
3287 generated by reload may truncate values incorrectly, but we still can avoid
3288 redundant computation of new control word by the mode switching pass.
3289 The fldcw instructions are still emitted redundantly, but this is probably
3290 not going to be noticeable problem, as most CPUs do have fast path for
3293 The machinery is to emit simple truncation instructions and split them
3294 before reload to instructions having USEs of two memory locations that
3295 are filled by this code to old and new control word.
3297 Post-reload pass may be later used to eliminate the redundant fildcw if
3300 enum fp_cw_mode
{FP_CW_STORED
, FP_CW_UNINITIALIZED
, FP_CW_ANY
};
3302 /* Define this macro if the port needs extra instructions inserted
3303 for mode switching in an optimizing compilation. */
3305 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3307 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3308 initializer for an array of integers. Each initializer element N
3309 refers to an entity that needs mode switching, and specifies the
3310 number of different modes that might need to be set for this
3311 entity. The position of the initializer in the initializer -
3312 starting counting at zero - determines the integer that is used to
3313 refer to the mode-switched entity in question. */
3315 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3317 /* ENTITY is an integer specifying a mode-switched entity. If
3318 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3319 return an integer value not larger than the corresponding element
3320 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3321 must be switched into prior to the execution of INSN. */
3323 #define MODE_NEEDED(ENTITY, I) \
3324 (GET_CODE (I) == CALL_INSN \
3325 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3326 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3327 ? FP_CW_UNINITIALIZED \
3328 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3332 /* This macro specifies the order in which modes for ENTITY are
3333 processed. 0 is the highest priority. */
3335 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3337 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3338 is the set of hard registers live at the point where the insn(s)
3339 are to be inserted. */
3341 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3342 ((MODE) == FP_CW_STORED \
3343 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3344 assign_386_stack_local (HImode, 2)), 0\
3347 /* Avoid renaming of stack registers, as doing so in combination with
3348 scheduling just increases amount of live registers at time and in
3349 the turn amount of fxch instructions needed.
3351 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3353 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3354 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)