1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 Under Section 7 of GPL version 3, you are granted additional
19 permissions described in the GCC Runtime Library Exception, version
20 3.1, as published by the Free Software Foundation.
22 You should have received a copy of the GNU General Public License and
23 a copy of the GCC Runtime Library Exception along with this program;
24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
25 <http://www.gnu.org/licenses/>. */
27 /* The purpose of this file is to define the characteristics of the i386,
28 independent of assembler syntax or operating system.
30 Three other files build on this one to describe a specific assembler syntax:
31 bsd386.h, att386.h, and sun386.h.
33 The actual tm.h file for a particular system should include
34 this file, and then the file for the appropriate assembler syntax.
36 Many macros that specify assembler syntax are omitted entirely from
37 this file because they really belong in the files for particular
38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
40 that start with ASM_ or end in ASM_OP. */
42 /* Redefines for option macros. */
44 #define TARGET_64BIT OPTION_ISA_64BIT
45 #define TARGET_MMX OPTION_ISA_MMX
46 #define TARGET_3DNOW OPTION_ISA_3DNOW
47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
48 #define TARGET_SSE OPTION_ISA_SSE
49 #define TARGET_SSE2 OPTION_ISA_SSE2
50 #define TARGET_SSE3 OPTION_ISA_SSE3
51 #define TARGET_SSSE3 OPTION_ISA_SSSE3
52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
54 #define TARGET_AVX OPTION_ISA_AVX
55 #define TARGET_AVX2 OPTION_ISA_AVX2
56 #define TARGET_FMA OPTION_ISA_FMA
57 #define TARGET_SSE4A OPTION_ISA_SSE4A
58 #define TARGET_FMA4 OPTION_ISA_FMA4
59 #define TARGET_XOP OPTION_ISA_XOP
60 #define TARGET_LWP OPTION_ISA_LWP
61 #define TARGET_ROUND OPTION_ISA_ROUND
62 #define TARGET_ABM OPTION_ISA_ABM
63 #define TARGET_BMI OPTION_ISA_BMI
64 #define TARGET_BMI2 OPTION_ISA_BMI2
65 #define TARGET_LZCNT OPTION_ISA_LZCNT
66 #define TARGET_TBM OPTION_ISA_TBM
67 #define TARGET_POPCNT OPTION_ISA_POPCNT
68 #define TARGET_SAHF OPTION_ISA_SAHF
69 #define TARGET_MOVBE OPTION_ISA_MOVBE
70 #define TARGET_CRC32 OPTION_ISA_CRC32
71 #define TARGET_AES OPTION_ISA_AES
72 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
73 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
74 #define TARGET_FSGSBASE OPTION_ISA_FSGSBASE
75 #define TARGET_RDRND OPTION_ISA_RDRND
76 #define TARGET_F16C OPTION_ISA_F16C
77 #define TARGET_RTM OPTION_ISA_RTM
78 #define TARGET_HLE OPTION_ISA_HLE
79 #define TARGET_RDSEED OPTION_ISA_RDSEED
80 #define TARGET_PRFCHW OPTION_ISA_PRFCHW
81 #define TARGET_ADX OPTION_ISA_ADX
83 #define TARGET_LP64 OPTION_ABI_64
84 #define TARGET_X32 OPTION_ABI_X32
86 /* SSE4.1 defines round instructions */
87 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
88 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
90 #include "config/vxworks-dummy.h"
92 #include "config/i386/i386-opts.h"
94 #define MAX_STRINGOP_ALGS 4
96 /* Specify what algorithm to use for stringops on known size.
97 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
98 known at compile time or estimated via feedback, the SIZE array
99 is walked in order until MAX is greater then the estimate (or -1
100 means infinity). Corresponding ALG is used then.
101 For example initializer:
102 {{256, loop}, {-1, rep_prefix_4_byte}}
103 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
104 be used otherwise. */
107 const enum stringop_alg unknown_size
;
108 const struct stringop_strategy
{
110 const enum stringop_alg alg
;
111 } size
[MAX_STRINGOP_ALGS
];
114 /* Define the specific costs for a given cpu */
116 struct processor_costs
{
117 const int add
; /* cost of an add instruction */
118 const int lea
; /* cost of a lea instruction */
119 const int shift_var
; /* variable shift costs */
120 const int shift_const
; /* constant shift costs */
121 const int mult_init
[5]; /* cost of starting a multiply
122 in QImode, HImode, SImode, DImode, TImode*/
123 const int mult_bit
; /* cost of multiply per each bit set */
124 const int divide
[5]; /* cost of a divide/mod
125 in QImode, HImode, SImode, DImode, TImode*/
126 int movsx
; /* The cost of movsx operation. */
127 int movzx
; /* The cost of movzx operation. */
128 const int large_insn
; /* insns larger than this cost more */
129 const int move_ratio
; /* The threshold of number of scalar
130 memory-to-memory move insns. */
131 const int movzbl_load
; /* cost of loading using movzbl */
132 const int int_load
[3]; /* cost of loading integer registers
133 in QImode, HImode and SImode relative
134 to reg-reg move (2). */
135 const int int_store
[3]; /* cost of storing integer register
136 in QImode, HImode and SImode */
137 const int fp_move
; /* cost of reg,reg fld/fst */
138 const int fp_load
[3]; /* cost of loading FP register
139 in SFmode, DFmode and XFmode */
140 const int fp_store
[3]; /* cost of storing FP register
141 in SFmode, DFmode and XFmode */
142 const int mmx_move
; /* cost of moving MMX register. */
143 const int mmx_load
[2]; /* cost of loading MMX register
144 in SImode and DImode */
145 const int mmx_store
[2]; /* cost of storing MMX register
146 in SImode and DImode */
147 const int sse_move
; /* cost of moving SSE register. */
148 const int sse_load
[3]; /* cost of loading SSE register
149 in SImode, DImode and TImode*/
150 const int sse_store
[3]; /* cost of storing SSE register
151 in SImode, DImode and TImode*/
152 const int mmxsse_to_integer
; /* cost of moving mmxsse register to
153 integer and vice versa. */
154 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
155 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
156 const int prefetch_block
; /* bytes moved to cache for prefetch. */
157 const int simultaneous_prefetches
; /* number of parallel prefetch
159 const int branch_cost
; /* Default value for BRANCH_COST. */
160 const int fadd
; /* cost of FADD and FSUB instructions. */
161 const int fmul
; /* cost of FMUL instruction. */
162 const int fdiv
; /* cost of FDIV instruction. */
163 const int fabs
; /* cost of FABS instruction. */
164 const int fchs
; /* cost of FCHS instruction. */
165 const int fsqrt
; /* cost of FSQRT instruction. */
166 /* Specify what algorithm
167 to use for stringops on unknown size. */
168 struct stringop_algs memcpy
[2], memset
[2];
169 const int scalar_stmt_cost
; /* Cost of any scalar operation, excluding
171 const int scalar_load_cost
; /* Cost of scalar load. */
172 const int scalar_store_cost
; /* Cost of scalar store. */
173 const int vec_stmt_cost
; /* Cost of any vector operation, excluding
174 load, store, vector-to-scalar and
175 scalar-to-vector operation. */
176 const int vec_to_scalar_cost
; /* Cost of vect-to-scalar operation. */
177 const int scalar_to_vec_cost
; /* Cost of scalar-to-vector operation. */
178 const int vec_align_load_cost
; /* Cost of aligned vector load. */
179 const int vec_unalign_load_cost
; /* Cost of unaligned vector load. */
180 const int vec_store_cost
; /* Cost of vector store. */
181 const int cond_taken_branch_cost
; /* Cost of taken branch for vectorizer
183 const int cond_not_taken_branch_cost
;/* Cost of not taken branch for
184 vectorizer cost model. */
187 extern const struct processor_costs
*ix86_cost
;
188 extern const struct processor_costs ix86_size_cost
;
190 #define ix86_cur_cost() \
191 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
193 /* Macros used in the machine description to test the flags. */
195 /* configure can arrange to make this 2, to force a 486. */
197 #ifndef TARGET_CPU_DEFAULT
198 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
201 #ifndef TARGET_FPMATH_DEFAULT
202 #define TARGET_FPMATH_DEFAULT \
203 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
206 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
208 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
209 compile-time constant. */
213 #define TARGET_64BIT 1
215 #define TARGET_64BIT 0
218 #ifndef TARGET_BI_ARCH
220 #if TARGET_64BIT_DEFAULT
221 #define TARGET_64BIT 1
223 #define TARGET_64BIT 0
228 #define HAS_LONG_COND_BRANCH 1
229 #define HAS_LONG_UNCOND_BRANCH 1
231 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
232 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
233 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
234 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
235 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
236 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
237 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
238 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
239 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
240 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
241 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
242 #define TARGET_CORE2_32 (ix86_tune == PROCESSOR_CORE2_32)
243 #define TARGET_CORE2_64 (ix86_tune == PROCESSOR_CORE2_64)
244 #define TARGET_CORE2 (TARGET_CORE2_32 || TARGET_CORE2_64)
245 #define TARGET_COREI7_32 (ix86_tune == PROCESSOR_COREI7_32)
246 #define TARGET_COREI7_64 (ix86_tune == PROCESSOR_COREI7_64)
247 #define TARGET_COREI7 (TARGET_COREI7_32 || TARGET_COREI7_64)
248 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
249 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
250 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
251 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
252 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
253 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
254 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
255 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
256 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
258 /* Feature tests against the various tunings. */
259 enum ix86_tune_indices
{
261 X86_TUNE_PUSH_MEMORY
,
262 X86_TUNE_ZERO_EXTEND_WITH_AND
,
263 X86_TUNE_UNROLL_STRLEN
,
264 X86_TUNE_BRANCH_PREDICTION_HINTS
,
265 X86_TUNE_DOUBLE_WITH_ADD
,
268 X86_TUNE_PARTIAL_REG_STALL
,
269 X86_TUNE_PARTIAL_FLAG_REG_STALL
,
271 X86_TUNE_USE_HIMODE_FIOP
,
272 X86_TUNE_USE_SIMODE_FIOP
,
276 X86_TUNE_SPLIT_LONG_MOVES
,
277 X86_TUNE_READ_MODIFY_WRITE
,
278 X86_TUNE_READ_MODIFY
,
279 X86_TUNE_PROMOTE_QIMODE
,
280 X86_TUNE_FAST_PREFIX
,
281 X86_TUNE_SINGLE_STRINGOP
,
282 X86_TUNE_QIMODE_MATH
,
283 X86_TUNE_HIMODE_MATH
,
284 X86_TUNE_PROMOTE_QI_REGS
,
285 X86_TUNE_PROMOTE_HI_REGS
,
288 X86_TUNE_SINGLE_PUSH
,
289 X86_TUNE_DOUBLE_PUSH
,
290 X86_TUNE_INTEGER_DFMODE_MOVES
,
291 X86_TUNE_PARTIAL_REG_DEPENDENCY
,
292 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY
,
293 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL
,
294 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL
,
295 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL
,
296 X86_TUNE_SSE_SPLIT_REGS
,
297 X86_TUNE_SSE_TYPELESS_STORES
,
298 X86_TUNE_SSE_LOAD0_BY_PXOR
,
299 X86_TUNE_MEMORY_MISMATCH_STALL
,
300 X86_TUNE_PROLOGUE_USING_MOVE
,
301 X86_TUNE_EPILOGUE_USING_MOVE
,
304 X86_TUNE_INTER_UNIT_MOVES
,
305 X86_TUNE_INTER_UNIT_CONVERSIONS
,
306 X86_TUNE_FOUR_JUMP_LIMIT
,
310 X86_TUNE_PAD_RETURNS
,
311 X86_TUNE_PAD_SHORT_FUNCTION
,
312 X86_TUNE_EXT_80387_CONSTANTS
,
313 X86_TUNE_SHORTEN_X87_SSE
,
314 X86_TUNE_AVOID_VECTOR_DECODE
,
315 X86_TUNE_PROMOTE_HIMODE_IMUL
,
316 X86_TUNE_SLOW_IMUL_IMM32_MEM
,
317 X86_TUNE_SLOW_IMUL_IMM8
,
318 X86_TUNE_MOVE_M1_VIA_OR
,
319 X86_TUNE_NOT_UNPAIRABLE
,
320 X86_TUNE_NOT_VECTORMODE
,
321 X86_TUNE_USE_VECTOR_FP_CONVERTS
,
322 X86_TUNE_USE_VECTOR_CONVERTS
,
323 X86_TUNE_FUSE_CMP_AND_BRANCH
,
325 X86_TUNE_VECTORIZE_DOUBLE
,
326 X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL
,
327 X86_TUNE_AVX128_OPTIMAL
,
328 X86_TUNE_REASSOC_INT_TO_PARALLEL
,
329 X86_TUNE_REASSOC_FP_TO_PARALLEL
,
334 extern unsigned char ix86_tune_features
[X86_TUNE_LAST
];
336 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
337 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
338 #define TARGET_ZERO_EXTEND_WITH_AND \
339 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
340 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
341 #define TARGET_BRANCH_PREDICTION_HINTS \
342 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
343 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
344 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
345 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
346 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
347 #define TARGET_PARTIAL_FLAG_REG_STALL \
348 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
349 #define TARGET_LCP_STALL \
350 ix86_tune_features[X86_TUNE_LCP_STALL]
351 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
352 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
353 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
354 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
355 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
356 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
357 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
358 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
359 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
360 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
361 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
362 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
363 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
364 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
365 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
366 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
367 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
368 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
369 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
370 #define TARGET_INTEGER_DFMODE_MOVES \
371 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
372 #define TARGET_PARTIAL_REG_DEPENDENCY \
373 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
374 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
375 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
376 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
377 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
378 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
379 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
380 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
381 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
382 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
383 #define TARGET_SSE_TYPELESS_STORES \
384 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
385 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
386 #define TARGET_MEMORY_MISMATCH_STALL \
387 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
388 #define TARGET_PROLOGUE_USING_MOVE \
389 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
390 #define TARGET_EPILOGUE_USING_MOVE \
391 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
392 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
393 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
394 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
395 #define TARGET_INTER_UNIT_CONVERSIONS\
396 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
397 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
398 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
399 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
400 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
401 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
402 #define TARGET_PAD_SHORT_FUNCTION \
403 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
404 #define TARGET_EXT_80387_CONSTANTS \
405 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
406 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
407 #define TARGET_AVOID_VECTOR_DECODE \
408 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
409 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
410 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
411 #define TARGET_SLOW_IMUL_IMM32_MEM \
412 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
413 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
414 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
415 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
416 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
417 #define TARGET_USE_VECTOR_FP_CONVERTS \
418 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
419 #define TARGET_USE_VECTOR_CONVERTS \
420 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
421 #define TARGET_FUSE_CMP_AND_BRANCH \
422 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
423 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
424 #define TARGET_VECTORIZE_DOUBLE \
425 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
426 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
427 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
428 #define TARGET_AVX128_OPTIMAL \
429 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
430 #define TARGET_REASSOC_INT_TO_PARALLEL \
431 ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL]
432 #define TARGET_REASSOC_FP_TO_PARALLEL \
433 ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL]
435 /* Feature tests against the various architecture variations. */
436 enum ix86_arch_indices
{
446 extern unsigned char ix86_arch_features
[X86_ARCH_LAST
];
448 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
449 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
450 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
451 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
452 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
454 /* For sane SSE instruction set generation we need fcomi instruction.
455 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
456 expands to a sequence that includes conditional move. */
457 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
459 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
461 extern int x86_prefetch_sse
;
463 #define TARGET_PREFETCH_SSE x86_prefetch_sse
465 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
467 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
468 #define TARGET_MIX_SSE_I387 \
469 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
471 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
472 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
473 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
474 #define TARGET_SUN_TLS 0
476 #ifndef TARGET_64BIT_DEFAULT
477 #define TARGET_64BIT_DEFAULT 0
479 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
480 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
483 /* Fence to use after loop using storent. */
485 extern tree x86_mfence
;
486 #define FENCE_FOLLOWING_MOVNT x86_mfence
488 /* Once GDB has been enhanced to deal with functions without frame
489 pointers, we can change this to allow for elimination of
490 the frame pointer in leaf functions. */
491 #define TARGET_DEFAULT 0
493 /* Extra bits to force. */
494 #define TARGET_SUBTARGET_DEFAULT 0
495 #define TARGET_SUBTARGET_ISA_DEFAULT 0
497 /* Extra bits to force on w/ 32-bit mode. */
498 #define TARGET_SUBTARGET32_DEFAULT 0
499 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
501 /* Extra bits to force on w/ 64-bit mode. */
502 #define TARGET_SUBTARGET64_DEFAULT 0
503 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
505 /* Replace MACH-O, ifdefs by in-line tests, where possible.
506 (a) Macros defined in config/i386/darwin.h */
507 #define TARGET_MACHO 0
508 #define TARGET_MACHO_BRANCH_ISLANDS 0
509 #define MACHOPIC_ATT_STUB 0
510 /* (b) Macros defined in config/darwin.h */
511 #define MACHO_DYNAMIC_NO_PIC_P 0
512 #define MACHOPIC_INDIRECT 0
513 #define MACHOPIC_PURE 0
515 /* For the Windows 64-bit ABI. */
516 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
518 /* For the Windows 32-bit ABI. */
519 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
521 /* This is re-defined by cygming.h. */
524 /* The default abi used by target. */
525 #define DEFAULT_ABI SYSV_ABI
527 /* Subtargets may reset this to 1 in order to enable 96-bit long double
528 with the rounding mode forced to 53 bits. */
529 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
531 /* -march=native handling only makes sense with compiler running on
532 an x86 or x86_64 chip. If changing this condition, also change
533 the condition in driver-i386.c. */
534 #if defined(__i386__) || defined(__x86_64__)
535 /* In driver-i386.c. */
536 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
537 #define EXTRA_SPEC_FUNCTIONS \
538 { "local_cpu_detect", host_detect_local_cpu },
539 #define HAVE_LOCAL_CPU_DETECT
542 #if TARGET_64BIT_DEFAULT
543 #define OPT_ARCH64 "!m32"
544 #define OPT_ARCH32 "m32"
546 #define OPT_ARCH64 "m64|mx32"
547 #define OPT_ARCH32 "m64|mx32:;"
550 /* Support for configure-time defaults of some command line options.
551 The order here is important so that -march doesn't squash the
552 tune or cpu values. */
553 #define OPTION_DEFAULT_SPECS \
554 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
555 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
556 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
557 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
558 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
559 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
560 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
561 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
562 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
564 /* Specs for the compiler proper */
567 #define CC1_CPU_SPEC_1 ""
569 #ifndef HAVE_LOCAL_CPU_DETECT
570 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
572 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
573 "%{march=native:%>march=native %:local_cpu_detect(arch) \
574 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
575 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
579 /* Target CPU builtins. */
580 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
582 /* Target Pragmas. */
583 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
585 enum target_cpu_default
587 TARGET_CPU_DEFAULT_generic
= 0,
589 TARGET_CPU_DEFAULT_i386
,
590 TARGET_CPU_DEFAULT_i486
,
591 TARGET_CPU_DEFAULT_pentium
,
592 TARGET_CPU_DEFAULT_pentium_mmx
,
593 TARGET_CPU_DEFAULT_pentiumpro
,
594 TARGET_CPU_DEFAULT_pentium2
,
595 TARGET_CPU_DEFAULT_pentium3
,
596 TARGET_CPU_DEFAULT_pentium4
,
597 TARGET_CPU_DEFAULT_pentium_m
,
598 TARGET_CPU_DEFAULT_prescott
,
599 TARGET_CPU_DEFAULT_nocona
,
600 TARGET_CPU_DEFAULT_core2
,
601 TARGET_CPU_DEFAULT_corei7
,
602 TARGET_CPU_DEFAULT_atom
,
604 TARGET_CPU_DEFAULT_geode
,
605 TARGET_CPU_DEFAULT_k6
,
606 TARGET_CPU_DEFAULT_k6_2
,
607 TARGET_CPU_DEFAULT_k6_3
,
608 TARGET_CPU_DEFAULT_athlon
,
609 TARGET_CPU_DEFAULT_athlon_sse
,
610 TARGET_CPU_DEFAULT_k8
,
611 TARGET_CPU_DEFAULT_amdfam10
,
612 TARGET_CPU_DEFAULT_bdver1
,
613 TARGET_CPU_DEFAULT_bdver2
,
614 TARGET_CPU_DEFAULT_btver1
,
615 TARGET_CPU_DEFAULT_btver2
,
617 TARGET_CPU_DEFAULT_max
621 #define CC1_SPEC "%(cc1_cpu) "
624 /* This macro defines names of additional specifications to put in the
625 specs that can be used in various specifications like CC1_SPEC. Its
626 definition is an initializer with a subgrouping for each command option.
628 Each subgrouping contains a string constant, that defines the
629 specification name, and a string constant that used by the GCC driver
632 Do not define this macro if it does not need to do anything. */
634 #ifndef SUBTARGET_EXTRA_SPECS
635 #define SUBTARGET_EXTRA_SPECS
638 #define EXTRA_SPECS \
639 { "cc1_cpu", CC1_CPU_SPEC }, \
640 SUBTARGET_EXTRA_SPECS
643 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
644 FPU, assume that the fpcw is set to extended precision; when using
645 only SSE, rounding is correct; when using both SSE and the FPU,
646 the rounding precision is indeterminate, since either may be chosen
647 apparently at random. */
648 #define TARGET_FLT_EVAL_METHOD \
649 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
651 /* Whether to allow x87 floating-point arithmetic on MODE (one of
652 SFmode, DFmode and XFmode) in the current excess precision
654 #define X87_ENABLE_ARITH(MODE) \
655 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
657 /* Likewise, whether to allow direct conversions from integer mode
658 IMODE (HImode, SImode or DImode) to MODE. */
659 #define X87_ENABLE_FLOAT(MODE, IMODE) \
660 (flag_excess_precision == EXCESS_PRECISION_FAST \
661 || (MODE) == XFmode \
662 || ((MODE) == DFmode && (IMODE) == SImode) \
663 || (IMODE) == HImode)
665 /* target machine storage layout */
667 #define SHORT_TYPE_SIZE 16
668 #define INT_TYPE_SIZE 32
669 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
670 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
671 #define LONG_LONG_TYPE_SIZE 64
672 #define FLOAT_TYPE_SIZE 32
673 #define DOUBLE_TYPE_SIZE 64
674 #define LONG_DOUBLE_TYPE_SIZE 80
676 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
678 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
679 #define MAX_BITS_PER_WORD 64
681 #define MAX_BITS_PER_WORD 32
684 /* Define this if most significant byte of a word is the lowest numbered. */
685 /* That is true on the 80386. */
687 #define BITS_BIG_ENDIAN 0
689 /* Define this if most significant byte of a word is the lowest numbered. */
690 /* That is not true on the 80386. */
691 #define BYTES_BIG_ENDIAN 0
693 /* Define this if most significant word of a multiword number is the lowest
695 /* Not true for 80386 */
696 #define WORDS_BIG_ENDIAN 0
698 /* Width of a word, in units (bytes). */
699 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
702 #define MIN_UNITS_PER_WORD 4
705 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
706 #define PARM_BOUNDARY BITS_PER_WORD
708 /* Boundary (in *bits*) on which stack pointer should be aligned. */
709 #define STACK_BOUNDARY \
710 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
712 /* Stack boundary of the main function guaranteed by OS. */
713 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
715 /* Minimum stack boundary. */
716 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32)
718 /* Boundary (in *bits*) on which the stack pointer prefers to be
719 aligned; the compiler cannot rely on having this alignment. */
720 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
722 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
723 both 32bit and 64bit, to support codes that need 128 bit stack
724 alignment for SSE instructions, but can't realign the stack. */
725 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
727 /* 1 if -mstackrealign should be turned on by default. It will
728 generate an alternate prologue and epilogue that realigns the
729 runtime stack if nessary. This supports mixing codes that keep a
730 4-byte aligned stack, as specified by i386 psABI, with codes that
731 need a 16-byte aligned stack, as required by SSE instructions. */
732 #define STACK_REALIGN_DEFAULT 0
734 /* Boundary (in *bits*) on which the incoming stack is aligned. */
735 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
737 /* According to Windows x64 software convention, the maximum stack allocatable
738 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
739 instructions allowed to adjust the stack pointer in the epilog, forcing the
740 use of frame pointer for frames larger than 2 GB. This theorical limit
741 is reduced by 256, an over-estimated upper bound for the stack use by the
743 We define only one threshold for both the prolog and the epilog. When the
744 frame size is larger than this threshold, we allocate the area to save SSE
745 regs, then save them, and then allocate the remaining. There is no SEH
746 unwind info for this later allocation. */
747 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
749 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
750 mandatory for the 64-bit ABI, and may or may not be true for other
751 operating systems. */
752 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
754 /* Minimum allocation boundary for the code of a function. */
755 #define FUNCTION_BOUNDARY 8
757 /* C++ stores the virtual bit in the lowest bit of function pointers. */
758 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
760 /* Minimum size in bits of the largest boundary to which any
761 and all fundamental data types supported by the hardware
762 might need to be aligned. No data type wants to be aligned
765 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
766 and Pentium Pro XFmode values at 128 bit boundaries. */
768 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128)
770 /* Maximum stack alignment. */
771 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
773 /* Alignment value for attribute ((aligned)). It is a constant since
774 it is the part of the ABI. We shouldn't change it with -mavx. */
775 #define ATTRIBUTE_ALIGNED_VALUE 128
777 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
778 #define ALIGN_MODE_128(MODE) \
779 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
781 /* The published ABIs say that doubles should be aligned on word
782 boundaries, so lower the alignment for structure fields unless
783 -malign-double is set. */
785 /* ??? Blah -- this macro is used directly by libobjc. Since it
786 supports no vector modes, cut out the complexity and fall back
787 on BIGGEST_FIELD_ALIGNMENT. */
788 #ifdef IN_TARGET_LIBS
790 #define BIGGEST_FIELD_ALIGNMENT 128
792 #define BIGGEST_FIELD_ALIGNMENT 32
795 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
796 x86_field_alignment (FIELD, COMPUTED)
799 /* If defined, a C expression to compute the alignment given to a
800 constant that is being placed in memory. EXP is the constant
801 and ALIGN is the alignment that the object would ordinarily have.
802 The value of this macro is used instead of that alignment to align
805 If this macro is not defined, then ALIGN is used.
807 The typical use of this macro is to increase alignment for string
808 constants to be word aligned so that `strcpy' calls that copy
809 constants can be done inline. */
811 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
813 /* If defined, a C expression to compute the alignment for a static
814 variable. TYPE is the data type, and ALIGN is the alignment that
815 the object would ordinarily have. The value of this macro is used
816 instead of that alignment to align the object.
818 If this macro is not defined, then ALIGN is used.
820 One use of this macro is to increase alignment of medium-size
821 data to make it all fit in fewer cache lines. Another is to
822 cause character arrays to be word-aligned so that `strcpy' calls
823 that copy constants to character arrays can be done inline. */
825 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
827 /* If defined, a C expression to compute the alignment for a local
828 variable. TYPE is the data type, and ALIGN is the alignment that
829 the object would ordinarily have. The value of this macro is used
830 instead of that alignment to align the object.
832 If this macro is not defined, then ALIGN is used.
834 One use of this macro is to increase alignment of medium-size
835 data to make it all fit in fewer cache lines. */
837 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
838 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
840 /* If defined, a C expression to compute the alignment for stack slot.
841 TYPE is the data type, MODE is the widest mode available, and ALIGN
842 is the alignment that the slot would ordinarily have. The value of
843 this macro is used instead of that alignment to align the slot.
845 If this macro is not defined, then ALIGN is used when TYPE is NULL,
846 Otherwise, LOCAL_ALIGNMENT will be used.
848 One use of this macro is to set alignment of stack slot to the
849 maximum alignment of all possible modes which the slot may have. */
851 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
852 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
854 /* If defined, a C expression to compute the alignment for a local
857 If this macro is not defined, then
858 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
860 One use of this macro is to increase alignment of medium-size
861 data to make it all fit in fewer cache lines. */
863 #define LOCAL_DECL_ALIGNMENT(DECL) \
864 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
866 /* If defined, a C expression to compute the minimum required alignment
867 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
868 MODE, assuming normal alignment ALIGN.
870 If this macro is not defined, then (ALIGN) will be used. */
872 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
873 ix86_minimum_alignment (EXP, MODE, ALIGN)
876 /* Set this nonzero if move instructions will actually fail to work
877 when given unaligned data. */
878 #define STRICT_ALIGNMENT 0
880 /* If bit field type is int, don't let it cross an int,
881 and give entire struct the alignment of an int. */
882 /* Required on the 386 since it doesn't have bit-field insns. */
883 #define PCC_BITFIELD_TYPE_MATTERS 1
885 /* Standard register usage. */
887 /* This processor has special stack-like registers. See reg-stack.c
892 #define IS_STACK_MODE(MODE) \
893 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \
894 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
897 /* Number of actual hardware registers.
898 The hardware registers are assigned numbers for the compiler
899 from 0 to just below FIRST_PSEUDO_REGISTER.
900 All registers that the compiler knows about must be given numbers,
901 even those that are not normally considered general registers.
903 In the 80386 we give the 8 general purpose registers the numbers 0-7.
904 We number the floating point registers 8-15.
905 Note that registers 0-7 can be accessed as a short or int,
906 while only 0-3 may be used with byte `mov' instructions.
908 Reg 16 does not correspond to any hardware register, but instead
909 appears in the RTL as an argument pointer prior to reload, and is
910 eliminated during reloading in favor of either the stack or frame
913 #define FIRST_PSEUDO_REGISTER 53
915 /* Number of hardware registers that go into the DWARF-2 unwind info.
916 If not defined, equals FIRST_PSEUDO_REGISTER. */
918 #define DWARF_FRAME_REGISTERS 17
920 /* 1 for registers that have pervasive standard uses
921 and are not available for the register allocator.
922 On the 80386, the stack pointer is such, as is the arg pointer.
924 The value is zero if the register is not fixed on either 32 or
925 64 bit targets, one if the register if fixed on both 32 and 64
926 bit targets, two if it is only fixed on 32bit targets and three
927 if its only fixed on 64bit targets.
928 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
930 #define FIXED_REGISTERS \
931 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
932 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
933 /*arg,flags,fpsr,fpcr,frame*/ \
935 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
936 0, 0, 0, 0, 0, 0, 0, 0, \
937 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
938 0, 0, 0, 0, 0, 0, 0, 0, \
939 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
940 2, 2, 2, 2, 2, 2, 2, 2, \
941 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
942 2, 2, 2, 2, 2, 2, 2, 2 }
945 /* 1 for registers not available across function calls.
946 These must include the FIXED_REGISTERS and also any
947 registers that can be used without being saved.
948 The latter must include the registers where values are returned
949 and the register where structure-value addresses are passed.
950 Aside from that, you can include as many other registers as you like.
952 The value is zero if the register is not call used on either 32 or
953 64 bit targets, one if the register if call used on both 32 and 64
954 bit targets, two if it is only call used on 32bit targets and three
955 if its only call used on 64bit targets.
956 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
958 #define CALL_USED_REGISTERS \
959 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
960 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
961 /*arg,flags,fpsr,fpcr,frame*/ \
963 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
964 1, 1, 1, 1, 1, 1, 1, 1, \
965 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
966 1, 1, 1, 1, 1, 1, 1, 1, \
967 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
968 1, 1, 1, 1, 2, 2, 2, 2, \
969 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
970 1, 1, 1, 1, 1, 1, 1, 1 }
972 /* Order in which to allocate registers. Each register must be
973 listed once, even those in FIXED_REGISTERS. List frame pointer
974 late and fixed registers last. Note that, in general, we prefer
975 registers listed in CALL_USED_REGISTERS, keeping the others
976 available for storage of persistent values.
978 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
979 so this is just empty initializer for array. */
981 #define REG_ALLOC_ORDER \
982 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
983 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
984 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
987 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
988 to be rearranged based on a particular function. When using sse math,
989 we want to allocate SSE before x87 registers and vice versa. */
991 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
994 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
996 /* Return number of consecutive hard regs needed starting at reg REGNO
997 to hold something of mode MODE.
998 This is ordinarily the length in words of a value of mode MODE
999 but can be less for certain modes in special long registers.
1001 Actually there are no two word move instructions for consecutive
1002 registers. And only registers 0-3 may have mov byte instructions
1005 #define HARD_REGNO_NREGS(REGNO, MODE) \
1006 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1007 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1008 : ((MODE) == XFmode \
1009 ? (TARGET_64BIT ? 2 : 3) \
1010 : (MODE) == XCmode \
1011 ? (TARGET_64BIT ? 4 : 6) \
1012 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1014 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1015 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1016 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1018 : ((MODE) == XFmode || (MODE) == XCmode)) \
1021 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1023 #define VALID_AVX256_REG_MODE(MODE) \
1024 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1025 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1026 || (MODE) == V4DFmode)
1028 #define VALID_SSE2_REG_MODE(MODE) \
1029 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1030 || (MODE) == V2DImode || (MODE) == DFmode)
1032 #define VALID_SSE_REG_MODE(MODE) \
1033 ((MODE) == V1TImode || (MODE) == TImode \
1034 || (MODE) == V4SFmode || (MODE) == V4SImode \
1035 || (MODE) == SFmode || (MODE) == TFmode)
1037 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1038 ((MODE) == V2SFmode || (MODE) == SFmode)
1040 #define VALID_MMX_REG_MODE(MODE) \
1041 ((MODE == V1DImode) || (MODE) == DImode \
1042 || (MODE) == V2SImode || (MODE) == SImode \
1043 || (MODE) == V4HImode || (MODE) == V8QImode)
1045 #define VALID_DFP_MODE_P(MODE) \
1046 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1048 #define VALID_FP_MODE_P(MODE) \
1049 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1050 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1052 #define VALID_INT_MODE_P(MODE) \
1053 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1054 || (MODE) == DImode \
1055 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1056 || (MODE) == CDImode \
1057 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1058 || (MODE) == TFmode || (MODE) == TCmode)))
1060 /* Return true for modes passed in SSE registers. */
1061 #define SSE_REG_MODE_P(MODE) \
1062 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1063 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1064 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1065 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1066 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1067 || (MODE) == V2TImode)
1069 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1071 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1072 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1074 /* Value is 1 if it is a good idea to tie two pseudo registers
1075 when one has mode MODE1 and one has mode MODE2.
1076 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1077 for any hard reg, then this must be 0 for correct output. */
1079 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1081 /* It is possible to write patterns to move flags; but until someone
1083 #define AVOID_CCMODE_COPIES
1085 /* Specify the modes required to caller save a given hard regno.
1086 We do this on i386 to prevent flags from being saved at all.
1088 Kill any attempts to combine saving of modes. */
1090 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1091 (CC_REGNO_P (REGNO) ? VOIDmode \
1092 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1093 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1094 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1095 : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO)) ? SImode \
1098 /* The only ABI that saves SSE registers across calls is Win64 (thus no
1099 need to check the current ABI here), and with AVX enabled Win64 only
1100 guarantees that the low 16 bytes are saved. */
1101 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1102 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16)
1104 /* Specify the registers used for certain standard purposes.
1105 The values of these macros are register numbers. */
1107 /* on the 386 the pc register is %eip, and is not usable as a general
1108 register. The ordinary mov instructions won't work */
1109 /* #define PC_REGNUM */
1111 /* Register to use for pushing function arguments. */
1112 #define STACK_POINTER_REGNUM 7
1114 /* Base register for access to local variables of the function. */
1115 #define HARD_FRAME_POINTER_REGNUM 6
1117 /* Base register for access to local variables of the function. */
1118 #define FRAME_POINTER_REGNUM 20
1120 /* First floating point reg */
1121 #define FIRST_FLOAT_REG 8
1123 /* First & last stack-like regs */
1124 #define FIRST_STACK_REG FIRST_FLOAT_REG
1125 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1127 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1128 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1130 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1131 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1133 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1134 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1136 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1137 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1139 /* Override this in other tm.h files to cope with various OS lossage
1140 requiring a frame pointer. */
1141 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1142 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1145 /* Make sure we can access arbitrary call frames. */
1146 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1148 /* Base register for access to arguments of the function. */
1149 #define ARG_POINTER_REGNUM 16
1151 /* Register to hold the addressing base for position independent
1152 code access to data items. We don't use PIC pointer for 64bit
1153 mode. Define the regnum to dummy value to prevent gcc from
1154 pessimizing code dealing with EBX.
1156 To avoid clobbering a call-saved register unnecessarily, we renumber
1157 the pic register when possible. The change is visible after the
1158 prologue has been emitted. */
1160 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1162 #define PIC_OFFSET_TABLE_REGNUM \
1163 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1164 || !flag_pic ? INVALID_REGNUM \
1165 : reload_completed ? REGNO (pic_offset_table_rtx) \
1166 : REAL_PIC_OFFSET_TABLE_REGNUM)
1168 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1170 /* This is overridden by <cygwin.h>. */
1171 #define MS_AGGREGATE_RETURN 0
1173 #define KEEP_AGGREGATE_RETURN_POINTER 0
1175 /* Define the classes of registers for register constraints in the
1176 machine description. Also define ranges of constants.
1178 One of the classes must always be named ALL_REGS and include all hard regs.
1179 If there is more than one class, another class must be named NO_REGS
1180 and contain no registers.
1182 The name GENERAL_REGS must be the name of a class (or an alias for
1183 another name such as ALL_REGS). This is the class of registers
1184 that is allowed by "g" or "r" in a register constraint.
1185 Also, registers outside this class are allocated only when
1186 instructions express preferences for them.
1188 The classes must be numbered in nondecreasing order; that is,
1189 a larger-numbered class must never be contained completely
1190 in a smaller-numbered class.
1192 For any two classes, it is very desirable that there be another
1193 class that represents their union.
1195 It might seem that class BREG is unnecessary, since no useful 386
1196 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1197 and the "b" register constraint is useful in asms for syscalls.
1199 The flags, fpsr and fpcr registers are in no class. */
1204 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
1205 AD_REGS
, /* %eax/%edx for DImode */
1206 CLOBBERED_REGS
, /* call-clobbered integers */
1207 Q_REGS
, /* %eax %ebx %ecx %edx */
1208 NON_Q_REGS
, /* %esi %edi %ebp %esp */
1209 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1210 LEGACY_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1211 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1212 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1213 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
1224 ALL_REGS
, LIM_REG_CLASSES
1227 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1229 #define INTEGER_CLASS_P(CLASS) \
1230 reg_class_subset_p ((CLASS), GENERAL_REGS)
1231 #define FLOAT_CLASS_P(CLASS) \
1232 reg_class_subset_p ((CLASS), FLOAT_REGS)
1233 #define SSE_CLASS_P(CLASS) \
1234 reg_class_subset_p ((CLASS), SSE_REGS)
1235 #define MMX_CLASS_P(CLASS) \
1236 ((CLASS) == MMX_REGS)
1237 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1238 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1239 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1240 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1241 #define MAYBE_SSE_CLASS_P(CLASS) \
1242 reg_classes_intersect_p (SSE_REGS, (CLASS))
1243 #define MAYBE_MMX_CLASS_P(CLASS) \
1244 reg_classes_intersect_p (MMX_REGS, (CLASS))
1246 #define Q_CLASS_P(CLASS) \
1247 reg_class_subset_p ((CLASS), Q_REGS)
1249 /* Give names of register classes as strings for dump file. */
1251 #define REG_CLASS_NAMES \
1253 "AREG", "DREG", "CREG", "BREG", \
1257 "Q_REGS", "NON_Q_REGS", \
1261 "FP_TOP_REG", "FP_SECOND_REG", \
1266 "FP_TOP_SSE_REGS", \
1267 "FP_SECOND_SSE_REGS", \
1271 "FLOAT_INT_SSE_REGS", \
1274 /* Define which registers fit in which classes. This is an initializer
1275 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1277 Note that the default setting of CLOBBERED_REGS is for 32-bit; this
1278 is adjusted by TARGET_CONDITIONAL_REGISTER_USAGE for the 64-bit ABI
1281 #define REG_CLASS_CONTENTS \
1283 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1284 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1285 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1286 { 0x03, 0x0 }, /* AD_REGS */ \
1287 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \
1288 { 0x0f, 0x0 }, /* Q_REGS */ \
1289 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1290 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1291 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1292 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1293 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1294 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1295 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1296 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1297 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1298 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1299 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1300 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1301 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1302 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1303 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1304 { 0xffffffff,0x1fffff } \
1307 /* The same information, inverted:
1308 Return the class number of the smallest class containing
1309 reg number REGNO. This could be a conditional expression
1310 or could index an array. */
1312 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1314 /* When this hook returns true for MODE, the compiler allows
1315 registers explicitly used in the rtl to be used as spill registers
1316 but prevents the compiler from extending the lifetime of these
1318 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1320 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1321 #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG)
1323 #define GENERAL_REG_P(X) \
1324 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1325 #define GENERAL_REGNO_P(N) \
1326 (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N))
1328 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1329 #define ANY_QI_REGNO_P(N) \
1330 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1332 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1333 #define REX_INT_REGNO_P(N) \
1334 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1336 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1337 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1339 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1340 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1342 #define X87_FLOAT_MODE_P(MODE) \
1343 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1345 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1346 #define SSE_REGNO_P(N) \
1347 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1348 || REX_SSE_REGNO_P (N))
1350 #define REX_SSE_REGNO_P(N) \
1351 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1353 #define SSE_REGNO(N) \
1354 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1356 #define SSE_FLOAT_MODE_P(MODE) \
1357 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1359 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1360 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1361 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1363 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1364 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1366 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1367 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1369 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG)
1371 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1372 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1374 /* The class value for index registers, and the one for base regs. */
1376 #define INDEX_REG_CLASS INDEX_REGS
1377 #define BASE_REG_CLASS GENERAL_REGS
1379 /* Place additional restrictions on the register class to use when it
1380 is necessary to be able to hold a value of mode MODE in a reload
1381 register for which class CLASS would ordinarily be used. */
1383 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1384 ((MODE) == QImode && !TARGET_64BIT \
1385 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1386 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1389 /* If we are copying between general and FP registers, we need a memory
1390 location. The same is true for SSE and MMX registers. */
1391 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1392 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1394 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1395 There is no need to emit full 64 bit move on 64 bit targets
1396 for integral modes that can be moved using 32 bit move. */
1397 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1398 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1399 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1402 /* Return a class of registers that cannot change FROM mode to TO mode. */
1404 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1405 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1407 /* Stack layout; function entry, exit and calling. */
1409 /* Define this if pushing a word on the stack
1410 makes the stack pointer a smaller address. */
1411 #define STACK_GROWS_DOWNWARD
1413 /* Define this to nonzero if the nominal address of the stack frame
1414 is at the high-address end of the local variables;
1415 that is, each additional local variable allocated
1416 goes at a more negative offset in the frame. */
1417 #define FRAME_GROWS_DOWNWARD 1
1419 /* Offset within stack frame to start allocating local variables at.
1420 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1421 first local allocated. Otherwise, it is the offset to the BEGINNING
1422 of the first local allocated. */
1423 #define STARTING_FRAME_OFFSET 0
1425 /* If we generate an insn to push BYTES bytes, this says how many the stack
1426 pointer really advances by. On 386, we have pushw instruction that
1427 decrements by exactly 2 no matter what the position was, there is no pushb.
1429 But as CIE data alignment factor on this arch is -4 for 32bit targets
1430 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1431 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1433 #define PUSH_ROUNDING(BYTES) \
1434 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
1436 /* If defined, the maximum amount of space required for outgoing arguments
1437 will be computed and placed into the variable `crtl->outgoing_args_size'.
1438 No space will be pushed onto the stack for each call; instead, the
1439 function prologue should increase the stack frame size by this amount.
1441 64-bit MS ABI seem to require 16 byte alignment everywhere except for
1442 function prologue and apilogue. This is not possible without
1443 ACCUMULATE_OUTGOING_ARGS. */
1445 #define ACCUMULATE_OUTGOING_ARGS \
1446 (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI)
1448 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1449 instructions to pass outgoing arguments. */
1451 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1453 /* We want the stack and args grow in opposite directions, even if
1455 #define PUSH_ARGS_REVERSED 1
1457 /* Offset of first parameter from the argument pointer register value. */
1458 #define FIRST_PARM_OFFSET(FNDECL) 0
1460 /* Define this macro if functions should assume that stack space has been
1461 allocated for arguments even when their values are passed in registers.
1463 The value of this macro is the size, in bytes, of the area reserved for
1464 arguments passed in registers for the function represented by FNDECL.
1466 This space can be allocated by the caller, or be a part of the
1467 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1469 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1471 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1472 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1474 /* Define how to find the value returned by a library function
1475 assuming the value has mode MODE. */
1477 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1479 /* Define the size of the result block used for communication between
1480 untyped_call and untyped_return. The block contains a DImode value
1481 followed by the block used by fnsave and frstor. */
1483 #define APPLY_RESULT_SIZE (8+108)
1485 /* 1 if N is a possible register number for function argument passing. */
1486 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1488 /* Define a data type for recording info about an argument list
1489 during the scan of that argument list. This data type should
1490 hold all necessary information about the function itself
1491 and about the args processed so far, enough to enable macros
1492 such as FUNCTION_ARG to determine where the next arg should go. */
1494 typedef struct ix86_args
{
1495 int words
; /* # words passed so far */
1496 int nregs
; /* # registers available for passing */
1497 int regno
; /* next available register number */
1498 int fastcall
; /* fastcall or thiscall calling convention
1500 int sse_words
; /* # sse words passed so far */
1501 int sse_nregs
; /* # sse registers available for passing */
1502 int warn_avx
; /* True when we want to warn about AVX ABI. */
1503 int warn_sse
; /* True when we want to warn about SSE ABI. */
1504 int warn_mmx
; /* True when we want to warn about MMX ABI. */
1505 int sse_regno
; /* next available sse register number */
1506 int mmx_words
; /* # mmx words passed so far */
1507 int mmx_nregs
; /* # mmx registers available for passing */
1508 int mmx_regno
; /* next available mmx register number */
1509 int maybe_vaarg
; /* true for calls to possibly vardic fncts. */
1510 int caller
; /* true if it is caller. */
1511 int float_in_sse
; /* Set to 1 or 2 for 32bit targets if
1512 SFmode/DFmode arguments should be passed
1513 in SSE registers. Otherwise 0. */
1514 enum calling_abi call_abi
; /* Set to SYSV_ABI for sysv abi. Otherwise
1515 MS_ABI for ms abi. */
1518 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1519 for a call to a function whose data type is FNTYPE.
1520 For a library call, FNTYPE is 0. */
1522 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1523 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1524 (N_NAMED_ARGS) != -1)
1526 /* Output assembler code to FILE to increment profiler label # LABELNO
1527 for profiling a function entry. */
1529 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1531 #define MCOUNT_NAME "_mcount"
1533 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1535 #define PROFILE_COUNT_REGISTER "edx"
1537 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1538 the stack pointer does not matter. The value is tested only in
1539 functions that have frame pointers.
1540 No definition is equivalent to always zero. */
1541 /* Note on the 386 it might be more efficient not to define this since
1542 we have to restore it ourselves from the frame pointer, in order to
1545 #define EXIT_IGNORE_STACK 1
1547 /* Output assembler code for a block containing the constant parts
1548 of a trampoline, leaving space for the variable parts. */
1550 /* On the 386, the trampoline contains two instructions:
1553 The trampoline is generated entirely at runtime. The operand of JMP
1554 is the address of FUNCTION relative to the instruction following the
1555 JMP (which is 5 bytes long). */
1557 /* Length in units of the trampoline for entering a nested function. */
1559 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1561 /* Definitions for register eliminations.
1563 This is an array of structures. Each structure initializes one pair
1564 of eliminable registers. The "from" register number is given first,
1565 followed by "to". Eliminations of the same "from" register are listed
1566 in order of preference.
1568 There are two registers that can always be eliminated on the i386.
1569 The frame pointer and the arg pointer can be replaced by either the
1570 hard frame pointer or to the stack pointer, depending upon the
1571 circumstances. The hard frame pointer is not used before reload and
1572 so it is not eligible for elimination. */
1574 #define ELIMINABLE_REGS \
1575 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1576 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1577 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1578 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1580 /* Define the offset between two registers, one to be eliminated, and the other
1581 its replacement, at the start of a routine. */
1583 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1584 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1586 /* Addressing modes, and classification of registers for them. */
1588 /* Macros to check register numbers against specific register classes. */
1590 /* These assume that REGNO is a hard or pseudo reg number.
1591 They give nonzero only if REGNO is a hard reg of the suitable class
1592 or a pseudo reg currently allocated to a suitable hard reg.
1593 Since they use reg_renumber, they are safe only once reg_renumber
1594 has been allocated, which happens in local-alloc.c. */
1596 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1597 ((REGNO) < STACK_POINTER_REGNUM \
1598 || REX_INT_REGNO_P (REGNO) \
1599 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1600 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1602 #define REGNO_OK_FOR_BASE_P(REGNO) \
1603 (GENERAL_REGNO_P (REGNO) \
1604 || (REGNO) == ARG_POINTER_REGNUM \
1605 || (REGNO) == FRAME_POINTER_REGNUM \
1606 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1608 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1609 and check its validity for a certain class.
1610 We have two alternate definitions for each of them.
1611 The usual definition accepts all pseudo regs; the other rejects
1612 them unless they have been allocated suitable hard regs.
1613 The symbol REG_OK_STRICT causes the latter definition to be used.
1615 Most source files want to accept pseudo regs in the hope that
1616 they will get allocated to the class that the insn wants them to be in.
1617 Source files for reload pass need to be strict.
1618 After reload, it makes no difference, since pseudo regs have
1619 been eliminated by then. */
1622 /* Non strict versions, pseudos are ok. */
1623 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1624 (REGNO (X) < STACK_POINTER_REGNUM \
1625 || REX_INT_REGNO_P (REGNO (X)) \
1626 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1628 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1629 (GENERAL_REGNO_P (REGNO (X)) \
1630 || REGNO (X) == ARG_POINTER_REGNUM \
1631 || REGNO (X) == FRAME_POINTER_REGNUM \
1632 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1634 /* Strict versions, hard registers only */
1635 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1636 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1638 #ifndef REG_OK_STRICT
1639 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1640 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1643 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1644 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1647 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1648 that is a valid memory address for an instruction.
1649 The MODE argument is the machine mode for the MEM expression
1650 that wants to use this address.
1652 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1653 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1655 See legitimize_pic_address in i386.c for details as to what
1656 constitutes a legitimate address when -fpic is used. */
1658 #define MAX_REGS_PER_ADDRESS 2
1660 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1662 /* Try a machine-dependent way of reloading an illegitimate address
1663 operand. If we find one, push the reload and jump to WIN. This
1664 macro is used in only one place: `find_reloads_address' in reload.c. */
1666 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \
1668 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \
1669 (int)(TYPE), (INDL))) \
1673 /* If defined, a C expression to determine the base term of address X.
1674 This macro is used in only one place: `find_base_term' in alias.c.
1676 It is always safe for this macro to not be defined. It exists so
1677 that alias analysis can understand machine-dependent addresses.
1679 The typical use of this macro is to handle addresses containing
1680 a label_ref or symbol_ref within an UNSPEC. */
1682 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1684 /* Nonzero if the constant value X is a legitimate general operand
1685 when generating PIC code. It is given that flag_pic is on and
1686 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1688 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1690 #define SYMBOLIC_CONST(X) \
1691 (GET_CODE (X) == SYMBOL_REF \
1692 || GET_CODE (X) == LABEL_REF \
1693 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1695 /* Max number of args passed in registers. If this is more than 3, we will
1696 have problems with ebx (register #4), since it is a caller save register and
1697 is also used as the pic register in ELF. So for now, don't allow more than
1698 3 registers to be passed in registers. */
1700 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1701 #define X86_64_REGPARM_MAX 6
1702 #define X86_64_MS_REGPARM_MAX 4
1704 #define X86_32_REGPARM_MAX 3
1706 #define REGPARM_MAX \
1708 ? (TARGET_64BIT_MS_ABI \
1709 ? X86_64_MS_REGPARM_MAX \
1710 : X86_64_REGPARM_MAX) \
1711 : X86_32_REGPARM_MAX)
1713 #define X86_64_SSE_REGPARM_MAX 8
1714 #define X86_64_MS_SSE_REGPARM_MAX 4
1716 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1718 #define SSE_REGPARM_MAX \
1720 ? (TARGET_64BIT_MS_ABI \
1721 ? X86_64_MS_SSE_REGPARM_MAX \
1722 : X86_64_SSE_REGPARM_MAX) \
1723 : X86_32_SSE_REGPARM_MAX)
1725 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1727 /* Specify the machine mode that this machine uses
1728 for the index in the tablejump instruction. */
1729 #define CASE_VECTOR_MODE \
1730 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1732 /* Define this as 1 if `char' should by default be signed; else as 0. */
1733 #define DEFAULT_SIGNED_CHAR 1
1735 /* Max number of bytes we can move from memory to memory
1736 in one reasonably fast instruction. */
1739 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1740 move efficiently, as opposed to MOVE_MAX which is the maximum
1741 number of bytes we can move with a single instruction. */
1742 #define MOVE_MAX_PIECES UNITS_PER_WORD
1744 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1745 move-instruction pairs, we will do a movmem or libcall instead.
1746 Increasing the value will always make code faster, but eventually
1747 incurs high cost in increased code size.
1749 If you don't define this, a reasonable default is used. */
1751 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1753 /* If a clear memory operation would take CLEAR_RATIO or more simple
1754 move-instruction sequences, we will do a clrmem or libcall instead. */
1756 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1758 /* Define if shifts truncate the shift count which implies one can
1759 omit a sign-extension or zero-extension of a shift count.
1761 On i386, shifts do truncate the count. But bit test instructions
1762 take the modulo of the bit offset operand. */
1764 /* #define SHIFT_COUNT_TRUNCATED */
1766 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1767 is done just by pretending it is already truncated. */
1768 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1770 /* A macro to update M and UNSIGNEDP when an object whose type is
1771 TYPE and which has the specified mode and signedness is to be
1772 stored in a register. This macro is only called when TYPE is a
1775 On i386 it is sometimes useful to promote HImode and QImode
1776 quantities to SImode. The choice depends on target type. */
1778 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1780 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1781 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1785 /* Specify the machine mode that pointers have.
1786 After generation of rtl, the compiler makes no further distinction
1787 between pointers and any other objects of this machine mode. */
1788 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1790 /* A C expression whose value is zero if pointers that need to be extended
1791 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1792 greater then zero if they are zero-extended and less then zero if the
1793 ptr_extend instruction should be used. */
1795 #define POINTERS_EXTEND_UNSIGNED 1
1797 /* A function address in a call instruction
1798 is a byte address (for indexing purposes)
1799 so give the MEM rtx a byte's mode. */
1800 #define FUNCTION_MODE QImode
1803 /* A C expression for the cost of a branch instruction. A value of 1
1804 is the default; other values are interpreted relative to that. */
1806 #define BRANCH_COST(speed_p, predictable_p) \
1807 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1809 /* Define this macro as a C expression which is nonzero if accessing
1810 less than a word of memory (i.e. a `char' or a `short') is no
1811 faster than accessing a word of memory, i.e., if such access
1812 require more than one instruction or if there is no difference in
1813 cost between byte and (aligned) word loads.
1815 When this macro is not defined, the compiler will access a field by
1816 finding the smallest containing object; when it is defined, a
1817 fullword load will be used if alignment permits. Unless bytes
1818 accesses are faster than word accesses, using word accesses is
1819 preferable since it may eliminate subsequent memory access if
1820 subsequent accesses occur to other fields in the same word of the
1821 structure, but to different bytes. */
1823 #define SLOW_BYTE_ACCESS 0
1825 /* Nonzero if access to memory by shorts is slow and undesirable. */
1826 #define SLOW_SHORT_ACCESS 0
1828 /* Define this macro to be the value 1 if unaligned accesses have a
1829 cost many times greater than aligned accesses, for example if they
1830 are emulated in a trap handler.
1832 When this macro is nonzero, the compiler will act as if
1833 `STRICT_ALIGNMENT' were nonzero when generating code for block
1834 moves. This can cause significantly more instructions to be
1835 produced. Therefore, do not set this macro nonzero if unaligned
1836 accesses only add a cycle or two to the time for a memory access.
1838 If the value of this macro is always zero, it need not be defined. */
1840 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1842 /* Define this macro if it is as good or better to call a constant
1843 function address than to call an address kept in a register.
1845 Desirable on the 386 because a CALL with a constant address is
1846 faster than one with a register address. */
1848 #define NO_FUNCTION_CSE
1850 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1851 return the mode to be used for the comparison.
1853 For floating-point equality comparisons, CCFPEQmode should be used.
1854 VOIDmode should be used in all other cases.
1856 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1857 possible, to allow for more combinations. */
1859 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1861 /* Return nonzero if MODE implies a floating point inequality can be
1864 #define REVERSIBLE_CC_MODE(MODE) 1
1866 /* A C expression whose value is reversed condition code of the CODE for
1867 comparison done in CC_MODE mode. */
1868 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1871 /* Control the assembler format that we output, to the extent
1872 this does not vary between assemblers. */
1874 /* How to refer to registers in assembler output.
1875 This sequence is indexed by compiler's hard-register-number (see above). */
1877 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1878 For non floating point regs, the following are the HImode names.
1880 For float regs, the stack top is sometimes referred to as "%st(0)"
1881 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1884 #define HI_REGISTER_NAMES \
1885 {"ax","dx","cx","bx","si","di","bp","sp", \
1886 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1887 "argp", "flags", "fpsr", "fpcr", "frame", \
1888 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1889 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1890 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1891 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1893 #define REGISTER_NAMES HI_REGISTER_NAMES
1895 /* Table of additional register names to use in user input. */
1897 #define ADDITIONAL_REGISTER_NAMES \
1898 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1899 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1900 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1901 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1902 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1903 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1905 /* Note we are omitting these since currently I don't know how
1906 to get gcc to use these, since they want the same but different
1907 number as al, and ax.
1910 #define QI_REGISTER_NAMES \
1911 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1913 /* These parallel the array above, and can be used to access bits 8:15
1914 of regs 0 through 3. */
1916 #define QI_HIGH_REGISTER_NAMES \
1917 {"ah", "dh", "ch", "bh", }
1919 /* How to renumber registers for dbx and gdb. */
1921 #define DBX_REGISTER_NUMBER(N) \
1922 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1924 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
1925 extern int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
];
1926 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
1928 /* Before the prologue, RA is at 0(%esp). */
1929 #define INCOMING_RETURN_ADDR_RTX \
1930 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1932 /* After the prologue, RA is at -4(AP) in the current frame. */
1933 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1935 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
1937 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD)))
1939 /* PC is dbx register 8; let's use that column for RA. */
1940 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1942 /* Before the prologue, the top of the frame is at 4(%esp). */
1943 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1945 /* Describe how we implement __builtin_eh_return. */
1946 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
1947 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
1950 /* Select a format to encode pointers in exception handling data. CODE
1951 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1952 true if the symbol may be affected by dynamic relocations.
1954 ??? All x86 object file formats are capable of representing this.
1955 After all, the relocation needed is the same as for the call insn.
1956 Whether or not a particular assembler allows us to enter such, I
1957 guess we'll have to see. */
1958 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1959 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1961 /* This is how to output an insn to push a register on the stack.
1962 It need not be very fast code. */
1964 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1967 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1968 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1970 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
1973 /* This is how to output an insn to pop a register from the stack.
1974 It need not be very fast code. */
1976 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1979 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
1980 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1982 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
1985 /* This is how to output an element of a case-vector that is absolute. */
1987 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1988 ix86_output_addr_vec_elt ((FILE), (VALUE))
1990 /* This is how to output an element of a case-vector that is relative. */
1992 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1993 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
1995 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
1997 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
1999 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2000 (PTR) += TARGET_AVX ? 1 : 2; \
2003 /* A C statement or statements which output an assembler instruction
2004 opcode to the stdio stream STREAM. The macro-operand PTR is a
2005 variable of type `char *' which points to the opcode name in
2006 its "internal" form--the form that is written in the machine
2009 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2010 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2012 /* A C statement to output to the stdio stream FILE an assembler
2013 command to pad the location counter to a multiple of 1<<LOG
2014 bytes if it is within MAX_SKIP bytes. */
2016 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2017 #undef ASM_OUTPUT_MAX_SKIP_PAD
2018 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2021 if ((MAX_SKIP) == 0) \
2022 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2024 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2028 /* Write the extra assembler code needed to declare a function
2031 #undef ASM_OUTPUT_FUNCTION_LABEL
2032 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2033 ix86_asm_output_function_label (FILE, NAME, DECL)
2035 /* Under some conditions we need jump tables in the text section,
2036 because the assembler cannot handle label differences between
2037 sections. This is the case for x86_64 on Mach-O for example. */
2039 #define JUMP_TABLES_IN_TEXT_SECTION \
2040 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2041 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2043 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2044 and switch back. For x86 we do this only to save a few bytes that
2045 would otherwise be unused in the text section. */
2046 #define CRT_MKSTR2(VAL) #VAL
2047 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2049 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2050 asm (SECTION_OP "\n\t" \
2051 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2052 TEXT_SECTION_ASM_OP);
2054 /* Which processor to tune code generation for. */
2058 PROCESSOR_I386
= 0, /* 80386 */
2059 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
2061 PROCESSOR_PENTIUMPRO
,
2070 PROCESSOR_COREI7_32
,
2071 PROCESSOR_COREI7_64
,
2072 PROCESSOR_GENERIC32
,
2073 PROCESSOR_GENERIC64
,
2083 extern enum processor_type ix86_tune
;
2084 extern enum processor_type ix86_arch
;
2086 /* Size of the RED_ZONE area. */
2087 #define RED_ZONE_SIZE 128
2088 /* Reserved area of the red zone for temporaries. */
2089 #define RED_ZONE_RESERVE 8
2091 extern unsigned int ix86_preferred_stack_boundary
;
2092 extern unsigned int ix86_incoming_stack_boundary
;
2094 /* Smallest class containing REGNO. */
2095 extern enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
];
2097 enum ix86_fpcmp_strategy
{
2103 /* To properly truncate FP values into integers, we need to set i387 control
2104 word. We can't emit proper mode switching code before reload, as spills
2105 generated by reload may truncate values incorrectly, but we still can avoid
2106 redundant computation of new control word by the mode switching pass.
2107 The fldcw instructions are still emitted redundantly, but this is probably
2108 not going to be noticeable problem, as most CPUs do have fast path for
2111 The machinery is to emit simple truncation instructions and split them
2112 before reload to instructions having USEs of two memory locations that
2113 are filled by this code to old and new control word.
2115 Post-reload pass may be later used to eliminate the redundant fildcw if
2127 enum ix86_stack_slot
2136 MAX_386_STACK_LOCALS
2139 /* Define this macro if the port needs extra instructions inserted
2140 for mode switching in an optimizing compilation. */
2142 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2143 ix86_optimize_mode_switching[(ENTITY)]
2145 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2146 initializer for an array of integers. Each initializer element N
2147 refers to an entity that needs mode switching, and specifies the
2148 number of different modes that might need to be set for this
2149 entity. The position of the initializer in the initializer -
2150 starting counting at zero - determines the integer that is used to
2151 refer to the mode-switched entity in question. */
2153 #define NUM_MODES_FOR_MODE_SWITCHING \
2154 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2156 /* ENTITY is an integer specifying a mode-switched entity. If
2157 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2158 return an integer value not larger than the corresponding element
2159 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2160 must be switched into prior to the execution of INSN. */
2162 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2164 /* This macro specifies the order in which modes for ENTITY are
2165 processed. 0 is the highest priority. */
2167 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2169 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2170 is the set of hard registers live at the point where the insn(s)
2171 are to be inserted. */
2173 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2174 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2175 ? emit_i387_cw_initialization (MODE), 0 \
2179 /* Avoid renaming of stack registers, as doing so in combination with
2180 scheduling just increases amount of live registers at time and in
2181 the turn amount of fxch instructions needed.
2183 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2185 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2186 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2189 #define FASTCALL_PREFIX '@'
2191 /* Machine specific frame tracking during prologue/epilogue generation. */
2193 #ifndef USED_FOR_TARGET
2194 struct GTY(()) machine_frame_state
2196 /* This pair tracks the currently active CFA as reg+offset. When reg
2197 is drap_reg, we don't bother trying to record here the real CFA when
2198 it might really be a DW_CFA_def_cfa_expression. */
2200 HOST_WIDE_INT cfa_offset
;
2202 /* The current offset (canonically from the CFA) of ESP and EBP.
2203 When stack frame re-alignment is active, these may not be relative
2204 to the CFA. However, in all cases they are relative to the offsets
2205 of the saved registers stored in ix86_frame. */
2206 HOST_WIDE_INT sp_offset
;
2207 HOST_WIDE_INT fp_offset
;
2209 /* The size of the red-zone that may be assumed for the purposes of
2210 eliding register restore notes in the epilogue. This may be zero
2211 if no red-zone is in effect, or may be reduced from the real
2212 red-zone value by a maximum runtime stack re-alignment value. */
2213 int red_zone_offset
;
2215 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2216 value within the frame. If false then the offset above should be
2217 ignored. Note that DRAP, if valid, *always* points to the CFA and
2218 thus has an offset of zero. */
2219 BOOL_BITFIELD sp_valid
: 1;
2220 BOOL_BITFIELD fp_valid
: 1;
2221 BOOL_BITFIELD drap_valid
: 1;
2223 /* Indicate whether the local stack frame has been re-aligned. When
2224 set, the SP/FP offsets above are relative to the aligned frame
2226 BOOL_BITFIELD realigned
: 1;
2229 /* Private to winnt.c. */
2230 struct seh_frame_state
;
2232 struct GTY(()) machine_function
{
2233 struct stack_local_entry
*stack_locals
;
2234 const char *some_ld_name
;
2235 int varargs_gpr_size
;
2236 int varargs_fpr_size
;
2237 int optimize_mode_switching
[MAX_386_ENTITIES
];
2239 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
2240 has been computed for. */
2241 int use_fast_prologue_epilogue_nregs
;
2243 /* For -fsplit-stack support: A stack local which holds a pointer to
2244 the stack arguments for a function with a variable number of
2245 arguments. This is set at the start of the function and is used
2246 to initialize the overflow_arg_area field of the va_list
2248 rtx split_stack_varargs_pointer
;
2250 /* This value is used for amd64 targets and specifies the current abi
2251 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2252 ENUM_BITFIELD(calling_abi
) call_abi
: 8;
2254 /* Nonzero if the function accesses a previous frame. */
2255 BOOL_BITFIELD accesses_prev_frame
: 1;
2257 /* Nonzero if the function requires a CLD in the prologue. */
2258 BOOL_BITFIELD needs_cld
: 1;
2260 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2261 expander to determine the style used. */
2262 BOOL_BITFIELD use_fast_prologue_epilogue
: 1;
2264 /* If true, the current function needs the default PIC register, not
2265 an alternate register (on x86) and must not use the red zone (on
2266 x86_64), even if it's a leaf function. We don't want the
2267 function to be regarded as non-leaf because TLS calls need not
2268 affect register allocation. This flag is set when a TLS call
2269 instruction is expanded within a function, and never reset, even
2270 if all such instructions are optimized away. Use the
2271 ix86_current_function_calls_tls_descriptor macro for a better
2273 BOOL_BITFIELD tls_descriptor_call_expanded_p
: 1;
2275 /* If true, the current function has a STATIC_CHAIN is placed on the
2276 stack below the return address. */
2277 BOOL_BITFIELD static_chain_on_stack
: 1;
2279 /* Nonzero if caller passes 256bit AVX modes. */
2280 BOOL_BITFIELD caller_pass_avx256_p
: 1;
2282 /* Nonzero if caller returns 256bit AVX modes. */
2283 BOOL_BITFIELD caller_return_avx256_p
: 1;
2285 /* Nonzero if the current callee passes 256bit AVX modes. */
2286 BOOL_BITFIELD callee_pass_avx256_p
: 1;
2288 /* Nonzero if the current callee returns 256bit AVX modes. */
2289 BOOL_BITFIELD callee_return_avx256_p
: 1;
2291 /* Nonzero if rescan vzerouppers in the current function is needed. */
2292 BOOL_BITFIELD rescan_vzeroupper_p
: 1;
2294 /* During prologue/epilogue generation, the current frame state.
2295 Otherwise, the frame state at the end of the prologue. */
2296 struct machine_frame_state fs
;
2298 /* During SEH output, this is non-null. */
2299 struct seh_frame_state
* GTY((skip(""))) seh
;
2303 #define ix86_stack_locals (cfun->machine->stack_locals)
2304 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2305 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2306 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2307 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2308 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2309 (cfun->machine->tls_descriptor_call_expanded_p)
2310 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2311 calls are optimized away, we try to detect cases in which it was
2312 optimized away. Since such instructions (use (reg REG_SP)), we can
2313 verify whether there's any such instruction live by testing that
2315 #define ix86_current_function_calls_tls_descriptor \
2316 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2317 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2319 /* Control behavior of x86_file_start. */
2320 #define X86_FILE_START_VERSION_DIRECTIVE false
2321 #define X86_FILE_START_FLTUSED false
2323 /* Flag to mark data that is in the large address area. */
2324 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2325 #define SYMBOL_REF_FAR_ADDR_P(X) \
2326 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2328 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2329 have defined always, to avoid ifdefing. */
2330 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2331 #define SYMBOL_REF_DLLIMPORT_P(X) \
2332 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2334 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2335 #define SYMBOL_REF_DLLEXPORT_P(X) \
2336 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2338 extern void debug_ready_dispatch (void);
2339 extern void debug_dispatch_window (int);
2341 /* The value at zero is only defined for the BMI instructions
2342 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2343 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2344 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
2345 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2346 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT)
2349 /* Flags returned by ix86_get_callcvt (). */
2350 #define IX86_CALLCVT_CDECL 0x1
2351 #define IX86_CALLCVT_STDCALL 0x2
2352 #define IX86_CALLCVT_FASTCALL 0x4
2353 #define IX86_CALLCVT_THISCALL 0x8
2354 #define IX86_CALLCVT_REGPARM 0x10
2355 #define IX86_CALLCVT_SSEREGPARM 0x20
2357 #define IX86_BASE_CALLCVT(FLAGS) \
2358 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2359 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2361 #define RECIP_MASK_NONE 0x00
2362 #define RECIP_MASK_DIV 0x01
2363 #define RECIP_MASK_SQRT 0x02
2364 #define RECIP_MASK_VEC_DIV 0x04
2365 #define RECIP_MASK_VEC_SQRT 0x08
2366 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2367 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2368 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2370 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2371 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2372 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2373 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2375 #define IX86_HLE_ACQUIRE (1 << 16)
2376 #define IX86_HLE_RELEASE (1 << 17)