1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs
{
54 int add
; /* cost of an add instruction */
55 int lea
; /* cost of a lea instruction */
56 int shift_var
; /* variable shift costs */
57 int shift_const
; /* constant shift costs */
58 int mult_init
; /* cost of starting a multiply */
59 int mult_bit
; /* cost of multiply per each bit set */
60 int divide
; /* cost of a divide/mod */
61 int large_insn
; /* insns larger than this cost more */
62 int move_ratio
; /* The threshold of number of scalar
63 memory-to-memory move insns. */
64 int movzbl_load
; /* cost of loading using movzbl */
65 int int_load
[3]; /* cost of loading integer registers
66 in QImode, HImode and SImode relative
67 to reg-reg move (2). */
68 int int_store
[3]; /* cost of storing integer register
69 in QImode, HImode and SImode */
70 int fp_move
; /* cost of reg,reg fld/fst */
71 int fp_load
[3]; /* cost of loading FP register
72 in SFmode, DFmode and XFmode */
73 int fp_store
[3]; /* cost of storing FP register
74 in SFmode, DFmode and XFmode */
77 extern struct processor_costs
*ix86_cost
;
79 /* Run-time compilation parameters selecting different hardware subsets. */
81 extern int target_flags
;
83 /* Macros used in the machine description to test the flags. */
85 /* configure can arrange to make this 2, to force a 486. */
87 #ifndef TARGET_CPU_DEFAULT
88 #define TARGET_CPU_DEFAULT 0
91 /* Masks for the -m switches */
92 #define MASK_80387 0x00000001 /* Hardware floating point */
93 #define MASK_RTD 0x00000002 /* Use ret that pops args */
94 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
95 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
96 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
97 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
98 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
99 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
100 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
101 #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
102 #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
103 #define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
104 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
105 #define MASK_MMX 0x00010000 /* Support MMX regs/builtins */
106 #define MASK_SSE 0x00020000 /* Support SSE regs/builtins */
108 /* Temporary codegen switches */
109 #define MASK_INTEL_SYNTAX 0x00000200
110 #define MASK_DEBUG_ARG 0x00000400 /* function_arg */
111 #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */
113 /* Use the floating point instructions */
114 #define TARGET_80387 (target_flags & MASK_80387)
116 /* Compile using ret insn that pops args.
117 This will not work unless you use prototypes at least
118 for all functions that can take varying numbers of args. */
119 #define TARGET_RTD (target_flags & MASK_RTD)
121 /* Align doubles to a two word boundary. This breaks compatibility with
122 the published ABI's for structures containing doubles, but produces
123 faster code on the pentium. */
124 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
126 /* Use push instructions to save outgoing args. */
127 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
129 /* Accumulate stack adjustments to prologue/epilogue. */
130 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
131 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
133 /* Put uninitialized locals into bss, not data.
134 Meaningful only on svr3. */
135 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
137 /* Use IEEE floating point comparisons. These handle correctly the cases
138 where the result of a comparison is unordered. Normally SIGFPE is
139 generated in such cases, in which case this isn't needed. */
140 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
142 /* Functions that return a floating point value may return that value
143 in the 387 FPU or in 386 integer registers. If set, this flag causes
144 the 387 to be used, which is compatible with most calling conventions. */
145 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
147 /* Disable generation of FP sin, cos and sqrt operations for 387.
148 This is because FreeBSD lacks these in the math-emulator-code */
149 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
151 /* Don't create frame pointers for leaf functions */
152 #define TARGET_OMIT_LEAF_FRAME_POINTER \
153 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
155 /* Debug GO_IF_LEGITIMATE_ADDRESS */
156 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
158 /* Debug FUNCTION_ARG macros */
159 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
161 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
162 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
163 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
164 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
165 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
166 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
168 #define CPUMASK (1 << ix86_cpu)
169 extern const int x86_use_leave
, x86_push_memory
, x86_zero_extend_with_and
;
170 extern const int x86_use_bit_test
, x86_cmove
, x86_deep_branch
;
171 extern const int x86_unroll_strlen
, x86_use_q_reg
, x86_use_any_reg
;
172 extern const int x86_double_with_add
, x86_partial_reg_stall
, x86_movx
;
173 extern const int x86_use_loop
, x86_use_fiop
, x86_use_mov0
;
174 extern const int x86_use_cltd
, x86_read_modify_write
;
175 extern const int x86_read_modify
, x86_split_long_moves
;
176 extern const int x86_promote_QImode
, x86_single_stringop
;
177 extern const int x86_himode_math
, x86_qimode_math
, x86_promote_qi_regs
;
178 extern const int x86_promote_hi_regs
, x86_integer_DFmode_moves
;
179 extern const int x86_add_esp_4
, x86_add_esp_8
, x86_sub_esp_4
, x86_sub_esp_8
;
180 extern const int x86_partial_reg_dependency
, x86_memory_mismatch_stall
;
182 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
183 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
184 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
185 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
186 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
187 #define TARGET_USE_Q_REG (x86_use_q_reg & CPUMASK)
188 #define TARGET_USE_ANY_REG (x86_use_any_reg & CPUMASK)
189 #define TARGET_CMOVE (x86_cmove & (1 << ix86_arch))
190 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
191 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
192 #define TARGET_USE_SAHF (x86_use_sahf & CPUMASK)
193 #define TARGET_MOVX (x86_movx & CPUMASK)
194 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
195 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
196 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
197 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
198 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
199 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
200 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
201 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
202 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
203 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
204 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
205 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
206 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
207 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
208 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
209 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
210 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
211 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
212 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
213 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
214 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
216 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
218 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
219 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
221 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
223 #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
224 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
226 #define TARGET_SWITCHES \
227 { { "80387", MASK_80387, N_("Use hardware fp") }, \
228 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
229 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
230 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
231 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
232 { "386", 0, N_("Same as -mcpu=i386") }, \
233 { "486", 0, N_("Same as -mcpu=i486") }, \
234 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
235 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
237 N_("Alternate calling convention") }, \
238 { "no-rtd", -MASK_RTD, \
239 N_("Use normal calling convention") }, \
240 { "align-double", MASK_ALIGN_DOUBLE, \
241 N_("Align some doubles on dword boundary") }, \
242 { "no-align-double", -MASK_ALIGN_DOUBLE, \
243 N_("Align doubles on word boundary") }, \
244 { "svr3-shlib", MASK_SVR3_SHLIB, \
245 N_("Uninitialized locals in .bss") }, \
246 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
247 N_("Uninitialized locals in .data") }, \
248 { "ieee-fp", MASK_IEEE_FP, \
249 N_("Use IEEE math for fp comparisons") }, \
250 { "no-ieee-fp", -MASK_IEEE_FP, \
251 N_("Do not use IEEE math for fp comparisons") }, \
252 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
253 N_("Return values of functions in FPU registers") }, \
254 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
255 N_("Do not return values of functions in FPU registers")}, \
256 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
257 N_("Do not generate sin, cos, sqrt for FPU") }, \
258 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
259 N_("Generate sin, cos, sqrt for FPU")}, \
260 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
261 N_("Omit the frame pointer in leaf functions") }, \
262 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
263 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
264 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
265 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
266 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
267 { "stack-arg-probe", MASK_STACK_PROBE, \
268 N_("Enable stack probing") }, \
269 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
270 { "windows", 0, 0 /* undocumented */ }, \
271 { "dll", 0, 0 /* undocumented */ }, \
272 { "intel-syntax", MASK_INTEL_SYNTAX, \
273 N_("Emit Intel syntax assembler opcodes") }, \
274 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
275 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
276 N_("Align destination of the string operations") }, \
277 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
278 N_("Do not align destination of the string operations") }, \
279 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
280 N_("Inline all known string operations") }, \
281 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
282 N_("Do not inline all known string operations") }, \
283 { "push-args", -MASK_NO_PUSH_ARGS, \
284 N_("Use push instructions to save outgoing arguments") }, \
285 { "no-push-args", MASK_NO_PUSH_ARGS, \
286 N_("Do not use push instructions to save outgoing arguments") }, \
287 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
288 N_("Use push instructions to save outgoing arguments") }, \
289 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
290 N_("Do not use push instructions to save outgoing arguments") }, \
291 { "mmx", MASK_MMX, N_("Support MMX builtins") }, \
292 { "no-mmx", -MASK_MMX, \
293 N_("Do not support MMX builtins") }, \
295 N_("Support MMX and SSE builtins") }, \
296 { "no-sse", -MASK_SSE, \
297 N_("Do not support MMX and SSE builtins") }, \
299 { "", TARGET_DEFAULT, 0 }}
301 /* Which processor to schedule for. The cpu attribute defines a list that
302 mirrors this list, so changes to i386.md must be made at the same time. */
306 PROCESSOR_I386
, /* 80386 */
307 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
309 PROCESSOR_PENTIUMPRO
,
315 extern enum processor_type ix86_cpu
;
317 extern int ix86_arch
;
319 /* This macro is similar to `TARGET_SWITCHES' but defines names of
320 command options that have values. Its definition is an
321 initializer with a subgrouping for each command option.
323 Each subgrouping contains a string constant, that defines the
324 fixed part of the option name, and the address of a variable. The
325 variable, type `char *', is set to the variable part of the given
326 option if the fixed part matches. The actual option name is made
327 by appending `-m' to the specified name. */
328 #define TARGET_OPTIONS \
329 { { "cpu=", &ix86_cpu_string, \
330 N_("Schedule code for given CPU")}, \
331 { "arch=", &ix86_arch_string, \
332 N_("Generate code for given CPU")}, \
333 { "reg-alloc=", &ix86_reg_alloc_order, \
334 N_("Control allocation order of integer registers") }, \
335 { "regparm=", &ix86_regparm_string, \
336 N_("Number of registers used to pass integer arguments") }, \
337 { "align-loops=", &ix86_align_loops_string, \
338 N_("Loop code aligned to this power of 2") }, \
339 { "align-jumps=", &ix86_align_jumps_string, \
340 N_("Jump targets are aligned to this power of 2") }, \
341 { "align-functions=", &ix86_align_funcs_string, \
342 N_("Function starts are aligned to this power of 2") }, \
343 { "preferred-stack-boundary=", \
344 &ix86_preferred_stack_boundary_string, \
345 N_("Attempt to keep stack aligned to this power of 2") }, \
346 { "branch-cost=", &ix86_branch_cost_string, \
347 N_("Branches are this expensive (1-5, arbitrary units)") }, \
351 /* Sometimes certain combinations of command options do not make
352 sense on a particular target machine. You can define a macro
353 `OVERRIDE_OPTIONS' to take account of this. This macro, if
354 defined, is executed once just after all the command options have
357 Don't use this macro to turn on various extra optimizations for
358 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
360 #define OVERRIDE_OPTIONS override_options ()
362 /* These are meant to be redefined in the host dependent files */
363 #define SUBTARGET_SWITCHES
364 #define SUBTARGET_OPTIONS
366 /* Define this to change the optimizations performed by default. */
367 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
369 /* Specs for the compiler proper */
372 #define CC1_CPU_SPEC "\
376 %{mpentium:-mcpu=pentium} \
377 %{mpentiumpro:-mcpu=pentiumpro}}"
380 #ifndef CPP_CPU_DEFAULT_SPEC
381 #if TARGET_CPU_DEFAULT == 1
382 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
384 #if TARGET_CPU_DEFAULT == 2
385 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium__"
387 #if TARGET_CPU_DEFAULT == 3
388 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentiumpro__"
390 #if TARGET_CPU_DEFAULT == 4
391 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
393 #if TARGET_CPU_DEFAULT == 5
394 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
396 #ifndef CPP_CPU_DEFAULT_SPEC
397 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
399 #endif /* CPP_CPU_DEFAULT_SPEC */
402 #define CPP_CPU_SPEC "\
403 -Acpu(i386) -Amachine(i386) \
404 %{!ansi:-Di386} -D__i386 -D__i386__ \
405 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
406 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
407 %{march=pentium|march=i586:-D__pentium -D__pentium__ \
408 %{!mcpu*:-D__tune_pentium__ }}\
409 %{march=pentiumpro|march=i686:-D__pentiumpro -D__pentiumpro__ \
410 %{!mcpu*:-D__tune_pentiumpro__ }}\
411 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
412 %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
413 %{m386|mcpu=i386:-D__tune_i386__ }\
414 %{m486|mcpu=i486:-D__tune_i486__ }\
415 %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_pentium__ }\
416 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_pentiumpro__ }\
417 %{mcpu=k6:-D__tune_k6__ }\
418 %{mcpu=athlon:-D__tune_athlon__ }\
419 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
423 #define CC1_SPEC "%(cc1_cpu) "
426 /* This macro defines names of additional specifications to put in the
427 specs that can be used in various specifications like CC1_SPEC. Its
428 definition is an initializer with a subgrouping for each command option.
430 Each subgrouping contains a string constant, that defines the
431 specification name, and a string constant that used by the GNU CC driver
434 Do not define this macro if it does not need to do anything. */
436 #ifndef SUBTARGET_EXTRA_SPECS
437 #define SUBTARGET_EXTRA_SPECS
440 #define EXTRA_SPECS \
441 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
442 { "cpp_cpu", CPP_CPU_SPEC }, \
443 { "cc1_cpu", CC1_CPU_SPEC }, \
444 SUBTARGET_EXTRA_SPECS
446 /* target machine storage layout */
448 /* Define for XFmode extended real floating point support.
449 This will automatically cause REAL_ARITHMETIC to be defined. */
450 #define LONG_DOUBLE_TYPE_SIZE 96
452 /* Define if you don't want extended real, but do want to use the
453 software floating point emulator for REAL_ARITHMETIC and
454 decimal <-> binary conversion. */
455 /* #define REAL_ARITHMETIC */
457 /* Define this if most significant byte of a word is the lowest numbered. */
458 /* That is true on the 80386. */
460 #define BITS_BIG_ENDIAN 0
462 /* Define this if most significant byte of a word is the lowest numbered. */
463 /* That is not true on the 80386. */
464 #define BYTES_BIG_ENDIAN 0
466 /* Define this if most significant word of a multiword number is the lowest
468 /* Not true for 80386 */
469 #define WORDS_BIG_ENDIAN 0
471 /* number of bits in an addressable storage unit */
472 #define BITS_PER_UNIT 8
474 /* Width in bits of a "word", which is the contents of a machine register.
475 Note that this is not necessarily the width of data type `int';
476 if using 16-bit ints on a 80386, this would still be 32.
477 But on a machine with 16-bit registers, this would be 16. */
478 #define BITS_PER_WORD 32
480 /* Width of a word, in units (bytes). */
481 #define UNITS_PER_WORD 4
483 /* Width in bits of a pointer.
484 See also the macro `Pmode' defined below. */
485 #define POINTER_SIZE 32
487 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
488 #define PARM_BOUNDARY 32
490 /* Boundary (in *bits*) on which stack pointer should be aligned. */
491 #define STACK_BOUNDARY 32
493 /* Boundary (in *bits*) on which the stack pointer preferrs to be
494 aligned; the compiler cannot rely on having this alignment. */
495 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
497 /* Allocation boundary for the code of a function. */
498 #define FUNCTION_BOUNDARY \
499 (1 << ((ix86_align_funcs >= 0 ? ix86_align_funcs : -ix86_align_funcs) + 3))
501 /* Alignment of field after `int : 0' in a structure. */
503 #define EMPTY_FIELD_BOUNDARY 32
505 /* Minimum size in bits of the largest boundary to which any
506 and all fundamental data types supported by the hardware
507 might need to be aligned. No data type wants to be aligned
510 Pentium+ preferrs DFmode values to be alignmed to 64 bit boundary
511 and Pentium Pro XFmode values at 128 bit boundaries. */
513 #define BIGGEST_ALIGNMENT 128
515 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
516 #define ALIGN_MODE_128(MODE) \
517 ((MODE) == XFmode || ((MODE) == TImode) || (MODE) == V4SFmode \
518 || (MODE) == V4SImode)
520 /* The published ABIs say that doubles should be aligned on word
521 boundaries, so lower the aligment for structure fields unless
522 -malign-double is set. */
523 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
524 constant. Use the smaller value in that context. */
525 #ifndef IN_TARGET_LIBS
526 #define BIGGEST_FIELD_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
528 #define BIGGEST_FIELD_ALIGNMENT 32
531 /* If defined, a C expression to compute the alignment given to a
532 constant that is being placed in memory. EXP is the constant
533 and ALIGN is the alignment that the object would ordinarily have.
534 The value of this macro is used instead of that alignment to align
537 If this macro is not defined, then ALIGN is used.
539 The typical use of this macro is to increase alignment for string
540 constants to be word aligned so that `strcpy' calls that copy
541 constants can be done inline. */
543 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
545 /* If defined, a C expression to compute the alignment for a static
546 variable. TYPE is the data type, and ALIGN is the alignment that
547 the object would ordinarily have. The value of this macro is used
548 instead of that alignment to align the object.
550 If this macro is not defined, then ALIGN is used.
552 One use of this macro is to increase alignment of medium-size
553 data to make it all fit in fewer cache lines. Another is to
554 cause character arrays to be word-aligned so that `strcpy' calls
555 that copy constants to character arrays can be done inline. */
557 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
559 /* If defined, a C expression to compute the alignment for a local
560 variable. TYPE is the data type, and ALIGN is the alignment that
561 the object would ordinarily have. The value of this macro is used
562 instead of that alignment to align the object.
564 If this macro is not defined, then ALIGN is used.
566 One use of this macro is to increase alignment of medium-size
567 data to make it all fit in fewer cache lines. */
569 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
571 /* Set this non-zero if move instructions will actually fail to work
572 when given unaligned data. */
573 #define STRICT_ALIGNMENT 0
575 /* If bit field type is int, don't let it cross an int,
576 and give entire struct the alignment of an int. */
577 /* Required on the 386 since it doesn't have bitfield insns. */
578 #define PCC_BITFIELD_TYPE_MATTERS 1
580 /* Align loop starts for optimal branching. */
581 #define LOOP_ALIGN(LABEL) \
582 (ix86_align_loops < 0 ? -ix86_align_loops : ix86_align_loops)
583 #define LOOP_ALIGN_MAX_SKIP \
584 (ix86_align_loops < -3 ? (1<<(-ix86_align_loops-1))-1 : 0)
586 /* This is how to align an instruction for optimal branching. */
587 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
588 (ix86_align_jumps < 0 ? -ix86_align_jumps : ix86_align_jumps)
589 #define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP \
590 (ix86_align_jumps < -3 ? (1<<(-ix86_align_jumps-1))-1 : 0)
592 /* Standard register usage. */
594 /* This processor has special stack-like registers. See reg-stack.c
598 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode || mode==XFmode)
600 /* Number of actual hardware registers.
601 The hardware registers are assigned numbers for the compiler
602 from 0 to just below FIRST_PSEUDO_REGISTER.
603 All registers that the compiler knows about must be given numbers,
604 even those that are not normally considered general registers.
606 In the 80386 we give the 8 general purpose registers the numbers 0-7.
607 We number the floating point registers 8-15.
608 Note that registers 0-7 can be accessed as a short or int,
609 while only 0-3 may be used with byte `mov' instructions.
611 Reg 16 does not correspond to any hardware register, but instead
612 appears in the RTL as an argument pointer prior to reload, and is
613 eliminated during reloading in favor of either the stack or frame
616 #define FIRST_PSEUDO_REGISTER 37
618 /* Number of hardware registers that go into the DWARF-2 unwind info.
619 If not defined, equals FIRST_PSEUDO_REGISTER. */
621 #define DWARF_FRAME_REGISTERS 17
623 /* 1 for registers that have pervasive standard uses
624 and are not available for the register allocator.
625 On the 80386, the stack pointer is such, as is the arg pointer. */
626 #define FIXED_REGISTERS \
627 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
628 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
629 /*arg,flags,fpsr,dir,frame*/ \
631 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
632 0, 0, 0, 0, 0, 0, 0, 0, \
633 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
634 0, 0, 0, 0, 0, 0, 0, 0}
636 /* 1 for registers not available across function calls.
637 These must include the FIXED_REGISTERS and also any
638 registers that can be used without being saved.
639 The latter must include the registers where values are returned
640 and the register where structure-value addresses are passed.
641 Aside from that, you can include as many other registers as you like. */
643 #define CALL_USED_REGISTERS \
644 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
645 { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
646 /*arg,flags,fpsr,dir,frame*/ \
648 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
649 1, 1, 1, 1, 1, 1, 1, 1, \
650 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
651 1, 1, 1, 1, 1, 1, 1, 1}
653 /* Order in which to allocate registers. Each register must be
654 listed once, even those in FIXED_REGISTERS. List frame pointer
655 late and fixed registers last. Note that, in general, we prefer
656 registers listed in CALL_USED_REGISTERS, keeping the others
657 available for storage of persistent values.
659 Three different versions of REG_ALLOC_ORDER have been tried:
661 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
662 but slower code on simple functions returning values in eax.
664 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
665 perl 4.036 due to not being able to create a DImode register (to hold a 2
668 If the order is eax, edx, ecx, ... it produces better code for simple
669 functions, and a slightly slower compiler. Users complained about the code
670 generated by allocating edx first, so restore the 'natural' order of things. */
672 #define REG_ALLOC_ORDER \
673 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
674 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
675 /*,arg,cc,fpsr,dir,frame*/ \
677 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
678 21, 22, 23, 24, 25, 26, 27, 28, \
679 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
680 29, 30, 31, 32, 33, 34, 35, 36 }
682 /* A C statement (sans semicolon) to choose the order in which to
683 allocate hard registers for pseudo-registers local to a basic
686 Store the desired register order in the array `reg_alloc_order'.
687 Element 0 should be the register to allocate first; element 1, the
688 next register; and so on.
690 The macro body should not assume anything about the contents of
691 `reg_alloc_order' before execution of the macro.
693 On most machines, it is not necessary to define this macro. */
695 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
697 /* Macro to conditionally modify fixed_regs/call_used_regs. */
698 #define CONDITIONAL_REGISTER_USAGE \
702 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
703 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
708 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
709 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
710 fixed_regs[i] = call_used_regs[i] = 1; \
715 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
716 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
717 fixed_regs[i] = call_used_regs[i] = 1; \
719 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
723 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
724 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
725 if (TEST_HARD_REG_BIT (x, i)) \
726 fixed_regs[i] = call_used_regs[i] = 1; \
730 /* Return number of consecutive hard regs needed starting at reg REGNO
731 to hold something of mode MODE.
732 This is ordinarily the length in words of a value of mode MODE
733 but can be less for certain modes in special long registers.
735 Actually there are no two word move instructions for consecutive
736 registers. And only registers 0-3 may have mov byte instructions
740 #define HARD_REGNO_NREGS(REGNO, MODE) \
741 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) ? 1 \
742 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
744 #define VALID_SSE_REG_MODE(MODE) \
745 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode)
747 #define VALID_MMX_REG_MODE(MODE) \
748 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
749 || (MODE) == V2SImode || (MODE) == SImode)
751 #define VECTOR_MODE_SUPPORTED_P(MODE) \
752 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
753 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 : 0)
755 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
757 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
758 /* Flags and only flags can only hold CCmode values. */ \
759 (CC_REGNO_P (REGNO) \
760 ? GET_MODE_CLASS (MODE) == MODE_CC \
761 : GET_MODE_CLASS (MODE) == MODE_CC ? 0 \
762 /* FP regs can only hold floating point; make it clear they \
763 cannot hold TFmode floats. */ \
764 : FP_REGNO_P (REGNO) \
765 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
766 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
767 && GET_MODE_UNIT_SIZE (MODE) <= (LONG_DOUBLE_TYPE_SIZE == 96 ? 12 : 8))\
768 : SSE_REGNO_P (REGNO) ? VALID_SSE_REG_MODE (MODE) \
769 : MMX_REGNO_P (REGNO) ? VALID_MMX_REG_MODE (MODE) \
770 /* Only SSE and MMX regs can hold vector modes. */ \
771 : VECTOR_MODE_P (MODE) || (MODE) == TImode ? 0 \
773 /* Other regs cannot do byte accesses. */ \
774 : (MODE) != QImode ? 1 \
775 : reload_in_progress || reload_completed \
776 || !TARGET_PARTIAL_REG_STALL)
778 /* Value is 1 if it is a good idea to tie two pseudo registers
779 when one has mode MODE1 and one has mode MODE2.
780 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
781 for any hard reg, then this must be 0 for correct output. */
783 #define MODES_TIEABLE_P(MODE1, MODE2) \
784 ((MODE1) == (MODE2) \
785 || ((MODE1) == SImode && (MODE2) == HImode) \
786 || ((MODE1) == HImode && (MODE2) == SImode))
788 /* Specify the modes required to caller save a given hard regno.
789 We do this on i386 to prevent flags from being saved at all. */
791 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) \
792 (CC_REGNO_P (REGNO) ? VOIDmode \
793 : choose_hard_reg_mode ((REGNO), (NREGS)))
795 /* Specify the registers used for certain standard purposes.
796 The values of these macros are register numbers. */
798 /* on the 386 the pc register is %eip, and is not usable as a general
799 register. The ordinary mov instructions won't work */
800 /* #define PC_REGNUM */
802 /* Register to use for pushing function arguments. */
803 #define STACK_POINTER_REGNUM 7
805 /* Base register for access to local variables of the function. */
806 #define HARD_FRAME_POINTER_REGNUM 6
808 /* Base register for access to local variables of the function. */
809 #define FRAME_POINTER_REGNUM 20
811 /* First floating point reg */
812 #define FIRST_FLOAT_REG 8
814 /* First & last stack-like regs */
815 #define FIRST_STACK_REG FIRST_FLOAT_REG
816 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
820 #define DIRFLAG_REG 19
822 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
823 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
825 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
826 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
828 /* Value should be nonzero if functions must have frame pointers.
829 Zero means the frame pointer need not be set up (and parms
830 may be accessed via the stack pointer) in functions that seem suitable.
831 This is computed in `reload', in reload1.c. */
832 #define FRAME_POINTER_REQUIRED (TARGET_OMIT_LEAF_FRAME_POINTER && !leaf_function_p ())
834 /* Base register for access to arguments of the function. */
835 #define ARG_POINTER_REGNUM 16
837 /* Register in which static-chain is passed to a function. */
838 #define STATIC_CHAIN_REGNUM 2
840 /* Register to hold the addressing base for position independent
841 code access to data items. */
842 #define PIC_OFFSET_TABLE_REGNUM 3
844 /* Register in which address to store a structure value
845 arrives in the function. On the 386, the prologue
846 copies this from the stack to register %eax. */
847 #define STRUCT_VALUE_INCOMING 0
849 /* Place in which caller passes the structure value address.
850 0 means push the value on the stack like an argument. */
851 #define STRUCT_VALUE 0
853 /* A C expression which can inhibit the returning of certain function
854 values in registers, based on the type of value. A nonzero value
855 says to return the function value in memory, just as large
856 structures are always returned. Here TYPE will be a C expression
857 of type `tree', representing the data type of the value.
859 Note that values of mode `BLKmode' must be explicitly handled by
860 this macro. Also, the option `-fpcc-struct-return' takes effect
861 regardless of this macro. On most systems, it is possible to
862 leave the macro undefined; this causes a default definition to be
863 used, whose value is the constant 1 for `BLKmode' values, and 0
866 Do not use this macro to indicate that structures and unions
867 should always be returned in memory. You should instead use
868 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
870 #define RETURN_IN_MEMORY(TYPE) \
871 ((TYPE_MODE (TYPE) == BLKmode) \
872 || (VECTOR_MODE_P (TYPE_MODE (TYPE)) && int_size_in_bytes (TYPE) == 8) \
873 || (int_size_in_bytes (TYPE) > 12 && TYPE_MODE (TYPE) != TImode \
874 && ! VECTOR_MODE_P (TYPE_MODE (TYPE))))
877 /* Define the classes of registers for register constraints in the
878 machine description. Also define ranges of constants.
880 One of the classes must always be named ALL_REGS and include all hard regs.
881 If there is more than one class, another class must be named NO_REGS
882 and contain no registers.
884 The name GENERAL_REGS must be the name of a class (or an alias for
885 another name such as ALL_REGS). This is the class of registers
886 that is allowed by "g" or "r" in a register constraint.
887 Also, registers outside this class are allocated only when
888 instructions express preferences for them.
890 The classes must be numbered in nondecreasing order; that is,
891 a larger-numbered class must never be contained completely
892 in a smaller-numbered class.
894 For any two classes, it is very desirable that there be another
895 class that represents their union.
897 It might seem that class BREG is unnecessary, since no useful 386
898 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
899 and the "b" register constraint is useful in asms for syscalls.
901 The flags and fpsr registers are in no class. */
906 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
907 AD_REGS
, /* %eax/%edx for DImode */
908 Q_REGS
, /* %eax %ebx %ecx %edx */
909 NON_Q_REGS
, /* %esi %edi %ebp %esp */
910 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
911 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
912 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
916 FLOAT_INT_REGS
, /* FLOAT_REGS and GENERAL_REGS. */
917 ALL_REGS
, LIM_REG_CLASSES
920 #define N_REG_CLASSES (int) LIM_REG_CLASSES
922 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
924 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
926 /* Give names of register classes as strings for dump file. */
928 #define REG_CLASS_NAMES \
930 "AREG", "DREG", "CREG", "BREG", \
933 "Q_REGS", "NON_Q_REGS", \
936 "FP_TOP_REG", "FP_SECOND_REG", \
943 /* Define which registers fit in which classes.
944 This is an initializer for a vector of HARD_REG_SET
945 of length N_REG_CLASSES. */
947 #define REG_CLASS_CONTENTS \
949 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
950 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
951 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
952 { 0x03, 0x0 }, /* AD_REGS */ \
953 { 0x0f, 0x0 }, /* Q_REGS */ \
954 { 0x1100f0, 0x0 }, /* NON_Q_REGS */ \
955 { 0x7f, 0x0 }, /* INDEX_REGS */ \
956 { 0x1100ff, 0x0 }, /* GENERAL_REGS */ \
957 { 0x100, 0x0 }, { 0x0200, 0x0 }, /* FP_TOP_REG, FP_SECOND_REG */ \
958 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
959 { 0x1fe00000, 0x0 }, /* SSE_REGS */ \
960 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
961 { 0x1ffff, 0x0 }, /* FLOAT_INT_REGS */ \
962 { 0xffffffff, 0x1f } \
965 /* The same information, inverted:
966 Return the class number of the smallest class containing
967 reg number REGNO. This could be a conditional expression
968 or could index an array. */
970 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
972 /* When defined, the compiler allows registers explicitly used in the
973 rtl to be used as spill registers but prevents the compiler from
974 extending the lifetime of these registers. */
976 #define SMALL_REGISTER_CLASSES 1
978 #define QI_REG_P(X) \
979 (REG_P (X) && REGNO (X) < 4)
980 #define NON_QI_REG_P(X) \
981 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
983 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
984 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
986 #define SSE_REGNO_P(n) ((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG)
988 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
989 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
991 #define STACK_REG_P(xop) (REG_P (xop) && \
992 REGNO (xop) >= FIRST_STACK_REG && \
993 REGNO (xop) <= LAST_STACK_REG)
995 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
997 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
999 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1000 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1002 /* Indicate whether hard register numbered REG_NO should be converted
1004 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1005 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1007 /* The class value for index registers, and the one for base regs. */
1009 #define INDEX_REG_CLASS INDEX_REGS
1010 #define BASE_REG_CLASS GENERAL_REGS
1012 /* Get reg_class from a letter such as appears in the machine description. */
1014 #define REG_CLASS_FROM_LETTER(C) \
1015 ((C) == 'r' ? GENERAL_REGS : \
1016 (C) == 'q' ? Q_REGS : \
1017 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1020 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1023 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1026 (C) == 'a' ? AREG : \
1027 (C) == 'b' ? BREG : \
1028 (C) == 'c' ? CREG : \
1029 (C) == 'd' ? DREG : \
1030 (C) == 'x' ? SSE_REGS : \
1031 (C) == 'y' ? MMX_REGS : \
1032 (C) == 'A' ? AD_REGS : \
1033 (C) == 'D' ? DIREG : \
1034 (C) == 'S' ? SIREG : NO_REGS)
1036 /* The letters I, J, K, L and M in a register constraint string
1037 can be used to stand for particular ranges of immediate operands.
1038 This macro defines what the ranges are.
1039 C is the letter, and VALUE is a constant value.
1040 Return 1 if VALUE is in the range specified by C.
1042 I is for non-DImode shifts.
1043 J is for DImode shifts.
1044 K is for signed imm8 operands.
1045 L is for andsi as zero-extending move.
1046 M is for shifts that can be executed by the "lea" opcode.
1049 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1050 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1051 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1052 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1053 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1054 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1057 /* Similar, but for floating constants, and defining letters G and H.
1058 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1059 TARGET_387 isn't set, because the stack register converter may need to
1060 load 0.0 into the function value register. */
1062 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1063 ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0)
1065 /* Place additional restrictions on the register class to use when it
1066 is necessary to be able to hold a value of mode MODE in a reload
1067 register for which class CLASS would ordinarily be used. */
1069 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1070 ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1073 /* Given an rtx X being reloaded into a reg required to be
1074 in class CLASS, return the class of reg to actually use.
1075 In general this is just CLASS; but on some machines
1076 in some cases it is preferable to use a more restrictive class.
1077 On the 80386 series, we prevent floating constants from being
1078 reloaded into floating registers (since no move-insn can do that)
1079 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1081 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1082 QImode must go into class Q_REGS.
1083 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1084 movdf to do mem-to-mem moves through integer regs. */
1086 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1087 (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode \
1088 ? (standard_80387_constant_p (X) \
1090 : (reg_class_subset_p (CLASS, FLOAT_REGS) \
1092 : reg_class_subset_p (CLASS, GENERAL_REGS) ? CLASS : GENERAL_REGS)) \
1093 : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \
1096 /* If we are copying between general and FP registers, we need a memory
1098 /* The same is true for SSE and MMX registers. */
1099 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1100 (FLOAT_CLASS_P (CLASS1) != FLOAT_CLASS_P (CLASS2) \
1101 || ((CLASS1 == SSE_REGS) != (CLASS2 == SSE_REGS)) \
1102 || ((CLASS1 == MMX_REGS) != (CLASS2 == MMX_REGS) && (MODE) != SImode))
1104 /* QImode spills from non-QI registers need a scratch. This does not
1105 happen often -- the only example so far requires an uninitialized
1108 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1109 ((CLASS) == GENERAL_REGS && (MODE) == QImode ? Q_REGS : NO_REGS)
1111 /* Return the maximum number of consecutive registers
1112 needed to represent mode MODE in a register of class CLASS. */
1113 /* On the 80386, this is the size of MODE in words,
1114 except in the FP regs, where a single reg is always enough. */
1115 #define CLASS_MAX_NREGS(CLASS, MODE) \
1116 (FLOAT_CLASS_P (CLASS) || (CLASS) == SSE_REGS || (CLASS) == MMX_REGS \
1118 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1120 /* A C expression whose value is nonzero if pseudos that have been
1121 assigned to registers of class CLASS would likely be spilled
1122 because registers of CLASS are needed for spill registers.
1124 The default value of this macro returns 1 if CLASS has exactly one
1125 register and zero otherwise. On most machines, this default
1126 should be used. Only define this macro to some other expression
1127 if pseudo allocated by `local-alloc.c' end up in memory because
1128 their hard registers were needed for spill registers. If this
1129 macro returns nonzero for those classes, those pseudos will only
1130 be allocated by `global.c', which knows how to reallocate the
1131 pseudo to another register. If there would not be another
1132 register available for reallocation, you should not change the
1133 definition of this macro since the only effect of such a
1134 definition would be to slow down register allocation. */
1136 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1137 (((CLASS) == AREG) \
1138 || ((CLASS) == DREG) \
1139 || ((CLASS) == CREG) \
1140 || ((CLASS) == BREG) \
1141 || ((CLASS) == AD_REGS) \
1142 || ((CLASS) == SIREG) \
1143 || ((CLASS) == DIREG))
1145 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1146 to automatically clobber for all asms.
1148 We do this in the new i386 backend to maintain source compatibility
1149 with the old cc0-based compiler. */
1151 #define MD_ASM_CLOBBERS(CLOBBERS) \
1153 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1154 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1155 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1158 /* Stack layout; function entry, exit and calling. */
1160 /* Define this if pushing a word on the stack
1161 makes the stack pointer a smaller address. */
1162 #define STACK_GROWS_DOWNWARD
1164 /* Define this if the nominal address of the stack frame
1165 is at the high-address end of the local variables;
1166 that is, each additional local variable allocated
1167 goes at a more negative offset in the frame. */
1168 #define FRAME_GROWS_DOWNWARD
1170 /* Offset within stack frame to start allocating local variables at.
1171 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1172 first local allocated. Otherwise, it is the offset to the BEGINNING
1173 of the first local allocated. */
1174 #define STARTING_FRAME_OFFSET 0
1176 /* If we generate an insn to push BYTES bytes,
1177 this says how many the stack pointer really advances by.
1178 On 386 pushw decrements by exactly 2 no matter what the position was.
1179 On the 386 there is no pushb; we use pushw instead, and this
1180 has the effect of rounding up to 2. */
1182 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
1184 /* If defined, the maximum amount of space required for outgoing arguments will
1185 be computed and placed into the variable
1186 `current_function_outgoing_args_size'. No space will be pushed onto the
1187 stack for each call; instead, the function prologue should increase the stack
1188 frame size by this amount. */
1190 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1192 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1193 instructions to pass outgoing arguments. */
1195 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1197 /* Offset of first parameter from the argument pointer register value. */
1198 #define FIRST_PARM_OFFSET(FNDECL) 0
1200 /* Define this macro if functions should assume that stack space has been
1201 allocated for arguments even when their values are passed in registers.
1203 The value of this macro is the size, in bytes, of the area reserved for
1204 arguments passed in registers for the function represented by FNDECL.
1206 This space can be allocated by the caller, or be a part of the
1207 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1209 #define REG_PARM_STACK_SPACE(FNDECL) 0
1211 /* Define as a C expression that evaluates to nonzero if we do not know how
1212 to pass TYPE solely in registers. The file expr.h defines a
1213 definition that is usually appropriate, refer to expr.h for additional
1214 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1215 computed in the stack and then loaded into a register. */
1216 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1218 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1219 || TREE_ADDRESSABLE (TYPE) \
1220 || ((MODE) == TImode) \
1221 || ((MODE) == BLKmode \
1222 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1223 && 0 == (int_size_in_bytes (TYPE) \
1224 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1225 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1226 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1228 /* Value is the number of bytes of arguments automatically
1229 popped when returning from a subroutine call.
1230 FUNDECL is the declaration node of the function (as a tree),
1231 FUNTYPE is the data type of the function (as a tree),
1232 or for a library call it is an identifier node for the subroutine name.
1233 SIZE is the number of bytes of arguments passed on the stack.
1235 On the 80386, the RTD insn may be used to pop them if the number
1236 of args is fixed, but if the number is variable then the caller
1237 must pop them all. RTD can't be used for library calls now
1238 because the library is compiled with the Unix compiler.
1239 Use of RTD is a selectable option, since it is incompatible with
1240 standard Unix calling sequences. If the option is not selected,
1241 the caller must always pop the args.
1243 The attribute stdcall is equivalent to RTD on a per module basis. */
1245 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1246 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1248 /* Define how to find the value returned by a function.
1249 VALTYPE is the data type of the value (as a tree).
1250 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1251 otherwise, FUNC is 0. */
1252 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1253 gen_rtx_REG (TYPE_MODE (VALTYPE), \
1254 VALUE_REGNO (TYPE_MODE (VALTYPE)))
1256 /* Define how to find the value returned by a library function
1257 assuming the value has mode MODE. */
1259 #define LIBCALL_VALUE(MODE) \
1260 gen_rtx_REG (MODE, VALUE_REGNO (MODE))
1262 /* Define the size of the result block used for communication between
1263 untyped_call and untyped_return. The block contains a DImode value
1264 followed by the block used by fnsave and frstor. */
1266 #define APPLY_RESULT_SIZE (8+108)
1268 /* 1 if N is a possible register number for function argument passing. */
1269 #define FUNCTION_ARG_REGNO_P(N) ((N) < REGPARM_MAX)
1271 /* Define a data type for recording info about an argument list
1272 during the scan of that argument list. This data type should
1273 hold all necessary information about the function itself
1274 and about the args processed so far, enough to enable macros
1275 such as FUNCTION_ARG to determine where the next arg should go. */
1277 typedef struct ix86_args
{
1278 int words
; /* # words passed so far */
1279 int nregs
; /* # registers available for passing */
1280 int regno
; /* next available register number */
1281 int sse_words
; /* # sse words passed so far */
1282 int sse_nregs
; /* # sse registers available for passing */
1283 int sse_regno
; /* next available sse register number */
1286 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1287 for a call to a function whose data type is FNTYPE.
1288 For a library call, FNTYPE is 0. */
1290 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1291 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1293 /* Update the data in CUM to advance over an argument
1294 of mode MODE and data type TYPE.
1295 (TYPE is null for libcalls where that information may not be available.) */
1297 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1298 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1300 /* Define where to put the arguments to a function.
1301 Value is zero to push the argument on the stack,
1302 or a hard register in which to store the argument.
1304 MODE is the argument's machine mode.
1305 TYPE is the data type of the argument (as a tree).
1306 This is null for libcalls where that information may
1308 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1309 the preceding args and about the function being called.
1310 NAMED is nonzero if this argument is a named parameter
1311 (otherwise it is an extra parameter matching an ellipsis). */
1313 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1314 (function_arg (&CUM, MODE, TYPE, NAMED))
1316 /* For an arg passed partly in registers and partly in memory,
1317 this is the number of registers used.
1318 For args passed entirely in registers or entirely in memory, zero. */
1320 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1322 /* If PIC, we cannot make sibling calls to global functions
1323 because the PLT requires %ebx live.
1324 If we are returning floats on the register stack, we cannot make
1325 sibling calls to functions that return floats. (The stack adjust
1326 instruction will wind up after the sibcall jump, and not be executed.) */
1327 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL \
1328 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1329 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1330 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1331 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1333 /* This macro is invoked just before the start of a function.
1334 It is used here to output code for -fpic that will load the
1335 return address into %ebx. */
1337 #undef ASM_OUTPUT_FUNCTION_PREFIX
1338 #define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \
1339 asm_output_function_prefix (FILE, FNNAME)
1341 /* Output assembler code to FILE to increment profiler label # LABELNO
1342 for profiling a function entry. */
1344 #define FUNCTION_PROFILER(FILE, LABELNO) \
1348 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1349 LPREFIX, (LABELNO)); \
1350 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1354 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1355 fprintf (FILE, "\tcall\t_mcount\n"); \
1360 /* There are three profiling modes for basic blocks available.
1361 The modes are selected at compile time by using the options
1362 -a or -ax of the gnu compiler.
1363 The variable `profile_block_flag' will be set according to the
1366 profile_block_flag == 0, no option used:
1370 profile_block_flag == 1, -a option used.
1372 Count frequency of execution of every basic block.
1374 profile_block_flag == 2, -ax option used.
1376 Generate code to allow several different profiling modes at run time.
1377 Available modes are:
1378 Produce a trace of all basic blocks.
1379 Count frequency of jump instructions executed.
1380 In every mode it is possible to start profiling upon entering
1381 certain functions and to disable profiling of some other functions.
1383 The result of basic-block profiling will be written to a file `bb.out'.
1384 If the -ax option is used parameters for the profiling will be read
1389 /* The following macro shall output assembler code to FILE
1390 to initialize basic-block profiling. */
1392 #undef FUNCTION_BLOCK_PROFILER
1393 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1394 ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL)
1396 /* The following macro shall output assembler code to FILE
1397 to increment a counter associated with basic block number BLOCKNO. */
1399 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1400 ix86_output_block_profiler (FILE, BLOCKNO)
1402 /* The following macro shall output rtl for the epilogue
1403 to indicate a return from function during basic-block profiling.
1405 If profiling_block_flag == 2:
1407 Output assembler code to call function `__bb_trace_ret'.
1409 Note that function `__bb_trace_ret' must not change the
1410 machine state, especially the flag register. To grant
1411 this, you must output code to save and restore registers
1412 either in this macro or in the macros MACHINE_STATE_SAVE
1413 and MACHINE_STATE_RESTORE. The last two macros will be
1414 used in the function `__bb_trace_ret', so you must make
1415 sure that the function prologue does not change any
1416 register prior to saving it with MACHINE_STATE_SAVE.
1418 else if profiling_block_flag != 0:
1420 The macro will not be used, so it need not distinguish
1424 #define FUNCTION_BLOCK_PROFILER_EXIT \
1425 emit_call_insn (gen_call (gen_rtx_MEM (QImode, \
1426 gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \
1429 /* The function `__bb_trace_func' is called in every basic block
1430 and is not allowed to change the machine state. Saving (restoring)
1431 the state can either be done in the BLOCK_PROFILER macro,
1432 before calling function (rsp. after returning from function)
1433 `__bb_trace_func', or it can be done inside the function by
1434 defining the macros:
1436 MACHINE_STATE_SAVE(ID)
1437 MACHINE_STATE_RESTORE(ID)
1439 In the latter case care must be taken, that the prologue code
1440 of function `__bb_trace_func' does not already change the
1441 state prior to saving it with MACHINE_STATE_SAVE.
1443 The parameter `ID' is a string identifying a unique macro use.
1445 On the i386 the initialization code at the begin of
1446 function `__bb_trace_func' contains a `sub' instruction
1447 therefore we handle save and restore of the flag register
1448 in the BLOCK_PROFILER macro.
1450 Note that ebx, esi, and edi are callee-save, so we don't have to
1451 preserve them explicitly. */
1453 #define MACHINE_STATE_SAVE(ID) \
1455 register int eax_ __asm__("eax"); \
1456 register int ecx_ __asm__("ecx"); \
1457 register int edx_ __asm__("edx"); \
1458 __asm__ __volatile__ ("\
1462 : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
1465 #define MACHINE_STATE_RESTORE(ID) \
1467 register int eax_ __asm__("eax"); \
1468 register int ecx_ __asm__("ecx"); \
1469 register int edx_ __asm__("edx"); \
1470 __asm__ __volatile__ ("\
1474 : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
1477 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1478 the stack pointer does not matter. The value is tested only in
1479 functions that have frame pointers.
1480 No definition is equivalent to always zero. */
1481 /* Note on the 386 it might be more efficient not to define this since
1482 we have to restore it ourselves from the frame pointer, in order to
1485 #define EXIT_IGNORE_STACK 1
1487 /* Output assembler code for a block containing the constant parts
1488 of a trampoline, leaving space for the variable parts. */
1490 /* On the 386, the trampoline contains two instructions:
1493 The trampoline is generated entirely at runtime. The operand of JMP
1494 is the address of FUNCTION relative to the instruction following the
1495 JMP (which is 5 bytes long). */
1497 /* Length in units of the trampoline for entering a nested function. */
1499 #define TRAMPOLINE_SIZE 10
1501 /* Emit RTL insns to initialize the variable parts of a trampoline.
1502 FNADDR is an RTX for the address of the function's pure code.
1503 CXT is an RTX for the static chain value for the function. */
1505 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1507 /* Compute offset from the end of the jmp to the target function. */ \
1508 rtx disp = expand_binop (SImode, sub_optab, FNADDR, \
1509 plus_constant (TRAMP, 10), \
1510 NULL_RTX, 1, OPTAB_DIRECT); \
1511 emit_move_insn (gen_rtx_MEM (QImode, TRAMP), GEN_INT (0xb9)); \
1512 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 1)), CXT); \
1513 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 5)), GEN_INT (0xe9));\
1514 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 6)), disp); \
1517 /* Definitions for register eliminations.
1519 This is an array of structures. Each structure initializes one pair
1520 of eliminable registers. The "from" register number is given first,
1521 followed by "to". Eliminations of the same "from" register are listed
1522 in order of preference.
1524 There are two registers that can always be eliminated on the i386.
1525 The frame pointer and the arg pointer can be replaced by either the
1526 hard frame pointer or to the stack pointer, depending upon the
1527 circumstances. The hard frame pointer is not used before reload and
1528 so it is not eligible for elimination. */
1530 #define ELIMINABLE_REGS \
1531 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1532 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1533 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1534 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1536 /* Given FROM and TO register numbers, say whether this elimination is
1537 allowed. Frame pointer elimination is automatically handled.
1539 All other eliminations are valid. */
1541 #define CAN_ELIMINATE(FROM, TO) \
1542 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1544 /* Define the offset between two registers, one to be eliminated, and the other
1545 its replacement, at the start of a routine. */
1547 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1548 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1550 /* Addressing modes, and classification of registers for them. */
1552 /* #define HAVE_POST_INCREMENT 0 */
1553 /* #define HAVE_POST_DECREMENT 0 */
1555 /* #define HAVE_PRE_DECREMENT 0 */
1556 /* #define HAVE_PRE_INCREMENT 0 */
1558 /* Macros to check register numbers against specific register classes. */
1560 /* These assume that REGNO is a hard or pseudo reg number.
1561 They give nonzero only if REGNO is a hard reg of the suitable class
1562 or a pseudo reg currently allocated to a suitable hard reg.
1563 Since they use reg_renumber, they are safe only once reg_renumber
1564 has been allocated, which happens in local-alloc.c. */
1566 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1567 ((REGNO) < STACK_POINTER_REGNUM \
1568 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1570 #define REGNO_OK_FOR_BASE_P(REGNO) \
1571 ((REGNO) <= STACK_POINTER_REGNUM \
1572 || (REGNO) == ARG_POINTER_REGNUM \
1573 || (REGNO) == FRAME_POINTER_REGNUM \
1574 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1576 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1577 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1579 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1580 and check its validity for a certain class.
1581 We have two alternate definitions for each of them.
1582 The usual definition accepts all pseudo regs; the other rejects
1583 them unless they have been allocated suitable hard regs.
1584 The symbol REG_OK_STRICT causes the latter definition to be used.
1586 Most source files want to accept pseudo regs in the hope that
1587 they will get allocated to the class that the insn wants them to be in.
1588 Source files for reload pass need to be strict.
1589 After reload, it makes no difference, since pseudo regs have
1590 been eliminated by then. */
1593 /* Non strict versions, pseudos are ok */
1594 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1595 (REGNO (X) < STACK_POINTER_REGNUM \
1596 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1598 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1599 (REGNO (X) <= STACK_POINTER_REGNUM \
1600 || REGNO (X) == ARG_POINTER_REGNUM \
1601 || REGNO (X) == FRAME_POINTER_REGNUM \
1602 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1604 #define REG_OK_FOR_STRREG_NONSTRICT_P(X) \
1605 (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1607 /* Strict versions, hard registers only */
1608 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1609 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1610 #define REG_OK_FOR_STRREG_STRICT_P(X) \
1611 (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X)))
1613 #ifndef REG_OK_STRICT
1614 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1615 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1616 #define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X)
1619 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1620 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1621 #define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X)
1624 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1625 that is a valid memory address for an instruction.
1626 The MODE argument is the machine mode for the MEM expression
1627 that wants to use this address.
1629 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1630 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1632 See legitimize_pic_address in i386.c for details as to what
1633 constitutes a legitimate address when -fpic is used. */
1635 #define MAX_REGS_PER_ADDRESS 2
1637 #define CONSTANT_ADDRESS_P(X) \
1638 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1639 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
1641 /* Nonzero if the constant value X is a legitimate general operand.
1642 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1644 #define LEGITIMATE_CONSTANT_P(X) 1
1646 #ifdef REG_OK_STRICT
1647 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1649 if (legitimate_address_p (MODE, X, 1)) \
1654 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1656 if (legitimate_address_p (MODE, X, 0)) \
1662 /* If defined, a C expression to determine the base term of address X.
1663 This macro is used in only one place: `find_base_term' in alias.c.
1665 It is always safe for this macro to not be defined. It exists so
1666 that alias analysis can understand machine-dependent addresses.
1668 The typical use of this macro is to handle addresses containing
1669 a label_ref or symbol_ref within an UNSPEC. */
1671 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1673 /* Try machine-dependent ways of modifying an illegitimate address
1674 to be legitimate. If we find one, return the new, valid address.
1675 This macro is used in only one place: `memory_address' in explow.c.
1677 OLDX is the address as it was before break_out_memory_refs was called.
1678 In some cases it is useful to look at this to decide what needs to be done.
1680 MODE and WIN are passed so that this macro can use
1681 GO_IF_LEGITIMATE_ADDRESS.
1683 It is always safe for this macro to do nothing. It exists to recognize
1684 opportunities to optimize the output.
1686 For the 80386, we handle X+REG by loading X into a register R and
1687 using R+REG. R will go in a general reg and indexing will be used.
1688 However, if REG is a broken-out memory address or multiplication,
1689 nothing needs to be done because REG can certainly go in a general reg.
1691 When -fpic is used, special handling is needed for symbolic references.
1692 See comments by legitimize_pic_address in i386.c for details. */
1694 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1696 (X) = legitimize_address (X, OLDX, MODE); \
1697 if (memory_address_p (MODE, X)) \
1701 #define REWRITE_ADDRESS(x) rewrite_address(x)
1703 /* Nonzero if the constant value X is a legitimate general operand
1704 when generating PIC code. It is given that flag_pic is on and
1705 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1707 #define LEGITIMATE_PIC_OPERAND_P(X) \
1708 (! SYMBOLIC_CONST (X) \
1709 || legitimate_pic_address_disp_p (X))
1711 #define SYMBOLIC_CONST(X) \
1712 (GET_CODE (X) == SYMBOL_REF \
1713 || GET_CODE (X) == LABEL_REF \
1714 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1716 /* Go to LABEL if ADDR (a legitimate address expression)
1717 has an effect that depends on the machine mode it is used for.
1718 On the 80386, only postdecrement and postincrement address depend thus
1719 (the amount of decrement or increment being the length of the operand). */
1720 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1721 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
1723 /* Define this macro if references to a symbol must be treated
1724 differently depending on something about the variable or
1725 function named by the symbol (such as what section it is in).
1727 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
1728 so that we may access it directly in the GOT. */
1730 #define ENCODE_SECTION_INFO(DECL) \
1735 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
1736 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
1738 if (GET_CODE (rtl) == MEM) \
1740 if (TARGET_DEBUG_ADDR \
1741 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
1743 fprintf (stderr, "Encode %s, public = %d\n", \
1744 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
1745 TREE_PUBLIC (DECL)); \
1748 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
1749 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
1750 || ! TREE_PUBLIC (DECL)); \
1756 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
1757 codes once the function is being compiled into assembly code, but
1758 not before. (It is not done before, because in the case of
1759 compiling an inline function, it would lead to multiple PIC
1760 prologues being included in functions which used inline functions
1761 and were compiled to assembly language.) */
1763 #define FINALIZE_PIC \
1766 current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
1771 /* If defined, a C expression whose value is nonzero if IDENTIFIER
1772 with arguments ARGS is a valid machine specific attribute for DECL.
1773 The attributes in ATTRIBUTES have previously been assigned to DECL. */
1775 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
1776 (ix86_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
1778 /* If defined, a C expression whose value is nonzero if IDENTIFIER
1779 with arguments ARGS is a valid machine specific attribute for TYPE.
1780 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
1782 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
1783 (ix86_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
1785 /* If defined, a C expression whose value is zero if the attributes on
1786 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
1787 two if they are nearly compatible (which causes a warning to be
1790 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
1791 (ix86_comp_type_attributes (TYPE1, TYPE2))
1793 /* If defined, a C statement that assigns default attributes to newly
1796 /* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */
1798 /* Max number of args passed in registers. If this is more than 3, we will
1799 have problems with ebx (register #4), since it is a caller save register and
1800 is also used as the pic register in ELF. So for now, don't allow more than
1801 3 registers to be passed in registers. */
1803 #define REGPARM_MAX 3
1806 /* Specify the machine mode that this machine uses
1807 for the index in the tablejump instruction. */
1808 #define CASE_VECTOR_MODE Pmode
1810 /* Define as C expression which evaluates to nonzero if the tablejump
1811 instruction expects the table to contain offsets from the address of the
1813 Do not define this if the table should contain absolute addresses. */
1814 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1816 /* Specify the tree operation to be used to convert reals to integers.
1817 This should be changed to take advantage of fist --wfs ??
1819 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1821 /* This is the kind of divide that is easiest to do in the general case. */
1822 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1824 /* Define this as 1 if `char' should by default be signed; else as 0. */
1825 #define DEFAULT_SIGNED_CHAR 1
1827 /* Max number of bytes we can move from memory to memory
1828 in one reasonably fast instruction. */
1831 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1832 move-instruction pairs, we will do a movstr or libcall instead.
1833 Increasing the value will always make code faster, but eventually
1834 incurs high cost in increased code size.
1836 If you don't define this, a reasonable default is used. */
1838 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1840 /* Define if shifts truncate the shift count
1841 which implies one can omit a sign-extension or zero-extension
1842 of a shift count. */
1843 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1845 /* #define SHIFT_COUNT_TRUNCATED */
1847 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1848 is done just by pretending it is already truncated. */
1849 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1851 /* We assume that the store-condition-codes instructions store 0 for false
1852 and some other value for true. This is the value stored for true. */
1854 #define STORE_FLAG_VALUE 1
1856 /* When a prototype says `char' or `short', really pass an `int'.
1857 (The 386 can't easily push less than an int.) */
1859 #define PROMOTE_PROTOTYPES 1
1861 /* A macro to update M and UNSIGNEDP when an object whose type is
1862 TYPE and which has the specified mode and signedness is to be
1863 stored in a register. This macro is only called when TYPE is a
1866 On i386 it is sometimes usefull to promote HImode and QImode
1867 quantities to SImode. The choice depends on target type. */
1869 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1870 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1871 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1874 /* Specify the machine mode that pointers have.
1875 After generation of rtl, the compiler makes no further distinction
1876 between pointers and any other objects of this machine mode. */
1877 #define Pmode SImode
1879 /* A function address in a call instruction
1880 is a byte address (for indexing purposes)
1881 so give the MEM rtx a byte's mode. */
1882 #define FUNCTION_MODE QImode
1884 /* A part of a C `switch' statement that describes the relative costs
1885 of constant RTL expressions. It must contain `case' labels for
1886 expression codes `const_int', `const', `symbol_ref', `label_ref'
1887 and `const_double'. Each case must ultimately reach a `return'
1888 statement to return the relative cost of the use of that kind of
1889 constant value in an expression. The cost may depend on the
1890 precise value of the constant, which is available for examination
1891 in X, and the rtx code of the expression in which it is contained,
1892 found in OUTER_CODE.
1894 CODE is the expression code--redundant, since it can be obtained
1895 with `GET_CODE (X)'. */
1897 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1899 return (unsigned) INTVAL (RTX) < 256 ? 0 : 1; \
1903 return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 1; \
1905 case CONST_DOUBLE: \
1908 if (GET_MODE (RTX) == VOIDmode) \
1911 code = standard_80387_constant_p (RTX); \
1912 return code == 1 ? 0 : \
1917 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
1918 #define TOPLEVEL_COSTS_N_INSNS(N) \
1919 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
1921 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
1922 This can be used, for example, to indicate how costly a multiply
1923 instruction is. In writing this macro, you can use the construct
1924 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
1925 instructions. OUTER_CODE is the code of the expression in which X
1928 This macro is optional; do not define it if the default cost
1929 assumptions are adequate for the target machine. */
1931 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1933 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1934 && GET_MODE (XEXP (X, 0)) == SImode) \
1936 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
1938 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
1939 if (value == 2 || value == 3) \
1940 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
1942 /* fall through */ \
1948 if (GET_MODE (XEXP (X, 0)) == DImode) \
1950 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1952 if (INTVAL (XEXP (X, 1)) > 32) \
1953 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
1955 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
1959 if (GET_CODE (XEXP (X, 1)) == AND) \
1960 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
1962 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
1967 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1968 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
1970 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
1975 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1977 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
1981 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
1982 if (value == 4 || value == 8) \
1983 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
1985 while (value != 0) \
1992 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
1994 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
1995 + nbits * ix86_cost->mult_bit); \
1997 else /* This is arbitrary */ \
1998 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
1999 + 7 * ix86_cost->mult_bit); \
2005 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2008 if (GET_CODE (XEXP (X, 0)) == PLUS \
2009 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2010 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2011 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2013 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \
2014 if (val == 2 || val == 4 || val == 8) \
2016 return (COSTS_N_INSNS (ix86_cost->lea) \
2017 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2018 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2019 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2022 else if (GET_CODE (XEXP (X, 0)) == MULT \
2023 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2025 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2026 if (val == 2 || val == 4 || val == 8) \
2028 return (COSTS_N_INSNS (ix86_cost->lea) \
2029 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2030 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2033 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2035 return (COSTS_N_INSNS (ix86_cost->lea) \
2036 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2037 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2038 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2041 /* fall through */ \
2046 if (GET_MODE (X) == DImode) \
2047 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2048 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2049 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2050 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2051 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2053 /* fall through */ \
2056 if (GET_MODE (X) == DImode) \
2057 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2058 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2064 /* An expression giving the cost of an addressing mode that contains
2065 ADDRESS. If not defined, the cost is computed from the ADDRESS
2066 expression and the `CONST_COSTS' values.
2068 For most CISC machines, the default cost is a good approximation
2069 of the true cost of the addressing mode. However, on RISC
2070 machines, all instructions normally have the same length and
2071 execution time. Hence all addresses will have equal costs.
2073 In cases where more than one form of an address is known, the form
2074 with the lowest cost will be used. If multiple forms have the
2075 same, lowest, cost, the one that is the most complex will be used.
2077 For example, suppose an address that is equal to the sum of a
2078 register and a constant is used twice in the same basic block.
2079 When this macro is not defined, the address will be computed in a
2080 register and memory references will be indirect through that
2081 register. On machines where the cost of the addressing mode
2082 containing the sum is no higher than that of a simple indirect
2083 reference, this will produce an additional instruction and
2084 possibly require an additional register. Proper specification of
2085 this macro eliminates this overhead for such machines.
2087 Similar use of this macro is made in strength reduction of loops.
2089 ADDRESS need not be valid as an address. In such a case, the cost
2090 is not relevant and can be any value; invalid addresses need not be
2091 assigned a different cost.
2093 On machines where an address involving more than one register is as
2094 cheap as an address computation involving only one register,
2095 defining `ADDRESS_COST' to reflect this can cause two registers to
2096 be live over a region of code where only one would have been if
2097 `ADDRESS_COST' were not defined in that manner. This effect should
2098 be considered in the definition of this macro. Equivalent costs
2099 should probably only be given to addresses with different numbers
2100 of registers on machines with lots of registers.
2102 This macro will normally either not be defined or be defined as a
2105 For i386, it is better to use a complex address than let gcc copy
2106 the address into a reg and make a new pseudo. But not if the address
2107 requires to two regs - that would mean more pseudos with longer
2110 #define ADDRESS_COST(RTX) \
2111 ix86_address_cost (x)
2113 /* A C expression for the cost of moving data from a register in class FROM to
2114 one in class TO. The classes are expressed using the enumeration values
2115 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2116 interpreted relative to that.
2118 It is not required that the cost always equal 2 when FROM is the same as TO;
2119 on some machines it is expensive to move between registers if they are not
2122 On the i386, copying between floating-point and fixed-point
2123 registers is done trough memory.
2125 Integer -> fp moves are noticeably slower than the opposite direction
2126 because of the partial memory stall they cause. Give it an
2130 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2131 ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \
2132 ? (MEMORY_MOVE_COST (DFmode, CLASS1, 0) \
2133 + MEMORY_MOVE_COST (DFmode, CLASS2, 1)) \
2134 : (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2)) ? 10 \
2135 : ((CLASS1) == MMX_REGS && (CLASS2) == SSE_REGS) ? 10 \
2136 : ((CLASS1) == SSE_REGS && (CLASS2) == MMX_REGS) ? 10 \
2137 : ((CLASS1) == MMX_REGS) != ((CLASS2) == MMX_REGS) ? 3 \
2140 /* A C expression for the cost of moving data of mode M between a
2141 register and memory. A value of 2 is the default; this cost is
2142 relative to those in `REGISTER_MOVE_COST'.
2144 If moving between registers and memory is more expensive than
2145 between two registers, you should define this macro to express the
2148 Model also increased moving costs of QImode registers in non
2152 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2153 (FLOAT_CLASS_P (CLASS) \
2154 ? (GET_MODE_SIZE (MODE)==4 \
2155 ? (IN ? ix86_cost->fp_load[0] : ix86_cost->fp_store[0]) \
2156 : (GET_MODE_SIZE (MODE)==8 \
2157 ? (IN ? ix86_cost->fp_load[1] : ix86_cost->fp_store[1]) \
2158 : (IN ? ix86_cost->fp_load[2] : ix86_cost->fp_store[2]))) \
2159 : (GET_MODE_SIZE (MODE)==1 \
2160 ? (IN ? (Q_CLASS_P (CLASS) ? ix86_cost->int_load[0] \
2161 : ix86_cost->movzbl_load) \
2162 : (Q_CLASS_P (CLASS) ? ix86_cost->int_store[0] \
2163 : ix86_cost->int_store[0] + 4)) \
2164 : (GET_MODE_SIZE (MODE)==2 \
2165 ? (IN ? ix86_cost->int_load[1] : ix86_cost->int_store[1]) \
2166 : ((IN ? ix86_cost->int_load[2] : ix86_cost->int_store[2]) \
2167 * (int) GET_MODE_SIZE (MODE) / 4))))
2169 /* A C expression for the cost of a branch instruction. A value of 1
2170 is the default; other values are interpreted relative to that. */
2172 #define BRANCH_COST ix86_branch_cost
2174 /* Define this macro as a C expression which is nonzero if accessing
2175 less than a word of memory (i.e. a `char' or a `short') is no
2176 faster than accessing a word of memory, i.e., if such access
2177 require more than one instruction or if there is no difference in
2178 cost between byte and (aligned) word loads.
2180 When this macro is not defined, the compiler will access a field by
2181 finding the smallest containing object; when it is defined, a
2182 fullword load will be used if alignment permits. Unless bytes
2183 accesses are faster than word accesses, using word accesses is
2184 preferable since it may eliminate subsequent memory access if
2185 subsequent accesses occur to other fields in the same word of the
2186 structure, but to different bytes. */
2188 #define SLOW_BYTE_ACCESS 0
2190 /* Nonzero if access to memory by shorts is slow and undesirable. */
2191 #define SLOW_SHORT_ACCESS 0
2193 /* Define this macro if zero-extension (of a `char' or `short' to an
2194 `int') can be done faster if the destination is a register that is
2197 If you define this macro, you must have instruction patterns that
2198 recognize RTL structures like this:
2200 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2202 and likewise for `HImode'. */
2204 /* #define SLOW_ZERO_EXTEND */
2206 /* Define this macro to be the value 1 if unaligned accesses have a
2207 cost many times greater than aligned accesses, for example if they
2208 are emulated in a trap handler.
2210 When this macro is non-zero, the compiler will act as if
2211 `STRICT_ALIGNMENT' were non-zero when generating code for block
2212 moves. This can cause significantly more instructions to be
2213 produced. Therefore, do not set this macro non-zero if unaligned
2214 accesses only add a cycle or two to the time for a memory access.
2216 If the value of this macro is always zero, it need not be defined. */
2218 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2220 /* Define this macro to inhibit strength reduction of memory
2221 addresses. (On some machines, such strength reduction seems to do
2222 harm rather than good.) */
2224 /* #define DONT_REDUCE_ADDR */
2226 /* Define this macro if it is as good or better to call a constant
2227 function address than to call an address kept in a register.
2229 Desirable on the 386 because a CALL with a constant address is
2230 faster than one with a register address. */
2232 #define NO_FUNCTION_CSE
2234 /* Define this macro if it is as good or better for a function to call
2235 itself with an explicit address than to call an address kept in a
2238 #define NO_RECURSIVE_FUNCTION_CSE
2240 /* A C statement (sans semicolon) to update the integer variable COST
2241 based on the relationship between INSN that is dependent on
2242 DEP_INSN through the dependence LINK. The default is to make no
2243 adjustment to COST. This can be used for example to specify to
2244 the scheduler that an output- or anti-dependence does not incur
2245 the same cost as a data-dependence. */
2247 #define ADJUST_COST(insn,link,dep_insn,cost) \
2248 (cost) = ix86_adjust_cost(insn, link, dep_insn, cost)
2250 #define ISSUE_RATE \
2253 #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \
2254 ix86_sched_init (DUMP, SCHED_VERBOSE)
2256 #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
2257 (CIM) = ix86_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK)
2259 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
2260 ((CAN_ISSUE_MORE) = \
2261 ix86_variable_issue (DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE))
2263 /* Add any extra modes needed to represent the condition code.
2265 For the i386, we need separate modes when floating-point
2266 equality comparisons are being done.
2268 Add CCNO to indicate No Overflow, which is often also includes
2269 No Carry. This is typically used on the output of logicals,
2270 and is only valid in comparisons against zero.
2272 Add CCZ to indicate that only the Zero flag is valid. */
2274 #define EXTRA_CC_MODES \
2275 CC(CCNOmode, "CCNO") \
2276 CC(CCZmode, "CCZ") \
2277 CC(CCFPmode, "CCFP") \
2278 CC(CCFPUmode, "CCFPU")
2280 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2281 return the mode to be used for the comparison.
2283 For floating-point equality comparisons, CCFPEQmode should be used.
2284 VOIDmode should be used in all other cases.
2286 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2287 possible, to allow for more combinations. */
2289 #define SELECT_CC_MODE(OP,X,Y) \
2290 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2291 ? (OP) == EQ || (OP) == NE ? CCFPUmode : CCFPmode \
2292 : (OP) == LE || (OP) == GT ? CCmode \
2293 : (Y) != const0_rtx ? CCmode \
2294 : (OP) == EQ || (OP) == NE ? CCZmode : CCNOmode)
2296 /* Control the assembler format that we output, to the extent
2297 this does not vary between assemblers. */
2299 /* How to refer to registers in assembler output.
2300 This sequence is indexed by compiler's hard-register-number (see above). */
2302 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2303 For non floating point regs, the following are the HImode names.
2305 For float regs, the stack top is sometimes referred to as "%st(0)"
2306 instead of just "%st". PRINT_REG handles this with the "y" code. */
2308 #define HI_REGISTER_NAMES \
2309 {"ax","dx","cx","bx","si","di","bp","sp", \
2310 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2311 "flags","fpsr", "dirflag", "frame" }
2313 #undef HI_REGISTER_NAMES
2314 #define HI_REGISTER_NAMES \
2315 {"ax","dx","cx","bx","si","di","bp","sp", \
2316 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2317 "flags","fpsr", "dirflag", "frame", \
2318 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2319 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" }
2321 #define REGISTER_NAMES HI_REGISTER_NAMES
2323 /* Table of additional register names to use in user input. */
2325 #define ADDITIONAL_REGISTER_NAMES \
2326 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2327 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2328 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2329 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2330 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2331 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2333 /* Note we are omitting these since currently I don't know how
2334 to get gcc to use these, since they want the same but different
2335 number as al, and ax.
2338 /* note the last four are not really qi_registers, but
2339 the md will have to never output movb into one of them
2340 only a movw . There is no movb into the last four regs */
2342 #define QI_REGISTER_NAMES \
2343 {"al", "dl", "cl", "bl", "si", "di", "bp", "sp",}
2345 /* These parallel the array above, and can be used to access bits 8:15
2346 of regs 0 through 3. */
2348 #define QI_HIGH_REGISTER_NAMES \
2349 {"ah", "dh", "ch", "bh", }
2351 #define MMX_REGISTER_NAMES \
2352 {0,0,0,0,0,0,0,0,"mm0","mm1","mm2","mm3","mm4","mm5","mm6","mm7"}
2354 /* How to renumber registers for dbx and gdb. */
2356 #define DBX_REGISTER_NUMBER(n) dbx_register_map[n]
2358 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2359 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2361 /* Before the prologue, RA is at 0(%esp). */
2362 #define INCOMING_RETURN_ADDR_RTX \
2363 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2365 /* After the prologue, RA is at -4(AP) in the current frame. */
2366 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2368 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -4))\
2369 : gen_rtx_MEM (Pmode, plus_constant (FRAME, 4)))
2371 /* PC is dbx register 8; let's use that column for RA. */
2372 #define DWARF_FRAME_RETURN_COLUMN 8
2374 /* Before the prologue, the top of the frame is at 4(%esp). */
2375 #define INCOMING_FRAME_SP_OFFSET 4
2377 /* This is how to output the definition of a user-level label named NAME,
2378 such as the label on a static function or variable NAME. */
2380 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2381 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2383 /* This is how to output an assembler line defining a `double' constant. */
2385 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2387 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2388 fprintf (FILE, "%s\t0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2391 /* This is how to output a `long double' extended real constant. */
2393 #undef ASM_OUTPUT_LONG_DOUBLE
2394 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2396 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2397 fprintf (FILE, "%s\t0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2400 /* This is how to output an assembler line defining a `float' constant. */
2402 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2404 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2405 fprintf ((FILE), "%s\t0x%lx\n", ASM_LONG, l); \
2408 /* Store in OUTPUT a string (made with alloca) containing
2409 an assembler-name for a local static variable named NAME.
2410 LABELNO is an integer which is different for each call. */
2412 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2413 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2414 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2416 /* This is how to output an assembler line defining an `int' constant. */
2418 #define ASM_OUTPUT_INT(FILE,VALUE) \
2419 ( fprintf (FILE, "%s\t", ASM_LONG), \
2420 output_addr_const (FILE,(VALUE)), \
2423 /* Likewise for `char' and `short' constants. */
2424 /* is this supposed to do align too?? */
2426 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2427 ( fprintf (FILE, "%s\t", ASM_SHORT), \
2428 output_addr_const (FILE,(VALUE)), \
2431 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2432 ( fprintf (FILE, "%s\t", ASM_BYTE_OP), \
2433 output_addr_const (FILE, (VALUE)), \
2436 /* This is how to output an assembler line for a numeric constant byte. */
2438 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2439 asm_fprintf ((FILE), "%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2441 /* This is how to output an insn to push a register on the stack.
2442 It need not be very fast code. */
2444 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2445 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2447 /* This is how to output an insn to pop a register from the stack.
2448 It need not be very fast code. */
2450 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2451 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2453 /* This is how to output an element of a case-vector that is absolute.
2456 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2457 fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE)
2459 /* This is how to output an element of a case-vector that is relative.
2460 We don't use these on the 386 yet, because the ATT assembler can't do
2461 forward reference the differences.
2464 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2465 fprintf (FILE, "\t%s\t%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
2467 /* A C statement that outputs an address constant appropriate to
2468 for DWARF debugging. */
2470 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2471 i386_dwarf_output_addr_const((FILE),(X))
2473 /* Either simplify a location expression, or return the original. */
2475 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2476 i386_simplify_dwarf_addr(X)
2478 /* Define the parentheses used to group arithmetic operations
2479 in assembler code. */
2481 #define ASM_OPEN_PAREN ""
2482 #define ASM_CLOSE_PAREN ""
2484 /* Define results of standard character escape sequences. */
2485 #define TARGET_BELL 007
2486 #define TARGET_BS 010
2487 #define TARGET_TAB 011
2488 #define TARGET_NEWLINE 012
2489 #define TARGET_VT 013
2490 #define TARGET_FF 014
2491 #define TARGET_CR 015
2493 /* Print operand X (an rtx) in assembler syntax to file FILE.
2494 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2495 The CODE z takes the size of operand from the following digit, and
2496 outputs b,w,or l respectively.
2498 On the 80386, we use several such letters:
2499 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
2500 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
2501 R -- print the prefix for register names.
2502 z -- print the opcode suffix for the size of the current operand.
2503 * -- print a star (in certain assembler syntax)
2504 P -- if PIC, print an @PLT suffix.
2505 X -- don't print any sort of PIC '@' suffix for a symbol.
2506 s -- ??? something to do with double shifts. not actually used, afaik.
2507 C -- print a conditional move suffix corresponding to the op code.
2508 c -- likewise, but reverse the condition.
2509 F,f -- likewise, but for floating-point. */
2511 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2514 /* Print the name of a register based on its machine mode and number.
2515 If CODE is 'w', pretend the mode is HImode.
2516 If CODE is 'b', pretend the mode is QImode.
2517 If CODE is 'k', pretend the mode is SImode.
2518 If CODE is 'h', pretend the reg is the `high' byte register.
2519 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2521 #define PRINT_REG(X, CODE, FILE) \
2522 print_reg (X, CODE, FILE)
2524 #define PRINT_OPERAND(FILE, X, CODE) \
2525 print_operand (FILE, X, CODE)
2527 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2528 print_operand_address (FILE, ADDR)
2530 /* Print the name of a register for based on its machine mode and number.
2531 This macro is used to print debugging output.
2532 This macro is different from PRINT_REG in that it may be used in
2533 programs that are not linked with aux-output.o. */
2535 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2536 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2537 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2538 fprintf (FILE, "%d ", REGNO (X)); \
2539 if (REGNO (X) == FLAGS_REG) \
2540 { fputs ("flags", FILE); break; } \
2541 if (REGNO (X) == DIRFLAG_REG) \
2542 { fputs ("dirflag", FILE); break; } \
2543 if (REGNO (X) == FPSR_REG) \
2544 { fputs ("fpsr", FILE); break; } \
2545 if (REGNO (X) == ARG_POINTER_REGNUM) \
2546 { fputs ("argp", FILE); break; } \
2547 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2548 { fputs ("frame", FILE); break; } \
2549 if (STACK_TOP_P (X)) \
2550 { fputs ("st(0)", FILE); break; } \
2552 { fputs (hi_name[REGNO(X)], FILE); break; } \
2553 switch (GET_MODE_SIZE (GET_MODE (X))) \
2556 fputs ("e", FILE); \
2558 fputs (hi_name[REGNO (X)], FILE); \
2561 fputs (qi_name[REGNO (X)], FILE); \
2566 /* Routines in libgcc that return floats must return them in an fp reg,
2567 just as other functions do which return such values.
2568 These macros make that happen. */
2570 #define FLOAT_VALUE_TYPE float
2571 #define INTIFY(FLOATVAL) FLOATVAL
2573 /* a letter which is not needed by the normal asm syntax, which
2574 we can use for operand syntax in the extended asm */
2576 #define ASM_OPERAND_LETTER '#'
2577 #define RET return ""
2578 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
2580 /* Define the codes that are matched by predicates in i386.c. */
2582 #define PREDICATE_CODES \
2583 {"const_int_1_operand", {CONST_INT}}, \
2584 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2585 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2586 LABEL_REF, SUBREG, REG, MEM}}, \
2587 {"pic_symbolic_operand", {CONST}}, \
2588 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
2589 {"constant_call_address_operand", {SYMBOL_REF}}, \
2590 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
2591 {"const1_operand", {CONST_INT}}, \
2592 {"const248_operand", {CONST_INT}}, \
2593 {"incdec_operand", {CONST_INT}}, \
2594 {"reg_no_sp_operand", {SUBREG, REG}}, \
2595 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
2596 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
2597 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
2598 {"q_regs_operand", {SUBREG, REG}}, \
2599 {"non_q_regs_operand", {SUBREG, REG}}, \
2600 {"no_comparison_operator", {EQ, NE, LT, GE, LTU, GTU, LEU, GEU}}, \
2601 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU}}, \
2602 {"uno_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
2603 GTU, UNORDERED, ORDERED}}, \
2604 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
2605 {"ext_register_operand", {SUBREG, REG}}, \
2606 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
2607 {"mult_operator", {MULT}}, \
2608 {"div_operator", {DIV}}, \
2609 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
2610 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
2611 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
2612 LSHIFTRT, ROTATERT}}, \
2613 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
2614 {"memory_displacement_operand", {MEM}}, \
2615 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2616 LABEL_REF, SUBREG, REG, MEM, AND}}, \
2617 {"long_memory_operand", {MEM}},
2619 /* A list of predicates that do special things with modes, and so
2620 should not elicit warnings for VOIDmode match_operand. */
2622 #define SPECIAL_MODE_PREDICATES \
2623 "ext_register_operand",
2625 /* Variables in i386.c */
2626 extern const char *ix86_cpu_string
; /* for -mcpu=<xxx> */
2627 extern const char *ix86_arch_string
; /* for -march=<xxx> */
2628 extern const char *ix86_reg_alloc_order
; /* register allocation order */
2629 extern const char *ix86_regparm_string
; /* # registers to use to pass args */
2630 extern const char *ix86_align_loops_string
; /* power of two alignment for loops */
2631 extern const char *ix86_align_jumps_string
; /* power of two alignment for non-loop jumps */
2632 extern const char *ix86_align_funcs_string
; /* power of two alignment for functions */
2633 extern const char *ix86_preferred_stack_boundary_string
;/* power of two alignment for stack boundary */
2634 extern const char *ix86_branch_cost_string
; /* values 1-5: see jump.c */
2635 extern int ix86_regparm
; /* ix86_regparm_string as a number */
2636 extern int ix86_align_loops
; /* power of two alignment for loops */
2637 extern int ix86_align_jumps
; /* power of two alignment for non-loop jumps */
2638 extern int ix86_align_funcs
; /* power of two alignment for functions */
2639 extern int ix86_preferred_stack_boundary
; /* preferred stack boundary alignment in bits */
2640 extern int ix86_branch_cost
; /* values 1-5: see jump.c */
2641 extern const char * const hi_reg_name
[]; /* names for 16 bit regs */
2642 extern const char * const qi_reg_name
[]; /* names for 8 bit regs (low) */
2643 extern const char * const qi_high_reg_name
[]; /* names for 8 bit regs (high) */
2644 extern enum reg_class
const regclass_map
[]; /* smalled class containing REGNO */
2645 extern struct rtx_def
*ix86_compare_op0
; /* operand 0 for comparisons */
2646 extern struct rtx_def
*ix86_compare_op1
; /* operand 1 for comparisons */