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i386.h (TARGET_SAHF): New define.
[gcc.git] / gcc / config / i386 / i386.h
1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation,
4 Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "config/vxworks-dummy.h"
24
25 /* Algorithm to expand string function with. */
26 enum stringop_alg
27 {
28 no_stringop,
29 libcall,
30 rep_prefix_1_byte,
31 rep_prefix_4_byte,
32 rep_prefix_8_byte,
33 loop_1_byte,
34 loop,
35 unrolled_loop
36 };
37 #define NAX_STRINGOP_ALGS 4
38 /* Specify what algorithm to use for stringops on known size.
39 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
40 known at compile time or estimated via feedback, the SIZE array
41 is walked in order until MAX is greater then the estimate (or -1
42 means infinity). Corresponding ALG is used then.
43 For example initializer:
44 {{256, loop}, {-1, rep_prefix_4_byte}}
45 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
46 be used otherwise.
47 */
48 struct stringop_algs
49 {
50 const enum stringop_alg unknown_size;
51 const struct stringop_strategy {
52 const int max;
53 const enum stringop_alg alg;
54 } size [NAX_STRINGOP_ALGS];
55 };
56
57 /* The purpose of this file is to define the characteristics of the i386,
58 independent of assembler syntax or operating system.
59
60 Three other files build on this one to describe a specific assembler syntax:
61 bsd386.h, att386.h, and sun386.h.
62
63 The actual tm.h file for a particular system should include
64 this file, and then the file for the appropriate assembler syntax.
65
66 Many macros that specify assembler syntax are omitted entirely from
67 this file because they really belong in the files for particular
68 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
69 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
70 that start with ASM_ or end in ASM_OP. */
71
72 /* Define the specific costs for a given cpu */
73
74 struct processor_costs {
75 const int add; /* cost of an add instruction */
76 const int lea; /* cost of a lea instruction */
77 const int shift_var; /* variable shift costs */
78 const int shift_const; /* constant shift costs */
79 const int mult_init[5]; /* cost of starting a multiply
80 in QImode, HImode, SImode, DImode, TImode*/
81 const int mult_bit; /* cost of multiply per each bit set */
82 const int divide[5]; /* cost of a divide/mod
83 in QImode, HImode, SImode, DImode, TImode*/
84 int movsx; /* The cost of movsx operation. */
85 int movzx; /* The cost of movzx operation. */
86 const int large_insn; /* insns larger than this cost more */
87 const int move_ratio; /* The threshold of number of scalar
88 memory-to-memory move insns. */
89 const int movzbl_load; /* cost of loading using movzbl */
90 const int int_load[3]; /* cost of loading integer registers
91 in QImode, HImode and SImode relative
92 to reg-reg move (2). */
93 const int int_store[3]; /* cost of storing integer register
94 in QImode, HImode and SImode */
95 const int fp_move; /* cost of reg,reg fld/fst */
96 const int fp_load[3]; /* cost of loading FP register
97 in SFmode, DFmode and XFmode */
98 const int fp_store[3]; /* cost of storing FP register
99 in SFmode, DFmode and XFmode */
100 const int mmx_move; /* cost of moving MMX register. */
101 const int mmx_load[2]; /* cost of loading MMX register
102 in SImode and DImode */
103 const int mmx_store[2]; /* cost of storing MMX register
104 in SImode and DImode */
105 const int sse_move; /* cost of moving SSE register. */
106 const int sse_load[3]; /* cost of loading SSE register
107 in SImode, DImode and TImode*/
108 const int sse_store[3]; /* cost of storing SSE register
109 in SImode, DImode and TImode*/
110 const int mmxsse_to_integer; /* cost of moving mmxsse register to
111 integer and vice versa. */
112 const int prefetch_block; /* bytes moved to cache for prefetch. */
113 const int simultaneous_prefetches; /* number of parallel prefetch
114 operations. */
115 const int branch_cost; /* Default value for BRANCH_COST. */
116 const int fadd; /* cost of FADD and FSUB instructions. */
117 const int fmul; /* cost of FMUL instruction. */
118 const int fdiv; /* cost of FDIV instruction. */
119 const int fabs; /* cost of FABS instruction. */
120 const int fchs; /* cost of FCHS instruction. */
121 const int fsqrt; /* cost of FSQRT instruction. */
122 /* Specify what algorithm
123 to use for stringops on unknown size. */
124 struct stringop_algs memcpy[2], memset[2];
125 };
126
127 extern const struct processor_costs *ix86_cost;
128
129 /* Macros used in the machine description to test the flags. */
130
131 /* configure can arrange to make this 2, to force a 486. */
132
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
135 #endif
136
137 #ifndef TARGET_FPMATH_DEFAULT
138 #define TARGET_FPMATH_DEFAULT \
139 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
140 #endif
141
142 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
143
144 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
145 compile-time constant. */
146 #ifdef IN_LIBGCC2
147 #undef TARGET_64BIT
148 #ifdef __x86_64__
149 #define TARGET_64BIT 1
150 #else
151 #define TARGET_64BIT 0
152 #endif
153 #else
154 #ifndef TARGET_BI_ARCH
155 #undef TARGET_64BIT
156 #if TARGET_64BIT_DEFAULT
157 #define TARGET_64BIT 1
158 #else
159 #define TARGET_64BIT 0
160 #endif
161 #endif
162 #endif
163
164 #define HAS_LONG_COND_BRANCH 1
165 #define HAS_LONG_UNCOND_BRANCH 1
166
167 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
168 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
169 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
170 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
171 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
172 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
173 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
174 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
175 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
176 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
177 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
178 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
179 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
180 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
181 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
182 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
183
184 /* Feature tests against the various tunings. */
185 enum ix86_tune_indices {
186 X86_TUNE_USE_LEAVE,
187 X86_TUNE_PUSH_MEMORY,
188 X86_TUNE_ZERO_EXTEND_WITH_AND,
189 X86_TUNE_USE_BIT_TEST,
190 X86_TUNE_UNROLL_STRLEN,
191 X86_TUNE_DEEP_BRANCH_PREDICTION,
192 X86_TUNE_BRANCH_PREDICTION_HINTS,
193 X86_TUNE_DOUBLE_WITH_ADD,
194 X86_TUNE_USE_SAHF,
195 X86_TUNE_MOVX,
196 X86_TUNE_PARTIAL_REG_STALL,
197 X86_TUNE_PARTIAL_FLAG_REG_STALL,
198 X86_TUNE_USE_HIMODE_FIOP,
199 X86_TUNE_USE_SIMODE_FIOP,
200 X86_TUNE_USE_MOV0,
201 X86_TUNE_USE_CLTD,
202 X86_TUNE_USE_XCHGB,
203 X86_TUNE_SPLIT_LONG_MOVES,
204 X86_TUNE_READ_MODIFY_WRITE,
205 X86_TUNE_READ_MODIFY,
206 X86_TUNE_PROMOTE_QIMODE,
207 X86_TUNE_FAST_PREFIX,
208 X86_TUNE_SINGLE_STRINGOP,
209 X86_TUNE_QIMODE_MATH,
210 X86_TUNE_HIMODE_MATH,
211 X86_TUNE_PROMOTE_QI_REGS,
212 X86_TUNE_PROMOTE_HI_REGS,
213 X86_TUNE_ADD_ESP_4,
214 X86_TUNE_ADD_ESP_8,
215 X86_TUNE_SUB_ESP_4,
216 X86_TUNE_SUB_ESP_8,
217 X86_TUNE_INTEGER_DFMODE_MOVES,
218 X86_TUNE_PARTIAL_REG_DEPENDENCY,
219 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
220 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
221 X86_TUNE_SSE_SPLIT_REGS,
222 X86_TUNE_SSE_TYPELESS_STORES,
223 X86_TUNE_SSE_LOAD0_BY_PXOR,
224 X86_TUNE_MEMORY_MISMATCH_STALL,
225 X86_TUNE_PROLOGUE_USING_MOVE,
226 X86_TUNE_EPILOGUE_USING_MOVE,
227 X86_TUNE_SHIFT1,
228 X86_TUNE_USE_FFREEP,
229 X86_TUNE_INTER_UNIT_MOVES,
230 X86_TUNE_FOUR_JUMP_LIMIT,
231 X86_TUNE_SCHEDULE,
232 X86_TUNE_USE_BT,
233 X86_TUNE_USE_INCDEC,
234 X86_TUNE_PAD_RETURNS,
235 X86_TUNE_EXT_80387_CONSTANTS,
236
237 X86_TUNE_LAST
238 };
239
240 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
241
242 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
243 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
244 #define TARGET_ZERO_EXTEND_WITH_AND \
245 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
246 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
247 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
248 #define TARGET_DEEP_BRANCH_PREDICTION \
249 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
250 #define TARGET_BRANCH_PREDICTION_HINTS \
251 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
252 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
253 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
254 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
255 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
256 #define TARGET_PARTIAL_FLAG_REG_STALL \
257 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
258 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
259 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
260 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
261 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
262 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
263 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
264 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
265 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
266 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
267 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
268 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
269 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
270 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
271 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
272 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
273 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
274 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
275 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
276 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
277 #define TARGET_INTEGER_DFMODE_MOVES \
278 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
279 #define TARGET_PARTIAL_REG_DEPENDENCY \
280 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
281 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
282 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
283 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
284 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
285 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
286 #define TARGET_SSE_TYPELESS_STORES \
287 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
288 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
289 #define TARGET_MEMORY_MISMATCH_STALL \
290 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
291 #define TARGET_PROLOGUE_USING_MOVE \
292 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
293 #define TARGET_EPILOGUE_USING_MOVE \
294 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
295 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
296 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
297 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
298 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
299 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
300 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
301 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
302 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
303 #define TARGET_EXT_80387_CONSTANTS \
304 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
305
306 /* Feature tests against the various architecture variations. */
307 enum ix86_arch_indices {
308 X86_ARCH_CMOVE, /* || TARGET_SSE */
309 X86_ARCH_CMPXCHG,
310 X86_ARCH_CMPXCHG8B,
311 X86_ARCH_XADD,
312 X86_ARCH_BSWAP,
313
314 X86_ARCH_LAST
315 };
316
317 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
318
319 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
320 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
321 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
322 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
323 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
324
325 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
326
327 extern int x86_prefetch_sse;
328 #define TARGET_PREFETCH_SSE x86_prefetch_sse
329
330 extern int x86_cmpxchg16b;
331 #define TARGET_CMPXCHG16B x86_cmpxchg16b
332
333 extern int x86_sahf;
334 #define TARGET_SAHF x86_sahf
335
336 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
337
338 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
339 #define TARGET_MIX_SSE_I387 \
340 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
341
342 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
343 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
344 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
345 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
346
347 #ifndef TARGET_64BIT_DEFAULT
348 #define TARGET_64BIT_DEFAULT 0
349 #endif
350 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
351 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
352 #endif
353
354 /* Once GDB has been enhanced to deal with functions without frame
355 pointers, we can change this to allow for elimination of
356 the frame pointer in leaf functions. */
357 #define TARGET_DEFAULT 0
358
359 /* This is not really a target flag, but is done this way so that
360 it's analogous to similar code for Mach-O on PowerPC. darwin.h
361 redefines this to 1. */
362 #define TARGET_MACHO 0
363
364 /* Subtargets may reset this to 1 in order to enable 96-bit long double
365 with the rounding mode forced to 53 bits. */
366 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
367
368 /* Sometimes certain combinations of command options do not make
369 sense on a particular target machine. You can define a macro
370 `OVERRIDE_OPTIONS' to take account of this. This macro, if
371 defined, is executed once just after all the command options have
372 been parsed.
373
374 Don't use this macro to turn on various extra optimizations for
375 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
376
377 #define OVERRIDE_OPTIONS override_options ()
378
379 /* Define this to change the optimizations performed by default. */
380 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
381 optimization_options ((LEVEL), (SIZE))
382
383 /* -march=native handling only makes sense with compiler running on
384 an x86 or x86_64 chip. If changing this condition, also change
385 the condition in driver-i386.c. */
386 #if defined(__i386__) || defined(__x86_64__)
387 /* In driver-i386.c. */
388 extern const char *host_detect_local_cpu (int argc, const char **argv);
389 #define EXTRA_SPEC_FUNCTIONS \
390 { "local_cpu_detect", host_detect_local_cpu },
391 #define HAVE_LOCAL_CPU_DETECT
392 #endif
393
394 /* Support for configure-time defaults of some command line options.
395 The order here is important so that -march doesn't squash the
396 tune or cpu values. */
397 #define OPTION_DEFAULT_SPECS \
398 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
399 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
400 {"arch", "%{!march=*:-march=%(VALUE)}"}
401
402 /* Specs for the compiler proper */
403
404 #ifndef CC1_CPU_SPEC
405 #define CC1_CPU_SPEC_1 "\
406 %{!mtune*: \
407 %{m386:mtune=i386 \
408 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
409 %{m486:-mtune=i486 \
410 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
411 %{mpentium:-mtune=pentium \
412 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
413 %{mpentiumpro:-mtune=pentiumpro \
414 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
415 %{mcpu=*:-mtune=%* \
416 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
417 %<mcpu=* \
418 %{mintel-syntax:-masm=intel \
419 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
420 %{mno-intel-syntax:-masm=att \
421 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
422
423 #ifndef HAVE_LOCAL_CPU_DETECT
424 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
425 #else
426 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
427 "%{march=native:%<march=native %:local_cpu_detect(arch) \
428 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
429 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
430 #endif
431 #endif
432 \f
433 /* Target CPU builtins. */
434 #define TARGET_CPU_CPP_BUILTINS() \
435 do \
436 { \
437 size_t arch_len = strlen (ix86_arch_string); \
438 size_t tune_len = strlen (ix86_tune_string); \
439 int last_arch_char = ix86_arch_string[arch_len - 1]; \
440 int last_tune_char = ix86_tune_string[tune_len - 1]; \
441 \
442 if (TARGET_64BIT) \
443 { \
444 builtin_assert ("cpu=x86_64"); \
445 builtin_assert ("machine=x86_64"); \
446 builtin_define ("__amd64"); \
447 builtin_define ("__amd64__"); \
448 builtin_define ("__x86_64"); \
449 builtin_define ("__x86_64__"); \
450 } \
451 else \
452 { \
453 builtin_assert ("cpu=i386"); \
454 builtin_assert ("machine=i386"); \
455 builtin_define_std ("i386"); \
456 } \
457 \
458 /* Built-ins based on -mtune= (or -march= if no \
459 -mtune= given). */ \
460 if (TARGET_386) \
461 builtin_define ("__tune_i386__"); \
462 else if (TARGET_486) \
463 builtin_define ("__tune_i486__"); \
464 else if (TARGET_PENTIUM) \
465 { \
466 builtin_define ("__tune_i586__"); \
467 builtin_define ("__tune_pentium__"); \
468 if (last_tune_char == 'x') \
469 builtin_define ("__tune_pentium_mmx__"); \
470 } \
471 else if (TARGET_PENTIUMPRO) \
472 { \
473 builtin_define ("__tune_i686__"); \
474 builtin_define ("__tune_pentiumpro__"); \
475 switch (last_tune_char) \
476 { \
477 case '3': \
478 builtin_define ("__tune_pentium3__"); \
479 /* FALLTHRU */ \
480 case '2': \
481 builtin_define ("__tune_pentium2__"); \
482 break; \
483 } \
484 } \
485 else if (TARGET_GEODE) \
486 { \
487 builtin_define ("__tune_geode__"); \
488 } \
489 else if (TARGET_K6) \
490 { \
491 builtin_define ("__tune_k6__"); \
492 if (last_tune_char == '2') \
493 builtin_define ("__tune_k6_2__"); \
494 else if (last_tune_char == '3') \
495 builtin_define ("__tune_k6_3__"); \
496 } \
497 else if (TARGET_ATHLON) \
498 { \
499 builtin_define ("__tune_athlon__"); \
500 /* Only plain "athlon" lacks SSE. */ \
501 if (last_tune_char != 'n') \
502 builtin_define ("__tune_athlon_sse__"); \
503 } \
504 else if (TARGET_K8) \
505 builtin_define ("__tune_k8__"); \
506 else if (TARGET_AMDFAM10) \
507 builtin_define ("__tune_amdfam10__"); \
508 else if (TARGET_PENTIUM4) \
509 builtin_define ("__tune_pentium4__"); \
510 else if (TARGET_NOCONA) \
511 builtin_define ("__tune_nocona__"); \
512 else if (TARGET_CORE2) \
513 builtin_define ("__tune_core2__"); \
514 \
515 if (TARGET_MMX) \
516 builtin_define ("__MMX__"); \
517 if (TARGET_3DNOW) \
518 builtin_define ("__3dNOW__"); \
519 if (TARGET_3DNOW_A) \
520 builtin_define ("__3dNOW_A__"); \
521 if (TARGET_SSE) \
522 builtin_define ("__SSE__"); \
523 if (TARGET_SSE2) \
524 builtin_define ("__SSE2__"); \
525 if (TARGET_SSE3) \
526 builtin_define ("__SSE3__"); \
527 if (TARGET_SSSE3) \
528 builtin_define ("__SSSE3__"); \
529 if (TARGET_SSE4A) \
530 builtin_define ("__SSE4A__"); \
531 if (TARGET_SSE_MATH && TARGET_SSE) \
532 builtin_define ("__SSE_MATH__"); \
533 if (TARGET_SSE_MATH && TARGET_SSE2) \
534 builtin_define ("__SSE2_MATH__"); \
535 \
536 /* Built-ins based on -march=. */ \
537 if (ix86_arch == PROCESSOR_I486) \
538 { \
539 builtin_define ("__i486"); \
540 builtin_define ("__i486__"); \
541 } \
542 else if (ix86_arch == PROCESSOR_PENTIUM) \
543 { \
544 builtin_define ("__i586"); \
545 builtin_define ("__i586__"); \
546 builtin_define ("__pentium"); \
547 builtin_define ("__pentium__"); \
548 if (last_arch_char == 'x') \
549 builtin_define ("__pentium_mmx__"); \
550 } \
551 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
552 { \
553 builtin_define ("__i686"); \
554 builtin_define ("__i686__"); \
555 builtin_define ("__pentiumpro"); \
556 builtin_define ("__pentiumpro__"); \
557 } \
558 else if (ix86_arch == PROCESSOR_GEODE) \
559 { \
560 builtin_define ("__geode"); \
561 builtin_define ("__geode__"); \
562 } \
563 else if (ix86_arch == PROCESSOR_K6) \
564 { \
565 \
566 builtin_define ("__k6"); \
567 builtin_define ("__k6__"); \
568 if (last_arch_char == '2') \
569 builtin_define ("__k6_2__"); \
570 else if (last_arch_char == '3') \
571 builtin_define ("__k6_3__"); \
572 } \
573 else if (ix86_arch == PROCESSOR_ATHLON) \
574 { \
575 builtin_define ("__athlon"); \
576 builtin_define ("__athlon__"); \
577 /* Only plain "athlon" lacks SSE. */ \
578 if (last_arch_char != 'n') \
579 builtin_define ("__athlon_sse__"); \
580 } \
581 else if (ix86_arch == PROCESSOR_K8) \
582 { \
583 builtin_define ("__k8"); \
584 builtin_define ("__k8__"); \
585 } \
586 else if (ix86_arch == PROCESSOR_AMDFAM10) \
587 { \
588 builtin_define ("__amdfam10"); \
589 builtin_define ("__amdfam10__"); \
590 } \
591 else if (ix86_arch == PROCESSOR_PENTIUM4) \
592 { \
593 builtin_define ("__pentium4"); \
594 builtin_define ("__pentium4__"); \
595 } \
596 else if (ix86_arch == PROCESSOR_NOCONA) \
597 { \
598 builtin_define ("__nocona"); \
599 builtin_define ("__nocona__"); \
600 } \
601 else if (ix86_arch == PROCESSOR_CORE2) \
602 { \
603 builtin_define ("__core2"); \
604 builtin_define ("__core2__"); \
605 } \
606 } \
607 while (0)
608
609 #define TARGET_CPU_DEFAULT_i386 0
610 #define TARGET_CPU_DEFAULT_i486 1
611 #define TARGET_CPU_DEFAULT_pentium 2
612 #define TARGET_CPU_DEFAULT_pentium_mmx 3
613 #define TARGET_CPU_DEFAULT_pentiumpro 4
614 #define TARGET_CPU_DEFAULT_pentium2 5
615 #define TARGET_CPU_DEFAULT_pentium3 6
616 #define TARGET_CPU_DEFAULT_pentium4 7
617 #define TARGET_CPU_DEFAULT_geode 8
618 #define TARGET_CPU_DEFAULT_k6 9
619 #define TARGET_CPU_DEFAULT_k6_2 10
620 #define TARGET_CPU_DEFAULT_k6_3 11
621 #define TARGET_CPU_DEFAULT_athlon 12
622 #define TARGET_CPU_DEFAULT_athlon_sse 13
623 #define TARGET_CPU_DEFAULT_k8 14
624 #define TARGET_CPU_DEFAULT_pentium_m 15
625 #define TARGET_CPU_DEFAULT_prescott 16
626 #define TARGET_CPU_DEFAULT_nocona 17
627 #define TARGET_CPU_DEFAULT_core2 18
628 #define TARGET_CPU_DEFAULT_generic 19
629 #define TARGET_CPU_DEFAULT_amdfam10 20
630
631 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
632 "pentiumpro", "pentium2", "pentium3", \
633 "pentium4", "geode", "k6", "k6-2", "k6-3", \
634 "athlon", "athlon-4", "k8", \
635 "pentium-m", "prescott", "nocona", \
636 "core2", "generic", "amdfam10"}
637
638 #ifndef CC1_SPEC
639 #define CC1_SPEC "%(cc1_cpu) "
640 #endif
641
642 /* This macro defines names of additional specifications to put in the
643 specs that can be used in various specifications like CC1_SPEC. Its
644 definition is an initializer with a subgrouping for each command option.
645
646 Each subgrouping contains a string constant, that defines the
647 specification name, and a string constant that used by the GCC driver
648 program.
649
650 Do not define this macro if it does not need to do anything. */
651
652 #ifndef SUBTARGET_EXTRA_SPECS
653 #define SUBTARGET_EXTRA_SPECS
654 #endif
655
656 #define EXTRA_SPECS \
657 { "cc1_cpu", CC1_CPU_SPEC }, \
658 SUBTARGET_EXTRA_SPECS
659 \f
660 /* target machine storage layout */
661
662 #define LONG_DOUBLE_TYPE_SIZE 80
663
664 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
665 FPU, assume that the fpcw is set to extended precision; when using
666 only SSE, rounding is correct; when using both SSE and the FPU,
667 the rounding precision is indeterminate, since either may be chosen
668 apparently at random. */
669 #define TARGET_FLT_EVAL_METHOD \
670 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
671
672 #define SHORT_TYPE_SIZE 16
673 #define INT_TYPE_SIZE 32
674 #define FLOAT_TYPE_SIZE 32
675 #define LONG_TYPE_SIZE BITS_PER_WORD
676 #define DOUBLE_TYPE_SIZE 64
677 #define LONG_LONG_TYPE_SIZE 64
678
679 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
680 #define MAX_BITS_PER_WORD 64
681 #else
682 #define MAX_BITS_PER_WORD 32
683 #endif
684
685 /* Define this if most significant byte of a word is the lowest numbered. */
686 /* That is true on the 80386. */
687
688 #define BITS_BIG_ENDIAN 0
689
690 /* Define this if most significant byte of a word is the lowest numbered. */
691 /* That is not true on the 80386. */
692 #define BYTES_BIG_ENDIAN 0
693
694 /* Define this if most significant word of a multiword number is the lowest
695 numbered. */
696 /* Not true for 80386 */
697 #define WORDS_BIG_ENDIAN 0
698
699 /* Width of a word, in units (bytes). */
700 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
701 #ifdef IN_LIBGCC2
702 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
703 #else
704 #define MIN_UNITS_PER_WORD 4
705 #endif
706
707 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
708 #define PARM_BOUNDARY BITS_PER_WORD
709
710 /* Boundary (in *bits*) on which stack pointer should be aligned. */
711 #define STACK_BOUNDARY BITS_PER_WORD
712
713 /* Boundary (in *bits*) on which the stack pointer prefers to be
714 aligned; the compiler cannot rely on having this alignment. */
715 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
716
717 /* As of July 2001, many runtimes do not align the stack properly when
718 entering main. This causes expand_main_function to forcibly align
719 the stack, which results in aligned frames for functions called from
720 main, though it does nothing for the alignment of main itself. */
721 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
722 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
723
724 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
725 mandatory for the 64-bit ABI, and may or may not be true for other
726 operating systems. */
727 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
728
729 /* Minimum allocation boundary for the code of a function. */
730 #define FUNCTION_BOUNDARY 8
731
732 /* C++ stores the virtual bit in the lowest bit of function pointers. */
733 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
734
735 /* Alignment of field after `int : 0' in a structure. */
736
737 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
738
739 /* Minimum size in bits of the largest boundary to which any
740 and all fundamental data types supported by the hardware
741 might need to be aligned. No data type wants to be aligned
742 rounder than this.
743
744 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
745 and Pentium Pro XFmode values at 128 bit boundaries. */
746
747 #define BIGGEST_ALIGNMENT 128
748
749 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
750 #define ALIGN_MODE_128(MODE) \
751 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
752
753 /* The published ABIs say that doubles should be aligned on word
754 boundaries, so lower the alignment for structure fields unless
755 -malign-double is set. */
756
757 /* ??? Blah -- this macro is used directly by libobjc. Since it
758 supports no vector modes, cut out the complexity and fall back
759 on BIGGEST_FIELD_ALIGNMENT. */
760 #ifdef IN_TARGET_LIBS
761 #ifdef __x86_64__
762 #define BIGGEST_FIELD_ALIGNMENT 128
763 #else
764 #define BIGGEST_FIELD_ALIGNMENT 32
765 #endif
766 #else
767 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
768 x86_field_alignment (FIELD, COMPUTED)
769 #endif
770
771 /* If defined, a C expression to compute the alignment given to a
772 constant that is being placed in memory. EXP is the constant
773 and ALIGN is the alignment that the object would ordinarily have.
774 The value of this macro is used instead of that alignment to align
775 the object.
776
777 If this macro is not defined, then ALIGN is used.
778
779 The typical use of this macro is to increase alignment for string
780 constants to be word aligned so that `strcpy' calls that copy
781 constants can be done inline. */
782
783 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
784
785 /* If defined, a C expression to compute the alignment for a static
786 variable. TYPE is the data type, and ALIGN is the alignment that
787 the object would ordinarily have. The value of this macro is used
788 instead of that alignment to align the object.
789
790 If this macro is not defined, then ALIGN is used.
791
792 One use of this macro is to increase alignment of medium-size
793 data to make it all fit in fewer cache lines. Another is to
794 cause character arrays to be word-aligned so that `strcpy' calls
795 that copy constants to character arrays can be done inline. */
796
797 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
798
799 /* If defined, a C expression to compute the alignment for a local
800 variable. TYPE is the data type, and ALIGN is the alignment that
801 the object would ordinarily have. The value of this macro is used
802 instead of that alignment to align the object.
803
804 If this macro is not defined, then ALIGN is used.
805
806 One use of this macro is to increase alignment of medium-size
807 data to make it all fit in fewer cache lines. */
808
809 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
810
811 /* If defined, a C expression that gives the alignment boundary, in
812 bits, of an argument with the specified mode and type. If it is
813 not defined, `PARM_BOUNDARY' is used for all arguments. */
814
815 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
816 ix86_function_arg_boundary ((MODE), (TYPE))
817
818 /* Set this nonzero if move instructions will actually fail to work
819 when given unaligned data. */
820 #define STRICT_ALIGNMENT 0
821
822 /* If bit field type is int, don't let it cross an int,
823 and give entire struct the alignment of an int. */
824 /* Required on the 386 since it doesn't have bit-field insns. */
825 #define PCC_BITFIELD_TYPE_MATTERS 1
826 \f
827 /* Standard register usage. */
828
829 /* This processor has special stack-like registers. See reg-stack.c
830 for details. */
831
832 #define STACK_REGS
833 #define IS_STACK_MODE(MODE) \
834 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
835 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
836 || (MODE) == XFmode)
837
838 /* Number of actual hardware registers.
839 The hardware registers are assigned numbers for the compiler
840 from 0 to just below FIRST_PSEUDO_REGISTER.
841 All registers that the compiler knows about must be given numbers,
842 even those that are not normally considered general registers.
843
844 In the 80386 we give the 8 general purpose registers the numbers 0-7.
845 We number the floating point registers 8-15.
846 Note that registers 0-7 can be accessed as a short or int,
847 while only 0-3 may be used with byte `mov' instructions.
848
849 Reg 16 does not correspond to any hardware register, but instead
850 appears in the RTL as an argument pointer prior to reload, and is
851 eliminated during reloading in favor of either the stack or frame
852 pointer. */
853
854 #define FIRST_PSEUDO_REGISTER 53
855
856 /* Number of hardware registers that go into the DWARF-2 unwind info.
857 If not defined, equals FIRST_PSEUDO_REGISTER. */
858
859 #define DWARF_FRAME_REGISTERS 17
860
861 /* 1 for registers that have pervasive standard uses
862 and are not available for the register allocator.
863 On the 80386, the stack pointer is such, as is the arg pointer.
864
865 The value is zero if the register is not fixed on either 32 or
866 64 bit targets, one if the register if fixed on both 32 and 64
867 bit targets, two if it is only fixed on 32bit targets and three
868 if its only fixed on 64bit targets.
869 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
870 */
871 #define FIXED_REGISTERS \
872 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
873 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
874 /*arg,flags,fpsr,fpcr,frame*/ \
875 1, 1, 1, 1, 1, \
876 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
877 0, 0, 0, 0, 0, 0, 0, 0, \
878 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
879 0, 0, 0, 0, 0, 0, 0, 0, \
880 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
881 2, 2, 2, 2, 2, 2, 2, 2, \
882 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
883 2, 2, 2, 2, 2, 2, 2, 2}
884
885
886 /* 1 for registers not available across function calls.
887 These must include the FIXED_REGISTERS and also any
888 registers that can be used without being saved.
889 The latter must include the registers where values are returned
890 and the register where structure-value addresses are passed.
891 Aside from that, you can include as many other registers as you like.
892
893 The value is zero if the register is not call used on either 32 or
894 64 bit targets, one if the register if call used on both 32 and 64
895 bit targets, two if it is only call used on 32bit targets and three
896 if its only call used on 64bit targets.
897 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
898 */
899 #define CALL_USED_REGISTERS \
900 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
901 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
902 /*arg,flags,fpsr,fpcr,frame*/ \
903 1, 1, 1, 1, 1, \
904 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
905 1, 1, 1, 1, 1, 1, 1, 1, \
906 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
907 1, 1, 1, 1, 1, 1, 1, 1, \
908 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
909 1, 1, 1, 1, 2, 2, 2, 2, \
910 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
911 1, 1, 1, 1, 1, 1, 1, 1} \
912
913 /* Order in which to allocate registers. Each register must be
914 listed once, even those in FIXED_REGISTERS. List frame pointer
915 late and fixed registers last. Note that, in general, we prefer
916 registers listed in CALL_USED_REGISTERS, keeping the others
917 available for storage of persistent values.
918
919 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
920 so this is just empty initializer for array. */
921
922 #define REG_ALLOC_ORDER \
923 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
924 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
925 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
926 48, 49, 50, 51, 52 }
927
928 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
929 to be rearranged based on a particular function. When using sse math,
930 we want to allocate SSE before x87 registers and vice versa. */
931
932 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
933
934
935 /* Macro to conditionally modify fixed_regs/call_used_regs. */
936 #define CONDITIONAL_REGISTER_USAGE \
937 do { \
938 int i; \
939 unsigned int j; \
940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
941 { \
942 if (fixed_regs[i] > 1) \
943 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
944 if (call_used_regs[i] > 1) \
945 call_used_regs[i] = (call_used_regs[i] \
946 == (TARGET_64BIT ? 3 : 2)); \
947 } \
948 j = PIC_OFFSET_TABLE_REGNUM; \
949 if (j != INVALID_REGNUM) \
950 { \
951 fixed_regs[j] = 1; \
952 call_used_regs[j] = 1; \
953 } \
954 if (! TARGET_MMX) \
955 { \
956 int i; \
957 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
958 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
959 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
960 } \
961 if (! TARGET_SSE) \
962 { \
963 int i; \
964 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
965 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
966 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
967 } \
968 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
969 { \
970 int i; \
971 HARD_REG_SET x; \
972 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
973 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
974 if (TEST_HARD_REG_BIT (x, i)) \
975 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
976 } \
977 if (! TARGET_64BIT) \
978 { \
979 int i; \
980 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
981 reg_names[i] = ""; \
982 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
983 reg_names[i] = ""; \
984 } \
985 } while (0)
986
987 /* Return number of consecutive hard regs needed starting at reg REGNO
988 to hold something of mode MODE.
989 This is ordinarily the length in words of a value of mode MODE
990 but can be less for certain modes in special long registers.
991
992 Actually there are no two word move instructions for consecutive
993 registers. And only registers 0-3 may have mov byte instructions
994 applied to them.
995 */
996
997 #define HARD_REGNO_NREGS(REGNO, MODE) \
998 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
999 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1000 : ((MODE) == XFmode \
1001 ? (TARGET_64BIT ? 2 : 3) \
1002 : (MODE) == XCmode \
1003 ? (TARGET_64BIT ? 4 : 6) \
1004 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1005
1006 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1007 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1008 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1009 ? 0 \
1010 : ((MODE) == XFmode || (MODE) == XCmode)) \
1011 : 0)
1012
1013 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1014
1015 #define VALID_SSE2_REG_MODE(MODE) \
1016 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1017 || (MODE) == V2DImode || (MODE) == DFmode)
1018
1019 #define VALID_SSE_REG_MODE(MODE) \
1020 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1021 || (MODE) == SFmode || (MODE) == TFmode)
1022
1023 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1024 ((MODE) == V2SFmode || (MODE) == SFmode)
1025
1026 #define VALID_MMX_REG_MODE(MODE) \
1027 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1028 || (MODE) == V2SImode || (MODE) == SImode)
1029
1030 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1031 place emms and femms instructions. */
1032 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
1033
1034 #define VALID_FP_MODE_P(MODE) \
1035 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1036 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1037
1038 #define VALID_INT_MODE_P(MODE) \
1039 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1040 || (MODE) == DImode \
1041 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1042 || (MODE) == CDImode \
1043 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1044 || (MODE) == TFmode || (MODE) == TCmode)))
1045
1046 /* Return true for modes passed in SSE registers. */
1047 #define SSE_REG_MODE_P(MODE) \
1048 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1049 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1050 || (MODE) == V4SFmode || (MODE) == V4SImode)
1051
1052 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1053
1054 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1055 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1056
1057 /* Value is 1 if it is a good idea to tie two pseudo registers
1058 when one has mode MODE1 and one has mode MODE2.
1059 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1060 for any hard reg, then this must be 0 for correct output. */
1061
1062 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1063
1064 /* It is possible to write patterns to move flags; but until someone
1065 does it, */
1066 #define AVOID_CCMODE_COPIES
1067
1068 /* Specify the modes required to caller save a given hard regno.
1069 We do this on i386 to prevent flags from being saved at all.
1070
1071 Kill any attempts to combine saving of modes. */
1072
1073 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1074 (CC_REGNO_P (REGNO) ? VOIDmode \
1075 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1076 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1077 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1078 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1079 : (MODE))
1080 /* Specify the registers used for certain standard purposes.
1081 The values of these macros are register numbers. */
1082
1083 /* on the 386 the pc register is %eip, and is not usable as a general
1084 register. The ordinary mov instructions won't work */
1085 /* #define PC_REGNUM */
1086
1087 /* Register to use for pushing function arguments. */
1088 #define STACK_POINTER_REGNUM 7
1089
1090 /* Base register for access to local variables of the function. */
1091 #define HARD_FRAME_POINTER_REGNUM 6
1092
1093 /* Base register for access to local variables of the function. */
1094 #define FRAME_POINTER_REGNUM 20
1095
1096 /* First floating point reg */
1097 #define FIRST_FLOAT_REG 8
1098
1099 /* First & last stack-like regs */
1100 #define FIRST_STACK_REG FIRST_FLOAT_REG
1101 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1102
1103 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1104 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1105
1106 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1107 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1108
1109 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1110 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1111
1112 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1113 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1114
1115 /* Value should be nonzero if functions must have frame pointers.
1116 Zero means the frame pointer need not be set up (and parms
1117 may be accessed via the stack pointer) in functions that seem suitable.
1118 This is computed in `reload', in reload1.c. */
1119 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1120
1121 /* Override this in other tm.h files to cope with various OS lossage
1122 requiring a frame pointer. */
1123 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1124 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1125 #endif
1126
1127 /* Make sure we can access arbitrary call frames. */
1128 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1129
1130 /* Base register for access to arguments of the function. */
1131 #define ARG_POINTER_REGNUM 16
1132
1133 /* Register in which static-chain is passed to a function.
1134 We do use ECX as static chain register for 32 bit ABI. On the
1135 64bit ABI, ECX is an argument register, so we use R10 instead. */
1136 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1137
1138 /* Register to hold the addressing base for position independent
1139 code access to data items. We don't use PIC pointer for 64bit
1140 mode. Define the regnum to dummy value to prevent gcc from
1141 pessimizing code dealing with EBX.
1142
1143 To avoid clobbering a call-saved register unnecessarily, we renumber
1144 the pic register when possible. The change is visible after the
1145 prologue has been emitted. */
1146
1147 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1148
1149 #define PIC_OFFSET_TABLE_REGNUM \
1150 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1151 || !flag_pic ? INVALID_REGNUM \
1152 : reload_completed ? REGNO (pic_offset_table_rtx) \
1153 : REAL_PIC_OFFSET_TABLE_REGNUM)
1154
1155 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1156
1157 /* A C expression which can inhibit the returning of certain function
1158 values in registers, based on the type of value. A nonzero value
1159 says to return the function value in memory, just as large
1160 structures are always returned. Here TYPE will be a C expression
1161 of type `tree', representing the data type of the value.
1162
1163 Note that values of mode `BLKmode' must be explicitly handled by
1164 this macro. Also, the option `-fpcc-struct-return' takes effect
1165 regardless of this macro. On most systems, it is possible to
1166 leave the macro undefined; this causes a default definition to be
1167 used, whose value is the constant 1 for `BLKmode' values, and 0
1168 otherwise.
1169
1170 Do not use this macro to indicate that structures and unions
1171 should always be returned in memory. You should instead use
1172 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1173
1174 #define RETURN_IN_MEMORY(TYPE) \
1175 ix86_return_in_memory (TYPE)
1176
1177 /* This is overridden by <cygwin.h>. */
1178 #define MS_AGGREGATE_RETURN 0
1179
1180 /* This is overridden by <netware.h>. */
1181 #define KEEP_AGGREGATE_RETURN_POINTER 0
1182 \f
1183 /* Define the classes of registers for register constraints in the
1184 machine description. Also define ranges of constants.
1185
1186 One of the classes must always be named ALL_REGS and include all hard regs.
1187 If there is more than one class, another class must be named NO_REGS
1188 and contain no registers.
1189
1190 The name GENERAL_REGS must be the name of a class (or an alias for
1191 another name such as ALL_REGS). This is the class of registers
1192 that is allowed by "g" or "r" in a register constraint.
1193 Also, registers outside this class are allocated only when
1194 instructions express preferences for them.
1195
1196 The classes must be numbered in nondecreasing order; that is,
1197 a larger-numbered class must never be contained completely
1198 in a smaller-numbered class.
1199
1200 For any two classes, it is very desirable that there be another
1201 class that represents their union.
1202
1203 It might seem that class BREG is unnecessary, since no useful 386
1204 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1205 and the "b" register constraint is useful in asms for syscalls.
1206
1207 The flags, fpsr and fpcr registers are in no class. */
1208
1209 enum reg_class
1210 {
1211 NO_REGS,
1212 AREG, DREG, CREG, BREG, SIREG, DIREG,
1213 AD_REGS, /* %eax/%edx for DImode */
1214 Q_REGS, /* %eax %ebx %ecx %edx */
1215 NON_Q_REGS, /* %esi %edi %ebp %esp */
1216 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1217 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1218 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1219 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1220 FLOAT_REGS,
1221 SSE_REGS,
1222 MMX_REGS,
1223 FP_TOP_SSE_REGS,
1224 FP_SECOND_SSE_REGS,
1225 FLOAT_SSE_REGS,
1226 FLOAT_INT_REGS,
1227 INT_SSE_REGS,
1228 FLOAT_INT_SSE_REGS,
1229 ALL_REGS, LIM_REG_CLASSES
1230 };
1231
1232 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1233
1234 #define INTEGER_CLASS_P(CLASS) \
1235 reg_class_subset_p ((CLASS), GENERAL_REGS)
1236 #define FLOAT_CLASS_P(CLASS) \
1237 reg_class_subset_p ((CLASS), FLOAT_REGS)
1238 #define SSE_CLASS_P(CLASS) \
1239 ((CLASS) == SSE_REGS)
1240 #define MMX_CLASS_P(CLASS) \
1241 ((CLASS) == MMX_REGS)
1242 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1243 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1244 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1245 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1246 #define MAYBE_SSE_CLASS_P(CLASS) \
1247 reg_classes_intersect_p (SSE_REGS, (CLASS))
1248 #define MAYBE_MMX_CLASS_P(CLASS) \
1249 reg_classes_intersect_p (MMX_REGS, (CLASS))
1250
1251 #define Q_CLASS_P(CLASS) \
1252 reg_class_subset_p ((CLASS), Q_REGS)
1253
1254 /* Give names of register classes as strings for dump file. */
1255
1256 #define REG_CLASS_NAMES \
1257 { "NO_REGS", \
1258 "AREG", "DREG", "CREG", "BREG", \
1259 "SIREG", "DIREG", \
1260 "AD_REGS", \
1261 "Q_REGS", "NON_Q_REGS", \
1262 "INDEX_REGS", \
1263 "LEGACY_REGS", \
1264 "GENERAL_REGS", \
1265 "FP_TOP_REG", "FP_SECOND_REG", \
1266 "FLOAT_REGS", \
1267 "SSE_REGS", \
1268 "MMX_REGS", \
1269 "FP_TOP_SSE_REGS", \
1270 "FP_SECOND_SSE_REGS", \
1271 "FLOAT_SSE_REGS", \
1272 "FLOAT_INT_REGS", \
1273 "INT_SSE_REGS", \
1274 "FLOAT_INT_SSE_REGS", \
1275 "ALL_REGS" }
1276
1277 /* Define which registers fit in which classes.
1278 This is an initializer for a vector of HARD_REG_SET
1279 of length N_REG_CLASSES. */
1280
1281 #define REG_CLASS_CONTENTS \
1282 { { 0x00, 0x0 }, \
1283 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1284 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1285 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1286 { 0x03, 0x0 }, /* AD_REGS */ \
1287 { 0x0f, 0x0 }, /* Q_REGS */ \
1288 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1289 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1290 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1291 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1292 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1293 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1294 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1295 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1296 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1297 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1298 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1299 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1300 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1301 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1302 { 0xffffffff,0x1fffff } \
1303 }
1304
1305 /* The same information, inverted:
1306 Return the class number of the smallest class containing
1307 reg number REGNO. This could be a conditional expression
1308 or could index an array. */
1309
1310 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1311
1312 /* When defined, the compiler allows registers explicitly used in the
1313 rtl to be used as spill registers but prevents the compiler from
1314 extending the lifetime of these registers. */
1315
1316 #define SMALL_REGISTER_CLASSES 1
1317
1318 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1319
1320 #define GENERAL_REGNO_P(N) \
1321 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1322
1323 #define GENERAL_REG_P(X) \
1324 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1325
1326 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1327
1328 #define REX_INT_REGNO_P(N) \
1329 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1330 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1331
1332 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1333 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1334 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1335 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1336
1337 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1338 #define SSE_REGNO_P(N) \
1339 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1340 || REX_SSE_REGNO_P (N))
1341
1342 #define REX_SSE_REGNO_P(N) \
1343 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1344
1345 #define SSE_REGNO(N) \
1346 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1347
1348 #define SSE_FLOAT_MODE_P(MODE) \
1349 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1350
1351 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1352 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1353
1354 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1355 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1356
1357 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1358
1359 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1360 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1361
1362 /* The class value for index registers, and the one for base regs. */
1363
1364 #define INDEX_REG_CLASS INDEX_REGS
1365 #define BASE_REG_CLASS GENERAL_REGS
1366
1367 /* Place additional restrictions on the register class to use when it
1368 is necessary to be able to hold a value of mode MODE in a reload
1369 register for which class CLASS would ordinarily be used. */
1370
1371 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1372 ((MODE) == QImode && !TARGET_64BIT \
1373 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1374 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1375 ? Q_REGS : (CLASS))
1376
1377 /* Given an rtx X being reloaded into a reg required to be
1378 in class CLASS, return the class of reg to actually use.
1379 In general this is just CLASS; but on some machines
1380 in some cases it is preferable to use a more restrictive class.
1381 On the 80386 series, we prevent floating constants from being
1382 reloaded into floating registers (since no move-insn can do that)
1383 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1384
1385 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1386 QImode must go into class Q_REGS.
1387 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1388 movdf to do mem-to-mem moves through integer regs. */
1389
1390 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1391 ix86_preferred_reload_class ((X), (CLASS))
1392
1393 /* Discourage putting floating-point values in SSE registers unless
1394 SSE math is being used, and likewise for the 387 registers. */
1395
1396 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1397 ix86_preferred_output_reload_class ((X), (CLASS))
1398
1399 /* If we are copying between general and FP registers, we need a memory
1400 location. The same is true for SSE and MMX registers. */
1401 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1402 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1403
1404 /* QImode spills from non-QI registers need a scratch. This does not
1405 happen often -- the only example so far requires an uninitialized
1406 pseudo. */
1407
1408 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1409 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1410 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1411 ? Q_REGS : NO_REGS)
1412
1413 /* Return the maximum number of consecutive registers
1414 needed to represent mode MODE in a register of class CLASS. */
1415 /* On the 80386, this is the size of MODE in words,
1416 except in the FP regs, where a single reg is always enough. */
1417 #define CLASS_MAX_NREGS(CLASS, MODE) \
1418 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1419 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1420 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1421 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1422
1423 /* A C expression whose value is nonzero if pseudos that have been
1424 assigned to registers of class CLASS would likely be spilled
1425 because registers of CLASS are needed for spill registers.
1426
1427 The default value of this macro returns 1 if CLASS has exactly one
1428 register and zero otherwise. On most machines, this default
1429 should be used. Only define this macro to some other expression
1430 if pseudo allocated by `local-alloc.c' end up in memory because
1431 their hard registers were needed for spill registers. If this
1432 macro returns nonzero for those classes, those pseudos will only
1433 be allocated by `global.c', which knows how to reallocate the
1434 pseudo to another register. If there would not be another
1435 register available for reallocation, you should not change the
1436 definition of this macro since the only effect of such a
1437 definition would be to slow down register allocation. */
1438
1439 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1440 (((CLASS) == AREG) \
1441 || ((CLASS) == DREG) \
1442 || ((CLASS) == CREG) \
1443 || ((CLASS) == BREG) \
1444 || ((CLASS) == AD_REGS) \
1445 || ((CLASS) == SIREG) \
1446 || ((CLASS) == DIREG) \
1447 || ((CLASS) == FP_TOP_REG) \
1448 || ((CLASS) == FP_SECOND_REG))
1449
1450 /* Return a class of registers that cannot change FROM mode to TO mode. */
1451
1452 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1453 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1454 \f
1455 /* Stack layout; function entry, exit and calling. */
1456
1457 /* Define this if pushing a word on the stack
1458 makes the stack pointer a smaller address. */
1459 #define STACK_GROWS_DOWNWARD
1460
1461 /* Define this to nonzero if the nominal address of the stack frame
1462 is at the high-address end of the local variables;
1463 that is, each additional local variable allocated
1464 goes at a more negative offset in the frame. */
1465 #define FRAME_GROWS_DOWNWARD 1
1466
1467 /* Offset within stack frame to start allocating local variables at.
1468 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1469 first local allocated. Otherwise, it is the offset to the BEGINNING
1470 of the first local allocated. */
1471 #define STARTING_FRAME_OFFSET 0
1472
1473 /* If we generate an insn to push BYTES bytes,
1474 this says how many the stack pointer really advances by.
1475 On 386, we have pushw instruction that decrements by exactly 2 no
1476 matter what the position was, there is no pushb.
1477 But as CIE data alignment factor on this arch is -4, we need to make
1478 sure all stack pointer adjustments are in multiple of 4.
1479
1480 For 64bit ABI we round up to 8 bytes.
1481 */
1482
1483 #define PUSH_ROUNDING(BYTES) \
1484 (TARGET_64BIT \
1485 ? (((BYTES) + 7) & (-8)) \
1486 : (((BYTES) + 3) & (-4)))
1487
1488 /* If defined, the maximum amount of space required for outgoing arguments will
1489 be computed and placed into the variable
1490 `current_function_outgoing_args_size'. No space will be pushed onto the
1491 stack for each call; instead, the function prologue should increase the stack
1492 frame size by this amount. */
1493
1494 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1495
1496 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1497 instructions to pass outgoing arguments. */
1498
1499 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1500
1501 /* We want the stack and args grow in opposite directions, even if
1502 PUSH_ARGS is 0. */
1503 #define PUSH_ARGS_REVERSED 1
1504
1505 /* Offset of first parameter from the argument pointer register value. */
1506 #define FIRST_PARM_OFFSET(FNDECL) 0
1507
1508 /* Define this macro if functions should assume that stack space has been
1509 allocated for arguments even when their values are passed in registers.
1510
1511 The value of this macro is the size, in bytes, of the area reserved for
1512 arguments passed in registers for the function represented by FNDECL.
1513
1514 This space can be allocated by the caller, or be a part of the
1515 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1516 which. */
1517 #define REG_PARM_STACK_SPACE(FNDECL) 0
1518
1519 /* Value is the number of bytes of arguments automatically
1520 popped when returning from a subroutine call.
1521 FUNDECL is the declaration node of the function (as a tree),
1522 FUNTYPE is the data type of the function (as a tree),
1523 or for a library call it is an identifier node for the subroutine name.
1524 SIZE is the number of bytes of arguments passed on the stack.
1525
1526 On the 80386, the RTD insn may be used to pop them if the number
1527 of args is fixed, but if the number is variable then the caller
1528 must pop them all. RTD can't be used for library calls now
1529 because the library is compiled with the Unix compiler.
1530 Use of RTD is a selectable option, since it is incompatible with
1531 standard Unix calling sequences. If the option is not selected,
1532 the caller must always pop the args.
1533
1534 The attribute stdcall is equivalent to RTD on a per module basis. */
1535
1536 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1537 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1538
1539 #define FUNCTION_VALUE_REGNO_P(N) \
1540 ix86_function_value_regno_p (N)
1541
1542 /* Define how to find the value returned by a library function
1543 assuming the value has mode MODE. */
1544
1545 #define LIBCALL_VALUE(MODE) \
1546 ix86_libcall_value (MODE)
1547
1548 /* Define the size of the result block used for communication between
1549 untyped_call and untyped_return. The block contains a DImode value
1550 followed by the block used by fnsave and frstor. */
1551
1552 #define APPLY_RESULT_SIZE (8+108)
1553
1554 /* 1 if N is a possible register number for function argument passing. */
1555 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1556
1557 /* Define a data type for recording info about an argument list
1558 during the scan of that argument list. This data type should
1559 hold all necessary information about the function itself
1560 and about the args processed so far, enough to enable macros
1561 such as FUNCTION_ARG to determine where the next arg should go. */
1562
1563 typedef struct ix86_args {
1564 int words; /* # words passed so far */
1565 int nregs; /* # registers available for passing */
1566 int regno; /* next available register number */
1567 int fastcall; /* fastcall calling convention is used */
1568 int sse_words; /* # sse words passed so far */
1569 int sse_nregs; /* # sse registers available for passing */
1570 int warn_sse; /* True when we want to warn about SSE ABI. */
1571 int warn_mmx; /* True when we want to warn about MMX ABI. */
1572 int sse_regno; /* next available sse register number */
1573 int mmx_words; /* # mmx words passed so far */
1574 int mmx_nregs; /* # mmx registers available for passing */
1575 int mmx_regno; /* next available mmx register number */
1576 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1577 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1578 be passed in SSE registers. Otherwise 0. */
1579 } CUMULATIVE_ARGS;
1580
1581 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1582 for a call to a function whose data type is FNTYPE.
1583 For a library call, FNTYPE is 0. */
1584
1585 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1586 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1587
1588 /* Update the data in CUM to advance over an argument
1589 of mode MODE and data type TYPE.
1590 (TYPE is null for libcalls where that information may not be available.) */
1591
1592 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1593 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1594
1595 /* Define where to put the arguments to a function.
1596 Value is zero to push the argument on the stack,
1597 or a hard register in which to store the argument.
1598
1599 MODE is the argument's machine mode.
1600 TYPE is the data type of the argument (as a tree).
1601 This is null for libcalls where that information may
1602 not be available.
1603 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1604 the preceding args and about the function being called.
1605 NAMED is nonzero if this argument is a named parameter
1606 (otherwise it is an extra parameter matching an ellipsis). */
1607
1608 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1609 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1610
1611 /* Implement `va_start' for varargs and stdarg. */
1612 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1613 ix86_va_start (VALIST, NEXTARG)
1614
1615 #define TARGET_ASM_FILE_END ix86_file_end
1616 #define NEED_INDICATE_EXEC_STACK 0
1617
1618 /* Output assembler code to FILE to increment profiler label # LABELNO
1619 for profiling a function entry. */
1620
1621 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1622
1623 #define MCOUNT_NAME "_mcount"
1624
1625 #define PROFILE_COUNT_REGISTER "edx"
1626
1627 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1628 the stack pointer does not matter. The value is tested only in
1629 functions that have frame pointers.
1630 No definition is equivalent to always zero. */
1631 /* Note on the 386 it might be more efficient not to define this since
1632 we have to restore it ourselves from the frame pointer, in order to
1633 use pop */
1634
1635 #define EXIT_IGNORE_STACK 1
1636
1637 /* Output assembler code for a block containing the constant parts
1638 of a trampoline, leaving space for the variable parts. */
1639
1640 /* On the 386, the trampoline contains two instructions:
1641 mov #STATIC,ecx
1642 jmp FUNCTION
1643 The trampoline is generated entirely at runtime. The operand of JMP
1644 is the address of FUNCTION relative to the instruction following the
1645 JMP (which is 5 bytes long). */
1646
1647 /* Length in units of the trampoline for entering a nested function. */
1648
1649 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1650
1651 /* Emit RTL insns to initialize the variable parts of a trampoline.
1652 FNADDR is an RTX for the address of the function's pure code.
1653 CXT is an RTX for the static chain value for the function. */
1654
1655 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1656 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1657 \f
1658 /* Definitions for register eliminations.
1659
1660 This is an array of structures. Each structure initializes one pair
1661 of eliminable registers. The "from" register number is given first,
1662 followed by "to". Eliminations of the same "from" register are listed
1663 in order of preference.
1664
1665 There are two registers that can always be eliminated on the i386.
1666 The frame pointer and the arg pointer can be replaced by either the
1667 hard frame pointer or to the stack pointer, depending upon the
1668 circumstances. The hard frame pointer is not used before reload and
1669 so it is not eligible for elimination. */
1670
1671 #define ELIMINABLE_REGS \
1672 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1673 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1674 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1675 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1676
1677 /* Given FROM and TO register numbers, say whether this elimination is
1678 allowed. Frame pointer elimination is automatically handled.
1679
1680 All other eliminations are valid. */
1681
1682 #define CAN_ELIMINATE(FROM, TO) \
1683 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1684
1685 /* Define the offset between two registers, one to be eliminated, and the other
1686 its replacement, at the start of a routine. */
1687
1688 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1689 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1690 \f
1691 /* Addressing modes, and classification of registers for them. */
1692
1693 /* Macros to check register numbers against specific register classes. */
1694
1695 /* These assume that REGNO is a hard or pseudo reg number.
1696 They give nonzero only if REGNO is a hard reg of the suitable class
1697 or a pseudo reg currently allocated to a suitable hard reg.
1698 Since they use reg_renumber, they are safe only once reg_renumber
1699 has been allocated, which happens in local-alloc.c. */
1700
1701 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1702 ((REGNO) < STACK_POINTER_REGNUM \
1703 || REX_INT_REGNO_P (REGNO) \
1704 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1705 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1706
1707 #define REGNO_OK_FOR_BASE_P(REGNO) \
1708 (GENERAL_REGNO_P (REGNO) \
1709 || (REGNO) == ARG_POINTER_REGNUM \
1710 || (REGNO) == FRAME_POINTER_REGNUM \
1711 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1712
1713 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1714 and check its validity for a certain class.
1715 We have two alternate definitions for each of them.
1716 The usual definition accepts all pseudo regs; the other rejects
1717 them unless they have been allocated suitable hard regs.
1718 The symbol REG_OK_STRICT causes the latter definition to be used.
1719
1720 Most source files want to accept pseudo regs in the hope that
1721 they will get allocated to the class that the insn wants them to be in.
1722 Source files for reload pass need to be strict.
1723 After reload, it makes no difference, since pseudo regs have
1724 been eliminated by then. */
1725
1726
1727 /* Non strict versions, pseudos are ok. */
1728 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1729 (REGNO (X) < STACK_POINTER_REGNUM \
1730 || REX_INT_REGNO_P (REGNO (X)) \
1731 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1732
1733 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1734 (GENERAL_REGNO_P (REGNO (X)) \
1735 || REGNO (X) == ARG_POINTER_REGNUM \
1736 || REGNO (X) == FRAME_POINTER_REGNUM \
1737 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1738
1739 /* Strict versions, hard registers only */
1740 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1741 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1742
1743 #ifndef REG_OK_STRICT
1744 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1745 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1746
1747 #else
1748 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1749 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1750 #endif
1751
1752 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1753 that is a valid memory address for an instruction.
1754 The MODE argument is the machine mode for the MEM expression
1755 that wants to use this address.
1756
1757 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1758 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1759
1760 See legitimize_pic_address in i386.c for details as to what
1761 constitutes a legitimate address when -fpic is used. */
1762
1763 #define MAX_REGS_PER_ADDRESS 2
1764
1765 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1766
1767 /* Nonzero if the constant value X is a legitimate general operand.
1768 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1769
1770 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1771
1772 #ifdef REG_OK_STRICT
1773 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1774 do { \
1775 if (legitimate_address_p ((MODE), (X), 1)) \
1776 goto ADDR; \
1777 } while (0)
1778
1779 #else
1780 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1781 do { \
1782 if (legitimate_address_p ((MODE), (X), 0)) \
1783 goto ADDR; \
1784 } while (0)
1785
1786 #endif
1787
1788 /* If defined, a C expression to determine the base term of address X.
1789 This macro is used in only one place: `find_base_term' in alias.c.
1790
1791 It is always safe for this macro to not be defined. It exists so
1792 that alias analysis can understand machine-dependent addresses.
1793
1794 The typical use of this macro is to handle addresses containing
1795 a label_ref or symbol_ref within an UNSPEC. */
1796
1797 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1798
1799 /* Try machine-dependent ways of modifying an illegitimate address
1800 to be legitimate. If we find one, return the new, valid address.
1801 This macro is used in only one place: `memory_address' in explow.c.
1802
1803 OLDX is the address as it was before break_out_memory_refs was called.
1804 In some cases it is useful to look at this to decide what needs to be done.
1805
1806 MODE and WIN are passed so that this macro can use
1807 GO_IF_LEGITIMATE_ADDRESS.
1808
1809 It is always safe for this macro to do nothing. It exists to recognize
1810 opportunities to optimize the output.
1811
1812 For the 80386, we handle X+REG by loading X into a register R and
1813 using R+REG. R will go in a general reg and indexing will be used.
1814 However, if REG is a broken-out memory address or multiplication,
1815 nothing needs to be done because REG can certainly go in a general reg.
1816
1817 When -fpic is used, special handling is needed for symbolic references.
1818 See comments by legitimize_pic_address in i386.c for details. */
1819
1820 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1821 do { \
1822 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1823 if (memory_address_p ((MODE), (X))) \
1824 goto WIN; \
1825 } while (0)
1826
1827 /* Nonzero if the constant value X is a legitimate general operand
1828 when generating PIC code. It is given that flag_pic is on and
1829 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1830
1831 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1832
1833 #define SYMBOLIC_CONST(X) \
1834 (GET_CODE (X) == SYMBOL_REF \
1835 || GET_CODE (X) == LABEL_REF \
1836 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1837
1838 /* Go to LABEL if ADDR (a legitimate address expression)
1839 has an effect that depends on the machine mode it is used for.
1840 On the 80386, only postdecrement and postincrement address depend thus
1841 (the amount of decrement or increment being the length of the operand).
1842 These are now caught in recog.c. */
1843 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1844 \f
1845 /* Max number of args passed in registers. If this is more than 3, we will
1846 have problems with ebx (register #4), since it is a caller save register and
1847 is also used as the pic register in ELF. So for now, don't allow more than
1848 3 registers to be passed in registers. */
1849
1850 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1851
1852 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1853
1854 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1855
1856 \f
1857 /* Specify the machine mode that this machine uses
1858 for the index in the tablejump instruction. */
1859 #define CASE_VECTOR_MODE \
1860 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1861
1862 /* Define this as 1 if `char' should by default be signed; else as 0. */
1863 #define DEFAULT_SIGNED_CHAR 1
1864
1865 /* Max number of bytes we can move from memory to memory
1866 in one reasonably fast instruction. */
1867 #define MOVE_MAX 16
1868
1869 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1870 move efficiently, as opposed to MOVE_MAX which is the maximum
1871 number of bytes we can move with a single instruction. */
1872 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1873
1874 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1875 move-instruction pairs, we will do a movmem or libcall instead.
1876 Increasing the value will always make code faster, but eventually
1877 incurs high cost in increased code size.
1878
1879 If you don't define this, a reasonable default is used. */
1880
1881 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1882
1883 /* If a clear memory operation would take CLEAR_RATIO or more simple
1884 move-instruction sequences, we will do a clrmem or libcall instead. */
1885
1886 #define CLEAR_RATIO (optimize_size ? 2 \
1887 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1888
1889 /* Define if shifts truncate the shift count
1890 which implies one can omit a sign-extension or zero-extension
1891 of a shift count. */
1892 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1893
1894 /* #define SHIFT_COUNT_TRUNCATED */
1895
1896 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1897 is done just by pretending it is already truncated. */
1898 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1899
1900 /* A macro to update M and UNSIGNEDP when an object whose type is
1901 TYPE and which has the specified mode and signedness is to be
1902 stored in a register. This macro is only called when TYPE is a
1903 scalar type.
1904
1905 On i386 it is sometimes useful to promote HImode and QImode
1906 quantities to SImode. The choice depends on target type. */
1907
1908 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1909 do { \
1910 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1911 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1912 (MODE) = SImode; \
1913 } while (0)
1914
1915 /* Specify the machine mode that pointers have.
1916 After generation of rtl, the compiler makes no further distinction
1917 between pointers and any other objects of this machine mode. */
1918 #define Pmode (TARGET_64BIT ? DImode : SImode)
1919
1920 /* A function address in a call instruction
1921 is a byte address (for indexing purposes)
1922 so give the MEM rtx a byte's mode. */
1923 #define FUNCTION_MODE QImode
1924 \f
1925 /* A C expression for the cost of moving data from a register in class FROM to
1926 one in class TO. The classes are expressed using the enumeration values
1927 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1928 interpreted relative to that.
1929
1930 It is not required that the cost always equal 2 when FROM is the same as TO;
1931 on some machines it is expensive to move between registers if they are not
1932 general registers. */
1933
1934 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1935 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1936
1937 /* A C expression for the cost of moving data of mode M between a
1938 register and memory. A value of 2 is the default; this cost is
1939 relative to those in `REGISTER_MOVE_COST'.
1940
1941 If moving between registers and memory is more expensive than
1942 between two registers, you should define this macro to express the
1943 relative cost. */
1944
1945 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1946 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1947
1948 /* A C expression for the cost of a branch instruction. A value of 1
1949 is the default; other values are interpreted relative to that. */
1950
1951 #define BRANCH_COST ix86_branch_cost
1952
1953 /* Define this macro as a C expression which is nonzero if accessing
1954 less than a word of memory (i.e. a `char' or a `short') is no
1955 faster than accessing a word of memory, i.e., if such access
1956 require more than one instruction or if there is no difference in
1957 cost between byte and (aligned) word loads.
1958
1959 When this macro is not defined, the compiler will access a field by
1960 finding the smallest containing object; when it is defined, a
1961 fullword load will be used if alignment permits. Unless bytes
1962 accesses are faster than word accesses, using word accesses is
1963 preferable since it may eliminate subsequent memory access if
1964 subsequent accesses occur to other fields in the same word of the
1965 structure, but to different bytes. */
1966
1967 #define SLOW_BYTE_ACCESS 0
1968
1969 /* Nonzero if access to memory by shorts is slow and undesirable. */
1970 #define SLOW_SHORT_ACCESS 0
1971
1972 /* Define this macro to be the value 1 if unaligned accesses have a
1973 cost many times greater than aligned accesses, for example if they
1974 are emulated in a trap handler.
1975
1976 When this macro is nonzero, the compiler will act as if
1977 `STRICT_ALIGNMENT' were nonzero when generating code for block
1978 moves. This can cause significantly more instructions to be
1979 produced. Therefore, do not set this macro nonzero if unaligned
1980 accesses only add a cycle or two to the time for a memory access.
1981
1982 If the value of this macro is always zero, it need not be defined. */
1983
1984 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1985
1986 /* Define this macro if it is as good or better to call a constant
1987 function address than to call an address kept in a register.
1988
1989 Desirable on the 386 because a CALL with a constant address is
1990 faster than one with a register address. */
1991
1992 #define NO_FUNCTION_CSE
1993 \f
1994 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1995 return the mode to be used for the comparison.
1996
1997 For floating-point equality comparisons, CCFPEQmode should be used.
1998 VOIDmode should be used in all other cases.
1999
2000 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2001 possible, to allow for more combinations. */
2002
2003 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2004
2005 /* Return nonzero if MODE implies a floating point inequality can be
2006 reversed. */
2007
2008 #define REVERSIBLE_CC_MODE(MODE) 1
2009
2010 /* A C expression whose value is reversed condition code of the CODE for
2011 comparison done in CC_MODE mode. */
2012 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2013
2014 \f
2015 /* Control the assembler format that we output, to the extent
2016 this does not vary between assemblers. */
2017
2018 /* How to refer to registers in assembler output.
2019 This sequence is indexed by compiler's hard-register-number (see above). */
2020
2021 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2022 For non floating point regs, the following are the HImode names.
2023
2024 For float regs, the stack top is sometimes referred to as "%st(0)"
2025 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2026
2027 #define HI_REGISTER_NAMES \
2028 {"ax","dx","cx","bx","si","di","bp","sp", \
2029 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2030 "argp", "flags", "fpsr", "fpcr", "frame", \
2031 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2032 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2033 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2034 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2035
2036 #define REGISTER_NAMES HI_REGISTER_NAMES
2037
2038 /* Table of additional register names to use in user input. */
2039
2040 #define ADDITIONAL_REGISTER_NAMES \
2041 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2042 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2043 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2044 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2045 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2046 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2047
2048 /* Note we are omitting these since currently I don't know how
2049 to get gcc to use these, since they want the same but different
2050 number as al, and ax.
2051 */
2052
2053 #define QI_REGISTER_NAMES \
2054 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2055
2056 /* These parallel the array above, and can be used to access bits 8:15
2057 of regs 0 through 3. */
2058
2059 #define QI_HIGH_REGISTER_NAMES \
2060 {"ah", "dh", "ch", "bh", }
2061
2062 /* How to renumber registers for dbx and gdb. */
2063
2064 #define DBX_REGISTER_NUMBER(N) \
2065 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2066
2067 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2068 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2069 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2070
2071 /* Before the prologue, RA is at 0(%esp). */
2072 #define INCOMING_RETURN_ADDR_RTX \
2073 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2074
2075 /* After the prologue, RA is at -4(AP) in the current frame. */
2076 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2077 ((COUNT) == 0 \
2078 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2079 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2080
2081 /* PC is dbx register 8; let's use that column for RA. */
2082 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2083
2084 /* Before the prologue, the top of the frame is at 4(%esp). */
2085 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2086
2087 /* Describe how we implement __builtin_eh_return. */
2088 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2089 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2090
2091
2092 /* Select a format to encode pointers in exception handling data. CODE
2093 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2094 true if the symbol may be affected by dynamic relocations.
2095
2096 ??? All x86 object file formats are capable of representing this.
2097 After all, the relocation needed is the same as for the call insn.
2098 Whether or not a particular assembler allows us to enter such, I
2099 guess we'll have to see. */
2100 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2101 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2102
2103 /* This is how to output an insn to push a register on the stack.
2104 It need not be very fast code. */
2105
2106 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2107 do { \
2108 if (TARGET_64BIT) \
2109 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2110 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2111 else \
2112 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2113 } while (0)
2114
2115 /* This is how to output an insn to pop a register from the stack.
2116 It need not be very fast code. */
2117
2118 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2119 do { \
2120 if (TARGET_64BIT) \
2121 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2122 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2123 else \
2124 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2125 } while (0)
2126
2127 /* This is how to output an element of a case-vector that is absolute. */
2128
2129 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2130 ix86_output_addr_vec_elt ((FILE), (VALUE))
2131
2132 /* This is how to output an element of a case-vector that is relative. */
2133
2134 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2135 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2136
2137 /* Under some conditions we need jump tables in the text section,
2138 because the assembler cannot handle label differences between
2139 sections. This is the case for x86_64 on Mach-O for example. */
2140
2141 #define JUMP_TABLES_IN_TEXT_SECTION \
2142 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2143 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2144
2145 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2146 and switch back. For x86 we do this only to save a few bytes that
2147 would otherwise be unused in the text section. */
2148 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2149 asm (SECTION_OP "\n\t" \
2150 "call " USER_LABEL_PREFIX #FUNC "\n" \
2151 TEXT_SECTION_ASM_OP);
2152 \f
2153 /* Print operand X (an rtx) in assembler syntax to file FILE.
2154 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2155 Effect of various CODE letters is described in i386.c near
2156 print_operand function. */
2157
2158 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2159 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2160
2161 #define PRINT_OPERAND(FILE, X, CODE) \
2162 print_operand ((FILE), (X), (CODE))
2163
2164 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2165 print_operand_address ((FILE), (ADDR))
2166
2167 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2168 do { \
2169 if (! output_addr_const_extra (FILE, (X))) \
2170 goto FAIL; \
2171 } while (0);
2172 \f
2173 /* Which processor to schedule for. The cpu attribute defines a list that
2174 mirrors this list, so changes to i386.md must be made at the same time. */
2175
2176 enum processor_type
2177 {
2178 PROCESSOR_I386, /* 80386 */
2179 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2180 PROCESSOR_PENTIUM,
2181 PROCESSOR_PENTIUMPRO,
2182 PROCESSOR_GEODE,
2183 PROCESSOR_K6,
2184 PROCESSOR_ATHLON,
2185 PROCESSOR_PENTIUM4,
2186 PROCESSOR_K8,
2187 PROCESSOR_NOCONA,
2188 PROCESSOR_CORE2,
2189 PROCESSOR_GENERIC32,
2190 PROCESSOR_GENERIC64,
2191 PROCESSOR_AMDFAM10,
2192 PROCESSOR_max
2193 };
2194
2195 extern enum processor_type ix86_tune;
2196 extern enum processor_type ix86_arch;
2197
2198 enum fpmath_unit
2199 {
2200 FPMATH_387 = 1,
2201 FPMATH_SSE = 2
2202 };
2203
2204 extern enum fpmath_unit ix86_fpmath;
2205
2206 enum tls_dialect
2207 {
2208 TLS_DIALECT_GNU,
2209 TLS_DIALECT_GNU2,
2210 TLS_DIALECT_SUN
2211 };
2212
2213 extern enum tls_dialect ix86_tls_dialect;
2214
2215 enum cmodel {
2216 CM_32, /* The traditional 32-bit ABI. */
2217 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2218 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2219 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2220 CM_LARGE, /* No assumptions. */
2221 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2222 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2223 CM_LARGE_PIC /* No assumptions. */
2224 };
2225
2226 extern enum cmodel ix86_cmodel;
2227
2228 /* Size of the RED_ZONE area. */
2229 #define RED_ZONE_SIZE 128
2230 /* Reserved area of the red zone for temporaries. */
2231 #define RED_ZONE_RESERVE 8
2232
2233 enum asm_dialect {
2234 ASM_ATT,
2235 ASM_INTEL
2236 };
2237
2238 extern enum asm_dialect ix86_asm_dialect;
2239 extern unsigned int ix86_preferred_stack_boundary;
2240 extern int ix86_branch_cost, ix86_section_threshold;
2241
2242 /* Smallest class containing REGNO. */
2243 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2244
2245 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2246 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2247 extern rtx ix86_compare_emitted;
2248 \f
2249 /* To properly truncate FP values into integers, we need to set i387 control
2250 word. We can't emit proper mode switching code before reload, as spills
2251 generated by reload may truncate values incorrectly, but we still can avoid
2252 redundant computation of new control word by the mode switching pass.
2253 The fldcw instructions are still emitted redundantly, but this is probably
2254 not going to be noticeable problem, as most CPUs do have fast path for
2255 the sequence.
2256
2257 The machinery is to emit simple truncation instructions and split them
2258 before reload to instructions having USEs of two memory locations that
2259 are filled by this code to old and new control word.
2260
2261 Post-reload pass may be later used to eliminate the redundant fildcw if
2262 needed. */
2263
2264 enum ix86_entity
2265 {
2266 I387_TRUNC = 0,
2267 I387_FLOOR,
2268 I387_CEIL,
2269 I387_MASK_PM,
2270 MAX_386_ENTITIES
2271 };
2272
2273 enum ix86_stack_slot
2274 {
2275 SLOT_TEMP = 0,
2276 SLOT_CW_STORED,
2277 SLOT_CW_TRUNC,
2278 SLOT_CW_FLOOR,
2279 SLOT_CW_CEIL,
2280 SLOT_CW_MASK_PM,
2281 MAX_386_STACK_LOCALS
2282 };
2283
2284 /* Define this macro if the port needs extra instructions inserted
2285 for mode switching in an optimizing compilation. */
2286
2287 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2288 ix86_optimize_mode_switching[(ENTITY)]
2289
2290 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2291 initializer for an array of integers. Each initializer element N
2292 refers to an entity that needs mode switching, and specifies the
2293 number of different modes that might need to be set for this
2294 entity. The position of the initializer in the initializer -
2295 starting counting at zero - determines the integer that is used to
2296 refer to the mode-switched entity in question. */
2297
2298 #define NUM_MODES_FOR_MODE_SWITCHING \
2299 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2300
2301 /* ENTITY is an integer specifying a mode-switched entity. If
2302 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2303 return an integer value not larger than the corresponding element
2304 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2305 must be switched into prior to the execution of INSN. */
2306
2307 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2308
2309 /* This macro specifies the order in which modes for ENTITY are
2310 processed. 0 is the highest priority. */
2311
2312 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2313
2314 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2315 is the set of hard registers live at the point where the insn(s)
2316 are to be inserted. */
2317
2318 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2319 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2320 ? emit_i387_cw_initialization (MODE), 0 \
2321 : 0)
2322
2323 \f
2324 /* Avoid renaming of stack registers, as doing so in combination with
2325 scheduling just increases amount of live registers at time and in
2326 the turn amount of fxch instructions needed.
2327
2328 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2329
2330 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2331 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2332
2333 \f
2334 #define DLL_IMPORT_EXPORT_PREFIX '#'
2335
2336 #define FASTCALL_PREFIX '@'
2337 \f
2338 struct machine_function GTY(())
2339 {
2340 struct stack_local_entry *stack_locals;
2341 const char *some_ld_name;
2342 rtx force_align_arg_pointer;
2343 int save_varrargs_registers;
2344 int accesses_prev_frame;
2345 int optimize_mode_switching[MAX_386_ENTITIES];
2346 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2347 determine the style used. */
2348 int use_fast_prologue_epilogue;
2349 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2350 for. */
2351 int use_fast_prologue_epilogue_nregs;
2352 /* If true, the current function needs the default PIC register, not
2353 an alternate register (on x86) and must not use the red zone (on
2354 x86_64), even if it's a leaf function. We don't want the
2355 function to be regarded as non-leaf because TLS calls need not
2356 affect register allocation. This flag is set when a TLS call
2357 instruction is expanded within a function, and never reset, even
2358 if all such instructions are optimized away. Use the
2359 ix86_current_function_calls_tls_descriptor macro for a better
2360 approximation. */
2361 int tls_descriptor_call_expanded_p;
2362 };
2363
2364 #define ix86_stack_locals (cfun->machine->stack_locals)
2365 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2366 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2367 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2368 (cfun->machine->tls_descriptor_call_expanded_p)
2369 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2370 calls are optimized away, we try to detect cases in which it was
2371 optimized away. Since such instructions (use (reg REG_SP)), we can
2372 verify whether there's any such instruction live by testing that
2373 REG_SP is live. */
2374 #define ix86_current_function_calls_tls_descriptor \
2375 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2376
2377 /* Control behavior of x86_file_start. */
2378 #define X86_FILE_START_VERSION_DIRECTIVE false
2379 #define X86_FILE_START_FLTUSED false
2380
2381 /* Flag to mark data that is in the large address area. */
2382 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2383 #define SYMBOL_REF_FAR_ADDR_P(X) \
2384 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2385 /*
2386 Local variables:
2387 version-control: t
2388 End:
2389 */