1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
25 /* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
40 /* Redefines for option macros. */
42 #define TARGET_64BIT TARGET_ISA_64BIT
43 #define TARGET_MMX TARGET_ISA_MMX
44 #define TARGET_3DNOW TARGET_ISA_3DNOW
45 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A
46 #define TARGET_SSE TARGET_ISA_SSE
47 #define TARGET_SSE2 TARGET_ISA_SSE2
48 #define TARGET_SSE3 TARGET_ISA_SSE3
49 #define TARGET_SSSE3 TARGET_ISA_SSSE3
50 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1
51 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2
52 #define TARGET_AVX TARGET_ISA_AVX
53 #define TARGET_AVX2 TARGET_ISA_AVX2
54 #define TARGET_FMA TARGET_ISA_FMA
55 #define TARGET_SSE4A TARGET_ISA_SSE4A
56 #define TARGET_FMA4 TARGET_ISA_FMA4
57 #define TARGET_XOP TARGET_ISA_XOP
58 #define TARGET_LWP TARGET_ISA_LWP
59 #define TARGET_ROUND TARGET_ISA_ROUND
60 #define TARGET_ABM TARGET_ISA_ABM
61 #define TARGET_BMI TARGET_ISA_BMI
62 #define TARGET_BMI2 TARGET_ISA_BMI2
63 #define TARGET_LZCNT TARGET_ISA_LZCNT
64 #define TARGET_TBM TARGET_ISA_TBM
65 #define TARGET_POPCNT TARGET_ISA_POPCNT
66 #define TARGET_SAHF TARGET_ISA_SAHF
67 #define TARGET_MOVBE TARGET_ISA_MOVBE
68 #define TARGET_CRC32 TARGET_ISA_CRC32
69 #define TARGET_AES TARGET_ISA_AES
70 #define TARGET_PCLMUL TARGET_ISA_PCLMUL
71 #define TARGET_CMPXCHG16B TARGET_ISA_CX16
72 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE
73 #define TARGET_RDRND TARGET_ISA_RDRND
74 #define TARGET_F16C TARGET_ISA_F16C
75 #define TARGET_RTM TARGET_ISA_RTM
76 #define TARGET_HLE TARGET_ISA_HLE
77 #define TARGET_RDSEED TARGET_ISA_RDSEED
78 #define TARGET_PRFCHW TARGET_ISA_PRFCHW
79 #define TARGET_ADX TARGET_ISA_ADX
80 #define TARGET_FXSR TARGET_ISA_FXSR
81 #define TARGET_XSAVE TARGET_ISA_XSAVE
82 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
84 #define TARGET_LP64 TARGET_ABI_64
85 #define TARGET_X32 TARGET_ABI_X32
87 /* SSE4.1 defines round instructions */
88 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
89 #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
91 #include "config/vxworks-dummy.h"
93 #include "config/i386/i386-opts.h"
95 #define MAX_STRINGOP_ALGS 4
97 /* Specify what algorithm to use for stringops on known size.
98 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
99 known at compile time or estimated via feedback, the SIZE array
100 is walked in order until MAX is greater then the estimate (or -1
101 means infinity). Corresponding ALG is used then.
102 When NOALIGN is true the code guaranting the alignment of the memory
105 For example initializer:
106 {{256, loop}, {-1, rep_prefix_4_byte}}
107 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
108 be used otherwise. */
111 const enum stringop_alg unknown_size
;
112 const struct stringop_strategy
{
114 const enum stringop_alg alg
;
116 } size
[MAX_STRINGOP_ALGS
];
119 /* Define the specific costs for a given cpu */
121 struct processor_costs
{
122 const int add
; /* cost of an add instruction */
123 const int lea
; /* cost of a lea instruction */
124 const int shift_var
; /* variable shift costs */
125 const int shift_const
; /* constant shift costs */
126 const int mult_init
[5]; /* cost of starting a multiply
127 in QImode, HImode, SImode, DImode, TImode*/
128 const int mult_bit
; /* cost of multiply per each bit set */
129 const int divide
[5]; /* cost of a divide/mod
130 in QImode, HImode, SImode, DImode, TImode*/
131 int movsx
; /* The cost of movsx operation. */
132 int movzx
; /* The cost of movzx operation. */
133 const int large_insn
; /* insns larger than this cost more */
134 const int move_ratio
; /* The threshold of number of scalar
135 memory-to-memory move insns. */
136 const int movzbl_load
; /* cost of loading using movzbl */
137 const int int_load
[3]; /* cost of loading integer registers
138 in QImode, HImode and SImode relative
139 to reg-reg move (2). */
140 const int int_store
[3]; /* cost of storing integer register
141 in QImode, HImode and SImode */
142 const int fp_move
; /* cost of reg,reg fld/fst */
143 const int fp_load
[3]; /* cost of loading FP register
144 in SFmode, DFmode and XFmode */
145 const int fp_store
[3]; /* cost of storing FP register
146 in SFmode, DFmode and XFmode */
147 const int mmx_move
; /* cost of moving MMX register. */
148 const int mmx_load
[2]; /* cost of loading MMX register
149 in SImode and DImode */
150 const int mmx_store
[2]; /* cost of storing MMX register
151 in SImode and DImode */
152 const int sse_move
; /* cost of moving SSE register. */
153 const int sse_load
[3]; /* cost of loading SSE register
154 in SImode, DImode and TImode*/
155 const int sse_store
[3]; /* cost of storing SSE register
156 in SImode, DImode and TImode*/
157 const int mmxsse_to_integer
; /* cost of moving mmxsse register to
158 integer and vice versa. */
159 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
160 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
161 const int prefetch_block
; /* bytes moved to cache for prefetch. */
162 const int simultaneous_prefetches
; /* number of parallel prefetch
164 const int branch_cost
; /* Default value for BRANCH_COST. */
165 const int fadd
; /* cost of FADD and FSUB instructions. */
166 const int fmul
; /* cost of FMUL instruction. */
167 const int fdiv
; /* cost of FDIV instruction. */
168 const int fabs
; /* cost of FABS instruction. */
169 const int fchs
; /* cost of FCHS instruction. */
170 const int fsqrt
; /* cost of FSQRT instruction. */
171 /* Specify what algorithm
172 to use for stringops on unknown size. */
173 struct stringop_algs memcpy
[2], memset
[2];
174 const int scalar_stmt_cost
; /* Cost of any scalar operation, excluding
176 const int scalar_load_cost
; /* Cost of scalar load. */
177 const int scalar_store_cost
; /* Cost of scalar store. */
178 const int vec_stmt_cost
; /* Cost of any vector operation, excluding
179 load, store, vector-to-scalar and
180 scalar-to-vector operation. */
181 const int vec_to_scalar_cost
; /* Cost of vect-to-scalar operation. */
182 const int scalar_to_vec_cost
; /* Cost of scalar-to-vector operation. */
183 const int vec_align_load_cost
; /* Cost of aligned vector load. */
184 const int vec_unalign_load_cost
; /* Cost of unaligned vector load. */
185 const int vec_store_cost
; /* Cost of vector store. */
186 const int cond_taken_branch_cost
; /* Cost of taken branch for vectorizer
188 const int cond_not_taken_branch_cost
;/* Cost of not taken branch for
189 vectorizer cost model. */
192 extern const struct processor_costs
*ix86_cost
;
193 extern const struct processor_costs ix86_size_cost
;
195 #define ix86_cur_cost() \
196 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
198 /* Macros used in the machine description to test the flags. */
200 /* configure can arrange to make this 2, to force a 486. */
202 #ifndef TARGET_CPU_DEFAULT
203 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
206 #ifndef TARGET_FPMATH_DEFAULT
207 #define TARGET_FPMATH_DEFAULT \
208 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
211 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
213 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
214 compile-time constant. */
218 #define TARGET_64BIT 1
220 #define TARGET_64BIT 0
223 #ifndef TARGET_BI_ARCH
225 #if TARGET_64BIT_DEFAULT
226 #define TARGET_64BIT 1
228 #define TARGET_64BIT 0
233 #define HAS_LONG_COND_BRANCH 1
234 #define HAS_LONG_UNCOND_BRANCH 1
236 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
237 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
238 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
239 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
240 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
241 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
242 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
243 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
244 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
245 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
246 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
247 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
248 #define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
249 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
250 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
251 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
252 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
253 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
254 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
255 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3)
256 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
257 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
258 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
260 /* Feature tests against the various tunings. */
261 enum ix86_tune_indices
{
263 X86_TUNE_PUSH_MEMORY
,
264 X86_TUNE_ZERO_EXTEND_WITH_AND
,
265 X86_TUNE_UNROLL_STRLEN
,
266 X86_TUNE_BRANCH_PREDICTION_HINTS
,
267 X86_TUNE_DOUBLE_WITH_ADD
,
270 X86_TUNE_PARTIAL_REG_STALL
,
271 X86_TUNE_PARTIAL_FLAG_REG_STALL
,
273 X86_TUNE_USE_HIMODE_FIOP
,
274 X86_TUNE_USE_SIMODE_FIOP
,
278 X86_TUNE_SPLIT_LONG_MOVES
,
279 X86_TUNE_READ_MODIFY_WRITE
,
280 X86_TUNE_READ_MODIFY
,
281 X86_TUNE_PROMOTE_QIMODE
,
282 X86_TUNE_FAST_PREFIX
,
283 X86_TUNE_SINGLE_STRINGOP
,
284 X86_TUNE_QIMODE_MATH
,
285 X86_TUNE_HIMODE_MATH
,
286 X86_TUNE_PROMOTE_QI_REGS
,
287 X86_TUNE_PROMOTE_HI_REGS
,
290 X86_TUNE_SINGLE_PUSH
,
291 X86_TUNE_DOUBLE_PUSH
,
292 X86_TUNE_INTEGER_DFMODE_MOVES
,
293 X86_TUNE_PARTIAL_REG_DEPENDENCY
,
294 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY
,
295 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL
,
296 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL
,
297 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL
,
298 X86_TUNE_SSE_SPLIT_REGS
,
299 X86_TUNE_SSE_TYPELESS_STORES
,
300 X86_TUNE_SSE_LOAD0_BY_PXOR
,
301 X86_TUNE_MEMORY_MISMATCH_STALL
,
302 X86_TUNE_PROLOGUE_USING_MOVE
,
303 X86_TUNE_EPILOGUE_USING_MOVE
,
306 X86_TUNE_INTER_UNIT_MOVES
,
307 X86_TUNE_INTER_UNIT_CONVERSIONS
,
308 X86_TUNE_FOUR_JUMP_LIMIT
,
312 X86_TUNE_PAD_RETURNS
,
313 X86_TUNE_PAD_SHORT_FUNCTION
,
314 X86_TUNE_EXT_80387_CONSTANTS
,
315 X86_TUNE_AVOID_VECTOR_DECODE
,
316 X86_TUNE_PROMOTE_HIMODE_IMUL
,
317 X86_TUNE_SLOW_IMUL_IMM32_MEM
,
318 X86_TUNE_SLOW_IMUL_IMM8
,
319 X86_TUNE_MOVE_M1_VIA_OR
,
320 X86_TUNE_NOT_UNPAIRABLE
,
321 X86_TUNE_NOT_VECTORMODE
,
322 X86_TUNE_USE_VECTOR_FP_CONVERTS
,
323 X86_TUNE_USE_VECTOR_CONVERTS
,
324 X86_TUNE_FUSE_CMP_AND_BRANCH
,
326 X86_TUNE_VECTORIZE_DOUBLE
,
327 X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL
,
328 X86_TUNE_AVX128_OPTIMAL
,
329 X86_TUNE_REASSOC_INT_TO_PARALLEL
,
330 X86_TUNE_REASSOC_FP_TO_PARALLEL
,
331 X86_TUNE_GENERAL_REGS_SSE_SPILL
,
332 X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE
,
337 extern unsigned char ix86_tune_features
[X86_TUNE_LAST
];
339 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
340 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
341 #define TARGET_ZERO_EXTEND_WITH_AND \
342 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
343 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
344 #define TARGET_BRANCH_PREDICTION_HINTS \
345 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
346 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
347 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
348 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
349 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
350 #define TARGET_PARTIAL_FLAG_REG_STALL \
351 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
352 #define TARGET_LCP_STALL \
353 ix86_tune_features[X86_TUNE_LCP_STALL]
354 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
355 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
356 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
357 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
358 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
359 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
360 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
361 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
362 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
363 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
364 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
365 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
366 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
367 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
368 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
369 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
370 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
371 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
372 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
373 #define TARGET_INTEGER_DFMODE_MOVES \
374 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
375 #define TARGET_PARTIAL_REG_DEPENDENCY \
376 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
377 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
378 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
379 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
380 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
381 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
382 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
383 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
384 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
385 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
386 #define TARGET_SSE_TYPELESS_STORES \
387 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
388 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
389 #define TARGET_MEMORY_MISMATCH_STALL \
390 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
391 #define TARGET_PROLOGUE_USING_MOVE \
392 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
393 #define TARGET_EPILOGUE_USING_MOVE \
394 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
395 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
396 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
397 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
398 #define TARGET_INTER_UNIT_CONVERSIONS\
399 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
400 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
401 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
402 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
403 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
404 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
405 #define TARGET_PAD_SHORT_FUNCTION \
406 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
407 #define TARGET_EXT_80387_CONSTANTS \
408 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
409 #define TARGET_AVOID_VECTOR_DECODE \
410 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
411 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
412 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
413 #define TARGET_SLOW_IMUL_IMM32_MEM \
414 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
415 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
416 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
417 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
418 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
419 #define TARGET_USE_VECTOR_FP_CONVERTS \
420 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
421 #define TARGET_USE_VECTOR_CONVERTS \
422 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
423 #define TARGET_FUSE_CMP_AND_BRANCH \
424 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
425 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
426 #define TARGET_VECTORIZE_DOUBLE \
427 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
428 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
429 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
430 #define TARGET_AVX128_OPTIMAL \
431 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
432 #define TARGET_REASSOC_INT_TO_PARALLEL \
433 ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL]
434 #define TARGET_REASSOC_FP_TO_PARALLEL \
435 ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL]
436 #define TARGET_GENERAL_REGS_SSE_SPILL \
437 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
438 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
439 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
441 /* Feature tests against the various architecture variations. */
442 enum ix86_arch_indices
{
452 extern unsigned char ix86_arch_features
[X86_ARCH_LAST
];
454 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
455 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
456 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
457 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
458 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
460 /* For sane SSE instruction set generation we need fcomi instruction.
461 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
462 expands to a sequence that includes conditional move. */
463 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
465 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
467 extern unsigned char x86_prefetch_sse
;
468 #define TARGET_PREFETCH_SSE x86_prefetch_sse
470 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
472 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
473 #define TARGET_MIX_SSE_I387 \
474 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
476 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
477 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
478 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
479 #define TARGET_SUN_TLS 0
481 #ifndef TARGET_64BIT_DEFAULT
482 #define TARGET_64BIT_DEFAULT 0
484 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
485 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
488 /* Fence to use after loop using storent. */
490 extern tree x86_mfence
;
491 #define FENCE_FOLLOWING_MOVNT x86_mfence
493 /* Once GDB has been enhanced to deal with functions without frame
494 pointers, we can change this to allow for elimination of
495 the frame pointer in leaf functions. */
496 #define TARGET_DEFAULT 0
498 /* Extra bits to force. */
499 #define TARGET_SUBTARGET_DEFAULT 0
500 #define TARGET_SUBTARGET_ISA_DEFAULT 0
502 /* Extra bits to force on w/ 32-bit mode. */
503 #define TARGET_SUBTARGET32_DEFAULT 0
504 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
506 /* Extra bits to force on w/ 64-bit mode. */
507 #define TARGET_SUBTARGET64_DEFAULT 0
508 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
510 /* Replace MACH-O, ifdefs by in-line tests, where possible.
511 (a) Macros defined in config/i386/darwin.h */
512 #define TARGET_MACHO 0
513 #define TARGET_MACHO_BRANCH_ISLANDS 0
514 #define MACHOPIC_ATT_STUB 0
515 /* (b) Macros defined in config/darwin.h */
516 #define MACHO_DYNAMIC_NO_PIC_P 0
517 #define MACHOPIC_INDIRECT 0
518 #define MACHOPIC_PURE 0
520 /* For the Windows 64-bit ABI. */
521 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
523 /* For the Windows 32-bit ABI. */
524 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
526 /* This is re-defined by cygming.h. */
529 /* The default abi used by target. */
530 #define DEFAULT_ABI SYSV_ABI
532 /* Subtargets may reset this to 1 in order to enable 96-bit long double
533 with the rounding mode forced to 53 bits. */
534 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
536 /* -march=native handling only makes sense with compiler running on
537 an x86 or x86_64 chip. If changing this condition, also change
538 the condition in driver-i386.c. */
539 #if defined(__i386__) || defined(__x86_64__)
540 /* In driver-i386.c. */
541 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
542 #define EXTRA_SPEC_FUNCTIONS \
543 { "local_cpu_detect", host_detect_local_cpu },
544 #define HAVE_LOCAL_CPU_DETECT
547 #if TARGET_64BIT_DEFAULT
548 #define OPT_ARCH64 "!m32"
549 #define OPT_ARCH32 "m32"
551 #define OPT_ARCH64 "m64|mx32"
552 #define OPT_ARCH32 "m64|mx32:;"
555 /* Support for configure-time defaults of some command line options.
556 The order here is important so that -march doesn't squash the
557 tune or cpu values. */
558 #define OPTION_DEFAULT_SPECS \
559 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
560 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
561 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
562 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
563 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
564 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
565 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
566 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
567 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
569 /* Specs for the compiler proper */
572 #define CC1_CPU_SPEC_1 ""
574 #ifndef HAVE_LOCAL_CPU_DETECT
575 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
577 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
578 "%{march=native:%>march=native %:local_cpu_detect(arch) \
579 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
580 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
584 /* Target CPU builtins. */
585 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
587 /* Target Pragmas. */
588 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
590 enum target_cpu_default
592 TARGET_CPU_DEFAULT_generic
= 0,
594 TARGET_CPU_DEFAULT_i386
,
595 TARGET_CPU_DEFAULT_i486
,
596 TARGET_CPU_DEFAULT_pentium
,
597 TARGET_CPU_DEFAULT_pentium_mmx
,
598 TARGET_CPU_DEFAULT_pentiumpro
,
599 TARGET_CPU_DEFAULT_pentium2
,
600 TARGET_CPU_DEFAULT_pentium3
,
601 TARGET_CPU_DEFAULT_pentium4
,
602 TARGET_CPU_DEFAULT_pentium_m
,
603 TARGET_CPU_DEFAULT_prescott
,
604 TARGET_CPU_DEFAULT_nocona
,
605 TARGET_CPU_DEFAULT_core2
,
606 TARGET_CPU_DEFAULT_corei7
,
607 TARGET_CPU_DEFAULT_atom
,
609 TARGET_CPU_DEFAULT_geode
,
610 TARGET_CPU_DEFAULT_k6
,
611 TARGET_CPU_DEFAULT_k6_2
,
612 TARGET_CPU_DEFAULT_k6_3
,
613 TARGET_CPU_DEFAULT_athlon
,
614 TARGET_CPU_DEFAULT_athlon_sse
,
615 TARGET_CPU_DEFAULT_k8
,
616 TARGET_CPU_DEFAULT_amdfam10
,
617 TARGET_CPU_DEFAULT_bdver1
,
618 TARGET_CPU_DEFAULT_bdver2
,
619 TARGET_CPU_DEFAULT_bdver3
,
620 TARGET_CPU_DEFAULT_btver1
,
621 TARGET_CPU_DEFAULT_btver2
,
623 TARGET_CPU_DEFAULT_max
627 #define CC1_SPEC "%(cc1_cpu) "
630 /* This macro defines names of additional specifications to put in the
631 specs that can be used in various specifications like CC1_SPEC. Its
632 definition is an initializer with a subgrouping for each command option.
634 Each subgrouping contains a string constant, that defines the
635 specification name, and a string constant that used by the GCC driver
638 Do not define this macro if it does not need to do anything. */
640 #ifndef SUBTARGET_EXTRA_SPECS
641 #define SUBTARGET_EXTRA_SPECS
644 #define EXTRA_SPECS \
645 { "cc1_cpu", CC1_CPU_SPEC }, \
646 SUBTARGET_EXTRA_SPECS
649 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
650 FPU, assume that the fpcw is set to extended precision; when using
651 only SSE, rounding is correct; when using both SSE and the FPU,
652 the rounding precision is indeterminate, since either may be chosen
653 apparently at random. */
654 #define TARGET_FLT_EVAL_METHOD \
655 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
657 /* Whether to allow x87 floating-point arithmetic on MODE (one of
658 SFmode, DFmode and XFmode) in the current excess precision
660 #define X87_ENABLE_ARITH(MODE) \
661 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
663 /* Likewise, whether to allow direct conversions from integer mode
664 IMODE (HImode, SImode or DImode) to MODE. */
665 #define X87_ENABLE_FLOAT(MODE, IMODE) \
666 (flag_excess_precision == EXCESS_PRECISION_FAST \
667 || (MODE) == XFmode \
668 || ((MODE) == DFmode && (IMODE) == SImode) \
669 || (IMODE) == HImode)
671 /* target machine storage layout */
673 #define SHORT_TYPE_SIZE 16
674 #define INT_TYPE_SIZE 32
675 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
676 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
677 #define LONG_LONG_TYPE_SIZE 64
678 #define FLOAT_TYPE_SIZE 32
679 #define DOUBLE_TYPE_SIZE 64
680 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 80)
682 /* Define this to set long double type size to use in libgcc2.c, which can
683 not depend on target_flags. */
684 #ifdef __LONG_DOUBLE_64__
685 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
687 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
690 #define WIDEST_HARDWARE_FP_SIZE 80
692 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
693 #define MAX_BITS_PER_WORD 64
695 #define MAX_BITS_PER_WORD 32
698 /* Define this if most significant byte of a word is the lowest numbered. */
699 /* That is true on the 80386. */
701 #define BITS_BIG_ENDIAN 0
703 /* Define this if most significant byte of a word is the lowest numbered. */
704 /* That is not true on the 80386. */
705 #define BYTES_BIG_ENDIAN 0
707 /* Define this if most significant word of a multiword number is the lowest
709 /* Not true for 80386 */
710 #define WORDS_BIG_ENDIAN 0
712 /* Width of a word, in units (bytes). */
713 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
716 #define MIN_UNITS_PER_WORD 4
719 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
720 #define PARM_BOUNDARY BITS_PER_WORD
722 /* Boundary (in *bits*) on which stack pointer should be aligned. */
723 #define STACK_BOUNDARY \
724 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
726 /* Stack boundary of the main function guaranteed by OS. */
727 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
729 /* Minimum stack boundary. */
730 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32)
732 /* Boundary (in *bits*) on which the stack pointer prefers to be
733 aligned; the compiler cannot rely on having this alignment. */
734 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
736 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
737 both 32bit and 64bit, to support codes that need 128 bit stack
738 alignment for SSE instructions, but can't realign the stack. */
739 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
741 /* 1 if -mstackrealign should be turned on by default. It will
742 generate an alternate prologue and epilogue that realigns the
743 runtime stack if nessary. This supports mixing codes that keep a
744 4-byte aligned stack, as specified by i386 psABI, with codes that
745 need a 16-byte aligned stack, as required by SSE instructions. */
746 #define STACK_REALIGN_DEFAULT 0
748 /* Boundary (in *bits*) on which the incoming stack is aligned. */
749 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
751 /* According to Windows x64 software convention, the maximum stack allocatable
752 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
753 instructions allowed to adjust the stack pointer in the epilog, forcing the
754 use of frame pointer for frames larger than 2 GB. This theorical limit
755 is reduced by 256, an over-estimated upper bound for the stack use by the
757 We define only one threshold for both the prolog and the epilog. When the
758 frame size is larger than this threshold, we allocate the area to save SSE
759 regs, then save them, and then allocate the remaining. There is no SEH
760 unwind info for this later allocation. */
761 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
763 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
764 mandatory for the 64-bit ABI, and may or may not be true for other
765 operating systems. */
766 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
768 /* Minimum allocation boundary for the code of a function. */
769 #define FUNCTION_BOUNDARY 8
771 /* C++ stores the virtual bit in the lowest bit of function pointers. */
772 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
774 /* Minimum size in bits of the largest boundary to which any
775 and all fundamental data types supported by the hardware
776 might need to be aligned. No data type wants to be aligned
779 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
780 and Pentium Pro XFmode values at 128 bit boundaries. */
782 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128)
784 /* Maximum stack alignment. */
785 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
787 /* Alignment value for attribute ((aligned)). It is a constant since
788 it is the part of the ABI. We shouldn't change it with -mavx. */
789 #define ATTRIBUTE_ALIGNED_VALUE 128
791 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
792 #define ALIGN_MODE_128(MODE) \
793 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
795 /* The published ABIs say that doubles should be aligned on word
796 boundaries, so lower the alignment for structure fields unless
797 -malign-double is set. */
799 /* ??? Blah -- this macro is used directly by libobjc. Since it
800 supports no vector modes, cut out the complexity and fall back
801 on BIGGEST_FIELD_ALIGNMENT. */
802 #ifdef IN_TARGET_LIBS
804 #define BIGGEST_FIELD_ALIGNMENT 128
806 #define BIGGEST_FIELD_ALIGNMENT 32
809 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
810 x86_field_alignment (FIELD, COMPUTED)
813 /* If defined, a C expression to compute the alignment given to a
814 constant that is being placed in memory. EXP is the constant
815 and ALIGN is the alignment that the object would ordinarily have.
816 The value of this macro is used instead of that alignment to align
819 If this macro is not defined, then ALIGN is used.
821 The typical use of this macro is to increase alignment for string
822 constants to be word aligned so that `strcpy' calls that copy
823 constants can be done inline. */
825 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
827 /* If defined, a C expression to compute the alignment for a static
828 variable. TYPE is the data type, and ALIGN is the alignment that
829 the object would ordinarily have. The value of this macro is used
830 instead of that alignment to align the object.
832 If this macro is not defined, then ALIGN is used.
834 One use of this macro is to increase alignment of medium-size
835 data to make it all fit in fewer cache lines. Another is to
836 cause character arrays to be word-aligned so that `strcpy' calls
837 that copy constants to character arrays can be done inline. */
839 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
841 /* If defined, a C expression to compute the alignment for a local
842 variable. TYPE is the data type, and ALIGN is the alignment that
843 the object would ordinarily have. The value of this macro is used
844 instead of that alignment to align the object.
846 If this macro is not defined, then ALIGN is used.
848 One use of this macro is to increase alignment of medium-size
849 data to make it all fit in fewer cache lines. */
851 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
852 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
854 /* If defined, a C expression to compute the alignment for stack slot.
855 TYPE is the data type, MODE is the widest mode available, and ALIGN
856 is the alignment that the slot would ordinarily have. The value of
857 this macro is used instead of that alignment to align the slot.
859 If this macro is not defined, then ALIGN is used when TYPE is NULL,
860 Otherwise, LOCAL_ALIGNMENT will be used.
862 One use of this macro is to set alignment of stack slot to the
863 maximum alignment of all possible modes which the slot may have. */
865 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
866 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
868 /* If defined, a C expression to compute the alignment for a local
871 If this macro is not defined, then
872 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
874 One use of this macro is to increase alignment of medium-size
875 data to make it all fit in fewer cache lines. */
877 #define LOCAL_DECL_ALIGNMENT(DECL) \
878 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
880 /* If defined, a C expression to compute the minimum required alignment
881 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
882 MODE, assuming normal alignment ALIGN.
884 If this macro is not defined, then (ALIGN) will be used. */
886 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
887 ix86_minimum_alignment (EXP, MODE, ALIGN)
890 /* Set this nonzero if move instructions will actually fail to work
891 when given unaligned data. */
892 #define STRICT_ALIGNMENT 0
894 /* If bit field type is int, don't let it cross an int,
895 and give entire struct the alignment of an int. */
896 /* Required on the 386 since it doesn't have bit-field insns. */
897 #define PCC_BITFIELD_TYPE_MATTERS 1
899 /* Standard register usage. */
901 /* This processor has special stack-like registers. See reg-stack.c
906 #define IS_STACK_MODE(MODE) \
907 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \
908 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
911 /* Number of actual hardware registers.
912 The hardware registers are assigned numbers for the compiler
913 from 0 to just below FIRST_PSEUDO_REGISTER.
914 All registers that the compiler knows about must be given numbers,
915 even those that are not normally considered general registers.
917 In the 80386 we give the 8 general purpose registers the numbers 0-7.
918 We number the floating point registers 8-15.
919 Note that registers 0-7 can be accessed as a short or int,
920 while only 0-3 may be used with byte `mov' instructions.
922 Reg 16 does not correspond to any hardware register, but instead
923 appears in the RTL as an argument pointer prior to reload, and is
924 eliminated during reloading in favor of either the stack or frame
927 #define FIRST_PSEUDO_REGISTER 53
929 /* Number of hardware registers that go into the DWARF-2 unwind info.
930 If not defined, equals FIRST_PSEUDO_REGISTER. */
932 #define DWARF_FRAME_REGISTERS 17
934 /* 1 for registers that have pervasive standard uses
935 and are not available for the register allocator.
936 On the 80386, the stack pointer is such, as is the arg pointer.
938 REX registers are disabled for 32bit targets in
939 TARGET_CONDITIONAL_REGISTER_USAGE. */
941 #define FIXED_REGISTERS \
942 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
943 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
944 /*arg,flags,fpsr,fpcr,frame*/ \
946 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
947 0, 0, 0, 0, 0, 0, 0, 0, \
948 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
949 0, 0, 0, 0, 0, 0, 0, 0, \
950 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
951 0, 0, 0, 0, 0, 0, 0, 0, \
952 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
953 0, 0, 0, 0, 0, 0, 0, 0 }
955 /* 1 for registers not available across function calls.
956 These must include the FIXED_REGISTERS and also any
957 registers that can be used without being saved.
958 The latter must include the registers where values are returned
959 and the register where structure-value addresses are passed.
960 Aside from that, you can include as many other registers as you like.
962 Value is set to 1 if the register is call used unconditionally.
963 Bit one is set if the register is call used on TARGET_32BIT ABI.
964 Bit two is set if the register is call used on TARGET_64BIT ABI.
965 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
967 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
969 #define CALL_USED_REGISTERS \
970 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
971 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
972 /*arg,flags,fpsr,fpcr,frame*/ \
974 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
975 1, 1, 1, 1, 1, 1, 6, 6, \
976 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
977 1, 1, 1, 1, 1, 1, 1, 1, \
978 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
979 1, 1, 1, 1, 2, 2, 2, 2, \
980 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
981 6, 6, 6, 6, 6, 6, 6, 6 }
983 /* Order in which to allocate registers. Each register must be
984 listed once, even those in FIXED_REGISTERS. List frame pointer
985 late and fixed registers last. Note that, in general, we prefer
986 registers listed in CALL_USED_REGISTERS, keeping the others
987 available for storage of persistent values.
989 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
990 so this is just empty initializer for array. */
992 #define REG_ALLOC_ORDER \
993 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
994 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
995 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
998 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
999 to be rearranged based on a particular function. When using sse math,
1000 we want to allocate SSE before x87 registers and vice versa. */
1002 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1005 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1007 /* Return number of consecutive hard regs needed starting at reg REGNO
1008 to hold something of mode MODE.
1009 This is ordinarily the length in words of a value of mode MODE
1010 but can be less for certain modes in special long registers.
1012 Actually there are no two word move instructions for consecutive
1013 registers. And only registers 0-3 may have mov byte instructions
1016 #define HARD_REGNO_NREGS(REGNO, MODE) \
1017 (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1018 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1019 : ((MODE) == XFmode \
1020 ? (TARGET_64BIT ? 2 : 3) \
1021 : (MODE) == XCmode \
1022 ? (TARGET_64BIT ? 4 : 6) \
1023 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1025 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1026 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1027 ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1029 : ((MODE) == XFmode || (MODE) == XCmode)) \
1032 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1034 #define VALID_AVX256_REG_MODE(MODE) \
1035 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1036 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1037 || (MODE) == V4DFmode)
1039 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1040 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1042 #define VALID_SSE2_REG_MODE(MODE) \
1043 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1044 || (MODE) == V2DImode || (MODE) == DFmode)
1046 #define VALID_SSE_REG_MODE(MODE) \
1047 ((MODE) == V1TImode || (MODE) == TImode \
1048 || (MODE) == V4SFmode || (MODE) == V4SImode \
1049 || (MODE) == SFmode || (MODE) == TFmode)
1051 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1052 ((MODE) == V2SFmode || (MODE) == SFmode)
1054 #define VALID_MMX_REG_MODE(MODE) \
1055 ((MODE == V1DImode) || (MODE) == DImode \
1056 || (MODE) == V2SImode || (MODE) == SImode \
1057 || (MODE) == V4HImode || (MODE) == V8QImode)
1059 #define VALID_DFP_MODE_P(MODE) \
1060 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1062 #define VALID_FP_MODE_P(MODE) \
1063 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1064 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1066 #define VALID_INT_MODE_P(MODE) \
1067 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1068 || (MODE) == DImode \
1069 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1070 || (MODE) == CDImode \
1071 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1072 || (MODE) == TFmode || (MODE) == TCmode)))
1074 /* Return true for modes passed in SSE registers. */
1075 #define SSE_REG_MODE_P(MODE) \
1076 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1077 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1078 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1079 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1080 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1081 || (MODE) == V2TImode)
1083 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1085 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1086 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1088 /* Value is 1 if it is a good idea to tie two pseudo registers
1089 when one has mode MODE1 and one has mode MODE2.
1090 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1091 for any hard reg, then this must be 0 for correct output. */
1093 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1095 /* It is possible to write patterns to move flags; but until someone
1097 #define AVOID_CCMODE_COPIES
1099 /* Specify the modes required to caller save a given hard regno.
1100 We do this on i386 to prevent flags from being saved at all.
1102 Kill any attempts to combine saving of modes. */
1104 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1105 (CC_REGNO_P (REGNO) ? VOIDmode \
1106 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1107 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1108 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1109 : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO)) ? SImode \
1112 /* The only ABI that saves SSE registers across calls is Win64 (thus no
1113 need to check the current ABI here), and with AVX enabled Win64 only
1114 guarantees that the low 16 bytes are saved. */
1115 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1116 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16)
1118 /* Specify the registers used for certain standard purposes.
1119 The values of these macros are register numbers. */
1121 /* on the 386 the pc register is %eip, and is not usable as a general
1122 register. The ordinary mov instructions won't work */
1123 /* #define PC_REGNUM */
1125 /* Register to use for pushing function arguments. */
1126 #define STACK_POINTER_REGNUM 7
1128 /* Base register for access to local variables of the function. */
1129 #define HARD_FRAME_POINTER_REGNUM 6
1131 /* Base register for access to local variables of the function. */
1132 #define FRAME_POINTER_REGNUM 20
1134 /* First floating point reg */
1135 #define FIRST_FLOAT_REG 8
1137 /* First & last stack-like regs */
1138 #define FIRST_STACK_REG FIRST_FLOAT_REG
1139 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1141 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1142 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1144 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1145 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1147 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1148 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1150 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1151 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1153 /* Override this in other tm.h files to cope with various OS lossage
1154 requiring a frame pointer. */
1155 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1156 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1159 /* Make sure we can access arbitrary call frames. */
1160 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1162 /* Base register for access to arguments of the function. */
1163 #define ARG_POINTER_REGNUM 16
1165 /* Register to hold the addressing base for position independent
1166 code access to data items. We don't use PIC pointer for 64bit
1167 mode. Define the regnum to dummy value to prevent gcc from
1168 pessimizing code dealing with EBX.
1170 To avoid clobbering a call-saved register unnecessarily, we renumber
1171 the pic register when possible. The change is visible after the
1172 prologue has been emitted. */
1174 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1176 #define PIC_OFFSET_TABLE_REGNUM \
1177 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1178 || !flag_pic ? INVALID_REGNUM \
1179 : reload_completed ? REGNO (pic_offset_table_rtx) \
1180 : REAL_PIC_OFFSET_TABLE_REGNUM)
1182 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1184 /* This is overridden by <cygwin.h>. */
1185 #define MS_AGGREGATE_RETURN 0
1187 #define KEEP_AGGREGATE_RETURN_POINTER 0
1189 /* Define the classes of registers for register constraints in the
1190 machine description. Also define ranges of constants.
1192 One of the classes must always be named ALL_REGS and include all hard regs.
1193 If there is more than one class, another class must be named NO_REGS
1194 and contain no registers.
1196 The name GENERAL_REGS must be the name of a class (or an alias for
1197 another name such as ALL_REGS). This is the class of registers
1198 that is allowed by "g" or "r" in a register constraint.
1199 Also, registers outside this class are allocated only when
1200 instructions express preferences for them.
1202 The classes must be numbered in nondecreasing order; that is,
1203 a larger-numbered class must never be contained completely
1204 in a smaller-numbered class.
1206 For any two classes, it is very desirable that there be another
1207 class that represents their union.
1209 It might seem that class BREG is unnecessary, since no useful 386
1210 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1211 and the "b" register constraint is useful in asms for syscalls.
1213 The flags, fpsr and fpcr registers are in no class. */
1218 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
1219 AD_REGS
, /* %eax/%edx for DImode */
1220 Q_REGS
, /* %eax %ebx %ecx %edx */
1221 NON_Q_REGS
, /* %esi %edi %ebp %esp */
1222 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1223 LEGACY_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1224 CLOBBERED_REGS
, /* call-clobbered integer registers */
1225 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1226 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1227 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
1238 ALL_REGS
, LIM_REG_CLASSES
1241 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1243 #define INTEGER_CLASS_P(CLASS) \
1244 reg_class_subset_p ((CLASS), GENERAL_REGS)
1245 #define FLOAT_CLASS_P(CLASS) \
1246 reg_class_subset_p ((CLASS), FLOAT_REGS)
1247 #define SSE_CLASS_P(CLASS) \
1248 reg_class_subset_p ((CLASS), SSE_REGS)
1249 #define MMX_CLASS_P(CLASS) \
1250 ((CLASS) == MMX_REGS)
1251 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1252 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1253 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1254 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1255 #define MAYBE_SSE_CLASS_P(CLASS) \
1256 reg_classes_intersect_p (SSE_REGS, (CLASS))
1257 #define MAYBE_MMX_CLASS_P(CLASS) \
1258 reg_classes_intersect_p (MMX_REGS, (CLASS))
1260 #define Q_CLASS_P(CLASS) \
1261 reg_class_subset_p ((CLASS), Q_REGS)
1263 /* Give names of register classes as strings for dump file. */
1265 #define REG_CLASS_NAMES \
1267 "AREG", "DREG", "CREG", "BREG", \
1270 "Q_REGS", "NON_Q_REGS", \
1275 "FP_TOP_REG", "FP_SECOND_REG", \
1280 "FP_TOP_SSE_REGS", \
1281 "FP_SECOND_SSE_REGS", \
1285 "FLOAT_INT_SSE_REGS", \
1288 /* Define which registers fit in which classes. This is an initializer
1289 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1291 Note that CLOBBERED_REGS are calculated by
1292 TARGET_CONDITIONAL_REGISTER_USAGE. */
1294 #define REG_CLASS_CONTENTS \
1296 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1297 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1298 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1299 { 0x03, 0x0 }, /* AD_REGS */ \
1300 { 0x0f, 0x0 }, /* Q_REGS */ \
1301 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1302 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1303 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1304 { 0x00, 0x0 }, /* CLOBBERED_REGS */ \
1305 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1306 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1307 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1308 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1309 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1310 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1311 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1312 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1313 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1314 { 0x11ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1315 { 0x1ff100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1316 { 0x1ff1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1317 { 0xffffffff,0x1fffff } \
1320 /* The same information, inverted:
1321 Return the class number of the smallest class containing
1322 reg number REGNO. This could be a conditional expression
1323 or could index an array. */
1325 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1327 /* When this hook returns true for MODE, the compiler allows
1328 registers explicitly used in the rtl to be used as spill registers
1329 but prevents the compiler from extending the lifetime of these
1331 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1333 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1334 #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG)
1336 #define GENERAL_REG_P(X) \
1337 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1338 #define GENERAL_REGNO_P(N) \
1339 (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N))
1341 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1342 #define ANY_QI_REGNO_P(N) \
1343 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1345 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1346 #define REX_INT_REGNO_P(N) \
1347 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1349 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1350 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1352 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1353 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1355 #define X87_FLOAT_MODE_P(MODE) \
1356 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1358 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1359 #define SSE_REGNO_P(N) \
1360 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1361 || REX_SSE_REGNO_P (N))
1363 #define REX_SSE_REGNO_P(N) \
1364 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1366 #define SSE_REGNO(N) \
1367 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1369 #define SSE_FLOAT_MODE_P(MODE) \
1370 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1372 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1373 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1374 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1376 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1377 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1379 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG)
1381 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1382 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1384 /* The class value for index registers, and the one for base regs. */
1386 #define INDEX_REG_CLASS INDEX_REGS
1387 #define BASE_REG_CLASS GENERAL_REGS
1389 /* Place additional restrictions on the register class to use when it
1390 is necessary to be able to hold a value of mode MODE in a reload
1391 register for which class CLASS would ordinarily be used.
1393 We avoid classes containing registers from multiple units due to
1394 the limitation in ix86_secondary_memory_needed. We limit these
1395 classes to their "natural mode" single unit register class, depending
1396 on the unit availability.
1398 Please note that reg_class_subset_p is not commutative, so these
1399 conditions mean "... if (CLASS) includes ALL registers from the
1402 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1403 (((MODE) == QImode && !TARGET_64BIT \
1404 && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \
1405 : (((MODE) == SImode || (MODE) == DImode) \
1406 && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \
1407 : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \
1408 && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \
1409 : (X87_FLOAT_MODE_P (MODE) \
1410 && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \
1413 /* If we are copying between general and FP registers, we need a memory
1414 location. The same is true for SSE and MMX registers. */
1415 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1416 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1418 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1419 There is no need to emit full 64 bit move on 64 bit targets
1420 for integral modes that can be moved using 32 bit move. */
1421 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1422 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1423 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1426 /* Return a class of registers that cannot change FROM mode to TO mode. */
1428 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1429 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1431 /* Stack layout; function entry, exit and calling. */
1433 /* Define this if pushing a word on the stack
1434 makes the stack pointer a smaller address. */
1435 #define STACK_GROWS_DOWNWARD
1437 /* Define this to nonzero if the nominal address of the stack frame
1438 is at the high-address end of the local variables;
1439 that is, each additional local variable allocated
1440 goes at a more negative offset in the frame. */
1441 #define FRAME_GROWS_DOWNWARD 1
1443 /* Offset within stack frame to start allocating local variables at.
1444 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1445 first local allocated. Otherwise, it is the offset to the BEGINNING
1446 of the first local allocated. */
1447 #define STARTING_FRAME_OFFSET 0
1449 /* If we generate an insn to push BYTES bytes, this says how many the stack
1450 pointer really advances by. On 386, we have pushw instruction that
1451 decrements by exactly 2 no matter what the position was, there is no pushb.
1453 But as CIE data alignment factor on this arch is -4 for 32bit targets
1454 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1455 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1457 #define PUSH_ROUNDING(BYTES) \
1458 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
1460 /* If defined, the maximum amount of space required for outgoing arguments
1461 will be computed and placed into the variable `crtl->outgoing_args_size'.
1462 No space will be pushed onto the stack for each call; instead, the
1463 function prologue should increase the stack frame size by this amount.
1465 64-bit MS ABI seem to require 16 byte alignment everywhere except for
1466 function prologue and apilogue. This is not possible without
1467 ACCUMULATE_OUTGOING_ARGS. */
1469 #define ACCUMULATE_OUTGOING_ARGS \
1470 (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI)
1472 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1473 instructions to pass outgoing arguments. */
1475 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1477 /* We want the stack and args grow in opposite directions, even if
1479 #define PUSH_ARGS_REVERSED 1
1481 /* Offset of first parameter from the argument pointer register value. */
1482 #define FIRST_PARM_OFFSET(FNDECL) 0
1484 /* Define this macro if functions should assume that stack space has been
1485 allocated for arguments even when their values are passed in registers.
1487 The value of this macro is the size, in bytes, of the area reserved for
1488 arguments passed in registers for the function represented by FNDECL.
1490 This space can be allocated by the caller, or be a part of the
1491 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1493 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1495 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1496 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1498 /* Define how to find the value returned by a library function
1499 assuming the value has mode MODE. */
1501 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1503 /* Define the size of the result block used for communication between
1504 untyped_call and untyped_return. The block contains a DImode value
1505 followed by the block used by fnsave and frstor. */
1507 #define APPLY_RESULT_SIZE (8+108)
1509 /* 1 if N is a possible register number for function argument passing. */
1510 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1512 /* Define a data type for recording info about an argument list
1513 during the scan of that argument list. This data type should
1514 hold all necessary information about the function itself
1515 and about the args processed so far, enough to enable macros
1516 such as FUNCTION_ARG to determine where the next arg should go. */
1518 typedef struct ix86_args
{
1519 int words
; /* # words passed so far */
1520 int nregs
; /* # registers available for passing */
1521 int regno
; /* next available register number */
1522 int fastcall
; /* fastcall or thiscall calling convention
1524 int sse_words
; /* # sse words passed so far */
1525 int sse_nregs
; /* # sse registers available for passing */
1526 int warn_avx
; /* True when we want to warn about AVX ABI. */
1527 int warn_sse
; /* True when we want to warn about SSE ABI. */
1528 int warn_mmx
; /* True when we want to warn about MMX ABI. */
1529 int sse_regno
; /* next available sse register number */
1530 int mmx_words
; /* # mmx words passed so far */
1531 int mmx_nregs
; /* # mmx registers available for passing */
1532 int mmx_regno
; /* next available mmx register number */
1533 int maybe_vaarg
; /* true for calls to possibly vardic fncts. */
1534 int caller
; /* true if it is caller. */
1535 int float_in_sse
; /* Set to 1 or 2 for 32bit targets if
1536 SFmode/DFmode arguments should be passed
1537 in SSE registers. Otherwise 0. */
1538 enum calling_abi call_abi
; /* Set to SYSV_ABI for sysv abi. Otherwise
1539 MS_ABI for ms abi. */
1542 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1543 for a call to a function whose data type is FNTYPE.
1544 For a library call, FNTYPE is 0. */
1546 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1547 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1548 (N_NAMED_ARGS) != -1)
1550 /* Output assembler code to FILE to increment profiler label # LABELNO
1551 for profiling a function entry. */
1553 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1555 #define MCOUNT_NAME "_mcount"
1557 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1559 #define PROFILE_COUNT_REGISTER "edx"
1561 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1562 the stack pointer does not matter. The value is tested only in
1563 functions that have frame pointers.
1564 No definition is equivalent to always zero. */
1565 /* Note on the 386 it might be more efficient not to define this since
1566 we have to restore it ourselves from the frame pointer, in order to
1569 #define EXIT_IGNORE_STACK 1
1571 /* Output assembler code for a block containing the constant parts
1572 of a trampoline, leaving space for the variable parts. */
1574 /* On the 386, the trampoline contains two instructions:
1577 The trampoline is generated entirely at runtime. The operand of JMP
1578 is the address of FUNCTION relative to the instruction following the
1579 JMP (which is 5 bytes long). */
1581 /* Length in units of the trampoline for entering a nested function. */
1583 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1585 /* Definitions for register eliminations.
1587 This is an array of structures. Each structure initializes one pair
1588 of eliminable registers. The "from" register number is given first,
1589 followed by "to". Eliminations of the same "from" register are listed
1590 in order of preference.
1592 There are two registers that can always be eliminated on the i386.
1593 The frame pointer and the arg pointer can be replaced by either the
1594 hard frame pointer or to the stack pointer, depending upon the
1595 circumstances. The hard frame pointer is not used before reload and
1596 so it is not eligible for elimination. */
1598 #define ELIMINABLE_REGS \
1599 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1600 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1601 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1602 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1604 /* Define the offset between two registers, one to be eliminated, and the other
1605 its replacement, at the start of a routine. */
1607 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1608 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1610 /* Addressing modes, and classification of registers for them. */
1612 /* Macros to check register numbers against specific register classes. */
1614 /* These assume that REGNO is a hard or pseudo reg number.
1615 They give nonzero only if REGNO is a hard reg of the suitable class
1616 or a pseudo reg currently allocated to a suitable hard reg.
1617 Since they use reg_renumber, they are safe only once reg_renumber
1618 has been allocated, which happens in reginfo.c during register
1621 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1622 ((REGNO) < STACK_POINTER_REGNUM \
1623 || REX_INT_REGNO_P (REGNO) \
1624 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1625 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1627 #define REGNO_OK_FOR_BASE_P(REGNO) \
1628 (GENERAL_REGNO_P (REGNO) \
1629 || (REGNO) == ARG_POINTER_REGNUM \
1630 || (REGNO) == FRAME_POINTER_REGNUM \
1631 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1633 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1634 and check its validity for a certain class.
1635 We have two alternate definitions for each of them.
1636 The usual definition accepts all pseudo regs; the other rejects
1637 them unless they have been allocated suitable hard regs.
1638 The symbol REG_OK_STRICT causes the latter definition to be used.
1640 Most source files want to accept pseudo regs in the hope that
1641 they will get allocated to the class that the insn wants them to be in.
1642 Source files for reload pass need to be strict.
1643 After reload, it makes no difference, since pseudo regs have
1644 been eliminated by then. */
1647 /* Non strict versions, pseudos are ok. */
1648 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1649 (REGNO (X) < STACK_POINTER_REGNUM \
1650 || REX_INT_REGNO_P (REGNO (X)) \
1651 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1653 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1654 (GENERAL_REGNO_P (REGNO (X)) \
1655 || REGNO (X) == ARG_POINTER_REGNUM \
1656 || REGNO (X) == FRAME_POINTER_REGNUM \
1657 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1659 /* Strict versions, hard registers only */
1660 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1661 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1663 #ifndef REG_OK_STRICT
1664 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1665 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1668 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1669 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1672 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1673 that is a valid memory address for an instruction.
1674 The MODE argument is the machine mode for the MEM expression
1675 that wants to use this address.
1677 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1678 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1680 See legitimize_pic_address in i386.c for details as to what
1681 constitutes a legitimate address when -fpic is used. */
1683 #define MAX_REGS_PER_ADDRESS 2
1685 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1687 /* Try a machine-dependent way of reloading an illegitimate address
1688 operand. If we find one, push the reload and jump to WIN. This
1689 macro is used in only one place: `find_reloads_address' in reload.c. */
1691 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \
1693 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \
1694 (int)(TYPE), (INDL))) \
1698 /* If defined, a C expression to determine the base term of address X.
1699 This macro is used in only one place: `find_base_term' in alias.c.
1701 It is always safe for this macro to not be defined. It exists so
1702 that alias analysis can understand machine-dependent addresses.
1704 The typical use of this macro is to handle addresses containing
1705 a label_ref or symbol_ref within an UNSPEC. */
1707 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1709 /* Nonzero if the constant value X is a legitimate general operand
1710 when generating PIC code. It is given that flag_pic is on and
1711 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1713 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1715 #define SYMBOLIC_CONST(X) \
1716 (GET_CODE (X) == SYMBOL_REF \
1717 || GET_CODE (X) == LABEL_REF \
1718 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1720 /* Max number of args passed in registers. If this is more than 3, we will
1721 have problems with ebx (register #4), since it is a caller save register and
1722 is also used as the pic register in ELF. So for now, don't allow more than
1723 3 registers to be passed in registers. */
1725 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1726 #define X86_64_REGPARM_MAX 6
1727 #define X86_64_MS_REGPARM_MAX 4
1729 #define X86_32_REGPARM_MAX 3
1731 #define REGPARM_MAX \
1733 ? (TARGET_64BIT_MS_ABI \
1734 ? X86_64_MS_REGPARM_MAX \
1735 : X86_64_REGPARM_MAX) \
1736 : X86_32_REGPARM_MAX)
1738 #define X86_64_SSE_REGPARM_MAX 8
1739 #define X86_64_MS_SSE_REGPARM_MAX 4
1741 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1743 #define SSE_REGPARM_MAX \
1745 ? (TARGET_64BIT_MS_ABI \
1746 ? X86_64_MS_SSE_REGPARM_MAX \
1747 : X86_64_SSE_REGPARM_MAX) \
1748 : X86_32_SSE_REGPARM_MAX)
1750 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1752 /* Specify the machine mode that this machine uses
1753 for the index in the tablejump instruction. */
1754 #define CASE_VECTOR_MODE \
1755 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1757 /* Define this as 1 if `char' should by default be signed; else as 0. */
1758 #define DEFAULT_SIGNED_CHAR 1
1760 /* Max number of bytes we can move from memory to memory
1761 in one reasonably fast instruction. */
1764 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1765 move efficiently, as opposed to MOVE_MAX which is the maximum
1766 number of bytes we can move with a single instruction. */
1767 #define MOVE_MAX_PIECES UNITS_PER_WORD
1769 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1770 move-instruction pairs, we will do a movmem or libcall instead.
1771 Increasing the value will always make code faster, but eventually
1772 incurs high cost in increased code size.
1774 If you don't define this, a reasonable default is used. */
1776 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1778 /* If a clear memory operation would take CLEAR_RATIO or more simple
1779 move-instruction sequences, we will do a clrmem or libcall instead. */
1781 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1783 /* Define if shifts truncate the shift count which implies one can
1784 omit a sign-extension or zero-extension of a shift count.
1786 On i386, shifts do truncate the count. But bit test instructions
1787 take the modulo of the bit offset operand. */
1789 /* #define SHIFT_COUNT_TRUNCATED */
1791 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1792 is done just by pretending it is already truncated. */
1793 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1795 /* A macro to update M and UNSIGNEDP when an object whose type is
1796 TYPE and which has the specified mode and signedness is to be
1797 stored in a register. This macro is only called when TYPE is a
1800 On i386 it is sometimes useful to promote HImode and QImode
1801 quantities to SImode. The choice depends on target type. */
1803 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1805 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1806 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1810 /* Specify the machine mode that pointers have.
1811 After generation of rtl, the compiler makes no further distinction
1812 between pointers and any other objects of this machine mode. */
1813 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1815 /* A C expression whose value is zero if pointers that need to be extended
1816 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1817 greater then zero if they are zero-extended and less then zero if the
1818 ptr_extend instruction should be used. */
1820 #define POINTERS_EXTEND_UNSIGNED 1
1822 /* A function address in a call instruction
1823 is a byte address (for indexing purposes)
1824 so give the MEM rtx a byte's mode. */
1825 #define FUNCTION_MODE QImode
1828 /* A C expression for the cost of a branch instruction. A value of 1
1829 is the default; other values are interpreted relative to that. */
1831 #define BRANCH_COST(speed_p, predictable_p) \
1832 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1834 /* An integer expression for the size in bits of the largest integer machine
1835 mode that should actually be used. We allow pairs of registers. */
1836 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1838 /* Define this macro as a C expression which is nonzero if accessing
1839 less than a word of memory (i.e. a `char' or a `short') is no
1840 faster than accessing a word of memory, i.e., if such access
1841 require more than one instruction or if there is no difference in
1842 cost between byte and (aligned) word loads.
1844 When this macro is not defined, the compiler will access a field by
1845 finding the smallest containing object; when it is defined, a
1846 fullword load will be used if alignment permits. Unless bytes
1847 accesses are faster than word accesses, using word accesses is
1848 preferable since it may eliminate subsequent memory access if
1849 subsequent accesses occur to other fields in the same word of the
1850 structure, but to different bytes. */
1852 #define SLOW_BYTE_ACCESS 0
1854 /* Nonzero if access to memory by shorts is slow and undesirable. */
1855 #define SLOW_SHORT_ACCESS 0
1857 /* Define this macro to be the value 1 if unaligned accesses have a
1858 cost many times greater than aligned accesses, for example if they
1859 are emulated in a trap handler.
1861 When this macro is nonzero, the compiler will act as if
1862 `STRICT_ALIGNMENT' were nonzero when generating code for block
1863 moves. This can cause significantly more instructions to be
1864 produced. Therefore, do not set this macro nonzero if unaligned
1865 accesses only add a cycle or two to the time for a memory access.
1867 If the value of this macro is always zero, it need not be defined. */
1869 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1871 /* Define this macro if it is as good or better to call a constant
1872 function address than to call an address kept in a register.
1874 Desirable on the 386 because a CALL with a constant address is
1875 faster than one with a register address. */
1877 #define NO_FUNCTION_CSE
1879 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1880 return the mode to be used for the comparison.
1882 For floating-point equality comparisons, CCFPEQmode should be used.
1883 VOIDmode should be used in all other cases.
1885 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1886 possible, to allow for more combinations. */
1888 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1890 /* Return nonzero if MODE implies a floating point inequality can be
1893 #define REVERSIBLE_CC_MODE(MODE) 1
1895 /* A C expression whose value is reversed condition code of the CODE for
1896 comparison done in CC_MODE mode. */
1897 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1900 /* Control the assembler format that we output, to the extent
1901 this does not vary between assemblers. */
1903 /* How to refer to registers in assembler output.
1904 This sequence is indexed by compiler's hard-register-number (see above). */
1906 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1907 For non floating point regs, the following are the HImode names.
1909 For float regs, the stack top is sometimes referred to as "%st(0)"
1910 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1913 #define HI_REGISTER_NAMES \
1914 {"ax","dx","cx","bx","si","di","bp","sp", \
1915 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1916 "argp", "flags", "fpsr", "fpcr", "frame", \
1917 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1918 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1919 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1920 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1922 #define REGISTER_NAMES HI_REGISTER_NAMES
1924 /* Table of additional register names to use in user input. */
1926 #define ADDITIONAL_REGISTER_NAMES \
1927 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1928 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1929 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1930 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1931 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1932 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1934 /* Note we are omitting these since currently I don't know how
1935 to get gcc to use these, since they want the same but different
1936 number as al, and ax.
1939 #define QI_REGISTER_NAMES \
1940 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1942 /* These parallel the array above, and can be used to access bits 8:15
1943 of regs 0 through 3. */
1945 #define QI_HIGH_REGISTER_NAMES \
1946 {"ah", "dh", "ch", "bh", }
1948 /* How to renumber registers for dbx and gdb. */
1950 #define DBX_REGISTER_NUMBER(N) \
1951 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1953 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
1954 extern int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
];
1955 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
1957 /* Before the prologue, RA is at 0(%esp). */
1958 #define INCOMING_RETURN_ADDR_RTX \
1959 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1961 /* After the prologue, RA is at -4(AP) in the current frame. */
1962 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1964 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
1966 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD)))
1968 /* PC is dbx register 8; let's use that column for RA. */
1969 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1971 /* Before the prologue, the top of the frame is at 4(%esp). */
1972 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1974 /* Describe how we implement __builtin_eh_return. */
1975 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
1976 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
1979 /* Select a format to encode pointers in exception handling data. CODE
1980 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1981 true if the symbol may be affected by dynamic relocations.
1983 ??? All x86 object file formats are capable of representing this.
1984 After all, the relocation needed is the same as for the call insn.
1985 Whether or not a particular assembler allows us to enter such, I
1986 guess we'll have to see. */
1987 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1988 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1990 /* This is how to output an insn to push a register on the stack.
1991 It need not be very fast code. */
1993 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1996 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1997 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1999 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2002 /* This is how to output an insn to pop a register from the stack.
2003 It need not be very fast code. */
2005 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2008 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2009 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2011 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2014 /* This is how to output an element of a case-vector that is absolute. */
2016 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2017 ix86_output_addr_vec_elt ((FILE), (VALUE))
2019 /* This is how to output an element of a case-vector that is relative. */
2021 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2022 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2024 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2026 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2028 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2029 (PTR) += TARGET_AVX ? 1 : 2; \
2032 /* A C statement or statements which output an assembler instruction
2033 opcode to the stdio stream STREAM. The macro-operand PTR is a
2034 variable of type `char *' which points to the opcode name in
2035 its "internal" form--the form that is written in the machine
2038 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2039 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2041 /* A C statement to output to the stdio stream FILE an assembler
2042 command to pad the location counter to a multiple of 1<<LOG
2043 bytes if it is within MAX_SKIP bytes. */
2045 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2046 #undef ASM_OUTPUT_MAX_SKIP_PAD
2047 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2050 if ((MAX_SKIP) == 0) \
2051 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2053 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2057 /* Write the extra assembler code needed to declare a function
2060 #undef ASM_OUTPUT_FUNCTION_LABEL
2061 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2062 ix86_asm_output_function_label (FILE, NAME, DECL)
2064 /* Under some conditions we need jump tables in the text section,
2065 because the assembler cannot handle label differences between
2066 sections. This is the case for x86_64 on Mach-O for example. */
2068 #define JUMP_TABLES_IN_TEXT_SECTION \
2069 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2070 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2072 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2073 and switch back. For x86 we do this only to save a few bytes that
2074 would otherwise be unused in the text section. */
2075 #define CRT_MKSTR2(VAL) #VAL
2076 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2078 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2079 asm (SECTION_OP "\n\t" \
2080 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2081 TEXT_SECTION_ASM_OP);
2083 /* Which processor to tune code generation for. */
2087 PROCESSOR_I386
= 0, /* 80386 */
2088 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
2090 PROCESSOR_PENTIUMPRO
,
2099 PROCESSOR_GENERIC32
,
2100 PROCESSOR_GENERIC64
,
2111 extern enum processor_type ix86_tune
;
2112 extern enum processor_type ix86_arch
;
2114 /* Size of the RED_ZONE area. */
2115 #define RED_ZONE_SIZE 128
2116 /* Reserved area of the red zone for temporaries. */
2117 #define RED_ZONE_RESERVE 8
2119 extern unsigned int ix86_preferred_stack_boundary
;
2120 extern unsigned int ix86_incoming_stack_boundary
;
2122 /* Smallest class containing REGNO. */
2123 extern enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
];
2125 enum ix86_fpcmp_strategy
{
2131 /* To properly truncate FP values into integers, we need to set i387 control
2132 word. We can't emit proper mode switching code before reload, as spills
2133 generated by reload may truncate values incorrectly, but we still can avoid
2134 redundant computation of new control word by the mode switching pass.
2135 The fldcw instructions are still emitted redundantly, but this is probably
2136 not going to be noticeable problem, as most CPUs do have fast path for
2139 The machinery is to emit simple truncation instructions and split them
2140 before reload to instructions having USEs of two memory locations that
2141 are filled by this code to old and new control word.
2143 Post-reload pass may be later used to eliminate the redundant fildcw if
2156 enum ix86_stack_slot
2164 MAX_386_STACK_LOCALS
2174 /* Define this macro if the port needs extra instructions inserted
2175 for mode switching in an optimizing compilation. */
2177 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2178 ix86_optimize_mode_switching[(ENTITY)]
2180 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2181 initializer for an array of integers. Each initializer element N
2182 refers to an entity that needs mode switching, and specifies the
2183 number of different modes that might need to be set for this
2184 entity. The position of the initializer in the initializer -
2185 starting counting at zero - determines the integer that is used to
2186 refer to the mode-switched entity in question. */
2188 #define NUM_MODES_FOR_MODE_SWITCHING \
2189 { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2191 /* ENTITY is an integer specifying a mode-switched entity. If
2192 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2193 return an integer value not larger than the corresponding element
2194 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2195 must be switched into prior to the execution of INSN. */
2197 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2199 /* If this macro is defined, it is evaluated for every INSN during
2200 mode switching. It determines the mode that an insn results in (if
2201 different from the incoming mode). */
2203 #define MODE_AFTER(ENTITY, MODE, I) ix86_mode_after ((ENTITY), (MODE), (I))
2205 /* If this macro is defined, it is evaluated for every ENTITY that
2206 needs mode switching. It should evaluate to an integer, which is
2207 a mode that ENTITY is assumed to be switched to at function entry. */
2209 #define MODE_ENTRY(ENTITY) ix86_mode_entry (ENTITY)
2211 /* If this macro is defined, it is evaluated for every ENTITY that
2212 needs mode switching. It should evaluate to an integer, which is
2213 a mode that ENTITY is assumed to be switched to at function exit. */
2215 #define MODE_EXIT(ENTITY) ix86_mode_exit (ENTITY)
2217 /* This macro specifies the order in which modes for ENTITY are
2218 processed. 0 is the highest priority. */
2220 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2222 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2223 is the set of hard registers live at the point where the insn(s)
2224 are to be inserted. */
2226 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2227 ix86_emit_mode_set ((ENTITY), (MODE), (HARD_REGS_LIVE))
2229 /* Avoid renaming of stack registers, as doing so in combination with
2230 scheduling just increases amount of live registers at time and in
2231 the turn amount of fxch instructions needed.
2233 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2235 #define HARD_REGNO_RENAME_OK(SRC, TARGET) !STACK_REGNO_P (SRC)
2238 #define FASTCALL_PREFIX '@'
2240 /* Machine specific frame tracking during prologue/epilogue generation. */
2242 #ifndef USED_FOR_TARGET
2243 struct GTY(()) machine_frame_state
2245 /* This pair tracks the currently active CFA as reg+offset. When reg
2246 is drap_reg, we don't bother trying to record here the real CFA when
2247 it might really be a DW_CFA_def_cfa_expression. */
2249 HOST_WIDE_INT cfa_offset
;
2251 /* The current offset (canonically from the CFA) of ESP and EBP.
2252 When stack frame re-alignment is active, these may not be relative
2253 to the CFA. However, in all cases they are relative to the offsets
2254 of the saved registers stored in ix86_frame. */
2255 HOST_WIDE_INT sp_offset
;
2256 HOST_WIDE_INT fp_offset
;
2258 /* The size of the red-zone that may be assumed for the purposes of
2259 eliding register restore notes in the epilogue. This may be zero
2260 if no red-zone is in effect, or may be reduced from the real
2261 red-zone value by a maximum runtime stack re-alignment value. */
2262 int red_zone_offset
;
2264 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2265 value within the frame. If false then the offset above should be
2266 ignored. Note that DRAP, if valid, *always* points to the CFA and
2267 thus has an offset of zero. */
2268 BOOL_BITFIELD sp_valid
: 1;
2269 BOOL_BITFIELD fp_valid
: 1;
2270 BOOL_BITFIELD drap_valid
: 1;
2272 /* Indicate whether the local stack frame has been re-aligned. When
2273 set, the SP/FP offsets above are relative to the aligned frame
2275 BOOL_BITFIELD realigned
: 1;
2278 /* Private to winnt.c. */
2279 struct seh_frame_state
;
2281 struct GTY(()) machine_function
{
2282 struct stack_local_entry
*stack_locals
;
2283 const char *some_ld_name
;
2284 int varargs_gpr_size
;
2285 int varargs_fpr_size
;
2286 int optimize_mode_switching
[MAX_386_ENTITIES
];
2288 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
2289 has been computed for. */
2290 int use_fast_prologue_epilogue_nregs
;
2292 /* For -fsplit-stack support: A stack local which holds a pointer to
2293 the stack arguments for a function with a variable number of
2294 arguments. This is set at the start of the function and is used
2295 to initialize the overflow_arg_area field of the va_list
2297 rtx split_stack_varargs_pointer
;
2299 /* This value is used for amd64 targets and specifies the current abi
2300 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2301 ENUM_BITFIELD(calling_abi
) call_abi
: 8;
2303 /* Nonzero if the function accesses a previous frame. */
2304 BOOL_BITFIELD accesses_prev_frame
: 1;
2306 /* Nonzero if the function requires a CLD in the prologue. */
2307 BOOL_BITFIELD needs_cld
: 1;
2309 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2310 expander to determine the style used. */
2311 BOOL_BITFIELD use_fast_prologue_epilogue
: 1;
2313 /* If true, the current function needs the default PIC register, not
2314 an alternate register (on x86) and must not use the red zone (on
2315 x86_64), even if it's a leaf function. We don't want the
2316 function to be regarded as non-leaf because TLS calls need not
2317 affect register allocation. This flag is set when a TLS call
2318 instruction is expanded within a function, and never reset, even
2319 if all such instructions are optimized away. Use the
2320 ix86_current_function_calls_tls_descriptor macro for a better
2322 BOOL_BITFIELD tls_descriptor_call_expanded_p
: 1;
2324 /* If true, the current function has a STATIC_CHAIN is placed on the
2325 stack below the return address. */
2326 BOOL_BITFIELD static_chain_on_stack
: 1;
2328 /* During prologue/epilogue generation, the current frame state.
2329 Otherwise, the frame state at the end of the prologue. */
2330 struct machine_frame_state fs
;
2332 /* During SEH output, this is non-null. */
2333 struct seh_frame_state
* GTY((skip(""))) seh
;
2337 #define ix86_stack_locals (cfun->machine->stack_locals)
2338 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2339 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2340 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2341 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2342 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2343 (cfun->machine->tls_descriptor_call_expanded_p)
2344 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2345 calls are optimized away, we try to detect cases in which it was
2346 optimized away. Since such instructions (use (reg REG_SP)), we can
2347 verify whether there's any such instruction live by testing that
2349 #define ix86_current_function_calls_tls_descriptor \
2350 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2351 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2353 /* Control behavior of x86_file_start. */
2354 #define X86_FILE_START_VERSION_DIRECTIVE false
2355 #define X86_FILE_START_FLTUSED false
2357 /* Flag to mark data that is in the large address area. */
2358 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2359 #define SYMBOL_REF_FAR_ADDR_P(X) \
2360 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2362 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2363 have defined always, to avoid ifdefing. */
2364 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2365 #define SYMBOL_REF_DLLIMPORT_P(X) \
2366 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2368 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2369 #define SYMBOL_REF_DLLEXPORT_P(X) \
2370 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2372 extern void debug_ready_dispatch (void);
2373 extern void debug_dispatch_window (int);
2375 /* The value at zero is only defined for the BMI instructions
2376 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2377 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2378 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
2379 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2380 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT)
2383 /* Flags returned by ix86_get_callcvt (). */
2384 #define IX86_CALLCVT_CDECL 0x1
2385 #define IX86_CALLCVT_STDCALL 0x2
2386 #define IX86_CALLCVT_FASTCALL 0x4
2387 #define IX86_CALLCVT_THISCALL 0x8
2388 #define IX86_CALLCVT_REGPARM 0x10
2389 #define IX86_CALLCVT_SSEREGPARM 0x20
2391 #define IX86_BASE_CALLCVT(FLAGS) \
2392 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2393 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2395 #define RECIP_MASK_NONE 0x00
2396 #define RECIP_MASK_DIV 0x01
2397 #define RECIP_MASK_SQRT 0x02
2398 #define RECIP_MASK_VEC_DIV 0x04
2399 #define RECIP_MASK_VEC_SQRT 0x08
2400 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2401 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2402 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2404 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2405 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2406 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2407 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2409 #define IX86_HLE_ACQUIRE (1 << 16)
2410 #define IX86_HLE_RELEASE (1 << 17)