1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
77 ;; For SSE/MMX support:
78 ;; 30 This is `fix', guaranteed to be truncating.
79 ;; 31 This is a `emms' operation.
80 ;; 32 This is a `maskmov' operation.
81 ;; 33 This is a `movmsk' operation.
82 ;; 34 This is a `non-temporal' move.
83 ;; 35 This is a `prefetch' operation.
84 ;; 36 This is used to distinguish COMISS from UCOMISS.
85 ;; 37 This is a `ldmxcsr' operation.
86 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
87 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
88 ;; 40 This is a `stmxcsr' operation.
89 ;; 41 This is a `shuffle' operation.
90 ;; 42 This is a `rcp' operation.
91 ;; 43 This is a `rsqsrt' operation.
92 ;; 44 This is a `sfence' operation.
93 ;; 45 This is a noop to prevent excessive combiner cleverness.
95 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
99 ;; Processor type. This attribute must exactly match the processor_type
100 ;; enumeration in i386.h.
101 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
102 (const (symbol_ref "ix86_cpu")))
104 ;; A basic instruction type. Refinements due to arguments to be
105 ;; provided in other attributes.
107 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx"
108 (const_string "other"))
110 ;; Main data type used by the insn
111 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
112 (const_string "unknown"))
114 ;; Set for i387 operations.
115 (define_attr "i387" ""
116 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
120 ;; The (bounding maximum) length of an instruction immediate.
121 (define_attr "length_immediate" ""
122 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
126 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
127 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
128 (eq_attr "type" "imov,test")
129 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
130 (eq_attr "type" "call")
131 (if_then_else (match_operand 0 "constant_call_address_operand" "")
134 (eq_attr "type" "callv")
135 (if_then_else (match_operand 1 "constant_call_address_operand" "")
138 (eq_attr "type" "ibr")
139 (if_then_else (and (ge (minus (match_dup 0) (pc))
141 (lt (minus (match_dup 0) (pc))
146 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
148 ;; The (bounding maximum) length of an instruction address.
149 (define_attr "length_address" ""
150 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
152 (and (eq_attr "type" "call")
153 (match_operand 1 "constant_call_address_operand" ""))
155 (and (eq_attr "type" "callv")
156 (match_operand 1 "constant_call_address_operand" ""))
159 (symbol_ref "ix86_attr_length_address_default (insn)")))
161 ;; Set when length prefix is used.
162 (define_attr "prefix_data16" ""
163 (if_then_else (eq_attr "mode" "HI")
167 ;; Set when string REP prefix is used.
168 (define_attr "prefix_rep" "" (const_int 0))
170 ;; Set when 0f opcode prefix is used.
171 (define_attr "prefix_0f" ""
172 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
176 ;; Set when modrm byte is used.
177 (define_attr "modrm" ""
178 (cond [(eq_attr "type" "str,cld")
182 (and (eq_attr "type" "incdec")
183 (ior (match_operand:SI 1 "register_operand" "")
184 (match_operand:HI 1 "register_operand" "")))
186 (and (eq_attr "type" "push")
187 (not (match_operand 1 "memory_operand" "")))
189 (and (eq_attr "type" "pop")
190 (not (match_operand 0 "memory_operand" "")))
192 (and (eq_attr "type" "imov")
193 (and (match_operand 0 "register_operand" "")
194 (match_operand 1 "immediate_operand" "")))
199 ;; The (bounding maximum) length of an instruction in bytes.
200 (define_attr "length" ""
201 (cond [(eq_attr "type" "other,multi")
204 (plus (plus (attr "modrm")
205 (plus (attr "prefix_0f")
208 (plus (attr "prefix_rep")
209 (plus (attr "prefix_data16")
210 (plus (attr "length_immediate")
211 (attr "length_address")))))))
213 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
214 ;; `store' if there is a simple memory reference therein, or `unknown'
215 ;; if the instruction is complex.
217 (define_attr "memory" "none,load,store,both,unknown"
218 (cond [(eq_attr "type" "other,multi,str")
219 (const_string "unknown")
220 (eq_attr "type" "lea,fcmov,fpspc,cld")
221 (const_string "none")
222 (eq_attr "type" "push")
223 (if_then_else (match_operand 1 "memory_operand" "")
224 (const_string "both")
225 (const_string "store"))
226 (eq_attr "type" "pop,setcc")
227 (if_then_else (match_operand 0 "memory_operand" "")
228 (const_string "both")
229 (const_string "load"))
230 (eq_attr "type" "icmp,test")
231 (if_then_else (ior (match_operand 0 "memory_operand" "")
232 (match_operand 1 "memory_operand" ""))
233 (const_string "load")
234 (const_string "none"))
235 (eq_attr "type" "ibr")
236 (if_then_else (match_operand 0 "memory_operand" "")
237 (const_string "load")
238 (const_string "none"))
239 (eq_attr "type" "call")
240 (if_then_else (match_operand 0 "constant_call_address_operand" "")
241 (const_string "none")
242 (const_string "load"))
243 (eq_attr "type" "callv")
244 (if_then_else (match_operand 1 "constant_call_address_operand" "")
245 (const_string "none")
246 (const_string "load"))
247 (and (eq_attr "type" "alu1,negnot")
248 (match_operand 1 "memory_operand" ""))
249 (const_string "both")
250 (and (match_operand 0 "memory_operand" "")
251 (match_operand 1 "memory_operand" ""))
252 (const_string "both")
253 (match_operand 0 "memory_operand" "")
254 (const_string "store")
255 (match_operand 1 "memory_operand" "")
256 (const_string "load")
257 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
258 (match_operand 2 "memory_operand" ""))
259 (const_string "load")
260 (and (eq_attr "type" "icmov")
261 (match_operand 3 "memory_operand" ""))
262 (const_string "load")
264 (const_string "none")))
266 ;; Indicates if an instruction has both an immediate and a displacement.
268 (define_attr "imm_disp" "false,true,unknown"
269 (cond [(eq_attr "type" "other,multi")
270 (const_string "unknown")
271 (and (eq_attr "type" "icmp,test,imov")
272 (and (match_operand 0 "memory_displacement_operand" "")
273 (match_operand 1 "immediate_operand" "")))
274 (const_string "true")
275 (and (eq_attr "type" "alu,ishift,imul,idiv")
276 (and (match_operand 0 "memory_displacement_operand" "")
277 (match_operand 2 "immediate_operand" "")))
278 (const_string "true")
280 (const_string "false")))
282 ;; Indicates if an FP operation has an integer source.
284 (define_attr "fp_int_src" "false,true"
285 (const_string "false"))
287 ;; Describe a user's asm statement.
288 (define_asm_attributes
289 [(set_attr "length" "128")
290 (set_attr "type" "multi")])
292 ;; Pentium Scheduling
294 ;; The Pentium is an in-order core with two integer pipelines.
296 ;; True for insns that behave like prefixed insns on the Pentium.
297 (define_attr "pent_prefix" "false,true"
298 (if_then_else (ior (eq_attr "prefix_0f" "1")
299 (ior (eq_attr "prefix_data16" "1")
300 (eq_attr "prefix_rep" "1")))
301 (const_string "true")
302 (const_string "false")))
304 ;; Categorize how an instruction slots.
306 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
307 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
308 ;; rules, because it results in noticeably better code on non-MMX Pentium
309 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
310 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
312 (define_attr "pent_pair" "uv,pu,pv,np"
313 (cond [(eq_attr "imm_disp" "true")
315 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
316 (and (eq_attr "type" "pop,push")
317 (eq_attr "memory" "!both")))
318 (if_then_else (eq_attr "pent_prefix" "true")
321 (eq_attr "type" "ibr")
323 (and (eq_attr "type" "ishift")
324 (match_operand 2 "const_int_operand" ""))
326 (and (eq_attr "type" "call")
327 (match_operand 0 "constant_call_address_operand" ""))
329 (and (eq_attr "type" "callv")
330 (match_operand 1 "constant_call_address_operand" ""))
333 (const_string "np")))
335 ;; Rough readiness numbers. Fine tuning happens in i386.c.
337 ;; u describes pipe U
338 ;; v describes pipe V
339 ;; uv describes either pipe U or V for those that can issue to either
340 ;; np describes not paring
342 ;; fpm describes fp insns of different types are not pipelined.
344 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
346 (define_function_unit "pent_np" 1 0
347 (and (eq_attr "cpu" "pentium")
348 (eq_attr "type" "imul"))
351 (define_function_unit "pent_mul" 1 1
352 (and (eq_attr "cpu" "pentium")
353 (eq_attr "type" "imul"))
356 ;; Rep movs takes minimally 12 cycles.
357 (define_function_unit "pent_np" 1 0
358 (and (eq_attr "cpu" "pentium")
359 (eq_attr "type" "str"))
362 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
363 (define_function_unit "pent_np" 1 0
364 (and (eq_attr "cpu" "pentium")
365 (eq_attr "type" "idiv"))
368 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
369 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
370 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
371 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
372 ; like normal fp operation and fist takes 6 cycles.
374 (define_function_unit "fpu" 1 0
375 (and (eq_attr "cpu" "pentium")
376 (and (eq_attr "type" "fmov")
377 (and (eq_attr "memory" "load,store")
378 (eq_attr "mode" "XF"))))
381 (define_function_unit "pent_np" 1 0
382 (and (eq_attr "cpu" "pentium")
383 (and (eq_attr "type" "fmov")
384 (and (eq_attr "memory" "load,store")
385 (eq_attr "mode" "XF"))))
388 (define_function_unit "fpu" 1 0
389 (and (eq_attr "cpu" "pentium")
390 (and (eq_attr "type" "fmov")
391 (ior (match_operand 1 "immediate_operand" "")
392 (eq_attr "memory" "store"))))
395 (define_function_unit "pent_np" 1 0
396 (and (eq_attr "cpu" "pentium")
397 (and (eq_attr "type" "fmov")
398 (ior (match_operand 1 "immediate_operand" "")
399 (eq_attr "memory" "store"))))
402 (define_function_unit "pent_np" 1 0
403 (and (eq_attr "cpu" "pentium")
404 (eq_attr "type" "cld"))
407 (define_function_unit "fpu" 1 0
408 (and (eq_attr "cpu" "pentium")
409 (and (eq_attr "type" "fmov")
410 (eq_attr "memory" "none,load")))
413 ; Read/Modify/Write instructions usually take 3 cycles.
414 (define_function_unit "pent_u" 1 0
415 (and (eq_attr "cpu" "pentium")
416 (and (eq_attr "type" "alu,alu1,ishift")
417 (and (eq_attr "pent_pair" "pu")
418 (eq_attr "memory" "both"))))
421 (define_function_unit "pent_uv" 2 0
422 (and (eq_attr "cpu" "pentium")
423 (and (eq_attr "type" "alu,alu1,ishift")
424 (and (eq_attr "pent_pair" "!np")
425 (eq_attr "memory" "both"))))
428 (define_function_unit "pent_np" 1 0
429 (and (eq_attr "cpu" "pentium")
430 (and (eq_attr "type" "alu,alu1,negnot,ishift")
431 (and (eq_attr "pent_pair" "np")
432 (eq_attr "memory" "both"))))
435 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
436 (define_function_unit "pent_u" 1 0
437 (and (eq_attr "cpu" "pentium")
438 (and (eq_attr "type" "alu,ishift")
439 (and (eq_attr "pent_pair" "pu")
440 (eq_attr "memory" "load,store"))))
443 (define_function_unit "pent_uv" 2 0
444 (and (eq_attr "cpu" "pentium")
445 (and (eq_attr "type" "alu,ishift")
446 (and (eq_attr "pent_pair" "!np")
447 (eq_attr "memory" "load,store"))))
450 (define_function_unit "pent_np" 1 0
451 (and (eq_attr "cpu" "pentium")
452 (and (eq_attr "type" "alu,ishift")
453 (and (eq_attr "pent_pair" "np")
454 (eq_attr "memory" "load,store"))))
457 ; Insns w/o memory operands and move instructions usually take one cycle.
458 (define_function_unit "pent_u" 1 0
459 (and (eq_attr "cpu" "pentium")
460 (eq_attr "pent_pair" "pu"))
463 (define_function_unit "pent_v" 1 0
464 (and (eq_attr "cpu" "pentium")
465 (eq_attr "pent_pair" "pv"))
468 (define_function_unit "pent_uv" 2 0
469 (and (eq_attr "cpu" "pentium")
470 (eq_attr "pent_pair" "!np"))
473 (define_function_unit "pent_np" 1 0
474 (and (eq_attr "cpu" "pentium")
475 (eq_attr "pent_pair" "np"))
478 ; Pairable insns only conflict with other non-pairable insns.
479 (define_function_unit "pent_np" 1 0
480 (and (eq_attr "cpu" "pentium")
481 (and (eq_attr "type" "alu,alu1,ishift")
482 (and (eq_attr "pent_pair" "!np")
483 (eq_attr "memory" "both"))))
485 [(eq_attr "pent_pair" "np")])
487 (define_function_unit "pent_np" 1 0
488 (and (eq_attr "cpu" "pentium")
489 (and (eq_attr "type" "alu,alu1,ishift")
490 (and (eq_attr "pent_pair" "!np")
491 (eq_attr "memory" "load,store"))))
493 [(eq_attr "pent_pair" "np")])
495 (define_function_unit "pent_np" 1 0
496 (and (eq_attr "cpu" "pentium")
497 (eq_attr "pent_pair" "!np"))
499 [(eq_attr "pent_pair" "np")])
501 ; Floating point instructions usually blocks cycle longer when combined with
502 ; integer instructions, because of the inpaired fxch instruction.
503 (define_function_unit "pent_np" 1 0
504 (and (eq_attr "cpu" "pentium")
505 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp"))
507 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp")])
509 (define_function_unit "fpu" 1 0
510 (and (eq_attr "cpu" "pentium")
511 (eq_attr "type" "fcmp,fxch,fsgn"))
514 ; Addition takes 3 cycles; assume other random cruft does as well.
515 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
516 (define_function_unit "fpu" 1 0
517 (and (eq_attr "cpu" "pentium")
518 (eq_attr "type" "fop,fop1"))
521 ; Multiplication takes 3 cycles and is only half pipelined.
522 (define_function_unit "fpu" 1 0
523 (and (eq_attr "cpu" "pentium")
524 (eq_attr "type" "fmul"))
527 (define_function_unit "pent_mul" 1 1
528 (and (eq_attr "cpu" "pentium")
529 (eq_attr "type" "fmul"))
532 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
533 ; They can overlap with integer insns. Only the last two cycles can overlap
534 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
535 ; Only last two cycles of fsin/fcos can overlap with other instructions.
536 (define_function_unit "fpu" 1 0
537 (and (eq_attr "cpu" "pentium")
538 (eq_attr "type" "fdiv"))
541 (define_function_unit "pent_mul" 1 1
542 (and (eq_attr "cpu" "pentium")
543 (eq_attr "type" "fdiv"))
546 (define_function_unit "fpu" 1 0
547 (and (eq_attr "cpu" "pentium")
548 (eq_attr "type" "fpspc"))
551 (define_function_unit "pent_mul" 1 1
552 (and (eq_attr "cpu" "pentium")
553 (eq_attr "type" "fpspc"))
556 ;; Pentium Pro/PII Scheduling
558 ;; The PPro has an out-of-order core, but the instruction decoders are
559 ;; naturally in-order and asymmetric. We get best performance by scheduling
560 ;; for the decoders, for in doing so we give the oo execution unit the
563 ;; Categorize how many uops an ia32 instruction evaluates to:
564 ;; one -- an instruction with 1 uop can be decoded by any of the
566 ;; few -- an instruction with 1 to 4 uops can be decoded only by
568 ;; many -- a complex instruction may take an unspecified number of
569 ;; cycles to decode in decoder 0.
571 (define_attr "ppro_uops" "one,few,many"
572 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
573 (const_string "many")
574 (eq_attr "type" "icmov,fcmov,str,cld")
576 (eq_attr "type" "imov")
577 (if_then_else (eq_attr "memory" "store,both")
579 (const_string "one"))
580 (eq_attr "memory" "!none")
583 (const_string "one")))
585 ;; Rough readiness numbers. Fine tuning happens in i386.c.
587 ;; p0 describes port 0.
588 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
589 ;; p2 describes port 2 for loads.
590 ;; p34 describes ports 3 and 4 for stores.
591 ;; fpu describes the fpu accessed via port 0.
592 ;; ??? It is less than clear if there are separate fadd and fmul units
593 ;; that could operate in parallel.
595 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
597 (define_function_unit "ppro_p0" 1 0
598 (and (eq_attr "cpu" "pentiumpro")
599 (eq_attr "type" "ishift,lea,ibr,cld"))
602 (define_function_unit "ppro_p0" 1 0
603 (and (eq_attr "cpu" "pentiumpro")
604 (eq_attr "type" "imul"))
607 ;; ??? Does the divider lock out the pipe while it works,
608 ;; or is there a disconnected unit?
609 (define_function_unit "ppro_p0" 1 0
610 (and (eq_attr "cpu" "pentiumpro")
611 (eq_attr "type" "idiv"))
614 (define_function_unit "ppro_p0" 1 0
615 (and (eq_attr "cpu" "pentiumpro")
616 (eq_attr "type" "fop,fop1,fsgn"))
619 (define_function_unit "ppro_p0" 1 0
620 (and (eq_attr "cpu" "pentiumpro")
621 (eq_attr "type" "fcmov"))
624 (define_function_unit "ppro_p0" 1 0
625 (and (eq_attr "cpu" "pentiumpro")
626 (eq_attr "type" "fcmp"))
629 (define_function_unit "ppro_p0" 1 0
630 (and (eq_attr "cpu" "pentiumpro")
631 (eq_attr "type" "fmov"))
634 (define_function_unit "ppro_p0" 1 0
635 (and (eq_attr "cpu" "pentiumpro")
636 (eq_attr "type" "fmul"))
639 (define_function_unit "ppro_p0" 1 0
640 (and (eq_attr "cpu" "pentiumpro")
641 (eq_attr "type" "fdiv,fpspc"))
644 (define_function_unit "ppro_p01" 2 0
645 (and (eq_attr "cpu" "pentiumpro")
646 (eq_attr "type" "!imov,fmov"))
649 (define_function_unit "ppro_p01" 2 0
650 (and (and (eq_attr "cpu" "pentiumpro")
651 (eq_attr "type" "imov,fmov"))
652 (eq_attr "memory" "none"))
655 (define_function_unit "ppro_p2" 1 0
656 (and (eq_attr "cpu" "pentiumpro")
657 (ior (eq_attr "type" "pop")
658 (eq_attr "memory" "load,both")))
661 (define_function_unit "ppro_p34" 1 0
662 (and (eq_attr "cpu" "pentiumpro")
663 (ior (eq_attr "type" "push")
664 (eq_attr "memory" "store,both")))
667 (define_function_unit "fpu" 1 0
668 (and (eq_attr "cpu" "pentiumpro")
669 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov"))
672 (define_function_unit "fpu" 1 0
673 (and (eq_attr "cpu" "pentiumpro")
674 (eq_attr "type" "fmul"))
677 (define_function_unit "fpu" 1 0
678 (and (eq_attr "cpu" "pentiumpro")
679 (eq_attr "type" "fdiv,fpspc"))
682 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
683 (define_function_unit "fpu" 1 0
684 (and (eq_attr "cpu" "pentiumpro")
685 (eq_attr "type" "imul"))
688 ;; AMD K6/K6-2 Scheduling
690 ;; The K6 has similar architecture to PPro. Important difference is, that
691 ;; there are only two decoders and they seems to be much slower than execution
692 ;; units. So we have to pay much more attention to proper decoding for
693 ;; schedulers. We share most of scheduler code for PPro in i386.c
695 ;; The fp unit is not pipelined and do one operation per two cycles including
698 ;; alu describes both ALU units (ALU-X and ALU-Y).
699 ;; alux describes X alu unit
700 ;; fpu describes FPU unit
701 ;; load describes load unit.
702 ;; branch describes branch unit.
703 ;; store decsribes store unit. This unit is not modelled completely and only
704 ;; used to model lea operation. Otherwise it lie outside of the critical
707 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
709 ;; The decoder specification is in the PPro section above!
711 ;; Shift instructions and certain arithmetic are issued only to X pipe.
712 (define_function_unit "k6_alux" 1 0
713 (and (eq_attr "cpu" "k6")
714 (eq_attr "type" "ishift,alu1,negnot,cld"))
717 ;; The QI mode arithmetic is issued to X pipe only.
718 (define_function_unit "k6_alux" 1 0
719 (and (eq_attr "cpu" "k6")
720 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
721 (match_operand:QI 0 "general_operand" "")))
724 (define_function_unit "k6_alu" 2 0
725 (and (eq_attr "cpu" "k6")
726 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
729 (define_function_unit "k6_alu" 2 0
730 (and (eq_attr "cpu" "k6")
731 (and (eq_attr "type" "imov")
732 (eq_attr "memory" "none")))
735 (define_function_unit "k6_branch" 1 0
736 (and (eq_attr "cpu" "k6")
737 (eq_attr "type" "call,callv,ibr"))
740 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
741 (define_function_unit "k6_load" 1 0
742 (and (eq_attr "cpu" "k6")
743 (ior (eq_attr "type" "pop")
744 (eq_attr "memory" "load,both")))
747 (define_function_unit "k6_load" 1 0
748 (and (eq_attr "cpu" "k6")
749 (and (eq_attr "type" "str")
750 (eq_attr "memory" "load,both")))
753 ;; Lea have two instructions, so latency is probably 2
754 (define_function_unit "k6_store" 1 0
755 (and (eq_attr "cpu" "k6")
756 (eq_attr "type" "lea"))
759 (define_function_unit "k6_store" 1 0
760 (and (eq_attr "cpu" "k6")
761 (eq_attr "type" "str"))
764 (define_function_unit "k6_store" 1 0
765 (and (eq_attr "cpu" "k6")
766 (ior (eq_attr "type" "push")
767 (eq_attr "memory" "store,both")))
770 (define_function_unit "k6_fpu" 1 1
771 (and (eq_attr "cpu" "k6")
772 (eq_attr "type" "fop,fop1,fmov,fcmp"))
775 (define_function_unit "k6_fpu" 1 1
776 (and (eq_attr "cpu" "k6")
777 (eq_attr "type" "fmul"))
781 (define_function_unit "k6_fpu" 1 1
782 (and (eq_attr "cpu" "k6")
783 (eq_attr "type" "fdiv,fpspc"))
786 (define_function_unit "k6_alu" 2 0
787 (and (eq_attr "cpu" "k6")
788 (eq_attr "type" "imul"))
791 (define_function_unit "k6_alux" 1 0
792 (and (eq_attr "cpu" "k6")
793 (eq_attr "type" "imul"))
797 (define_function_unit "k6_alu" 2 0
798 (and (eq_attr "cpu" "k6")
799 (eq_attr "type" "idiv"))
802 (define_function_unit "k6_alux" 1 0
803 (and (eq_attr "cpu" "k6")
804 (eq_attr "type" "idiv"))
807 ;; AMD Athlon Scheduling
809 ;; The Athlon does contain three pipelined FP units, three integer units and
810 ;; three address generation units.
812 ;; The predecode logic is determining boundaries of instructions in the 64
813 ;; byte cache line. So the cache line straddling problem of K6 might be issue
814 ;; here as well, but it is not noted in the documentation.
816 ;; Three DirectPath instructions decoders and only one VectorPath decoder
817 ;; is available. They can decode three DirectPath instructions or one VectorPath
818 ;; instruction per cycle.
819 ;; Decoded macro instructions are then passed to 72 entry instruction control
821 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
823 ;; The load/store queue unit is not attached to the schedulers but
824 ;; communicates with all the execution units seperately instead.
826 (define_attr "athlon_decode" "direct,vector"
827 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
828 (const_string "vector")
829 (and (eq_attr "type" "push")
830 (match_operand 1 "memory_operand" ""))
831 (const_string "vector")
832 (and (eq_attr "type" "fmov")
833 (and (eq_attr "memory" "load,store")
834 (eq_attr "mode" "XF")))
835 (const_string "vector")]
836 (const_string "direct")))
838 (define_function_unit "athlon_vectordec" 1 0
839 (and (eq_attr "cpu" "athlon")
840 (eq_attr "athlon_decode" "vector"))
843 (define_function_unit "athlon_directdec" 3 0
844 (and (eq_attr "cpu" "athlon")
845 (eq_attr "athlon_decode" "direct"))
848 (define_function_unit "athlon_vectordec" 1 0
849 (and (eq_attr "cpu" "athlon")
850 (eq_attr "athlon_decode" "direct"))
851 1 1 [(eq_attr "athlon_decode" "vector")])
853 (define_function_unit "athlon_ieu" 3 0
854 (and (eq_attr "cpu" "athlon")
855 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
858 (define_function_unit "athlon_ieu" 3 0
859 (and (eq_attr "cpu" "athlon")
860 (eq_attr "type" "str"))
863 (define_function_unit "athlon_ieu" 3 0
864 (and (eq_attr "cpu" "athlon")
865 (eq_attr "type" "imul"))
868 (define_function_unit "athlon_ieu" 3 0
869 (and (eq_attr "cpu" "athlon")
870 (eq_attr "type" "idiv"))
873 (define_function_unit "athlon_muldiv" 1 0
874 (and (eq_attr "cpu" "athlon")
875 (eq_attr "type" "imul"))
878 (define_function_unit "athlon_muldiv" 1 0
879 (and (eq_attr "cpu" "athlon")
880 (eq_attr "type" "idiv"))
883 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
884 (cond [(eq_attr "type" "fop,fop1,fcmp")
886 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
888 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
889 (const_string "store")
890 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
892 (and (eq_attr "type" "fmov")
893 (ior (match_operand:SI 1 "register_operand" "")
894 (match_operand 1 "immediate_operand" "")))
895 (const_string "store")
896 (eq_attr "type" "fmov")
897 (const_string "muladd")]
898 (const_string "none")))
900 ;; We use latencies 1 for definitions. This is OK to model colisions
901 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
903 ;; fsin, fcos: 96-192
905 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
906 (define_function_unit "athlon_fp" 3 0
907 (and (eq_attr "cpu" "athlon")
908 (eq_attr "type" "fpspc"))
911 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
912 (define_function_unit "athlon_fp" 3 0
913 (and (eq_attr "cpu" "athlon")
914 (eq_attr "type" "fdiv"))
917 (define_function_unit "athlon_fp" 3 0
918 (and (eq_attr "cpu" "athlon")
919 (eq_attr "type" "fop,fop1,fmul"))
922 ;; XFmode loads are slow.
923 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
924 ;; there are no dependent instructions.
926 (define_function_unit "athlon_fp" 3 0
927 (and (eq_attr "cpu" "athlon")
928 (and (eq_attr "type" "fmov")
929 (and (eq_attr "memory" "load")
930 (eq_attr "mode" "XF"))))
933 (define_function_unit "athlon_fp" 3 0
934 (and (eq_attr "cpu" "athlon")
935 (eq_attr "type" "fmov,fsgn"))
938 ;; fcmp and ftst instructions
939 (define_function_unit "athlon_fp" 3 0
940 (and (eq_attr "cpu" "athlon")
941 (and (eq_attr "type" "fcmp")
942 (eq_attr "athlon_decode" "direct")))
945 ;; fcmpi instructions.
946 (define_function_unit "athlon_fp" 3 0
947 (and (eq_attr "cpu" "athlon")
948 (and (eq_attr "type" "fcmp")
949 (eq_attr "athlon_decode" "vector")))
952 (define_function_unit "athlon_fp" 3 0
953 (and (eq_attr "cpu" "athlon")
954 (eq_attr "type" "fcmov"))
957 (define_function_unit "athlon_fp_mul" 1 0
958 (and (eq_attr "cpu" "athlon")
959 (eq_attr "athlon_fpunits" "mul"))
962 (define_function_unit "athlon_fp_add" 1 0
963 (and (eq_attr "cpu" "athlon")
964 (eq_attr "athlon_fpunits" "add"))
967 (define_function_unit "athlon_fp_muladd" 2 0
968 (and (eq_attr "cpu" "athlon")
969 (eq_attr "athlon_fpunits" "muladd,mul,add"))
972 (define_function_unit "athlon_fp_store" 1 0
973 (and (eq_attr "cpu" "athlon")
974 (eq_attr "athlon_fpunits" "store"))
977 ;; We don't need to model the Adress Generation Unit, since we don't model
978 ;; the re-order buffer yet and thus we never schedule more than three operations
979 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
980 ;; decoders independently on the functional units.
982 ;(define_function_unit "athlon_agu" 3 0
983 ; (and (eq_attr "cpu" "athlon")
984 ; (and (eq_attr "memory" "!none")
985 ; (eq_attr "athlon_fpunits" "none")))
988 ;; Model load unit to avoid too long sequences of loads. We don't need to
989 ;; model store queue, since it is hardly going to be bottleneck.
991 (define_function_unit "athlon_load" 2 0
992 (and (eq_attr "cpu" "athlon")
993 (eq_attr "memory" "load,both"))
997 ;; Compare instructions.
999 ;; All compare insns have expanders that save the operands away without
1000 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1001 ;; after the cmp) will actually emit the cmpM.
1003 (define_expand "cmpdi"
1005 (compare:CC (match_operand:DI 0 "general_operand" "")
1006 (match_operand:DI 1 "general_operand" "")))]
1010 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1011 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1012 operands[0] = force_reg (DImode, operands[0]);
1013 ix86_compare_op0 = operands[0];
1014 ix86_compare_op1 = operands[1];
1018 (define_expand "cmpsi"
1020 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1021 (match_operand:SI 1 "general_operand" "")))]
1025 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1026 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1027 operands[0] = force_reg (SImode, operands[0]);
1028 ix86_compare_op0 = operands[0];
1029 ix86_compare_op1 = operands[1];
1033 (define_expand "cmphi"
1035 (compare:CC (match_operand:HI 0 "general_operand" "")
1036 (match_operand:HI 1 "general_operand" "")))]
1040 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1041 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1042 operands[0] = force_reg (HImode, operands[0]);
1043 ix86_compare_op0 = operands[0];
1044 ix86_compare_op1 = operands[1];
1048 (define_expand "cmpqi"
1050 (compare:CC (match_operand:QI 0 "general_operand" "")
1051 (match_operand:QI 1 "general_operand" "")))]
1052 "TARGET_QIMODE_MATH"
1055 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1056 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1057 operands[0] = force_reg (QImode, operands[0]);
1058 ix86_compare_op0 = operands[0];
1059 ix86_compare_op1 = operands[1];
1063 (define_insn "*cmpsi_ccno_1"
1065 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1066 (match_operand:SI 1 "const0_operand" "n,n")))]
1067 "ix86_match_ccmode (insn, CCNOmode)"
1069 test{l}\\t{%0, %0|%0, %0}
1070 cmp{l}\\t{%1, %0|%0, %1}"
1071 [(set_attr "type" "test,icmp")
1072 (set_attr "length_immediate" "0,1")
1073 (set_attr "mode" "SI")])
1075 (define_insn "*cmpsi_minus_1"
1077 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1078 (match_operand:SI 1 "general_operand" "ri,mr"))
1080 "ix86_match_ccmode (insn, CCGOCmode)"
1081 "cmp{l}\\t{%1, %0|%0, %1}"
1082 [(set_attr "type" "icmp")
1083 (set_attr "mode" "SI")])
1085 (define_expand "cmpsi_1"
1087 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1088 (match_operand:SI 1 "general_operand" "ri,mr")))]
1092 (define_insn "*cmpsi_1_insn"
1094 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1095 (match_operand:SI 1 "general_operand" "ri,mr")))]
1096 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1097 && ix86_match_ccmode (insn, CCmode)"
1098 "cmp{l}\\t{%1, %0|%0, %1}"
1099 [(set_attr "type" "icmp")
1100 (set_attr "mode" "SI")])
1102 (define_insn "*cmphi_ccno_1"
1104 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1105 (match_operand:HI 1 "const0_operand" "n,n")))]
1106 "ix86_match_ccmode (insn, CCNOmode)"
1108 test{w}\\t{%0, %0|%0, %0}
1109 cmp{w}\\t{%1, %0|%0, %1}"
1110 [(set_attr "type" "test,icmp")
1111 (set_attr "length_immediate" "0,1")
1112 (set_attr "mode" "HI")])
1114 (define_insn "*cmphi_minus_1"
1116 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1117 (match_operand:HI 1 "general_operand" "ri,mr"))
1119 "ix86_match_ccmode (insn, CCGOCmode)"
1120 "cmp{w}\\t{%1, %0|%0, %1}"
1121 [(set_attr "type" "icmp")
1122 (set_attr "mode" "HI")])
1124 (define_insn "*cmphi_1"
1126 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1127 (match_operand:HI 1 "general_operand" "ri,mr")))]
1128 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1129 && ix86_match_ccmode (insn, CCmode)"
1130 "cmp{w}\\t{%1, %0|%0, %1}"
1131 [(set_attr "type" "icmp")
1132 (set_attr "mode" "HI")])
1134 (define_insn "*cmpqi_ccno_1"
1136 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1137 (match_operand:QI 1 "const0_operand" "n,n")))]
1138 "ix86_match_ccmode (insn, CCNOmode)"
1140 test{b}\\t{%0, %0|%0, %0}
1141 cmp{b}\\t{$0, %0|%0, 0}"
1142 [(set_attr "type" "test,icmp")
1143 (set_attr "length_immediate" "0,1")
1144 (set_attr "mode" "QI")])
1146 (define_insn "*cmpqi_1"
1148 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1149 (match_operand:QI 1 "general_operand" "qi,mq")))]
1150 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1151 && ix86_match_ccmode (insn, CCmode)"
1152 "cmp{b}\\t{%1, %0|%0, %1}"
1153 [(set_attr "type" "icmp")
1154 (set_attr "mode" "QI")])
1156 (define_insn "*cmpqi_minus_1"
1158 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1159 (match_operand:QI 1 "general_operand" "qi,mq"))
1161 "ix86_match_ccmode (insn, CCGOCmode)"
1162 "cmp{b}\\t{%1, %0|%0, %1}"
1163 [(set_attr "type" "icmp")
1164 (set_attr "mode" "QI")])
1166 (define_insn "*cmpqi_ext_1"
1169 (match_operand:QI 0 "general_operand" "Qm")
1172 (match_operand 1 "ext_register_operand" "Q")
1174 (const_int 8)) 0)))]
1175 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1176 "cmp{b}\\t{%h1, %0|%0, %h1}"
1177 [(set_attr "type" "icmp")
1178 (set_attr "mode" "QI")])
1180 (define_insn "*cmpqi_ext_1_rex64"
1183 (match_operand:QI 0 "ext_register_operand" "Q")
1186 (match_operand 1 "ext_register_operand" "Q")
1188 (const_int 8)) 0)))]
1189 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1190 "cmp{b}\\t{%h1, %0|%0, %h1}"
1191 [(set_attr "type" "icmp")
1192 (set_attr "mode" "QI")])
1194 (define_insn "*cmpqi_ext_2"
1199 (match_operand 0 "ext_register_operand" "Q")
1202 (match_operand:QI 1 "const0_operand" "n")))]
1203 "ix86_match_ccmode (insn, CCNOmode)"
1204 "test{b}\\t%h0, %h0"
1205 [(set_attr "type" "test")
1206 (set_attr "length_immediate" "0")
1207 (set_attr "mode" "QI")])
1209 (define_expand "cmpqi_ext_3"
1214 (match_operand 0 "ext_register_operand" "")
1217 (match_operand:QI 1 "general_operand" "")))]
1221 (define_insn "cmpqi_ext_3_insn"
1226 (match_operand 0 "ext_register_operand" "Q")
1229 (match_operand:QI 1 "general_operand" "Qmn")))]
1230 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1231 "cmp{b}\\t{%1, %h0|%h0, %1}"
1232 [(set_attr "type" "icmp")
1233 (set_attr "mode" "QI")])
1235 (define_insn "cmpqi_ext_3_insn_rex64"
1240 (match_operand 0 "ext_register_operand" "Q")
1243 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1244 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1245 "cmp{b}\\t{%1, %h0|%h0, %1}"
1246 [(set_attr "type" "icmp")
1247 (set_attr "mode" "QI")])
1249 (define_insn "*cmpqi_ext_4"
1254 (match_operand 0 "ext_register_operand" "Q")
1259 (match_operand 1 "ext_register_operand" "Q")
1261 (const_int 8)) 0)))]
1262 "ix86_match_ccmode (insn, CCmode)"
1263 "cmp{b}\\t{%h1, %h0|%h0, %h1}"
1264 [(set_attr "type" "icmp")
1265 (set_attr "mode" "QI")])
1267 ;; These implement float point compares.
1268 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1269 ;; which would allow mix and match FP modes on the compares. Which is what
1270 ;; the old patterns did, but with many more of them.
1272 (define_expand "cmpxf"
1274 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1275 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1276 "TARGET_80387 && !TARGET_64BIT"
1279 ix86_compare_op0 = operands[0];
1280 ix86_compare_op1 = operands[1];
1284 (define_expand "cmptf"
1286 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1287 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1291 ix86_compare_op0 = operands[0];
1292 ix86_compare_op1 = operands[1];
1296 (define_expand "cmpdf"
1298 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1299 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1300 "TARGET_80387 || TARGET_SSE2"
1303 ix86_compare_op0 = operands[0];
1304 ix86_compare_op1 = operands[1];
1308 (define_expand "cmpsf"
1310 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1311 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1312 "TARGET_80387 || TARGET_SSE"
1315 ix86_compare_op0 = operands[0];
1316 ix86_compare_op1 = operands[1];
1320 ;; FP compares, step 1:
1321 ;; Set the FP condition codes.
1323 ;; CCFPmode compare with exceptions
1324 ;; CCFPUmode compare with no exceptions
1326 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1327 ;; and that fp moves clobber the condition codes, and that there is
1328 ;; currently no way to describe this fact to reg-stack. So there are
1329 ;; no splitters yet for this.
1331 ;; %%% YIKES! This scheme does not retain a strong connection between
1332 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1333 ;; work! Only allow tos/mem with tos in op 0.
1335 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1336 ;; things aren't as bad as they sound...
1338 (define_insn "*cmpfp_0"
1339 [(set (match_operand:HI 0 "register_operand" "=a")
1341 [(compare:CCFP (match_operand 1 "register_operand" "f")
1342 (match_operand 2 "const0_operand" "X"))] 9))]
1344 && FLOAT_MODE_P (GET_MODE (operands[1]))
1345 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1348 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1349 return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
1351 return \"ftst\;fnstsw\\t%0\";
1353 [(set_attr "type" "multi")
1354 (set_attr "mode" "unknownfp")])
1356 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1357 ;; used to manage the reg stack popping would not be preserved.
1359 (define_insn "*cmpfp_2_sf"
1362 (match_operand:SF 0 "register_operand" "f")
1363 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1365 "* return output_fp_compare (insn, operands, 0, 0);"
1366 [(set_attr "type" "fcmp")
1367 (set_attr "mode" "SF")])
1369 (define_insn "*cmpfp_2_sf_1"
1370 [(set (match_operand:HI 0 "register_operand" "=a")
1373 (match_operand:SF 1 "register_operand" "f")
1374 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1376 "* return output_fp_compare (insn, operands, 2, 0);"
1377 [(set_attr "type" "fcmp")
1378 (set_attr "mode" "SF")])
1380 (define_insn "*cmpfp_2_df"
1383 (match_operand:DF 0 "register_operand" "f")
1384 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1386 "* return output_fp_compare (insn, operands, 0, 0);"
1387 [(set_attr "type" "fcmp")
1388 (set_attr "mode" "DF")])
1390 (define_insn "*cmpfp_2_df_1"
1391 [(set (match_operand:HI 0 "register_operand" "=a")
1394 (match_operand:DF 1 "register_operand" "f")
1395 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1397 "* return output_fp_compare (insn, operands, 2, 0);"
1398 [(set_attr "type" "multi")
1399 (set_attr "mode" "DF")])
1401 (define_insn "*cmpfp_2_xf"
1404 (match_operand:XF 0 "register_operand" "f")
1405 (match_operand:XF 1 "register_operand" "f")))]
1406 "TARGET_80387 && !TARGET_64BIT"
1407 "* return output_fp_compare (insn, operands, 0, 0);"
1408 [(set_attr "type" "fcmp")
1409 (set_attr "mode" "XF")])
1411 (define_insn "*cmpfp_2_tf"
1414 (match_operand:TF 0 "register_operand" "f")
1415 (match_operand:TF 1 "register_operand" "f")))]
1417 "* return output_fp_compare (insn, operands, 0, 0);"
1418 [(set_attr "type" "fcmp")
1419 (set_attr "mode" "XF")])
1421 (define_insn "*cmpfp_2_xf_1"
1422 [(set (match_operand:HI 0 "register_operand" "=a")
1425 (match_operand:XF 1 "register_operand" "f")
1426 (match_operand:XF 2 "register_operand" "f"))] 9))]
1427 "TARGET_80387 && !TARGET_64BIT"
1428 "* return output_fp_compare (insn, operands, 2, 0);"
1429 [(set_attr "type" "multi")
1430 (set_attr "mode" "XF")])
1432 (define_insn "*cmpfp_2_tf_1"
1433 [(set (match_operand:HI 0 "register_operand" "=a")
1436 (match_operand:TF 1 "register_operand" "f")
1437 (match_operand:TF 2 "register_operand" "f"))] 9))]
1439 "* return output_fp_compare (insn, operands, 2, 0);"
1440 [(set_attr "type" "multi")
1441 (set_attr "mode" "XF")])
1443 (define_insn "*cmpfp_2u"
1444 [(set (reg:CCFPU 18)
1446 (match_operand 0 "register_operand" "f")
1447 (match_operand 1 "register_operand" "f")))]
1449 && FLOAT_MODE_P (GET_MODE (operands[0]))
1450 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1451 "* return output_fp_compare (insn, operands, 0, 1);"
1452 [(set_attr "type" "fcmp")
1453 (set_attr "mode" "unknownfp")])
1455 (define_insn "*cmpfp_2u_1"
1456 [(set (match_operand:HI 0 "register_operand" "=a")
1459 (match_operand 1 "register_operand" "f")
1460 (match_operand 2 "register_operand" "f"))] 9))]
1462 && FLOAT_MODE_P (GET_MODE (operands[1]))
1463 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1464 "* return output_fp_compare (insn, operands, 2, 1);"
1465 [(set_attr "type" "multi")
1466 (set_attr "mode" "unknownfp")])
1468 ;; Patterns to match the SImode-in-memory ficom instructions.
1470 ;; %%% Play games with accepting gp registers, as otherwise we have to
1471 ;; force them to memory during rtl generation, which is no good. We
1472 ;; can get rid of this once we teach reload to do memory input reloads
1475 (define_insn "*ficom_1"
1478 (match_operand 0 "register_operand" "f,f")
1479 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1480 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1481 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1484 ;; Split the not-really-implemented gp register case into a
1485 ;; push-op-pop sequence.
1487 ;; %%% This is most efficient, but am I gonna get in trouble
1488 ;; for separating cc0_setter and cc0_user?
1493 (match_operand:SF 0 "register_operand" "")
1494 (float (match_operand:SI 1 "register_operand" ""))))]
1495 "0 && TARGET_80387 && reload_completed"
1496 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1497 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1498 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1499 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1500 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1501 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1503 ;; FP compares, step 2
1504 ;; Move the fpsw to ax.
1506 (define_insn "x86_fnstsw_1"
1507 [(set (match_operand:HI 0 "register_operand" "=a")
1508 (unspec:HI [(reg 18)] 9))]
1511 [(set_attr "length" "2")
1512 (set_attr "mode" "SI")
1513 (set_attr "i387" "1")
1514 (set_attr "ppro_uops" "few")])
1516 ;; FP compares, step 3
1517 ;; Get ax into flags, general case.
1519 (define_insn "x86_sahf_1"
1521 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1524 [(set_attr "length" "1")
1525 (set_attr "athlon_decode" "vector")
1526 (set_attr "mode" "SI")
1527 (set_attr "ppro_uops" "one")])
1529 ;; Pentium Pro can do steps 1 through 3 in one go.
1531 (define_insn "*cmpfp_i"
1533 (compare:CCFP (match_operand 0 "register_operand" "f")
1534 (match_operand 1 "register_operand" "f")))]
1535 "TARGET_80387 && TARGET_CMOVE
1536 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1537 && FLOAT_MODE_P (GET_MODE (operands[0]))
1538 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1539 "* return output_fp_compare (insn, operands, 1, 0);"
1540 [(set_attr "type" "fcmp")
1541 (set_attr "mode" "unknownfp")
1542 (set_attr "athlon_decode" "vector")])
1544 (define_insn "*cmpfp_i_sse"
1546 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1547 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1549 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1550 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1551 "* return output_fp_compare (insn, operands, 1, 0);"
1552 [(set_attr "type" "fcmp,sse")
1553 (set_attr "mode" "unknownfp")
1554 (set_attr "athlon_decode" "vector")])
1556 (define_insn "*cmpfp_i_sse_only"
1558 (compare:CCFP (match_operand 0 "register_operand" "x")
1559 (match_operand 1 "nonimmediate_operand" "xm")))]
1560 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1561 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1562 "* return output_fp_compare (insn, operands, 1, 0);"
1563 [(set_attr "type" "sse")
1564 (set_attr "mode" "unknownfp")
1565 (set_attr "athlon_decode" "vector")])
1567 (define_insn "*cmpfp_iu"
1568 [(set (reg:CCFPU 17)
1569 (compare:CCFPU (match_operand 0 "register_operand" "f")
1570 (match_operand 1 "register_operand" "f")))]
1571 "TARGET_80387 && TARGET_CMOVE
1572 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1573 && FLOAT_MODE_P (GET_MODE (operands[0]))
1574 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1575 "* return output_fp_compare (insn, operands, 1, 1);"
1576 [(set_attr "type" "fcmp")
1577 (set_attr "mode" "unknownfp")
1578 (set_attr "athlon_decode" "vector")])
1580 (define_insn "*cmpfp_iu_sse"
1581 [(set (reg:CCFPU 17)
1582 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1583 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1585 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1586 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1587 "* return output_fp_compare (insn, operands, 1, 1);"
1588 [(set_attr "type" "fcmp,sse")
1589 (set_attr "mode" "unknownfp")
1590 (set_attr "athlon_decode" "vector")])
1592 (define_insn "*cmpfp_iu_sse_only"
1593 [(set (reg:CCFPU 17)
1594 (compare:CCFPU (match_operand 0 "register_operand" "x")
1595 (match_operand 1 "nonimmediate_operand" "xm")))]
1596 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1597 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1598 "* return output_fp_compare (insn, operands, 1, 1);"
1599 [(set_attr "type" "sse")
1600 (set_attr "mode" "unknownfp")
1601 (set_attr "athlon_decode" "vector")])
1603 ;; Move instructions.
1605 ;; General case of fullword move.
1607 (define_expand "movsi"
1608 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1609 (match_operand:SI 1 "general_operand" ""))]
1611 "ix86_expand_move (SImode, operands); DONE;")
1613 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1616 ;; %%% We don't use a post-inc memory reference because x86 is not a
1617 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1618 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1619 ;; targets without our curiosities, and it is just as easy to represent
1620 ;; this differently.
1622 (define_insn "*pushsi2"
1623 [(set (match_operand:SI 0 "push_operand" "=<")
1624 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1627 [(set_attr "type" "push")
1628 (set_attr "mode" "SI")])
1630 ;; For 64BIT abi we always round up to 8 bytes.
1631 (define_insn "*pushsi2_rex64"
1632 [(set (match_operand:SI 0 "push_operand" "=X")
1633 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1636 [(set_attr "type" "push")
1637 (set_attr "mode" "SI")])
1639 (define_insn "*pushsi2_prologue"
1640 [(set (match_operand:SI 0 "push_operand" "=<")
1641 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1642 (set (reg:SI 6) (reg:SI 6))]
1645 [(set_attr "type" "push")
1646 (set_attr "mode" "SI")])
1648 (define_insn "*popsi1_epilogue"
1649 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1650 (mem:SI (reg:SI 7)))
1652 (plus:SI (reg:SI 7) (const_int 4)))
1653 (set (reg:SI 6) (reg:SI 6))]
1656 [(set_attr "type" "pop")
1657 (set_attr "mode" "SI")])
1659 (define_insn "popsi1"
1660 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1661 (mem:SI (reg:SI 7)))
1663 (plus:SI (reg:SI 7) (const_int 4)))]
1666 [(set_attr "type" "pop")
1667 (set_attr "mode" "SI")])
1669 (define_insn "*movsi_xor"
1670 [(set (match_operand:SI 0 "register_operand" "=r")
1671 (match_operand:SI 1 "const0_operand" "i"))
1672 (clobber (reg:CC 17))]
1673 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1674 "xor{l}\\t{%0, %0|%0, %0}"
1675 [(set_attr "type" "alu1")
1676 (set_attr "mode" "SI")
1677 (set_attr "length_immediate" "0")])
1679 (define_insn "*movsi_or"
1680 [(set (match_operand:SI 0 "register_operand" "=r")
1681 (match_operand:SI 1 "immediate_operand" "i"))
1682 (clobber (reg:CC 17))]
1683 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1684 && INTVAL (operands[1]) == -1
1685 && (TARGET_PENTIUM || optimize_size)"
1688 operands[1] = constm1_rtx;
1689 return \"or{l}\\t{%1, %0|%0, %1}\";
1691 [(set_attr "type" "alu1")
1692 (set_attr "mode" "SI")
1693 (set_attr "length_immediate" "1")])
1695 (define_insn "*movsi_1"
1696 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!r")
1697 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,r,*y"))]
1698 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1701 switch (get_attr_type (insn))
1704 return \"movd\\t{%1, %0|%0, %1}\";
1707 return \"lea{l}\\t{%1, %0|%0, %1}\";
1710 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1712 return \"mov{l}\\t{%1, %0|%0, %1}\";
1716 (cond [(ior (match_operand:SI 0 "mmx_reg_operand" "")
1717 (match_operand:SI 1 "mmx_reg_operand" ""))
1718 (const_string "mmx")
1719 (and (ne (symbol_ref "flag_pic") (const_int 0))
1720 (match_operand:SI 1 "symbolic_operand" ""))
1721 (const_string "lea")
1723 (const_string "imov")))
1724 (set_attr "modrm" "0,*,0,*,*,*")
1725 (set_attr "mode" "SI")])
1727 ;; Stores and loads of ax to arbitary constant address.
1728 ;; We fake an second form of instruction to force reload to load address
1729 ;; into register when rax is not available
1730 (define_insn "*movabssi_1_rex64"
1731 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1732 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1735 movabs{l}\\t{%1, %P0|%P0, %1}
1736 mov{l}\\t{%1, %a0|%a0, %1}
1737 movabs{l}\\t{%1, %a0|%a0, %1}"
1738 [(set_attr "type" "imov")
1739 (set_attr "modrm" "0,*,*")
1740 (set_attr "length_address" "8,0,0")
1741 (set_attr "length_immediate" "0,*,*")
1742 (set_attr "memory" "store")
1743 (set_attr "mode" "SI")])
1745 (define_insn "*movabssi_2_rex64"
1746 [(set (match_operand:SI 0 "register_operand" "=a,r")
1747 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1750 movabs{l}\\t{%P1, %0|%0, %P1}
1751 mov{l}\\t{%a1, %0|%0, %a1}"
1752 [(set_attr "type" "imov")
1753 (set_attr "modrm" "0,*")
1754 (set_attr "length_address" "8,0")
1755 (set_attr "length_immediate" "0")
1756 (set_attr "memory" "load")
1757 (set_attr "mode" "SI")])
1759 (define_insn "*swapsi"
1760 [(set (match_operand:SI 0 "register_operand" "+r")
1761 (match_operand:SI 1 "register_operand" "+r"))
1766 [(set_attr "type" "imov")
1767 (set_attr "pent_pair" "np")
1768 (set_attr "athlon_decode" "vector")
1769 (set_attr "mode" "SI")
1770 (set_attr "modrm" "0")
1771 (set_attr "ppro_uops" "few")])
1773 (define_expand "movhi"
1774 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1775 (match_operand:HI 1 "general_operand" ""))]
1777 "ix86_expand_move (HImode, operands); DONE;")
1779 (define_insn "*pushhi2"
1780 [(set (match_operand:HI 0 "push_operand" "=<,<")
1781 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1784 push{w}\\t{|WORD PTR }%1
1786 [(set_attr "type" "push")
1787 (set_attr "mode" "HI")])
1789 (define_insn "*movhi_1"
1790 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1791 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1792 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1795 switch (get_attr_type (insn))
1798 /* movzwl is faster than movw on p2 due to partial word stalls,
1799 though not as fast as an aligned movl. */
1800 return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
1802 if (get_attr_mode (insn) == MODE_SI)
1803 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1805 return \"mov{w}\\t{%1, %0|%0, %1}\";
1809 (cond [(and (eq_attr "alternative" "0,1")
1810 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1812 (eq (symbol_ref "TARGET_HIMODE_MATH")
1814 (const_string "imov")
1815 (and (eq_attr "alternative" "2,3,4")
1816 (match_operand:HI 1 "aligned_operand" ""))
1817 (const_string "imov")
1818 (and (ne (symbol_ref "TARGET_MOVX")
1820 (eq_attr "alternative" "0,1,3,4"))
1821 (const_string "imovx")
1823 (const_string "imov")))
1825 (cond [(eq_attr "type" "imovx")
1827 (and (eq_attr "alternative" "2,3,4")
1828 (match_operand:HI 1 "aligned_operand" ""))
1830 (and (eq_attr "alternative" "0,1")
1831 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1833 (eq (symbol_ref "TARGET_HIMODE_MATH")
1837 (const_string "HI")))
1838 (set_attr "modrm" "0,*,*,0,*,*")])
1840 ;; Stores and loads of ax to arbitary constant address.
1841 ;; We fake an second form of instruction to force reload to load address
1842 ;; into register when rax is not available
1843 (define_insn "*movabshi_1_rex64"
1844 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1845 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1848 movabs{w}\\t{%1, %P0|%P0, %1}
1849 mov{w}\\t{%1, %a0|%a0, %1}
1850 movabs{w}\\t{%1, %a0|%a0, %1}"
1851 [(set_attr "type" "imov")
1852 (set_attr "modrm" "0,*,*")
1853 (set_attr "length_address" "8,0,0")
1854 (set_attr "length_immediate" "0,*,*")
1855 (set_attr "memory" "store")
1856 (set_attr "mode" "HI")])
1858 (define_insn "*movabshi_2_rex64"
1859 [(set (match_operand:HI 0 "register_operand" "=a,r")
1860 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1863 movabs{w}\\t{%P1, %0|%0, %P1}
1864 mov{w}\\t{%a1, %0|%0, %a1}"
1865 [(set_attr "type" "imov")
1866 (set_attr "modrm" "0,*")
1867 (set_attr "length_address" "8,0")
1868 (set_attr "length_immediate" "0")
1869 (set_attr "memory" "load")
1870 (set_attr "mode" "HI")])
1872 (define_insn "*swaphi_1"
1873 [(set (match_operand:HI 0 "register_operand" "+r")
1874 (match_operand:HI 1 "register_operand" "+r"))
1877 "TARGET_PARTIAL_REG_STALL"
1879 [(set_attr "type" "imov")
1880 (set_attr "pent_pair" "np")
1881 (set_attr "mode" "HI")
1882 (set_attr "modrm" "0")
1883 (set_attr "ppro_uops" "few")])
1885 (define_insn "*swaphi_2"
1886 [(set (match_operand:HI 0 "register_operand" "+r")
1887 (match_operand:HI 1 "register_operand" "+r"))
1890 "! TARGET_PARTIAL_REG_STALL"
1891 "xchg{l}\\t%k1, %k0"
1892 [(set_attr "type" "imov")
1893 (set_attr "pent_pair" "np")
1894 (set_attr "mode" "SI")
1895 (set_attr "modrm" "0")
1896 (set_attr "ppro_uops" "few")])
1898 (define_expand "movstricthi"
1899 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1900 (match_operand:HI 1 "general_operand" ""))]
1901 "! TARGET_PARTIAL_REG_STALL"
1904 /* Don't generate memory->memory moves, go through a register */
1905 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1906 operands[1] = force_reg (HImode, operands[1]);
1909 (define_insn "*movstricthi_1"
1910 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1911 (match_operand:HI 1 "general_operand" "rn,m"))]
1912 "! TARGET_PARTIAL_REG_STALL
1913 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1914 "mov{w}\\t{%1, %0|%0, %1}"
1915 [(set_attr "type" "imov")
1916 (set_attr "mode" "HI")])
1918 (define_insn "*movstricthi_xor"
1919 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1920 (match_operand:HI 1 "const0_operand" "i"))
1921 (clobber (reg:CC 17))]
1922 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1923 "xor{w}\\t{%0, %0|%0, %0}"
1924 [(set_attr "type" "alu1")
1925 (set_attr "mode" "HI")
1926 (set_attr "length_immediate" "0")])
1928 (define_expand "movqi"
1929 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1930 (match_operand:QI 1 "general_operand" ""))]
1932 "ix86_expand_move (QImode, operands); DONE;")
1934 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1935 ;; "push a byte". But actually we use pushw, which has the effect
1936 ;; of rounding the amount pushed up to a halfword.
1938 (define_insn "*pushqi2"
1939 [(set (match_operand:QI 0 "push_operand" "=X,X")
1940 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1943 push{w}\\t{|word ptr }%1
1945 [(set_attr "type" "push")
1946 (set_attr "mode" "HI")])
1948 ;; Situation is quite tricky about when to choose full sized (SImode) move
1949 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1950 ;; partial register dependency machines (such as AMD Athlon), where QImode
1951 ;; moves issue extra dependency and for partial register stalls machines
1952 ;; that don't use QImode patterns (and QImode move cause stall on the next
1955 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1956 ;; register stall machines with, where we use QImode instructions, since
1957 ;; partial register stall can be caused there. Then we use movzx.
1958 (define_insn "*movqi_1"
1959 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1960 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1961 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1964 switch (get_attr_type (insn))
1967 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1969 return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
1971 if (get_attr_mode (insn) == MODE_SI)
1972 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1974 return \"mov{b}\\t{%1, %0|%0, %1}\";
1978 (cond [(and (eq_attr "alternative" "3")
1979 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1981 (eq (symbol_ref "TARGET_QIMODE_MATH")
1983 (const_string "imov")
1984 (eq_attr "alternative" "3,5")
1985 (const_string "imovx")
1986 (and (ne (symbol_ref "TARGET_MOVX")
1988 (eq_attr "alternative" "2"))
1989 (const_string "imovx")
1991 (const_string "imov")))
1993 (cond [(eq_attr "alternative" "3,4,5")
1995 (eq_attr "alternative" "6")
1997 (eq_attr "type" "imovx")
1999 (and (eq_attr "type" "imov")
2000 (and (eq_attr "alternative" "0,1,2")
2001 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2004 ;; Avoid partial register stalls when not using QImode arithmetic
2005 (and (eq_attr "type" "imov")
2006 (and (eq_attr "alternative" "0,1,2")
2007 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2009 (eq (symbol_ref "TARGET_QIMODE_MATH")
2013 (const_string "QI")))])
2015 (define_expand "reload_outqi"
2016 [(parallel [(match_operand:QI 0 "" "=m")
2017 (match_operand:QI 1 "register_operand" "r")
2018 (match_operand:QI 2 "register_operand" "=&q")])]
2023 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2025 if (reg_overlap_mentioned_p (op2, op0))
2027 if (! q_regs_operand (op1, QImode))
2029 emit_insn (gen_movqi (op2, op1));
2032 emit_insn (gen_movqi (op0, op1));
2036 (define_insn "*swapqi"
2037 [(set (match_operand:QI 0 "register_operand" "+r")
2038 (match_operand:QI 1 "register_operand" "+r"))
2043 [(set_attr "type" "imov")
2044 (set_attr "pent_pair" "np")
2045 (set_attr "mode" "QI")
2046 (set_attr "modrm" "0")
2047 (set_attr "ppro_uops" "few")])
2049 (define_expand "movstrictqi"
2050 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2051 (match_operand:QI 1 "general_operand" ""))]
2052 "! TARGET_PARTIAL_REG_STALL"
2055 /* Don't generate memory->memory moves, go through a register */
2056 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2057 operands[1] = force_reg (QImode, operands[1]);
2060 (define_insn "*movstrictqi_1"
2061 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2062 (match_operand:QI 1 "general_operand" "*qn,m"))]
2063 "! TARGET_PARTIAL_REG_STALL
2064 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2065 "mov{b}\\t{%1, %0|%0, %1}"
2066 [(set_attr "type" "imov")
2067 (set_attr "mode" "QI")])
2069 (define_insn "*movstrictqi_xor"
2070 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2071 (match_operand:QI 1 "const0_operand" "i"))
2072 (clobber (reg:CC 17))]
2073 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2074 "xor{b}\\t{%0, %0|%0, %0}"
2075 [(set_attr "type" "alu1")
2076 (set_attr "mode" "QI")
2077 (set_attr "length_immediate" "0")])
2079 (define_insn "*movsi_extv_1"
2080 [(set (match_operand:SI 0 "register_operand" "=R")
2081 (sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
2085 "movs{bl|x}\\t{%h1, %0|%0, %h1}"
2086 [(set_attr "type" "imovx")
2087 (set_attr "mode" "SI")])
2089 (define_insn "*movhi_extv_1"
2090 [(set (match_operand:HI 0 "register_operand" "=R")
2091 (sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
2095 "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
2096 [(set_attr "type" "imovx")
2097 (set_attr "mode" "SI")])
2099 (define_insn "*movqi_extv_1"
2100 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2101 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2107 switch (get_attr_type (insn))
2110 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2112 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2116 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2117 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2118 (ne (symbol_ref "TARGET_MOVX")
2120 (const_string "imovx")
2121 (const_string "imov")))
2123 (if_then_else (eq_attr "type" "imovx")
2125 (const_string "QI")))])
2127 (define_insn "*movqi_extv_1_rex64"
2128 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2129 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2135 switch (get_attr_type (insn))
2138 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2140 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2144 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2145 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2146 (ne (symbol_ref "TARGET_MOVX")
2148 (const_string "imovx")
2149 (const_string "imov")))
2151 (if_then_else (eq_attr "type" "imovx")
2153 (const_string "QI")))])
2155 ;; Stores and loads of ax to arbitary constant address.
2156 ;; We fake an second form of instruction to force reload to load address
2157 ;; into register when rax is not available
2158 (define_insn "*movabsqi_1_rex64"
2159 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2160 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2163 movabs{q}\\t{%1, %P0|%P0, %1}
2164 mov{q}\\t{%1, %a0|%a0, %1}
2165 movabs{q}\\t{%1, %a0|%a0, %1}"
2166 [(set_attr "type" "imov")
2167 (set_attr "modrm" "0,*,*")
2168 (set_attr "length_address" "8,0,0")
2169 (set_attr "length_immediate" "0,*,*")
2170 (set_attr "memory" "store")
2171 (set_attr "mode" "QI")])
2173 (define_insn "*movabsqi_2_rex64"
2174 [(set (match_operand:QI 0 "register_operand" "=a,r")
2175 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2178 movabs{q}\\t{%P1, %0|%0, %P1}
2179 mov{q}\\t{%a1, %0|%0, %a1}"
2180 [(set_attr "type" "imov")
2181 (set_attr "modrm" "0,*")
2182 (set_attr "length_address" "8,0")
2183 (set_attr "length_immediate" "0")
2184 (set_attr "memory" "load")
2185 (set_attr "mode" "QI")])
2187 (define_insn "*movsi_extzv_1"
2188 [(set (match_operand:SI 0 "register_operand" "=R")
2189 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2193 "movz{bl|x}\\t{%h1, %0|%0, %h1}"
2194 [(set_attr "type" "imovx")
2195 (set_attr "mode" "SI")])
2197 (define_insn "*movqi_extzv_2"
2198 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2199 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2205 switch (get_attr_type (insn))
2208 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2210 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2214 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2215 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2216 (ne (symbol_ref "TARGET_MOVX")
2218 (const_string "imovx")
2219 (const_string "imov")))
2221 (if_then_else (eq_attr "type" "imovx")
2223 (const_string "QI")))])
2225 (define_insn "*movqi_extzv_2_rex64"
2226 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2227 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2233 switch (get_attr_type (insn))
2236 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2238 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2242 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2243 (ne (symbol_ref "TARGET_MOVX")
2245 (const_string "imovx")
2246 (const_string "imov")))
2248 (if_then_else (eq_attr "type" "imovx")
2250 (const_string "QI")))])
2252 (define_insn "*movsi_insv_1"
2253 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2256 (match_operand:SI 1 "nonimmediate_operand" "Qm"))]
2258 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2259 [(set_attr "type" "imov")
2260 (set_attr "mode" "QI")])
2262 (define_insn "*movsi_insv_1_rex64"
2263 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2266 (match_operand:SI 1 "ext_register_operand" "Q"))]
2268 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2269 [(set_attr "type" "imov")
2270 (set_attr "mode" "QI")])
2272 (define_insn "*movqi_insv_2"
2273 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2276 (and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
2280 "mov{b}\\t{%h1, %h0|%h0, %h1}"
2281 [(set_attr "type" "imov")
2282 (set_attr "mode" "QI")])
2284 (define_expand "movdi"
2285 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2286 (match_operand:DI 1 "general_operand" ""))]
2288 "ix86_expand_move (DImode, operands); DONE;")
2290 (define_insn "*pushdi"
2291 [(set (match_operand:DI 0 "push_operand" "=<")
2292 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2296 (define_insn "pushdi2_rex64"
2297 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2298 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2303 [(set_attr "type" "push,multi")
2304 (set_attr "mode" "DI")])
2306 ;; Convert impossible pushes of immediate to existing instructions.
2307 ;; First try to get scratch register and go trought it. In case this
2308 ;; fails, push sign extended lower part first and then overwrite
2309 ;; upper part by 32bit move.
2311 [(match_scratch:DI 2 "r")
2312 (set (match_operand:DI 0 "push_operand" "")
2313 (match_operand:DI 1 "immediate_operand" ""))]
2314 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2315 && !x86_64_immediate_operand (operands[1], DImode)"
2316 [(set (match_dup 2) (match_dup 1))
2317 (set (match_dup 0) (match_dup 2))]
2320 ;; We need to define this as both peepholer and splitter for case
2321 ;; peephole2 pass is not run.
2323 [(set (match_operand:DI 0 "push_operand" "")
2324 (match_operand:DI 1 "immediate_operand" ""))]
2325 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2326 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2327 [(set (match_dup 0) (match_dup 1))
2328 (set (match_dup 2) (match_dup 3))]
2329 "split_di (operands + 1, 1, operands + 2, operands + 3);
2330 operands[1] = gen_lowpart (DImode, operands[2]);
2331 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2336 [(set (match_operand:DI 0 "push_operand" "")
2337 (match_operand:DI 1 "immediate_operand" ""))]
2338 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2339 && !symbolic_operand (operands[1], DImode)
2340 && !x86_64_immediate_operand (operands[1], DImode)"
2341 [(set (match_dup 0) (match_dup 1))
2342 (set (match_dup 2) (match_dup 3))]
2343 "split_di (operands + 1, 1, operands + 2, operands + 3);
2344 operands[1] = gen_lowpart (DImode, operands[2]);
2345 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2349 (define_insn "*pushdi2_prologue_rex64"
2350 [(set (match_operand:DI 0 "push_operand" "=<")
2351 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2352 (set (reg:DI 6) (reg:DI 6))]
2355 [(set_attr "type" "push")
2356 (set_attr "mode" "DI")])
2358 (define_insn "*popdi1_epilogue_rex64"
2359 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2360 (mem:DI (reg:DI 7)))
2362 (plus:DI (reg:DI 7) (const_int 8)))
2363 (set (reg:DI 6) (reg:DI 6))]
2366 [(set_attr "type" "pop")
2367 (set_attr "mode" "DI")])
2369 (define_insn "popdi1"
2370 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2371 (mem:DI (reg:DI 7)))
2373 (plus:DI (reg:DI 7) (const_int 8)))]
2376 [(set_attr "type" "pop")
2377 (set_attr "mode" "DI")])
2379 (define_insn "*movdi_xor_rex64"
2380 [(set (match_operand:DI 0 "register_operand" "=r")
2381 (match_operand:DI 1 "const0_operand" "i"))
2382 (clobber (reg:CC 17))]
2383 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
2385 "xor{l}\\t{%k0, %k0|%k0, %k0}"
2386 [(set_attr "type" "alu1")
2387 (set_attr "mode" "SI")
2388 (set_attr "length_immediate" "0")])
2390 (define_insn "*movdi_or_rex64"
2391 [(set (match_operand:DI 0 "register_operand" "=r")
2392 (match_operand:DI 1 "const_int_operand" "i"))
2393 (clobber (reg:CC 17))]
2394 "reload_completed && GET_CODE (operands[1]) == CONST_INT
2396 && INTVAL (operands[1]) == -1
2397 && (TARGET_PENTIUM || optimize_size)"
2400 operands[1] = constm1_rtx;
2401 return \"or{q}\\t{%1, %0|%0, %1}\";
2403 [(set_attr "type" "alu1")
2404 (set_attr "mode" "DI")
2405 (set_attr "length_immediate" "1")])
2407 (define_insn "*movdi_2"
2408 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y")
2409 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m"))]
2411 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2415 movq\\t{%1, %0|%0, %1}
2416 movq\\t{%1, %0|%0, %1}"
2417 [(set_attr "type" "*,*,mmx,mmx")])
2420 [(set (match_operand:DI 0 "push_operand" "")
2421 (match_operand:DI 1 "general_operand" ""))]
2422 "!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[1])"
2424 "if (!ix86_split_long_move (operands)) abort (); DONE;")
2426 ;; %%% This multiword shite has got to go.
2428 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2429 (match_operand:DI 1 "general_operand" ""))]
2430 "!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[0])
2431 && ! MMX_REG_P (operands[1])"
2432 [(set (match_dup 2) (match_dup 5))
2433 (set (match_dup 3) (match_dup 6))]
2434 "if (ix86_split_long_move (operands)) DONE;")
2436 (define_insn "*movdi_1_rex64"
2437 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,*m,*Y")
2438 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*m"))]
2439 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2443 switch (get_attr_type (insn))
2447 return \"movd\\t{%1, %0|%0, %1}\";
2451 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
2453 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2455 if (get_attr_mode (insn) == MODE_SI)
2456 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2457 else if (which_alternative == 2)
2458 return \"movabs{q}\\t{%1, %0|%0, %1}\";
2460 return \"mov{q}\\t{%1, %0|%0, %1}\";
2464 (cond [(eq_attr "alternative" "5,6")
2465 (const_string "mmx")
2466 (eq_attr "alternative" "7,8")
2467 (const_string "sse")
2468 (eq_attr "alternative" "4")
2469 (const_string "multi")
2470 (and (ne (symbol_ref "flag_pic") (const_int 0))
2471 (match_operand:DI 1 "symbolic_operand" ""))
2472 (const_string "lea")
2474 (const_string "imov")))
2475 (set_attr "modrm" "*,0,0,*,*,*,*,*,*")
2476 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*")
2477 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI")])
2479 ;; Stores and loads of ax to arbitary constant address.
2480 ;; We fake an second form of instruction to force reload to load address
2481 ;; into register when rax is not available
2482 (define_insn "*movabsdi_1_rex64"
2483 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2484 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2487 movabs{q}\\t{%1, %P0|%P0, %1}
2488 mov{q}\\t{%1, %a0|%a0, %1}
2489 movabs{q}\\t{%1, %a0|%a0, %1}"
2490 [(set_attr "type" "imov")
2491 (set_attr "modrm" "0,*,*")
2492 (set_attr "length_address" "8,0,0")
2493 (set_attr "length_immediate" "0,*,*")
2494 (set_attr "memory" "store")
2495 (set_attr "mode" "DI")])
2497 (define_insn "*movabsdi_2_rex64"
2498 [(set (match_operand:DI 0 "register_operand" "=a,r")
2499 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2502 movabs{q}\\t{%P1, %0|%0, %P1}
2503 mov{q}\\t{%a1, %0|%0, %a1}"
2504 [(set_attr "type" "imov")
2505 (set_attr "modrm" "0,*")
2506 (set_attr "length_address" "8,0")
2507 (set_attr "length_immediate" "0")
2508 (set_attr "memory" "load")
2509 (set_attr "mode" "DI")])
2511 ;; Convert impossible stores of immediate to existing instructions.
2512 ;; First try to get scratch register and go trought it. In case this
2513 ;; fails, move by 32bit parts.
2515 [(match_scratch:DI 2 "r")
2516 (set (match_operand:DI 0 "memory_operand" "")
2517 (match_operand:DI 1 "immediate_operand" ""))]
2518 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2519 && !x86_64_immediate_operand (operands[1], DImode)"
2520 [(set (match_dup 2) (match_dup 1))
2521 (set (match_dup 0) (match_dup 2))]
2524 ;; We need to define this as both peepholer and splitter for case
2525 ;; peephole2 pass is not run.
2527 [(set (match_operand:DI 0 "memory_operand" "")
2528 (match_operand:DI 1 "immediate_operand" ""))]
2529 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2530 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2531 [(set (match_dup 2) (match_dup 3))
2532 (set (match_dup 4) (match_dup 5))]
2533 "split_di (operands, 2, operands + 2, operands + 4);")
2536 [(set (match_operand:DI 0 "memory_operand" "")
2537 (match_operand:DI 1 "immediate_operand" ""))]
2538 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2539 && !symbolic_operand (operands[1], DImode)
2540 && !x86_64_immediate_operand (operands[1], DImode)"
2541 [(set (match_dup 2) (match_dup 3))
2542 (set (match_dup 4) (match_dup 5))]
2543 "split_di (operands, 2, operands + 2, operands + 4);")
2545 (define_insn "*swapdi_rex64"
2546 [(set (match_operand:DI 0 "register_operand" "+r")
2547 (match_operand:DI 1 "register_operand" "+r"))
2552 [(set_attr "type" "imov")
2553 (set_attr "pent_pair" "np")
2554 (set_attr "athlon_decode" "vector")
2555 (set_attr "mode" "DI")
2556 (set_attr "modrm" "0")
2557 (set_attr "ppro_uops" "few")])
2560 (define_expand "movsf"
2561 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2562 (match_operand:SF 1 "general_operand" ""))]
2564 "ix86_expand_move (SFmode, operands); DONE;")
2566 (define_insn "*pushsf"
2567 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2568 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2572 switch (which_alternative)
2575 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2576 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2577 operands[2] = stack_pointer_rtx;
2578 operands[3] = GEN_INT (4);
2579 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2580 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2582 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2585 return \"push{l}\\t%1\";
2593 [(set_attr "type" "multi,push,multi")
2594 (set_attr "mode" "SF,SI,SF")])
2596 (define_insn "*pushsf_rex64"
2597 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2598 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2602 switch (which_alternative)
2605 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2606 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2607 operands[2] = stack_pointer_rtx;
2608 operands[3] = GEN_INT (8);
2609 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2610 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2612 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2615 return \"push{q}\\t%q1\";
2624 [(set_attr "type" "multi,push,multi")
2625 (set_attr "mode" "SF,DI,SF")])
2628 [(set (match_operand:SF 0 "push_operand" "")
2629 (match_operand:SF 1 "memory_operand" ""))]
2631 && GET_CODE (operands[1]) == MEM
2632 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2633 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2636 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2639 ;; %%% Kill this when call knows how to work this out.
2641 [(set (match_operand:SF 0 "push_operand" "")
2642 (match_operand:SF 1 "register_operand" ""))]
2643 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2644 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2645 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2648 [(set (match_operand:SF 0 "push_operand" "")
2649 (match_operand:SF 1 "register_operand" ""))]
2650 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2651 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2652 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2654 (define_insn "*movsf_1"
2655 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2656 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2657 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2658 && (reload_in_progress || reload_completed
2659 || GET_CODE (operands[1]) != CONST_DOUBLE
2660 || memory_operand (operands[0], SFmode))"
2663 switch (which_alternative)
2666 if (REG_P (operands[1])
2667 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2668 return \"fstp\\t%y0\";
2669 else if (STACK_TOP_P (operands[0]))
2670 return \"fld%z1\\t%y1\";
2672 return \"fst\\t%y0\";
2675 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2676 return \"fstp%z0\\t%y0\";
2678 return \"fst%z0\\t%y0\";
2681 switch (standard_80387_constant_p (operands[1]))
2692 return \"mov{l}\\t{%1, %0|%0, %1}\";
2694 return \"pxor\\t%0, %0\";
2696 if (TARGET_PARTIAL_REG_DEPENDENCY)
2697 return \"movaps\\t{%1, %0|%0, %1}\";
2699 return \"movss\\t{%1, %0|%0, %1}\";
2702 return \"movss\\t{%1, %0|%0, %1}\";
2708 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2709 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2711 (define_insn "*swapsf"
2712 [(set (match_operand:SF 0 "register_operand" "+f")
2713 (match_operand:SF 1 "register_operand" "+f"))
2716 "reload_completed || !TARGET_SSE2"
2719 if (STACK_TOP_P (operands[0]))
2720 return \"fxch\\t%1\";
2722 return \"fxch\\t%0\";
2724 [(set_attr "type" "fxch")
2725 (set_attr "mode" "SF")])
2727 (define_expand "movdf"
2728 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2729 (match_operand:DF 1 "general_operand" ""))]
2731 "ix86_expand_move (DFmode, operands); DONE;")
2733 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2734 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2735 ;; On the average, pushdf using integers can be still shorter. Allow this
2736 ;; pattern for optimize_size too.
2738 (define_insn "*pushdf_nointeger"
2739 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2740 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2741 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2744 switch (which_alternative)
2747 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2748 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2749 operands[2] = stack_pointer_rtx;
2750 operands[3] = GEN_INT (8);
2751 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2752 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2754 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2765 [(set_attr "type" "multi")
2766 (set_attr "mode" "DF,SI,SI,DF")])
2768 (define_insn "*pushdf_integer"
2769 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2770 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2771 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2774 switch (which_alternative)
2777 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2778 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2779 operands[2] = stack_pointer_rtx;
2780 operands[3] = GEN_INT (8);
2782 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2783 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2785 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2787 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2788 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2790 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2801 [(set_attr "type" "multi")
2802 (set_attr "mode" "DF,SI,DF")])
2804 ;; %%% Kill this when call knows how to work this out.
2806 [(set (match_operand:DF 0 "push_operand" "")
2807 (match_operand:DF 1 "register_operand" ""))]
2808 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2809 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2810 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2814 [(set (match_operand:DF 0 "push_operand" "")
2815 (match_operand:DF 1 "register_operand" ""))]
2816 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2817 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2818 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2822 [(set (match_operand:DF 0 "push_operand" "")
2823 (match_operand:DF 1 "general_operand" ""))]
2826 "if (!ix86_split_long_move (operands)) abort (); DONE;")
2828 ;; Moving is usually shorter when only FP registers are used. This separate
2829 ;; movdf pattern avoids the use of integer registers for FP operations
2830 ;; when optimizing for size.
2832 (define_insn "*movdf_nointeger"
2833 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2834 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2835 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2836 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2837 && (reload_in_progress || reload_completed
2838 || GET_CODE (operands[1]) != CONST_DOUBLE
2839 || memory_operand (operands[0], DFmode))"
2842 switch (which_alternative)
2845 if (REG_P (operands[1])
2846 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2847 return \"fstp\\t%y0\";
2848 else if (STACK_TOP_P (operands[0]))
2849 return \"fld%z1\\t%y1\";
2851 return \"fst\\t%y0\";
2854 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2855 return \"fstp%z0\\t%y0\";
2857 return \"fst%z0\\t%y0\";
2860 switch (standard_80387_constant_p (operands[1]))
2873 return \"pxor\\t%0, %0\";
2875 if (TARGET_PARTIAL_REG_DEPENDENCY)
2876 return \"movapd\\t{%1, %0|%0, %1}\";
2878 return \"movsd\\t{%1, %0|%0, %1}\";
2881 return \"movsd\\t{%1, %0|%0, %1}\";
2887 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2888 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2890 (define_insn "*movdf_integer"
2891 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2892 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2893 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2894 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2895 && (reload_in_progress || reload_completed
2896 || GET_CODE (operands[1]) != CONST_DOUBLE
2897 || memory_operand (operands[0], DFmode))"
2900 switch (which_alternative)
2903 if (REG_P (operands[1])
2904 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2905 return \"fstp\\t%y0\";
2906 else if (STACK_TOP_P (operands[0]))
2907 return \"fld%z1\\t%y1\";
2909 return \"fst\\t%y0\";
2912 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2913 return \"fstp%z0\\t%y0\";
2915 return \"fst%z0\\t%y0\";
2918 switch (standard_80387_constant_p (operands[1]))
2932 return \"pxor\\t%0, %0\";
2934 if (TARGET_PARTIAL_REG_DEPENDENCY)
2935 return \"movapd\\t{%1, %0|%0, %1}\";
2937 return \"movsd\\t{%1, %0|%0, %1}\";
2940 return \"movsd\\t{%1, %0|%0, %1}\";
2946 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2947 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2950 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2951 (match_operand:DF 1 "general_operand" ""))]
2953 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2954 && ! (ANY_FP_REG_P (operands[0]) ||
2955 (GET_CODE (operands[0]) == SUBREG
2956 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2957 && ! (ANY_FP_REG_P (operands[1]) ||
2958 (GET_CODE (operands[1]) == SUBREG
2959 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2960 [(set (match_dup 2) (match_dup 5))
2961 (set (match_dup 3) (match_dup 6))]
2962 "if (ix86_split_long_move (operands)) DONE;")
2964 (define_insn "*swapdf"
2965 [(set (match_operand:DF 0 "register_operand" "+f")
2966 (match_operand:DF 1 "register_operand" "+f"))
2969 "reload_completed || !TARGET_SSE2"
2972 if (STACK_TOP_P (operands[0]))
2973 return \"fxch\\t%1\";
2975 return \"fxch\\t%0\";
2977 [(set_attr "type" "fxch")
2978 (set_attr "mode" "DF")])
2980 (define_expand "movxf"
2981 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2982 (match_operand:XF 1 "general_operand" ""))]
2984 "ix86_expand_move (XFmode, operands); DONE;")
2986 (define_expand "movtf"
2987 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2988 (match_operand:TF 1 "general_operand" ""))]
2990 "ix86_expand_move (TFmode, operands); DONE;")
2992 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2993 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
2994 ;; Pushing using integer instructions is longer except for constants
2995 ;; and direct memory references.
2996 ;; (assuming that any given constant is pushed only once, but this ought to be
2997 ;; handled elsewhere).
2999 (define_insn "*pushxf_nointeger"
3000 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3001 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3002 "optimize_size && !TARGET_64BIT"
3005 switch (which_alternative)
3008 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3009 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3010 operands[2] = stack_pointer_rtx;
3011 operands[3] = GEN_INT (12);
3012 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3013 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3015 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3025 [(set_attr "type" "multi")
3026 (set_attr "mode" "XF,SI,SI")])
3028 (define_insn "*pushtf_nointeger"
3029 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3030 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3034 switch (which_alternative)
3037 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3038 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3039 operands[2] = stack_pointer_rtx;
3040 operands[3] = GEN_INT (16);
3041 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3042 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3044 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3054 [(set_attr "type" "multi")
3055 (set_attr "mode" "XF,SI,SI")])
3057 (define_insn "*pushxf_integer"
3058 [(set (match_operand:XF 0 "push_operand" "=<,<")
3059 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3060 "!optimize_size && !TARGET_64BIT"
3063 switch (which_alternative)
3066 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3067 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3068 operands[2] = stack_pointer_rtx;
3069 operands[3] = GEN_INT (12);
3070 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3071 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3073 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3082 [(set_attr "type" "multi")
3083 (set_attr "mode" "XF,SI")])
3085 (define_insn "*pushtf_integer"
3086 [(set (match_operand:TF 0 "push_operand" "=<,<")
3087 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3091 switch (which_alternative)
3094 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3095 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3096 operands[2] = stack_pointer_rtx;
3097 operands[3] = GEN_INT (16);
3099 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3100 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3102 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3104 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3105 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3107 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3116 [(set_attr "type" "multi")
3117 (set_attr "mode" "XF,SI")])
3120 [(set (match_operand 0 "push_operand" "")
3121 (match_operand 1 "general_operand" ""))]
3123 && (GET_MODE (operands[0]) == XFmode
3124 || GET_MODE (operands[0]) == TFmode
3125 || GET_MODE (operands[0]) == DFmode)
3126 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3128 "if (!ix86_split_long_move (operands)) abort (); DONE;")
3131 [(set (match_operand:XF 0 "push_operand" "")
3132 (match_operand:XF 1 "register_operand" ""))]
3133 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3134 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3135 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3138 [(set (match_operand:TF 0 "push_operand" "")
3139 (match_operand:TF 1 "register_operand" ""))]
3140 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3141 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3142 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3145 [(set (match_operand:TF 0 "push_operand" "")
3146 (match_operand:TF 1 "register_operand" ""))]
3147 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3148 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3149 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3151 ;; Do not use integer registers when optimizing for size
3152 (define_insn "*movxf_nointeger"
3153 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3154 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3155 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3158 && (reload_in_progress || reload_completed
3159 || GET_CODE (operands[1]) != CONST_DOUBLE
3160 || memory_operand (operands[0], XFmode))"
3163 switch (which_alternative)
3166 if (REG_P (operands[1])
3167 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3168 return \"fstp\\t%y0\";
3169 else if (STACK_TOP_P (operands[0]))
3170 return \"fld%z1\\t%y1\";
3172 return \"fst\\t%y0\";
3175 /* There is no non-popping store to memory for XFmode. So if
3176 we need one, follow the store with a load. */
3177 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3178 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3180 return \"fstp%z0\\t%y0\";
3183 switch (standard_80387_constant_p (operands[1]))
3197 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3198 (set_attr "mode" "XF,XF,XF,SI,SI")])
3200 (define_insn "*movtf_nointeger"
3201 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3202 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3203 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3205 && (reload_in_progress || reload_completed
3206 || GET_CODE (operands[1]) != CONST_DOUBLE
3207 || memory_operand (operands[0], TFmode))"
3210 switch (which_alternative)
3213 if (REG_P (operands[1])
3214 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3215 return \"fstp\\t%y0\";
3216 else if (STACK_TOP_P (operands[0]))
3217 return \"fld%z1\\t%y1\";
3219 return \"fst\\t%y0\";
3222 /* There is no non-popping store to memory for XFmode. So if
3223 we need one, follow the store with a load. */
3224 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3225 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3227 return \"fstp%z0\\t%y0\";
3230 switch (standard_80387_constant_p (operands[1]))
3244 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3245 (set_attr "mode" "XF,XF,XF,SI,SI")])
3247 (define_insn "*movxf_integer"
3248 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3249 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3250 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3253 && (reload_in_progress || reload_completed
3254 || GET_CODE (operands[1]) != CONST_DOUBLE
3255 || memory_operand (operands[0], XFmode))"
3258 switch (which_alternative)
3261 if (REG_P (operands[1])
3262 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3263 return \"fstp\\t%y0\";
3264 else if (STACK_TOP_P (operands[0]))
3265 return \"fld%z1\\t%y1\";
3267 return \"fst\\t%y0\";
3270 /* There is no non-popping store to memory for XFmode. So if
3271 we need one, follow the store with a load. */
3272 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3273 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3275 return \"fstp%z0\\t%y0\";
3278 switch (standard_80387_constant_p (operands[1]))
3292 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3293 (set_attr "mode" "XF,XF,XF,SI,SI")])
3295 (define_insn "*movtf_integer"
3296 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3297 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3298 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3300 && (reload_in_progress || reload_completed
3301 || GET_CODE (operands[1]) != CONST_DOUBLE
3302 || memory_operand (operands[0], TFmode))"
3305 switch (which_alternative)
3308 if (REG_P (operands[1])
3309 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3310 return \"fstp\\t%y0\";
3311 else if (STACK_TOP_P (operands[0]))
3312 return \"fld%z1\\t%y1\";
3314 return \"fst\\t%y0\";
3317 /* There is no non-popping store to memory for XFmode. So if
3318 we need one, follow the store with a load. */
3319 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3320 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3322 return \"fstp%z0\\t%y0\";
3325 switch (standard_80387_constant_p (operands[1]))
3339 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3340 (set_attr "mode" "XF,XF,XF,SI,SI")])
3343 [(set (match_operand 0 "nonimmediate_operand" "")
3344 (match_operand 1 "general_operand" ""))]
3346 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3347 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3348 && ! (ANY_FP_REG_P (operands[0]) ||
3349 (GET_CODE (operands[0]) == SUBREG
3350 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3351 && ! (ANY_FP_REG_P (operands[1]) ||
3352 (GET_CODE (operands[1]) == SUBREG
3353 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3354 [(set (match_dup 2) (match_dup 5))
3355 (set (match_dup 3) (match_dup 6))
3356 (set (match_dup 4) (match_dup 7))]
3357 "if (ix86_split_long_move (operands)) DONE;")
3360 [(set (match_operand 0 "register_operand" "")
3361 (match_operand 1 "memory_operand" ""))]
3363 && GET_CODE (operands[1]) == MEM
3364 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3365 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3366 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3367 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3368 && (!(SSE_REG_P (operands[0]) ||
3369 (GET_CODE (operands[0]) == SUBREG
3370 && SSE_REG_P (SUBREG_REG (operands[0]))))
3371 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3372 && (!(FP_REG_P (operands[0]) ||
3373 (GET_CODE (operands[0]) == SUBREG
3374 && FP_REG_P (SUBREG_REG (operands[0]))))
3375 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3378 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3380 (define_insn "swapxf"
3381 [(set (match_operand:XF 0 "register_operand" "+f")
3382 (match_operand:XF 1 "register_operand" "+f"))
3388 if (STACK_TOP_P (operands[0]))
3389 return \"fxch\\t%1\";
3391 return \"fxch\\t%0\";
3393 [(set_attr "type" "fxch")
3394 (set_attr "mode" "XF")])
3396 (define_insn "swaptf"
3397 [(set (match_operand:TF 0 "register_operand" "+f")
3398 (match_operand:TF 1 "register_operand" "+f"))
3404 if (STACK_TOP_P (operands[0]))
3405 return \"fxch\\t%1\";
3407 return \"fxch\\t%0\";
3409 [(set_attr "type" "fxch")
3410 (set_attr "mode" "XF")])
3412 ;; Zero extension instructions
3414 (define_expand "zero_extendhisi2"
3415 [(set (match_operand:SI 0 "register_operand" "")
3416 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3420 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3422 operands[1] = force_reg (HImode, operands[1]);
3423 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3428 (define_insn "zero_extendhisi2_and"
3429 [(set (match_operand:SI 0 "register_operand" "=r")
3430 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3431 (clobber (reg:CC 17))]
3432 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3434 [(set_attr "type" "alu1")
3435 (set_attr "mode" "SI")])
3438 [(set (match_operand:SI 0 "register_operand" "")
3439 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3440 (clobber (reg:CC 17))]
3441 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3442 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3443 (clobber (reg:CC 17))])]
3446 (define_insn "*zero_extendhisi2_movzwl"
3447 [(set (match_operand:SI 0 "register_operand" "=r")
3448 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3449 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3450 "movz{wl|x}\\t{%1, %0|%0, %1}"
3451 [(set_attr "type" "imovx")
3452 (set_attr "mode" "SI")])
3454 (define_expand "zero_extendqihi2"
3456 [(set (match_operand:HI 0 "register_operand" "")
3457 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3458 (clobber (reg:CC 17))])]
3462 (define_insn "*zero_extendqihi2_and"
3463 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3464 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3465 (clobber (reg:CC 17))]
3466 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3468 [(set_attr "type" "alu1")
3469 (set_attr "mode" "HI")])
3471 (define_insn "*zero_extendqihi2_movzbw_and"
3472 [(set (match_operand:HI 0 "register_operand" "=r,r")
3473 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3474 (clobber (reg:CC 17))]
3475 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3477 [(set_attr "type" "imovx,alu1")
3478 (set_attr "mode" "HI")])
3480 (define_insn "*zero_extendqihi2_movzbw"
3481 [(set (match_operand:HI 0 "register_operand" "=r")
3482 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3483 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3484 "movz{bw|x}\\t{%1, %0|%0, %1}"
3485 [(set_attr "type" "imovx")
3486 (set_attr "mode" "HI")])
3488 ;; For the movzbw case strip only the clobber
3490 [(set (match_operand:HI 0 "register_operand" "")
3491 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3492 (clobber (reg:CC 17))]
3494 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3495 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3496 [(set (match_operand:HI 0 "register_operand" "")
3497 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3499 ;; When source and destination does not overlap, clear destination
3500 ;; first and then do the movb
3502 [(set (match_operand:HI 0 "register_operand" "")
3503 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3504 (clobber (reg:CC 17))]
3506 && ANY_QI_REG_P (operands[0])
3507 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3508 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3509 [(set (match_dup 0) (const_int 0))
3510 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3511 "operands[2] = gen_lowpart (QImode, operands[0]);")
3513 ;; Rest is handled by single and.
3515 [(set (match_operand:HI 0 "register_operand" "")
3516 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3517 (clobber (reg:CC 17))]
3519 && true_regnum (operands[0]) == true_regnum (operands[1])"
3520 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3521 (clobber (reg:CC 17))])]
3524 (define_expand "zero_extendqisi2"
3526 [(set (match_operand:SI 0 "register_operand" "")
3527 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3528 (clobber (reg:CC 17))])]
3532 (define_insn "*zero_extendqisi2_and"
3533 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3534 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3535 (clobber (reg:CC 17))]
3536 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3538 [(set_attr "type" "alu1")
3539 (set_attr "mode" "SI")])
3541 (define_insn "*zero_extendqisi2_movzbw_and"
3542 [(set (match_operand:SI 0 "register_operand" "=r,r")
3543 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3544 (clobber (reg:CC 17))]
3545 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3547 [(set_attr "type" "imovx,alu1")
3548 (set_attr "mode" "SI")])
3550 (define_insn "*zero_extendqisi2_movzbw"
3551 [(set (match_operand:SI 0 "register_operand" "=r")
3552 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3553 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3554 "movz{bl|x}\\t{%1, %0|%0, %1}"
3555 [(set_attr "type" "imovx")
3556 (set_attr "mode" "SI")])
3558 ;; For the movzbl case strip only the clobber
3560 [(set (match_operand:SI 0 "register_operand" "")
3561 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3562 (clobber (reg:CC 17))]
3564 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3565 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3567 (zero_extend:SI (match_dup 1)))])
3569 ;; When source and destination does not overlap, clear destination
3570 ;; first and then do the movb
3572 [(set (match_operand:SI 0 "register_operand" "")
3573 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3574 (clobber (reg:CC 17))]
3576 && ANY_QI_REG_P (operands[0])
3577 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3578 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3579 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3580 [(set (match_dup 0) (const_int 0))
3581 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3582 "operands[2] = gen_lowpart (QImode, operands[0]);")
3584 ;; Rest is handled by single and.
3586 [(set (match_operand:SI 0 "register_operand" "")
3587 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3588 (clobber (reg:CC 17))]
3590 && true_regnum (operands[0]) == true_regnum (operands[1])"
3591 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3592 (clobber (reg:CC 17))])]
3595 ;; %%% Kill me once multi-word ops are sane.
3596 (define_expand "zero_extendsidi2"
3597 [(set (match_operand:DI 0 "register_operand" "=r")
3598 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3602 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3607 (define_insn "zero_extendsidi2_32"
3608 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3609 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3610 (clobber (reg:CC 17))]
3613 [(set_attr "mode" "SI")])
3615 (define_insn "zero_extendsidi2_rex64"
3616 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3617 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3620 mov\\t{%k1, %k0|%k0, %k1}
3622 [(set_attr "type" "imovx,imov")
3623 (set_attr "mode" "SI,DI")])
3626 [(set (match_operand:DI 0 "memory_operand" "")
3627 (zero_extend:DI (match_dup 0)))]
3629 [(set (match_dup 4) (const_int 0))]
3630 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3633 [(set (match_operand:DI 0 "register_operand" "")
3634 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3635 (clobber (reg:CC 17))]
3636 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
3638 [(set (match_dup 4) (const_int 0))]
3639 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3642 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3643 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3644 (clobber (reg:CC 17))]
3645 "reload_completed && !TARGET_64BIT"
3646 [(set (match_dup 3) (match_dup 1))
3647 (set (match_dup 4) (const_int 0))]
3648 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3650 (define_insn "zero_extendhidi2"
3651 [(set (match_operand:DI 0 "register_operand" "=r,r")
3652 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3655 movz{wl|x}\\t{%1, %k0|%k0, %1}
3656 movz{wq|x}\\t{%1, %0|%0, %1}"
3657 [(set_attr "type" "imovx")
3658 (set_attr "mode" "SI,DI")])
3660 (define_insn "zero_extendqidi2"
3661 [(set (match_operand:DI 0 "register_operand" "=r,r")
3662 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3665 movz{bl|x}\\t{%1, %k0|%k0, %1}
3666 movz{bq|x}\\t{%1, %0|%0, %1}"
3667 [(set_attr "type" "imovx")
3668 (set_attr "mode" "SI,DI")])
3670 ;; Sign extension instructions
3672 (define_expand "extendsidi2"
3673 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3674 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3675 (clobber (reg:CC 17))
3676 (clobber (match_scratch:SI 2 ""))])]
3682 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3687 (define_insn "*extendsidi2_1"
3688 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3689 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3690 (clobber (reg:CC 17))
3691 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3695 (define_insn "extendsidi2_rex64"
3696 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3697 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3701 movs{lq|x}\\t{%1,%0|%0, %1}"
3702 [(set_attr "type" "imovx")
3703 (set_attr "mode" "DI")
3704 (set_attr "prefix_0f" "0")
3705 (set_attr "modrm" "0,1")])
3707 (define_insn "extendhidi2"
3708 [(set (match_operand:DI 0 "register_operand" "=r")
3709 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3711 "movs{wq|x}\\t{%1,%0|%0, %1}"
3712 [(set_attr "type" "imovx")
3713 (set_attr "mode" "DI")])
3715 (define_insn "extendqidi2"
3716 [(set (match_operand:DI 0 "register_operand" "=r")
3717 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3719 "movs{bq|x}\\t{%1,%0|%0, %1}"
3720 [(set_attr "type" "imovx")
3721 (set_attr "mode" "DI")])
3723 ;; Extend to memory case when source register does die.
3725 [(set (match_operand:DI 0 "memory_operand" "")
3726 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3727 (clobber (reg:CC 17))
3728 (clobber (match_operand:SI 2 "register_operand" ""))]
3730 && dead_or_set_p (insn, operands[1])
3731 && !reg_mentioned_p (operands[1], operands[0]))"
3732 [(set (match_dup 3) (match_dup 1))
3733 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3734 (clobber (reg:CC 17))])
3735 (set (match_dup 4) (match_dup 1))]
3736 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3738 ;; Extend to memory case when source register does not die.
3740 [(set (match_operand:DI 0 "memory_operand" "")
3741 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3742 (clobber (reg:CC 17))
3743 (clobber (match_operand:SI 2 "register_operand" ""))]
3748 split_di (&operands[0], 1, &operands[3], &operands[4]);
3750 emit_move_insn (operands[3], operands[1]);
3752 /* Generate a cltd if possible and doing so it profitable. */
3753 if (true_regnum (operands[1]) == 0
3754 && true_regnum (operands[2]) == 1
3755 && (optimize_size || TARGET_USE_CLTD))
3757 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3761 emit_move_insn (operands[2], operands[1]);
3762 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3764 emit_move_insn (operands[4], operands[2]);
3768 ;; Extend to register case. Optimize case where source and destination
3769 ;; registers match and cases where we can use cltd.
3771 [(set (match_operand:DI 0 "register_operand" "")
3772 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3773 (clobber (reg:CC 17))
3774 (clobber (match_scratch:SI 2 ""))]
3779 split_di (&operands[0], 1, &operands[3], &operands[4]);
3781 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3782 emit_move_insn (operands[3], operands[1]);
3784 /* Generate a cltd if possible and doing so it profitable. */
3785 if (true_regnum (operands[3]) == 0
3786 && (optimize_size || TARGET_USE_CLTD))
3788 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3792 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3793 emit_move_insn (operands[4], operands[1]);
3795 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3799 (define_insn "extendhisi2"
3800 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3801 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3805 switch (get_attr_prefix_0f (insn))
3808 return \"{cwtl|cwde}\";
3810 return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
3813 [(set_attr "type" "imovx")
3814 (set_attr "mode" "SI")
3815 (set (attr "prefix_0f")
3816 ;; movsx is short decodable while cwtl is vector decoded.
3817 (if_then_else (and (eq_attr "cpu" "!k6")
3818 (eq_attr "alternative" "0"))
3820 (const_string "1")))
3822 (if_then_else (eq_attr "prefix_0f" "0")
3824 (const_string "1")))])
3826 (define_insn "*extendhisi2_zext"
3827 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3829 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3833 switch (get_attr_prefix_0f (insn))
3836 return \"{cwtl|cwde}\";
3838 return \"movs{wl|x}\\t{%1,%k0|%k0, %1}\";
3841 [(set_attr "type" "imovx")
3842 (set_attr "mode" "SI")
3843 (set (attr "prefix_0f")
3844 ;; movsx is short decodable while cwtl is vector decoded.
3845 (if_then_else (and (eq_attr "cpu" "!k6")
3846 (eq_attr "alternative" "0"))
3848 (const_string "1")))
3850 (if_then_else (eq_attr "prefix_0f" "0")
3852 (const_string "1")))])
3854 (define_insn "extendqihi2"
3855 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3856 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3860 switch (get_attr_prefix_0f (insn))
3863 return \"{cbtw|cbw}\";
3865 return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
3868 [(set_attr "type" "imovx")
3869 (set_attr "mode" "HI")
3870 (set (attr "prefix_0f")
3871 ;; movsx is short decodable while cwtl is vector decoded.
3872 (if_then_else (and (eq_attr "cpu" "!k6")
3873 (eq_attr "alternative" "0"))
3875 (const_string "1")))
3877 (if_then_else (eq_attr "prefix_0f" "0")
3879 (const_string "1")))])
3881 (define_insn "extendqisi2"
3882 [(set (match_operand:SI 0 "register_operand" "=r")
3883 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3885 "movs{bl|x}\\t{%1,%0|%0, %1}"
3886 [(set_attr "type" "imovx")
3887 (set_attr "mode" "SI")])
3889 (define_insn "*extendqisi2_zext"
3890 [(set (match_operand:DI 0 "register_operand" "=r")
3892 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3894 "movs{bl|x}\\t{%1,%k0|%k0, %1}"
3895 [(set_attr "type" "imovx")
3896 (set_attr "mode" "SI")])
3898 ;; Conversions between float and double.
3900 ;; These are all no-ops in the model used for the 80387. So just
3903 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3904 (define_insn "*dummy_extendsfdf2"
3905 [(set (match_operand:DF 0 "push_operand" "=<")
3906 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3911 [(set (match_operand:DF 0 "push_operand" "")
3912 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3913 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3914 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3915 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3918 [(set (match_operand:DF 0 "push_operand" "")
3919 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3920 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3921 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3922 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3924 (define_insn "*dummy_extendsfxf2"
3925 [(set (match_operand:XF 0 "push_operand" "=<")
3926 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3931 [(set (match_operand:XF 0 "push_operand" "")
3932 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3933 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3934 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3935 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3937 (define_insn "*dummy_extendsftf2"
3938 [(set (match_operand:TF 0 "push_operand" "=<")
3939 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3944 [(set (match_operand:TF 0 "push_operand" "")
3945 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3946 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3947 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3948 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3951 [(set (match_operand:TF 0 "push_operand" "")
3952 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3953 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3954 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3955 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3957 (define_insn "*dummy_extenddfxf2"
3958 [(set (match_operand:XF 0 "push_operand" "=<")
3959 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3964 [(set (match_operand:XF 0 "push_operand" "")
3965 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
3966 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3967 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3968 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3970 (define_insn "*dummy_extenddftf2"
3971 [(set (match_operand:TF 0 "push_operand" "=<")
3972 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3977 [(set (match_operand:TF 0 "push_operand" "")
3978 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3979 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3980 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3981 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3984 [(set (match_operand:TF 0 "push_operand" "")
3985 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3986 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3987 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3988 (set (mem:TF (reg:DI 7)) (float_extend:XF (match_dup 1)))])
3990 (define_expand "extendsfdf2"
3991 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3992 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3993 "TARGET_80387 || TARGET_SSE2"
3996 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3997 operands[1] = force_reg (SFmode, operands[1]);
4000 (define_insn "*extendsfdf2_1"
4001 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4002 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4003 "(TARGET_80387 || TARGET_SSE2)
4004 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4007 switch (which_alternative)
4010 if (REG_P (operands[1])
4011 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4012 return \"fstp\\t%y0\";
4013 else if (STACK_TOP_P (operands[0]))
4014 return \"fld%z1\\t%y1\";
4016 return \"fst\\t%y0\";
4019 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4020 return \"fstp%z0\\t%y0\";
4023 return \"fst%z0\\t%y0\";
4025 return \"cvtss2sd\\t{%1, %0|%0, %1}\";
4031 [(set_attr "type" "fmov,fmov,sse")
4032 (set_attr "mode" "SF,XF,DF")])
4034 (define_insn "*extendsfdf2_1_sse_only"
4035 [(set (match_operand:DF 0 "register_operand" "=Y")
4036 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4037 "!TARGET_80387 && TARGET_SSE2
4038 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4039 "cvtss2sd\\t{%1, %0|%0, %1}"
4040 [(set_attr "type" "sse")
4041 (set_attr "mode" "DF")])
4043 (define_expand "extendsfxf2"
4044 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4045 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4046 "TARGET_80387 && !TARGET_64BIT"
4049 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4050 operands[1] = force_reg (SFmode, operands[1]);
4053 (define_insn "*extendsfxf2_1"
4054 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4055 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4056 "TARGET_80387 && !TARGET_64BIT
4057 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4060 switch (which_alternative)
4063 if (REG_P (operands[1])
4064 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4065 return \"fstp\\t%y0\";
4066 else if (STACK_TOP_P (operands[0]))
4067 return \"fld%z1\\t%y1\";
4069 return \"fst\\t%y0\";
4072 /* There is no non-popping store to memory for XFmode. So if
4073 we need one, follow the store with a load. */
4074 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4075 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4077 return \"fstp%z0\\t%y0\";
4083 [(set_attr "type" "fmov")
4084 (set_attr "mode" "SF,XF")])
4086 (define_expand "extendsftf2"
4087 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4088 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4092 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4093 operands[1] = force_reg (SFmode, operands[1]);
4096 (define_insn "*extendsftf2_1"
4097 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4098 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4100 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4103 switch (which_alternative)
4106 if (REG_P (operands[1])
4107 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4108 return \"fstp\\t%y0\";
4109 else if (STACK_TOP_P (operands[0]))
4110 return \"fld%z1\\t%y1\";
4112 return \"fst\\t%y0\";
4115 /* There is no non-popping store to memory for XFmode. So if
4116 we need one, follow the store with a load. */
4117 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4118 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4120 return \"fstp%z0\\t%y0\";
4126 [(set_attr "type" "fmov")
4127 (set_attr "mode" "SF,XF")])
4129 (define_expand "extenddfxf2"
4130 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4131 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4132 "TARGET_80387 && !TARGET_64BIT"
4135 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4136 operands[1] = force_reg (DFmode, operands[1]);
4139 (define_insn "*extenddfxf2_1"
4140 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4141 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4142 "TARGET_80387 && !TARGET_64BIT
4143 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4146 switch (which_alternative)
4149 if (REG_P (operands[1])
4150 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4151 return \"fstp\\t%y0\";
4152 else if (STACK_TOP_P (operands[0]))
4153 return \"fld%z1\\t%y1\";
4155 return \"fst\\t%y0\";
4158 /* There is no non-popping store to memory for XFmode. So if
4159 we need one, follow the store with a load. */
4160 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4161 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4163 return \"fstp%z0\\t%y0\";
4169 [(set_attr "type" "fmov")
4170 (set_attr "mode" "DF,XF")])
4172 (define_expand "extenddftf2"
4173 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4174 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4178 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4179 operands[1] = force_reg (DFmode, operands[1]);
4182 (define_insn "*extenddftf2_1"
4183 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4184 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4186 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4189 switch (which_alternative)
4192 if (REG_P (operands[1])
4193 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4194 return \"fstp\\t%y0\";
4195 else if (STACK_TOP_P (operands[0]))
4196 return \"fld%z1\\t%y1\";
4198 return \"fst\\t%y0\";
4201 /* There is no non-popping store to memory for XFmode. So if
4202 we need one, follow the store with a load. */
4203 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4204 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4206 return \"fstp%z0\\t%y0\";
4212 [(set_attr "type" "fmov")
4213 (set_attr "mode" "DF,XF")])
4215 ;; %%% This seems bad bad news.
4216 ;; This cannot output into an f-reg because there is no way to be sure
4217 ;; of truncating in that case. Otherwise this is just like a simple move
4218 ;; insn. So we pretend we can output to a reg in order to get better
4219 ;; register preferencing, but we really use a stack slot.
4221 (define_expand "truncdfsf2"
4222 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4224 (match_operand:DF 1 "register_operand" "")))
4225 (clobber (match_dup 2))])]
4226 "TARGET_80387 || TARGET_SSE2"
4229 operands[2] = assign_386_stack_local (SFmode, 0);
4232 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4237 (define_insn "*truncdfsf2_1"
4238 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f")
4240 (match_operand:DF 1 "register_operand" "f,0")))
4241 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
4242 "TARGET_80387 && !TARGET_SSE2"
4245 switch (which_alternative)
4248 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4249 return \"fstp%z0\\t%y0\";
4251 return \"fst%z0\\t%y0\";
4253 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4257 [(set_attr "type" "fmov,multi")
4258 (set_attr "mode" "SF,SF")])
4260 (define_insn "*truncdfsf2_1_sse"
4261 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f,Y")
4263 (match_operand:DF 1 "nonimmediate_operand" "f,0,mY")))
4264 (clobber (match_operand:SF 2 "memory_operand" "=X,m,X"))]
4265 "TARGET_80387 && TARGET_SSE2"
4268 switch (which_alternative)
4271 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4272 return \"fstp%z0\\t%y0\";
4274 return \"fst%z0\\t%y0\";
4276 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4279 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4283 [(set_attr "type" "fmov,multi,sse")
4284 (set_attr "mode" "SF,SF,DF")])
4286 (define_insn "*truncdfsf2_2"
4287 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4289 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4290 "TARGET_80387 && TARGET_SSE2
4291 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4294 switch (which_alternative)
4297 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4299 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4300 return \"fstp%z0\\t%y0\";
4302 return \"fst%z0\\t%y0\";
4305 [(set_attr "type" "sse,fmov")
4306 (set_attr "mode" "DF,SF")])
4308 (define_insn "truncdfsf2_3"
4309 [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
4311 (match_operand:DF 1 "register_operand" "f")))]
4315 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4316 return \"fstp%z0\\t%y0\";
4318 return \"fst%z0\\t%y0\";
4320 [(set_attr "type" "fmov")
4321 (set_attr "mode" "SF")])
4323 (define_insn "truncdfsf2_sse_only"
4324 [(set (match_operand:SF 0 "register_operand" "=Y")
4326 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4327 "!TARGET_80387 && TARGET_SSE2"
4328 "cvtsd2ss\\t{%1, %0|%0, %1}"
4329 [(set_attr "type" "sse")
4330 (set_attr "mode" "DF")])
4333 [(set (match_operand:SF 0 "memory_operand" "")
4335 (match_operand:DF 1 "register_operand" "")))
4336 (clobber (match_operand:SF 2 "memory_operand" ""))]
4338 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4342 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4344 (match_operand:DF 1 "nonimmediate_operand" "")))
4345 (clobber (match_operand 2 "" ""))]
4346 "TARGET_80387 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4347 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4351 [(set (match_operand:SF 0 "register_operand" "")
4353 (match_operand:DF 1 "register_operand" "")))
4354 (clobber (match_operand:SF 2 "memory_operand" ""))]
4355 "TARGET_80387 && reload_completed
4356 && FP_REG_P (operands[0])"
4357 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4358 (set (match_dup 0) (match_dup 2))]
4361 (define_expand "truncxfsf2"
4362 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4364 (match_operand:XF 1 "register_operand" "")))
4365 (clobber (match_dup 2))])]
4366 "TARGET_80387 && !TARGET_64BIT"
4367 "operands[2] = assign_386_stack_local (SFmode, 0);")
4369 (define_insn "*truncxfsf2_1"
4370 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f")
4372 (match_operand:XF 1 "register_operand" "f,0")))
4373 (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
4374 "TARGET_80387 && !TARGET_64BIT"
4377 switch (which_alternative)
4380 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4381 return \"fstp%z0\\t%y0\";
4383 return \"fst%z0\\t%y0\";
4385 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4389 [(set_attr "type" "fmov,multi")
4390 (set_attr "mode" "SF")])
4392 (define_insn "*truncxfsf2_2"
4393 [(set (match_operand:SF 0 "memory_operand" "=m")
4395 (match_operand:XF 1 "register_operand" "f")))]
4396 "TARGET_80387 && !TARGET_64BIT"
4399 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4400 return \"fstp%z0\\t%y0\";
4402 return \"fst%z0\\t%y0\";
4404 [(set_attr "type" "fmov")
4405 (set_attr "mode" "SF")])
4408 [(set (match_operand:SF 0 "memory_operand" "")
4410 (match_operand:XF 1 "register_operand" "")))
4411 (clobber (match_operand:SF 2 "memory_operand" ""))]
4413 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4417 [(set (match_operand:SF 0 "register_operand" "")
4419 (match_operand:XF 1 "register_operand" "")))
4420 (clobber (match_operand:SF 2 "memory_operand" ""))]
4421 "TARGET_80387 && reload_completed"
4422 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4423 (set (match_dup 0) (match_dup 2))]
4426 (define_expand "trunctfsf2"
4427 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4429 (match_operand:TF 1 "register_operand" "")))
4430 (clobber (match_dup 2))])]
4432 "operands[2] = assign_386_stack_local (SFmode, 0);")
4434 (define_insn "*trunctfsf2_1"
4435 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f")
4437 (match_operand:TF 1 "register_operand" "f,0")))
4438 (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
4442 switch (which_alternative)
4445 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4446 return \"fstp%z0\\t%y0\";
4448 return \"fst%z0\\t%y0\";
4450 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4454 [(set_attr "type" "fmov,multi")
4455 (set_attr "mode" "SF")])
4457 (define_insn "*trunctfsf2_2"
4458 [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
4460 (match_operand:TF 1 "register_operand" "f")))]
4464 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4465 return \"fstp%z0\\t%y0\";
4467 return \"fst%z0\\t%y0\";
4469 [(set_attr "type" "fmov")
4470 (set_attr "mode" "SF")])
4473 [(set (match_operand:SF 0 "memory_operand" "")
4475 (match_operand:TF 1 "register_operand" "")))
4476 (clobber (match_operand:SF 2 "memory_operand" ""))]
4478 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4482 [(set (match_operand:SF 0 "register_operand" "")
4484 (match_operand:TF 1 "register_operand" "")))
4485 (clobber (match_operand:SF 2 "memory_operand" ""))]
4486 "TARGET_80387 && reload_completed"
4487 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4488 (set (match_dup 0) (match_dup 2))]
4492 (define_expand "truncxfdf2"
4493 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4495 (match_operand:XF 1 "register_operand" "")))
4496 (clobber (match_dup 2))])]
4497 "TARGET_80387 && !TARGET_64BIT"
4498 "operands[2] = assign_386_stack_local (DFmode, 0);")
4500 (define_insn "*truncxfdf2_1"
4501 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,f")
4503 (match_operand:XF 1 "register_operand" "f,0")))
4504 (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
4505 "TARGET_80387 && !TARGET_64BIT"
4508 switch (which_alternative)
4511 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4512 return \"fstp%z0\\t%y0\";
4514 return \"fst%z0\\t%y0\";
4516 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4520 [(set_attr "type" "fmov,multi")
4521 (set_attr "mode" "DF")])
4523 (define_insn "*truncxfdf2_2"
4524 [(set (match_operand:DF 0 "memory_operand" "=m")
4526 (match_operand:XF 1 "register_operand" "f")))]
4527 "TARGET_80387 && !TARGET_64BIT"
4530 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4531 return \"fstp%z0\\t%y0\";
4533 return \"fst%z0\\t%y0\";
4535 [(set_attr "type" "fmov")
4536 (set_attr "mode" "DF")])
4539 [(set (match_operand:DF 0 "memory_operand" "")
4541 (match_operand:XF 1 "register_operand" "")))
4542 (clobber (match_operand:DF 2 "memory_operand" ""))]
4544 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4548 [(set (match_operand:DF 0 "register_operand" "")
4550 (match_operand:XF 1 "register_operand" "")))
4551 (clobber (match_operand:DF 2 "memory_operand" ""))]
4552 "TARGET_80387 && reload_completed"
4553 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4554 (set (match_dup 0) (match_dup 2))]
4557 (define_expand "trunctfdf2"
4558 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4560 (match_operand:TF 1 "register_operand" "")))
4561 (clobber (match_dup 2))])]
4563 "operands[2] = assign_386_stack_local (DFmode, 0);")
4565 (define_insn "*trunctfdf2_1"
4566 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,f")
4568 (match_operand:TF 1 "register_operand" "f,0")))
4569 (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
4573 switch (which_alternative)
4576 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4577 return \"fstp%z0\\t%y0\";
4579 return \"fst%z0\\t%y0\";
4581 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4585 [(set_attr "type" "fmov,multi")
4586 (set_attr "mode" "DF")])
4588 (define_insn "*trunctfdf2_2"
4589 [(set (match_operand:DF 0 "memory_operand" "=m")
4591 (match_operand:TF 1 "register_operand" "f")))]
4595 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4596 return \"fstp%z0\\t%y0\";
4598 return \"fst%z0\\t%y0\";
4600 [(set_attr "type" "fmov")
4601 (set_attr "mode" "DF")])
4604 [(set (match_operand:DF 0 "memory_operand" "")
4606 (match_operand:TF 1 "register_operand" "")))
4607 (clobber (match_operand:DF 2 "memory_operand" ""))]
4609 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4613 [(set (match_operand:DF 0 "register_operand" "")
4615 (match_operand:TF 1 "register_operand" "")))
4616 (clobber (match_operand:DF 2 "memory_operand" ""))]
4617 "TARGET_80387 && reload_completed"
4618 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4619 (set (match_dup 0) (match_dup 2))]
4623 ;; %%% Break up all these bad boys.
4625 ;; Signed conversion to DImode.
4627 (define_expand "fix_truncxfdi2"
4628 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4629 (fix:DI (match_operand:XF 1 "register_operand" "")))
4630 (clobber (match_dup 2))
4631 (clobber (match_dup 3))
4632 (clobber (match_scratch:SI 4 ""))
4633 (clobber (match_scratch:XF 5 ""))])]
4634 "TARGET_80387 && !TARGET_64BIT"
4635 "operands[2] = assign_386_stack_local (SImode, 0);
4636 operands[3] = assign_386_stack_local (DImode, 1);")
4638 (define_expand "fix_trunctfdi2"
4639 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4640 (fix:DI (match_operand:TF 1 "register_operand" "")))
4641 (clobber (match_dup 2))
4642 (clobber (match_dup 3))
4643 (clobber (match_scratch:SI 4 ""))
4644 (clobber (match_scratch:TF 5 ""))])]
4646 "operands[2] = assign_386_stack_local (SImode, 0);
4647 operands[3] = assign_386_stack_local (DImode, 1);")
4649 (define_expand "fix_truncdfdi2"
4650 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4651 (fix:DI (match_operand:DF 1 "register_operand" "")))
4652 (clobber (match_dup 2))
4653 (clobber (match_dup 3))
4654 (clobber (match_scratch:SI 4 ""))
4655 (clobber (match_scratch:DF 5 ""))])]
4657 "operands[2] = assign_386_stack_local (SImode, 0);
4658 operands[3] = assign_386_stack_local (DImode, 1);")
4660 (define_expand "fix_truncsfdi2"
4661 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4662 (fix:DI (match_operand:SF 1 "register_operand" "")))
4663 (clobber (match_dup 2))
4664 (clobber (match_dup 3))
4665 (clobber (match_scratch:SI 4 ""))
4666 (clobber (match_scratch:SF 5 ""))])]
4668 "operands[2] = assign_386_stack_local (SImode, 0);
4669 operands[3] = assign_386_stack_local (DImode, 1);")
4671 (define_insn "*fix_truncdi_1"
4672 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4673 (fix:DI (match_operand 1 "register_operand" "f,f")))
4674 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4675 (clobber (match_operand:DI 3 "memory_operand" "=m,m"))
4676 (clobber (match_scratch:SI 4 "=&r,&r"))
4677 (clobber (match_scratch 5 "=&f,&f"))]
4678 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))"
4679 "* return output_fix_trunc (insn, operands);"
4680 [(set_attr "type" "multi")])
4683 [(set (match_operand:DI 0 "register_operand" "")
4684 (fix:DI (match_operand 1 "register_operand" "")))
4685 (clobber (match_operand:SI 2 "memory_operand" ""))
4686 (clobber (match_operand:DI 3 "memory_operand" ""))
4687 (clobber (match_scratch:SI 4 ""))
4688 (clobber (match_scratch 5 ""))]
4689 "reload_completed && !reg_overlap_mentioned_p (operands[4], operands[3])"
4690 [(parallel [(set (match_dup 3) (fix:DI (match_dup 1)))
4691 (clobber (match_dup 2))
4692 (clobber (match_dup 3))
4693 (clobber (match_dup 4))
4694 (clobber (match_dup 5))])
4695 (set (match_dup 0) (match_dup 3))]
4698 ;; Signed conversion to SImode.
4700 (define_expand "fix_truncxfsi2"
4701 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4702 (fix:SI (match_operand:XF 1 "register_operand" "")))
4703 (clobber (match_dup 2))
4704 (clobber (match_dup 3))
4705 (clobber (match_scratch:SI 4 ""))])]
4706 "TARGET_80387 && !TARGET_64BIT"
4707 "operands[2] = assign_386_stack_local (SImode, 0);
4708 operands[3] = assign_386_stack_local (SImode, 1);")
4710 (define_expand "fix_trunctfsi2"
4711 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4712 (fix:SI (match_operand:TF 1 "register_operand" "")))
4713 (clobber (match_dup 2))
4714 (clobber (match_dup 3))
4715 (clobber (match_scratch:SI 4 ""))])]
4717 "operands[2] = assign_386_stack_local (SImode, 0);
4718 operands[3] = assign_386_stack_local (SImode, 1);")
4720 (define_expand "fix_truncdfsi2"
4721 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4722 (fix:SI (match_operand:DF 1 "register_operand" "")))
4723 (clobber (match_dup 2))
4724 (clobber (match_dup 3))
4725 (clobber (match_scratch:SI 4 ""))])]
4726 "TARGET_80387 || TARGET_SSE2"
4731 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4732 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4733 if (out != operands[0])
4734 emit_move_insn (operands[0], out);
4739 operands[2] = assign_386_stack_local (SImode, 0);
4740 operands[3] = assign_386_stack_local (SImode, 1);
4744 (define_expand "fix_truncsfsi2"
4745 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4746 (fix:SI (match_operand:SF 1 "register_operand" "")))
4747 (clobber (match_dup 2))
4748 (clobber (match_dup 3))
4749 (clobber (match_scratch:SI 4 ""))])]
4750 "TARGET_80387 || TARGET_SSE"
4755 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4756 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4757 if (out != operands[0])
4758 emit_move_insn (operands[0], out);
4763 operands[2] = assign_386_stack_local (SImode, 0);
4764 operands[3] = assign_386_stack_local (SImode, 1);
4768 (define_insn "*fix_truncsi_1"
4769 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4770 (fix:SI (match_operand 1 "register_operand" "f,f")))
4771 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4772 (clobber (match_operand:SI 3 "memory_operand" "=m,m"))
4773 (clobber (match_scratch:SI 4 "=&r,r"))]
4774 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4775 && (!TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4776 "* return output_fix_trunc (insn, operands);"
4777 [(set_attr "type" "multi")])
4779 ;; When SSE available, it is always faster to use it!
4780 (define_insn "fix_truncsfsi_sse"
4781 [(set (match_operand:SI 0 "register_operand" "=r")
4782 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4784 "cvttss2si\\t{%1, %0|%0, %1}"
4785 [(set_attr "type" "sse")])
4787 (define_insn "fix_truncdfsi_sse"
4788 [(set (match_operand:SI 0 "register_operand" "=r")
4789 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4791 "cvttsd2si\\t{%1, %0|%0, %1}"
4792 [(set_attr "type" "sse")])
4795 [(set (match_operand:SI 0 "register_operand" "")
4796 (fix:SI (match_operand 1 "register_operand" "")))
4797 (clobber (match_operand:SI 2 "memory_operand" ""))
4798 (clobber (match_operand:SI 3 "memory_operand" ""))
4799 (clobber (match_scratch:SI 4 ""))]
4801 [(parallel [(set (match_dup 3) (fix:SI (match_dup 1)))
4802 (clobber (match_dup 2))
4803 (clobber (match_dup 3))
4804 (clobber (match_dup 4))])
4805 (set (match_dup 0) (match_dup 3))]
4808 ;; Signed conversion to HImode.
4810 (define_expand "fix_truncxfhi2"
4811 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4812 (fix:HI (match_operand:XF 1 "register_operand" "")))
4813 (clobber (match_dup 2))
4814 (clobber (match_dup 3))
4815 (clobber (match_scratch:SI 4 ""))])]
4816 "TARGET_80387 && !TARGET_64BIT"
4817 "operands[2] = assign_386_stack_local (SImode, 0);
4818 operands[3] = assign_386_stack_local (HImode, 1);")
4820 (define_expand "fix_trunctfhi2"
4821 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4822 (fix:HI (match_operand:TF 1 "register_operand" "")))
4823 (clobber (match_dup 2))
4824 (clobber (match_dup 3))
4825 (clobber (match_scratch:SI 4 ""))])]
4827 "operands[2] = assign_386_stack_local (SImode, 0);
4828 operands[3] = assign_386_stack_local (HImode, 1);")
4830 (define_expand "fix_truncdfhi2"
4831 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4832 (fix:HI (match_operand:DF 1 "register_operand" "")))
4833 (clobber (match_dup 2))
4834 (clobber (match_dup 3))
4835 (clobber (match_scratch:SI 4 ""))])]
4836 "TARGET_80387 && !TARGET_SSE2"
4837 "operands[2] = assign_386_stack_local (SImode, 0);
4838 operands[3] = assign_386_stack_local (HImode, 1);")
4840 (define_expand "fix_truncsfhi2"
4841 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4842 (fix:HI (match_operand:SF 1 "register_operand" "")))
4843 (clobber (match_dup 2))
4844 (clobber (match_dup 3))
4845 (clobber (match_scratch:SI 4 ""))])]
4846 "TARGET_80387 && !TARGET_SSE"
4847 "operands[2] = assign_386_stack_local (SImode, 0);
4848 operands[3] = assign_386_stack_local (HImode, 1);")
4850 (define_insn "*fix_trunchi_1"
4851 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4852 (fix:HI (match_operand 1 "register_operand" "f,f")))
4853 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4854 (clobber (match_operand:HI 3 "memory_operand" "=m,m"))
4855 (clobber (match_scratch:SI 4 "=&r,r"))]
4856 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4857 && (TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4858 "* return output_fix_trunc (insn, operands);"
4859 [(set_attr "type" "multi")])
4862 [(set (match_operand:HI 0 "register_operand" "")
4863 (fix:HI (match_operand 1 "register_operand" "")))
4864 (clobber (match_operand:SI 2 "memory_operand" ""))
4865 (clobber (match_operand:HI 3 "memory_operand" ""))
4866 (clobber (match_scratch:SI 4 ""))]
4868 [(parallel [(set (match_dup 3) (fix:HI (match_dup 1)))
4869 (clobber (match_dup 2))
4870 (clobber (match_dup 3))
4871 (clobber (match_dup 4))])
4872 (set (match_dup 0) (match_dup 3))]
4875 ;; %%% Kill these when reload knows how to do it.
4877 [(set (match_operand 0 "register_operand" "")
4878 (fix (match_operand 1 "register_operand" "")))]
4879 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[1]))
4880 && FP_REG_P (operands[1])"
4884 operands[2] = ix86_force_to_memory (GET_MODE (operands[0]), operands[0]);
4885 operands[2] = gen_rtx_FIX (GET_MODE (operands[2]), operands[1]);
4886 emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
4887 emit_move_insn (operands[0], operands[2]);
4888 ix86_free_from_memory (GET_MODE (operands[0]));
4893 (define_insn "x86_fnstcw_1"
4894 [(set (match_operand:HI 0 "memory_operand" "=m")
4895 (unspec:HI [(reg:HI 18)] 11))]
4898 [(set_attr "length" "2")
4899 (set_attr "mode" "HI")
4900 (set_attr "i387" "1")
4901 (set_attr "ppro_uops" "few")])
4903 (define_insn "x86_fldcw_1"
4905 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
4908 [(set_attr "length" "2")
4909 (set_attr "mode" "HI")
4910 (set_attr "i387" "1")
4911 (set_attr "athlon_decode" "vector")
4912 (set_attr "ppro_uops" "few")])
4914 ;; Conversion between fixed point and floating point.
4916 ;; Even though we only accept memory inputs, the backend _really_
4917 ;; wants to be able to do this between registers.
4919 (define_insn "floathisf2"
4920 [(set (match_operand:SF 0 "register_operand" "=f,f")
4921 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4922 "TARGET_80387 && !TARGET_SSE"
4926 [(set_attr "type" "fmov,multi")
4927 (set_attr "mode" "SF")
4928 (set_attr "fp_int_src" "true")])
4930 (define_expand "floatsisf2"
4931 [(set (match_operand:SF 0 "register_operand" "")
4932 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4933 "TARGET_SSE || TARGET_80387"
4936 (define_insn "*floatsisf2_i387"
4937 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4938 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4939 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4943 cvtsi2ss\\t{%1, %0|%0, %1}"
4944 [(set_attr "type" "fmov,multi,sse")
4945 (set_attr "mode" "SF")
4946 (set_attr "fp_int_src" "true")])
4948 (define_insn "*floatsisf2_sse"
4949 [(set (match_operand:SF 0 "register_operand" "=x")
4950 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4951 "TARGET_80387 && TARGET_SSE"
4952 "cvtsi2ss\\t{%1, %0|%0, %1}"
4953 [(set_attr "type" "sse")
4954 (set_attr "mode" "SF")
4955 (set_attr "fp_int_src" "true")])
4957 (define_insn "floatdisf2"
4958 [(set (match_operand:SF 0 "register_operand" "=f,f")
4959 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4964 [(set_attr "type" "fmov,multi")
4965 (set_attr "mode" "SF")
4966 (set_attr "fp_int_src" "true")])
4968 (define_insn "floathidf2"
4969 [(set (match_operand:DF 0 "register_operand" "=f,f")
4970 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4971 "TARGET_80387 && !TARGET_SSE2"
4975 [(set_attr "type" "fmov,multi")
4976 (set_attr "mode" "DF")
4977 (set_attr "fp_int_src" "true")])
4979 (define_expand "floatsidf2"
4980 [(set (match_operand:DF 0 "register_operand" "")
4981 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4985 (define_insn "*floatsidf2_i387"
4986 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4987 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4988 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4992 cvtsi2sd\\t{%1, %0|%0, %1}"
4993 [(set_attr "type" "fmov,multi,sse")
4994 (set_attr "mode" "DF")
4995 (set_attr "fp_int_src" "true")])
4997 (define_insn "*floatsidf2_sse"
4998 [(set (match_operand:DF 0 "register_operand" "=Y")
4999 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5001 "cvtsi2sd\\t{%1, %0|%0, %1}"
5002 [(set_attr "type" "sse")
5003 (set_attr "mode" "DF")
5004 (set_attr "fp_int_src" "true")])
5006 (define_insn "floatdidf2"
5007 [(set (match_operand:DF 0 "register_operand" "=f,f")
5008 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5009 "TARGET_80387 && TARGET_SSE2"
5013 [(set_attr "type" "fmov,multi")
5014 (set_attr "mode" "DF")
5015 (set_attr "fp_int_src" "true")])
5017 (define_insn "floathixf2"
5018 [(set (match_operand:XF 0 "register_operand" "=f,f")
5019 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5020 "TARGET_80387 && !TARGET_64BIT"
5024 [(set_attr "type" "fmov,multi")
5025 (set_attr "mode" "XF")
5026 (set_attr "fp_int_src" "true")])
5028 (define_insn "floathitf2"
5029 [(set (match_operand:TF 0 "register_operand" "=f,f")
5030 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5035 [(set_attr "type" "fmov,multi")
5036 (set_attr "mode" "XF")
5037 (set_attr "fp_int_src" "true")])
5039 (define_insn "floatsixf2"
5040 [(set (match_operand:XF 0 "register_operand" "=f,f")
5041 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5042 "TARGET_80387 && !TARGET_64BIT"
5046 [(set_attr "type" "fmov,multi")
5047 (set_attr "mode" "XF")
5048 (set_attr "fp_int_src" "true")])
5050 (define_insn "floatsitf2"
5051 [(set (match_operand:TF 0 "register_operand" "=f,f")
5052 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5057 [(set_attr "type" "fmov,multi")
5058 (set_attr "mode" "XF")
5059 (set_attr "fp_int_src" "true")])
5061 (define_insn "floatdixf2"
5062 [(set (match_operand:XF 0 "register_operand" "=f,f")
5063 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5064 "TARGET_80387 && !TARGET_64BIT"
5068 [(set_attr "type" "fmov,multi")
5069 (set_attr "mode" "XF")
5070 (set_attr "fp_int_src" "true")])
5072 (define_insn "floatditf2"
5073 [(set (match_operand:TF 0 "register_operand" "=f,f")
5074 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5079 [(set_attr "type" "fmov,multi")
5080 (set_attr "mode" "XF")
5081 (set_attr "fp_int_src" "true")])
5083 ;; %%% Kill these when reload knows how to do it.
5085 [(set (match_operand 0 "register_operand" "")
5086 (float (match_operand 1 "register_operand" "")))]
5087 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5088 && FP_REG_P (operands[0])"
5092 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5093 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5094 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5095 ix86_free_from_memory (GET_MODE (operands[1]));
5101 ;; %%% define_expand from the very first?
5102 ;; %%% splits for addsidi3
5103 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5104 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5105 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5107 (define_insn "adddi3"
5108 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5109 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5110 (match_operand:DI 2 "general_operand" "roiF,riF")))
5111 (clobber (reg:CC 17))]
5116 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5117 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5118 (match_operand:DI 2 "general_operand" "")))
5119 (clobber (reg:CC 17))]
5120 "reload_completed && !TARGET_64BIT"
5121 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5122 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5123 (parallel [(set (match_dup 3)
5124 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5127 (clobber (reg:CC 17))])]
5128 "split_di (operands+0, 1, operands+0, operands+3);
5129 split_di (operands+1, 1, operands+1, operands+4);
5130 split_di (operands+2, 1, operands+2, operands+5);")
5132 (define_insn "*addsi3_carry"
5133 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5134 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5135 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5136 (match_operand:SI 2 "general_operand" "ri,rm")))
5137 (clobber (reg:CC 17))]
5138 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5139 "adc{l}\\t{%2, %0|%0, %2}"
5140 [(set_attr "type" "alu")
5141 (set_attr "pent_pair" "pu")
5142 (set_attr "mode" "SI")
5143 (set_attr "ppro_uops" "few")])
5145 (define_insn "*addsi3_cc"
5146 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5147 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5148 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5149 (plus:SI (match_dup 1) (match_dup 2)))]
5150 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5151 "add{l}\\t{%2, %0|%0, %2}"
5152 [(set_attr "type" "alu")
5153 (set_attr "mode" "SI")])
5155 (define_insn "addqi3_cc"
5156 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5157 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5158 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5159 (plus:QI (match_dup 1) (match_dup 2)))]
5160 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5161 "add{b}\\t{%2, %0|%0, %2}"
5162 [(set_attr "type" "alu")
5163 (set_attr "mode" "QI")])
5165 (define_expand "addsi3"
5166 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5167 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5168 (match_operand:SI 2 "general_operand" "")))
5169 (clobber (reg:CC 17))])]
5171 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5173 (define_insn "*lea_0"
5174 [(set (match_operand:SI 0 "register_operand" "=r")
5175 (match_operand:SI 1 "address_operand" "p"))]
5177 "lea{l}\\t{%a1, %0|%0, %a1}"
5178 [(set_attr "type" "lea")
5179 (set_attr "mode" "SI")])
5181 ;; The lea patterns for non-Pmodes needs to be matched by several
5182 ;; insns converted to real lea by splitters.
5184 (define_insn_and_split "*lea_general_1"
5185 [(set (match_operand 0 "register_operand" "=r")
5186 (plus (plus (match_operand 1 "register_operand" "r")
5187 (match_operand 2 "register_operand" "r"))
5188 (match_operand 3 "immediate_operand" "i")))]
5189 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
5190 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5191 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5192 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5193 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5194 || GET_MODE (operands[3]) == VOIDmode)"
5196 "&& reload_completed"
5201 operands[0] = gen_lowpart (SImode, operands[0]);
5202 operands[1] = gen_lowpart (Pmode, operands[1]);
5203 operands[2] = gen_lowpart (Pmode, operands[2]);
5204 operands[3] = gen_lowpart (Pmode, operands[3]);
5205 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5207 if (Pmode != SImode)
5208 pat = gen_rtx_SUBREG (SImode, pat, 0);
5209 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5212 [(set_attr "type" "lea")
5213 (set_attr "mode" "SI")])
5215 (define_insn_and_split "*lea_general_2"
5216 [(set (match_operand 0 "register_operand" "=r")
5217 (plus (mult (match_operand 1 "register_operand" "r")
5218 (match_operand 2 "const248_operand" "i"))
5219 (match_operand 3 "nonmemory_operand" "ri")))]
5220 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
5221 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5222 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5223 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5224 || GET_MODE (operands[3]) == VOIDmode)"
5226 "&& reload_completed"
5231 operands[0] = gen_lowpart (SImode, operands[0]);
5232 operands[1] = gen_lowpart (Pmode, operands[1]);
5233 operands[3] = gen_lowpart (Pmode, operands[3]);
5234 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5236 if (Pmode != SImode)
5237 pat = gen_rtx_SUBREG (SImode, pat, 0);
5238 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5241 [(set_attr "type" "lea")
5242 (set_attr "mode" "SI")])
5244 (define_insn_and_split "*lea_general_3"
5245 [(set (match_operand 0 "register_operand" "=r")
5246 (plus (plus (mult (match_operand 1 "register_operand" "r")
5247 (match_operand 2 "const248_operand" "i"))
5248 (match_operand 3 "register_operand" "r"))
5249 (match_operand 4 "immediate_operand" "i")))]
5250 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
5251 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5252 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5253 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5255 "&& reload_completed"
5260 operands[0] = gen_lowpart (SImode, operands[0]);
5261 operands[1] = gen_lowpart (Pmode, operands[1]);
5262 operands[3] = gen_lowpart (Pmode, operands[3]);
5263 operands[4] = gen_lowpart (Pmode, operands[4]);
5264 pat = gen_rtx_PLUS (Pmode,
5265 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5269 if (Pmode != SImode)
5270 pat = gen_rtx_SUBREG (SImode, pat, 0);
5271 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5274 [(set_attr "type" "lea")
5275 (set_attr "mode" "SI")])
5277 (define_insn "*addsi_1"
5278 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5279 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5280 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5281 (clobber (reg:CC 17))]
5282 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5285 switch (get_attr_type (insn))
5288 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5289 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
5292 if (! rtx_equal_p (operands[0], operands[1]))
5294 if (operands[2] == const1_rtx)
5295 return \"inc{l}\\t%0\";
5296 else if (operands[2] == constm1_rtx)
5297 return \"dec{l}\\t%0\";
5302 if (! rtx_equal_p (operands[0], operands[1]))
5305 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5306 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5307 if (GET_CODE (operands[2]) == CONST_INT
5308 && (INTVAL (operands[2]) == 128
5309 || (INTVAL (operands[2]) < 0
5310 && INTVAL (operands[2]) != -128)))
5312 operands[2] = GEN_INT (-INTVAL (operands[2]));
5313 return \"sub{l}\\t{%2, %0|%0, %2}\";
5315 return \"add{l}\\t{%2, %0|%0, %2}\";
5319 (cond [(eq_attr "alternative" "2")
5320 (const_string "lea")
5321 ; Current assemblers are broken and do not allow @GOTOFF in
5322 ; ought but a memory context.
5323 (match_operand:SI 2 "pic_symbolic_operand" "")
5324 (const_string "lea")
5325 (match_operand:SI 2 "incdec_operand" "")
5326 (const_string "incdec")
5328 (const_string "alu")))
5329 (set_attr "mode" "SI")])
5331 ;; Convert lea to the lea pattern to avoid flags dependency.
5333 [(set (match_operand 0 "register_operand" "")
5334 (plus (match_operand 1 "register_operand" "")
5335 (match_operand 2 "nonmemory_operand" "")))
5336 (clobber (reg:CC 17))]
5338 && true_regnum (operands[0]) != true_regnum (operands[1])"
5343 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5344 may confuse gen_lowpart. */
5345 if (GET_MODE (operands[0]) != Pmode)
5347 operands[1] = gen_lowpart (Pmode, operands[1]);
5348 operands[2] = gen_lowpart (Pmode, operands[2]);
5350 operands[0] = gen_lowpart (SImode, operands[0]);
5351 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5352 if (Pmode != SImode)
5353 pat = gen_rtx_SUBREG (SImode, pat, 0);
5354 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5358 (define_insn "*addsi_2"
5361 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5362 (match_operand:SI 2 "general_operand" "rmni,rni"))
5364 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5365 (plus:SI (match_dup 1) (match_dup 2)))]
5366 "ix86_match_ccmode (insn, CCGOCmode)
5367 && ix86_binary_operator_ok (PLUS, SImode, operands)
5368 /* Current assemblers are broken and do not allow @GOTOFF in
5369 ought but a memory context. */
5370 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5373 switch (get_attr_type (insn))
5376 if (! rtx_equal_p (operands[0], operands[1]))
5378 if (operands[2] == const1_rtx)
5379 return \"inc{l}\\t%0\";
5380 else if (operands[2] == constm1_rtx)
5381 return \"dec{l}\\t%0\";
5386 if (! rtx_equal_p (operands[0], operands[1]))
5388 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5389 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5390 if (GET_CODE (operands[2]) == CONST_INT
5391 && (INTVAL (operands[2]) == 128
5392 || (INTVAL (operands[2]) < 0
5393 && INTVAL (operands[2]) != -128)))
5395 operands[2] = GEN_INT (-INTVAL (operands[2]));
5396 return \"sub{l}\\t{%2, %0|%0, %2}\";
5398 return \"add{l}\\t{%2, %0|%0, %2}\";
5402 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5403 (const_string "incdec")
5404 (const_string "alu")))
5405 (set_attr "mode" "SI")])
5407 (define_insn "*addsi_3"
5409 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5410 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5411 (clobber (match_scratch:SI 0 "=r"))]
5412 "ix86_match_ccmode (insn, CCZmode)
5413 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5414 /* Current assemblers are broken and do not allow @GOTOFF in
5415 ought but a memory context. */
5416 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5419 switch (get_attr_type (insn))
5422 if (! rtx_equal_p (operands[0], operands[1]))
5424 if (operands[2] == const1_rtx)
5425 return \"inc{l}\\t%0\";
5426 else if (operands[2] == constm1_rtx)
5427 return \"dec{l}\\t%0\";
5432 if (! rtx_equal_p (operands[0], operands[1]))
5434 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5435 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5436 if (GET_CODE (operands[2]) == CONST_INT
5437 && (INTVAL (operands[2]) == 128
5438 || (INTVAL (operands[2]) < 0
5439 && INTVAL (operands[2]) != -128)))
5441 operands[2] = GEN_INT (-INTVAL (operands[2]));
5442 return \"sub{l}\\t{%2, %0|%0, %2}\";
5444 return \"add{l}\\t{%2, %0|%0, %2}\";
5448 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5449 (const_string "incdec")
5450 (const_string "alu")))
5451 (set_attr "mode" "SI")])
5453 ; For comparisons agains 1, -1 and 128, we may generate better code
5454 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5455 ; is matched then. We can't accept general immediate, because for
5456 ; case of overflows, the result is messed up.
5457 ; This pattern also don't hold of 0x80000000, since the value overflows
5459 ; Also carry flag is reversed compared to cmp, so this converison is valid
5460 ; only for comparisons not depending on it.
5461 (define_insn "*addsi_4"
5463 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5464 (match_operand:SI 2 "const_int_operand" "n")))
5465 (clobber (match_scratch:SI 0 "=rm"))]
5466 "ix86_match_ccmode (insn, CCGCmode)
5467 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5470 switch (get_attr_type (insn))
5473 if (operands[2] == constm1_rtx)
5474 return \"inc{l}\\t%0\";
5475 else if (operands[2] == const1_rtx)
5476 return \"dec{l}\\t%0\";
5481 if (! rtx_equal_p (operands[0], operands[1]))
5483 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5484 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5485 if ((INTVAL (operands[2]) == -128
5486 || (INTVAL (operands[2]) > 0
5487 && INTVAL (operands[2]) != 128)))
5488 return \"sub{l}\\t{%2, %0|%0, %2}\";
5489 operands[2] = GEN_INT (-INTVAL (operands[2]));
5490 return \"add{l}\\t{%2, %0|%0, %2}\";
5494 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5495 (const_string "incdec")
5496 (const_string "alu")))
5497 (set_attr "mode" "SI")])
5499 (define_insn "*addsi_5"
5502 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5503 (match_operand:SI 2 "general_operand" "rmni"))
5505 (clobber (match_scratch:SI 0 "=r"))]
5506 "ix86_match_ccmode (insn, CCGOCmode)
5507 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5508 /* Current assemblers are broken and do not allow @GOTOFF in
5509 ought but a memory context. */
5510 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5513 switch (get_attr_type (insn))
5516 if (! rtx_equal_p (operands[0], operands[1]))
5518 if (operands[2] == const1_rtx)
5519 return \"inc{l}\\t%0\";
5520 else if (operands[2] == constm1_rtx)
5521 return \"dec{l}\\t%0\";
5526 if (! rtx_equal_p (operands[0], operands[1]))
5528 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5529 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5530 if (GET_CODE (operands[2]) == CONST_INT
5531 && (INTVAL (operands[2]) == 128
5532 || (INTVAL (operands[2]) < 0
5533 && INTVAL (operands[2]) != -128)))
5535 operands[2] = GEN_INT (-INTVAL (operands[2]));
5536 return \"sub{l}\\t{%2, %0|%0, %2}\";
5538 return \"add{l}\\t{%2, %0|%0, %2}\";
5542 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5543 (const_string "incdec")
5544 (const_string "alu")))
5545 (set_attr "mode" "SI")])
5547 (define_expand "addhi3"
5548 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5549 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5550 (match_operand:HI 2 "general_operand" "")))
5551 (clobber (reg:CC 17))])]
5552 "TARGET_HIMODE_MATH"
5553 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5555 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5556 ;; type optimizations enabled by define-splits. This is not important
5557 ;; for PII, and in fact harmful because of partial register stalls.
5559 (define_insn "*addhi_1_lea"
5560 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5561 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5562 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5563 (clobber (reg:CC 17))]
5564 "!TARGET_PARTIAL_REG_STALL
5565 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5568 switch (get_attr_type (insn))
5573 if (operands[2] == const1_rtx)
5574 return \"inc{w}\\t%0\";
5575 else if (operands[2] == constm1_rtx
5576 || (GET_CODE (operands[2]) == CONST_INT
5577 && INTVAL (operands[2]) == 65535))
5578 return \"dec{w}\\t%0\";
5582 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5583 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5584 if (GET_CODE (operands[2]) == CONST_INT
5585 && (INTVAL (operands[2]) == 128
5586 || (INTVAL (operands[2]) < 0
5587 && INTVAL (operands[2]) != -128)))
5589 operands[2] = GEN_INT (-INTVAL (operands[2]));
5590 return \"sub{w}\\t{%2, %0|%0, %2}\";
5592 return \"add{w}\\t{%2, %0|%0, %2}\";
5596 (if_then_else (eq_attr "alternative" "2")
5597 (const_string "lea")
5598 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5599 (const_string "incdec")
5600 (const_string "alu"))))
5601 (set_attr "mode" "HI,HI,SI")])
5603 (define_insn "*addhi_1"
5604 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5605 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5606 (match_operand:HI 2 "general_operand" "ri,rm")))
5607 (clobber (reg:CC 17))]
5608 "TARGET_PARTIAL_REG_STALL
5609 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5612 switch (get_attr_type (insn))
5615 if (operands[2] == const1_rtx)
5616 return \"inc{w}\\t%0\";
5617 else if (operands[2] == constm1_rtx
5618 || (GET_CODE (operands[2]) == CONST_INT
5619 && INTVAL (operands[2]) == 65535))
5620 return \"dec{w}\\t%0\";
5624 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5625 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5626 if (GET_CODE (operands[2]) == CONST_INT
5627 && (INTVAL (operands[2]) == 128
5628 || (INTVAL (operands[2]) < 0
5629 && INTVAL (operands[2]) != -128)))
5631 operands[2] = GEN_INT (-INTVAL (operands[2]));
5632 return \"sub{w}\\t{%2, %0|%0, %2}\";
5634 return \"add{w}\\t{%2, %0|%0, %2}\";
5638 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5639 (const_string "incdec")
5640 (const_string "alu")))
5641 (set_attr "mode" "HI")])
5643 (define_insn "*addhi_2"
5646 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5647 (match_operand:HI 2 "general_operand" "rmni,rni"))
5649 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
5650 (plus:HI (match_dup 1) (match_dup 2)))]
5651 "ix86_match_ccmode (insn, CCGOCmode)
5652 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5655 switch (get_attr_type (insn))
5658 if (operands[2] == const1_rtx)
5659 return \"inc{w}\\t%0\";
5660 else if (operands[2] == constm1_rtx
5661 || (GET_CODE (operands[2]) == CONST_INT
5662 && INTVAL (operands[2]) == 65535))
5663 return \"dec{w}\\t%0\";
5667 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5668 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5669 if (GET_CODE (operands[2]) == CONST_INT
5670 && (INTVAL (operands[2]) == 128
5671 || (INTVAL (operands[2]) < 0
5672 && INTVAL (operands[2]) != -128)))
5674 operands[2] = GEN_INT (-INTVAL (operands[2]));
5675 return \"sub{w}\\t{%2, %0|%0, %2}\";
5677 return \"add{w}\\t{%2, %0|%0, %2}\";
5681 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5682 (const_string "incdec")
5683 (const_string "alu")))
5684 (set_attr "mode" "HI")])
5686 (define_insn "*addhi_3"
5688 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
5689 (match_operand:HI 1 "nonimmediate_operand" "%0")))
5690 (clobber (match_scratch:HI 0 "=r"))]
5691 "ix86_match_ccmode (insn, CCZmode)
5692 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5695 switch (get_attr_type (insn))
5698 if (operands[2] == const1_rtx)
5699 return \"inc{w}\\t%0\";
5700 else if (operands[2] == constm1_rtx
5701 || (GET_CODE (operands[2]) == CONST_INT
5702 && INTVAL (operands[2]) == 65535))
5703 return \"dec{w}\\t%0\";
5707 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5708 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5709 if (GET_CODE (operands[2]) == CONST_INT
5710 && (INTVAL (operands[2]) == 128
5711 || (INTVAL (operands[2]) < 0
5712 && INTVAL (operands[2]) != -128)))
5714 operands[2] = GEN_INT (-INTVAL (operands[2]));
5715 return \"sub{w}\\t{%2, %0|%0, %2}\";
5717 return \"add{w}\\t{%2, %0|%0, %2}\";
5721 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5722 (const_string "incdec")
5723 (const_string "alu")))
5724 (set_attr "mode" "HI")])
5726 ; See comments above addsi_3_imm for details.
5727 (define_insn "*addhi_4"
5729 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
5730 (match_operand:HI 2 "const_int_operand" "n")))
5731 (clobber (match_scratch:HI 0 "=rm"))]
5732 "ix86_match_ccmode (insn, CCGCmode)
5733 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5736 switch (get_attr_type (insn))
5739 if (operands[2] == constm1_rtx
5740 || (GET_CODE (operands[2]) == CONST_INT
5741 && INTVAL (operands[2]) == 65535))
5742 return \"inc{w}\\t%0\";
5743 else if (operands[2] == const1_rtx)
5744 return \"dec{w}\\t%0\";
5749 if (! rtx_equal_p (operands[0], operands[1]))
5751 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5752 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5753 if ((INTVAL (operands[2]) == -128
5754 || (INTVAL (operands[2]) > 0
5755 && INTVAL (operands[2]) != 128)))
5756 return \"sub{w}\\t{%2, %0|%0, %2}\";
5757 operands[2] = GEN_INT (-INTVAL (operands[2]));
5758 return \"add{w}\\t{%2, %0|%0, %2}\";
5762 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5763 (const_string "incdec")
5764 (const_string "alu")))
5765 (set_attr "mode" "SI")])
5768 (define_insn "*addhi_5"
5771 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
5772 (match_operand:HI 2 "general_operand" "rmni"))
5774 (clobber (match_scratch:HI 0 "=r"))]
5775 "ix86_match_ccmode (insn, CCGOCmode)
5776 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5779 switch (get_attr_type (insn))
5782 if (operands[2] == const1_rtx)
5783 return \"inc{w}\\t%0\";
5784 else if (operands[2] == constm1_rtx
5785 || (GET_CODE (operands[2]) == CONST_INT
5786 && INTVAL (operands[2]) == 65535))
5787 return \"dec{w}\\t%0\";
5791 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5792 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5793 if (GET_CODE (operands[2]) == CONST_INT
5794 && (INTVAL (operands[2]) == 128
5795 || (INTVAL (operands[2]) < 0
5796 && INTVAL (operands[2]) != -128)))
5798 operands[2] = GEN_INT (-INTVAL (operands[2]));
5799 return \"sub{w}\\t{%2, %0|%0, %2}\";
5801 return \"add{w}\\t{%2, %0|%0, %2}\";
5805 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5806 (const_string "incdec")
5807 (const_string "alu")))
5808 (set_attr "mode" "HI")])
5810 (define_expand "addqi3"
5811 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
5812 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
5813 (match_operand:QI 2 "general_operand" "")))
5814 (clobber (reg:CC 17))])]
5815 "TARGET_QIMODE_MATH"
5816 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
5818 ;; %%% Potential partial reg stall on alternative 2. What to do?
5819 (define_insn "*addqi_1_lea"
5820 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
5821 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
5822 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
5823 (clobber (reg:CC 17))]
5824 "!TARGET_PARTIAL_REG_STALL
5825 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5828 int widen = (which_alternative == 2);
5829 switch (get_attr_type (insn))
5834 if (operands[2] == const1_rtx)
5835 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
5836 else if (operands[2] == constm1_rtx
5837 || (GET_CODE (operands[2]) == CONST_INT
5838 && INTVAL (operands[2]) == 255))
5839 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
5843 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5844 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5845 if (GET_CODE (operands[2]) == CONST_INT
5846 && (INTVAL (operands[2]) == 128
5847 || (INTVAL (operands[2]) < 0
5848 && INTVAL (operands[2]) != -128)))
5850 operands[2] = GEN_INT (-INTVAL (operands[2]));
5852 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5854 return \"sub{b}\\t{%2, %0|%0, %2}\";
5857 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
5859 return \"add{b}\\t{%2, %0|%0, %2}\";
5863 (if_then_else (eq_attr "alternative" "3")
5864 (const_string "lea")
5865 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5866 (const_string "incdec")
5867 (const_string "alu"))))
5868 (set_attr "mode" "QI,QI,SI,SI")])
5870 (define_insn "*addqi_1"
5871 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
5872 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5873 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
5874 (clobber (reg:CC 17))]
5875 "TARGET_PARTIAL_REG_STALL
5876 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5879 int widen = (which_alternative == 2);
5880 switch (get_attr_type (insn))
5883 if (operands[2] == const1_rtx)
5884 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
5885 else if (operands[2] == constm1_rtx
5886 || (GET_CODE (operands[2]) == CONST_INT
5887 && INTVAL (operands[2]) == 255))
5888 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
5892 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5893 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5894 if (GET_CODE (operands[2]) == CONST_INT
5895 && (INTVAL (operands[2]) == 128
5896 || (INTVAL (operands[2]) < 0
5897 && INTVAL (operands[2]) != -128)))
5899 operands[2] = GEN_INT (-INTVAL (operands[2]));
5901 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5903 return \"sub{b}\\t{%2, %0|%0, %2}\";
5906 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
5908 return \"add{b}\\t{%2, %0|%0, %2}\";
5912 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5913 (const_string "incdec")
5914 (const_string "alu")))
5915 (set_attr "mode" "QI,QI,SI")])
5917 (define_insn "*addqi_2"
5920 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
5921 (match_operand:QI 2 "general_operand" "qmni,qni"))
5923 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
5924 (plus:QI (match_dup 1) (match_dup 2)))]
5925 "ix86_match_ccmode (insn, CCGOCmode)
5926 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5929 switch (get_attr_type (insn))
5932 if (operands[2] == const1_rtx)
5933 return \"inc{b}\\t%0\";
5934 else if (operands[2] == constm1_rtx
5935 || (GET_CODE (operands[2]) == CONST_INT
5936 && INTVAL (operands[2]) == 255))
5937 return \"dec{b}\\t%0\";
5941 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
5942 if (GET_CODE (operands[2]) == CONST_INT
5943 && INTVAL (operands[2]) < 0)
5945 operands[2] = GEN_INT (-INTVAL (operands[2]));
5946 return \"sub{b}\\t{%2, %0|%0, %2}\";
5948 return \"add{b}\\t{%2, %0|%0, %2}\";
5952 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5953 (const_string "incdec")
5954 (const_string "alu")))
5955 (set_attr "mode" "QI")])
5957 (define_insn "*addqi_3"
5959 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
5960 (match_operand:QI 1 "nonimmediate_operand" "%0")))
5961 (clobber (match_scratch:QI 0 "=q"))]
5962 "ix86_match_ccmode (insn, CCZmode)
5963 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5966 switch (get_attr_type (insn))
5969 if (operands[2] == const1_rtx)
5970 return \"inc{b}\\t%0\";
5971 else if (operands[2] == constm1_rtx
5972 || (GET_CODE (operands[2]) == CONST_INT
5973 && INTVAL (operands[2]) == 255))
5974 return \"dec{b}\\t%0\";
5978 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
5979 if (GET_CODE (operands[2]) == CONST_INT
5980 && INTVAL (operands[2]) < 0)
5982 operands[2] = GEN_INT (-INTVAL (operands[2]));
5983 return \"sub{b}\\t{%2, %0|%0, %2}\";
5985 return \"add{b}\\t{%2, %0|%0, %2}\";
5989 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5990 (const_string "incdec")
5991 (const_string "alu")))
5992 (set_attr "mode" "QI")])
5994 ; See comments above addsi_3_imm for details.
5995 (define_insn "*addqi_4"
5997 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
5998 (match_operand:QI 2 "const_int_operand" "n")))
5999 (clobber (match_scratch:QI 0 "=qm"))]
6000 "ix86_match_ccmode (insn, CCGCmode)
6001 && (INTVAL (operands[2]) & 0xff) != 0x80"
6004 switch (get_attr_type (insn))
6007 if (operands[2] == constm1_rtx
6008 || (GET_CODE (operands[2]) == CONST_INT
6009 && INTVAL (operands[2]) == 255))
6010 return \"inc{b}\\t%0\";
6011 else if (operands[2] == const1_rtx)
6012 return \"dec{b}\\t%0\";
6017 if (! rtx_equal_p (operands[0], operands[1]))
6019 if (INTVAL (operands[2]) < 0)
6021 operands[2] = GEN_INT (-INTVAL (operands[2]));
6022 return \"add{b}\\t{%2, %0|%0, %2}\";
6024 return \"sub{b}\\t{%2, %0|%0, %2}\";
6028 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6029 (const_string "incdec")
6030 (const_string "alu")))
6031 (set_attr "mode" "QI")])
6034 (define_insn "*addqi_5"
6037 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6038 (match_operand:QI 2 "general_operand" "qmni"))
6040 (clobber (match_scratch:QI 0 "=q"))]
6041 "ix86_match_ccmode (insn, CCGOCmode)
6042 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6045 switch (get_attr_type (insn))
6048 if (operands[2] == const1_rtx)
6049 return \"inc{b}\\t%0\";
6050 else if (operands[2] == constm1_rtx
6051 || (GET_CODE (operands[2]) == CONST_INT
6052 && INTVAL (operands[2]) == 255))
6053 return \"dec{b}\\t%0\";
6057 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6058 if (GET_CODE (operands[2]) == CONST_INT
6059 && INTVAL (operands[2]) < 0)
6061 operands[2] = GEN_INT (-INTVAL (operands[2]));
6062 return \"sub{b}\\t{%2, %0|%0, %2}\";
6064 return \"add{b}\\t{%2, %0|%0, %2}\";
6068 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6069 (const_string "incdec")
6070 (const_string "alu")))
6071 (set_attr "mode" "QI")])
6074 (define_insn "addqi_ext_1"
6075 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6080 (match_operand 1 "ext_register_operand" "0")
6083 (match_operand:QI 2 "general_operand" "qmn")))
6084 (clobber (reg:CC 17))]
6088 switch (get_attr_type (insn))
6091 if (operands[2] == const1_rtx)
6092 return \"inc{b}\\t%h0\";
6093 else if (operands[2] == constm1_rtx
6094 || (GET_CODE (operands[2]) == CONST_INT
6095 && INTVAL (operands[2]) == 255))
6096 return \"dec{b}\\t%h0\";
6100 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6104 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6105 (const_string "incdec")
6106 (const_string "alu")))
6107 (set_attr "mode" "QI")])
6109 (define_insn "*addqi_ext_1_rex64"
6110 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6115 (match_operand 1 "ext_register_operand" "0")
6118 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6119 (clobber (reg:CC 17))]
6123 switch (get_attr_type (insn))
6126 if (operands[2] == const1_rtx)
6127 return \"inc{b}\\t%h0\";
6128 else if (operands[2] == constm1_rtx
6129 || (GET_CODE (operands[2]) == CONST_INT
6130 && INTVAL (operands[2]) == 255))
6131 return \"dec{b}\\t%h0\";
6135 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6139 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6140 (const_string "incdec")
6141 (const_string "alu")))
6142 (set_attr "mode" "QI")])
6144 (define_insn "*addqi_ext_2"
6145 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6150 (match_operand 1 "ext_register_operand" "%0")
6154 (match_operand 2 "ext_register_operand" "Q")
6157 (clobber (reg:CC 17))]
6159 "add{b}\\t{%h2, %h0|%h0, %h2}"
6160 [(set_attr "type" "alu")
6161 (set_attr "mode" "QI")])
6163 ;; The patterns that match these are at the end of this file.
6165 (define_expand "addxf3"
6166 [(set (match_operand:XF 0 "register_operand" "")
6167 (plus:XF (match_operand:XF 1 "register_operand" "")
6168 (match_operand:XF 2 "register_operand" "")))]
6169 "TARGET_80387 && !TARGET_64BIT"
6172 (define_expand "addtf3"
6173 [(set (match_operand:TF 0 "register_operand" "")
6174 (plus:TF (match_operand:TF 1 "register_operand" "")
6175 (match_operand:TF 2 "register_operand" "")))]
6179 (define_expand "adddf3"
6180 [(set (match_operand:DF 0 "register_operand" "")
6181 (plus:DF (match_operand:DF 1 "register_operand" "")
6182 (match_operand:DF 2 "nonimmediate_operand" "")))]
6183 "TARGET_80387 || TARGET_SSE2"
6186 (define_expand "addsf3"
6187 [(set (match_operand:SF 0 "register_operand" "")
6188 (plus:SF (match_operand:SF 1 "register_operand" "")
6189 (match_operand:SF 2 "nonimmediate_operand" "")))]
6190 "TARGET_80387 || TARGET_SSE"
6193 ;; Subtract instructions
6195 ;; %%% define_expand from the very first?
6196 ;; %%% splits for subsidi3
6198 (define_insn "subdi3"
6199 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6200 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6201 (match_operand:DI 2 "general_operand" "roiF,riF")))
6202 (clobber (reg:CC 17))]
6207 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6208 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6209 (match_operand:DI 2 "general_operand" "")))
6210 (clobber (reg:CC 17))]
6211 "reload_completed && !TARGET_64BIT"
6212 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6213 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6214 (parallel [(set (match_dup 3)
6215 (minus:SI (match_dup 4)
6216 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6218 (clobber (reg:CC 17))])]
6219 "split_di (operands+0, 1, operands+0, operands+3);
6220 split_di (operands+1, 1, operands+1, operands+4);
6221 split_di (operands+2, 1, operands+2, operands+5);")
6223 (define_insn "subsi3_carry"
6224 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6225 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6226 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6227 (match_operand:SI 2 "general_operand" "ri,rm"))))
6228 (clobber (reg:CC 17))]
6229 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6230 "sbb{l}\\t{%2, %0|%0, %2}"
6231 [(set_attr "type" "alu")
6232 (set_attr "pent_pair" "pu")
6233 (set_attr "ppro_uops" "few")
6234 (set_attr "mode" "SI")])
6236 (define_expand "subsi3"
6237 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6238 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6239 (match_operand:SI 2 "general_operand" "")))
6240 (clobber (reg:CC 17))])]
6242 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6244 (define_insn "*subsi_1"
6245 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6246 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6247 (match_operand:SI 2 "general_operand" "ri,rm")))
6248 (clobber (reg:CC 17))]
6249 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6250 "sub{l}\\t{%2, %0|%0, %2}"
6251 [(set_attr "type" "alu")
6252 (set_attr "mode" "SI")])
6254 (define_insn "*subsi_2"
6257 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6258 (match_operand:SI 2 "general_operand" "ri,rm"))
6260 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6261 (minus:SI (match_dup 1) (match_dup 2)))]
6262 "ix86_match_ccmode (insn, CCGOCmode)
6263 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6264 "sub{l}\\t{%2, %0|%0, %2}"
6265 [(set_attr "type" "alu")
6266 (set_attr "mode" "SI")])
6268 (define_insn "*subsi_3"
6270 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6271 (match_operand:SI 2 "general_operand" "ri,rm")))
6272 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6273 (minus:SI (match_dup 1) (match_dup 2)))]
6274 "ix86_match_ccmode (insn, CCmode)
6275 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6276 "sub{l}\\t{%2, %0|%0, %2}"
6277 [(set_attr "type" "alu")
6278 (set_attr "mode" "SI")])
6280 (define_expand "subhi3"
6281 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6282 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6283 (match_operand:HI 2 "general_operand" "")))
6284 (clobber (reg:CC 17))])]
6285 "TARGET_HIMODE_MATH"
6286 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6288 (define_insn "*subhi_1"
6289 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6290 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6291 (match_operand:HI 2 "general_operand" "ri,rm")))
6292 (clobber (reg:CC 17))]
6293 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6294 "sub{w}\\t{%2, %0|%0, %2}"
6295 [(set_attr "type" "alu")
6296 (set_attr "mode" "HI")])
6298 (define_insn "*subhi_2"
6301 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6302 (match_operand:HI 2 "general_operand" "ri,rm"))
6304 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6305 (minus:HI (match_dup 1) (match_dup 2)))]
6306 "ix86_match_ccmode (insn, CCGOCmode)
6307 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6308 "sub{w}\\t{%2, %0|%0, %2}"
6309 [(set_attr "type" "alu")
6310 (set_attr "mode" "HI")])
6312 (define_insn "*subhi_3"
6314 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6315 (match_operand:HI 2 "general_operand" "ri,rm")))
6316 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6317 (minus:HI (match_dup 1) (match_dup 2)))]
6318 "ix86_match_ccmode (insn, CCmode)
6319 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6320 "sub{w}\\t{%2, %0|%0, %2}"
6321 [(set_attr "type" "alu")
6322 (set_attr "mode" "HI")])
6324 (define_expand "subqi3"
6325 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6326 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6327 (match_operand:QI 2 "general_operand" "")))
6328 (clobber (reg:CC 17))])]
6329 "TARGET_QIMODE_MATH"
6330 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6332 (define_insn "*subqi_1"
6333 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6334 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6335 (match_operand:QI 2 "general_operand" "qn,qmn")))
6336 (clobber (reg:CC 17))]
6337 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6338 "sub{b}\\t{%2, %0|%0, %2}"
6339 [(set_attr "type" "alu")
6340 (set_attr "mode" "QI")])
6342 (define_insn "*subqi_2"
6345 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6346 (match_operand:QI 2 "general_operand" "qi,qm"))
6348 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6349 (minus:HI (match_dup 1) (match_dup 2)))]
6350 "ix86_match_ccmode (insn, CCGOCmode)
6351 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6352 "sub{b}\\t{%2, %0|%0, %2}"
6353 [(set_attr "type" "alu")
6354 (set_attr "mode" "QI")])
6356 (define_insn "*subqi_3"
6358 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6359 (match_operand:QI 2 "general_operand" "qi,qm")))
6360 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6361 (minus:HI (match_dup 1) (match_dup 2)))]
6362 "ix86_match_ccmode (insn, CCmode)
6363 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6364 "sub{b}\\t{%2, %0|%0, %2}"
6365 [(set_attr "type" "alu")
6366 (set_attr "mode" "QI")])
6368 ;; The patterns that match these are at the end of this file.
6370 (define_expand "subxf3"
6371 [(set (match_operand:XF 0 "register_operand" "")
6372 (minus:XF (match_operand:XF 1 "register_operand" "")
6373 (match_operand:XF 2 "register_operand" "")))]
6374 "TARGET_80387 && !TARGET_64BIT"
6377 (define_expand "subtf3"
6378 [(set (match_operand:TF 0 "register_operand" "")
6379 (minus:TF (match_operand:TF 1 "register_operand" "")
6380 (match_operand:TF 2 "register_operand" "")))]
6384 (define_expand "subdf3"
6385 [(set (match_operand:DF 0 "register_operand" "")
6386 (minus:DF (match_operand:DF 1 "register_operand" "")
6387 (match_operand:DF 2 "nonimmediate_operand" "")))]
6388 "TARGET_80387 || TARGET_SSE2"
6391 (define_expand "subsf3"
6392 [(set (match_operand:SF 0 "register_operand" "")
6393 (minus:SF (match_operand:SF 1 "register_operand" "")
6394 (match_operand:SF 2 "nonimmediate_operand" "")))]
6395 "TARGET_80387 || TARGET_SSE"
6398 ;; Multiply instructions
6400 (define_expand "mulsi3"
6401 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6402 (mult:SI (match_operand:SI 1 "register_operand" "")
6403 (match_operand:SI 2 "general_operand" "")))
6404 (clobber (reg:CC 17))])]
6408 (define_insn "*mulsi3_1"
6409 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6410 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6411 (match_operand:SI 2 "general_operand" "K,i,mr")))
6412 (clobber (reg:CC 17))]
6413 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6414 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6415 ; there are two ways of writing the exact same machine instruction
6416 ; in assembly language. One, for example, is:
6420 ; while the other is:
6422 ; imul $12, %eax, %eax
6424 ; The first is simply short-hand for the latter. But, some assemblers,
6425 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6427 imul{l}\\t{%2, %1, %0|%0, %1, %2}
6428 imul{l}\\t{%2, %1, %0|%0, %1, %2}
6429 imul{l}\\t{%2, %0|%0, %2}"
6430 [(set_attr "type" "imul")
6431 (set_attr "prefix_0f" "0,0,1")
6432 (set_attr "mode" "SI")])
6434 (define_expand "mulhi3"
6435 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6436 (mult:HI (match_operand:HI 1 "register_operand" "")
6437 (match_operand:HI 2 "general_operand" "")))
6438 (clobber (reg:CC 17))])]
6439 "TARGET_HIMODE_MATH"
6442 (define_insn "*mulhi3_1"
6443 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6444 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
6445 (match_operand:HI 2 "general_operand" "K,i,mr")))
6446 (clobber (reg:CC 17))]
6447 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6448 ; %%% There was a note about "Assembler has weird restrictions",
6449 ; concerning alternative 1 when op1 == op0. True?
6451 imul{w}\\t{%2, %1, %0|%0, %1, %2}
6452 imul{w}\\t{%2, %1, %0|%0, %1, %2}
6453 imul{w}\\t{%2, %0|%0, %2}"
6454 [(set_attr "type" "imul")
6455 (set_attr "prefix_0f" "0,0,1")
6456 (set_attr "mode" "HI")])
6458 (define_insn "mulqi3"
6459 [(set (match_operand:QI 0 "register_operand" "=a")
6460 (mult:QI (match_operand:QI 1 "register_operand" "%0")
6461 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6462 (clobber (reg:CC 17))]
6463 "TARGET_QIMODE_MATH"
6465 [(set_attr "type" "imul")
6466 (set_attr "length_immediate" "0")
6467 (set_attr "mode" "QI")])
6469 (define_insn "umulqihi3"
6470 [(set (match_operand:HI 0 "register_operand" "=a")
6471 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
6472 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6473 (clobber (reg:CC 17))]
6474 "TARGET_QIMODE_MATH"
6476 [(set_attr "type" "imul")
6477 (set_attr "length_immediate" "0")
6478 (set_attr "mode" "QI")])
6480 (define_insn "mulqihi3"
6481 [(set (match_operand:HI 0 "register_operand" "=a")
6482 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
6483 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6484 (clobber (reg:CC 17))]
6485 "TARGET_QIMODE_MATH"
6487 [(set_attr "type" "imul")
6488 (set_attr "length_immediate" "0")
6489 (set_attr "mode" "QI")])
6491 (define_insn "umulsi3"
6492 [(set (match_operand:SI 0 "register_operand" "=a")
6493 (mult:SI (match_operand:SI 1 "register_operand" "%0")
6494 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6495 (clobber (match_operand:SI 3 "register_operand" "=d"))
6496 (clobber (reg:CC 17))]
6499 [(set_attr "type" "imul")
6500 (set_attr "ppro_uops" "few")
6501 (set_attr "length_immediate" "0")
6502 (set_attr "mode" "SI")])
6504 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
6505 (define_insn "umulsidi3"
6506 [(set (match_operand:DI 0 "register_operand" "=A")
6507 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
6508 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6509 (clobber (reg:CC 17))]
6512 [(set_attr "type" "imul")
6513 (set_attr "ppro_uops" "few")
6514 (set_attr "length_immediate" "0")
6515 (set_attr "mode" "SI")])
6517 (define_insn "mulsidi3"
6518 [(set (match_operand:DI 0 "register_operand" "=A")
6519 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
6520 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6521 (clobber (reg:CC 17))]
6524 [(set_attr "type" "imul")
6525 (set_attr "length_immediate" "0")
6526 (set_attr "mode" "SI")])
6528 (define_insn "umulsi3_highpart"
6529 [(set (match_operand:SI 0 "register_operand" "=d")
6532 (mult:DI (zero_extend:DI
6533 (match_operand:SI 1 "register_operand" "%a"))
6535 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6537 (clobber (match_scratch:SI 3 "=a"))
6538 (clobber (reg:CC 17))]
6541 [(set_attr "type" "imul")
6542 (set_attr "ppro_uops" "few")
6543 (set_attr "length_immediate" "0")
6544 (set_attr "mode" "SI")])
6546 (define_insn "smulsi3_highpart"
6547 [(set (match_operand:SI 0 "register_operand" "=d")
6550 (mult:DI (sign_extend:DI
6551 (match_operand:SI 1 "register_operand" "%a"))
6553 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6555 (clobber (match_scratch:SI 3 "=a"))
6556 (clobber (reg:CC 17))]
6559 [(set_attr "type" "imul")
6560 (set_attr "ppro_uops" "few")
6561 (set_attr "mode" "SI")])
6563 ;; The patterns that match these are at the end of this file.
6565 (define_expand "mulxf3"
6566 [(set (match_operand:XF 0 "register_operand" "")
6567 (mult:XF (match_operand:XF 1 "register_operand" "")
6568 (match_operand:XF 2 "register_operand" "")))]
6569 "TARGET_80387 && !TARGET_64BIT"
6572 (define_expand "multf3"
6573 [(set (match_operand:TF 0 "register_operand" "")
6574 (mult:TF (match_operand:TF 1 "register_operand" "")
6575 (match_operand:TF 2 "register_operand" "")))]
6579 (define_expand "muldf3"
6580 [(set (match_operand:DF 0 "register_operand" "")
6581 (mult:DF (match_operand:DF 1 "register_operand" "")
6582 (match_operand:DF 2 "nonimmediate_operand" "")))]
6583 "TARGET_80387 || TARGET_SSE2"
6586 (define_expand "mulsf3"
6587 [(set (match_operand:SF 0 "register_operand" "")
6588 (mult:SF (match_operand:SF 1 "register_operand" "")
6589 (match_operand:SF 2 "nonimmediate_operand" "")))]
6590 "TARGET_80387 || TARGET_SSE"
6593 ;; Divide instructions
6595 (define_insn "divqi3"
6596 [(set (match_operand:QI 0 "register_operand" "=a")
6597 (div:QI (match_operand:HI 1 "register_operand" "0")
6598 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6599 (clobber (reg:CC 17))]
6600 "TARGET_QIMODE_MATH"
6602 [(set_attr "type" "idiv")
6603 (set_attr "mode" "QI")
6604 (set_attr "ppro_uops" "few")])
6606 (define_insn "udivqi3"
6607 [(set (match_operand:QI 0 "register_operand" "=a")
6608 (udiv:QI (match_operand:HI 1 "register_operand" "0")
6609 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6610 (clobber (reg:CC 17))]
6611 "TARGET_QIMODE_MATH"
6613 [(set_attr "type" "idiv")
6614 (set_attr "mode" "QI")
6615 (set_attr "ppro_uops" "few")])
6617 ;; The patterns that match these are at the end of this file.
6619 (define_expand "divxf3"
6620 [(set (match_operand:XF 0 "register_operand" "")
6621 (div:XF (match_operand:XF 1 "register_operand" "")
6622 (match_operand:XF 2 "register_operand" "")))]
6623 "TARGET_80387 && !TARGET_64BIT"
6626 (define_expand "divtf3"
6627 [(set (match_operand:TF 0 "register_operand" "")
6628 (div:TF (match_operand:TF 1 "register_operand" "")
6629 (match_operand:TF 2 "register_operand" "")))]
6633 (define_expand "divdf3"
6634 [(set (match_operand:DF 0 "register_operand" "")
6635 (div:DF (match_operand:DF 1 "register_operand" "")
6636 (match_operand:DF 2 "nonimmediate_operand" "")))]
6637 "TARGET_80387 || TARGET_SSE2"
6640 (define_expand "divsf3"
6641 [(set (match_operand:SF 0 "register_operand" "")
6642 (div:SF (match_operand:SF 1 "register_operand" "")
6643 (match_operand:SF 2 "nonimmediate_operand" "")))]
6644 "TARGET_80387 || TARGET_SSE"
6647 ;; Remainder instructions.
6648 (define_expand "divmodsi4"
6649 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6650 (div:SI (match_operand:SI 1 "register_operand" "")
6651 (match_operand:SI 2 "nonimmediate_operand" "")))
6652 (set (match_operand:SI 3 "register_operand" "")
6653 (mod:SI (match_dup 1) (match_dup 2)))
6654 (clobber (reg:CC 17))])]
6658 ;; Allow to come the parameter in eax or edx to avoid extra moves.
6659 ;; Penalize eax case sligthly because it results in worse scheduling
6661 (define_insn "*divmodsi4_nocltd"
6662 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
6663 (div:SI (match_operand:SI 2 "register_operand" "1,0")
6664 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
6665 (set (match_operand:SI 1 "register_operand" "=&d,&d")
6666 (mod:SI (match_dup 2) (match_dup 3)))
6667 (clobber (reg:CC 17))]
6668 "!optimize_size && !TARGET_USE_CLTD"
6670 [(set_attr "type" "multi")])
6672 (define_insn "*divmodsi4_cltd"
6673 [(set (match_operand:SI 0 "register_operand" "=a")
6674 (div:SI (match_operand:SI 2 "register_operand" "a")
6675 (match_operand:SI 3 "nonimmediate_operand" "rm")))
6676 (set (match_operand:SI 1 "register_operand" "=&d")
6677 (mod:SI (match_dup 2) (match_dup 3)))
6678 (clobber (reg:CC 17))]
6679 "optimize_size || TARGET_USE_CLTD"
6681 [(set_attr "type" "multi")])
6683 (define_insn "*divmodsi_noext"
6684 [(set (match_operand:SI 0 "register_operand" "=a")
6685 (div:SI (match_operand:SI 1 "register_operand" "0")
6686 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6687 (set (match_operand:SI 3 "register_operand" "=d")
6688 (mod:SI (match_dup 1) (match_dup 2)))
6689 (use (match_operand:SI 4 "register_operand" "3"))
6690 (clobber (reg:CC 17))]
6693 [(set_attr "type" "idiv")
6694 (set_attr "mode" "SI")
6695 (set_attr "ppro_uops" "few")])
6698 [(set (match_operand:SI 0 "register_operand" "")
6699 (div:SI (match_operand:SI 1 "register_operand" "")
6700 (match_operand:SI 2 "nonimmediate_operand" "")))
6701 (set (match_operand:SI 3 "register_operand" "")
6702 (mod:SI (match_dup 1) (match_dup 2)))
6703 (clobber (reg:CC 17))]
6705 [(parallel [(set (match_dup 3)
6706 (ashiftrt:SI (match_dup 4) (const_int 31)))
6707 (clobber (reg:CC 17))])
6708 (parallel [(set (match_dup 0)
6709 (div:SI (reg:SI 0) (match_dup 2)))
6711 (mod:SI (reg:SI 0) (match_dup 2)))
6713 (clobber (reg:CC 17))])]
6716 /* Avoid use of cltd in favour of a mov+shift. */
6717 if (!TARGET_USE_CLTD && !optimize_size)
6719 if (true_regnum (operands[1]))
6720 emit_move_insn (operands[0], operands[1]);
6722 emit_move_insn (operands[3], operands[1]);
6723 operands[4] = operands[3];
6727 if (true_regnum (operands[1]))
6729 operands[4] = operands[1];
6733 (define_insn "divmodhi4"
6734 [(set (match_operand:HI 0 "register_operand" "=a")
6735 (div:HI (match_operand:HI 1 "register_operand" "0")
6736 (match_operand:HI 2 "nonimmediate_operand" "rm")))
6737 (set (match_operand:HI 3 "register_operand" "=&d")
6738 (mod:HI (match_dup 1) (match_dup 2)))
6739 (clobber (reg:CC 17))]
6740 "TARGET_HIMODE_MATH"
6741 "cwtd\;idiv{w}\\t%2"
6742 [(set_attr "type" "multi")
6743 (set_attr "length_immediate" "0")
6744 (set_attr "mode" "SI")])
6746 (define_insn "udivmodsi4"
6747 [(set (match_operand:SI 0 "register_operand" "=a")
6748 (udiv:SI (match_operand:SI 1 "register_operand" "0")
6749 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6750 (set (match_operand:SI 3 "register_operand" "=&d")
6751 (umod:SI (match_dup 1) (match_dup 2)))
6752 (clobber (reg:CC 17))]
6754 "xor{l}\\t%3, %3\;div{l}\\t%2"
6755 [(set_attr "type" "multi")
6756 (set_attr "length_immediate" "0")
6757 (set_attr "mode" "SI")])
6759 (define_insn "*udivmodsi4_noext"
6760 [(set (match_operand:SI 0 "register_operand" "=a")
6761 (udiv:SI (match_operand:SI 1 "register_operand" "0")
6762 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6763 (set (match_operand:SI 3 "register_operand" "=d")
6764 (umod:SI (match_dup 1) (match_dup 2)))
6766 (clobber (reg:CC 17))]
6769 [(set_attr "type" "idiv")
6770 (set_attr "ppro_uops" "few")
6771 (set_attr "mode" "SI")])
6774 [(set (match_operand:SI 0 "register_operand" "")
6775 (udiv:SI (match_operand:SI 1 "register_operand" "")
6776 (match_operand:SI 2 "nonimmediate_operand" "")))
6777 (set (match_operand:SI 3 "register_operand" "")
6778 (umod:SI (match_dup 1) (match_dup 2)))
6779 (clobber (reg:CC 17))]
6781 [(set (match_dup 3) (const_int 0))
6782 (parallel [(set (match_dup 0)
6783 (udiv:SI (match_dup 1) (match_dup 2)))
6785 (umod:SI (match_dup 1) (match_dup 2)))
6787 (clobber (reg:CC 17))])]
6790 (define_expand "udivmodhi4"
6791 [(set (match_dup 4) (const_int 0))
6792 (parallel [(set (match_operand:HI 0 "register_operand" "")
6793 (udiv:HI (match_operand:HI 1 "register_operand" "")
6794 (match_operand:HI 2 "nonimmediate_operand" "")))
6795 (set (match_operand:HI 3 "register_operand" "")
6796 (umod:HI (match_dup 1) (match_dup 2)))
6798 (clobber (reg:CC 17))])]
6799 "TARGET_HIMODE_MATH"
6800 "operands[4] = gen_reg_rtx (HImode);")
6802 (define_insn "*udivmodhi_noext"
6803 [(set (match_operand:HI 0 "register_operand" "=a")
6804 (udiv:HI (match_operand:HI 1 "register_operand" "0")
6805 (match_operand:HI 2 "nonimmediate_operand" "rm")))
6806 (set (match_operand:HI 3 "register_operand" "=d")
6807 (umod:HI (match_dup 1) (match_dup 2)))
6808 (use (match_operand:HI 4 "register_operand" "3"))
6809 (clobber (reg:CC 17))]
6812 [(set_attr "type" "idiv")
6813 (set_attr "mode" "HI")
6814 (set_attr "ppro_uops" "few")])
6816 ;; We can not use div/idiv for double division, because it causes
6817 ;; "division by zero" on the overflow and that's not what we expect
6818 ;; from truncate. Because true (non truncating) double division is
6819 ;; never generated, we can't create this insn anyway.
6822 ; [(set (match_operand:SI 0 "register_operand" "=a")
6824 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
6826 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
6827 ; (set (match_operand:SI 3 "register_operand" "=d")
6829 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
6830 ; (clobber (reg:CC 17))]
6832 ; "div{l}\\t{%2, %0|%0, %2}"
6833 ; [(set_attr "type" "idiv")
6834 ; (set_attr "ppro_uops" "few")])
6836 ;;- Logical AND instructions
6838 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
6839 ;; Note that this excludes ah.
6842 (define_insn "testsi_1"
6845 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
6846 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
6848 "ix86_match_ccmode (insn, CCNOmode)"
6849 "test{l}\\t{%1, %0|%0, %1}"
6850 [(set_attr "type" "test")
6851 (set_attr "modrm" "0,1,1")
6852 (set_attr "mode" "SI")
6853 (set_attr "pent_pair" "uv,np,uv")])
6855 (define_expand "testsi_ccno_1"
6858 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
6859 (match_operand:SI 1 "nonmemory_operand" ""))
6864 (define_insn "*testhi_1"
6866 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
6867 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
6869 "ix86_match_ccmode (insn, CCNOmode)"
6870 "test{w}\\t{%1, %0|%0, %1}"
6871 [(set_attr "type" "test")
6872 (set_attr "modrm" "0,1,1")
6873 (set_attr "mode" "HI")
6874 (set_attr "pent_pair" "uv,np,uv")])
6876 (define_expand "testqi_ccz_1"
6878 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
6879 (match_operand:QI 1 "nonmemory_operand" ""))
6884 (define_insn "*testqi_1"
6886 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
6887 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
6889 "ix86_match_ccmode (insn, CCNOmode)"
6892 if (which_alternative == 3)
6894 if (GET_CODE (operands[1]) == CONST_INT
6895 && (INTVAL (operands[1]) & 0xffffff00))
6896 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
6897 return \"test{l}\\t{%1, %k0|%k0, %1}\";
6899 return \"test{b}\\t{%1, %0|%0, %1}\";
6901 [(set_attr "type" "test")
6902 (set_attr "modrm" "0,1,1,1")
6903 (set_attr "mode" "QI,QI,QI,SI")
6904 (set_attr "pent_pair" "uv,np,uv,np")])
6906 (define_expand "testqi_ext_ccno_0"
6911 (match_operand 0 "ext_register_operand" "")
6914 (match_operand 1 "const_int_operand" ""))
6919 (define_insn "*testqi_ext_0"
6924 (match_operand 0 "ext_register_operand" "Q")
6927 (match_operand 1 "const_int_operand" "n"))
6929 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
6930 && ix86_match_ccmode (insn, CCNOmode)"
6931 "test{b}\\t{%1, %h0|%h0, %1}"
6932 [(set_attr "type" "test")
6933 (set_attr "mode" "QI")
6934 (set_attr "length_immediate" "1")
6935 (set_attr "pent_pair" "np")])
6937 (define_insn "*testqi_ext_1"
6942 (match_operand 0 "ext_register_operand" "Q")
6946 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
6948 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
6949 "test{b}\\t{%1, %h0|%h0, %1}"
6950 [(set_attr "type" "test")
6951 (set_attr "mode" "QI")])
6953 (define_insn "*testqi_ext_1_rex64"
6958 (match_operand 0 "ext_register_operand" "Q")
6962 (match_operand:QI 1 "ext_register_operand" "Q")))
6964 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
6965 "test{b}\\t{%1, %h0|%h0, %1}"
6966 [(set_attr "type" "test")
6967 (set_attr "mode" "QI")])
6969 (define_insn "*testqi_ext_2"
6974 (match_operand 0 "ext_register_operand" "Q")
6978 (match_operand 1 "ext_register_operand" "Q")
6982 "ix86_match_ccmode (insn, CCNOmode)"
6983 "test{b}\\t{%h1, %h0|%h0, %h1}"
6984 [(set_attr "type" "test")
6985 (set_attr "mode" "QI")])
6987 ;; Combine likes to form bit extractions for some tests. Humor it.
6988 (define_insn "*testqi_ext_3"
6990 (compare (zero_extract:SI
6991 (match_operand 0 "nonimmediate_operand" "rm")
6992 (match_operand:SI 1 "const_int_operand" "")
6993 (match_operand:SI 2 "const_int_operand" ""))
6995 "ix86_match_ccmode (insn, CCNOmode)
6996 && (GET_MODE (operands[0]) == SImode
6997 || GET_MODE (operands[0]) == HImode
6998 || GET_MODE (operands[0]) == QImode)"
7003 (compare (zero_extract:SI
7004 (match_operand 0 "nonimmediate_operand" "rm")
7005 (match_operand:SI 1 "const_int_operand" "")
7006 (match_operand:SI 2 "const_int_operand" ""))
7008 "ix86_match_ccmode (insn, CCNOmode)"
7009 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
7012 HOST_WIDE_INT len = INTVAL (operands[1]);
7013 HOST_WIDE_INT pos = INTVAL (operands[2]);
7015 enum machine_mode mode;
7017 mode = GET_MODE (operands[0]);
7018 if (GET_CODE (operands[0]) == MEM)
7020 /* ??? Combine likes to put non-volatile mem extractions in QImode
7021 no matter the size of the test. So find a mode that works. */
7022 if (! MEM_VOLATILE_P (operands[0]))
7024 mode = smallest_mode_for_size (pos + len, MODE_INT);
7025 operands[0] = change_address (operands[0], mode, NULL_RTX);
7028 else if (mode == HImode && pos + len <= 8)
7030 /* Small HImode tests can be converted to QImode. */
7032 operands[0] = gen_lowpart (QImode, operands[0]);
7035 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7036 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7038 operands[3] = gen_rtx_AND (mode, operands[0], GEN_INT (mask));
7041 ;; %%% This used to optimize known byte-wide and operations to memory,
7042 ;; and sometimes to QImode registers. If this is considered useful,
7043 ;; it should be done with splitters.
7045 (define_expand "andsi3"
7046 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7047 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
7048 (match_operand:SI 2 "general_operand" "")))
7049 (clobber (reg:CC 17))]
7051 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
7053 (define_insn "*andsi_1"
7054 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
7055 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
7056 (match_operand:SI 2 "general_operand" "ri,rm,L")))
7057 (clobber (reg:CC 17))]
7058 "ix86_binary_operator_ok (AND, SImode, operands)"
7061 switch (get_attr_type (insn))
7065 enum machine_mode mode;
7067 if (GET_CODE (operands[2]) != CONST_INT)
7069 if (INTVAL (operands[2]) == 0xff)
7071 else if (INTVAL (operands[2]) == 0xffff)
7076 operands[1] = gen_lowpart (mode, operands[1]);
7078 return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
7080 return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
7084 if (! rtx_equal_p (operands[0], operands[1]))
7086 return \"and{l}\\t{%2, %0|%0, %2}\";
7089 [(set_attr "type" "alu,alu,imovx")
7090 (set_attr "length_immediate" "*,*,0")
7091 (set_attr "mode" "SI")])
7094 [(set (match_operand:SI 0 "register_operand" "")
7095 (and:SI (match_dup 0)
7096 (const_int -65536)))
7097 (clobber (reg:CC 17))]
7099 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7100 "operands[1] = gen_lowpart (HImode, operands[0]);")
7103 [(set (match_operand 0 "q_regs_operand" "")
7106 (clobber (reg:CC 17))]
7107 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
7108 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode)"
7109 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7110 "operands[1] = gen_lowpart (QImode, operands[0]);")
7113 [(set (match_operand 0 "q_regs_operand" "")
7115 (const_int -65281)))
7116 (clobber (reg:CC 17))]
7117 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
7118 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode)"
7119 [(parallel [(set (zero_extract:SI (match_dup 0)
7123 (zero_extract:SI (match_dup 0)
7126 (zero_extract:SI (match_dup 0)
7129 (clobber (reg:CC 17))])]
7130 "operands[0] = gen_lowpart (SImode, operands[0]);")
7132 (define_insn "*andsi_2"
7134 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7135 (match_operand:SI 2 "general_operand" "rim,ri"))
7137 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
7138 (and:SI (match_dup 1) (match_dup 2)))]
7139 "ix86_match_ccmode (insn, CCNOmode)
7140 && ix86_binary_operator_ok (AND, SImode, operands)"
7141 "and{l}\\t{%2, %0|%0, %2}"
7142 [(set_attr "type" "alu")
7143 (set_attr "mode" "SI")])
7145 (define_expand "andhi3"
7146 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7147 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
7148 (match_operand:HI 2 "general_operand" "")))
7149 (clobber (reg:CC 17))]
7150 "TARGET_HIMODE_MATH"
7151 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
7153 (define_insn "*andhi_1"
7154 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
7155 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
7156 (match_operand:HI 2 "general_operand" "ri,rm,L")))
7157 (clobber (reg:CC 17))]
7158 "ix86_binary_operator_ok (AND, HImode, operands)"
7161 switch (get_attr_type (insn))
7164 if (GET_CODE (operands[2]) != CONST_INT)
7166 if (INTVAL (operands[2]) == 0xff)
7167 return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
7171 if (! rtx_equal_p (operands[0], operands[1]))
7174 return \"and{w}\\t{%2, %0|%0, %2}\";
7177 [(set_attr "type" "alu,alu,imovx")
7178 (set_attr "length_immediate" "*,*,0")
7179 (set_attr "mode" "HI,HI,SI")])
7181 (define_insn "*andhi_2"
7183 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
7184 (match_operand:HI 2 "general_operand" "rim,ri"))
7186 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
7187 (and:HI (match_dup 1) (match_dup 2)))]
7188 "ix86_match_ccmode (insn, CCNOmode)
7189 && ix86_binary_operator_ok (AND, HImode, operands)"
7190 "and{w}\\t{%2, %0|%0, %2}"
7191 [(set_attr "type" "alu")
7192 (set_attr "mode" "HI")])
7194 (define_expand "andqi3"
7195 [(set (match_operand:QI 0 "nonimmediate_operand" "")
7196 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
7197 (match_operand:QI 2 "general_operand" "")))
7198 (clobber (reg:CC 17))]
7199 "TARGET_QIMODE_MATH"
7200 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
7202 ;; %%% Potential partial reg stall on alternative 2. What to do?
7203 (define_insn "*andqi_1"
7204 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
7205 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7206 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
7207 (clobber (reg:CC 17))]
7208 "ix86_binary_operator_ok (AND, QImode, operands)"
7210 and{b}\\t{%2, %0|%0, %2}
7211 and{b}\\t{%2, %0|%0, %2}
7212 and{l}\\t{%k2, %k0|%k0, %k2}"
7213 [(set_attr "type" "alu")
7214 (set_attr "mode" "QI,QI,SI")])
7216 (define_insn "*andqi_1_slp"
7217 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7218 (and:QI (match_dup 0)
7219 (match_operand:QI 1 "general_operand" "qi,qmi")))
7220 (clobber (reg:CC 17))]
7222 "and{b}\\t{%1, %0|%0, %1}"
7223 [(set_attr "type" "alu1")
7224 (set_attr "mode" "QI")])
7226 (define_insn "*andqi_2"
7229 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7230 (match_operand:QI 2 "general_operand" "qim,qi,i"))
7232 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
7233 (and:QI (match_dup 1) (match_dup 2)))]
7234 "ix86_match_ccmode (insn, CCNOmode)
7235 && ix86_binary_operator_ok (AND, QImode, operands)"
7238 if (which_alternative == 2)
7240 if (GET_CODE (operands[2]) == CONST_INT
7241 && (INTVAL (operands[2]) & 0xffffff00))
7242 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
7243 return \"and{l}\\t{%2, %k0|%k0, %2}\";
7245 return \"and{b}\\t{%2, %0|%0, %2}\";
7247 [(set_attr "type" "alu")
7248 (set_attr "mode" "QI,QI,SI")])
7250 (define_insn "*andqi_2_slp"
7253 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
7254 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
7256 (set (strict_low_part (match_dup 0))
7257 (and:QI (match_dup 0) (match_dup 1)))]
7258 "ix86_match_ccmode (insn, CCNOmode)"
7259 "and{b}\\t{%1, %0|%0, %1}"
7260 [(set_attr "type" "alu1")
7261 (set_attr "mode" "QI")])
7263 ;; ??? A bug in recog prevents it from recognizing a const_int as an
7264 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
7265 ;; for a QImode operand, which of course failed.
7267 (define_insn "andqi_ext_0"
7268 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7273 (match_operand 1 "ext_register_operand" "0")
7276 (match_operand 2 "const_int_operand" "n")))
7277 (clobber (reg:CC 17))]
7278 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
7279 "and{b}\\t{%2, %h0|%h0, %2}"
7280 [(set_attr "type" "alu")
7281 (set_attr "length_immediate" "1")
7282 (set_attr "mode" "QI")])
7284 ;; Generated by peephole translating test to and. This shows up
7285 ;; often in fp comparisons.
7287 (define_insn "*andqi_ext_0_cc"
7292 (match_operand 1 "ext_register_operand" "0")
7295 (match_operand 2 "const_int_operand" "n"))
7297 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7306 "ix86_match_ccmode (insn, CCNOmode)
7307 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
7308 "and{b}\\t{%2, %h0|%h0, %2}"
7309 [(set_attr "type" "alu")
7310 (set_attr "length_immediate" "1")
7311 (set_attr "mode" "QI")])
7313 (define_insn "*andqi_ext_1"
7314 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7319 (match_operand 1 "ext_register_operand" "0")
7323 (match_operand:QI 2 "general_operand" "Qm"))))
7324 (clobber (reg:CC 17))]
7326 "and{b}\\t{%2, %h0|%h0, %2}"
7327 [(set_attr "type" "alu")
7328 (set_attr "length_immediate" "0")
7329 (set_attr "mode" "QI")])
7331 (define_insn "*andqi_ext_1_rex64"
7332 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7337 (match_operand 1 "ext_register_operand" "0")
7341 (match_operand:QI 2 "ext_register_operand" "Q"))))
7342 (clobber (reg:CC 17))]
7344 "and{b}\\t{%2, %h0|%h0, %2}"
7345 [(set_attr "type" "alu")
7346 (set_attr "length_immediate" "0")
7347 (set_attr "mode" "QI")])
7349 (define_insn "*andqi_ext_2"
7350 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7355 (match_operand 1 "ext_register_operand" "%0")
7359 (match_operand 2 "ext_register_operand" "Q")
7362 (clobber (reg:CC 17))]
7364 "and{b}\\t{%h2, %h0|%h0, %h2}"
7365 [(set_attr "type" "alu")
7366 (set_attr "length_immediate" "0")
7367 (set_attr "mode" "QI")])
7369 ;; Logical inclusive OR instructions
7371 ;; %%% This used to optimize known byte-wide and operations to memory.
7372 ;; If this is considered useful, it should be done with splitters.
7374 (define_expand "iorsi3"
7375 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7376 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
7377 (match_operand:SI 2 "general_operand" "")))
7378 (clobber (reg:CC 17))]
7380 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
7382 (define_insn "*iorsi_1"
7383 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7384 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7385 (match_operand:SI 2 "general_operand" "ri,rmi")))
7386 (clobber (reg:CC 17))]
7387 "ix86_binary_operator_ok (IOR, SImode, operands)"
7388 "or{l}\\t{%2, %0|%0, %2}"
7389 [(set_attr "type" "alu")
7390 (set_attr "mode" "SI")])
7392 (define_insn "*iorsi_2"
7394 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7395 (match_operand:SI 2 "general_operand" "rim,ri"))
7397 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
7398 (ior:SI (match_dup 1) (match_dup 2)))]
7399 "ix86_match_ccmode (insn, CCNOmode)
7400 && ix86_binary_operator_ok (IOR, SImode, operands)"
7401 "or{l}\\t{%2, %0|%0, %2}"
7402 [(set_attr "type" "alu")
7403 (set_attr "mode" "SI")])
7405 (define_insn "*iorsi_3"
7407 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7408 (match_operand:SI 2 "general_operand" "rim"))
7410 (clobber (match_scratch:SI 0 "=r"))]
7411 "ix86_match_ccmode (insn, CCNOmode)
7412 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7413 "or{l}\\t{%2, %0|%0, %2}"
7414 [(set_attr "type" "alu")
7415 (set_attr "mode" "SI")])
7417 (define_expand "iorhi3"
7418 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7419 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
7420 (match_operand:HI 2 "general_operand" "")))
7421 (clobber (reg:CC 17))]
7422 "TARGET_HIMODE_MATH"
7423 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
7425 (define_insn "*iorhi_1"
7426 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
7427 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
7428 (match_operand:HI 2 "general_operand" "rmi,ri")))
7429 (clobber (reg:CC 17))]
7430 "ix86_binary_operator_ok (IOR, HImode, operands)"
7431 "or{w}\\t{%2, %0|%0, %2}"
7432 [(set_attr "type" "alu")
7433 (set_attr "mode" "HI")])
7435 (define_insn "*iorhi_2"
7437 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
7438 (match_operand:HI 2 "general_operand" "rim,ri"))
7440 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
7441 (ior:HI (match_dup 1) (match_dup 2)))]
7442 "ix86_match_ccmode (insn, CCNOmode)
7443 && ix86_binary_operator_ok (IOR, HImode, operands)"
7444 "or{w}\\t{%2, %0|%0, %2}"
7445 [(set_attr "type" "alu")
7446 (set_attr "mode" "HI")])
7448 (define_insn "*iorhi_3"
7450 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
7451 (match_operand:HI 2 "general_operand" "rim"))
7453 (clobber (match_scratch:HI 0 "=r"))]
7454 "ix86_match_ccmode (insn, CCNOmode)
7455 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7456 "or{w}\\t{%2, %0|%0, %2}"
7457 [(set_attr "type" "alu")
7458 (set_attr "mode" "HI")])
7460 (define_expand "iorqi3"
7461 [(set (match_operand:QI 0 "nonimmediate_operand" "")
7462 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
7463 (match_operand:QI 2 "general_operand" "")))
7464 (clobber (reg:CC 17))]
7465 "TARGET_QIMODE_MATH"
7466 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
7468 ;; %%% Potential partial reg stall on alternative 2. What to do?
7469 (define_insn "*iorqi_1"
7470 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
7471 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7472 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
7473 (clobber (reg:CC 17))]
7474 "ix86_binary_operator_ok (IOR, QImode, operands)"
7476 or{b}\\t{%2, %0|%0, %2}
7477 or{b}\\t{%2, %0|%0, %2}
7478 or{l}\\t{%k2, %k0|%k0, %k2}"
7479 [(set_attr "type" "alu")
7480 (set_attr "mode" "QI,QI,SI")])
7482 (define_insn "*iorqi_1_slp"
7483 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
7484 (ior:QI (match_dup 0)
7485 (match_operand:QI 1 "general_operand" "qmi,qi")))
7486 (clobber (reg:CC 17))]
7488 "or{b}\\t{%1, %0|%0, %1}"
7489 [(set_attr "type" "alu1")
7490 (set_attr "mode" "QI")])
7492 (define_insn "*iorqi_2"
7494 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
7495 (match_operand:QI 2 "general_operand" "qim,qi"))
7497 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
7498 (ior:QI (match_dup 1) (match_dup 2)))]
7499 "ix86_match_ccmode (insn, CCNOmode)
7500 && ix86_binary_operator_ok (IOR, QImode, operands)"
7501 "or{b}\\t{%2, %0|%0, %2}"
7502 [(set_attr "type" "alu")
7503 (set_attr "mode" "QI")])
7505 (define_insn "*iorqi_2_slp"
7507 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
7508 (match_operand:QI 1 "general_operand" "qim,qi"))
7510 (set (strict_low_part (match_dup 0))
7511 (ior:QI (match_dup 0) (match_dup 1)))]
7512 "ix86_match_ccmode (insn, CCNOmode)"
7513 "or{b}\\t{%1, %0|%0, %1}"
7514 [(set_attr "type" "alu1")
7515 (set_attr "mode" "QI")])
7517 (define_insn "*iorqi_3"
7519 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7520 (match_operand:QI 2 "general_operand" "qim"))
7522 (clobber (match_scratch:QI 0 "=q"))]
7523 "ix86_match_ccmode (insn, CCNOmode)
7524 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7525 "or{b}\\t{%2, %0|%0, %2}"
7526 [(set_attr "type" "alu")
7527 (set_attr "mode" "QI")])
7530 ;; Logical XOR instructions
7532 ;; %%% This used to optimize known byte-wide and operations to memory.
7533 ;; If this is considered useful, it should be done with splitters.
7535 (define_expand "xorsi3"
7536 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7537 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
7538 (match_operand:SI 2 "general_operand" "")))
7539 (clobber (reg:CC 17))]
7541 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
7543 (define_insn "*xorsi_1"
7544 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7545 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7546 (match_operand:SI 2 "general_operand" "ri,rm")))
7547 (clobber (reg:CC 17))]
7548 "ix86_binary_operator_ok (XOR, SImode, operands)"
7549 "xor{l}\\t{%2, %0|%0, %2}"
7550 [(set_attr "type" "alu")
7551 (set_attr "mode" "SI")])
7553 (define_insn "*xorsi_2"
7555 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7556 (match_operand:SI 2 "general_operand" "rim,ri"))
7558 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
7559 (xor:SI (match_dup 1) (match_dup 2)))]
7560 "ix86_match_ccmode (insn, CCNOmode)
7561 && ix86_binary_operator_ok (XOR, SImode, operands)"
7562 "xor{l}\\t{%2, %0|%0, %2}"
7563 [(set_attr "type" "alu")
7564 (set_attr "mode" "SI")])
7566 (define_insn "*xorsi_3"
7568 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7569 (match_operand:SI 2 "general_operand" "rim"))
7571 (clobber (match_scratch:SI 0 "=r"))]
7572 "ix86_match_ccmode (insn, CCNOmode)
7573 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7574 "xor{l}\\t{%2, %0|%0, %2}"
7575 [(set_attr "type" "alu")
7576 (set_attr "mode" "SI")])
7578 (define_expand "xorhi3"
7579 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7580 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
7581 (match_operand:HI 2 "general_operand" "")))
7582 (clobber (reg:CC 17))]
7583 "TARGET_HIMODE_MATH"
7584 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
7586 (define_insn "*xorhi_1"
7587 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
7588 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
7589 (match_operand:HI 2 "general_operand" "rmi,ri")))
7590 (clobber (reg:CC 17))]
7591 "ix86_binary_operator_ok (XOR, HImode, operands)"
7592 "xor{w}\\t{%2, %0|%0, %2}"
7593 [(set_attr "type" "alu")
7594 (set_attr "mode" "HI")])
7596 (define_insn "*xorhi_2"
7598 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
7599 (match_operand:HI 2 "general_operand" "rim,ri"))
7601 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
7602 (xor:HI (match_dup 1) (match_dup 2)))]
7603 "ix86_match_ccmode (insn, CCNOmode)
7604 && ix86_binary_operator_ok (XOR, HImode, operands)"
7605 "xor{w}\\t{%2, %0|%0, %2}"
7606 [(set_attr "type" "alu")
7607 (set_attr "mode" "HI")])
7609 (define_insn "*xorhi_3"
7611 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
7612 (match_operand:HI 2 "general_operand" "rim"))
7614 (clobber (match_scratch:HI 0 "=r"))]
7615 "ix86_match_ccmode (insn, CCNOmode)
7616 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7617 "xor{w}\\t{%2, %0|%0, %2}"
7618 [(set_attr "type" "alu")
7619 (set_attr "mode" "HI")])
7621 (define_expand "xorqi3"
7622 [(set (match_operand:QI 0 "nonimmediate_operand" "")
7623 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
7624 (match_operand:QI 2 "general_operand" "")))
7625 (clobber (reg:CC 17))]
7626 "TARGET_QIMODE_MATH"
7627 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
7629 ;; %%% Potential partial reg stall on alternative 2. What to do?
7630 (define_insn "*xorqi_1"
7631 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
7632 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7633 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
7634 (clobber (reg:CC 17))]
7635 "ix86_binary_operator_ok (XOR, QImode, operands)"
7637 xor{b}\\t{%2, %0|%0, %2}
7638 xor{b}\\t{%2, %0|%0, %2}
7639 xor{l}\\t{%k2, %k0|%k0, %k2}"
7640 [(set_attr "type" "alu")
7641 (set_attr "mode" "QI,QI,SI")])
7643 (define_insn "*xorqi_ext_1"
7644 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7648 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
7651 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
7654 (clobber (reg:CC 17))]
7656 "xor{b}\\t{%h2, %h0|%h0, %h2}"
7657 [(set_attr "type" "alu")
7658 (set_attr "length_immediate" "0")
7659 (set_attr "mode" "QI")])
7661 (define_insn "*xorqi_cc_1"
7664 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
7665 (match_operand:QI 2 "general_operand" "qim,qi"))
7667 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
7668 (xor:QI (match_dup 1) (match_dup 2)))]
7669 "ix86_match_ccmode (insn, CCNOmode)
7670 && ix86_binary_operator_ok (XOR, QImode, operands)"
7671 "xor{b}\\t{%2, %0|%0, %2}"
7672 [(set_attr "type" "alu")
7673 (set_attr "mode" "QI")])
7675 (define_insn "*xorqi_cc_2"
7678 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7679 (match_operand:QI 2 "general_operand" "qim"))
7681 (clobber (match_scratch:QI 0 "=q"))]
7682 "ix86_match_ccmode (insn, CCNOmode)
7683 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7684 "xor{b}\\t{%2, %0|%0, %2}"
7685 [(set_attr "type" "alu")
7686 (set_attr "mode" "QI")])
7688 (define_insn "*xorqi_cc_ext_1"
7693 (match_operand 1 "ext_register_operand" "0")
7696 (match_operand:QI 2 "general_operand" "qmn"))
7698 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
7702 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
7704 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7705 "xor{b}\\t{%2, %h0|%h0, %2}"
7706 [(set_attr "type" "alu")
7707 (set_attr "mode" "QI")])
7709 (define_insn "*xorqi_cc_ext_1_rex64"
7714 (match_operand 1 "ext_register_operand" "0")
7717 (match_operand:QI 2 "nonmemory_operand" "Qn"))
7719 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7723 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
7725 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7726 "xor{b}\\t{%2, %h0|%h0, %2}"
7727 [(set_attr "type" "alu")
7728 (set_attr "mode" "QI")])
7730 (define_expand "xorqi_cc_ext_1"
7736 (match_operand 1 "ext_register_operand" "")
7739 (match_operand:QI 2 "general_operand" ""))
7741 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
7745 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
7750 ;; Negation instructions
7752 ;; %%% define_expand from the very first?
7754 (define_expand "negdi2"
7755 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
7756 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
7757 (clobber (reg:CC 17))])]
7759 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
7761 (define_insn "*negdi2_1"
7762 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
7763 (neg:DI (match_operand:DI 1 "general_operand" "0")))
7764 (clobber (reg:CC 17))]
7766 && ix86_unary_operator_ok (NEG, DImode, operands)"
7770 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7771 (neg:DI (match_operand:DI 1 "general_operand" "")))
7772 (clobber (reg:CC 17))]
7777 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
7778 (set (match_dup 0) (neg:SI (match_dup 2)))])
7781 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7784 (clobber (reg:CC 17))])
7787 (neg:SI (match_dup 1)))
7788 (clobber (reg:CC 17))])]
7789 "split_di (operands+1, 1, operands+2, operands+3);
7790 split_di (operands+0, 1, operands+0, operands+1);")
7792 (define_expand "negsi2"
7793 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7794 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
7795 (clobber (reg:CC 17))])]
7797 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
7799 (define_insn "*negsi2_1"
7800 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7801 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
7802 (clobber (reg:CC 17))]
7803 "ix86_unary_operator_ok (NEG, SImode, operands)"
7805 [(set_attr "type" "negnot")
7806 (set_attr "mode" "SI")])
7808 ;; The problem with neg is that it does not perform (compare x 0),
7809 ;; it really performs (compare 0 x), which leaves us with the zero
7810 ;; flag being the only useful item.
7812 (define_insn "*negsi2_cmpz"
7814 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
7816 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7817 (neg:SI (match_dup 1)))]
7818 "ix86_unary_operator_ok (NEG, SImode, operands)"
7820 [(set_attr "type" "negnot")
7821 (set_attr "mode" "SI")])
7823 (define_expand "neghi2"
7824 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7825 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
7826 (clobber (reg:CC 17))])]
7827 "TARGET_HIMODE_MATH"
7828 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
7830 (define_insn "*neghi2_1"
7831 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
7832 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
7833 (clobber (reg:CC 17))]
7834 "ix86_unary_operator_ok (NEG, HImode, operands)"
7836 [(set_attr "type" "negnot")
7837 (set_attr "mode" "HI")])
7839 (define_insn "*neghi2_cmpz"
7841 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
7843 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
7844 (neg:HI (match_dup 1)))]
7845 "ix86_unary_operator_ok (NEG, HImode, operands)"
7847 [(set_attr "type" "negnot")
7848 (set_attr "mode" "HI")])
7850 (define_expand "negqi2"
7851 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7852 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
7853 (clobber (reg:CC 17))])]
7854 "TARGET_QIMODE_MATH"
7855 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
7857 (define_insn "*negqi2_1"
7858 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
7859 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
7860 (clobber (reg:CC 17))]
7861 "ix86_unary_operator_ok (NEG, QImode, operands)"
7863 [(set_attr "type" "negnot")
7864 (set_attr "mode" "QI")])
7866 (define_insn "*negqi2_cmpz"
7868 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
7870 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
7871 (neg:QI (match_dup 1)))]
7872 "ix86_unary_operator_ok (NEG, QImode, operands)"
7874 [(set_attr "type" "negnot")
7875 (set_attr "mode" "QI")])
7877 ;; Changing of sign for FP values is doable using integer unit too.
7879 (define_expand "negsf2"
7880 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
7881 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
7882 (clobber (reg:CC 17))])]
7884 "ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
7886 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7887 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7889 (define_insn "*negsf2_if"
7890 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
7891 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
7892 (clobber (reg:CC 17))]
7893 "TARGET_80387 && ix86_unary_operator_ok (NEG, SFmode, operands)"
7897 [(set (match_operand:SF 0 "register_operand" "")
7898 (neg:SF (match_operand:SF 1 "register_operand" "")))
7899 (clobber (reg:CC 17))]
7900 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7902 (neg:SF (match_dup 1)))]
7906 [(set (match_operand:SF 0 "register_operand" "")
7907 (neg:SF (match_operand:SF 1 "register_operand" "")))
7908 (clobber (reg:CC 17))]
7909 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7910 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
7911 (clobber (reg:CC 17))])]
7912 "operands[1] = GEN_INT (0x80000000);
7913 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
7916 [(set (match_operand 0 "memory_operand" "")
7917 (neg (match_operand 1 "memory_operand" "")))
7918 (clobber (reg:CC 17))]
7919 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
7920 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7921 (clobber (reg:CC 17))])]
7924 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
7926 /* XFmode's size is 12, but only 10 bytes are used. */
7929 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
7930 operands[0] = adj_offsettable_operand (operands[0], size - 1);
7931 operands[1] = GEN_INT (0x80);
7934 (define_expand "negdf2"
7935 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
7936 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
7937 (clobber (reg:CC 17))])]
7939 "ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
7941 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7942 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7944 (define_insn "*negdf2_if"
7945 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
7946 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
7947 (clobber (reg:CC 17))]
7948 "TARGET_80387 && ix86_unary_operator_ok (NEG, DFmode, operands)"
7952 [(set (match_operand:DF 0 "register_operand" "")
7953 (neg:DF (match_operand:DF 1 "register_operand" "")))
7954 (clobber (reg:CC 17))]
7955 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7957 (neg:DF (match_dup 1)))]
7961 [(set (match_operand:DF 0 "register_operand" "")
7962 (neg:DF (match_operand:DF 1 "register_operand" "")))
7963 (clobber (reg:CC 17))]
7964 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7965 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
7966 (clobber (reg:CC 17))])]
7967 "operands[4] = GEN_INT (0x80000000);
7968 split_di (operands+0, 1, operands+2, operands+3);")
7970 (define_expand "negxf2"
7971 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
7972 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
7973 (clobber (reg:CC 17))])]
7974 "TARGET_80387 && !TARGET_64BIT"
7975 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
7977 (define_expand "negtf2"
7978 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7979 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
7980 (clobber (reg:CC 17))])]
7982 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
7984 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7985 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7987 (define_insn "*negxf2_if"
7988 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
7989 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
7990 (clobber (reg:CC 17))]
7991 "TARGET_80387 && !TARGET_64BIT
7992 && ix86_unary_operator_ok (NEG, XFmode, operands)"
7996 [(set (match_operand:XF 0 "register_operand" "")
7997 (neg:XF (match_operand:XF 1 "register_operand" "")))
7998 (clobber (reg:CC 17))]
7999 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
8001 (neg:XF (match_dup 1)))]
8005 [(set (match_operand:XF 0 "register_operand" "")
8006 (neg:XF (match_operand:XF 1 "register_operand" "")))
8007 (clobber (reg:CC 17))]
8008 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
8009 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
8010 (clobber (reg:CC 17))])]
8011 "operands[1] = GEN_INT (0x8000);
8012 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
8014 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
8015 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
8017 (define_insn "*negtf2_if"
8018 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
8019 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
8020 (clobber (reg:CC 17))]
8021 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
8025 [(set (match_operand:TF 0 "register_operand" "")
8026 (neg:TF (match_operand:TF 1 "register_operand" "")))
8027 (clobber (reg:CC 17))]
8028 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
8030 (neg:TF (match_dup 1)))]
8034 [(set (match_operand:TF 0 "register_operand" "")
8035 (neg:TF (match_operand:TF 1 "register_operand" "")))
8036 (clobber (reg:CC 17))]
8037 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
8038 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
8039 (clobber (reg:CC 17))])]
8040 "operands[1] = GEN_INT (0x8000);
8041 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
8043 ;; Conditionize these after reload. If they matches before reload, we
8044 ;; lose the clobber and ability to use integer instructions.
8046 (define_insn "*negsf2_1"
8047 [(set (match_operand:SF 0 "register_operand" "=f")
8048 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
8049 "TARGET_80387 && reload_completed"
8051 [(set_attr "type" "fsgn")
8052 (set_attr "mode" "SF")
8053 (set_attr "ppro_uops" "few")])
8055 (define_insn "*negdf2_1"
8056 [(set (match_operand:DF 0 "register_operand" "=f")
8057 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
8058 "TARGET_80387 && reload_completed"
8060 [(set_attr "type" "fsgn")
8061 (set_attr "mode" "DF")
8062 (set_attr "ppro_uops" "few")])
8064 (define_insn "*negextendsfdf2"
8065 [(set (match_operand:DF 0 "register_operand" "=f")
8066 (neg:DF (float_extend:DF
8067 (match_operand:SF 1 "register_operand" "0"))))]
8070 [(set_attr "type" "fsgn")
8071 (set_attr "mode" "DF")
8072 (set_attr "ppro_uops" "few")])
8074 (define_insn "*negxf2_1"
8075 [(set (match_operand:XF 0 "register_operand" "=f")
8076 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
8077 "TARGET_80387 && !TARGET_64BIT && reload_completed"
8079 [(set_attr "type" "fsgn")
8080 (set_attr "mode" "XF")
8081 (set_attr "ppro_uops" "few")])
8083 (define_insn "*negextenddfxf2"
8084 [(set (match_operand:XF 0 "register_operand" "=f")
8085 (neg:XF (float_extend:XF
8086 (match_operand:DF 1 "register_operand" "0"))))]
8087 "TARGET_80387 && !TARGET_64BIT"
8089 [(set_attr "type" "fsgn")
8090 (set_attr "mode" "XF")
8091 (set_attr "ppro_uops" "few")])
8093 (define_insn "*negextendsfxf2"
8094 [(set (match_operand:XF 0 "register_operand" "=f")
8095 (neg:XF (float_extend:XF
8096 (match_operand:SF 1 "register_operand" "0"))))]
8097 "TARGET_80387 && !TARGET_64BIT"
8099 [(set_attr "type" "fsgn")
8100 (set_attr "mode" "XF")
8101 (set_attr "ppro_uops" "few")])
8103 (define_insn "*negtf2_1"
8104 [(set (match_operand:TF 0 "register_operand" "=f")
8105 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
8106 "TARGET_80387 && reload_completed"
8108 [(set_attr "type" "fsgn")
8109 (set_attr "mode" "XF")
8110 (set_attr "ppro_uops" "few")])
8112 (define_insn "*negextenddftf2"
8113 [(set (match_operand:TF 0 "register_operand" "=f")
8114 (neg:TF (float_extend:TF
8115 (match_operand:DF 1 "register_operand" "0"))))]
8118 [(set_attr "type" "fsgn")
8119 (set_attr "mode" "XF")
8120 (set_attr "ppro_uops" "few")])
8122 (define_insn "*negextendsftf2"
8123 [(set (match_operand:TF 0 "register_operand" "=f")
8124 (neg:TF (float_extend:TF
8125 (match_operand:SF 1 "register_operand" "0"))))]
8128 [(set_attr "type" "fsgn")
8129 (set_attr "mode" "XF")
8130 (set_attr "ppro_uops" "few")])
8132 ;; Absolute value instructions
8134 (define_expand "abssf2"
8135 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
8136 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
8137 (clobber (reg:CC 17))])]
8141 /* In case operand is in memory, we will not use SSE. */
8142 if (memory_operand (operands[0], VOIDmode)
8143 && rtx_equal_p (operands[0], operands[1]))
8144 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
8147 /* Using SSE is tricky, since we need bitwise negation of -0
8149 rtx reg = gen_reg_rtx (SFmode);
8150 emit_move_insn (reg, gen_lowpart (SFmode, GEN_INT (0x80000000)));
8151 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
8155 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
8157 (define_insn "abssf2_memory"
8158 [(set (match_operand:SF 0 "memory_operand" "=m")
8159 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
8160 (clobber (reg:CC 17))]
8161 "ix86_unary_operator_ok (ABS, SFmode, operands)"
8164 (define_insn "abssf2_ifs"
8165 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,r#xf")
8166 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
8167 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*X#x,*X#x"))
8168 (clobber (reg:CC 17))]
8173 [(set (match_operand:SF 0 "memory_operand" "")
8174 (abs:SF (match_operand:SF 1 "memory_operand" "")))
8175 (use (match_operand:SF 2 "" ""))
8176 (clobber (reg:CC 17))]
8178 [(parallel [(set (match_dup 0)
8179 (abs:SF (match_dup 1)))
8180 (clobber (reg:CC 17))])])
8183 [(set (match_operand:SF 0 "register_operand" "")
8184 (abs:SF (match_operand:SF 1 "register_operand" "")))
8185 (use (match_operand:SF 2 "" ""))
8186 (clobber (reg:CC 17))]
8187 "reload_completed && !SSE_REG_P (operands[0])"
8188 [(parallel [(set (match_dup 0)
8189 (abs:SF (match_dup 1)))
8190 (clobber (reg:CC 17))])])
8193 [(set (match_operand:SF 0 "register_operand" "")
8194 (abs:SF (match_operand:SF 1 "register_operand" "")))
8195 (use (match_operand:SF 2 "register_operand" ""))
8196 (clobber (reg:CC 17))]
8197 "reload_completed && SSE_REG_P (operands[0])"
8198 [(set (subreg:TI (match_dup 0) 0)
8199 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
8200 (subreg:TI (match_dup 1) 0)))])
8202 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
8203 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
8205 (define_insn "*abssf2_if"
8206 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
8207 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
8208 (clobber (reg:CC 17))]
8209 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
8213 [(set (match_operand:SF 0 "register_operand" "")
8214 (abs:SF (match_operand:SF 1 "register_operand" "")))
8215 (clobber (reg:CC 17))]
8216 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
8218 (abs:SF (match_dup 1)))]
8222 [(set (match_operand:SF 0 "register_operand" "")
8223 (abs:SF (match_operand:SF 1 "register_operand" "")))
8224 (clobber (reg:CC 17))]
8225 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
8226 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
8227 (clobber (reg:CC 17))])]
8228 "operands[1] = GEN_INT (~0x80000000);
8229 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
8232 [(set (match_operand 0 "memory_operand" "")
8233 (abs (match_operand 1 "memory_operand" "")))
8234 (clobber (reg:CC 17))]
8235 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
8236 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
8237 (clobber (reg:CC 17))])]
8240 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
8242 /* XFmode's size is 12, but only 10 bytes are used. */
8245 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
8246 operands[0] = adj_offsettable_operand (operands[0], size - 1);
8247 operands[1] = GEN_INT (~0x80);
8250 (define_expand "absdf2"
8251 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
8252 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
8253 (clobber (reg:CC 17))])]
8257 /* In case operand is in memory, we will not use SSE. */
8258 if (memory_operand (operands[0], VOIDmode)
8259 && rtx_equal_p (operands[0], operands[1]))
8260 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
8263 /* Using SSE is tricky, since we need bitwise negation of -0
8265 rtx reg = gen_reg_rtx (DFmode);
8266 #if HOST_BITS_PER_WIDE_INT >= 64
8267 rtx imm = GEN_INT (0x80000000);
8269 rtx imm = immed_double_const (0, 0x80000000, DImode);
8271 emit_move_insn (reg, gen_lowpart (DFmode, imm));
8272 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
8276 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
8278 (define_insn "absdf2_memory"
8279 [(set (match_operand:DF 0 "memory_operand" "=m")
8280 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
8281 (clobber (reg:CC 17))]
8282 "ix86_unary_operator_ok (ABS, DFmode, operands)"
8285 (define_insn "absdf2_ifs"
8286 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,f#Yr,r#Yf")
8287 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
8288 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*X#Y,*X#Y"))
8289 (clobber (reg:CC 17))]
8294 [(set (match_operand:DF 0 "memory_operand" "")
8295 (abs:DF (match_operand:DF 1 "memory_operand" "")))
8296 (use (match_operand:DF 2 "" ""))
8297 (clobber (reg:CC 17))]
8299 [(parallel [(set (match_dup 0)
8300 (abs:DF (match_dup 1)))
8301 (clobber (reg:CC 17))])])
8304 [(set (match_operand:DF 0 "register_operand" "")
8305 (abs:DF (match_operand:DF 1 "register_operand" "")))
8306 (use (match_operand:DF 2 "" ""))
8307 (clobber (reg:CC 17))]
8308 "reload_completed && !SSE_REG_P (operands[0])"
8309 [(parallel [(set (match_dup 0)
8310 (abs:DF (match_dup 1)))
8311 (clobber (reg:CC 17))])])
8314 [(set (match_operand:DF 0 "register_operand" "")
8315 (abs:DF (match_operand:DF 1 "register_operand" "")))
8316 (use (match_operand:DF 2 "register_operand" ""))
8317 (clobber (reg:CC 17))]
8318 "reload_completed && SSE_REG_P (operands[0])"
8319 [(set (subreg:TI (match_dup 0) 0)
8320 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
8321 (subreg:TI (match_dup 1) 0)))])
8324 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
8325 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
8327 (define_insn "*absdf2_if"
8328 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
8329 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
8330 (clobber (reg:CC 17))]
8331 "TARGET_80387 && ix86_unary_operator_ok (ABS, DFmode, operands)"
8335 [(set (match_operand:DF 0 "register_operand" "")
8336 (abs:DF (match_operand:DF 1 "register_operand" "")))
8337 (clobber (reg:CC 17))]
8338 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
8340 (abs:DF (match_dup 1)))]
8344 [(set (match_operand:DF 0 "register_operand" "")
8345 (abs:DF (match_operand:DF 1 "register_operand" "")))
8346 (clobber (reg:CC 17))]
8347 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
8348 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
8349 (clobber (reg:CC 17))])]
8350 "operands[4] = GEN_INT (~0x80000000);
8351 split_di (operands+0, 1, operands+2, operands+3);")
8353 (define_expand "absxf2"
8354 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
8355 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
8356 (clobber (reg:CC 17))])]
8357 "TARGET_80387 && !TARGET_64BIT"
8358 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
8360 (define_expand "abstf2"
8361 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8362 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
8363 (clobber (reg:CC 17))])]
8365 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
8367 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
8368 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
8370 (define_insn "*absxf2_if"
8371 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
8372 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
8373 (clobber (reg:CC 17))]
8374 "TARGET_80387 && !TARGET_64BIT
8375 && ix86_unary_operator_ok (ABS, XFmode, operands)"
8379 [(set (match_operand:XF 0 "register_operand" "")
8380 (abs:XF (match_operand:XF 1 "register_operand" "")))
8381 (clobber (reg:CC 17))]
8382 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
8384 (abs:XF (match_dup 1)))]
8388 [(set (match_operand:XF 0 "register_operand" "")
8389 (abs:XF (match_operand:XF 1 "register_operand" "")))
8390 (clobber (reg:CC 17))]
8391 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
8392 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
8393 (clobber (reg:CC 17))])]
8394 "operands[1] = GEN_INT (~0x8000);
8395 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
8397 (define_insn "*abstf2_if"
8398 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
8399 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
8400 (clobber (reg:CC 17))]
8401 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
8405 [(set (match_operand:TF 0 "register_operand" "")
8406 (abs:TF (match_operand:TF 1 "register_operand" "")))
8407 (clobber (reg:CC 17))]
8408 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
8410 (abs:TF (match_dup 1)))]
8414 [(set (match_operand:TF 0 "register_operand" "")
8415 (abs:TF (match_operand:TF 1 "register_operand" "")))
8416 (clobber (reg:CC 17))]
8417 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
8418 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
8419 (clobber (reg:CC 17))])]
8420 "operands[1] = GEN_INT (~0x8000);
8421 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
8423 (define_insn "*abssf2_1"
8424 [(set (match_operand:SF 0 "register_operand" "=f")
8425 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
8426 "TARGET_80387 && reload_completed"
8428 [(set_attr "type" "fsgn")
8429 (set_attr "mode" "SF")])
8431 (define_insn "*absdf2_1"
8432 [(set (match_operand:DF 0 "register_operand" "=f")
8433 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
8434 "TARGET_80387 && reload_completed"
8436 [(set_attr "type" "fsgn")
8437 (set_attr "mode" "DF")])
8439 (define_insn "*absextendsfdf2"
8440 [(set (match_operand:DF 0 "register_operand" "=f")
8441 (abs:DF (float_extend:DF
8442 (match_operand:SF 1 "register_operand" "0"))))]
8445 [(set_attr "type" "fsgn")
8446 (set_attr "mode" "DF")])
8448 (define_insn "*absxf2_1"
8449 [(set (match_operand:XF 0 "register_operand" "=f")
8450 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
8451 "TARGET_80387 && !TARGET_64BIT && reload_completed"
8453 [(set_attr "type" "fsgn")
8454 (set_attr "mode" "DF")])
8456 (define_insn "*absextenddfxf2"
8457 [(set (match_operand:XF 0 "register_operand" "=f")
8458 (abs:XF (float_extend:XF
8459 (match_operand:DF 1 "register_operand" "0"))))]
8460 "TARGET_80387 && !TARGET_64BIT"
8462 [(set_attr "type" "fsgn")
8463 (set_attr "mode" "XF")])
8465 (define_insn "*absextendsfxf2"
8466 [(set (match_operand:XF 0 "register_operand" "=f")
8467 (abs:XF (float_extend:XF
8468 (match_operand:SF 1 "register_operand" "0"))))]
8469 "TARGET_80387 && !TARGET_64BIT"
8471 [(set_attr "type" "fsgn")
8472 (set_attr "mode" "XF")])
8474 (define_insn "*abstf2_1"
8475 [(set (match_operand:TF 0 "register_operand" "=f")
8476 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
8477 "TARGET_80387 && reload_completed"
8479 [(set_attr "type" "fsgn")
8480 (set_attr "mode" "DF")])
8482 (define_insn "*absextenddftf2"
8483 [(set (match_operand:TF 0 "register_operand" "=f")
8484 (abs:TF (float_extend:TF
8485 (match_operand:DF 1 "register_operand" "0"))))]
8488 [(set_attr "type" "fsgn")
8489 (set_attr "mode" "XF")])
8491 (define_insn "*absextendsftf2"
8492 [(set (match_operand:TF 0 "register_operand" "=f")
8493 (abs:TF (float_extend:TF
8494 (match_operand:SF 1 "register_operand" "0"))))]
8497 [(set_attr "type" "fsgn")
8498 (set_attr "mode" "XF")])
8500 ;; One complement instructions
8502 (define_expand "one_cmplsi2"
8503 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8504 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
8506 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
8508 (define_insn "*one_cmplsi2_1"
8509 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8510 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
8511 "ix86_unary_operator_ok (NOT, SImode, operands)"
8513 [(set_attr "type" "negnot")
8514 (set_attr "mode" "SI")])
8516 (define_insn "*one_cmplsi2_2"
8518 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
8520 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8521 (not:SI (match_dup 1)))]
8522 "ix86_match_ccmode (insn, CCNOmode)
8523 && ix86_unary_operator_ok (NOT, SImode, operands)"
8525 [(set_attr "type" "alu1")
8526 (set_attr "mode" "SI")])
8530 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
8532 (set (match_operand:SI 0 "nonimmediate_operand" "")
8533 (not:SI (match_dup 1)))]
8534 "ix86_match_ccmode (insn, CCNOmode)"
8535 [(parallel [(set (reg:CCNO 17)
8536 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
8539 (xor:SI (match_dup 1) (const_int -1)))])]
8542 (define_expand "one_cmplhi2"
8543 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8544 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
8545 "TARGET_HIMODE_MATH"
8546 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
8548 (define_insn "*one_cmplhi2_1"
8549 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8550 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
8551 "ix86_unary_operator_ok (NOT, HImode, operands)"
8553 [(set_attr "type" "negnot")
8554 (set_attr "mode" "HI")])
8556 (define_insn "*one_cmplhi2_2"
8558 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
8560 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8561 (not:HI (match_dup 1)))]
8562 "ix86_match_ccmode (insn, CCNOmode)
8563 && ix86_unary_operator_ok (NEG, HImode, operands)"
8565 [(set_attr "type" "alu1")
8566 (set_attr "mode" "HI")])
8570 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
8572 (set (match_operand:HI 0 "nonimmediate_operand" "")
8573 (not:HI (match_dup 1)))]
8574 "ix86_match_ccmode (insn, CCNOmode)"
8575 [(parallel [(set (reg:CCNO 17)
8576 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
8579 (xor:HI (match_dup 1) (const_int -1)))])]
8582 ;; %%% Potential partial reg stall on alternative 1. What to do?
8583 (define_expand "one_cmplqi2"
8584 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8585 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
8586 "TARGET_QIMODE_MATH"
8587 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
8589 (define_insn "*one_cmplqi2_1"
8590 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
8591 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
8592 "ix86_unary_operator_ok (NOT, QImode, operands)"
8596 [(set_attr "type" "negnot")
8597 (set_attr "mode" "QI,SI")])
8599 (define_insn "*one_cmplqi2_2"
8601 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
8603 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8604 (not:QI (match_dup 1)))]
8605 "ix86_match_ccmode (insn, CCNOmode)
8606 && ix86_unary_operator_ok (NOT, QImode, operands)"
8608 [(set_attr "type" "alu1")
8609 (set_attr "mode" "QI")])
8613 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
8615 (set (match_operand:QI 0 "nonimmediate_operand" "")
8616 (not:QI (match_dup 1)))]
8617 "ix86_match_ccmode (insn, CCNOmode)"
8618 [(parallel [(set (reg:CCNO 17)
8619 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
8622 (xor:QI (match_dup 1) (const_int -1)))])]
8625 ;; Arithmetic shift instructions
8627 ;; DImode shifts are implemented using the i386 "shift double" opcode,
8628 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
8629 ;; is variable, then the count is in %cl and the "imm" operand is dropped
8630 ;; from the assembler input.
8632 ;; This instruction shifts the target reg/mem as usual, but instead of
8633 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
8634 ;; is a left shift double, bits are taken from the high order bits of
8635 ;; reg, else if the insn is a shift right double, bits are taken from the
8636 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
8637 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
8639 ;; Since sh[lr]d does not change the `reg' operand, that is done
8640 ;; separately, making all shifts emit pairs of shift double and normal
8641 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
8642 ;; support a 63 bit shift, each shift where the count is in a reg expands
8643 ;; to a pair of shifts, a branch, a shift by 32 and a label.
8645 ;; If the shift count is a constant, we need never emit more than one
8646 ;; shift pair, instead using moves and sign extension for counts greater
8649 (define_expand "ashldi3"
8650 [(parallel [(set (match_operand:DI 0 "register_operand" "")
8651 (ashift:DI (match_operand:DI 1 "register_operand" "")
8652 (match_operand:QI 2 "nonmemory_operand" "")))
8653 (clobber (reg:CC 17))])]
8657 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
8659 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
8662 ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;
8665 (define_insn "ashldi3_1"
8666 [(set (match_operand:DI 0 "register_operand" "=r")
8667 (ashift:DI (match_operand:DI 1 "register_operand" "0")
8668 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8669 (clobber (match_scratch:SI 3 "=&r"))
8670 (clobber (reg:CC 17))]
8673 [(set_attr "type" "multi")])
8675 (define_insn "*ashldi3_2"
8676 [(set (match_operand:DI 0 "register_operand" "=r")
8677 (ashift:DI (match_operand:DI 1 "register_operand" "0")
8678 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8679 (clobber (reg:CC 17))]
8682 [(set_attr "type" "multi")])
8685 [(set (match_operand:DI 0 "register_operand" "")
8686 (ashift:DI (match_operand:DI 1 "register_operand" "")
8687 (match_operand:QI 2 "nonmemory_operand" "")))
8688 (clobber (match_scratch:SI 3 ""))
8689 (clobber (reg:CC 17))]
8690 "TARGET_CMOVE && reload_completed"
8692 "ix86_split_ashldi (operands, operands[3]); DONE;")
8695 [(set (match_operand:DI 0 "register_operand" "")
8696 (ashift:DI (match_operand:DI 1 "register_operand" "")
8697 (match_operand:QI 2 "nonmemory_operand" "")))
8698 (clobber (reg:CC 17))]
8701 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
8703 (define_insn "x86_shld_1"
8704 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
8705 (ior:SI (ashift:SI (match_dup 0)
8706 (match_operand:QI 2 "nonmemory_operand" "I,c"))
8707 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
8708 (minus:QI (const_int 32) (match_dup 2)))))
8709 (clobber (reg:CC 17))]
8712 shld{l}\\t{%2, %1, %0|%0, %1, %2}
8713 shld{l}\\t{%s2%1, %0|%0, %1, %2}"
8714 [(set_attr "type" "ishift")
8715 (set_attr "prefix_0f" "1")
8716 (set_attr "mode" "SI")
8717 (set_attr "pent_pair" "np")
8718 (set_attr "athlon_decode" "vector")
8719 (set_attr "ppro_uops" "few")])
8721 (define_expand "x86_shift_adj_1"
8723 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
8726 (set (match_operand:SI 0 "register_operand" "")
8727 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
8728 (match_operand:SI 1 "register_operand" "")
8731 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
8732 (match_operand:SI 3 "register_operand" "r")
8737 (define_expand "x86_shift_adj_2"
8738 [(use (match_operand:SI 0 "register_operand" ""))
8739 (use (match_operand:SI 1 "register_operand" ""))
8740 (use (match_operand:QI 2 "register_operand" ""))]
8744 rtx label = gen_label_rtx ();
8747 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
8749 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
8750 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8751 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
8752 gen_rtx_LABEL_REF (VOIDmode, label),
8754 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
8755 JUMP_LABEL (tmp) = label;
8757 emit_move_insn (operands[0], operands[1]);
8758 emit_move_insn (operands[1], const0_rtx);
8761 LABEL_NUSES (label) = 1;
8766 (define_expand "ashlsi3"
8767 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8768 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
8769 (match_operand:QI 2 "nonmemory_operand" "")))
8770 (clobber (reg:CC 17))]
8772 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
8774 (define_insn "*ashlsi3_1"
8775 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8776 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
8777 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
8778 (clobber (reg:CC 17))]
8779 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
8782 switch (get_attr_type (insn))
8785 if (operands[2] != const1_rtx)
8787 if (!rtx_equal_p (operands[0], operands[1]))
8789 return \"add{l}\\t{%0, %0|%0, %0}\";
8795 if (REG_P (operands[2]))
8796 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
8797 else if (GET_CODE (operands[2]) == CONST_INT
8798 && INTVAL (operands[2]) == 1
8799 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8800 return \"sal{l}\\t%0\";
8802 return \"sal{l}\\t{%2, %0|%0, %2}\";
8806 (cond [(eq_attr "alternative" "1")
8807 (const_string "lea")
8808 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8810 (match_operand 0 "register_operand" ""))
8811 (match_operand 2 "const1_operand" ""))
8812 (const_string "alu")
8814 (const_string "ishift")))
8815 (set_attr "mode" "SI")])
8817 ;; Convert lea to the lea pattern to avoid flags dependency.
8819 [(set (match_operand 0 "register_operand" "")
8820 (ashift (match_operand 1 "register_operand" "")
8821 (match_operand:QI 2 "const_int_operand" "")))
8822 (clobber (reg:CC 17))]
8824 && true_regnum (operands[0]) != true_regnum (operands[1])"
8829 operands[0] = gen_lowpart (SImode, operands[0]);
8830 operands[1] = gen_lowpart (Pmode, operands[1]);
8831 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
8832 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
8833 if (Pmode != SImode)
8834 pat = gen_rtx_SUBREG (SImode, pat, 0);
8835 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
8839 ;; This pattern can't accept a variable shift count, since shifts by
8840 ;; zero don't affect the flags. We assume that shifts by constant
8841 ;; zero are optimized away.
8842 (define_insn "*ashlsi3_cmp"
8845 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8846 (match_operand:QI 2 "immediate_operand" "I"))
8848 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8849 (ashift:SI (match_dup 1) (match_dup 2)))]
8850 "ix86_match_ccmode (insn, CCGOCmode)
8851 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
8854 switch (get_attr_type (insn))
8857 if (operands[2] != const1_rtx)
8859 return \"add{l}\\t{%0, %0|%0, %0}\";
8862 if (REG_P (operands[2]))
8863 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
8864 else if (GET_CODE (operands[2]) == CONST_INT
8865 && INTVAL (operands[2]) == 1
8866 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8867 return \"sal{l}\\t%0\";
8869 return \"sal{l}\\t{%2, %0|%0, %2}\";
8873 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8875 (match_operand 0 "register_operand" ""))
8876 (match_operand 2 "const1_operand" ""))
8877 (const_string "alu")
8879 (const_string "ishift")))
8880 (set_attr "mode" "SI")])
8882 (define_expand "ashlhi3"
8883 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8884 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
8885 (match_operand:QI 2 "nonmemory_operand" "")))
8886 (clobber (reg:CC 17))]
8887 "TARGET_HIMODE_MATH"
8888 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
8890 (define_insn "*ashlhi3_1_lea"
8891 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
8892 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
8893 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
8894 (clobber (reg:CC 17))]
8895 "!TARGET_PARTIAL_REG_STALL
8896 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
8899 switch (get_attr_type (insn))
8904 if (operands[2] != const1_rtx)
8906 return \"add{w}\\t{%0, %0|%0, %0}\";
8909 if (REG_P (operands[2]))
8910 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
8911 else if (GET_CODE (operands[2]) == CONST_INT
8912 && INTVAL (operands[2]) == 1
8913 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8914 return \"sal{w}\\t%0\";
8916 return \"sal{w}\\t{%2, %0|%0, %2}\";
8920 (cond [(eq_attr "alternative" "1")
8921 (const_string "lea")
8922 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8924 (match_operand 0 "register_operand" ""))
8925 (match_operand 2 "const1_operand" ""))
8926 (const_string "alu")
8928 (const_string "ishift")))
8929 (set_attr "mode" "HI,SI")])
8931 (define_insn "*ashlhi3_1"
8932 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8933 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8934 (match_operand:QI 2 "nonmemory_operand" "cI")))
8935 (clobber (reg:CC 17))]
8936 "TARGET_PARTIAL_REG_STALL
8937 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
8940 switch (get_attr_type (insn))
8943 if (operands[2] != const1_rtx)
8945 return \"add{w}\\t{%0, %0|%0, %0}\";
8948 if (REG_P (operands[2]))
8949 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
8950 else if (GET_CODE (operands[2]) == CONST_INT
8951 && INTVAL (operands[2]) == 1
8952 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8953 return \"sal{w}\\t%0\";
8955 return \"sal{w}\\t{%2, %0|%0, %2}\";
8959 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8961 (match_operand 0 "register_operand" ""))
8962 (match_operand 2 "const1_operand" ""))
8963 (const_string "alu")
8965 (const_string "ishift")))
8966 (set_attr "mode" "HI")])
8968 ;; This pattern can't accept a variable shift count, since shifts by
8969 ;; zero don't affect the flags. We assume that shifts by constant
8970 ;; zero are optimized away.
8971 (define_insn "*ashlhi3_cmp"
8974 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8975 (match_operand:QI 2 "immediate_operand" "I"))
8977 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8978 (ashift:HI (match_dup 1) (match_dup 2)))]
8979 "ix86_match_ccmode (insn, CCGOCmode)
8980 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
8983 switch (get_attr_type (insn))
8986 if (operands[2] != const1_rtx)
8988 return \"add{w}\\t{%0, %0|%0, %0}\";
8991 if (REG_P (operands[2]))
8992 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
8993 else if (GET_CODE (operands[2]) == CONST_INT
8994 && INTVAL (operands[2]) == 1
8995 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8996 return \"sal{w}\\t%0\";
8998 return \"sal{w}\\t{%2, %0|%0, %2}\";
9002 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
9004 (match_operand 0 "register_operand" ""))
9005 (match_operand 2 "const1_operand" ""))
9006 (const_string "alu")
9008 (const_string "ishift")))
9009 (set_attr "mode" "HI")])
9011 (define_expand "ashlqi3"
9012 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9013 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
9014 (match_operand:QI 2 "nonmemory_operand" "")))
9015 (clobber (reg:CC 17))]
9016 "TARGET_QIMODE_MATH"
9017 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
9019 ;; %%% Potential partial reg stall on alternative 2. What to do?
9021 (define_insn "*ashlqi3_1_lea"
9022 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
9023 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
9024 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
9025 (clobber (reg:CC 17))]
9026 "!TARGET_PARTIAL_REG_STALL
9027 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
9030 switch (get_attr_type (insn))
9035 if (operands[2] != const1_rtx)
9037 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
9038 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
9040 return \"add{b}\\t{%0, %0|%0, %0}\";
9043 if (REG_P (operands[2]))
9045 if (get_attr_mode (insn) == MODE_SI)
9046 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
9048 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
9050 else if (GET_CODE (operands[2]) == CONST_INT
9051 && INTVAL (operands[2]) == 1
9052 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
9054 if (get_attr_mode (insn) == MODE_SI)
9055 return \"sal{l}\\t%0\";
9057 return \"sal{b}\\t%0\";
9061 if (get_attr_mode (insn) == MODE_SI)
9062 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
9064 return \"sal{b}\\t{%2, %0|%0, %2}\";
9069 (cond [(eq_attr "alternative" "2")
9070 (const_string "lea")
9071 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
9073 (match_operand 0 "register_operand" ""))
9074 (match_operand 2 "const1_operand" ""))
9075 (const_string "alu")
9077 (const_string "ishift")))
9078 (set_attr "mode" "QI,SI,SI")])
9080 (define_insn "*ashlqi3_1"
9081 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
9082 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9083 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
9084 (clobber (reg:CC 17))]
9085 "TARGET_PARTIAL_REG_STALL
9086 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
9089 switch (get_attr_type (insn))
9092 if (operands[2] != const1_rtx)
9094 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
9095 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
9097 return \"add{b}\\t{%0, %0|%0, %0}\";
9100 if (REG_P (operands[2]))
9102 if (get_attr_mode (insn) == MODE_SI)
9103 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
9105 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
9107 else if (GET_CODE (operands[2]) == CONST_INT
9108 && INTVAL (operands[2]) == 1
9109 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
9111 if (get_attr_mode (insn) == MODE_SI)
9112 return \"sal{l}\\t%0\";
9114 return \"sal{b}\\t%0\";
9118 if (get_attr_mode (insn) == MODE_SI)
9119 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
9121 return \"sal{b}\\t{%2, %0|%0, %2}\";
9126 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
9128 (match_operand 0 "register_operand" ""))
9129 (match_operand 2 "const1_operand" ""))
9130 (const_string "alu")
9132 (const_string "ishift")))
9133 (set_attr "mode" "QI,SI")])
9135 ;; This pattern can't accept a variable shift count, since shifts by
9136 ;; zero don't affect the flags. We assume that shifts by constant
9137 ;; zero are optimized away.
9138 (define_insn "*ashlqi3_cmp"
9141 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9142 (match_operand:QI 2 "immediate_operand" "I"))
9144 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9145 (ashift:QI (match_dup 1) (match_dup 2)))]
9146 "ix86_match_ccmode (insn, CCGOCmode)
9147 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
9150 switch (get_attr_type (insn))
9153 if (operands[2] != const1_rtx)
9155 return \"add{b}\\t{%0, %0|%0, %0}\";
9158 if (REG_P (operands[2]))
9159 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
9160 else if (GET_CODE (operands[2]) == CONST_INT
9161 && INTVAL (operands[2]) == 1
9162 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
9163 return \"sal{b}\\t%0\";
9165 return \"sal{b}\\t{%2, %0|%0, %2}\";
9169 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
9171 (match_operand 0 "register_operand" ""))
9172 (match_operand 2 "const1_operand" ""))
9173 (const_string "alu")
9175 (const_string "ishift")))
9176 (set_attr "mode" "QI")])
9178 ;; See comment above `ashldi3' about how this works.
9180 (define_expand "ashrdi3"
9181 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
9182 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
9183 (match_operand:QI 2 "nonmemory_operand" "Jc")))
9184 (clobber (reg:CC 17))])]
9188 if (TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
9190 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
9195 (define_insn "ashrdi3_1"
9196 [(set (match_operand:DI 0 "register_operand" "=r")
9197 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
9198 (match_operand:QI 2 "nonmemory_operand" "Jc")))
9199 (clobber (match_scratch:SI 3 "=&r"))
9200 (clobber (reg:CC 17))]
9203 [(set_attr "type" "multi")])
9205 (define_insn "*ashrdi3_2"
9206 [(set (match_operand:DI 0 "register_operand" "=r")
9207 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
9208 (match_operand:QI 2 "nonmemory_operand" "Jc")))
9209 (clobber (reg:CC 17))]
9212 [(set_attr "type" "multi")])
9215 [(set (match_operand:DI 0 "register_operand" "")
9216 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
9217 (match_operand:QI 2 "nonmemory_operand" "")))
9218 (clobber (match_scratch:SI 3 ""))
9219 (clobber (reg:CC 17))]
9220 "TARGET_CMOVE && reload_completed"
9222 "ix86_split_ashrdi (operands, operands[3]); DONE;")
9225 [(set (match_operand:DI 0 "register_operand" "")
9226 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
9227 (match_operand:QI 2 "nonmemory_operand" "")))
9228 (clobber (reg:CC 17))]
9231 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
9233 (define_insn "x86_shrd_1"
9234 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
9235 (ior:SI (ashiftrt:SI (match_dup 0)
9236 (match_operand:QI 2 "nonmemory_operand" "I,c"))
9237 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
9238 (minus:QI (const_int 32) (match_dup 2)))))
9239 (clobber (reg:CC 17))]
9242 shrd{l}\\t{%2, %1, %0|%0, %1, %2}
9243 shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
9244 [(set_attr "type" "ishift")
9245 (set_attr "prefix_0f" "1")
9246 (set_attr "pent_pair" "np")
9247 (set_attr "ppro_uops" "few")
9248 (set_attr "mode" "SI")])
9250 (define_expand "x86_shift_adj_3"
9251 [(use (match_operand:SI 0 "register_operand" ""))
9252 (use (match_operand:SI 1 "register_operand" ""))
9253 (use (match_operand:QI 2 "register_operand" ""))]
9257 rtx label = gen_label_rtx ();
9260 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
9262 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
9263 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
9264 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9265 gen_rtx_LABEL_REF (VOIDmode, label),
9267 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
9268 JUMP_LABEL (tmp) = label;
9270 emit_move_insn (operands[0], operands[1]);
9271 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
9274 LABEL_NUSES (label) = 1;
9279 (define_insn "ashrsi3_31"
9280 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
9281 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
9282 (match_operand:SI 2 "const_int_operand" "i,i")))
9283 (clobber (reg:CC 17))]
9284 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
9285 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
9288 sar{l}\\t{%2, %0|%0, %2}"
9289 [(set_attr "type" "imovx,ishift")
9290 (set_attr "prefix_0f" "0,*")
9291 (set_attr "length_immediate" "0,*")
9292 (set_attr "modrm" "0,1")
9293 (set_attr "mode" "SI")])
9295 (define_expand "ashrsi3"
9296 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9297 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
9298 (match_operand:QI 2 "nonmemory_operand" "")))
9299 (clobber (reg:CC 17))]
9301 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
9303 (define_insn "*ashrsi3_1_one_bit"
9304 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9305 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9306 (match_operand:QI 2 "const_int_1_operand" "")))
9307 (clobber (reg:CC 17))]
9308 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
9309 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9311 [(set_attr "type" "ishift")
9312 (set (attr "length")
9313 (if_then_else (match_operand:SI 0 "register_operand" "")
9315 (const_string "*")))])
9317 (define_insn "*ashrsi3_1"
9318 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
9319 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
9320 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9321 (clobber (reg:CC 17))]
9322 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
9324 sar{l}\\t{%2, %0|%0, %2}
9325 sar{l}\\t{%b2, %0|%0, %b2}"
9326 [(set_attr "type" "ishift")
9327 (set_attr "mode" "SI")])
9329 ;; This pattern can't accept a variable shift count, since shifts by
9330 ;; zero don't affect the flags. We assume that shifts by constant
9331 ;; zero are optimized away.
9332 (define_insn "*ashrsi3_one_bit_cmp"
9335 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9336 (match_operand:QI 2 "const_int_1_operand" ""))
9338 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9339 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
9340 "ix86_match_ccmode (insn, CCGOCmode)
9341 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
9342 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
9344 [(set_attr "type" "ishift")
9345 (set (attr "length")
9346 (if_then_else (match_operand:SI 0 "register_operand" "")
9348 (const_string "*")))])
9350 ;; This pattern can't accept a variable shift count, since shifts by
9351 ;; zero don't affect the flags. We assume that shifts by constant
9352 ;; zero are optimized away.
9353 (define_insn "*ashrsi3_cmp"
9356 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9357 (match_operand:QI 2 "immediate_operand" "I"))
9359 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9360 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
9361 "ix86_match_ccmode (insn, CCGOCmode)
9362 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
9363 "sar{l}\\t{%2, %0|%0, %2}"
9364 [(set_attr "type" "ishift")
9365 (set_attr "mode" "SI")])
9367 (define_expand "ashrhi3"
9368 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9369 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
9370 (match_operand:QI 2 "nonmemory_operand" "")))
9371 (clobber (reg:CC 17))]
9372 "TARGET_HIMODE_MATH"
9373 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
9375 (define_insn "*ashrhi3_1_one_bit"
9376 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9377 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9378 (match_operand:QI 2 "const_int_1_operand" "")))
9379 (clobber (reg:CC 17))]
9380 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
9381 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9383 [(set_attr "type" "ishift")
9384 (set (attr "length")
9385 (if_then_else (match_operand 0 "register_operand" "")
9387 (const_string "*")))])
9389 (define_insn "*ashrhi3_1"
9390 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
9391 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
9392 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9393 (clobber (reg:CC 17))]
9394 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
9396 sar{w}\\t{%2, %0|%0, %2}
9397 sar{w}\\t{%b2, %0|%0, %b2}"
9398 [(set_attr "type" "ishift")
9399 (set_attr "mode" "HI")])
9401 ;; This pattern can't accept a variable shift count, since shifts by
9402 ;; zero don't affect the flags. We assume that shifts by constant
9403 ;; zero are optimized away.
9404 (define_insn "*ashrhi3_one_bit_cmp"
9407 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9408 (match_operand:QI 2 "const_int_1_operand" ""))
9410 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9411 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
9412 "ix86_match_ccmode (insn, CCGOCmode)
9413 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
9414 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
9416 [(set_attr "type" "ishift")
9417 (set (attr "length")
9418 (if_then_else (match_operand 0 "register_operand" "")
9420 (const_string "*")))])
9422 ;; This pattern can't accept a variable shift count, since shifts by
9423 ;; zero don't affect the flags. We assume that shifts by constant
9424 ;; zero are optimized away.
9425 (define_insn "*ashrhi3_cmp"
9428 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9429 (match_operand:QI 2 "immediate_operand" "I"))
9431 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9432 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
9433 "ix86_match_ccmode (insn, CCGOCmode)
9434 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
9435 "sar{w}\\t{%2, %0|%0, %2}"
9436 [(set_attr "type" "ishift")
9437 (set_attr "mode" "HI")])
9439 (define_expand "ashrqi3"
9440 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9441 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
9442 (match_operand:QI 2 "nonmemory_operand" "")))
9443 (clobber (reg:CC 17))]
9444 "TARGET_QIMODE_MATH"
9445 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
9447 (define_insn "*ashrqi3_1_one_bit"
9448 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9449 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9450 (match_operand:QI 2 "const_int_1_operand" "")))
9451 (clobber (reg:CC 17))]
9452 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
9453 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9455 [(set_attr "type" "ishift")
9456 (set (attr "length")
9457 (if_then_else (match_operand 0 "register_operand" "")
9459 (const_string "*")))])
9461 (define_insn "*ashrqi3_1"
9462 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
9463 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9464 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9465 (clobber (reg:CC 17))]
9466 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
9468 sar{b}\\t{%2, %0|%0, %2}
9469 sar{b}\\t{%b2, %0|%0, %b2}"
9470 [(set_attr "type" "ishift")
9471 (set_attr "mode" "QI")])
9473 ;; This pattern can't accept a variable shift count, since shifts by
9474 ;; zero don't affect the flags. We assume that shifts by constant
9475 ;; zero are optimized away.
9476 (define_insn "*ashrqi3_one_bit_cmp"
9479 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9480 (match_operand:QI 2 "const_int_1_operand" "I"))
9482 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
9483 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
9484 "ix86_match_ccmode (insn, CCGOCmode)
9485 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
9486 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
9488 [(set_attr "type" "ishift")
9489 (set (attr "length")
9490 (if_then_else (match_operand 0 "register_operand" "")
9492 (const_string "*")))])
9494 ;; This pattern can't accept a variable shift count, since shifts by
9495 ;; zero don't affect the flags. We assume that shifts by constant
9496 ;; zero are optimized away.
9497 (define_insn "*ashrqi3_cmp"
9500 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9501 (match_operand:QI 2 "immediate_operand" "I"))
9503 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
9504 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
9505 "ix86_match_ccmode (insn, CCGOCmode)
9506 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
9507 "sar{b}\\t{%2, %0|%0, %2}"
9508 [(set_attr "type" "ishift")
9509 (set_attr "mode" "QI")])
9511 ;; Logical shift instructions
9513 ;; See comment above `ashldi3' about how this works.
9515 (define_expand "lshrdi3"
9516 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
9517 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
9518 (match_operand:QI 2 "nonmemory_operand" "Jc")))
9519 (clobber (reg:CC 17))])]
9523 if (TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
9525 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
9530 (define_insn "lshrdi3_1"
9531 [(set (match_operand:DI 0 "register_operand" "=r")
9532 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
9533 (match_operand:QI 2 "nonmemory_operand" "Jc")))
9534 (clobber (match_scratch:SI 3 "=&r"))
9535 (clobber (reg:CC 17))]
9536 "!TARGET_64BIT && TARGET_CMOVE"
9538 [(set_attr "type" "multi")])
9540 (define_insn "*lshrdi3_2"
9541 [(set (match_operand:DI 0 "register_operand" "=r")
9542 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
9543 (match_operand:QI 2 "nonmemory_operand" "Jc")))
9544 (clobber (reg:CC 17))]
9547 [(set_attr "type" "multi")])
9550 [(set (match_operand:DI 0 "register_operand" "")
9551 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
9552 (match_operand:QI 2 "nonmemory_operand" "")))
9553 (clobber (match_scratch:SI 3 ""))
9554 (clobber (reg:CC 17))]
9555 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
9557 "ix86_split_lshrdi (operands, operands[3]); DONE;")
9560 [(set (match_operand:DI 0 "register_operand" "")
9561 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
9562 (match_operand:QI 2 "nonmemory_operand" "")))
9563 (clobber (reg:CC 17))]
9564 "!TARGET_64BIT && reload_completed"
9566 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
9568 (define_expand "lshrsi3"
9569 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9570 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
9571 (match_operand:QI 2 "nonmemory_operand" "")))
9572 (clobber (reg:CC 17))]
9574 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
9576 (define_insn "*lshrsi3_1_one_bit"
9577 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9578 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9579 (match_operand:QI 2 "const_int_1_operand" "")))
9580 (clobber (reg:CC 17))]
9581 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
9582 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9584 [(set_attr "type" "ishift")
9585 (set (attr "length")
9586 (if_then_else (match_operand:SI 0 "register_operand" "")
9588 (const_string "*")))])
9590 (define_insn "*lshrsi3_1"
9591 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
9592 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
9593 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9594 (clobber (reg:CC 17))]
9595 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
9597 shr{l}\\t{%2, %0|%0, %2}
9598 shr{l}\\t{%b2, %0|%0, %b2}"
9599 [(set_attr "type" "ishift")
9600 (set_attr "mode" "SI")])
9602 ;; This pattern can't accept a variable shift count, since shifts by
9603 ;; zero don't affect the flags. We assume that shifts by constant
9604 ;; zero are optimized away.
9605 (define_insn "*lshrsi3_one_bit_cmp"
9608 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9609 (match_operand:QI 2 "const_int_1_operand" ""))
9611 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9612 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
9613 "ix86_match_ccmode (insn, CCGOCmode)
9614 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
9615 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
9617 [(set_attr "type" "ishift")
9618 (set (attr "length")
9619 (if_then_else (match_operand:SI 0 "register_operand" "")
9621 (const_string "*")))])
9623 ;; This pattern can't accept a variable shift count, since shifts by
9624 ;; zero don't affect the flags. We assume that shifts by constant
9625 ;; zero are optimized away.
9626 (define_insn "*lshrsi3_cmp"
9629 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9630 (match_operand:QI 2 "immediate_operand" "I"))
9632 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9633 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
9634 "ix86_match_ccmode (insn, CCGOCmode)
9635 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
9636 "shr{l}\\t{%2, %0|%0, %2}"
9637 [(set_attr "type" "ishift")
9638 (set_attr "mode" "SI")])
9640 (define_expand "lshrhi3"
9641 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9642 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
9643 (match_operand:QI 2 "nonmemory_operand" "")))
9644 (clobber (reg:CC 17))]
9645 "TARGET_HIMODE_MATH"
9646 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
9648 (define_insn "*lshrhi3_1_one_bit"
9649 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9650 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9651 (match_operand:QI 2 "const_int_1_operand" "")))
9652 (clobber (reg:CC 17))]
9653 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
9654 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9656 [(set_attr "type" "ishift")
9657 (set (attr "length")
9658 (if_then_else (match_operand 0 "register_operand" "")
9660 (const_string "*")))])
9662 (define_insn "*lshrhi3_1"
9663 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
9664 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
9665 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9666 (clobber (reg:CC 17))]
9667 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
9669 shr{w}\\t{%2, %0|%0, %2}
9670 shr{w}\\t{%b2, %0|%0, %b2}"
9671 [(set_attr "type" "ishift")
9672 (set_attr "mode" "HI")])
9674 ;; This pattern can't accept a variable shift count, since shifts by
9675 ;; zero don't affect the flags. We assume that shifts by constant
9676 ;; zero are optimized away.
9677 (define_insn "*lshrhi3_one_bit_cmp"
9680 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9681 (match_operand:QI 2 "const_int_1_operand" ""))
9683 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9684 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
9685 "ix86_match_ccmode (insn, CCGOCmode)
9686 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
9687 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
9689 [(set_attr "type" "ishift")
9690 (set (attr "length")
9691 (if_then_else (match_operand:SI 0 "register_operand" "")
9693 (const_string "*")))])
9695 ;; This pattern can't accept a variable shift count, since shifts by
9696 ;; zero don't affect the flags. We assume that shifts by constant
9697 ;; zero are optimized away.
9698 (define_insn "*lshrhi3_cmp"
9701 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9702 (match_operand:QI 2 "immediate_operand" "I"))
9704 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9705 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
9706 "ix86_match_ccmode (insn, CCGOCmode)
9707 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
9708 "shr{w}\\t{%2, %0|%0, %2}"
9709 [(set_attr "type" "ishift")
9710 (set_attr "mode" "HI")])
9712 (define_expand "lshrqi3"
9713 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9714 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
9715 (match_operand:QI 2 "nonmemory_operand" "")))
9716 (clobber (reg:CC 17))]
9717 "TARGET_QIMODE_MATH"
9718 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
9720 (define_insn "*lshrqi3_1_one_bit"
9721 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9722 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9723 (match_operand:QI 2 "const_int_1_operand" "")))
9724 (clobber (reg:CC 17))]
9725 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
9726 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9728 [(set_attr "type" "ishift")
9729 (set (attr "length")
9730 (if_then_else (match_operand 0 "register_operand" "")
9732 (const_string "*")))])
9734 (define_insn "*lshrqi3_1"
9735 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
9736 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9737 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9738 (clobber (reg:CC 17))]
9739 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
9741 shr{b}\\t{%2, %0|%0, %2}
9742 shr{b}\\t{%b2, %0|%0, %b2}"
9743 [(set_attr "type" "ishift")
9744 (set_attr "mode" "QI")])
9746 ;; This pattern can't accept a variable shift count, since shifts by
9747 ;; zero don't affect the flags. We assume that shifts by constant
9748 ;; zero are optimized away.
9749 (define_insn "*lshrqi2_one_bit_cmp"
9752 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9753 (match_operand:QI 2 "const_int_1_operand" ""))
9755 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9756 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
9757 "ix86_match_ccmode (insn, CCGOCmode)
9758 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
9759 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
9761 [(set_attr "type" "ishift")
9762 (set (attr "length")
9763 (if_then_else (match_operand:SI 0 "register_operand" "")
9765 (const_string "*")))])
9767 ;; This pattern can't accept a variable shift count, since shifts by
9768 ;; zero don't affect the flags. We assume that shifts by constant
9769 ;; zero are optimized away.
9770 (define_insn "*lshrqi2_cmp"
9773 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9774 (match_operand:QI 2 "immediate_operand" "I"))
9776 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9777 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
9778 "ix86_match_ccmode (insn, CCGOCmode)
9779 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
9780 "shr{b}\\t{%2, %0|%0, %2}"
9781 [(set_attr "type" "ishift")
9782 (set_attr "mode" "QI")])
9784 ;; Rotate instructions
9786 (define_expand "rotlsi3"
9787 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9788 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
9789 (match_operand:QI 2 "nonmemory_operand" "")))
9790 (clobber (reg:CC 17))]
9792 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
9794 (define_insn "*rotlsi3_1_one_bit"
9795 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9796 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9797 (match_operand:QI 2 "const_int_1_operand" "")))
9798 (clobber (reg:CC 17))]
9799 "ix86_binary_operator_ok (ROTATE, SImode, operands)
9800 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9802 [(set_attr "type" "ishift")
9803 (set (attr "length")
9804 (if_then_else (match_operand:SI 0 "register_operand" "")
9806 (const_string "*")))])
9808 (define_insn "*rotlsi3_1"
9809 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
9810 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
9811 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9812 (clobber (reg:CC 17))]
9813 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
9815 rol{l}\\t{%2, %0|%0, %2}
9816 rol{l}\\t{%b2, %0|%0, %b2}"
9817 [(set_attr "type" "ishift")
9818 (set_attr "mode" "SI")])
9820 (define_expand "rotlhi3"
9821 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9822 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
9823 (match_operand:QI 2 "nonmemory_operand" "")))
9824 (clobber (reg:CC 17))]
9825 "TARGET_HIMODE_MATH"
9826 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
9828 (define_insn "*rotlhi3_1_one_bit"
9829 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9830 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9831 (match_operand:QI 2 "const_int_1_operand" "")))
9832 (clobber (reg:CC 17))]
9833 "ix86_binary_operator_ok (ROTATE, HImode, operands)
9834 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9836 [(set_attr "type" "ishift")
9837 (set (attr "length")
9838 (if_then_else (match_operand 0 "register_operand" "")
9840 (const_string "*")))])
9842 (define_insn "*rotlhi3_1"
9843 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
9844 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
9845 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9846 (clobber (reg:CC 17))]
9847 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
9849 rol{w}\\t{%2, %0|%0, %2}
9850 rol{w}\\t{%b2, %0|%0, %b2}"
9851 [(set_attr "type" "ishift")
9852 (set_attr "mode" "HI")])
9854 (define_expand "rotlqi3"
9855 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9856 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
9857 (match_operand:QI 2 "nonmemory_operand" "")))
9858 (clobber (reg:CC 17))]
9859 "TARGET_QIMODE_MATH"
9860 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
9862 (define_insn "*rotlqi3_1_one_bit"
9863 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9864 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9865 (match_operand:QI 2 "const_int_1_operand" "")))
9866 (clobber (reg:CC 17))]
9867 "ix86_binary_operator_ok (ROTATE, QImode, operands)
9868 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9870 [(set_attr "type" "ishift")
9871 (set (attr "length")
9872 (if_then_else (match_operand 0 "register_operand" "")
9874 (const_string "*")))])
9876 (define_insn "*rotlqi3_1"
9877 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
9878 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9879 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9880 (clobber (reg:CC 17))]
9881 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
9883 rol{b}\\t{%2, %0|%0, %2}
9884 rol{b}\\t{%b2, %0|%0, %b2}"
9885 [(set_attr "type" "ishift")
9886 (set_attr "mode" "QI")])
9888 (define_expand "rotrsi3"
9889 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9890 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
9891 (match_operand:QI 2 "nonmemory_operand" "")))
9892 (clobber (reg:CC 17))]
9894 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
9896 (define_insn "*rotrsi3_1_one_bit"
9897 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9898 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9899 (match_operand:QI 2 "const_int_1_operand" "")))
9900 (clobber (reg:CC 17))]
9901 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
9902 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9904 [(set_attr "type" "ishift")
9905 (set (attr "length")
9906 (if_then_else (match_operand:SI 0 "register_operand" "")
9908 (const_string "*")))])
9910 (define_insn "*rotrsi3_1"
9911 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
9912 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
9913 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9914 (clobber (reg:CC 17))]
9915 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
9917 ror{l}\\t{%2, %0|%0, %2}
9918 ror{l}\\t{%b2, %0|%0, %b2}"
9919 [(set_attr "type" "ishift")
9920 (set_attr "mode" "SI")])
9922 (define_expand "rotrhi3"
9923 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9924 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
9925 (match_operand:QI 2 "nonmemory_operand" "")))
9926 (clobber (reg:CC 17))]
9927 "TARGET_HIMODE_MATH"
9928 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
9930 (define_insn "*rotrhi3_one_bit"
9931 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9932 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9933 (match_operand:QI 2 "const_int_1_operand" "")))
9934 (clobber (reg:CC 17))]
9935 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
9936 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9938 [(set_attr "type" "ishift")
9939 (set (attr "length")
9940 (if_then_else (match_operand 0 "register_operand" "")
9942 (const_string "*")))])
9944 (define_insn "*rotrhi3"
9945 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
9946 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
9947 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9948 (clobber (reg:CC 17))]
9949 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
9951 ror{w}\\t{%2, %0|%0, %2}
9952 ror{w}\\t{%b2, %0|%0, %b2}"
9953 [(set_attr "type" "ishift")
9954 (set_attr "mode" "HI")])
9956 (define_expand "rotrqi3"
9957 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9958 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
9959 (match_operand:QI 2 "nonmemory_operand" "")))
9960 (clobber (reg:CC 17))]
9961 "TARGET_QIMODE_MATH"
9962 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
9964 (define_insn "*rotrqi3_1_one_bit"
9965 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9966 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9967 (match_operand:QI 2 "const_int_1_operand" "")))
9968 (clobber (reg:CC 17))]
9969 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
9970 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9972 [(set_attr "type" "ishift")
9973 (set (attr "length")
9974 (if_then_else (match_operand 0 "register_operand" "")
9976 (const_string "*")))])
9978 (define_insn "*rotrqi3_1"
9979 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
9980 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9981 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9982 (clobber (reg:CC 17))]
9983 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
9985 ror{b}\\t{%2, %0|%0, %2}
9986 ror{b}\\t{%b2, %0|%0, %b2}"
9987 [(set_attr "type" "ishift")
9988 (set_attr "mode" "QI")])
9990 ;; Bit set / bit test instructions
9992 (define_expand "extv"
9993 [(set (match_operand:SI 0 "register_operand" "")
9994 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
9995 (match_operand:SI 2 "immediate_operand" "")
9996 (match_operand:SI 3 "immediate_operand" "")))]
10000 /* Handle extractions from %ah et al. */
10001 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
10004 /* From mips.md: extract_bit_field doesn't verify that our source
10005 matches the predicate, so check it again here. */
10006 if (! register_operand (operands[1], VOIDmode))
10010 (define_expand "extzv"
10011 [(set (match_operand:SI 0 "register_operand" "")
10012 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
10013 (match_operand:SI 2 "immediate_operand" "")
10014 (match_operand:SI 3 "immediate_operand" "")))]
10018 /* Handle extractions from %ah et al. */
10019 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
10022 /* From mips.md: extract_bit_field doesn't verify that our source
10023 matches the predicate, so check it again here. */
10024 if (! register_operand (operands[1], VOIDmode))
10028 (define_expand "insv"
10029 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
10030 (match_operand:SI 1 "immediate_operand" "")
10031 (match_operand:SI 2 "immediate_operand" ""))
10032 (match_operand:SI 3 "register_operand" ""))]
10036 /* Handle extractions from %ah et al. */
10037 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
10040 /* From mips.md: insert_bit_field doesn't verify that our source
10041 matches the predicate, so check it again here. */
10042 if (! register_operand (operands[0], VOIDmode))
10046 ;; %%% bts, btr, btc, bt.
10048 ;; Store-flag instructions.
10050 ;; For all sCOND expanders, also expand the compare or test insn that
10051 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
10053 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
10054 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
10055 ;; way, which can later delete the movzx if only QImode is needed.
10057 (define_expand "seq"
10058 [(set (match_operand:SI 0 "register_operand" "")
10059 (eq:SI (reg:CC 17) (const_int 0)))]
10061 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
10063 (define_expand "sne"
10064 [(set (match_operand:SI 0 "register_operand" "")
10065 (ne:SI (reg:CC 17) (const_int 0)))]
10067 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
10069 (define_expand "sgt"
10070 [(set (match_operand:SI 0 "register_operand" "")
10071 (gt:SI (reg:CC 17) (const_int 0)))]
10073 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
10075 (define_expand "sgtu"
10076 [(set (match_operand:SI 0 "register_operand" "")
10077 (gtu:SI (reg:CC 17) (const_int 0)))]
10079 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
10081 (define_expand "slt"
10082 [(set (match_operand:SI 0 "register_operand" "")
10083 (lt:SI (reg:CC 17) (const_int 0)))]
10085 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
10087 (define_expand "sltu"
10088 [(set (match_operand:SI 0 "register_operand" "")
10089 (ltu:SI (reg:CC 17) (const_int 0)))]
10091 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
10093 (define_expand "sge"
10094 [(set (match_operand:SI 0 "register_operand" "")
10095 (ge:SI (reg:CC 17) (const_int 0)))]
10097 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
10099 (define_expand "sgeu"
10100 [(set (match_operand:SI 0 "register_operand" "")
10101 (geu:SI (reg:CC 17) (const_int 0)))]
10103 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
10105 (define_expand "sle"
10106 [(set (match_operand:SI 0 "register_operand" "")
10107 (le:SI (reg:CC 17) (const_int 0)))]
10109 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
10111 (define_expand "sleu"
10112 [(set (match_operand:SI 0 "register_operand" "")
10113 (leu:SI (reg:CC 17) (const_int 0)))]
10115 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
10117 (define_expand "sunordered"
10118 [(set (match_operand:SI 0 "register_operand" "")
10119 (unordered:SI (reg:CC 17) (const_int 0)))]
10120 "TARGET_80387 || TARGET_SSE"
10121 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
10123 (define_expand "sordered"
10124 [(set (match_operand:SI 0 "register_operand" "")
10125 (ordered:SI (reg:CC 17) (const_int 0)))]
10127 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
10129 (define_expand "suneq"
10130 [(set (match_operand:SI 0 "register_operand" "")
10131 (uneq:SI (reg:CC 17) (const_int 0)))]
10132 "TARGET_80387 || TARGET_SSE"
10133 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
10135 (define_expand "sunge"
10136 [(set (match_operand:SI 0 "register_operand" "")
10137 (unge:SI (reg:CC 17) (const_int 0)))]
10138 "TARGET_80387 || TARGET_SSE"
10139 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
10141 (define_expand "sungt"
10142 [(set (match_operand:SI 0 "register_operand" "")
10143 (ungt:SI (reg:CC 17) (const_int 0)))]
10144 "TARGET_80387 || TARGET_SSE"
10145 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
10147 (define_expand "sunle"
10148 [(set (match_operand:SI 0 "register_operand" "")
10149 (unle:SI (reg:CC 17) (const_int 0)))]
10150 "TARGET_80387 || TARGET_SSE"
10151 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
10153 (define_expand "sunlt"
10154 [(set (match_operand:SI 0 "register_operand" "")
10155 (unlt:SI (reg:CC 17) (const_int 0)))]
10156 "TARGET_80387 || TARGET_SSE"
10157 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
10159 (define_expand "sltgt"
10160 [(set (match_operand:SI 0 "register_operand" "")
10161 (ltgt:SI (reg:CC 17) (const_int 0)))]
10162 "TARGET_80387 || TARGET_SSE"
10163 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
10165 (define_insn "*setcc_1"
10166 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10167 (match_operator:QI 1 "ix86_comparison_operator"
10168 [(reg 17) (const_int 0)]))]
10171 [(set_attr "type" "setcc")
10172 (set_attr "mode" "QI")])
10174 (define_insn "setcc_2"
10175 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
10176 (match_operator:QI 1 "ix86_comparison_operator"
10177 [(reg 17) (const_int 0)]))]
10180 [(set_attr "type" "setcc")
10181 (set_attr "mode" "QI")])
10183 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
10184 ;; subsequent logical operations are used to imitate conditional moves.
10185 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
10186 ;; it directly. Futher holding this value in pseudo register might bring
10187 ;; problem in implicit normalization in spill code.
10188 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
10189 ;; instructions after reload by splitting the conditional move patterns.
10191 (define_insn "*sse_setccsf"
10192 [(set (match_operand:SF 0 "register_operand" "=x")
10193 (match_operator:SF 1 "sse_comparison_operator"
10194 [(match_operand:SF 2 "register_operand" "0")
10195 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
10196 "TARGET_SSE && reload_completed"
10197 "cmp%D1ss\\t{%3, %0|%0, %3}"
10198 [(set_attr "type" "sse")
10199 (set_attr "mode" "SF")])
10201 (define_insn "*sse_setccdf"
10202 [(set (match_operand:DF 0 "register_operand" "=Y")
10203 (match_operator:DF 1 "sse_comparison_operator"
10204 [(match_operand:DF 2 "register_operand" "0")
10205 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
10206 "TARGET_SSE2 && reload_completed"
10207 "cmp%D1sd\\t{%3, %0|%0, %3}"
10208 [(set_attr "type" "sse")
10209 (set_attr "mode" "DF")])
10211 ;; Basic conditional jump instructions.
10212 ;; We ignore the overflow flag for signed branch instructions.
10214 ;; For all bCOND expanders, also expand the compare or test insn that
10215 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
10217 (define_expand "beq"
10219 (if_then_else (match_dup 1)
10220 (label_ref (match_operand 0 "" ""))
10223 "ix86_expand_branch (EQ, operands[0]); DONE;")
10225 (define_expand "bne"
10227 (if_then_else (match_dup 1)
10228 (label_ref (match_operand 0 "" ""))
10231 "ix86_expand_branch (NE, operands[0]); DONE;")
10233 (define_expand "bgt"
10235 (if_then_else (match_dup 1)
10236 (label_ref (match_operand 0 "" ""))
10239 "ix86_expand_branch (GT, operands[0]); DONE;")
10241 (define_expand "bgtu"
10243 (if_then_else (match_dup 1)
10244 (label_ref (match_operand 0 "" ""))
10247 "ix86_expand_branch (GTU, operands[0]); DONE;")
10249 (define_expand "blt"
10251 (if_then_else (match_dup 1)
10252 (label_ref (match_operand 0 "" ""))
10255 "ix86_expand_branch (LT, operands[0]); DONE;")
10257 (define_expand "bltu"
10259 (if_then_else (match_dup 1)
10260 (label_ref (match_operand 0 "" ""))
10263 "ix86_expand_branch (LTU, operands[0]); DONE;")
10265 (define_expand "bge"
10267 (if_then_else (match_dup 1)
10268 (label_ref (match_operand 0 "" ""))
10271 "ix86_expand_branch (GE, operands[0]); DONE;")
10273 (define_expand "bgeu"
10275 (if_then_else (match_dup 1)
10276 (label_ref (match_operand 0 "" ""))
10279 "ix86_expand_branch (GEU, operands[0]); DONE;")
10281 (define_expand "ble"
10283 (if_then_else (match_dup 1)
10284 (label_ref (match_operand 0 "" ""))
10287 "ix86_expand_branch (LE, operands[0]); DONE;")
10289 (define_expand "bleu"
10291 (if_then_else (match_dup 1)
10292 (label_ref (match_operand 0 "" ""))
10295 "ix86_expand_branch (LEU, operands[0]); DONE;")
10297 (define_expand "bunordered"
10299 (if_then_else (match_dup 1)
10300 (label_ref (match_operand 0 "" ""))
10302 "TARGET_80387 || TARGET_SSE"
10303 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
10305 (define_expand "bordered"
10307 (if_then_else (match_dup 1)
10308 (label_ref (match_operand 0 "" ""))
10310 "TARGET_80387 || TARGET_SSE"
10311 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
10313 (define_expand "buneq"
10315 (if_then_else (match_dup 1)
10316 (label_ref (match_operand 0 "" ""))
10318 "TARGET_80387 || TARGET_SSE"
10319 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
10321 (define_expand "bunge"
10323 (if_then_else (match_dup 1)
10324 (label_ref (match_operand 0 "" ""))
10326 "TARGET_80387 || TARGET_SSE"
10327 "ix86_expand_branch (UNGE, operands[0]); DONE;")
10329 (define_expand "bungt"
10331 (if_then_else (match_dup 1)
10332 (label_ref (match_operand 0 "" ""))
10334 "TARGET_80387 || TARGET_SSE"
10335 "ix86_expand_branch (UNGT, operands[0]); DONE;")
10337 (define_expand "bunle"
10339 (if_then_else (match_dup 1)
10340 (label_ref (match_operand 0 "" ""))
10342 "TARGET_80387 || TARGET_SSE"
10343 "ix86_expand_branch (UNLE, operands[0]); DONE;")
10345 (define_expand "bunlt"
10347 (if_then_else (match_dup 1)
10348 (label_ref (match_operand 0 "" ""))
10350 "TARGET_80387 || TARGET_SSE"
10351 "ix86_expand_branch (UNLT, operands[0]); DONE;")
10353 (define_expand "bltgt"
10355 (if_then_else (match_dup 1)
10356 (label_ref (match_operand 0 "" ""))
10358 "TARGET_80387 || TARGET_SSE"
10359 "ix86_expand_branch (LTGT, operands[0]); DONE;")
10361 (define_insn "*jcc_1"
10363 (if_then_else (match_operator 1 "ix86_comparison_operator"
10364 [(reg 17) (const_int 0)])
10365 (label_ref (match_operand 0 "" ""))
10369 [(set_attr "type" "ibr")
10370 (set (attr "prefix_0f")
10371 (if_then_else (and (ge (minus (match_dup 0) (pc))
10373 (lt (minus (match_dup 0) (pc))
10378 (define_insn "*jcc_2"
10380 (if_then_else (match_operator 1 "ix86_comparison_operator"
10381 [(reg 17) (const_int 0)])
10383 (label_ref (match_operand 0 "" ""))))]
10386 [(set_attr "type" "ibr")
10387 (set (attr "prefix_0f")
10388 (if_then_else (and (ge (minus (match_dup 0) (pc))
10390 (lt (minus (match_dup 0) (pc))
10395 ;; Define combination compare-and-branch fp compare instructions to use
10396 ;; during early optimization. Splitting the operation apart early makes
10397 ;; for bad code when we want to reverse the operation.
10399 (define_insn "*fp_jcc_1"
10401 (if_then_else (match_operator 0 "comparison_operator"
10402 [(match_operand 1 "register_operand" "f")
10403 (match_operand 2 "register_operand" "f")])
10404 (label_ref (match_operand 3 "" ""))
10406 (clobber (reg:CCFP 18))
10407 (clobber (reg:CCFP 17))]
10408 "TARGET_CMOVE && TARGET_80387
10409 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
10410 && FLOAT_MODE_P (GET_MODE (operands[1]))
10411 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10414 (define_insn "*fp_jcc_1_sse"
10416 (if_then_else (match_operator 0 "comparison_operator"
10417 [(match_operand 1 "register_operand" "f#x,x#f")
10418 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
10419 (label_ref (match_operand 3 "" ""))
10421 (clobber (reg:CCFP 18))
10422 (clobber (reg:CCFP 17))]
10424 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
10425 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10428 (define_insn "*fp_jcc_1_sse_only"
10430 (if_then_else (match_operator 0 "comparison_operator"
10431 [(match_operand 1 "register_operand" "x")
10432 (match_operand 2 "nonimmediate_operand" "xm")])
10433 (label_ref (match_operand 3 "" ""))
10435 (clobber (reg:CCFP 18))
10436 (clobber (reg:CCFP 17))]
10437 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
10438 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10441 (define_insn "*fp_jcc_2"
10443 (if_then_else (match_operator 0 "comparison_operator"
10444 [(match_operand 1 "register_operand" "f")
10445 (match_operand 2 "register_operand" "f")])
10447 (label_ref (match_operand 3 "" ""))))
10448 (clobber (reg:CCFP 18))
10449 (clobber (reg:CCFP 17))]
10450 "TARGET_CMOVE && TARGET_80387
10451 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
10452 && FLOAT_MODE_P (GET_MODE (operands[1]))
10453 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10456 (define_insn "*fp_jcc_2_sse"
10458 (if_then_else (match_operator 0 "comparison_operator"
10459 [(match_operand 1 "register_operand" "f#x,x#f")
10460 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
10462 (label_ref (match_operand 3 "" ""))))
10463 (clobber (reg:CCFP 18))
10464 (clobber (reg:CCFP 17))]
10466 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
10467 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10470 (define_insn "*fp_jcc_2_sse_only"
10472 (if_then_else (match_operator 0 "comparison_operator"
10473 [(match_operand 1 "register_operand" "x")
10474 (match_operand 2 "nonimmediate_operand" "xm")])
10476 (label_ref (match_operand 3 "" ""))))
10477 (clobber (reg:CCFP 18))
10478 (clobber (reg:CCFP 17))]
10479 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
10480 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10483 (define_insn "*fp_jcc_3"
10485 (if_then_else (match_operator 0 "comparison_operator"
10486 [(match_operand 1 "register_operand" "f")
10487 (match_operand 2 "nonimmediate_operand" "fm")])
10488 (label_ref (match_operand 3 "" ""))
10490 (clobber (reg:CCFP 18))
10491 (clobber (reg:CCFP 17))
10492 (clobber (match_scratch:HI 4 "=a"))]
10494 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
10495 && GET_MODE (operands[1]) == GET_MODE (operands[2])
10496 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
10497 && SELECT_CC_MODE (GET_CODE (operands[0]),
10498 operands[1], operands[2]) == CCFPmode"
10501 (define_insn "*fp_jcc_4"
10503 (if_then_else (match_operator 0 "comparison_operator"
10504 [(match_operand 1 "register_operand" "f")
10505 (match_operand 2 "nonimmediate_operand" "fm")])
10507 (label_ref (match_operand 3 "" ""))))
10508 (clobber (reg:CCFP 18))
10509 (clobber (reg:CCFP 17))
10510 (clobber (match_scratch:HI 4 "=a"))]
10512 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
10513 && GET_MODE (operands[1]) == GET_MODE (operands[2])
10514 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
10515 && SELECT_CC_MODE (GET_CODE (operands[0]),
10516 operands[1], operands[2]) == CCFPmode"
10519 (define_insn "*fp_jcc_5"
10521 (if_then_else (match_operator 0 "comparison_operator"
10522 [(match_operand 1 "register_operand" "f")
10523 (match_operand 2 "register_operand" "f")])
10524 (label_ref (match_operand 3 "" ""))
10526 (clobber (reg:CCFP 18))
10527 (clobber (reg:CCFP 17))
10528 (clobber (match_scratch:HI 4 "=a"))]
10530 && FLOAT_MODE_P (GET_MODE (operands[1]))
10531 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10534 (define_insn "*fp_jcc_6"
10536 (if_then_else (match_operator 0 "comparison_operator"
10537 [(match_operand 1 "register_operand" "f")
10538 (match_operand 2 "register_operand" "f")])
10540 (label_ref (match_operand 3 "" ""))))
10541 (clobber (reg:CCFP 18))
10542 (clobber (reg:CCFP 17))
10543 (clobber (match_scratch:HI 4 "=a"))]
10545 && FLOAT_MODE_P (GET_MODE (operands[1]))
10546 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
10551 (if_then_else (match_operator 0 "comparison_operator"
10552 [(match_operand 1 "register_operand" "")
10553 (match_operand 2 "nonimmediate_operand" "")])
10554 (match_operand 3 "" "")
10555 (match_operand 4 "" "")))
10556 (clobber (reg:CCFP 18))
10557 (clobber (reg:CCFP 17))]
10562 ix86_split_fp_branch (operands[0], operands[1], operands[2],
10563 operands[3], operands[4], NULL_RTX);
10569 (if_then_else (match_operator 0 "comparison_operator"
10570 [(match_operand 1 "register_operand" "")
10571 (match_operand 2 "nonimmediate_operand" "")])
10572 (match_operand 3 "" "")
10573 (match_operand 4 "" "")))
10574 (clobber (reg:CCFP 18))
10575 (clobber (reg:CCFP 17))
10576 (clobber (match_scratch:HI 5 "=a"))]
10579 (if_then_else (match_dup 6)
10584 ix86_split_fp_branch (operands[0], operands[1], operands[2],
10585 operands[3], operands[4], operands[5]);
10589 ;; Unconditional and other jump instructions
10591 (define_insn "jump"
10593 (label_ref (match_operand 0 "" "")))]
10596 [(set_attr "type" "ibr")])
10598 (define_insn "indirect_jump"
10599 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
10602 [(set_attr "type" "ibr")
10603 (set_attr "length_immediate" "0")])
10605 (define_insn "tablejump"
10606 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
10607 (use (label_ref (match_operand 1 "" "")))]
10610 [(set_attr "type" "ibr")
10611 (set_attr "length_immediate" "0")])
10613 ;; Implement switch statements when generating PIC code. Switches are
10614 ;; implemented by `tablejump' when not using -fpic.
10616 ;; Emit code here to do the range checking and make the index zero based.
10618 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
10619 ;; two rules below:
10621 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
10623 ;; 1. An expression involving an external reference may only use the
10624 ;; addition operator, and only with an assembly-time constant.
10625 ;; The example above satisfies this because ".-.L2" is a constant.
10627 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
10628 ;; given the value of "GOT - .", where GOT is the actual address of
10629 ;; the Global Offset Table. Therefore, the .long above actually
10630 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
10631 ;; expression "GOT - .L2" by itself would generate an error from as(1).
10633 ;; The pattern below emits code that looks like this:
10636 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
10639 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
10640 ;; the addr_diff_vec is known to be part of this module.
10642 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
10643 ;; evaluates to just ".L2".
10645 (define_expand "casesi"
10646 [(set (match_dup 5)
10647 (match_operand:SI 0 "general_operand" ""))
10648 (parallel [(set (match_dup 6)
10649 (minus:SI (match_dup 5)
10650 (match_operand:SI 1 "general_operand" "")))
10651 (clobber (reg:CC 17))])
10653 (compare:CC (match_dup 6)
10654 (match_operand:SI 2 "general_operand" "")))
10656 (if_then_else (gtu (reg:CC 17)
10658 (label_ref (match_operand 4 "" ""))
10661 [(set (match_dup 7)
10662 (minus:SI (match_dup 8)
10663 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
10665 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
10666 (clobber (reg:CC 17))])
10667 (parallel [(set (pc) (match_dup 7))
10668 (use (label_ref (match_dup 3)))])]
10672 operands[5] = gen_reg_rtx (SImode);
10673 operands[6] = gen_reg_rtx (SImode);
10674 operands[7] = gen_reg_rtx (SImode);
10675 operands[8] = pic_offset_table_rtx;
10676 current_function_uses_pic_offset_table = 1;
10679 (define_insn "*tablejump_pic"
10680 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
10681 (use (label_ref (match_operand 1 "" "")))]
10684 [(set_attr "type" "ibr")
10685 (set_attr "length_immediate" "0")])
10687 ;; Loop instruction
10689 ;; This is all complicated by the fact that since this is a jump insn
10690 ;; we must handle our own reloads.
10692 (define_expand "doloop_end"
10693 [(use (match_operand 0 "" "")) ; loop pseudo
10694 (use (match_operand 1 "" "")) ; iterations; zero if unknown
10695 (use (match_operand 2 "" "")) ; max iterations
10696 (use (match_operand 3 "" "")) ; loop level
10697 (use (match_operand 4 "" ""))] ; label
10698 "TARGET_USE_LOOP && !TARGET_64BIT"
10701 /* Only use cloop on innermost loops. */
10702 if (INTVAL (operands[3]) > 1)
10704 if (GET_MODE (operands[0]) != SImode)
10706 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
10711 (define_insn "doloop_end_internal"
10713 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
10715 (label_ref (match_operand 0 "" ""))
10717 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
10718 (plus:SI (match_dup 1)
10720 (clobber (match_scratch:SI 3 "=X,X,r"))
10721 (clobber (reg:CC 17))]
10722 "TARGET_USE_LOOP && !TARGET_64BIT"
10725 if (which_alternative != 0)
10727 if (get_attr_length (insn) == 2)
10728 return \"loop\\t%l0\";
10730 return \"dec{l}\\t%1\;jne\\t%l0\";
10732 [(set_attr "ppro_uops" "many")
10734 (if_then_else (and (eq_attr "alternative" "0")
10735 (and (ge (minus (match_dup 0) (pc))
10737 (lt (minus (match_dup 0) (pc))
10739 (const_string "ibr")
10740 (const_string "multi")))])
10744 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
10746 (match_operand 0 "" "")
10749 (plus:SI (match_dup 1)
10751 (clobber (match_scratch:SI 2 ""))
10752 (clobber (reg:CC 17))]
10753 "TARGET_USE_LOOP && !TARGET_64BIT
10754 && reload_completed
10755 && REGNO (operands[1]) != 2"
10756 [(parallel [(set (reg:CCZ 17)
10757 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
10759 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
10760 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
10767 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
10769 (match_operand 0 "" "")
10771 (set (match_operand:SI 2 "nonimmediate_operand" "")
10772 (plus:SI (match_dup 1)
10774 (clobber (match_scratch:SI 3 ""))
10775 (clobber (reg:CC 17))]
10776 "TARGET_USE_LOOP && !TARGET_64BIT
10777 && reload_completed
10778 && (! REG_P (operands[2])
10779 || ! rtx_equal_p (operands[1], operands[2]))"
10780 [(set (match_dup 3) (match_dup 1))
10781 (parallel [(set (reg:CCZ 17)
10782 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
10784 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
10785 (set (match_dup 2) (match_dup 3))
10786 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
10791 ;; Call instructions.
10793 ;; The predicates normally associated with named expanders are not properly
10794 ;; checked for calls. This is a bug in the generic code, but it isn't that
10795 ;; easy to fix. Ignore it for now and be prepared to fix things up.
10797 ;; Call subroutine returning no value.
10799 (define_expand "call_pop"
10800 [(parallel [(call (match_operand:QI 0 "" "")
10801 (match_operand:SI 1 "" ""))
10803 (plus:SI (reg:SI 7)
10804 (match_operand:SI 3 "" "")))])]
10808 if (operands[3] == const0_rtx)
10810 emit_insn (gen_call (operands[0], operands[1]));
10813 /* Static functions and indirect calls don't need
10814 current_function_uses_pic_offset_table. */
10816 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
10817 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
10818 current_function_uses_pic_offset_table = 1;
10819 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
10820 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
10825 (define_insn "*call_pop_0"
10826 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
10827 (match_operand:SI 1 "" ""))
10828 (set (reg:SI 7) (plus:SI (reg:SI 7)
10829 (match_operand:SI 2 "immediate_operand" "")))]
10833 if (SIBLING_CALL_P (insn))
10834 return \"jmp\\t%P0\";
10836 return \"call\\t%P0\";
10838 [(set_attr "type" "call")])
10840 (define_insn "*call_pop_1"
10841 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
10842 (match_operand:SI 1 "" ""))
10843 (set (reg:SI 7) (plus:SI (reg:SI 7)
10844 (match_operand:SI 2 "immediate_operand" "i")))]
10848 if (constant_call_address_operand (operands[0], Pmode))
10850 if (SIBLING_CALL_P (insn))
10851 return \"jmp\\t%P0\";
10853 return \"call\\t%P0\";
10855 if (SIBLING_CALL_P (insn))
10856 return \"jmp\\t%A0\";
10858 return \"call\\t%A0\";
10860 [(set_attr "type" "call")])
10862 (define_expand "call"
10863 [(call (match_operand:QI 0 "" "")
10864 (match_operand:SI 1 "" ""))]
10865 ;; Operand 1 not used on the i386.
10869 /* Static functions and indirect calls don't need
10870 current_function_uses_pic_offset_table. */
10872 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
10873 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
10874 current_function_uses_pic_offset_table = 1;
10875 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
10876 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
10879 (define_insn "*call_0"
10880 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
10881 (match_operand:SI 1 "" ""))]
10885 if (SIBLING_CALL_P (insn))
10886 return \"jmp\\t%P0\";
10888 return \"call\\t%P0\";
10890 [(set_attr "type" "call")])
10892 (define_insn "*call_1"
10893 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
10894 (match_operand:SI 1 "" ""))]
10898 if (constant_call_address_operand (operands[0], QImode))
10900 if (SIBLING_CALL_P (insn))
10901 return \"jmp\\t%P0\";
10903 return \"call\\t%P0\";
10905 if (SIBLING_CALL_P (insn))
10906 return \"jmp\\t%A0\";
10908 return \"call\\t%A0\";
10910 [(set_attr "type" "call")])
10912 ;; Call subroutine, returning value in operand 0
10913 ;; (which must be a hard register).
10915 (define_expand "call_value_pop"
10916 [(parallel [(set (match_operand 0 "" "")
10917 (call (match_operand:QI 1 "" "")
10918 (match_operand:SI 2 "" "")))
10920 (plus:SI (reg:SI 7)
10921 (match_operand:SI 4 "" "")))])]
10925 if (operands[4] == const0_rtx)
10927 emit_insn (gen_call_value (operands[0], operands[1], operands[2]));
10930 /* Static functions and indirect calls don't need
10931 current_function_uses_pic_offset_table. */
10933 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10934 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
10935 current_function_uses_pic_offset_table = 1;
10936 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
10937 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
10940 (define_expand "call_value"
10941 [(set (match_operand 0 "" "")
10942 (call (match_operand:QI 1 "" "")
10943 (match_operand:SI 2 "" "")))]
10944 ;; Operand 2 not used on the i386.
10948 /* Static functions and indirect calls don't need
10949 current_function_uses_pic_offset_table. */
10951 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10952 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
10953 current_function_uses_pic_offset_table = 1;
10954 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
10955 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
10958 ;; Call subroutine returning any type.
10960 (define_expand "untyped_call"
10961 [(parallel [(call (match_operand 0 "" "")
10963 (match_operand 1 "" "")
10964 (match_operand 2 "" "")])]
10970 /* In order to give reg-stack an easier job in validating two
10971 coprocessor registers as containing a possible return value,
10972 simply pretend the untyped call returns a complex long double
10975 emit_call_insn (TARGET_80387
10976 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
10977 operands[0], const0_rtx)
10978 : gen_call (operands[0], const0_rtx));
10980 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10982 rtx set = XVECEXP (operands[2], 0, i);
10983 emit_move_insn (SET_DEST (set), SET_SRC (set));
10986 /* The optimizer does not know that the call sets the function value
10987 registers we stored in the result block. We avoid problems by
10988 claiming that all hard registers are used and clobbered at this
10990 emit_insn (gen_blockage ());
10995 ;; Prologue and epilogue instructions
10997 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10998 ;; all of memory. This blocks insns from being moved across this point.
11000 (define_insn "blockage"
11001 [(unspec_volatile [(const_int 0)] 0)]
11004 [(set_attr "length" "0")])
11006 ;; Insn emitted into the body of a function to return from a function.
11007 ;; This is only done if the function's epilogue is known to be simple.
11008 ;; See comments for ix86_can_use_return_insn_p in i386.c.
11010 (define_expand "return"
11012 "ix86_can_use_return_insn_p ()"
11015 if (current_function_pops_args)
11017 rtx popc = GEN_INT (current_function_pops_args);
11018 emit_jump_insn (gen_return_pop_internal (popc));
11023 (define_insn "return_internal"
11027 [(set_attr "length" "1")
11028 (set_attr "length_immediate" "0")
11029 (set_attr "modrm" "0")])
11031 (define_insn "return_pop_internal"
11033 (use (match_operand:SI 0 "const_int_operand" ""))]
11036 [(set_attr "length" "3")
11037 (set_attr "length_immediate" "2")
11038 (set_attr "modrm" "0")])
11040 (define_insn "return_indirect_internal"
11042 (use (match_operand:SI 0 "register_operand" "r"))]
11045 [(set_attr "type" "ibr")
11046 (set_attr "length_immediate" "0")])
11052 [(set_attr "length" "1")
11053 (set_attr "length_immediate" "0")
11054 (set_attr "modrm" "0")
11055 (set_attr "ppro_uops" "one")])
11057 (define_expand "prologue"
11060 "ix86_expand_prologue (); DONE;")
11062 (define_insn "prologue_set_got"
11063 [(set (match_operand:SI 0 "register_operand" "=r")
11064 (unspec_volatile:SI
11065 [(plus:SI (match_dup 0)
11066 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
11067 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
11068 (clobber (reg:CC 17))]
11072 if (GET_CODE (operands[2]) == LABEL_REF)
11073 operands[2] = XEXP (operands[2], 0);
11074 if (TARGET_DEEP_BRANCH_PREDICTION)
11075 return \"add{l}\\t{%1, %0|%0, %1}\";
11077 return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
11079 [(set_attr "type" "alu")
11080 ; Since this insn may have two constant operands, we must set the
11082 (set_attr "length_immediate" "4")
11083 (set_attr "mode" "SI")])
11085 (define_insn "prologue_get_pc"
11086 [(set (match_operand:SI 0 "register_operand" "=r")
11087 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
11091 if (GET_CODE (operands[1]) == LABEL_REF)
11092 operands[1] = XEXP (operands[1], 0);
11093 output_asm_insn (\"call\\t%X1\", operands);
11094 if (! TARGET_DEEP_BRANCH_PREDICTION)
11096 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
11097 CODE_LABEL_NUMBER (operands[1]));
11101 [(set_attr "type" "multi")])
11103 (define_expand "epilogue"
11106 "ix86_expand_epilogue (1); DONE;")
11108 (define_expand "sibcall_epilogue"
11111 "ix86_expand_epilogue (0); DONE;")
11113 (define_insn "leave"
11114 [(set (reg:SI 7) (reg:SI 6))
11115 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
11118 [(set_attr "length_immediate" "0")
11119 (set_attr "length" "1")
11120 (set_attr "modrm" "0")
11121 (set_attr "modrm" "0")
11122 (set_attr "athlon_decode" "vector")
11123 (set_attr "ppro_uops" "few")])
11125 (define_expand "ffssi2"
11126 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11127 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
11131 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
11132 rtx in = operands[1];
11136 emit_move_insn (tmp, constm1_rtx);
11137 emit_insn (gen_ffssi_1 (out, in));
11138 emit_insn (gen_rtx_SET (VOIDmode, out,
11139 gen_rtx_IF_THEN_ELSE (SImode,
11140 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
11144 emit_insn (gen_addsi3 (out, out, const1_rtx));
11145 emit_move_insn (operands[0], out);
11148 /* Pentium bsf instruction is extremly slow. The following code is
11149 recommended by the Intel Optimizing Manual as a reasonable replacement:
11153 MOV DWORD PTR [TEMP+4],ECX
11156 MOV DWORD PTR [TEMP],EAX
11157 FILD QWORD PTR [TEMP]
11158 FSTP QWORD PTR [TEMP]
11159 WAIT ; WAIT only needed for compatibility with
11160 ; earlier processors
11161 MOV ECX, DWORD PTR [TEMP+4]
11164 TEST EAX,EAX ; clear zero flag
11166 Following piece of code expand ffs to similar beast.
11169 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
11171 rtx label = gen_label_rtx ();
11173 rtx mem = assign_386_stack_local (DImode, 0);
11174 rtx fptmp = gen_reg_rtx (DFmode);
11175 split_di (&mem, 1, &lo, &hi);
11177 emit_move_insn (out, const0_rtx);
11179 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
11181 emit_move_insn (hi, out);
11182 emit_insn (gen_subsi3 (out, out, in));
11183 emit_insn (gen_andsi3 (out, out, in));
11184 emit_move_insn (lo, out);
11185 emit_insn (gen_floatdidf2 (fptmp,mem));
11186 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
11187 emit_move_insn (out, hi);
11188 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
11189 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
11191 emit_label (label);
11192 LABEL_NUSES (label) = 1;
11194 emit_move_insn (operands[0], out);
11198 emit_move_insn (tmp, const0_rtx);
11199 emit_insn (gen_ffssi_1 (out, in));
11200 emit_insn (gen_rtx_SET (VOIDmode,
11201 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
11202 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
11204 emit_insn (gen_negsi2 (tmp, tmp));
11205 emit_insn (gen_iorsi3 (out, out, tmp));
11206 emit_insn (gen_addsi3 (out, out, const1_rtx));
11207 emit_move_insn (operands[0], out);
11212 (define_insn "ffssi_1"
11214 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
11216 (set (match_operand:SI 0 "register_operand" "=r")
11217 (unspec:SI [(match_dup 1)] 5))]
11219 "bsf{l}\\t{%1, %0|%0, %1}"
11220 [(set_attr "prefix_0f" "1")
11221 (set_attr "ppro_uops" "few")])
11223 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
11224 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
11226 ;; These patterns match the binary 387 instructions for addM3, subM3,
11227 ;; mulM3 and divM3. There are three patterns for each of DFmode and
11228 ;; SFmode. The first is the normal insn, the second the same insn but
11229 ;; with one operand a conversion, and the third the same insn but with
11230 ;; the other operand a conversion. The conversion may be SFmode or
11231 ;; SImode if the target mode DFmode, but only SImode if the target mode
11234 ;; Gcc is slightly more smart about handling normal two address instructions
11235 ;; so use special patterns for add and mull.
11236 (define_insn "*fop_sf_comm"
11237 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
11238 (match_operator:SF 3 "binary_fp_operator"
11239 [(match_operand:SF 1 "register_operand" "%0,0")
11240 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
11241 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
11242 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
11243 "* return output_387_binary_op (insn, operands);"
11244 [(set (attr "type")
11245 (if_then_else (eq_attr "alternative" "1")
11246 (const_string "sse")
11247 (if_then_else (match_operand:SF 3 "mult_operator" "")
11248 (const_string "fmul")
11249 (const_string "fop"))))
11250 (set_attr "mode" "SF")])
11252 (define_insn "*fop_sf_comm_sse"
11253 [(set (match_operand:SF 0 "register_operand" "=x")
11254 (match_operator:SF 3 "binary_fp_operator"
11255 [(match_operand:SF 1 "register_operand" "%0")
11256 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
11257 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
11258 "* return output_387_binary_op (insn, operands);"
11259 [(set_attr "type" "sse")
11260 (set_attr "mode" "SF")])
11262 (define_insn "*fop_df_comm"
11263 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
11264 (match_operator:DF 3 "binary_fp_operator"
11265 [(match_operand:DF 1 "register_operand" "%0,0")
11266 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
11267 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
11268 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
11269 "* return output_387_binary_op (insn, operands);"
11270 [(set (attr "type")
11271 (if_then_else (eq_attr "alternative" "1")
11272 (const_string "sse")
11273 (if_then_else (match_operand:SF 3 "mult_operator" "")
11274 (const_string "fmul")
11275 (const_string "fop"))))
11276 (set_attr "mode" "DF")])
11278 (define_insn "*fop_df_comm_sse"
11279 [(set (match_operand:DF 0 "register_operand" "=Y")
11280 (match_operator:DF 3 "binary_fp_operator"
11281 [(match_operand:DF 1 "register_operand" "%0")
11282 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
11284 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
11285 "* return output_387_binary_op (insn, operands);"
11286 [(set_attr "type" "sse")
11287 (set_attr "mode" "DF")])
11289 (define_insn "*fop_xf_comm"
11290 [(set (match_operand:XF 0 "register_operand" "=f")
11291 (match_operator:XF 3 "binary_fp_operator"
11292 [(match_operand:XF 1 "register_operand" "%0")
11293 (match_operand:XF 2 "register_operand" "f")]))]
11294 "TARGET_80387 && !TARGET_64BIT
11295 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
11296 "* return output_387_binary_op (insn, operands);"
11297 [(set (attr "type")
11298 (if_then_else (match_operand:XF 3 "mult_operator" "")
11299 (const_string "fmul")
11300 (const_string "fop")))
11301 (set_attr "mode" "XF")])
11303 (define_insn "*fop_tf_comm"
11304 [(set (match_operand:TF 0 "register_operand" "=f")
11305 (match_operator:TF 3 "binary_fp_operator"
11306 [(match_operand:TF 1 "register_operand" "%0")
11307 (match_operand:TF 2 "register_operand" "f")]))]
11308 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
11309 "* return output_387_binary_op (insn, operands);"
11310 [(set (attr "type")
11311 (if_then_else (match_operand:TF 3 "mult_operator" "")
11312 (const_string "fmul")
11313 (const_string "fop")))
11314 (set_attr "mode" "XF")])
11316 (define_insn "*fop_sf_1"
11317 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
11318 (match_operator:SF 3 "binary_fp_operator"
11319 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
11320 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
11321 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
11322 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
11323 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
11324 "* return output_387_binary_op (insn, operands);"
11325 [(set (attr "type")
11326 (cond [(eq_attr "alternative" "2")
11327 (const_string "sse")
11328 (match_operand:SF 3 "mult_operator" "")
11329 (const_string "fmul")
11330 (match_operand:SF 3 "div_operator" "")
11331 (const_string "fdiv")
11333 (const_string "fop")))
11334 (set_attr "mode" "SF")])
11336 (define_insn "*fop_sf_1_sse"
11337 [(set (match_operand:SF 0 "register_operand" "=x")
11338 (match_operator:SF 3 "binary_fp_operator"
11339 [(match_operand:SF 1 "register_operand" "0")
11340 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
11342 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
11343 "* return output_387_binary_op (insn, operands);"
11344 [(set_attr "type" "sse")
11345 (set_attr "mode" "SF")])
11347 ;; ??? Add SSE splitters for these!
11348 (define_insn "*fop_sf_2"
11349 [(set (match_operand:SF 0 "register_operand" "=f,f")
11350 (match_operator:SF 3 "binary_fp_operator"
11351 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
11352 (match_operand:SF 2 "register_operand" "0,0")]))]
11353 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
11354 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11355 [(set (attr "type")
11356 (cond [(match_operand:SF 3 "mult_operator" "")
11357 (const_string "fmul")
11358 (match_operand:SF 3 "div_operator" "")
11359 (const_string "fdiv")
11361 (const_string "fop")))
11362 (set_attr "fp_int_src" "true")
11363 (set_attr "ppro_uops" "many")
11364 (set_attr "mode" "SI")])
11366 (define_insn "*fop_sf_3"
11367 [(set (match_operand:SF 0 "register_operand" "=f,f")
11368 (match_operator:SF 3 "binary_fp_operator"
11369 [(match_operand:SF 1 "register_operand" "0,0")
11370 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
11371 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
11372 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11373 [(set (attr "type")
11374 (cond [(match_operand:SF 3 "mult_operator" "")
11375 (const_string "fmul")
11376 (match_operand:SF 3 "div_operator" "")
11377 (const_string "fdiv")
11379 (const_string "fop")))
11380 (set_attr "fp_int_src" "true")
11381 (set_attr "ppro_uops" "many")
11382 (set_attr "mode" "SI")])
11384 (define_insn "*fop_df_1"
11385 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
11386 (match_operator:DF 3 "binary_fp_operator"
11387 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
11388 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
11389 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
11390 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
11391 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
11392 "* return output_387_binary_op (insn, operands);"
11393 [(set (attr "type")
11394 (cond [(eq_attr "alternative" "2")
11395 (const_string "sse")
11396 (match_operand:DF 3 "mult_operator" "")
11397 (const_string "fmul")
11398 (match_operand:DF 3 "div_operator" "")
11399 (const_string "fdiv")
11401 (const_string "fop")))
11402 (set_attr "mode" "DF")])
11404 (define_insn "*fop_df_1_sse"
11405 [(set (match_operand:DF 0 "register_operand" "=Y")
11406 (match_operator:DF 3 "binary_fp_operator"
11407 [(match_operand:DF 1 "register_operand" "0")
11408 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
11410 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
11411 "* return output_387_binary_op (insn, operands);"
11412 [(set_attr "type" "sse")])
11414 ;; ??? Add SSE splitters for these!
11415 (define_insn "*fop_df_2"
11416 [(set (match_operand:DF 0 "register_operand" "=f,f")
11417 (match_operator:DF 3 "binary_fp_operator"
11418 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
11419 (match_operand:DF 2 "register_operand" "0,0")]))]
11420 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
11421 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11422 [(set (attr "type")
11423 (cond [(match_operand:DF 3 "mult_operator" "")
11424 (const_string "fmul")
11425 (match_operand:DF 3 "div_operator" "")
11426 (const_string "fdiv")
11428 (const_string "fop")))
11429 (set_attr "fp_int_src" "true")
11430 (set_attr "ppro_uops" "many")
11431 (set_attr "mode" "SI")])
11433 (define_insn "*fop_df_3"
11434 [(set (match_operand:DF 0 "register_operand" "=f,f")
11435 (match_operator:DF 3 "binary_fp_operator"
11436 [(match_operand:DF 1 "register_operand" "0,0")
11437 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
11438 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
11439 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11440 [(set (attr "type")
11441 (cond [(match_operand:DF 3 "mult_operator" "")
11442 (const_string "fmul")
11443 (match_operand:DF 3 "div_operator" "")
11444 (const_string "fdiv")
11446 (const_string "fop")))
11447 (set_attr "fp_int_src" "true")
11448 (set_attr "ppro_uops" "many")
11449 (set_attr "mode" "SI")])
11451 (define_insn "*fop_df_4"
11452 [(set (match_operand:DF 0 "register_operand" "=f,f")
11453 (match_operator:DF 3 "binary_fp_operator"
11454 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
11455 (match_operand:DF 2 "register_operand" "0,f")]))]
11457 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
11458 "* return output_387_binary_op (insn, operands);"
11459 [(set (attr "type")
11460 (cond [(match_operand:DF 3 "mult_operator" "")
11461 (const_string "fmul")
11462 (match_operand:DF 3 "div_operator" "")
11463 (const_string "fdiv")
11465 (const_string "fop")))
11466 (set_attr "mode" "SF")])
11468 (define_insn "*fop_df_5"
11469 [(set (match_operand:DF 0 "register_operand" "=f,f")
11470 (match_operator:DF 3 "binary_fp_operator"
11471 [(match_operand:DF 1 "register_operand" "0,f")
11473 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
11474 "TARGET_80387 && !TARGET_SSE2"
11475 "* return output_387_binary_op (insn, operands);"
11476 [(set (attr "type")
11477 (cond [(match_operand:DF 3 "mult_operator" "")
11478 (const_string "fmul")
11479 (match_operand:DF 3 "div_operator" "")
11480 (const_string "fdiv")
11482 (const_string "fop")))
11483 (set_attr "mode" "SF")])
11485 (define_insn "*fop_xf_1"
11486 [(set (match_operand:XF 0 "register_operand" "=f,f")
11487 (match_operator:XF 3 "binary_fp_operator"
11488 [(match_operand:XF 1 "register_operand" "0,f")
11489 (match_operand:XF 2 "register_operand" "f,0")]))]
11490 "TARGET_80387 && !TARGET_64BIT
11491 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
11492 "* return output_387_binary_op (insn, operands);"
11493 [(set (attr "type")
11494 (cond [(match_operand:XF 3 "mult_operator" "")
11495 (const_string "fmul")
11496 (match_operand:XF 3 "div_operator" "")
11497 (const_string "fdiv")
11499 (const_string "fop")))
11500 (set_attr "mode" "XF")])
11502 (define_insn "*fop_tf_1"
11503 [(set (match_operand:TF 0 "register_operand" "=f,f")
11504 (match_operator:TF 3 "binary_fp_operator"
11505 [(match_operand:TF 1 "register_operand" "0,f")
11506 (match_operand:TF 2 "register_operand" "f,0")]))]
11508 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
11509 "* return output_387_binary_op (insn, operands);"
11510 [(set (attr "type")
11511 (cond [(match_operand:TF 3 "mult_operator" "")
11512 (const_string "fmul")
11513 (match_operand:TF 3 "div_operator" "")
11514 (const_string "fdiv")
11516 (const_string "fop")))
11517 (set_attr "mode" "XF")])
11519 (define_insn "*fop_xf_2"
11520 [(set (match_operand:XF 0 "register_operand" "=f,f")
11521 (match_operator:XF 3 "binary_fp_operator"
11522 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
11523 (match_operand:XF 2 "register_operand" "0,0")]))]
11524 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
11525 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11526 [(set (attr "type")
11527 (cond [(match_operand:XF 3 "mult_operator" "")
11528 (const_string "fmul")
11529 (match_operand:XF 3 "div_operator" "")
11530 (const_string "fdiv")
11532 (const_string "fop")))
11533 (set_attr "fp_int_src" "true")
11534 (set_attr "mode" "SI")
11535 (set_attr "ppro_uops" "many")])
11537 (define_insn "*fop_tf_2"
11538 [(set (match_operand:TF 0 "register_operand" "=f,f")
11539 (match_operator:TF 3 "binary_fp_operator"
11540 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
11541 (match_operand:TF 2 "register_operand" "0,0")]))]
11542 "TARGET_80387 && TARGET_USE_FIOP"
11543 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11544 [(set (attr "type")
11545 (cond [(match_operand:TF 3 "mult_operator" "")
11546 (const_string "fmul")
11547 (match_operand:TF 3 "div_operator" "")
11548 (const_string "fdiv")
11550 (const_string "fop")))
11551 (set_attr "fp_int_src" "true")
11552 (set_attr "mode" "SI")
11553 (set_attr "ppro_uops" "many")])
11555 (define_insn "*fop_xf_3"
11556 [(set (match_operand:XF 0 "register_operand" "=f,f")
11557 (match_operator:XF 3 "binary_fp_operator"
11558 [(match_operand:XF 1 "register_operand" "0,0")
11559 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
11560 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
11561 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11562 [(set (attr "type")
11563 (cond [(match_operand:XF 3 "mult_operator" "")
11564 (const_string "fmul")
11565 (match_operand:XF 3 "div_operator" "")
11566 (const_string "fdiv")
11568 (const_string "fop")))
11569 (set_attr "fp_int_src" "true")
11570 (set_attr "mode" "SI")
11571 (set_attr "ppro_uops" "many")])
11573 (define_insn "*fop_tf_3"
11574 [(set (match_operand:TF 0 "register_operand" "=f,f")
11575 (match_operator:TF 3 "binary_fp_operator"
11576 [(match_operand:TF 1 "register_operand" "0,0")
11577 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
11578 "TARGET_80387 && TARGET_USE_FIOP"
11579 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
11580 [(set (attr "type")
11581 (cond [(match_operand:TF 3 "mult_operator" "")
11582 (const_string "fmul")
11583 (match_operand:TF 3 "div_operator" "")
11584 (const_string "fdiv")
11586 (const_string "fop")))
11587 (set_attr "fp_int_src" "true")
11588 (set_attr "mode" "SI")
11589 (set_attr "ppro_uops" "many")])
11591 (define_insn "*fop_xf_4"
11592 [(set (match_operand:XF 0 "register_operand" "=f,f")
11593 (match_operator:XF 3 "binary_fp_operator"
11594 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
11595 (match_operand:XF 2 "register_operand" "0,f")]))]
11596 "TARGET_80387 && !TARGET_64BIT"
11597 "* return output_387_binary_op (insn, operands);"
11598 [(set (attr "type")
11599 (cond [(match_operand:XF 3 "mult_operator" "")
11600 (const_string "fmul")
11601 (match_operand:XF 3 "div_operator" "")
11602 (const_string "fdiv")
11604 (const_string "fop")))
11605 (set_attr "mode" "SF")])
11607 (define_insn "*fop_tf_4"
11608 [(set (match_operand:TF 0 "register_operand" "=f,f")
11609 (match_operator:TF 3 "binary_fp_operator"
11610 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
11611 (match_operand:TF 2 "register_operand" "0,f")]))]
11613 "* return output_387_binary_op (insn, operands);"
11614 [(set (attr "type")
11615 (cond [(match_operand:TF 3 "mult_operator" "")
11616 (const_string "fmul")
11617 (match_operand:TF 3 "div_operator" "")
11618 (const_string "fdiv")
11620 (const_string "fop")))
11621 (set_attr "mode" "SF")])
11623 (define_insn "*fop_xf_5"
11624 [(set (match_operand:XF 0 "register_operand" "=f,f")
11625 (match_operator:XF 3 "binary_fp_operator"
11626 [(match_operand:XF 1 "register_operand" "0,f")
11628 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
11629 "TARGET_80387 && !TARGET_64BIT"
11630 "* return output_387_binary_op (insn, operands);"
11631 [(set (attr "type")
11632 (cond [(match_operand:XF 3 "mult_operator" "")
11633 (const_string "fmul")
11634 (match_operand:XF 3 "div_operator" "")
11635 (const_string "fdiv")
11637 (const_string "fop")))
11638 (set_attr "mode" "SF")])
11640 (define_insn "*fop_tf_5"
11641 [(set (match_operand:TF 0 "register_operand" "=f,f")
11642 (match_operator:TF 3 "binary_fp_operator"
11643 [(match_operand:TF 1 "register_operand" "0,f")
11645 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
11647 "* return output_387_binary_op (insn, operands);"
11648 [(set (attr "type")
11649 (cond [(match_operand:TF 3 "mult_operator" "")
11650 (const_string "fmul")
11651 (match_operand:TF 3 "div_operator" "")
11652 (const_string "fdiv")
11654 (const_string "fop")))
11655 (set_attr "mode" "SF")])
11657 (define_insn "*fop_xf_6"
11658 [(set (match_operand:XF 0 "register_operand" "=f,f")
11659 (match_operator:XF 3 "binary_fp_operator"
11660 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
11661 (match_operand:XF 2 "register_operand" "0,f")]))]
11662 "TARGET_80387 && !TARGET_64BIT"
11663 "* return output_387_binary_op (insn, operands);"
11664 [(set (attr "type")
11665 (cond [(match_operand:XF 3 "mult_operator" "")
11666 (const_string "fmul")
11667 (match_operand:XF 3 "div_operator" "")
11668 (const_string "fdiv")
11670 (const_string "fop")))
11671 (set_attr "mode" "DF")])
11673 (define_insn "*fop_tf_6"
11674 [(set (match_operand:TF 0 "register_operand" "=f,f")
11675 (match_operator:TF 3 "binary_fp_operator"
11676 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
11677 (match_operand:TF 2 "register_operand" "0,f")]))]
11679 "* return output_387_binary_op (insn, operands);"
11680 [(set (attr "type")
11681 (cond [(match_operand:TF 3 "mult_operator" "")
11682 (const_string "fmul")
11683 (match_operand:TF 3 "div_operator" "")
11684 (const_string "fdiv")
11686 (const_string "fop")))
11687 (set_attr "mode" "DF")])
11689 (define_insn "*fop_xf_7"
11690 [(set (match_operand:XF 0 "register_operand" "=f,f")
11691 (match_operator:XF 3 "binary_fp_operator"
11692 [(match_operand:XF 1 "register_operand" "0,f")
11694 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
11695 "TARGET_80387 && !TARGET_64BIT"
11696 "* return output_387_binary_op (insn, operands);"
11697 [(set (attr "type")
11698 (cond [(match_operand:XF 3 "mult_operator" "")
11699 (const_string "fmul")
11700 (match_operand:XF 3 "div_operator" "")
11701 (const_string "fdiv")
11703 (const_string "fop")))
11704 (set_attr "mode" "DF")])
11706 (define_insn "*fop_tf_7"
11707 [(set (match_operand:TF 0 "register_operand" "=f,f")
11708 (match_operator:TF 3 "binary_fp_operator"
11709 [(match_operand:TF 1 "register_operand" "0,f")
11711 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
11713 "* return output_387_binary_op (insn, operands);"
11714 [(set (attr "type")
11715 (cond [(match_operand:TF 3 "mult_operator" "")
11716 (const_string "fmul")
11717 (match_operand:TF 3 "div_operator" "")
11718 (const_string "fdiv")
11720 (const_string "fop")))
11721 (set_attr "mode" "DF")])
11724 [(set (match_operand 0 "register_operand" "")
11725 (match_operator 3 "binary_fp_operator"
11726 [(float (match_operand:SI 1 "register_operand" ""))
11727 (match_operand 2 "register_operand" "")]))]
11728 "TARGET_80387 && reload_completed
11729 && FLOAT_MODE_P (GET_MODE (operands[0]))"
11733 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
11734 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
11735 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11736 gen_rtx_fmt_ee (GET_CODE (operands[3]),
11737 GET_MODE (operands[3]),
11740 ix86_free_from_memory (GET_MODE (operands[1]));
11745 [(set (match_operand 0 "register_operand" "")
11746 (match_operator 3 "binary_fp_operator"
11747 [(match_operand 1 "register_operand" "")
11748 (float (match_operand:SI 2 "register_operand" ""))]))]
11749 "TARGET_80387 && reload_completed
11750 && FLOAT_MODE_P (GET_MODE (operands[0]))"
11754 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
11755 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
11756 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11757 gen_rtx_fmt_ee (GET_CODE (operands[3]),
11758 GET_MODE (operands[3]),
11761 ix86_free_from_memory (GET_MODE (operands[2]));
11765 ;; FPU special functions.
11767 (define_expand "sqrtsf2"
11768 [(set (match_operand:SF 0 "register_operand" "")
11769 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
11770 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
11774 operands[1] = force_reg (SFmode, operands[1]);
11777 (define_insn "sqrtsf2_1"
11778 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
11779 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
11780 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11781 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
11784 sqrtss\\t{%1, %0|%0, %1}"
11785 [(set_attr "type" "fpspc,sse")
11786 (set_attr "mode" "SF,SF")
11787 (set_attr "athlon_decode" "direct,*")])
11789 (define_insn "sqrtsf2_1_sse_only"
11790 [(set (match_operand:SF 0 "register_operand" "=x")
11791 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
11792 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
11793 "sqrtss\\t{%1, %0|%0, %1}"
11794 [(set_attr "type" "sse")
11795 (set_attr "mode" "SF")
11796 (set_attr "athlon_decode" "*")])
11798 (define_insn "sqrtsf2_i387"
11799 [(set (match_operand:SF 0 "register_operand" "=f")
11800 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
11801 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11802 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
11804 [(set_attr "type" "fpspc")
11805 (set_attr "mode" "SF")
11806 (set_attr "athlon_decode" "direct")])
11808 (define_expand "sqrtdf2"
11809 [(set (match_operand:DF 0 "register_operand" "")
11810 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
11811 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
11815 operands[1] = force_reg (SFmode, operands[1]);
11818 (define_insn "sqrtdf2_1"
11819 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
11820 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
11821 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11822 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
11825 sqrtsd\\t{%1, %0|%0, %1}"
11826 [(set_attr "type" "fpspc,sse")
11827 (set_attr "mode" "DF,DF")
11828 (set_attr "athlon_decode" "direct,*")])
11830 (define_insn "sqrtdf2_1_sse_only"
11831 [(set (match_operand:DF 0 "register_operand" "=Y")
11832 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
11833 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
11834 "sqrtsd\\t{%1, %0|%0, %1}"
11835 [(set_attr "type" "sse")
11836 (set_attr "mode" "DF")
11837 (set_attr "athlon_decode" "*")])
11839 (define_insn "sqrtdf2_i387"
11840 [(set (match_operand:DF 0 "register_operand" "=f")
11841 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
11842 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11843 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
11845 [(set_attr "type" "fpspc")
11846 (set_attr "mode" "DF")
11847 (set_attr "athlon_decode" "direct")])
11849 (define_insn "*sqrtextendsfdf2"
11850 [(set (match_operand:DF 0 "register_operand" "=f")
11851 (sqrt:DF (float_extend:DF
11852 (match_operand:SF 1 "register_operand" "0"))))]
11853 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
11855 [(set_attr "type" "fpspc")
11856 (set_attr "mode" "DF")
11857 (set_attr "athlon_decode" "direct")])
11859 (define_insn "sqrtxf2"
11860 [(set (match_operand:XF 0 "register_operand" "=f")
11861 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
11862 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
11863 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
11865 [(set_attr "type" "fpspc")
11866 (set_attr "mode" "XF")
11867 (set_attr "athlon_decode" "direct")])
11869 (define_insn "sqrttf2"
11870 [(set (match_operand:TF 0 "register_operand" "=f")
11871 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
11872 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11873 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
11875 [(set_attr "type" "fpspc")
11876 (set_attr "mode" "XF")
11877 (set_attr "athlon_decode" "direct")])
11879 (define_insn "*sqrtextenddfxf2"
11880 [(set (match_operand:XF 0 "register_operand" "=f")
11881 (sqrt:XF (float_extend:XF
11882 (match_operand:DF 1 "register_operand" "0"))))]
11883 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
11885 [(set_attr "type" "fpspc")
11886 (set_attr "mode" "XF")
11887 (set_attr "athlon_decode" "direct")])
11889 (define_insn "*sqrtextenddftf2"
11890 [(set (match_operand:TF 0 "register_operand" "=f")
11891 (sqrt:TF (float_extend:TF
11892 (match_operand:DF 1 "register_operand" "0"))))]
11893 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
11895 [(set_attr "type" "fpspc")
11896 (set_attr "mode" "XF")
11897 (set_attr "athlon_decode" "direct")])
11899 (define_insn "*sqrtextendsfxf2"
11900 [(set (match_operand:XF 0 "register_operand" "=f")
11901 (sqrt:XF (float_extend:XF
11902 (match_operand:SF 1 "register_operand" "0"))))]
11903 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
11905 [(set_attr "type" "fpspc")
11906 (set_attr "mode" "XF")
11907 (set_attr "athlon_decode" "direct")])
11909 (define_insn "*sqrtextendsftf2"
11910 [(set (match_operand:TF 0 "register_operand" "=f")
11911 (sqrt:TF (float_extend:TF
11912 (match_operand:SF 1 "register_operand" "0"))))]
11913 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
11915 [(set_attr "type" "fpspc")
11916 (set_attr "mode" "XF")
11917 (set_attr "athlon_decode" "direct")])
11919 (define_insn "sindf2"
11920 [(set (match_operand:DF 0 "register_operand" "=f")
11921 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
11922 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11923 && flag_unsafe_math_optimizations"
11925 [(set_attr "type" "fpspc")
11926 (set_attr "mode" "DF")])
11928 (define_insn "sinsf2"
11929 [(set (match_operand:SF 0 "register_operand" "=f")
11930 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
11931 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11932 && flag_unsafe_math_optimizations"
11934 [(set_attr "type" "fpspc")
11935 (set_attr "mode" "SF")])
11937 (define_insn "*sinextendsfdf2"
11938 [(set (match_operand:DF 0 "register_operand" "=f")
11939 (unspec:DF [(float_extend:DF
11940 (match_operand:SF 1 "register_operand" "0"))] 1))]
11941 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11942 && flag_unsafe_math_optimizations"
11944 [(set_attr "type" "fpspc")
11945 (set_attr "mode" "DF")])
11947 (define_insn "sinxf2"
11948 [(set (match_operand:XF 0 "register_operand" "=f")
11949 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
11950 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
11951 && flag_unsafe_math_optimizations"
11953 [(set_attr "type" "fpspc")
11954 (set_attr "mode" "XF")])
11956 (define_insn "sintf2"
11957 [(set (match_operand:TF 0 "register_operand" "=f")
11958 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
11959 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11960 && flag_unsafe_math_optimizations"
11962 [(set_attr "type" "fpspc")
11963 (set_attr "mode" "XF")])
11965 (define_insn "cosdf2"
11966 [(set (match_operand:DF 0 "register_operand" "=f")
11967 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
11968 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11969 && flag_unsafe_math_optimizations"
11971 [(set_attr "type" "fpspc")
11972 (set_attr "mode" "DF")])
11974 (define_insn "cossf2"
11975 [(set (match_operand:SF 0 "register_operand" "=f")
11976 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
11977 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11978 && flag_unsafe_math_optimizations"
11980 [(set_attr "type" "fpspc")
11981 (set_attr "mode" "SF")])
11983 (define_insn "*cosextendsfdf2"
11984 [(set (match_operand:DF 0 "register_operand" "=f")
11985 (unspec:DF [(float_extend:DF
11986 (match_operand:SF 1 "register_operand" "0"))] 2))]
11987 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11988 && flag_unsafe_math_optimizations"
11990 [(set_attr "type" "fpspc")
11991 (set_attr "mode" "DF")])
11993 (define_insn "cosxf2"
11994 [(set (match_operand:XF 0 "register_operand" "=f")
11995 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
11996 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11997 && flag_unsafe_math_optimizations"
11999 [(set_attr "type" "fpspc")
12000 (set_attr "mode" "XF")])
12002 (define_insn "costf2"
12003 [(set (match_operand:TF 0 "register_operand" "=f")
12004 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
12005 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
12006 && flag_unsafe_math_optimizations"
12008 [(set_attr "type" "fpspc")
12009 (set_attr "mode" "XF")])
12011 ;; Block operation instructions
12014 [(set (reg:SI 19) (const_int 0))]
12017 [(set_attr "type" "cld")])
12019 (define_expand "movstrsi"
12020 [(use (match_operand:BLK 0 "memory_operand" ""))
12021 (use (match_operand:BLK 1 "memory_operand" ""))
12022 (use (match_operand:SI 2 "nonmemory_operand" ""))
12023 (use (match_operand:SI 3 "const_int_operand" ""))]
12027 rtx srcreg, destreg, countreg;
12034 if (GET_CODE (operands[3]) == CONST_INT)
12035 align = INTVAL (operands[3]);
12037 /* This simple hack avoids all inlining code and simplifies code bellow. */
12038 if (!TARGET_ALIGN_STRINGOPS)
12041 if (GET_CODE (operands[2]) == CONST_INT)
12042 count = INTVAL (operands[2]);
12044 destreg = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
12045 srcreg = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
12047 emit_insn (gen_cld ());
12049 /* When optimizing for size emit simple rep ; movsb instruction for
12050 counts not divisible by 4. */
12052 if ((!optimize || optimize_size)
12053 && (count < 0 || (count & 0x03)))
12055 countreg = copy_to_mode_reg (SImode, operands[2]);
12056 emit_insn (gen_rep_movqi (destreg, srcreg, countreg,
12057 destreg, srcreg, countreg));
12060 /* For constant aligned (or small unaligned) copies use rep movsl
12061 followed by code copying the rest. For PentiumPro ensure 8 byte
12062 alignment to allow rep movsl acceleration. */
12064 else if (count >= 0
12066 || (!TARGET_PENTIUMPRO && align >= 4)
12067 || optimize_size || count < 64))
12071 countreg = copy_to_mode_reg (SImode,
12072 GEN_INT ((count >> 2)
12074 emit_insn (gen_rep_movsi (destreg, srcreg, countreg,
12075 destreg, srcreg, countreg));
12078 emit_insn (gen_strmovhi (destreg, srcreg));
12080 emit_insn (gen_strmovqi (destreg, srcreg));
12082 /* The generic code based on the glibc implementation:
12083 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
12084 allowing accelerated copying there)
12085 - copy the data using rep movsl
12086 - copy the rest. */
12092 /* In case we don't know anything about the alignment, default to
12093 library version, since it is usually equally fast and result in
12095 if (!TARGET_INLINE_ALL_STRINGOPS && align < 4)
12101 if (TARGET_SINGLE_STRINGOP)
12102 emit_insn (gen_cld ());
12104 countreg2 = gen_reg_rtx (SImode);
12105 countreg = copy_to_mode_reg (SImode, operands[2]);
12107 /* We don't use loops to align destination and to copy parts smaller
12108 than 4 bytes, because gcc is able to optimize such code better (in
12109 the case the destination or the count really is aligned, gcc is often
12110 able to predict the branches) and also it is friendlier to the
12111 hardware branch prediction.
12113 Using loops is benefical for generic case, because we can
12114 handle small counts using the loops. Many CPUs (such as Athlon)
12115 have large REP prefix setup costs.
12117 This is quite costy. Maybe we can revisit this decision later or
12118 add some customizability to this code. */
12121 && align < (TARGET_PENTIUMPRO && (count < 0 || count >= 260) ? 8 : 4))
12123 label = gen_label_rtx ();
12124 emit_cmp_and_jump_insns (countreg, GEN_INT (3),
12125 LEU, 0, SImode, 1, 0, label);
12129 rtx label = gen_label_rtx ();
12130 rtx tmpcount = gen_reg_rtx (SImode);
12131 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (1)));
12132 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12133 SImode, 1, 0, label);
12134 emit_insn (gen_strmovqi (destreg, srcreg));
12135 emit_insn (gen_addsi3 (countreg, countreg, constm1_rtx));
12136 emit_label (label);
12137 LABEL_NUSES (label) = 1;
12141 rtx label = gen_label_rtx ();
12142 rtx tmpcount = gen_reg_rtx (SImode);
12143 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (2)));
12144 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12145 SImode, 1, 0, label);
12146 emit_insn (gen_strmovhi (destreg, srcreg));
12147 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-2)));
12148 emit_label (label);
12149 LABEL_NUSES (label) = 1;
12151 if (align <= 4 && TARGET_PENTIUMPRO && (count < 1 || count >= 260))
12153 rtx label = gen_label_rtx ();
12154 rtx tmpcount = gen_reg_rtx (SImode);
12155 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (4)));
12156 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12157 SImode, 1, 0, label);
12158 emit_insn (gen_strmovsi (destreg, srcreg));
12159 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-4)));
12160 emit_label (label);
12161 LABEL_NUSES (label) = 1;
12164 if (!TARGET_SINGLE_STRINGOP)
12165 emit_insn (gen_cld());
12166 emit_insn (gen_lshrsi3 (countreg2, countreg, GEN_INT (2)));
12167 emit_insn (gen_rep_movsi (destreg, srcreg, countreg2,
12168 destreg, srcreg, countreg2));
12172 emit_label (label);
12173 LABEL_NUSES (label) = 1;
12175 if (align > 2 && count > 0 && (count & 2))
12176 emit_insn (gen_strmovhi (destreg, srcreg));
12177 if (align <= 2 || count < 0)
12179 rtx label = gen_label_rtx ();
12180 rtx tmpcount = gen_reg_rtx (SImode);
12181 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (2)));
12182 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12183 SImode, 1, 0, label);
12184 emit_insn (gen_strmovhi (destreg, srcreg));
12185 emit_label (label);
12186 LABEL_NUSES (label) = 1;
12188 if (align > 1 && count > 0 && (count & 1))
12189 emit_insn (gen_strmovsi (destreg, srcreg));
12190 if (align <= 1 || count < 0)
12192 rtx label = gen_label_rtx ();
12193 rtx tmpcount = gen_reg_rtx (SImode);
12194 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (1)));
12195 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12196 SImode, 1, 0, label);
12197 emit_insn (gen_strmovqi (destreg, srcreg));
12198 emit_label (label);
12199 LABEL_NUSES (label) = 1;
12203 insns = get_insns ();
12206 ix86_set_move_mem_attrs (insns, operands[0], operands[1], destreg, srcreg);
12207 emit_insns (insns);
12211 ;; Most CPUs don't like single string operations
12212 ;; Handle this case here to simplify previous expander.
12214 (define_expand "strmovsi"
12215 [(set (match_dup 2)
12216 (mem:SI (match_operand:SI 1 "register_operand" "")))
12217 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
12219 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
12220 (clobber (reg:CC 17))])
12221 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
12222 (clobber (reg:CC 17))])]
12226 if (TARGET_SINGLE_STRINGOP || optimize_size)
12228 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
12233 operands[2] = gen_reg_rtx (SImode);
12236 (define_expand "strmovhi"
12237 [(set (match_dup 2)
12238 (mem:HI (match_operand:SI 1 "register_operand" "")))
12239 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
12241 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
12242 (clobber (reg:CC 17))])
12243 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
12244 (clobber (reg:CC 17))])]
12248 if (TARGET_SINGLE_STRINGOP || optimize_size)
12250 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
12255 operands[2] = gen_reg_rtx (HImode);
12258 (define_expand "strmovqi"
12259 [(set (match_dup 2)
12260 (mem:QI (match_operand:SI 1 "register_operand" "")))
12261 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
12263 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
12264 (clobber (reg:CC 17))])
12265 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
12266 (clobber (reg:CC 17))])]
12270 if (TARGET_SINGLE_STRINGOP || optimize_size)
12272 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
12277 operands[2] = gen_reg_rtx (QImode);
12280 (define_insn "strmovsi_1"
12281 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
12282 (mem:SI (match_operand:SI 3 "register_operand" "1")))
12283 (set (match_operand:SI 0 "register_operand" "=D")
12284 (plus:SI (match_dup 2)
12286 (set (match_operand:SI 1 "register_operand" "=S")
12287 (plus:SI (match_dup 3)
12290 "TARGET_SINGLE_STRINGOP || optimize_size"
12292 [(set_attr "type" "str")
12293 (set_attr "mode" "SI")
12294 (set_attr "memory" "both")])
12296 (define_insn "strmovhi_1"
12297 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
12298 (mem:HI (match_operand:SI 3 "register_operand" "1")))
12299 (set (match_operand:SI 0 "register_operand" "=D")
12300 (plus:SI (match_dup 2)
12302 (set (match_operand:SI 1 "register_operand" "=S")
12303 (plus:SI (match_dup 3)
12306 "TARGET_SINGLE_STRINGOP || optimize_size"
12308 [(set_attr "type" "str")
12309 (set_attr "memory" "both")
12310 (set_attr "mode" "HI")])
12312 (define_insn "strmovqi_1"
12313 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
12314 (mem:QI (match_operand:SI 3 "register_operand" "1")))
12315 (set (match_operand:SI 0 "register_operand" "=D")
12316 (plus:SI (match_dup 2)
12318 (set (match_operand:SI 1 "register_operand" "=S")
12319 (plus:SI (match_dup 3)
12322 "TARGET_SINGLE_STRINGOP || optimize_size"
12324 [(set_attr "type" "str")
12325 (set_attr "memory" "both")
12326 (set_attr "mode" "QI")])
12328 (define_insn "rep_movsi"
12329 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
12330 (set (match_operand:SI 0 "register_operand" "=D")
12331 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
12333 (match_operand:SI 3 "register_operand" "0")))
12334 (set (match_operand:SI 1 "register_operand" "=S")
12335 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
12336 (match_operand:SI 4 "register_operand" "1")))
12337 (set (mem:BLK (match_dup 3))
12338 (mem:BLK (match_dup 4)))
12339 (use (match_dup 5))
12342 "rep\;movsl|rep movsd"
12343 [(set_attr "type" "str")
12344 (set_attr "prefix_rep" "1")
12345 (set_attr "memory" "both")
12346 (set_attr "mode" "SI")])
12348 (define_insn "rep_movqi"
12349 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
12350 (set (match_operand:SI 0 "register_operand" "=D")
12351 (plus:SI (match_operand:SI 3 "register_operand" "0")
12352 (match_operand:SI 5 "register_operand" "2")))
12353 (set (match_operand:SI 1 "register_operand" "=S")
12354 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
12355 (set (mem:BLK (match_dup 3))
12356 (mem:BLK (match_dup 4)))
12357 (use (match_dup 5))
12360 "rep\;movsb|rep movsb"
12361 [(set_attr "type" "str")
12362 (set_attr "prefix_rep" "1")
12363 (set_attr "memory" "both")
12364 (set_attr "mode" "SI")])
12366 (define_expand "clrstrsi"
12367 [(use (match_operand:BLK 0 "memory_operand" ""))
12368 (use (match_operand:SI 1 "nonmemory_operand" ""))
12369 (use (match_operand:SI 2 "const_int_operand" ""))]
12373 /* See comments in movstr expanders. The code is mostly identical. */
12375 rtx destreg, zeroreg, countreg;
12382 if (GET_CODE (operands[2]) == CONST_INT)
12383 align = INTVAL (operands[2]);
12385 /* This simple hack avoids all inlining code and simplifies code bellow. */
12386 if (!TARGET_ALIGN_STRINGOPS)
12389 if (GET_CODE (operands[1]) == CONST_INT)
12390 count = INTVAL (operands[1]);
12392 destreg = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
12394 emit_insn (gen_cld ());
12396 /* When optimizing for size emit simple rep ; movsb instruction for
12397 counts not divisible by 4. */
12399 if ((!optimize || optimize_size)
12400 && (count < 0 || (count & 0x03)))
12402 countreg = copy_to_mode_reg (SImode, operands[1]);
12403 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
12404 emit_insn (gen_rep_stosqi (destreg, countreg, zeroreg,
12405 destreg, countreg));
12407 else if (count >= 0
12409 || (!TARGET_PENTIUMPRO && align >= 4)
12410 || optimize_size || count < 64))
12412 zeroreg = copy_to_mode_reg (SImode, const0_rtx);
12413 if (INTVAL (operands[1]) & ~0x03)
12415 countreg = copy_to_mode_reg (SImode,
12416 GEN_INT ((INTVAL (operands[1]) >> 2)
12418 emit_insn (gen_rep_stossi (destreg, countreg, zeroreg,
12419 destreg, countreg));
12421 if (INTVAL (operands[1]) & 0x02)
12422 emit_insn (gen_strsethi (destreg,
12423 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12424 if (INTVAL (operands[1]) & 0x01)
12425 emit_insn (gen_strsetqi (destreg,
12426 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12433 /* In case we don't know anything about the alignment, default to
12434 library version, since it is usually equally fast and result in
12436 if (!TARGET_INLINE_ALL_STRINGOPS && align < 4)
12442 if (TARGET_SINGLE_STRINGOP)
12443 emit_insn (gen_cld ());
12445 countreg2 = gen_reg_rtx (SImode);
12446 countreg = copy_to_mode_reg (SImode, operands[1]);
12447 zeroreg = copy_to_mode_reg (SImode, const0_rtx);
12450 && align < (TARGET_PENTIUMPRO && (count < 0 || count >= 260) ? 8 : 4))
12452 label = gen_label_rtx ();
12453 emit_cmp_and_jump_insns (countreg, GEN_INT (3),
12454 LEU, 0, SImode, 1, 0, label);
12458 rtx label = gen_label_rtx ();
12459 rtx tmpcount = gen_reg_rtx (SImode);
12460 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (1)));
12461 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12462 SImode, 1, 0, label);
12463 emit_insn (gen_strsetqi (destreg,
12464 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12465 emit_insn (gen_addsi3 (countreg, countreg, constm1_rtx));
12466 emit_label (label);
12467 LABEL_NUSES (label) = 1;
12471 rtx label = gen_label_rtx ();
12472 rtx tmpcount = gen_reg_rtx (SImode);
12473 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (2)));
12474 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12475 SImode, 1, 0, label);
12476 emit_insn (gen_strsethi (destreg,
12477 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12478 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-2)));
12479 emit_label (label);
12480 LABEL_NUSES (label) = 1;
12482 if (align <= 4 && TARGET_PENTIUMPRO && (count < 1 || count >= 260))
12484 rtx label = gen_label_rtx ();
12485 rtx tmpcount = gen_reg_rtx (SImode);
12486 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (4)));
12487 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12488 SImode, 1, 0, label);
12489 emit_insn (gen_strsetsi (destreg, zeroreg));
12490 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-4)));
12491 emit_label (label);
12492 LABEL_NUSES (label) = 1;
12495 if (!TARGET_SINGLE_STRINGOP)
12496 emit_insn (gen_cld());
12497 emit_insn (gen_lshrsi3 (countreg2, countreg, GEN_INT (2)));
12498 emit_insn (gen_rep_stossi (destreg, countreg2, zeroreg,
12499 destreg, countreg2));
12503 emit_label (label);
12504 LABEL_NUSES (label) = 1;
12506 if (align > 2 && count > 0 && (count & 2))
12507 emit_insn (gen_strsethi (destreg,
12508 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12509 if (align <= 2 || count < 0)
12511 rtx label = gen_label_rtx ();
12512 rtx tmpcount = gen_reg_rtx (SImode);
12513 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (2)));
12514 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12515 SImode, 1, 0, label);
12516 emit_insn (gen_strsethi (destreg,
12517 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12518 emit_label (label);
12519 LABEL_NUSES (label) = 1;
12521 if (align > 1 && count > 0 && (count & 1))
12522 emit_insn (gen_strsetqi (destreg,
12523 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12524 if (align <= 1 || count < 0)
12526 rtx label = gen_label_rtx ();
12527 rtx tmpcount = gen_reg_rtx (SImode);
12528 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (1)));
12529 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
12530 SImode, 1, 0, label);
12531 emit_insn (gen_strsetqi (destreg,
12532 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12533 emit_label (label);
12534 LABEL_NUSES (label) = 1;
12538 insns = get_insns ();
12541 ix86_set_move_mem_attrs (insns, operands[0], operands[0], destreg, destreg);
12542 emit_insns (insns);
12547 ;; Most CPUs don't like single string operations
12548 ;; Handle this case here to simplify previous expander.
12550 (define_expand "strsetsi"
12551 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
12552 (match_operand:SI 1 "register_operand" ""))
12553 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
12554 (clobber (reg:CC 17))])]
12558 if (TARGET_SINGLE_STRINGOP || optimize_size)
12560 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
12565 (define_expand "strsethi"
12566 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
12567 (match_operand:HI 1 "register_operand" ""))
12568 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
12569 (clobber (reg:CC 17))])]
12573 if (TARGET_SINGLE_STRINGOP || optimize_size)
12575 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
12580 (define_expand "strsetqi"
12581 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
12582 (match_operand:QI 1 "register_operand" ""))
12583 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
12584 (clobber (reg:CC 17))])]
12588 if (TARGET_SINGLE_STRINGOP || optimize_size)
12590 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
12595 (define_insn "strsetsi_1"
12596 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
12597 (match_operand:SI 2 "register_operand" "a"))
12598 (set (match_operand:SI 0 "register_operand" "=D")
12599 (plus:SI (match_dup 1)
12602 "TARGET_SINGLE_STRINGOP || optimize_size"
12604 [(set_attr "type" "str")
12605 (set_attr "memory" "store")
12606 (set_attr "mode" "SI")])
12608 (define_insn "strsethi_1"
12609 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
12610 (match_operand:HI 2 "register_operand" "a"))
12611 (set (match_operand:SI 0 "register_operand" "=D")
12612 (plus:SI (match_dup 1)
12615 "TARGET_SINGLE_STRINGOP || optimize_size"
12617 [(set_attr "type" "str")
12618 (set_attr "memory" "store")
12619 (set_attr "mode" "HI")])
12621 (define_insn "strsetqi_1"
12622 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
12623 (match_operand:QI 2 "register_operand" "a"))
12624 (set (match_operand:SI 0 "register_operand" "=D")
12625 (plus:SI (match_dup 1)
12628 "TARGET_SINGLE_STRINGOP || optimize_size"
12630 [(set_attr "type" "str")
12631 (set_attr "memory" "store")
12632 (set_attr "mode" "QI")])
12634 (define_insn "rep_stossi"
12635 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
12636 (set (match_operand:SI 0 "register_operand" "=D")
12637 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
12639 (match_operand:SI 3 "register_operand" "0")))
12640 (set (mem:BLK (match_dup 3))
12642 (use (match_operand:SI 2 "register_operand" "a"))
12643 (use (match_dup 4))
12646 "rep\;stosl|rep stosd"
12647 [(set_attr "type" "str")
12648 (set_attr "prefix_rep" "1")
12649 (set_attr "memory" "store")
12650 (set_attr "mode" "SI")])
12652 (define_insn "rep_stosqi"
12653 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
12654 (set (match_operand:SI 0 "register_operand" "=D")
12655 (plus:SI (match_operand:SI 3 "register_operand" "0")
12656 (match_operand:SI 4 "register_operand" "1")))
12657 (set (mem:BLK (match_dup 3))
12659 (use (match_operand:QI 2 "register_operand" "a"))
12660 (use (match_dup 4))
12663 "rep\;stosb|rep stosb"
12664 [(set_attr "type" "str")
12665 (set_attr "prefix_rep" "1")
12666 (set_attr "memory" "store")
12667 (set_attr "mode" "QI")])
12669 (define_expand "cmpstrsi"
12670 [(set (match_operand:SI 0 "register_operand" "")
12671 (compare:SI (match_operand:BLK 1 "general_operand" "")
12672 (match_operand:BLK 2 "general_operand" "")))
12673 (use (match_operand:SI 3 "general_operand" ""))
12674 (use (match_operand:SI 4 "immediate_operand" ""))]
12678 rtx addr1, addr2, out, outlow, count, countreg, align;
12681 if (GET_CODE (out) != REG)
12682 out = gen_reg_rtx (SImode);
12684 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
12685 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
12687 count = operands[3];
12688 countreg = copy_to_mode_reg (SImode, count);
12690 /* %%% Iff we are testing strict equality, we can use known alignment
12691 to good advantage. This may be possible with combine, particularly
12692 once cc0 is dead. */
12693 align = operands[4];
12695 emit_insn (gen_cld ());
12696 if (GET_CODE (count) == CONST_INT)
12698 if (INTVAL (count) == 0)
12700 emit_move_insn (operands[0], const0_rtx);
12703 emit_insn (gen_cmpstrsi_nz_1 (addr1, addr2, countreg, align,
12704 addr1, addr2, countreg));
12708 emit_insn (gen_cmpsi_1 (countreg, countreg));
12709 emit_insn (gen_cmpstrsi_1 (addr1, addr2, countreg, align,
12710 addr1, addr2, countreg));
12713 outlow = gen_lowpart (QImode, out);
12714 emit_insn (gen_cmpintqi (outlow));
12715 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
12717 if (operands[0] != out)
12718 emit_move_insn (operands[0], out);
12723 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
12725 (define_expand "cmpintqi"
12726 [(set (match_dup 1)
12727 (gtu:QI (reg:CC 17) (const_int 0)))
12729 (ltu:QI (reg:CC 17) (const_int 0)))
12730 (parallel [(set (match_operand:QI 0 "register_operand" "")
12731 (minus:QI (match_dup 1)
12733 (clobber (reg:CC 17))])]
12735 "operands[1] = gen_reg_rtx (QImode);
12736 operands[2] = gen_reg_rtx (QImode);")
12738 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
12739 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
12741 (define_insn "cmpstrsi_nz_1"
12743 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
12744 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
12745 (use (match_operand:SI 6 "register_operand" "2"))
12746 (use (match_operand:SI 3 "immediate_operand" "i"))
12748 (clobber (match_operand:SI 0 "register_operand" "=S"))
12749 (clobber (match_operand:SI 1 "register_operand" "=D"))
12750 (clobber (match_operand:SI 2 "register_operand" "=c"))]
12753 [(set_attr "type" "str")
12754 (set_attr "mode" "QI")
12755 (set_attr "prefix_rep" "1")])
12757 ;; The same, but the count is not known to not be zero.
12759 (define_insn "cmpstrsi_1"
12761 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
12763 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
12764 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
12766 (use (match_operand:SI 3 "immediate_operand" "i"))
12769 (clobber (match_operand:SI 0 "register_operand" "=S"))
12770 (clobber (match_operand:SI 1 "register_operand" "=D"))
12771 (clobber (match_operand:SI 2 "register_operand" "=c"))]
12774 [(set_attr "type" "str")
12775 (set_attr "mode" "QI")
12776 (set_attr "prefix_rep" "1")])
12778 (define_expand "strlensi"
12779 [(set (match_operand:SI 0 "register_operand" "")
12780 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
12781 (match_operand:QI 2 "immediate_operand" "")
12782 (match_operand:SI 3 "immediate_operand" "")] 0))]
12786 rtx out, addr, scratch1, scratch2, scratch3;
12787 rtx eoschar = operands[2];
12788 rtx align = operands[3];
12790 /* The generic case of strlen expander is long. Avoid it's
12791 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
12793 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12794 && !TARGET_INLINE_ALL_STRINGOPS
12796 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
12800 addr = force_reg (Pmode, XEXP (operands[1], 0));
12801 scratch1 = gen_reg_rtx (SImode);
12803 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12806 /* Well it seems that some optimizer does not combine a call like
12807 foo(strlen(bar), strlen(bar));
12808 when the move and the subtraction is done here. It does calculate
12809 the length just once when these instructions are done inside of
12810 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
12811 often used and I use one fewer register for the lifetime of
12812 output_strlen_unroll() this is better. */
12814 if (GET_CODE (align) != CONST_INT || INTVAL (align) < 4)
12815 emit_move_insn (scratch1, addr);
12817 emit_move_insn (out, addr);
12819 ix86_expand_strlensi_unroll_1 (out, align, scratch1);
12821 /* strlensi_unroll_1 returns the address of the zero at the end of
12822 the string, like memchr(), so compute the length by subtracting
12823 the start address. */
12824 emit_insn (gen_subsi3 (out, out, addr));
12828 scratch2 = gen_reg_rtx (SImode);
12829 scratch3 = gen_reg_rtx (SImode);
12831 emit_move_insn (scratch3, addr);
12833 emit_insn (gen_cld ());
12834 emit_insn (gen_strlensi_1 (scratch1, scratch3, eoschar,
12835 align, constm1_rtx, scratch3));
12836 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
12837 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
12842 (define_insn "strlensi_1"
12843 [(set (match_operand:SI 0 "register_operand" "=&c")
12844 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
12845 (match_operand:QI 2 "general_operand" "a")
12846 (match_operand:SI 3 "immediate_operand" "i")
12847 (match_operand:SI 4 "immediate_operand" "0")] 0))
12849 (clobber (match_operand:SI 1 "register_operand" "=D"))
12850 (clobber (reg:CC 17))]
12853 [(set_attr "type" "str")
12854 (set_attr "mode" "QI")
12855 (set_attr "prefix_rep" "1")])
12857 ;; Conditional move instructions.
12859 (define_expand "movsicc"
12860 [(set (match_operand:SI 0 "register_operand" "")
12861 (if_then_else:SI (match_operand 1 "comparison_operator" "")
12862 (match_operand:SI 2 "general_operand" "")
12863 (match_operand:SI 3 "general_operand" "")))]
12865 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
12867 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
12868 ;; the register first winds up with `sbbl $0,reg', which is also weird.
12869 ;; So just document what we're doing explicitly.
12871 (define_insn "x86_movsicc_0_m1"
12872 [(set (match_operand:SI 0 "register_operand" "=r")
12873 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
12876 (clobber (reg:CC 17))]
12879 ; Since we don't have the proper number of operands for an alu insn,
12880 ; fill in all the blanks.
12881 [(set_attr "type" "alu")
12882 (set_attr "memory" "none")
12883 (set_attr "imm_disp" "false")
12884 (set_attr "mode" "SI")
12885 (set_attr "length_immediate" "0")])
12887 (define_insn "*movsicc_noc"
12888 [(set (match_operand:SI 0 "register_operand" "=r,r")
12889 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
12890 [(reg 17) (const_int 0)])
12891 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
12892 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
12894 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12896 cmov%C1\\t{%2, %0|%0, %2}
12897 cmov%c1\\t{%3, %0|%0, %3}"
12898 [(set_attr "type" "icmov")
12899 (set_attr "mode" "SI")])
12901 (define_expand "movhicc"
12902 [(set (match_operand:HI 0 "register_operand" "")
12903 (if_then_else:HI (match_operand 1 "comparison_operator" "")
12904 (match_operand:HI 2 "nonimmediate_operand" "")
12905 (match_operand:HI 3 "nonimmediate_operand" "")))]
12906 "TARGET_CMOVE && TARGET_HIMODE_MATH"
12907 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
12909 (define_insn "*movhicc_noc"
12910 [(set (match_operand:HI 0 "register_operand" "=r,r")
12911 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
12912 [(reg 17) (const_int 0)])
12913 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
12914 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
12916 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12918 cmov%C1\\t{%2, %0|%0, %2}
12919 cmov%c1\\t{%3, %0|%0, %3}"
12920 [(set_attr "type" "icmov")
12921 (set_attr "mode" "HI")])
12923 (define_expand "movsfcc"
12924 [(set (match_operand:SF 0 "register_operand" "")
12925 (if_then_else:SF (match_operand 1 "comparison_operator" "")
12926 (match_operand:SF 2 "register_operand" "")
12927 (match_operand:SF 3 "register_operand" "")))]
12929 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
12931 (define_insn "*movsfcc_1"
12932 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
12933 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
12934 [(reg 17) (const_int 0)])
12935 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
12936 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
12938 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12940 fcmov%F1\\t{%2, %0|%0, %2}
12941 fcmov%f1\\t{%3, %0|%0, %3}
12942 cmov%C1\\t{%2, %0|%0, %2}
12943 cmov%c1\\t{%3, %0|%0, %3}"
12944 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
12945 (set_attr "mode" "SF,SF,SI,SI")])
12947 (define_expand "movdfcc"
12948 [(set (match_operand:DF 0 "register_operand" "")
12949 (if_then_else:DF (match_operand 1 "comparison_operator" "")
12950 (match_operand:DF 2 "register_operand" "")
12951 (match_operand:DF 3 "register_operand" "")))]
12953 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
12955 (define_insn "*movdfcc_1"
12956 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
12957 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
12958 [(reg 17) (const_int 0)])
12959 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
12960 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
12961 "TARGET_CMOVE && !TARGET_64BIT
12962 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12964 fcmov%F1\\t{%2, %0|%0, %2}
12965 fcmov%f1\\t{%3, %0|%0, %3}
12968 [(set_attr "type" "fcmov,fcmov,multi,multi")
12969 (set_attr "mode" "DF")])
12971 (define_insn "*movdfcc_1_rex64"
12972 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
12973 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
12974 [(reg 17) (const_int 0)])
12975 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
12976 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
12977 "TARGET_CMOVE && TARGET_64BIT
12978 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12980 fcmov%F1\\t{%2, %0|%0, %2}
12981 fcmov%f1\\t{%3, %0|%0, %3}
12982 cmov%C1\\t{%2, %0|%0, %2}
12983 cmov%c1\\t{%3, %0|%0, %3}"
12984 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
12985 (set_attr "mode" "DF")])
12988 [(set (match_operand:DF 0 "register_operand" "")
12989 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
12990 [(match_operand 4 "" "") (const_int 0)])
12991 (match_operand:DF 2 "nonimmediate_operand" "")
12992 (match_operand:DF 3 "nonimmediate_operand" "")))]
12993 "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
12994 [(set (match_dup 2)
12995 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
12999 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
13002 "split_di (operands+2, 1, operands+5, operands+6);
13003 split_di (operands+3, 1, operands+7, operands+8);
13004 split_di (operands, 1, operands+2, operands+3);")
13006 (define_expand "movxfcc"
13007 [(set (match_operand:XF 0 "register_operand" "")
13008 (if_then_else:XF (match_operand 1 "comparison_operator" "")
13009 (match_operand:XF 2 "register_operand" "")
13010 (match_operand:XF 3 "register_operand" "")))]
13011 "TARGET_CMOVE && !TARGET_64BIT"
13012 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
13014 (define_expand "movtfcc"
13015 [(set (match_operand:TF 0 "register_operand" "")
13016 (if_then_else:TF (match_operand 1 "comparison_operator" "")
13017 (match_operand:TF 2 "register_operand" "")
13018 (match_operand:TF 3 "register_operand" "")))]
13020 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
13022 (define_insn "*movxfcc_1"
13023 [(set (match_operand:XF 0 "register_operand" "=f,f")
13024 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
13025 [(reg 17) (const_int 0)])
13026 (match_operand:XF 2 "register_operand" "f,0")
13027 (match_operand:XF 3 "register_operand" "0,f")))]
13028 "TARGET_CMOVE && !TARGET_64BIT"
13030 fcmov%F1\\t{%2, %0|%0, %2}
13031 fcmov%f1\\t{%3, %0|%0, %3}"
13032 [(set_attr "type" "fcmov")
13033 (set_attr "mode" "XF")])
13035 (define_insn "*movtfcc_1"
13036 [(set (match_operand:TF 0 "register_operand" "=f,f")
13037 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
13038 [(reg 17) (const_int 0)])
13039 (match_operand:TF 2 "register_operand" "f,0")
13040 (match_operand:TF 3 "register_operand" "0,f")))]
13043 fcmov%F1\\t{%2, %0|%0, %2}
13044 fcmov%f1\\t{%3, %0|%0, %3}"
13045 [(set_attr "type" "fcmov")
13046 (set_attr "mode" "XF")])
13048 (define_expand "minsf3"
13050 (set (match_operand:SF 0 "register_operand" "")
13051 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
13052 (match_operand:SF 2 "nonimmediate_operand" ""))
13055 (clobber (reg:CC 17))])]
13059 (define_insn "*minsf"
13060 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
13061 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
13062 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
13065 (clobber (reg:CC 17))]
13066 "TARGET_SSE && TARGET_IEEE_FP"
13069 (define_insn "*minsf_nonieee"
13070 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
13071 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
13072 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
13075 (clobber (reg:CC 17))]
13076 "TARGET_SSE && !TARGET_IEEE_FP"
13080 [(set (match_operand:SF 0 "register_operand" "")
13081 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
13082 (match_operand:SF 2 "nonimmediate_operand" ""))
13085 (clobber (reg:CC 17))]
13086 "SSE_REG_P (operands[0]) && reload_completed"
13087 [(set (match_dup 0)
13088 (if_then_else:SF (lt (match_dup 1)
13093 ;; We can't represent the LT test directly. Do this by swapping the operands.
13095 [(set (match_operand:SF 0 "register_operand" "")
13096 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
13097 (match_operand:SF 2 "register_operand" ""))
13100 (clobber (reg:CC 17))]
13101 "FP_REG_P (operands[0]) && reload_completed"
13102 [(set (reg:CCFP 17)
13103 (compare:CCFP (match_dup 2)
13106 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
13110 (define_insn "*minsf_sse"
13111 [(set (match_operand:SF 0 "register_operand" "=x")
13112 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
13113 (match_operand:SF 2 "nonimmediate_operand" "xm"))
13116 "TARGET_SSE && reload_completed"
13117 "minss\\t{%2, %0|%0, %2}"
13118 [(set_attr "type" "sse")
13119 (set_attr "mode" "SF")])
13121 (define_expand "mindf3"
13123 (set (match_operand:DF 0 "register_operand" "")
13124 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
13125 (match_operand:DF 2 "nonimmediate_operand" ""))
13128 (clobber (reg:CC 17))])]
13132 (define_insn "*mindf"
13133 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
13134 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
13135 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
13138 (clobber (reg:CC 17))]
13139 "TARGET_SSE2 && TARGET_IEEE_FP"
13142 (define_insn "*mindf_nonieee"
13143 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
13144 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
13145 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
13148 (clobber (reg:CC 17))]
13149 "TARGET_SSE2 && !TARGET_IEEE_FP"
13153 [(set (match_operand:DF 0 "register_operand" "")
13154 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
13155 (match_operand:DF 2 "nonimmediate_operand" ""))
13158 (clobber (reg:CC 17))]
13159 "SSE_REG_P (operands[0]) && reload_completed"
13160 [(set (match_dup 0)
13161 (if_then_else:DF (lt (match_dup 1)
13166 ;; We can't represent the LT test directly. Do this by swapping the operands.
13168 [(set (match_operand:DF 0 "register_operand" "")
13169 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
13170 (match_operand:DF 2 "register_operand" ""))
13173 (clobber (reg:CC 17))]
13174 "FP_REG_P (operands[0]) && reload_completed"
13175 [(set (reg:CCFP 17)
13176 (compare:CCFP (match_dup 2)
13179 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
13183 (define_insn "*mindf_sse"
13184 [(set (match_operand:DF 0 "register_operand" "=Y")
13185 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
13186 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
13189 "TARGET_SSE2 && reload_completed"
13190 "minsd\\t{%2, %0|%0, %2}"
13191 [(set_attr "type" "sse")
13192 (set_attr "mode" "DF")])
13194 (define_expand "maxsf3"
13196 (set (match_operand:SF 0 "register_operand" "")
13197 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
13198 (match_operand:SF 2 "nonimmediate_operand" ""))
13201 (clobber (reg:CC 17))])]
13205 (define_insn "*maxsf"
13206 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
13207 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
13208 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
13211 (clobber (reg:CC 17))]
13212 "TARGET_SSE && TARGET_IEEE_FP"
13215 (define_insn "*maxsf_nonieee"
13216 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
13217 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
13218 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
13221 (clobber (reg:CC 17))]
13222 "TARGET_SSE && !TARGET_IEEE_FP"
13226 [(set (match_operand:SF 0 "register_operand" "")
13227 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
13228 (match_operand:SF 2 "nonimmediate_operand" ""))
13231 (clobber (reg:CC 17))]
13232 "SSE_REG_P (operands[0]) && reload_completed"
13233 [(set (match_dup 0)
13234 (if_then_else:SF (gt (match_dup 1)
13240 [(set (match_operand:SF 0 "register_operand" "")
13241 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
13242 (match_operand:SF 2 "register_operand" ""))
13245 (clobber (reg:CC 17))]
13246 "FP_REG_P (operands[0]) && reload_completed"
13247 [(set (reg:CCFP 17)
13248 (compare:CCFP (match_dup 1)
13251 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
13255 (define_insn "*maxsf_sse"
13256 [(set (match_operand:SF 0 "register_operand" "=x")
13257 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
13258 (match_operand:SF 2 "nonimmediate_operand" "xm"))
13261 "TARGET_SSE && reload_completed"
13262 "maxss\\t{%2, %0|%0, %2}"
13263 [(set_attr "type" "sse")
13264 (set_attr "mode" "SF")])
13266 (define_expand "maxdf3"
13268 (set (match_operand:DF 0 "register_operand" "")
13269 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
13270 (match_operand:DF 2 "nonimmediate_operand" ""))
13273 (clobber (reg:CC 17))])]
13277 (define_insn "*maxdf"
13278 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
13279 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
13280 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
13283 (clobber (reg:CC 17))]
13284 "TARGET_SSE2 && TARGET_IEEE_FP"
13287 (define_insn "*maxdf_nonieee"
13288 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
13289 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
13290 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
13293 (clobber (reg:CC 17))]
13294 "TARGET_SSE2 && !TARGET_IEEE_FP"
13298 [(set (match_operand:DF 0 "register_operand" "")
13299 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
13300 (match_operand:DF 2 "nonimmediate_operand" ""))
13303 (clobber (reg:CC 17))]
13304 "SSE_REG_P (operands[0]) && reload_completed"
13305 [(set (match_dup 0)
13306 (if_then_else:DF (gt (match_dup 1)
13312 [(set (match_operand:DF 0 "register_operand" "")
13313 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
13314 (match_operand:DF 2 "register_operand" ""))
13317 (clobber (reg:CC 17))]
13318 "FP_REG_P (operands[0]) && reload_completed"
13319 [(set (reg:CCFP 17)
13320 (compare:CCFP (match_dup 1)
13323 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
13327 (define_insn "*maxdf_sse"
13328 [(set (match_operand:DF 0 "register_operand" "=Y")
13329 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
13330 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
13333 "TARGET_SSE2 && reload_completed"
13334 "maxsd\\t{%2, %0|%0, %2}"
13335 [(set_attr "type" "sse")
13336 (set_attr "mode" "DF")])
13338 ;; Misc patterns (?)
13340 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
13341 ;; Otherwise there will be nothing to keep
13343 ;; [(set (reg ebp) (reg esp))]
13344 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
13345 ;; (clobber (eflags)]
13346 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
13348 ;; in proper program order.
13350 (define_insn "pro_epilogue_adjust_stack"
13351 [(set (match_operand:SI 0 "register_operand" "=r,r")
13352 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
13353 (match_operand:SI 2 "immediate_operand" "i,i")))
13354 (set (match_operand:SI 3 "register_operand" "+r,r")
13356 (clobber (reg:CC 17))]
13360 switch (get_attr_type (insn))
13363 return \"mov{l}\\t{%1, %0|%0, %1}\";
13366 if (GET_CODE (operands[2]) == CONST_INT
13367 && (INTVAL (operands[2]) == 128
13368 || (INTVAL (operands[2]) < 0
13369 && INTVAL (operands[2]) != -128)))
13371 operands[2] = GEN_INT (-INTVAL (operands[2]));
13372 return \"sub{l}\\t{%2, %0|%0, %2}\";
13374 return \"add{l}\\t{%2, %0|%0, %2}\";
13377 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
13378 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
13384 [(set (attr "type")
13385 (cond [(eq_attr "alternative" "0")
13386 (const_string "alu")
13387 (match_operand:SI 2 "const0_operand" "")
13388 (const_string "imov")
13390 (const_string "lea")))
13391 (set_attr "mode" "SI")])
13393 ;; Placeholder for the conditional moves. This one is split eighter to SSE
13394 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
13395 ;; fact is that compares supported by the cmp??ss instructions are exactly
13396 ;; swapped of those supported by cmove sequence.
13397 ;; The EQ/NE comparisons also needs bit care, since they are not directly
13398 ;; supported by i387 comparisons and we do need to emit two conditional moves
13401 (define_insn "sse_movsfcc"
13402 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
13403 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
13404 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
13405 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
13406 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
13407 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
13408 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
13409 (clobber (reg:CC 17))]
13411 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
13412 && (!TARGET_IEEE_FP
13413 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
13416 (define_insn "sse_movsfcc_eq"
13417 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
13418 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
13419 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
13420 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
13421 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
13422 (clobber (match_scratch:SF 5 "=1,&4,X,X,X,X"))
13423 (clobber (reg:CC 17))]
13425 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
13428 (define_insn "sse_movdfcc"
13429 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
13430 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
13431 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
13432 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
13433 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
13434 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
13435 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
13436 (clobber (reg:CC 17))]
13438 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
13439 && (!TARGET_IEEE_FP
13440 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
13443 (define_insn "sse_movdfcc_eq"
13444 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
13445 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
13446 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
13447 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
13448 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
13449 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
13450 (clobber (reg:CC 17))]
13452 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
13455 ;; For non-sse moves just expand the usual cmove sequence.
13457 [(set (match_operand 0 "register_operand" "")
13458 (if_then_else (match_operator 1 "comparison_operator"
13459 [(match_operand 4 "nonimmediate_operand" "")
13460 (match_operand 5 "register_operand" "")])
13461 (match_operand 2 "nonimmediate_operand" "")
13462 (match_operand 3 "nonimmediate_operand" "")))
13463 (clobber (match_operand 6 "" ""))
13464 (clobber (reg:CC 17))]
13465 "!SSE_REG_P (operands[0]) && reload_completed
13466 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
13470 ix86_compare_op0 = operands[5];
13471 ix86_compare_op1 = operands[4];
13472 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
13473 VOIDmode, operands[5], operands[4]);
13474 ix86_expand_fp_movcc (operands);
13478 ;; Split SSE based conditional move into seqence:
13479 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
13480 ;; and op2, op0 - zero op2 if comparison was false
13481 ;; nand op0, op3 - load op3 to op0 if comparison was false
13482 ;; or op2, op0 - get the non-zero one into the result.
13484 [(set (match_operand 0 "register_operand" "")
13485 (if_then_else (match_operator 1 "sse_comparison_operator"
13486 [(match_operand 4 "register_operand" "")
13487 (match_operand 5 "nonimmediate_operand" "")])
13488 (match_operand 2 "register_operand" "")
13489 (match_operand 3 "register_operand" "")))
13490 (clobber (match_operand 6 "" ""))
13491 (clobber (reg:CC 17))]
13492 "SSE_REG_P (operands[0]) && reload_completed"
13493 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
13494 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
13495 (subreg:TI (match_dup 0) 0)))
13496 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 0) 0))
13497 (subreg:TI (match_dup 3) 0)))
13498 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
13499 (subreg:TI (match_dup 7) 0)))]
13502 PUT_MODE (operands[1], GET_MODE (operands[0]));
13503 if (rtx_equal_p (operands[0], operands[4]))
13504 operands[6] = operands[4], operands[7] = operands[2];
13506 operands[6] = operands[2], operands[7] = operands[0];
13509 ;; Special case of conditional move we can handle effectivly.
13510 ;; Do not brother with the integer/floating point case, since these are
13511 ;; bot considerably slower, unlike in the generic case.
13512 (define_insn "*sse_movsfcc_const0_1"
13513 [(set (match_operand:SF 0 "register_operand" "=x")
13514 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
13515 [(match_operand:SF 4 "register_operand" "0")
13516 (match_operand:SF 5 "nonimmediate_operand" "xm")])
13517 (match_operand:SF 2 "register_operand" "x")
13518 (match_operand:SF 3 "const0_operand" "X")))]
13522 (define_insn "*sse_movsfcc_const0_2"
13523 [(set (match_operand:SF 0 "register_operand" "=x")
13524 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
13525 [(match_operand:SF 4 "register_operand" "0")
13526 (match_operand:SF 5 "nonimmediate_operand" "xm")])
13527 (match_operand:SF 2 "const0_operand" "x")
13528 (match_operand:SF 3 "register_operand" "X")))]
13532 (define_insn "*sse_movsfcc_const0_3"
13533 [(set (match_operand:SF 0 "register_operand" "=x")
13534 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
13535 [(match_operand:SF 4 "nonimmediate_operand" "xm")
13536 (match_operand:SF 5 "register_operand" "0")])
13537 (match_operand:SF 2 "register_operand" "x")
13538 (match_operand:SF 3 "const0_operand" "X")))]
13542 (define_insn "*sse_movsfcc_const0_4"
13543 [(set (match_operand:SF 0 "register_operand" "=x")
13544 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
13545 [(match_operand:SF 4 "nonimmediate_operand" "xm")
13546 (match_operand:SF 5 "register_operand" "0")])
13547 (match_operand:SF 2 "const0_operand" "x")
13548 (match_operand:SF 3 "register_operand" "X")))]
13552 (define_insn "*sse_movdfcc_const0_1"
13553 [(set (match_operand:SF 0 "register_operand" "=x")
13554 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
13555 [(match_operand:SF 4 "register_operand" "0")
13556 (match_operand:SF 5 "nonimmediate_operand" "xm")])
13557 (match_operand:SF 2 "register_operand" "x")
13558 (match_operand:SF 3 "const0_operand" "X")))]
13562 (define_insn "*sse_movdfcc_const0_2"
13563 [(set (match_operand:SF 0 "register_operand" "=x")
13564 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
13565 [(match_operand:SF 4 "register_operand" "0")
13566 (match_operand:SF 5 "nonimmediate_operand" "xm")])
13567 (match_operand:SF 2 "const0_operand" "x")
13568 (match_operand:SF 3 "register_operand" "X")))]
13572 (define_insn "*sse_movdfcc_const0_3"
13573 [(set (match_operand:SF 0 "register_operand" "=x")
13574 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
13575 [(match_operand:SF 4 "nonimmediate_operand" "xm")
13576 (match_operand:SF 5 "register_operand" "0")])
13577 (match_operand:SF 2 "register_operand" "x")
13578 (match_operand:SF 3 "const0_operand" "X")))]
13582 (define_insn "*sse_movdfcc_const0_4"
13583 [(set (match_operand:SF 0 "register_operand" "=x")
13584 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
13585 [(match_operand:SF 4 "nonimmediate_operand" "xm")
13586 (match_operand:SF 5 "register_operand" "0")])
13587 (match_operand:SF 2 "const0_operand" "x")
13588 (match_operand:SF 3 "register_operand" "X")))]
13593 [(set (match_operand 0 "register_operand" "")
13594 (if_then_else (match_operator 1 "comparison_operator"
13595 [(match_operand 4 "register_operand" "")
13596 (match_operand 5 "nonimmediate_operand" "")])
13597 (match_operand 2 "nonmemory_operand" "")
13598 (match_operand 3 "nonmemory_operand" "")))]
13599 "SSE_REG_P (operands[0]) && reload_completed
13600 && (const0_operand (operands[2], GET_MODE (operands[0]))
13601 || const0_operand (operands[3], GET_MODE (operands[0])))"
13602 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
13603 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
13604 (subreg:TI (match_dup 7) 0)))]
13607 PUT_MODE (operands[1], GET_MODE (operands[0]));
13608 if (!sse_comparison_operator (operands[1], VOIDmode))
13610 rtx tmp = operands[5];
13611 operands[5] = operands[4];
13613 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
13615 if (const0_operand (operands[2], GET_MODE (operands[0])))
13617 operands[7] = operands[3];
13618 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
13623 operands[7] = operands[2];
13624 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
13628 (define_insn "allocate_stack_worker"
13629 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
13630 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
13631 (clobber (match_dup 0))
13632 (clobber (reg:CC 17))]
13633 "TARGET_STACK_PROBE"
13635 [(set_attr "type" "multi")
13636 (set_attr "length" "5")])
13638 (define_expand "allocate_stack"
13639 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
13640 (minus:SI (reg:SI 7)
13641 (match_operand:SI 1 "general_operand" "")))
13642 (clobber (reg:CC 17))])
13643 (parallel [(set (reg:SI 7)
13644 (minus:SI (reg:SI 7) (match_dup 1)))
13645 (clobber (reg:CC 17))])]
13646 "TARGET_STACK_PROBE"
13649 #ifdef CHECK_STACK_LIMIT
13650 if (GET_CODE (operands[1]) == CONST_INT
13651 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
13652 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
13656 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
13659 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
13663 (define_expand "exception_receiver"
13668 load_pic_register ();
13672 (define_expand "builtin_setjmp_receiver"
13673 [(label_ref (match_operand 0 "" ""))]
13677 load_pic_register ();
13681 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
13684 [(set (match_operand 0 "register_operand" "")
13685 (match_operator 3 "promotable_binary_operator"
13686 [(match_operand 1 "register_operand" "")
13687 (match_operand 2 "aligned_operand" "")]))
13688 (clobber (reg:CC 17))]
13689 "! TARGET_PARTIAL_REG_STALL && reload_completed
13690 && ((GET_MODE (operands[0]) == HImode
13691 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
13692 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
13693 || (GET_MODE (operands[0]) == QImode
13694 && (TARGET_PROMOTE_QImode || optimize_size)))"
13695 [(parallel [(set (match_dup 0)
13696 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
13697 (clobber (reg:CC 17))])]
13698 "operands[0] = gen_lowpart (SImode, operands[0]);
13699 operands[1] = gen_lowpart (SImode, operands[1]);
13700 if (GET_CODE (operands[3]) != ASHIFT)
13701 operands[2] = gen_lowpart (SImode, operands[2]);
13702 PUT_MODE (operands[3], SImode);")
13706 (compare (and (match_operand 1 "aligned_operand" "")
13707 (match_operand 2 "const_int_operand" ""))
13709 (set (match_operand 0 "register_operand" "")
13710 (and (match_dup 1) (match_dup 2)))]
13711 "! TARGET_PARTIAL_REG_STALL && reload_completed
13712 && ix86_match_ccmode (insn, CCNOmode)
13713 && (GET_MODE (operands[0]) == HImode
13714 || (GET_MODE (operands[0]) == QImode
13715 && (TARGET_PROMOTE_QImode || optimize_size)))"
13716 [(parallel [(set (reg:CCNO 17)
13717 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
13720 (and:SI (match_dup 1) (match_dup 2)))])]
13722 = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (GET_MODE (operands[0])));
13723 operands[0] = gen_lowpart (SImode, operands[0]);
13724 operands[1] = gen_lowpart (SImode, operands[1]);")
13728 (compare (and (match_operand 0 "aligned_operand" "")
13729 (match_operand 1 "const_int_operand" ""))
13731 "! TARGET_PARTIAL_REG_STALL && reload_completed
13732 && ix86_match_ccmode (insn, CCNOmode)
13733 && (GET_MODE (operands[0]) == HImode
13734 || (GET_MODE (operands[0]) == QImode
13735 && (TARGET_PROMOTE_QImode || optimize_size)))"
13736 [(set (reg:CCNO 17)
13737 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
13740 = GEN_INT (INTVAL (operands[1]) & GET_MODE_MASK (GET_MODE (operands[0])));
13741 operands[0] = gen_lowpart (SImode, operands[0]);")
13744 [(set (match_operand 0 "register_operand" "")
13745 (neg (match_operand 1 "register_operand" "")))
13746 (clobber (reg:CC 17))]
13747 "! TARGET_PARTIAL_REG_STALL && reload_completed
13748 && (GET_MODE (operands[0]) == HImode
13749 || (GET_MODE (operands[0]) == QImode
13750 && (TARGET_PROMOTE_QImode || optimize_size)))"
13751 [(parallel [(set (match_dup 0)
13752 (neg:SI (match_dup 1)))
13753 (clobber (reg:CC 17))])]
13754 "operands[0] = gen_lowpart (SImode, operands[0]);
13755 operands[1] = gen_lowpart (SImode, operands[1]);")
13758 [(set (match_operand 0 "register_operand" "")
13759 (not (match_operand 1 "register_operand" "")))]
13760 "! TARGET_PARTIAL_REG_STALL && reload_completed
13761 && (GET_MODE (operands[0]) == HImode
13762 || (GET_MODE (operands[0]) == QImode
13763 && (TARGET_PROMOTE_QImode || optimize_size)))"
13764 [(set (match_dup 0)
13765 (not:SI (match_dup 1)))]
13766 "operands[0] = gen_lowpart (SImode, operands[0]);
13767 operands[1] = gen_lowpart (SImode, operands[1]);")
13770 [(set (match_operand 0 "register_operand" "")
13771 (if_then_else (match_operator 1 "comparison_operator"
13772 [(reg 17) (const_int 0)])
13773 (match_operand 2 "register_operand" "")
13774 (match_operand 3 "register_operand" "")))]
13775 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
13776 && (GET_MODE (operands[0]) == HImode
13777 || (GET_MODE (operands[0]) == QImode
13778 && (TARGET_PROMOTE_QImode || optimize_size)))"
13779 [(set (match_dup 0)
13780 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
13781 "operands[0] = gen_lowpart (SImode, operands[0]);
13782 operands[2] = gen_lowpart (SImode, operands[2]);
13783 operands[3] = gen_lowpart (SImode, operands[3]);")
13786 ;; RTL Peephole optimizations, run before sched2. These primarily look to
13787 ;; transform a complex memory operation into two memory to register operations.
13789 ;; Don't push memory operands
13791 [(set (match_operand:SI 0 "push_operand" "")
13792 (match_operand:SI 1 "memory_operand" ""))
13793 (match_scratch:SI 2 "r")]
13794 "! optimize_size && ! TARGET_PUSH_MEMORY"
13795 [(set (match_dup 2) (match_dup 1))
13796 (set (match_dup 0) (match_dup 2))]
13799 ;; We need to handle SFmode only, because DFmode and XFmode is split to
13802 [(set (match_operand:SF 0 "push_operand" "")
13803 (match_operand:SF 1 "memory_operand" ""))
13804 (match_scratch:SF 2 "r")]
13805 "! optimize_size && ! TARGET_PUSH_MEMORY"
13806 [(set (match_dup 2) (match_dup 1))
13807 (set (match_dup 0) (match_dup 2))]
13811 [(set (match_operand:HI 0 "push_operand" "")
13812 (match_operand:HI 1 "memory_operand" ""))
13813 (match_scratch:HI 2 "r")]
13814 "! optimize_size && ! TARGET_PUSH_MEMORY"
13815 [(set (match_dup 2) (match_dup 1))
13816 (set (match_dup 0) (match_dup 2))]
13820 [(set (match_operand:QI 0 "push_operand" "")
13821 (match_operand:QI 1 "memory_operand" ""))
13822 (match_scratch:QI 2 "q")]
13823 "! optimize_size && ! TARGET_PUSH_MEMORY"
13824 [(set (match_dup 2) (match_dup 1))
13825 (set (match_dup 0) (match_dup 2))]
13828 ;; Don't move an immediate directly to memory when the instruction
13831 [(match_scratch:SI 1 "r")
13832 (set (match_operand:SI 0 "memory_operand" "")
13835 && ! TARGET_USE_MOV0
13836 && TARGET_SPLIT_LONG_MOVES
13837 && get_attr_length (insn) >= ix86_cost->large_insn
13838 && peep2_regno_dead_p (0, FLAGS_REG)"
13839 [(parallel [(set (match_dup 1) (const_int 0))
13840 (clobber (reg:CC 17))])
13841 (set (match_dup 0) (match_dup 1))]
13845 [(match_scratch:HI 1 "r")
13846 (set (match_operand:HI 0 "memory_operand" "")
13849 && ! TARGET_USE_MOV0
13850 && TARGET_SPLIT_LONG_MOVES
13851 && get_attr_length (insn) >= ix86_cost->large_insn
13852 && peep2_regno_dead_p (0, FLAGS_REG)"
13853 [(parallel [(set (match_dup 2) (const_int 0))
13854 (clobber (reg:CC 17))])
13855 (set (match_dup 0) (match_dup 1))]
13856 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
13859 [(match_scratch:QI 1 "q")
13860 (set (match_operand:QI 0 "memory_operand" "")
13863 && ! TARGET_USE_MOV0
13864 && TARGET_SPLIT_LONG_MOVES
13865 && get_attr_length (insn) >= ix86_cost->large_insn
13866 && peep2_regno_dead_p (0, FLAGS_REG)"
13867 [(parallel [(set (match_dup 2) (const_int 0))
13868 (clobber (reg:CC 17))])
13869 (set (match_dup 0) (match_dup 1))]
13870 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
13873 [(match_scratch:SI 2 "r")
13874 (set (match_operand:SI 0 "memory_operand" "")
13875 (match_operand:SI 1 "immediate_operand" ""))]
13877 && get_attr_length (insn) >= ix86_cost->large_insn
13878 && TARGET_SPLIT_LONG_MOVES"
13879 [(set (match_dup 2) (match_dup 1))
13880 (set (match_dup 0) (match_dup 2))]
13884 [(match_scratch:HI 2 "r")
13885 (set (match_operand:HI 0 "memory_operand" "")
13886 (match_operand:HI 1 "immediate_operand" ""))]
13887 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
13888 && TARGET_SPLIT_LONG_MOVES"
13889 [(set (match_dup 2) (match_dup 1))
13890 (set (match_dup 0) (match_dup 2))]
13894 [(match_scratch:QI 2 "q")
13895 (set (match_operand:QI 0 "memory_operand" "")
13896 (match_operand:QI 1 "immediate_operand" ""))]
13897 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
13898 && TARGET_SPLIT_LONG_MOVES"
13899 [(set (match_dup 2) (match_dup 1))
13900 (set (match_dup 0) (match_dup 2))]
13903 ;; Don't compare memory with zero, load and use a test instead.
13906 (compare (match_operand:SI 0 "memory_operand" "")
13908 (match_scratch:SI 3 "r")]
13909 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
13910 [(set (match_dup 3) (match_dup 0))
13911 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
13914 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
13915 ;; Don't split NOTs with a displacement operand, because resulting XOR
13916 ;; will not be pariable anyway.
13918 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
13919 ;; represented using a modRM byte. The XOR replacement is long decoded,
13920 ;; so this split helps here as well.
13922 ;; Note: Can't do this as a regular split because we can't get proper
13923 ;; lifetime information then.
13926 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
13927 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
13929 && peep2_regno_dead_p (0, FLAGS_REG)
13930 && ((TARGET_PENTIUM
13931 && (GET_CODE (operands[0]) != MEM
13932 || !memory_displacement_operand (operands[0], SImode)))
13933 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
13934 [(parallel [(set (match_dup 0)
13935 (xor:SI (match_dup 1) (const_int -1)))
13936 (clobber (reg:CC 17))])]
13940 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
13941 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
13943 && peep2_regno_dead_p (0, FLAGS_REG)
13944 && ((TARGET_PENTIUM
13945 && (GET_CODE (operands[0]) != MEM
13946 || !memory_displacement_operand (operands[0], HImode)))
13947 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
13948 [(parallel [(set (match_dup 0)
13949 (xor:HI (match_dup 1) (const_int -1)))
13950 (clobber (reg:CC 17))])]
13954 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
13955 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
13957 && peep2_regno_dead_p (0, FLAGS_REG)
13958 && ((TARGET_PENTIUM
13959 && (GET_CODE (operands[0]) != MEM
13960 || !memory_displacement_operand (operands[0], QImode)))
13961 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
13962 [(parallel [(set (match_dup 0)
13963 (xor:QI (match_dup 1) (const_int -1)))
13964 (clobber (reg:CC 17))])]
13967 ;; Non pairable "test imm, reg" instructions can be translated to
13968 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
13969 ;; byte opcode instead of two, have a short form for byte operands),
13970 ;; so do it for other CPUs as well. Given that the value was dead,
13971 ;; this should not create any new dependancies. Pass on the sub-word
13972 ;; versions if we're concerned about partial register stalls.
13976 (compare (and:SI (match_operand:SI 0 "register_operand" "")
13977 (match_operand:SI 1 "immediate_operand" ""))
13979 "ix86_match_ccmode (insn, CCNOmode)
13980 && (true_regnum (operands[0]) != 0
13981 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
13982 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13984 [(set (reg:CCNO 17)
13985 (compare:CCNO (and:SI (match_dup 0)
13989 (and:SI (match_dup 0) (match_dup 1)))])]
13992 ;; We don't need to handle HImode case, because it will be promoted to SImode
13993 ;; on ! TARGET_PARTIAL_REG_STALL
13997 (compare (and:QI (match_operand:QI 0 "register_operand" "")
13998 (match_operand:QI 1 "immediate_operand" ""))
14000 "! TARGET_PARTIAL_REG_STALL
14001 && ix86_match_ccmode (insn, CCNOmode)
14002 && true_regnum (operands[0]) != 0
14003 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14005 [(set (reg:CCNO 17)
14006 (compare:CCNO (and:QI (match_dup 0)
14010 (and:QI (match_dup 0) (match_dup 1)))])]
14018 (match_operand 0 "ext_register_operand" "q")
14021 (match_operand 1 "const_int_operand" "n"))
14023 "! TARGET_PARTIAL_REG_STALL
14024 && ix86_match_ccmode (insn, CCNOmode)
14025 && true_regnum (operands[0]) != 0
14026 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14027 [(parallel [(set (reg:CCNO 17)
14036 (set (zero_extract:SI (match_dup 0)
14047 ;; Don't do logical operations with memory inputs.
14049 [(match_scratch:SI 2 "r")
14050 (parallel [(set (match_operand:SI 0 "register_operand" "")
14051 (match_operator:SI 3 "arith_or_logical_operator"
14053 (match_operand:SI 1 "memory_operand" "")]))
14054 (clobber (reg:CC 17))])]
14055 "! optimize_size && ! TARGET_READ_MODIFY"
14056 [(set (match_dup 2) (match_dup 1))
14057 (parallel [(set (match_dup 0)
14058 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
14059 (clobber (reg:CC 17))])]
14063 [(match_scratch:SI 2 "r")
14064 (parallel [(set (match_operand:SI 0 "register_operand" "")
14065 (match_operator:SI 3 "arith_or_logical_operator"
14066 [(match_operand:SI 1 "memory_operand" "")
14068 (clobber (reg:CC 17))])]
14069 "! optimize_size && ! TARGET_READ_MODIFY"
14070 [(set (match_dup 2) (match_dup 1))
14071 (parallel [(set (match_dup 0)
14072 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
14073 (clobber (reg:CC 17))])]
14076 ; Don't do logical operations with memory outputs
14078 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
14079 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
14080 ; the same decoder scheduling characteristics as the original.
14083 [(match_scratch:SI 2 "r")
14084 (parallel [(set (match_operand:SI 0 "memory_operand" "")
14085 (match_operator:SI 3 "arith_or_logical_operator"
14087 (match_operand:SI 1 "nonmemory_operand" "")]))
14088 (clobber (reg:CC 17))])]
14089 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
14090 [(set (match_dup 2) (match_dup 0))
14091 (parallel [(set (match_dup 2)
14092 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
14093 (clobber (reg:CC 17))])
14094 (set (match_dup 0) (match_dup 2))]
14098 [(match_scratch:SI 2 "r")
14099 (parallel [(set (match_operand:SI 0 "memory_operand" "")
14100 (match_operator:SI 3 "arith_or_logical_operator"
14101 [(match_operand:SI 1 "nonmemory_operand" "")
14103 (clobber (reg:CC 17))])]
14104 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
14105 [(set (match_dup 2) (match_dup 0))
14106 (parallel [(set (match_dup 2)
14107 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
14108 (clobber (reg:CC 17))])
14109 (set (match_dup 0) (match_dup 2))]
14112 ;; Attempt to always use XOR for zeroing registers.
14114 [(set (match_operand 0 "register_operand" "")
14116 "(GET_MODE (operands[0]) == QImode
14117 || GET_MODE (operands[0]) == HImode
14118 || GET_MODE (operands[0]) == SImode)
14119 && (! TARGET_USE_MOV0 || optimize_size)
14120 && peep2_regno_dead_p (0, FLAGS_REG)"
14121 [(parallel [(set (match_dup 0) (const_int 0))
14122 (clobber (reg:CC 17))])]
14123 "operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
14126 [(set (strict_low_part (match_operand 0 "register_operand" ""))
14128 "(GET_MODE (operands[0]) == QImode
14129 || GET_MODE (operands[0]) == HImode)
14130 && (! TARGET_USE_MOV0 || optimize_size)
14131 && peep2_regno_dead_p (0, FLAGS_REG)"
14132 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
14133 (clobber (reg:CC 17))])])
14135 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
14137 [(set (match_operand 0 "register_operand" "")
14139 "(GET_MODE (operands[0]) == HImode
14140 || GET_MODE (operands[0]) == SImode)
14141 && (optimize_size || TARGET_PENTIUM)
14142 && peep2_regno_dead_p (0, FLAGS_REG)"
14143 [(parallel [(set (match_dup 0) (const_int -1))
14144 (clobber (reg:CC 17))])]
14145 "operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
14147 ;; Attempt to convert simple leas to adds. These can be created by
14150 [(set (match_operand:SI 0 "register_operand" "")
14151 (plus:SI (match_dup 0)
14152 (match_operand:SI 1 "nonmemory_operand" "")))]
14153 "peep2_regno_dead_p (0, FLAGS_REG)"
14154 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
14155 (clobber (reg:CC 17))])]
14159 [(set (match_operand:SI 0 "register_operand" "")
14160 (mult:SI (match_dup 0)
14161 (match_operand:SI 1 "immediate_operand" "")))]
14162 "exact_log2 (INTVAL (operands[1])) >= 0
14163 && peep2_regno_dead_p (0, FLAGS_REG)"
14164 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
14165 (clobber (reg:CC 17))])]
14166 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
14168 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
14169 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
14170 ;; many CPUs it is also faster, since special hardware to avoid esp
14171 ;; dependancies is present.
14173 ;; While some of these converisons may be done using splitters, we use peepholes
14174 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
14176 ;; Convert prologue esp substractions to push.
14177 ;; We need register to push. In order to keep verify_flow_info happy we have
14179 ;; - use scratch and clobber it in order to avoid dependencies
14180 ;; - use already live register
14181 ;; We can't use the second way right now, since there is no reliable way how to
14182 ;; verify that given register is live. First choice will also most likely in
14183 ;; fewer dependencies. On the place of esp adjustments it is very likely that
14184 ;; call clobbered registers are dead. We may want to use base pointer as an
14185 ;; alternative when no register is available later.
14188 [(match_scratch:SI 0 "r")
14189 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
14190 (set (reg:SI 6) (reg:SI 6))
14191 (clobber (reg:CC 17))])]
14192 "optimize_size || !TARGET_SUB_ESP_4"
14193 [(clobber (match_dup 0))
14194 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
14195 (set (reg:SI 6) (reg:SI 6))])])
14198 [(match_scratch:SI 0 "r")
14199 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
14200 (set (reg:SI 6) (reg:SI 6))
14201 (clobber (reg:CC 17))])]
14202 "optimize_size || !TARGET_SUB_ESP_8"
14203 [(clobber (match_dup 0))
14204 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
14205 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
14206 (set (reg:SI 6) (reg:SI 6))])])
14208 ;; Convert esp substractions to push.
14210 [(match_scratch:SI 0 "r")
14211 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
14212 (clobber (reg:CC 17))])]
14213 "optimize_size || !TARGET_SUB_ESP_4"
14214 [(clobber (match_dup 0))
14215 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
14218 [(match_scratch:SI 0 "r")
14219 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
14220 (clobber (reg:CC 17))])]
14221 "optimize_size || !TARGET_SUB_ESP_8"
14222 [(clobber (match_dup 0))
14223 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
14224 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
14226 ;; Convert epilogue deallocator to pop.
14228 [(match_scratch:SI 0 "r")
14229 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
14230 (set (reg:SI 6) (reg:SI 6))
14231 (clobber (reg:CC 17))])]
14232 "optimize_size || !TARGET_ADD_ESP_4"
14233 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14234 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
14235 (set (reg:SI 6) (reg:SI 6))])]
14238 ;; Two pops case is tricky, since pop causes dependency on destination register.
14239 ;; We use two registers if available.
14241 [(match_scratch:SI 0 "r")
14242 (match_scratch:SI 1 "r")
14243 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
14244 (set (reg:SI 6) (reg:SI 6))
14245 (clobber (reg:CC 17))])]
14246 "optimize_size || !TARGET_ADD_ESP_8"
14247 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14248 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
14249 (set (reg:SI 6) (reg:SI 6))])
14250 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
14251 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
14255 [(match_scratch:SI 0 "r")
14256 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
14257 (set (reg:SI 6) (reg:SI 6))
14258 (clobber (reg:CC 17))])]
14260 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14261 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
14262 (set (reg:SI 6) (reg:SI 6))])
14263 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14264 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
14267 ;; Convert esp additions to pop.
14269 [(match_scratch:SI 0 "r")
14270 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
14271 (clobber (reg:CC 17))])]
14273 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14274 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
14277 ;; Two pops case is tricky, since pop causes dependency on destination register.
14278 ;; We use two registers if available.
14280 [(match_scratch:SI 0 "r")
14281 (match_scratch:SI 1 "r")
14282 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
14283 (clobber (reg:CC 17))])]
14285 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14286 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
14287 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
14288 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
14292 [(match_scratch:SI 0 "r")
14293 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
14294 (clobber (reg:CC 17))])]
14296 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14297 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
14298 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
14299 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
14302 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
14303 ;; required and register dies.
14306 (compare (match_operand:SI 0 "register_operand" "")
14307 (match_operand:SI 1 "incdec_operand" "")))]
14308 "ix86_match_ccmode (insn, CCGCmode)
14309 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14310 [(parallel [(set (reg:CCGC 17)
14311 (compare:CCGC (match_dup 0)
14313 (clobber (match_dup 0))])]
14318 (compare (match_operand:HI 0 "register_operand" "")
14319 (match_operand:HI 1 "incdec_operand" "")))]
14320 "ix86_match_ccmode (insn, CCGCmode)
14321 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14322 [(parallel [(set (reg:CCGC 17)
14323 (compare:CCGC (match_dup 0)
14325 (clobber (match_dup 0))])]
14330 (compare (match_operand:QI 0 "register_operand" "")
14331 (match_operand:QI 1 "incdec_operand" "")))]
14332 "ix86_match_ccmode (insn, CCGCmode)
14333 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14334 [(parallel [(set (reg:CCGC 17)
14335 (compare:CCGC (match_dup 0)
14337 (clobber (match_dup 0))])]
14340 ;; Convert compares with 128 to shorter add -128
14343 (compare (match_operand:SI 0 "register_operand" "")
14345 "ix86_match_ccmode (insn, CCGCmode)
14346 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14347 [(parallel [(set (reg:CCGC 17)
14348 (compare:CCGC (match_dup 0)
14350 (clobber (match_dup 0))])]
14355 (compare (match_operand:HI 0 "register_operand" "")
14357 "ix86_match_ccmode (insn, CCGCmode)
14358 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
14359 [(parallel [(set (reg:CCGC 17)
14360 (compare:CCGC (match_dup 0)
14362 (clobber (match_dup 0))])]
14365 ;; Call-value patterns last so that the wildcard operand does not
14366 ;; disrupt insn-recog's switch tables.
14368 (define_insn "*call_value_pop_0"
14369 [(set (match_operand 0 "" "")
14370 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
14371 (match_operand:SI 2 "" "")))
14372 (set (reg:SI 7) (plus:SI (reg:SI 7)
14373 (match_operand:SI 3 "immediate_operand" "")))]
14377 if (SIBLING_CALL_P (insn))
14378 return \"jmp\\t%P1\";
14380 return \"call\\t%P1\";
14382 [(set_attr "type" "callv")])
14384 (define_insn "*call_value_pop_1"
14385 [(set (match_operand 0 "" "")
14386 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
14387 (match_operand:SI 2 "" "")))
14388 (set (reg:SI 7) (plus:SI (reg:SI 7)
14389 (match_operand:SI 3 "immediate_operand" "i")))]
14393 if (constant_call_address_operand (operands[1], QImode))
14395 if (SIBLING_CALL_P (insn))
14396 return \"jmp\\t%P1\";
14398 return \"call\\t%P1\";
14400 if (SIBLING_CALL_P (insn))
14401 return \"jmp\\t%A1\";
14403 return \"call\\t%A1\";
14405 [(set_attr "type" "callv")])
14407 (define_insn "*call_value_0"
14408 [(set (match_operand 0 "" "")
14409 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
14410 (match_operand:SI 2 "" "")))]
14414 if (SIBLING_CALL_P (insn))
14415 return \"jmp\\t%P1\";
14417 return \"call\\t%P1\";
14419 [(set_attr "type" "callv")])
14421 (define_insn "*call_value_1"
14422 [(set (match_operand 0 "" "")
14423 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
14424 (match_operand:SI 2 "" "")))]
14428 if (constant_call_address_operand (operands[1], QImode))
14430 if (SIBLING_CALL_P (insn))
14431 return \"jmp\\t%P1\";
14433 return \"call\\t%P1\";
14435 if (SIBLING_CALL_P (insn))
14436 return \"jmp\\t%A1\";
14438 return \"call\\t%A1\";
14440 [(set_attr "type" "callv")])
14442 (define_insn "trap"
14443 [(trap_if (const_int 1) (const_int 5))]
14447 ;;; ix86 doesn't have conditional trap instructions, but we fake them
14448 ;;; for the sake of bounds checking. By emitting bounds checks as
14449 ;;; conditional traps rather than as conditional jumps around
14450 ;;; unconditional traps we avoid introducing spurious basic-block
14451 ;;; boundaries and facilitate elimination of redundant checks. In
14452 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
14455 ;;; FIXME: Static branch prediction rules for ix86 are such that
14456 ;;; forward conditional branches predict as untaken. As implemented
14457 ;;; below, pseudo conditional traps violate that rule. We should use
14458 ;;; .pushsection/.popsection to place all of the `int 5's in a special
14459 ;;; section loaded at the end of the text segment and branch forward
14460 ;;; there on bounds-failure, and then jump back immediately (in case
14461 ;;; the system chooses to ignore bounds violations, or to report
14462 ;;; violations and continue execution).
14464 (define_expand "conditional_trap"
14465 [(trap_if (match_operator 0 "comparison_operator"
14466 [(match_dup 2) (const_int 0)])
14467 (match_operand 1 "const_int_operand" ""))]
14471 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
14472 ix86_expand_compare (GET_CODE (operands[0]),
14473 NULL_PTR, NULL_PTR),
14479 [(trap_if (match_operator 0 "comparison_operator"
14480 [(reg 17) (const_int 0)])
14481 (match_operand 1 "const_int_operand" ""))]
14485 operands[2] = gen_label_rtx ();
14486 output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
14487 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
14488 CODE_LABEL_NUMBER (operands[2]));
14492 ;; Pentium III SIMD instructions.
14494 ;; Moves for SSE/MMX regs.
14496 (define_insn "movv4sf_internal"
14497 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
14498 (match_operand:V4SF 1 "general_operand" "xm,x"))]
14500 ;; @@@ let's try to use movaps here.
14501 "movaps\\t{%1, %0|%0, %1}"
14502 [(set_attr "type" "sse")])
14504 (define_insn "movv4si_internal"
14505 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
14506 (match_operand:V4SI 1 "general_operand" "xm,x"))]
14508 ;; @@@ let's try to use movaps here.
14509 "movaps\\t{%1, %0|%0, %1}"
14510 [(set_attr "type" "sse")])
14512 (define_insn "movv8qi_internal"
14513 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
14514 (match_operand:V8QI 1 "general_operand" "ym,y"))]
14516 "movq\\t{%1, %0|%0, %1}"
14517 [(set_attr "type" "mmx")])
14519 (define_insn "movv4hi_internal"
14520 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
14521 (match_operand:V4HI 1 "general_operand" "ym,y"))]
14523 "movq\\t{%1, %0|%0, %1}"
14524 [(set_attr "type" "mmx")])
14526 (define_insn "movv2si_internal"
14527 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
14528 (match_operand:V2SI 1 "general_operand" "ym,y"))]
14530 "movq\\t{%1, %0|%0, %1}"
14531 [(set_attr "type" "mmx")])
14533 (define_expand "movti"
14534 [(set (match_operand:TI 0 "general_operand" "")
14535 (match_operand:TI 1 "general_operand" ""))]
14539 /* For constants other than zero into memory. We do not know how the
14540 instructions used to build constants modify the upper 64 bits
14541 of the register, once we have that information we may be able
14542 to handle some of them more efficiently. */
14543 if ((reload_in_progress | reload_completed) == 0
14544 && register_operand (operands[0], TImode)
14545 && CONSTANT_P (operands[1]))
14547 rtx addr = gen_reg_rtx (Pmode);
14549 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
14550 operands[1] = gen_rtx_MEM (TImode, addr);
14553 /* Make operand1 a register if it isn't already. */
14554 if ((reload_in_progress | reload_completed) == 0
14555 && !register_operand (operands[0], TImode)
14556 && !register_operand (operands[1], TImode)
14557 && operands[1] != CONST0_RTX (TImode))
14559 rtx temp = force_reg (TImode, operands[1]);
14560 emit_move_insn (operands[0], temp);
14565 (define_expand "movv4sf"
14566 [(set (match_operand:V4SF 0 "general_operand" "")
14567 (match_operand:V4SF 1 "general_operand" ""))]
14571 /* For constants other than zero into memory. We do not know how the
14572 instructions used to build constants modify the upper 64 bits
14573 of the register, once we have that information we may be able
14574 to handle some of them more efficiently. */
14575 if ((reload_in_progress | reload_completed) == 0
14576 && register_operand (operands[0], V4SFmode)
14577 && CONSTANT_P (operands[1]))
14579 rtx addr = gen_reg_rtx (Pmode);
14581 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
14582 operands[1] = gen_rtx_MEM (V4SFmode, addr);
14585 /* Make operand1 a register if it isn't already. */
14586 if ((reload_in_progress | reload_completed) == 0
14587 && !register_operand (operands[0], V4SFmode)
14588 && !register_operand (operands[1], V4SFmode)
14589 && operands[1] != CONST0_RTX (V4SFmode))
14591 rtx temp = force_reg (V4SFmode, operands[1]);
14592 emit_move_insn (operands[0], temp);
14597 (define_expand "movv4si"
14598 [(set (match_operand:V4SI 0 "general_operand" "")
14599 (match_operand:V4SI 1 "general_operand" ""))]
14603 /* For constants other than zero into memory. We do not know how the
14604 instructions used to build constants modify the upper 64 bits
14605 of the register, once we have that information we may be able
14606 to handle some of them more efficiently. */
14607 if ((reload_in_progress | reload_completed) == 0
14608 && register_operand (operands[0], V4SImode)
14609 && CONSTANT_P (operands[1]))
14611 rtx addr = gen_reg_rtx (Pmode);
14613 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
14614 operands[1] = gen_rtx_MEM (V4SImode, addr);
14617 /* Make operand1 a register if it isn't already. */
14618 if ((reload_in_progress | reload_completed) == 0
14619 && !register_operand (operands[0], V4SImode)
14620 && !register_operand (operands[1], V4SImode)
14621 && operands[1] != CONST0_RTX (V4SImode))
14623 rtx temp = force_reg (V4SImode, operands[1]);
14624 emit_move_insn (operands[0], temp);
14629 (define_expand "movv2si"
14630 [(set (match_operand:V2SI 0 "general_operand" "")
14631 (match_operand:V2SI 1 "general_operand" ""))]
14635 /* For constants other than zero into memory. We do not know how the
14636 instructions used to build constants modify the upper 64 bits
14637 of the register, once we have that information we may be able
14638 to handle some of them more efficiently. */
14639 if ((reload_in_progress | reload_completed) == 0
14640 && register_operand (operands[0], V2SImode)
14641 && CONSTANT_P (operands[1]))
14643 rtx addr = gen_reg_rtx (Pmode);
14645 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
14646 operands[1] = gen_rtx_MEM (V2SImode, addr);
14649 /* Make operand1 a register if it isn't already. */
14650 if ((reload_in_progress | reload_completed) == 0
14651 && !register_operand (operands[0], V2SImode)
14652 && !register_operand (operands[1], V2SImode)
14653 && operands[1] != CONST0_RTX (V2SImode))
14655 rtx temp = force_reg (V2SImode, operands[1]);
14656 emit_move_insn (operands[0], temp);
14661 (define_expand "movv4hi"
14662 [(set (match_operand:V4HI 0 "general_operand" "")
14663 (match_operand:V4HI 1 "general_operand" ""))]
14667 /* For constants other than zero into memory. We do not know how the
14668 instructions used to build constants modify the upper 64 bits
14669 of the register, once we have that information we may be able
14670 to handle some of them more efficiently. */
14671 if ((reload_in_progress | reload_completed) == 0
14672 && register_operand (operands[0], V4HImode)
14673 && CONSTANT_P (operands[1]))
14675 rtx addr = gen_reg_rtx (Pmode);
14677 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
14678 operands[1] = gen_rtx_MEM (V4HImode, addr);
14681 /* Make operand1 a register if it isn't already. */
14682 if ((reload_in_progress | reload_completed) == 0
14683 && !register_operand (operands[0], V4HImode)
14684 && !register_operand (operands[1], V4HImode)
14685 && operands[1] != CONST0_RTX (V4HImode))
14687 rtx temp = force_reg (V4HImode, operands[1]);
14688 emit_move_insn (operands[0], temp);
14693 (define_expand "movv8qi"
14694 [(set (match_operand:V8QI 0 "general_operand" "")
14695 (match_operand:V8QI 1 "general_operand" ""))]
14699 /* For constants other than zero into memory. We do not know how the
14700 instructions used to build constants modify the upper 64 bits
14701 of the register, once we have that information we may be able
14702 to handle some of them more efficiently. */
14703 if ((reload_in_progress | reload_completed) == 0
14704 && register_operand (operands[0], V8QImode)
14705 && CONSTANT_P (operands[1]))
14707 rtx addr = gen_reg_rtx (Pmode);
14709 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
14710 operands[1] = gen_rtx_MEM (V8QImode, addr);
14713 /* Make operand1 a register if it isn't already. */
14714 if ((reload_in_progress | reload_completed) == 0
14715 && !register_operand (operands[0], V8QImode)
14716 && !register_operand (operands[1], V8QImode)
14717 && operands[1] != CONST0_RTX (V8QImode))
14719 rtx temp = force_reg (V8QImode, operands[1]);
14720 emit_move_insn (operands[0], temp);
14725 (define_insn_and_split "*pushti"
14726 [(set (match_operand:TI 0 "push_operand" "=<")
14727 (match_operand:TI 1 "nonmemory_operand" "x"))]
14731 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
14732 (set (mem:TI (reg:SI 7)) (match_dup 1))]
14734 [(set_attr "type" "sse")])
14736 (define_insn_and_split "*pushv4sf"
14737 [(set (match_operand:V4SF 0 "push_operand" "=<")
14738 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
14742 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
14743 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
14745 [(set_attr "type" "sse")])
14747 (define_insn_and_split "*pushv4si"
14748 [(set (match_operand:V4SI 0 "push_operand" "=<")
14749 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
14753 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
14754 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
14756 [(set_attr "type" "sse")])
14758 (define_insn_and_split "*pushv2si"
14759 [(set (match_operand:V2SI 0 "push_operand" "=<")
14760 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
14764 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
14765 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
14767 [(set_attr "type" "mmx")])
14769 (define_insn_and_split "*pushv4hi"
14770 [(set (match_operand:V4HI 0 "push_operand" "=<")
14771 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
14775 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
14776 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
14778 [(set_attr "type" "mmx")])
14780 (define_insn_and_split "*pushv8qi"
14781 [(set (match_operand:V8QI 0 "push_operand" "=<")
14782 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
14786 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
14787 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
14789 [(set_attr "type" "mmx")])
14791 (define_insn "movti_internal"
14792 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
14793 (match_operand:TI 1 "general_operand" "xm,x"))]
14796 movaps\\t{%1, %0|%0, %1}
14797 movaps\\t{%1, %0|%0, %1}"
14798 [(set_attr "type" "sse")])
14800 ;; These two patterns are useful for specifying exactly whether to use
14801 ;; movaps or movups
14802 (define_insn "sse_movaps"
14803 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
14804 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
14807 movaps\\t{%1, %0|%0, %1}
14808 movaps\\t{%1, %0|%0, %1}"
14809 [(set_attr "type" "sse")])
14811 (define_insn "sse_movups"
14812 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
14813 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
14816 movups\\t{%1, %0|%0, %1}
14817 movups\\t{%1, %0|%0, %1}"
14818 [(set_attr "type" "sse")])
14821 ;; SSE Strange Moves.
14823 (define_insn "sse_movmskps"
14824 [(set (match_operand:SI 0 "register_operand" "=r")
14825 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
14827 "movmskps\\t{%1, %0|%0, %1}"
14828 [(set_attr "type" "sse")])
14830 (define_insn "mmx_pmovmskb"
14831 [(set (match_operand:SI 0 "register_operand" "=r")
14832 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
14834 "pmovmskb\\t{%1, %0|%0, %1}"
14835 [(set_attr "type" "sse")])
14837 (define_insn "mmx_maskmovq"
14838 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
14839 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
14840 (match_operand:V8QI 2 "register_operand" "y")] 32))]
14842 ;; @@@ check ordering of operands in intel/nonintel syntax
14843 "maskmovq\\t{%2, %1|%1, %2}"
14844 [(set_attr "type" "sse")])
14846 (define_insn "sse_movntv4sf"
14847 [(set (match_operand:V4SF 0 "memory_operand" "=m")
14848 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
14850 "movntps\\t{%1, %0|%0, %1}"
14851 [(set_attr "type" "sse")])
14853 (define_insn "sse_movntdi"
14854 [(set (match_operand:DI 0 "memory_operand" "=m")
14855 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
14857 "movntq\\t{%1, %0|%0, %1}"
14858 [(set_attr "type" "sse")])
14860 (define_insn "sse_movhlps"
14861 [(set (match_operand:V4SF 0 "register_operand" "=x")
14863 (match_operand:V4SF 1 "register_operand" "0")
14864 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
14865 (parallel [(const_int 2)
14871 "movhlps\\t{%2, %0|%0, %2}"
14872 [(set_attr "type" "sse")])
14874 (define_insn "sse_movlhps"
14875 [(set (match_operand:V4SF 0 "register_operand" "=x")
14877 (match_operand:V4SF 1 "register_operand" "0")
14878 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
14879 (parallel [(const_int 2)
14885 "movlhps\\t{%2, %0|%0, %2}"
14886 [(set_attr "type" "sse")])
14888 (define_insn "sse_movhps"
14889 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
14891 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
14892 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
14894 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
14895 "movhps\\t{%2, %0|%0, %2}"
14896 [(set_attr "type" "sse")])
14898 (define_insn "sse_movlps"
14899 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
14901 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
14902 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
14904 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
14905 "movlps\\t{%2, %0|%0, %2}"
14906 [(set_attr "type" "sse")])
14908 (define_insn "sse_loadss"
14909 [(set (match_operand:V4SF 0 "register_operand" "=x")
14911 (match_operand:V4SF 1 "memory_operand" "m")
14912 (vec_duplicate:V4SF (float:SF (const_int 0)))
14915 "movss\\t{%1, %0|%0, %1}"
14916 [(set_attr "type" "sse")])
14918 (define_insn "sse_movss"
14919 [(set (match_operand:V4SF 0 "register_operand" "=x")
14921 (match_operand:V4SF 1 "register_operand" "0")
14922 (match_operand:V4SF 2 "register_operand" "x")
14925 "movss\\t{%2, %0|%0, %2}"
14926 [(set_attr "type" "sse")])
14928 (define_insn "sse_storess"
14929 [(set (match_operand:SF 0 "memory_operand" "=m")
14931 (match_operand:V4SF 1 "register_operand" "x")
14932 (parallel [(const_int 0)])))]
14934 "movss\\t{%1, %0|%0, %1}"
14935 [(set_attr "type" "sse")])
14937 (define_insn "sse_shufps"
14938 [(set (match_operand:V4SF 0 "register_operand" "=x")
14939 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
14940 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
14941 (match_operand:SI 3 "immediate_operand" "i")] 41))]
14943 ;; @@@ check operand order for intel/nonintel syntax
14944 "shufps\\t{%3, %2, %0|%0, %2, %3}"
14945 [(set_attr "type" "sse")])
14950 (define_insn "addv4sf3"
14951 [(set (match_operand:V4SF 0 "register_operand" "=x")
14952 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14953 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14955 "addps\\t{%2, %0|%0, %2}"
14956 [(set_attr "type" "sse")])
14958 (define_insn "vmaddv4sf3"
14959 [(set (match_operand:V4SF 0 "register_operand" "=x")
14960 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14961 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14965 "addss\\t{%2, %0|%0, %2}"
14966 [(set_attr "type" "sse")])
14968 (define_insn "subv4sf3"
14969 [(set (match_operand:V4SF 0 "register_operand" "=x")
14970 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14971 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14973 "subps\\t{%2, %0|%0, %2}"
14974 [(set_attr "type" "sse")])
14976 (define_insn "vmsubv4sf3"
14977 [(set (match_operand:V4SF 0 "register_operand" "=x")
14978 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14979 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14983 "subss\\t{%2, %0|%0, %2}"
14984 [(set_attr "type" "sse")])
14986 (define_insn "mulv4sf3"
14987 [(set (match_operand:V4SF 0 "register_operand" "=x")
14988 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
14989 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14991 "mulps\\t{%2, %0|%0, %2}"
14992 [(set_attr "type" "sse")])
14994 (define_insn "vmmulv4sf3"
14995 [(set (match_operand:V4SF 0 "register_operand" "=x")
14996 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
14997 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
15001 "mulss\\t{%2, %0|%0, %2}"
15002 [(set_attr "type" "sse")])
15004 (define_insn "divv4sf3"
15005 [(set (match_operand:V4SF 0 "register_operand" "=x")
15006 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
15007 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
15009 "divps\\t{%2, %0|%0, %2}"
15010 [(set_attr "type" "sse")])
15012 (define_insn "vmdivv4sf3"
15013 [(set (match_operand:V4SF 0 "register_operand" "=x")
15014 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
15015 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
15019 "divss\\t{%2, %0|%0, %2}"
15020 [(set_attr "type" "sse")])
15023 ;; SSE square root/reciprocal
15025 (define_insn "rcpv4sf2"
15026 [(set (match_operand:V4SF 0 "register_operand" "=x")
15027 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
15029 "rcpps\\t{%1, %0|%0, %1}"
15030 [(set_attr "type" "sse")])
15032 (define_insn "vmrcpv4sf2"
15033 [(set (match_operand:V4SF 0 "register_operand" "=x")
15034 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
15035 (match_operand:V4SF 2 "register_operand" "0")
15038 "rcpss\\t{%1, %0|%0, %1}"
15039 [(set_attr "type" "sse")])
15041 (define_insn "rsqrtv4sf2"
15042 [(set (match_operand:V4SF 0 "register_operand" "=x")
15043 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
15045 "rsqrtps\\t{%1, %0|%0, %1}"
15046 [(set_attr "type" "sse")])
15048 (define_insn "vmrsqrtv4sf2"
15049 [(set (match_operand:V4SF 0 "register_operand" "=x")
15050 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
15051 (match_operand:V4SF 2 "register_operand" "0")
15054 "rsqrtss\\t{%1, %0|%0, %1}"
15055 [(set_attr "type" "sse")])
15057 (define_insn "sqrtv4sf2"
15058 [(set (match_operand:V4SF 0 "register_operand" "=x")
15059 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
15061 "sqrtps\\t{%1, %0|%0, %1}"
15062 [(set_attr "type" "sse")])
15064 (define_insn "vmsqrtv4sf2"
15065 [(set (match_operand:V4SF 0 "register_operand" "=x")
15066 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
15067 (match_operand:V4SF 2 "register_operand" "0")
15070 "sqrtss\\t{%1, %0|%0, %1}"
15071 [(set_attr "type" "sse")])
15074 ;; SSE logical operations.
15076 ;; These are not called andti3 etc. because we really really don't want
15077 ;; the compiler to widen DImode ands to TImode ands and then try to move
15078 ;; into DImode subregs of SSE registers, and them together, and move out
15079 ;; of DImode subregs again!
15081 (define_insn "*sse_andti3_df_1"
15082 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15083 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
15084 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
15086 "andpd\\t{%2, %0|%0, %2}"
15087 [(set_attr "type" "sse")])
15089 (define_insn "*sse_andti3_df_2"
15090 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15091 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
15092 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
15094 "andpd\\t{%2, %0|%0, %2}"
15095 [(set_attr "type" "sse")])
15097 (define_insn "*sse_andti3_sf_1"
15098 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15099 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
15100 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
15102 "andps\\t{%2, %0|%0, %2}"
15103 [(set_attr "type" "sse")])
15105 (define_insn "*sse_andti3_sf_2"
15106 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15107 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
15108 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15110 "andps\\t{%2, %0|%0, %2}"
15111 [(set_attr "type" "sse")])
15113 (define_insn "sse_andti3"
15114 [(set (match_operand:TI 0 "register_operand" "=x")
15115 (and:TI (match_operand:TI 1 "register_operand" "%0")
15116 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15117 "TARGET_SSE && !TARGET_SSE2"
15118 "andps\\t{%2, %0|%0, %2}"
15119 [(set_attr "type" "sse")])
15121 (define_insn "*sse_andti3_sse2"
15122 [(set (match_operand:TI 0 "register_operand" "=x")
15123 (and:TI (match_operand:TI 1 "register_operand" "%0")
15124 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15126 "pand\\t{%2, %0|%0, %2}"
15127 [(set_attr "type" "sse")])
15129 (define_insn "*sse_nandti3_df"
15130 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15131 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
15132 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
15134 "andnpd\\t{%2, %0|%0, %2}"
15135 [(set_attr "type" "sse")])
15137 (define_insn "*sse_nandti3_sf"
15138 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15139 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
15140 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15142 "andnps\\t{%2, %0|%0, %2}"
15143 [(set_attr "type" "sse")])
15145 (define_insn "sse_nandti3"
15146 [(set (match_operand:TI 0 "register_operand" "=x")
15147 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
15148 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15149 "TARGET_SSE && !TARGET_SSE2"
15150 "andnps\\t{%2, %0|%0, %2}"
15151 [(set_attr "type" "sse")])
15153 (define_insn "*sse_nandti3_sse2"
15154 [(set (match_operand:TI 0 "register_operand" "=x")
15155 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
15156 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15158 "pnand\\t{%2, %0|%0, %2}"
15159 [(set_attr "type" "sse")])
15161 (define_insn "*sse_iorti3_df_1"
15162 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15163 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
15164 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
15166 "orpd\\t{%2, %0|%0, %2}"
15167 [(set_attr "type" "sse")])
15169 (define_insn "*sse_iorti3_df_2"
15170 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15171 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
15172 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
15174 "orpd\\t{%2, %0|%0, %2}"
15175 [(set_attr "type" "sse")])
15177 (define_insn "*sse_iorti3_sf_1"
15178 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15179 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
15180 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
15182 "orps\\t{%2, %0|%0, %2}"
15183 [(set_attr "type" "sse")])
15185 (define_insn "*sse_iorti3_sf_2"
15186 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15187 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
15188 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15190 "orps\\t{%2, %0|%0, %2}"
15191 [(set_attr "type" "sse")])
15193 (define_insn "sse_iorti3"
15194 [(set (match_operand:TI 0 "register_operand" "=x")
15195 (ior:TI (match_operand:TI 1 "register_operand" "%0")
15196 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15197 "TARGET_SSE && !TARGET_SSE2"
15198 "orps\\t{%2, %0|%0, %2}"
15199 [(set_attr "type" "sse")])
15201 (define_insn "*sse_iorti3_sse2"
15202 [(set (match_operand:TI 0 "register_operand" "=x")
15203 (ior:TI (match_operand:TI 1 "register_operand" "%0")
15204 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15206 "por\\t{%2, %0|%0, %2}"
15207 [(set_attr "type" "sse")])
15209 (define_insn "*sse_xorti3_df_1"
15210 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15211 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
15212 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
15214 "xorpd\\t{%2, %0|%0, %2}"
15215 [(set_attr "type" "sse")])
15217 (define_insn "*sse_xorti3_df_2"
15218 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
15219 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
15220 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
15222 "xorpd\\t{%2, %0|%0, %2}"
15223 [(set_attr "type" "sse")])
15225 (define_insn "*sse_xorti3_sf_1"
15226 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15227 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
15228 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
15230 "xorps\\t{%2, %0|%0, %2}"
15231 [(set_attr "type" "sse")])
15233 (define_insn "*sse_xorti3_sf_2"
15234 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
15235 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
15236 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15238 "xorps\\t{%2, %0|%0, %2}"
15239 [(set_attr "type" "sse")])
15241 (define_insn "sse_xorti3"
15242 [(set (match_operand:TI 0 "register_operand" "=x")
15243 (xor:TI (match_operand:TI 1 "register_operand" "%0")
15244 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15245 "TARGET_SSE && !TARGET_SSE2"
15246 "xorps\\t{%2, %0|%0, %2}"
15247 [(set_attr "type" "sse")])
15249 (define_insn "*sse_xorti3_sse2"
15250 [(set (match_operand:TI 0 "register_operand" "=x")
15251 (xor:TI (match_operand:TI 1 "register_operand" "%0")
15252 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
15254 "pxor\\t{%2, %0|%0, %2}"
15255 [(set_attr "type" "sse")])
15257 ;; Use xor, but don't show input operands so they aren't live before
15259 (define_insn "sse_clrti"
15260 [(set (match_operand:TI 0 "register_operand" "=x")
15261 (unspec:TI [(const_int 0)] 45))]
15263 "xorps\\t{%0, %0|%0, %0}"
15264 [(set_attr "type" "sse")])
15267 ;; SSE mask-generating compares
15269 (define_insn "maskcmpv4sf3"
15270 [(set (match_operand:V4SI 0 "register_operand" "=x")
15271 (match_operator:V4SI 3 "sse_comparison_operator"
15272 [(match_operand:V4SF 1 "register_operand" "0")
15273 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
15275 "cmp%D3ps\\t{%2, %0|%0, %2}"
15276 [(set_attr "type" "sse")])
15278 (define_insn "maskncmpv4sf3"
15279 [(set (match_operand:V4SI 0 "register_operand" "=x")
15281 (match_operator:V4SI 3 "sse_comparison_operator"
15282 [(match_operand:V4SF 1 "register_operand" "0")
15283 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
15285 "cmpn%D3ps\\t{%2, %0|%0, %2}"
15286 [(set_attr "type" "sse")])
15288 (define_insn "vmmaskcmpv4sf3"
15289 [(set (match_operand:V4SI 0 "register_operand" "=x")
15291 (match_operator:V4SI 3 "sse_comparison_operator"
15292 [(match_operand:V4SF 1 "register_operand" "0")
15293 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
15297 "cmp%D3ss\\t{%2, %0|%0, %2}"
15298 [(set_attr "type" "sse")])
15300 (define_insn "vmmaskncmpv4sf3"
15301 [(set (match_operand:V4SI 0 "register_operand" "=x")
15304 (match_operator:V4SI 3 "sse_comparison_operator"
15305 [(match_operand:V4SF 1 "register_operand" "0")
15306 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
15307 (subreg:V4SI (match_dup 1) 0)
15310 "cmp%D3ss\\t{%2, %0|%0, %2}"
15311 [(set_attr "type" "sse")])
15313 (define_insn "sse_comi"
15314 [(set (reg:CCFP 17)
15315 (match_operator:CCFP 2 "sse_comparison_operator"
15317 (match_operand:V4SF 0 "register_operand" "x")
15318 (parallel [(const_int 0)]))
15320 (match_operand:V4SF 1 "register_operand" "x")
15321 (parallel [(const_int 0)]))]))]
15323 "comiss\\t{%2, %0|%0, %2}"
15324 [(set_attr "type" "sse")])
15326 (define_insn "sse_ucomi"
15327 [(set (reg:CCFPU 17)
15328 (match_operator:CCFPU 2 "sse_comparison_operator"
15330 (match_operand:V4SF 0 "register_operand" "x")
15331 (parallel [(const_int 0)]))
15333 (match_operand:V4SF 1 "register_operand" "x")
15334 (parallel [(const_int 0)]))]))]
15336 "ucomiss\\t{%2, %0|%0, %2}"
15337 [(set_attr "type" "sse")])
15342 (define_insn "sse_unpckhps"
15343 [(set (match_operand:V4SF 0 "register_operand" "=x")
15345 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
15346 (parallel [(const_int 2)
15350 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
15351 (parallel [(const_int 0)
15357 "unpckhps\\t{%2, %0|%0, %2}"
15358 [(set_attr "type" "sse")])
15360 (define_insn "sse_unpcklps"
15361 [(set (match_operand:V4SF 0 "register_operand" "=x")
15363 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
15364 (parallel [(const_int 0)
15368 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
15369 (parallel [(const_int 2)
15375 "unpcklps\\t{%2, %0|%0, %2}"
15376 [(set_attr "type" "sse")])
15381 (define_insn "smaxv4sf3"
15382 [(set (match_operand:V4SF 0 "register_operand" "=x")
15383 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
15384 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
15386 "maxps\\t{%2, %0|%0, %2}"
15387 [(set_attr "type" "sse")])
15389 (define_insn "vmsmaxv4sf3"
15390 [(set (match_operand:V4SF 0 "register_operand" "=x")
15391 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
15392 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
15396 "maxss\\t{%2, %0|%0, %2}"
15397 [(set_attr "type" "sse")])
15399 (define_insn "sminv4sf3"
15400 [(set (match_operand:V4SF 0 "register_operand" "=x")
15401 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
15402 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
15404 "minps\\t{%2, %0|%0, %2}"
15405 [(set_attr "type" "sse")])
15407 (define_insn "vmsminv4sf3"
15408 [(set (match_operand:V4SF 0 "register_operand" "=x")
15409 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
15410 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
15414 "minss\\t{%2, %0|%0, %2}"
15415 [(set_attr "type" "sse")])
15418 ;; SSE <-> integer/MMX conversions
15420 (define_insn "cvtpi2ps"
15421 [(set (match_operand:V4SF 0 "register_operand" "=x")
15422 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
15423 (vec_duplicate:V4SF
15424 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
15427 "cvtpi2ps\\t{%2, %0|%0, %2}"
15428 [(set_attr "type" "sse")])
15430 (define_insn "cvtps2pi"
15431 [(set (match_operand:V2SI 0 "register_operand" "=y")
15432 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
15437 "cvtps2pi\\t{%1, %0|%0, %1}"
15438 [(set_attr "type" "sse")])
15440 (define_insn "cvttps2pi"
15441 [(set (match_operand:V2SI 0 "register_operand" "=y")
15442 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
15447 "cvttps2pi\\t{%1, %0|%0, %1}"
15448 [(set_attr "type" "sse")])
15450 (define_insn "cvtsi2ss"
15451 [(set (match_operand:V4SF 0 "register_operand" "=x")
15452 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
15453 (vec_duplicate:V4SF
15454 (float:SF (match_operand:SI 2 "register_operand" "rm")))
15457 "cvtsi2ss\\t{%2, %0|%0, %2}"
15458 [(set_attr "type" "sse")])
15460 (define_insn "cvtss2si"
15461 [(set (match_operand:SI 0 "register_operand" "=y")
15462 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
15463 (parallel [(const_int 0)])))]
15465 "cvtss2si\\t{%1, %0|%0, %1}"
15466 [(set_attr "type" "sse")])
15468 (define_insn "cvttss2si"
15469 [(set (match_operand:SI 0 "register_operand" "=y")
15470 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
15471 (parallel [(const_int 0)])))]
15473 "cvttss2si\\t{%1, %0|%0, %1}"
15474 [(set_attr "type" "sse")])
15481 (define_insn "addv8qi3"
15482 [(set (match_operand:V8QI 0 "register_operand" "=y")
15483 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15484 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15486 "paddb\\t{%2, %0|%0, %2}"
15487 [(set_attr "type" "mmx")])
15489 (define_insn "addv4hi3"
15490 [(set (match_operand:V4HI 0 "register_operand" "=y")
15491 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
15492 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15494 "paddw\\t{%2, %0|%0, %2}"
15495 [(set_attr "type" "mmx")])
15497 (define_insn "addv2si3"
15498 [(set (match_operand:V2SI 0 "register_operand" "=y")
15499 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
15500 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
15502 "paddd\\t{%2, %0|%0, %2}"
15503 [(set_attr "type" "mmx")])
15505 (define_insn "ssaddv8qi3"
15506 [(set (match_operand:V8QI 0 "register_operand" "=y")
15507 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15508 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15510 "paddsb\\t{%2, %0|%0, %2}"
15511 [(set_attr "type" "mmx")])
15513 (define_insn "ssaddv4hi3"
15514 [(set (match_operand:V4HI 0 "register_operand" "=y")
15515 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
15516 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15518 "paddsw\\t{%2, %0|%0, %2}"
15519 [(set_attr "type" "mmx")])
15521 (define_insn "usaddv8qi3"
15522 [(set (match_operand:V8QI 0 "register_operand" "=y")
15523 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15524 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15526 "paddusb\\t{%2, %0|%0, %2}"
15527 [(set_attr "type" "mmx")])
15529 (define_insn "usaddv4hi3"
15530 [(set (match_operand:V4HI 0 "register_operand" "=y")
15531 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
15532 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15534 "paddusw\\t{%2, %0|%0, %2}"
15535 [(set_attr "type" "mmx")])
15537 (define_insn "subv8qi3"
15538 [(set (match_operand:V8QI 0 "register_operand" "=y")
15539 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15540 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15542 "psubb\\t{%2, %0|%0, %2}"
15543 [(set_attr "type" "mmx")])
15545 (define_insn "subv4hi3"
15546 [(set (match_operand:V4HI 0 "register_operand" "=y")
15547 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
15548 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15550 "psubw\\t{%2, %0|%0, %2}"
15551 [(set_attr "type" "mmx")])
15553 (define_insn "subv2si3"
15554 [(set (match_operand:V2SI 0 "register_operand" "=y")
15555 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
15556 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
15558 "psubd\\t{%2, %0|%0, %2}"
15559 [(set_attr "type" "mmx")])
15561 (define_insn "sssubv8qi3"
15562 [(set (match_operand:V8QI 0 "register_operand" "=y")
15563 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15564 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15566 "psubsb\\t{%2, %0|%0, %2}"
15567 [(set_attr "type" "mmx")])
15569 (define_insn "sssubv4hi3"
15570 [(set (match_operand:V4HI 0 "register_operand" "=y")
15571 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
15572 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15574 "psubsw\\t{%2, %0|%0, %2}"
15575 [(set_attr "type" "mmx")])
15577 (define_insn "ussubv8qi3"
15578 [(set (match_operand:V8QI 0 "register_operand" "=y")
15579 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15580 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15582 "psubusb\\t{%2, %0|%0, %2}"
15583 [(set_attr "type" "mmx")])
15585 (define_insn "ussubv4hi3"
15586 [(set (match_operand:V4HI 0 "register_operand" "=y")
15587 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
15588 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15590 "psubusw\\t{%2, %0|%0, %2}"
15591 [(set_attr "type" "mmx")])
15593 (define_insn "mulv4hi3"
15594 [(set (match_operand:V4HI 0 "register_operand" "=y")
15595 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
15596 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15598 "pmullw\\t{%2, %0|%0, %2}"
15599 [(set_attr "type" "mmx")])
15601 (define_insn "smulv4hi3_highpart"
15602 [(set (match_operand:V4HI 0 "register_operand" "=y")
15605 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
15606 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
15609 "pmulhw\\t{%2, %0|%0, %2}"
15610 [(set_attr "type" "mmx")])
15612 (define_insn "umulv4hi3_highpart"
15613 [(set (match_operand:V4HI 0 "register_operand" "=y")
15616 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
15617 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
15620 "pmulhuw\\t{%2, %0|%0, %2}"
15621 [(set_attr "type" "mmx")])
15623 (define_insn "mmx_pmaddwd"
15624 [(set (match_operand:V2SI 0 "register_operand" "=y")
15627 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
15628 (parallel [(const_int 0)
15630 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
15631 (parallel [(const_int 0)
15634 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
15635 (parallel [(const_int 1)
15637 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
15638 (parallel [(const_int 1)
15639 (const_int 3)]))))))]
15641 "pmaddwd\\t{%2, %0|%0, %2}"
15642 [(set_attr "type" "mmx")])
15645 ;; MMX logical operations
15646 ;; Note we don't want to declare these as regular iordi3 insns to prevent
15647 ;; normal code that also wants to use the FPU from getting broken.
15648 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
15649 (define_insn "mmx_iordi3"
15650 [(set (match_operand:DI 0 "register_operand" "=y")
15652 [(ior:DI (match_operand:DI 1 "register_operand" "0")
15653 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
15655 "por\\t{%2, %0|%0, %2}"
15656 [(set_attr "type" "mmx")])
15658 (define_insn "mmx_xordi3"
15659 [(set (match_operand:DI 0 "register_operand" "=y")
15661 [(xor:DI (match_operand:DI 1 "register_operand" "0")
15662 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
15664 "pxor\\t{%2, %0|%0, %2}"
15665 [(set_attr "type" "mmx")])
15667 ;; Same as pxor, but don't show input operands so that we don't think
15669 (define_insn "mmx_clrdi"
15670 [(set (match_operand:DI 0 "register_operand" "=y")
15671 (unspec:DI [(const_int 0)] 45))]
15673 "pxor\\t{%0, %0|%0, %0}"
15674 [(set_attr "type" "mmx")])
15676 (define_insn "mmx_anddi3"
15677 [(set (match_operand:DI 0 "register_operand" "=y")
15679 [(and:DI (match_operand:DI 1 "register_operand" "0")
15680 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
15682 "pand\\t{%2, %0|%0, %2}"
15683 [(set_attr "type" "mmx")])
15685 (define_insn "mmx_nanddi3"
15686 [(set (match_operand:DI 0 "register_operand" "=y")
15688 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
15689 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
15691 "pandn\\t{%2, %0|%0, %2}"
15692 [(set_attr "type" "mmx")])
15695 ;; MMX unsigned averages/sum of absolute differences
15697 (define_insn "mmx_uavgv8qi3"
15698 [(set (match_operand:V8QI 0 "register_operand" "=y")
15700 (plus:V8QI (plus:V8QI
15701 (match_operand:V8QI 1 "register_operand" "0")
15702 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
15703 (vec_const:V8QI (parallel [(const_int 1)
15713 "pavgb\\t{%2, %0|%0, %2}"
15714 [(set_attr "type" "sse")])
15716 (define_insn "mmx_uavgv4hi3"
15717 [(set (match_operand:V4HI 0 "register_operand" "=y")
15719 (plus:V4HI (plus:V4HI
15720 (match_operand:V4HI 1 "register_operand" "0")
15721 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
15722 (vec_const:V4HI (parallel [(const_int 1)
15728 "pavgw\\t{%2, %0|%0, %2}"
15729 [(set_attr "type" "sse")])
15731 (define_insn "mmx_psadbw"
15732 [(set (match_operand:V8QI 0 "register_operand" "=y")
15733 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
15734 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
15736 "psadbw\\t{%2, %0|%0, %2}"
15737 [(set_attr "type" "sse")])
15740 ;; MMX insert/extract/shuffle
15742 (define_insn "mmx_pinsrw"
15743 [(set (match_operand:V4HI 0 "register_operand" "=y")
15744 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
15745 (vec_duplicate:V4HI
15746 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
15747 (match_operand:SI 3 "immediate_operand" "i")))]
15749 "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
15750 [(set_attr "type" "sse")])
15752 (define_insn "mmx_pextrw"
15753 [(set (match_operand:SI 0 "register_operand" "=r")
15754 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
15756 [(match_operand:SI 2 "immediate_operand" "i")]))))]
15758 "pextrw\\t{%2, %1, %0|%0, %1, %2}"
15759 [(set_attr "type" "sse")])
15761 (define_insn "mmx_pshufw"
15762 [(set (match_operand:V4HI 0 "register_operand" "=y")
15763 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
15764 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
15765 (match_operand:SI 3 "immediate_operand" "i")] 41))]
15767 "pshufw\\t{%3, %2, %0|%0, %2, %3}"
15768 [(set_attr "type" "sse")])
15771 ;; MMX mask-generating comparisons
15773 (define_insn "eqv8qi3"
15774 [(set (match_operand:V8QI 0 "register_operand" "=y")
15775 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
15776 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15778 "pcmpeqb\\t{%2, %0|%0, %2}"
15779 [(set_attr "type" "mmx")])
15781 (define_insn "eqv4hi3"
15782 [(set (match_operand:V4HI 0 "register_operand" "=y")
15783 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
15784 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15786 "pcmpeqw\\t{%2, %0|%0, %2}"
15787 [(set_attr "type" "mmx")])
15789 (define_insn "eqv2si3"
15790 [(set (match_operand:V2SI 0 "register_operand" "=y")
15791 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
15792 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
15794 "pcmpeqd\\t{%2, %0|%0, %2}"
15795 [(set_attr "type" "mmx")])
15797 (define_insn "gtv8qi3"
15798 [(set (match_operand:V8QI 0 "register_operand" "=y")
15799 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
15800 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15802 "pcmpgtb\\t{%2, %0|%0, %2}"
15803 [(set_attr "type" "mmx")])
15805 (define_insn "gtv4hi3"
15806 [(set (match_operand:V4HI 0 "register_operand" "=y")
15807 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
15808 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15810 "pcmpgtw\\t{%2, %0|%0, %2}"
15811 [(set_attr "type" "mmx")])
15813 (define_insn "gtv2si3"
15814 [(set (match_operand:V2SI 0 "register_operand" "=y")
15815 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
15816 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
15818 "pcmpgtd\\t{%2, %0|%0, %2}"
15819 [(set_attr "type" "mmx")])
15822 ;; MMX max/min insns
15824 (define_insn "umaxv8qi3"
15825 [(set (match_operand:V8QI 0 "register_operand" "=y")
15826 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
15827 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15829 "pmaxub\\t{%2, %0|%0, %2}"
15830 [(set_attr "type" "sse")])
15832 (define_insn "smaxv4hi3"
15833 [(set (match_operand:V4HI 0 "register_operand" "=y")
15834 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
15835 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15837 "pmaxsw\\t{%2, %0|%0, %2}"
15838 [(set_attr "type" "sse")])
15840 (define_insn "uminv8qi3"
15841 [(set (match_operand:V8QI 0 "register_operand" "=y")
15842 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
15843 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
15845 "pminub\\t{%2, %0|%0, %2}"
15846 [(set_attr "type" "sse")])
15848 (define_insn "sminv4hi3"
15849 [(set (match_operand:V4HI 0 "register_operand" "=y")
15850 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
15851 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
15853 "pminsw\\t{%2, %0|%0, %2}"
15854 [(set_attr "type" "sse")])
15859 (define_insn "ashrv4hi3"
15860 [(set (match_operand:V4HI 0 "register_operand" "=y")
15861 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
15862 (match_operand:DI 2 "nonmemory_operand" "yi")))]
15864 "psraw\\t{%2, %0|%0, %2}"
15865 [(set_attr "type" "mmx")])
15867 (define_insn "ashrv2si3"
15868 [(set (match_operand:V2SI 0 "register_operand" "=y")
15869 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
15870 (match_operand:DI 2 "nonmemory_operand" "yi")))]
15872 "psrad\\t{%2, %0|%0, %2}"
15873 [(set_attr "type" "mmx")])
15875 (define_insn "lshrv4hi3"
15876 [(set (match_operand:V4HI 0 "register_operand" "=y")
15877 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
15878 (match_operand:DI 2 "nonmemory_operand" "yi")))]
15880 "psrlw\\t{%2, %0|%0, %2}"
15881 [(set_attr "type" "mmx")])
15883 (define_insn "lshrv2si3"
15884 [(set (match_operand:V2SI 0 "register_operand" "=y")
15885 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
15886 (match_operand:DI 2 "nonmemory_operand" "yi")))]
15888 "psrld\\t{%2, %0|%0, %2}"
15889 [(set_attr "type" "mmx")])
15891 ;; See logical MMX insns.
15892 (define_insn "mmx_lshrdi3"
15893 [(set (match_operand:DI 0 "register_operand" "=y")
15895 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
15896 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
15898 "psrlq\\t{%2, %0|%0, %2}"
15899 [(set_attr "type" "mmx")])
15901 (define_insn "ashlv4hi3"
15902 [(set (match_operand:V4HI 0 "register_operand" "=y")
15903 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
15904 (match_operand:DI 2 "nonmemory_operand" "yi")))]
15906 "psllw\\t{%2, %0|%0, %2}"
15907 [(set_attr "type" "mmx")])
15909 (define_insn "ashlv2si3"
15910 [(set (match_operand:V2SI 0 "register_operand" "=y")
15911 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
15912 (match_operand:DI 2 "nonmemory_operand" "yi")))]
15914 "pslld\\t{%2, %0|%0, %2}"
15915 [(set_attr "type" "mmx")])
15917 ;; See logical MMX insns.
15918 (define_insn "mmx_ashldi3"
15919 [(set (match_operand:DI 0 "register_operand" "=y")
15921 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
15922 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
15924 "psllq\\t{%2, %0|%0, %2}"
15925 [(set_attr "type" "mmx")])
15928 ;; MMX pack/unpack insns.
15930 (define_insn "mmx_packsswb"
15931 [(set (match_operand:V8QI 0 "register_operand" "=y")
15933 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
15934 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
15936 "packsswb\\t{%2, %0|%0, %2}"
15937 [(set_attr "type" "mmx")])
15939 (define_insn "mmx_packssdw"
15940 [(set (match_operand:V4HI 0 "register_operand" "=y")
15942 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
15943 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
15945 "packssdw\\t{%2, %0|%0, %2}"
15946 [(set_attr "type" "mmx")])
15948 (define_insn "mmx_packuswb"
15949 [(set (match_operand:V8QI 0 "register_operand" "=y")
15951 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
15952 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
15954 "packuswb\\t{%2, %0|%0, %2}"
15955 [(set_attr "type" "mmx")])
15957 (define_insn "mmx_punpckhbw"
15958 [(set (match_operand:V8QI 0 "register_operand" "=y")
15960 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
15961 (parallel [(const_int 4)
15969 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
15970 (parallel [(const_int 0)
15980 "punpckhbw\\t{%2, %0|%0, %2}"
15981 [(set_attr "type" "mmx")])
15983 (define_insn "mmx_punpckhwd"
15984 [(set (match_operand:V4HI 0 "register_operand" "=y")
15986 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
15987 (parallel [(const_int 0)
15991 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
15992 (parallel [(const_int 2)
15998 "punpckhwd\\t{%2, %0|%0, %2}"
15999 [(set_attr "type" "mmx")])
16001 (define_insn "mmx_punpckhdq"
16002 [(set (match_operand:V2SI 0 "register_operand" "=y")
16004 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
16005 (parallel [(const_int 0)
16007 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
16008 (parallel [(const_int 1)
16012 "punpckhdq\\t{%2, %0|%0, %2}"
16013 [(set_attr "type" "mmx")])
16015 (define_insn "mmx_punpcklbw"
16016 [(set (match_operand:V8QI 0 "register_operand" "=y")
16018 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
16019 (parallel [(const_int 0)
16027 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
16028 (parallel [(const_int 4)
16038 "punpcklbw\\t{%2, %0|%0, %2}"
16039 [(set_attr "type" "mmx")])
16041 (define_insn "mmx_punpcklwd"
16042 [(set (match_operand:V4HI 0 "register_operand" "=y")
16044 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
16045 (parallel [(const_int 2)
16049 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
16050 (parallel [(const_int 0)
16056 "punpcklwd\\t{%2, %0|%0, %2}"
16057 [(set_attr "type" "mmx")])
16059 (define_insn "mmx_punpckldq"
16060 [(set (match_operand:V2SI 0 "register_operand" "=y")
16062 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
16063 (parallel [(const_int 1)
16065 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
16066 (parallel [(const_int 0)
16070 "punpckldq\\t{%2, %0|%0, %2}"
16071 [(set_attr "type" "mmx")])
16074 ;; Miscellaneous stuff
16076 (define_insn "emms"
16077 [(unspec_volatile [(const_int 0)] 31)
16078 (clobber (reg:XF 8))
16079 (clobber (reg:XF 9))
16080 (clobber (reg:XF 10))
16081 (clobber (reg:XF 11))
16082 (clobber (reg:XF 12))
16083 (clobber (reg:XF 13))
16084 (clobber (reg:XF 14))
16085 (clobber (reg:XF 15))
16086 (clobber (reg:DI 29))
16087 (clobber (reg:DI 30))
16088 (clobber (reg:DI 31))
16089 (clobber (reg:DI 32))
16090 (clobber (reg:DI 33))
16091 (clobber (reg:DI 34))
16092 (clobber (reg:DI 35))
16093 (clobber (reg:DI 36))]
16096 [(set_attr "type" "mmx")
16097 (set_attr "memory" "unknown")])
16099 (define_insn "ldmxcsr"
16100 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
16103 [(set_attr "type" "mmx")])
16105 (define_insn "stmxcsr"
16106 [(set (match_operand:SI 0 "memory_operand" "=m")
16107 (unspec_volatile:SI [(const_int 0)] 40))]
16110 [(set_attr "type" "mmx")])
16112 (define_expand "sfence"
16113 [(set (match_dup 0)
16114 (unspec:BLK [(match_dup 0)] 44))]
16118 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
16119 MEM_VOLATILE_P (operands[0]) = 1;
16122 (define_insn "*sfence_insn"
16123 [(set (match_operand:BLK 0 "" "")
16124 (unspec:BLK [(match_dup 0)] 44))]
16127 [(set_attr "type" "sse")
16128 (set_attr "memory" "unknown")])
16130 (define_insn "prefetch"
16131 [(unspec [(match_operand:SI 0 "address_operand" "p")
16132 (match_operand:SI 1 "immediate_operand" "n")] 35)]
16136 switch (INTVAL (operands[1]))
16139 return \"prefetchnta\\t%a0\";
16141 return \"prefetcht0\\t%a0\";
16143 return \"prefetcht1\\t%a0\";
16145 return \"prefetcht2\\t%a0\";
16150 [(set_attr "type" "sse")])