1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_PROBE 10)
67 (UNSPEC_STACK_ALLOC 11)
69 (UNSPEC_SSE_PROLOGUE_SAVE 13)
74 (UNSPEC_TLS_LD_BASE 17)
76 ; Other random patterns
86 ; For SSE/MMX support:
97 (UNSPEC_NOP 45) ; prevents combiner cleverness
129 [(UNSPECV_BLOCKAGE 0)
130 (UNSPECV_EH_RETURN 13)
141 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
144 ;; In C guard expressions, put expressions which may be compile-time
145 ;; constants first. This allows for better optimization. For
146 ;; example, write "TARGET_64BIT && reload_completed", not
147 ;; "reload_completed && TARGET_64BIT".
150 ;; Processor type. This attribute must exactly match the processor_type
151 ;; enumeration in i386.h.
152 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
153 (const (symbol_ref "ix86_tune")))
155 ;; A basic instruction type. Refinements due to arguments to be
156 ;; provided in other attributes.
159 alu,alu1,negnot,imov,imovx,lea,
160 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
161 icmp,test,ibr,setcc,icmov,
162 push,pop,call,callv,leave,
164 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
165 sselog,sseiadd,sseishft,sseimul,
166 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
167 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
168 (const_string "other"))
170 ;; Main data type used by the insn
172 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
173 (const_string "unknown"))
175 ;; The CPU unit operations uses.
176 (define_attr "unit" "integer,i387,sse,mmx,unknown"
177 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
178 (const_string "i387")
179 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
180 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
182 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
184 (eq_attr "type" "other")
185 (const_string "unknown")]
186 (const_string "integer")))
188 ;; The (bounding maximum) length of an instruction immediate.
189 (define_attr "length_immediate" ""
190 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
192 (eq_attr "unit" "i387,sse,mmx")
194 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
196 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
197 (eq_attr "type" "imov,test")
198 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
199 (eq_attr "type" "call")
200 (if_then_else (match_operand 0 "constant_call_address_operand" "")
203 (eq_attr "type" "callv")
204 (if_then_else (match_operand 1 "constant_call_address_operand" "")
207 ;; We don't know the size before shorten_branches. Expect
208 ;; the instruction to fit for better scheduling.
209 (eq_attr "type" "ibr")
212 (symbol_ref "/* Update immediate_length and other attributes! */
215 ;; The (bounding maximum) length of an instruction address.
216 (define_attr "length_address" ""
217 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
219 (and (eq_attr "type" "call")
220 (match_operand 0 "constant_call_address_operand" ""))
222 (and (eq_attr "type" "callv")
223 (match_operand 1 "constant_call_address_operand" ""))
226 (symbol_ref "ix86_attr_length_address_default (insn)")))
228 ;; Set when length prefix is used.
229 (define_attr "prefix_data16" ""
230 (if_then_else (ior (eq_attr "mode" "HI")
231 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
235 ;; Set when string REP prefix is used.
236 (define_attr "prefix_rep" ""
237 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
241 ;; Set when 0f opcode prefix is used.
242 (define_attr "prefix_0f" ""
244 (ior (eq_attr "type" "imovx,setcc,icmov")
245 (eq_attr "unit" "sse,mmx"))
249 ;; Set when 0f opcode prefix is used.
250 (define_attr "prefix_rex" ""
251 (cond [(and (eq_attr "mode" "DI")
252 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
254 (and (eq_attr "mode" "QI")
255 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
258 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
264 ;; Set when modrm byte is used.
265 (define_attr "modrm" ""
266 (cond [(eq_attr "type" "str,cld,leave")
268 (eq_attr "unit" "i387")
270 (and (eq_attr "type" "incdec")
271 (ior (match_operand:SI 1 "register_operand" "")
272 (match_operand:HI 1 "register_operand" "")))
274 (and (eq_attr "type" "push")
275 (not (match_operand 1 "memory_operand" "")))
277 (and (eq_attr "type" "pop")
278 (not (match_operand 0 "memory_operand" "")))
280 (and (eq_attr "type" "imov")
281 (and (match_operand 0 "register_operand" "")
282 (match_operand 1 "immediate_operand" "")))
284 (and (eq_attr "type" "call")
285 (match_operand 0 "constant_call_address_operand" ""))
287 (and (eq_attr "type" "callv")
288 (match_operand 1 "constant_call_address_operand" ""))
293 ;; The (bounding maximum) length of an instruction in bytes.
294 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
295 ;; to split it and compute proper length as for other insns.
296 (define_attr "length" ""
297 (cond [(eq_attr "type" "other,multi,fistp")
299 (eq_attr "type" "fcmp")
301 (eq_attr "unit" "i387")
303 (plus (attr "prefix_data16")
304 (attr "length_address")))]
305 (plus (plus (attr "modrm")
306 (plus (attr "prefix_0f")
307 (plus (attr "prefix_rex")
309 (plus (attr "prefix_rep")
310 (plus (attr "prefix_data16")
311 (plus (attr "length_immediate")
312 (attr "length_address")))))))
314 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
315 ;; `store' if there is a simple memory reference therein, or `unknown'
316 ;; if the instruction is complex.
318 (define_attr "memory" "none,load,store,both,unknown"
319 (cond [(eq_attr "type" "other,multi,str")
320 (const_string "unknown")
321 (eq_attr "type" "lea,fcmov,fpspc,cld")
322 (const_string "none")
323 (eq_attr "type" "fistp,leave")
324 (const_string "both")
325 (eq_attr "type" "push")
326 (if_then_else (match_operand 1 "memory_operand" "")
327 (const_string "both")
328 (const_string "store"))
329 (eq_attr "type" "pop")
330 (if_then_else (match_operand 0 "memory_operand" "")
331 (const_string "both")
332 (const_string "load"))
333 (eq_attr "type" "setcc")
334 (if_then_else (match_operand 0 "memory_operand" "")
335 (const_string "store")
336 (const_string "none"))
337 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
338 (if_then_else (ior (match_operand 0 "memory_operand" "")
339 (match_operand 1 "memory_operand" ""))
340 (const_string "load")
341 (const_string "none"))
342 (eq_attr "type" "ibr")
343 (if_then_else (match_operand 0 "memory_operand" "")
344 (const_string "load")
345 (const_string "none"))
346 (eq_attr "type" "call")
347 (if_then_else (match_operand 0 "constant_call_address_operand" "")
348 (const_string "none")
349 (const_string "load"))
350 (eq_attr "type" "callv")
351 (if_then_else (match_operand 1 "constant_call_address_operand" "")
352 (const_string "none")
353 (const_string "load"))
354 (and (eq_attr "type" "alu1,negnot,ishift1")
355 (match_operand 1 "memory_operand" ""))
356 (const_string "both")
357 (and (match_operand 0 "memory_operand" "")
358 (match_operand 1 "memory_operand" ""))
359 (const_string "both")
360 (match_operand 0 "memory_operand" "")
361 (const_string "store")
362 (match_operand 1 "memory_operand" "")
363 (const_string "load")
365 "!alu1,negnot,ishift1,
366 imov,imovx,icmp,test,
368 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
369 mmx,mmxmov,mmxcmp,mmxcvt")
370 (match_operand 2 "memory_operand" ""))
371 (const_string "load")
372 (and (eq_attr "type" "icmov")
373 (match_operand 3 "memory_operand" ""))
374 (const_string "load")
376 (const_string "none")))
378 ;; Indicates if an instruction has both an immediate and a displacement.
380 (define_attr "imm_disp" "false,true,unknown"
381 (cond [(eq_attr "type" "other,multi")
382 (const_string "unknown")
383 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
384 (and (match_operand 0 "memory_displacement_operand" "")
385 (match_operand 1 "immediate_operand" "")))
386 (const_string "true")
387 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
388 (and (match_operand 0 "memory_displacement_operand" "")
389 (match_operand 2 "immediate_operand" "")))
390 (const_string "true")
392 (const_string "false")))
394 ;; Indicates if an FP operation has an integer source.
396 (define_attr "fp_int_src" "false,true"
397 (const_string "false"))
399 ;; Describe a user's asm statement.
400 (define_asm_attributes
401 [(set_attr "length" "128")
402 (set_attr "type" "multi")])
404 (include "pentium.md")
407 (include "athlon.md")
409 ;; Compare instructions.
411 ;; All compare insns have expanders that save the operands away without
412 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
413 ;; after the cmp) will actually emit the cmpM.
415 (define_expand "cmpdi"
417 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
418 (match_operand:DI 1 "x86_64_general_operand" "")))]
421 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
422 operands[0] = force_reg (DImode, operands[0]);
423 ix86_compare_op0 = operands[0];
424 ix86_compare_op1 = operands[1];
428 (define_expand "cmpsi"
430 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
431 (match_operand:SI 1 "general_operand" "")))]
434 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
435 operands[0] = force_reg (SImode, operands[0]);
436 ix86_compare_op0 = operands[0];
437 ix86_compare_op1 = operands[1];
441 (define_expand "cmphi"
443 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
444 (match_operand:HI 1 "general_operand" "")))]
447 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
448 operands[0] = force_reg (HImode, operands[0]);
449 ix86_compare_op0 = operands[0];
450 ix86_compare_op1 = operands[1];
454 (define_expand "cmpqi"
456 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
457 (match_operand:QI 1 "general_operand" "")))]
460 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
461 operands[0] = force_reg (QImode, operands[0]);
462 ix86_compare_op0 = operands[0];
463 ix86_compare_op1 = operands[1];
467 (define_insn "cmpdi_ccno_1_rex64"
469 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
470 (match_operand:DI 1 "const0_operand" "n,n")))]
471 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
473 test{q}\t{%0, %0|%0, %0}
474 cmp{q}\t{%1, %0|%0, %1}"
475 [(set_attr "type" "test,icmp")
476 (set_attr "length_immediate" "0,1")
477 (set_attr "mode" "DI")])
479 (define_insn "*cmpdi_minus_1_rex64"
481 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
482 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
484 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
485 "cmp{q}\t{%1, %0|%0, %1}"
486 [(set_attr "type" "icmp")
487 (set_attr "mode" "DI")])
489 (define_expand "cmpdi_1_rex64"
491 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
492 (match_operand:DI 1 "general_operand" "")))]
496 (define_insn "cmpdi_1_insn_rex64"
498 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
499 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
500 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
501 "cmp{q}\t{%1, %0|%0, %1}"
502 [(set_attr "type" "icmp")
503 (set_attr "mode" "DI")])
506 (define_insn "*cmpsi_ccno_1"
508 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
509 (match_operand:SI 1 "const0_operand" "n,n")))]
510 "ix86_match_ccmode (insn, CCNOmode)"
512 test{l}\t{%0, %0|%0, %0}
513 cmp{l}\t{%1, %0|%0, %1}"
514 [(set_attr "type" "test,icmp")
515 (set_attr "length_immediate" "0,1")
516 (set_attr "mode" "SI")])
518 (define_insn "*cmpsi_minus_1"
520 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
521 (match_operand:SI 1 "general_operand" "ri,mr"))
523 "ix86_match_ccmode (insn, CCGOCmode)"
524 "cmp{l}\t{%1, %0|%0, %1}"
525 [(set_attr "type" "icmp")
526 (set_attr "mode" "SI")])
528 (define_expand "cmpsi_1"
530 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
531 (match_operand:SI 1 "general_operand" "ri,mr")))]
535 (define_insn "*cmpsi_1_insn"
537 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
538 (match_operand:SI 1 "general_operand" "ri,mr")))]
539 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
540 && ix86_match_ccmode (insn, CCmode)"
541 "cmp{l}\t{%1, %0|%0, %1}"
542 [(set_attr "type" "icmp")
543 (set_attr "mode" "SI")])
545 (define_insn "*cmphi_ccno_1"
547 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
548 (match_operand:HI 1 "const0_operand" "n,n")))]
549 "ix86_match_ccmode (insn, CCNOmode)"
551 test{w}\t{%0, %0|%0, %0}
552 cmp{w}\t{%1, %0|%0, %1}"
553 [(set_attr "type" "test,icmp")
554 (set_attr "length_immediate" "0,1")
555 (set_attr "mode" "HI")])
557 (define_insn "*cmphi_minus_1"
559 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
560 (match_operand:HI 1 "general_operand" "ri,mr"))
562 "ix86_match_ccmode (insn, CCGOCmode)"
563 "cmp{w}\t{%1, %0|%0, %1}"
564 [(set_attr "type" "icmp")
565 (set_attr "mode" "HI")])
567 (define_insn "*cmphi_1"
569 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
570 (match_operand:HI 1 "general_operand" "ri,mr")))]
571 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
572 && ix86_match_ccmode (insn, CCmode)"
573 "cmp{w}\t{%1, %0|%0, %1}"
574 [(set_attr "type" "icmp")
575 (set_attr "mode" "HI")])
577 (define_insn "*cmpqi_ccno_1"
579 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
580 (match_operand:QI 1 "const0_operand" "n,n")))]
581 "ix86_match_ccmode (insn, CCNOmode)"
583 test{b}\t{%0, %0|%0, %0}
584 cmp{b}\t{$0, %0|%0, 0}"
585 [(set_attr "type" "test,icmp")
586 (set_attr "length_immediate" "0,1")
587 (set_attr "mode" "QI")])
589 (define_insn "*cmpqi_1"
591 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
592 (match_operand:QI 1 "general_operand" "qi,mq")))]
593 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
594 && ix86_match_ccmode (insn, CCmode)"
595 "cmp{b}\t{%1, %0|%0, %1}"
596 [(set_attr "type" "icmp")
597 (set_attr "mode" "QI")])
599 (define_insn "*cmpqi_minus_1"
601 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
602 (match_operand:QI 1 "general_operand" "qi,mq"))
604 "ix86_match_ccmode (insn, CCGOCmode)"
605 "cmp{b}\t{%1, %0|%0, %1}"
606 [(set_attr "type" "icmp")
607 (set_attr "mode" "QI")])
609 (define_insn "*cmpqi_ext_1"
612 (match_operand:QI 0 "general_operand" "Qm")
615 (match_operand 1 "ext_register_operand" "Q")
618 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
619 "cmp{b}\t{%h1, %0|%0, %h1}"
620 [(set_attr "type" "icmp")
621 (set_attr "mode" "QI")])
623 (define_insn "*cmpqi_ext_1_rex64"
626 (match_operand:QI 0 "register_operand" "Q")
629 (match_operand 1 "ext_register_operand" "Q")
632 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
633 "cmp{b}\t{%h1, %0|%0, %h1}"
634 [(set_attr "type" "icmp")
635 (set_attr "mode" "QI")])
637 (define_insn "*cmpqi_ext_2"
642 (match_operand 0 "ext_register_operand" "Q")
645 (match_operand:QI 1 "const0_operand" "n")))]
646 "ix86_match_ccmode (insn, CCNOmode)"
648 [(set_attr "type" "test")
649 (set_attr "length_immediate" "0")
650 (set_attr "mode" "QI")])
652 (define_expand "cmpqi_ext_3"
657 (match_operand 0 "ext_register_operand" "")
660 (match_operand:QI 1 "general_operand" "")))]
664 (define_insn "cmpqi_ext_3_insn"
669 (match_operand 0 "ext_register_operand" "Q")
672 (match_operand:QI 1 "general_operand" "Qmn")))]
673 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
674 "cmp{b}\t{%1, %h0|%h0, %1}"
675 [(set_attr "type" "icmp")
676 (set_attr "mode" "QI")])
678 (define_insn "cmpqi_ext_3_insn_rex64"
683 (match_operand 0 "ext_register_operand" "Q")
686 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
687 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
688 "cmp{b}\t{%1, %h0|%h0, %1}"
689 [(set_attr "type" "icmp")
690 (set_attr "mode" "QI")])
692 (define_insn "*cmpqi_ext_4"
697 (match_operand 0 "ext_register_operand" "Q")
702 (match_operand 1 "ext_register_operand" "Q")
705 "ix86_match_ccmode (insn, CCmode)"
706 "cmp{b}\t{%h1, %h0|%h0, %h1}"
707 [(set_attr "type" "icmp")
708 (set_attr "mode" "QI")])
710 ;; These implement float point compares.
711 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
712 ;; which would allow mix and match FP modes on the compares. Which is what
713 ;; the old patterns did, but with many more of them.
715 (define_expand "cmpxf"
717 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
718 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
721 ix86_compare_op0 = operands[0];
722 ix86_compare_op1 = operands[1];
726 (define_expand "cmpdf"
728 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
729 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
730 "TARGET_80387 || TARGET_SSE2"
732 ix86_compare_op0 = operands[0];
733 ix86_compare_op1 = operands[1];
737 (define_expand "cmpsf"
739 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
740 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
741 "TARGET_80387 || TARGET_SSE"
743 ix86_compare_op0 = operands[0];
744 ix86_compare_op1 = operands[1];
748 ;; FP compares, step 1:
749 ;; Set the FP condition codes.
751 ;; CCFPmode compare with exceptions
752 ;; CCFPUmode compare with no exceptions
754 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
755 ;; and that fp moves clobber the condition codes, and that there is
756 ;; currently no way to describe this fact to reg-stack. So there are
757 ;; no splitters yet for this.
759 ;; %%% YIKES! This scheme does not retain a strong connection between
760 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
761 ;; work! Only allow tos/mem with tos in op 0.
763 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
764 ;; things aren't as bad as they sound...
766 (define_insn "*cmpfp_0"
767 [(set (match_operand:HI 0 "register_operand" "=a")
769 [(compare:CCFP (match_operand 1 "register_operand" "f")
770 (match_operand 2 "const0_operand" "X"))]
773 && FLOAT_MODE_P (GET_MODE (operands[1]))
774 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
776 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
777 return "ftst\;fnstsw\t%0\;fstp\t%y0";
779 return "ftst\;fnstsw\t%0";
781 [(set_attr "type" "multi")
783 (cond [(match_operand:SF 1 "" "")
785 (match_operand:DF 1 "" "")
788 (const_string "XF")))])
790 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
791 ;; used to manage the reg stack popping would not be preserved.
793 (define_insn "*cmpfp_2_sf"
796 (match_operand:SF 0 "register_operand" "f")
797 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
799 "* return output_fp_compare (insn, operands, 0, 0);"
800 [(set_attr "type" "fcmp")
801 (set_attr "mode" "SF")])
803 (define_insn "*cmpfp_2_sf_1"
804 [(set (match_operand:HI 0 "register_operand" "=a")
807 (match_operand:SF 1 "register_operand" "f")
808 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
811 "* return output_fp_compare (insn, operands, 2, 0);"
812 [(set_attr "type" "fcmp")
813 (set_attr "mode" "SF")])
815 (define_insn "*cmpfp_2_df"
818 (match_operand:DF 0 "register_operand" "f")
819 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
821 "* return output_fp_compare (insn, operands, 0, 0);"
822 [(set_attr "type" "fcmp")
823 (set_attr "mode" "DF")])
825 (define_insn "*cmpfp_2_df_1"
826 [(set (match_operand:HI 0 "register_operand" "=a")
829 (match_operand:DF 1 "register_operand" "f")
830 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
833 "* return output_fp_compare (insn, operands, 2, 0);"
834 [(set_attr "type" "multi")
835 (set_attr "mode" "DF")])
837 (define_insn "*cmpfp_2_xf"
840 (match_operand:XF 0 "register_operand" "f")
841 (match_operand:XF 1 "register_operand" "f")))]
843 "* return output_fp_compare (insn, operands, 0, 0);"
844 [(set_attr "type" "fcmp")
845 (set_attr "mode" "XF")])
847 (define_insn "*cmpfp_2_xf_1"
848 [(set (match_operand:HI 0 "register_operand" "=a")
851 (match_operand:XF 1 "register_operand" "f")
852 (match_operand:XF 2 "register_operand" "f"))]
855 "* return output_fp_compare (insn, operands, 2, 0);"
856 [(set_attr "type" "multi")
857 (set_attr "mode" "XF")])
859 (define_insn "*cmpfp_2u"
862 (match_operand 0 "register_operand" "f")
863 (match_operand 1 "register_operand" "f")))]
865 && FLOAT_MODE_P (GET_MODE (operands[0]))
866 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
867 "* return output_fp_compare (insn, operands, 0, 1);"
868 [(set_attr "type" "fcmp")
870 (cond [(match_operand:SF 1 "" "")
872 (match_operand:DF 1 "" "")
875 (const_string "XF")))])
877 (define_insn "*cmpfp_2u_1"
878 [(set (match_operand:HI 0 "register_operand" "=a")
881 (match_operand 1 "register_operand" "f")
882 (match_operand 2 "register_operand" "f"))]
885 && FLOAT_MODE_P (GET_MODE (operands[1]))
886 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
887 "* return output_fp_compare (insn, operands, 2, 1);"
888 [(set_attr "type" "multi")
890 (cond [(match_operand:SF 1 "" "")
892 (match_operand:DF 1 "" "")
895 (const_string "XF")))])
897 ;; Patterns to match the SImode-in-memory ficom instructions.
899 ;; %%% Play games with accepting gp registers, as otherwise we have to
900 ;; force them to memory during rtl generation, which is no good. We
901 ;; can get rid of this once we teach reload to do memory input reloads
904 (define_insn "*ficom_1"
907 (match_operand 0 "register_operand" "f,f")
908 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
909 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
910 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
913 ;; Split the not-really-implemented gp register case into a
914 ;; push-op-pop sequence.
916 ;; %%% This is most efficient, but am I gonna get in trouble
917 ;; for separating cc0_setter and cc0_user?
922 (match_operand:SF 0 "register_operand" "")
923 (float (match_operand:SI 1 "register_operand" ""))))]
924 "0 && TARGET_80387 && reload_completed"
925 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
926 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
927 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
928 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
929 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
930 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
932 ;; FP compares, step 2
933 ;; Move the fpsw to ax.
935 (define_insn "*x86_fnstsw_1"
936 [(set (match_operand:HI 0 "register_operand" "=a")
937 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
940 [(set_attr "length" "2")
941 (set_attr "mode" "SI")
942 (set_attr "unit" "i387")
943 (set_attr "ppro_uops" "few")])
945 ;; FP compares, step 3
946 ;; Get ax into flags, general case.
948 (define_insn "x86_sahf_1"
950 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
953 [(set_attr "length" "1")
954 (set_attr "athlon_decode" "vector")
955 (set_attr "mode" "SI")
956 (set_attr "ppro_uops" "one")])
958 ;; Pentium Pro can do steps 1 through 3 in one go.
960 (define_insn "*cmpfp_i"
962 (compare:CCFP (match_operand 0 "register_operand" "f")
963 (match_operand 1 "register_operand" "f")))]
964 "TARGET_80387 && TARGET_CMOVE
965 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
966 && FLOAT_MODE_P (GET_MODE (operands[0]))
967 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
968 "* return output_fp_compare (insn, operands, 1, 0);"
969 [(set_attr "type" "fcmp")
971 (cond [(match_operand:SF 1 "" "")
973 (match_operand:DF 1 "" "")
976 (const_string "XF")))
977 (set_attr "athlon_decode" "vector")])
979 (define_insn "*cmpfp_i_sse"
981 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
982 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
984 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
985 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
986 "* return output_fp_compare (insn, operands, 1, 0);"
987 [(set_attr "type" "fcmp,ssecomi")
989 (if_then_else (match_operand:SF 1 "" "")
991 (const_string "DF")))
992 (set_attr "athlon_decode" "vector")])
994 (define_insn "*cmpfp_i_sse_only"
996 (compare:CCFP (match_operand 0 "register_operand" "x")
997 (match_operand 1 "nonimmediate_operand" "xm")))]
998 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
999 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1000 "* return output_fp_compare (insn, operands, 1, 0);"
1001 [(set_attr "type" "ssecomi")
1003 (if_then_else (match_operand:SF 1 "" "")
1005 (const_string "DF")))
1006 (set_attr "athlon_decode" "vector")])
1008 (define_insn "*cmpfp_iu"
1009 [(set (reg:CCFPU 17)
1010 (compare:CCFPU (match_operand 0 "register_operand" "f")
1011 (match_operand 1 "register_operand" "f")))]
1012 "TARGET_80387 && TARGET_CMOVE
1013 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1014 && FLOAT_MODE_P (GET_MODE (operands[0]))
1015 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1016 "* return output_fp_compare (insn, operands, 1, 1);"
1017 [(set_attr "type" "fcmp")
1019 (cond [(match_operand:SF 1 "" "")
1021 (match_operand:DF 1 "" "")
1024 (const_string "XF")))
1025 (set_attr "athlon_decode" "vector")])
1027 (define_insn "*cmpfp_iu_sse"
1028 [(set (reg:CCFPU 17)
1029 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1030 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1032 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1033 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1034 "* return output_fp_compare (insn, operands, 1, 1);"
1035 [(set_attr "type" "fcmp,ssecomi")
1037 (if_then_else (match_operand:SF 1 "" "")
1039 (const_string "DF")))
1040 (set_attr "athlon_decode" "vector")])
1042 (define_insn "*cmpfp_iu_sse_only"
1043 [(set (reg:CCFPU 17)
1044 (compare:CCFPU (match_operand 0 "register_operand" "x")
1045 (match_operand 1 "nonimmediate_operand" "xm")))]
1046 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1047 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1048 "* return output_fp_compare (insn, operands, 1, 1);"
1049 [(set_attr "type" "ssecomi")
1051 (if_then_else (match_operand:SF 1 "" "")
1053 (const_string "DF")))
1054 (set_attr "athlon_decode" "vector")])
1056 ;; Move instructions.
1058 ;; General case of fullword move.
1060 (define_expand "movsi"
1061 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1062 (match_operand:SI 1 "general_operand" ""))]
1064 "ix86_expand_move (SImode, operands); DONE;")
1066 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1069 ;; %%% We don't use a post-inc memory reference because x86 is not a
1070 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1071 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1072 ;; targets without our curiosities, and it is just as easy to represent
1073 ;; this differently.
1075 (define_insn "*pushsi2"
1076 [(set (match_operand:SI 0 "push_operand" "=<")
1077 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1080 [(set_attr "type" "push")
1081 (set_attr "mode" "SI")])
1083 ;; For 64BIT abi we always round up to 8 bytes.
1084 (define_insn "*pushsi2_rex64"
1085 [(set (match_operand:SI 0 "push_operand" "=X")
1086 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1089 [(set_attr "type" "push")
1090 (set_attr "mode" "SI")])
1092 (define_insn "*pushsi2_prologue"
1093 [(set (match_operand:SI 0 "push_operand" "=<")
1094 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1095 (clobber (mem:BLK (scratch)))]
1098 [(set_attr "type" "push")
1099 (set_attr "mode" "SI")])
1101 (define_insn "*popsi1_epilogue"
1102 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1103 (mem:SI (reg:SI 7)))
1105 (plus:SI (reg:SI 7) (const_int 4)))
1106 (clobber (mem:BLK (scratch)))]
1109 [(set_attr "type" "pop")
1110 (set_attr "mode" "SI")])
1112 (define_insn "popsi1"
1113 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1114 (mem:SI (reg:SI 7)))
1116 (plus:SI (reg:SI 7) (const_int 4)))]
1119 [(set_attr "type" "pop")
1120 (set_attr "mode" "SI")])
1122 (define_insn "*movsi_xor"
1123 [(set (match_operand:SI 0 "register_operand" "=r")
1124 (match_operand:SI 1 "const0_operand" "i"))
1125 (clobber (reg:CC 17))]
1126 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1127 "xor{l}\t{%0, %0|%0, %0}"
1128 [(set_attr "type" "alu1")
1129 (set_attr "mode" "SI")
1130 (set_attr "length_immediate" "0")])
1132 (define_insn "*movsi_or"
1133 [(set (match_operand:SI 0 "register_operand" "=r")
1134 (match_operand:SI 1 "immediate_operand" "i"))
1135 (clobber (reg:CC 17))]
1137 && operands[1] == constm1_rtx
1138 && (TARGET_PENTIUM || optimize_size)"
1140 operands[1] = constm1_rtx;
1141 return "or{l}\t{%1, %0|%0, %1}";
1143 [(set_attr "type" "alu1")
1144 (set_attr "mode" "SI")
1145 (set_attr "length_immediate" "1")])
1147 (define_insn "*movsi_1"
1148 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1149 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1150 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1151 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1153 switch (get_attr_type (insn))
1156 if (get_attr_mode (insn) == MODE_TI)
1157 return "movdqa\t{%1, %0|%0, %1}";
1158 return "movd\t{%1, %0|%0, %1}";
1161 if (get_attr_mode (insn) == MODE_DI)
1162 return "movq\t{%1, %0|%0, %1}";
1163 return "movd\t{%1, %0|%0, %1}";
1166 return "lea{l}\t{%1, %0|%0, %1}";
1169 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1171 return "mov{l}\t{%1, %0|%0, %1}";
1175 (cond [(eq_attr "alternative" "2,3,4")
1176 (const_string "mmxmov")
1177 (eq_attr "alternative" "5,6,7")
1178 (const_string "ssemov")
1179 (and (ne (symbol_ref "flag_pic") (const_int 0))
1180 (match_operand:SI 1 "symbolic_operand" ""))
1181 (const_string "lea")
1183 (const_string "imov")))
1184 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1186 (define_insn "*movsi_1_nointernunit"
1187 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1188 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1189 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1190 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1192 switch (get_attr_type (insn))
1195 if (get_attr_mode (insn) == MODE_TI)
1196 return "movdqa\t{%1, %0|%0, %1}";
1197 return "movd\t{%1, %0|%0, %1}";
1200 if (get_attr_mode (insn) == MODE_DI)
1201 return "movq\t{%1, %0|%0, %1}";
1202 return "movd\t{%1, %0|%0, %1}";
1205 return "lea{l}\t{%1, %0|%0, %1}";
1208 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1210 return "mov{l}\t{%1, %0|%0, %1}";
1214 (cond [(eq_attr "alternative" "2,3,4")
1215 (const_string "mmxmov")
1216 (eq_attr "alternative" "5,6,7")
1217 (const_string "ssemov")
1218 (and (ne (symbol_ref "flag_pic") (const_int 0))
1219 (match_operand:SI 1 "symbolic_operand" ""))
1220 (const_string "lea")
1222 (const_string "imov")))
1223 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1225 ;; Stores and loads of ax to arbitrary constant address.
1226 ;; We fake an second form of instruction to force reload to load address
1227 ;; into register when rax is not available
1228 (define_insn "*movabssi_1_rex64"
1229 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1230 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1231 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1233 movabs{l}\t{%1, %P0|%P0, %1}
1234 mov{l}\t{%1, %a0|%a0, %1}"
1235 [(set_attr "type" "imov")
1236 (set_attr "modrm" "0,*")
1237 (set_attr "length_address" "8,0")
1238 (set_attr "length_immediate" "0,*")
1239 (set_attr "memory" "store")
1240 (set_attr "mode" "SI")])
1242 (define_insn "*movabssi_2_rex64"
1243 [(set (match_operand:SI 0 "register_operand" "=a,r")
1244 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1245 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1247 movabs{l}\t{%P1, %0|%0, %P1}
1248 mov{l}\t{%a1, %0|%0, %a1}"
1249 [(set_attr "type" "imov")
1250 (set_attr "modrm" "0,*")
1251 (set_attr "length_address" "8,0")
1252 (set_attr "length_immediate" "0")
1253 (set_attr "memory" "load")
1254 (set_attr "mode" "SI")])
1256 (define_insn "*swapsi"
1257 [(set (match_operand:SI 0 "register_operand" "+r")
1258 (match_operand:SI 1 "register_operand" "+r"))
1263 [(set_attr "type" "imov")
1264 (set_attr "pent_pair" "np")
1265 (set_attr "athlon_decode" "vector")
1266 (set_attr "mode" "SI")
1267 (set_attr "modrm" "0")
1268 (set_attr "ppro_uops" "few")])
1270 (define_expand "movhi"
1271 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1272 (match_operand:HI 1 "general_operand" ""))]
1274 "ix86_expand_move (HImode, operands); DONE;")
1276 (define_insn "*pushhi2"
1277 [(set (match_operand:HI 0 "push_operand" "=<,<")
1278 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1281 push{w}\t{|WORD PTR }%1
1283 [(set_attr "type" "push")
1284 (set_attr "mode" "HI")])
1286 ;; For 64BIT abi we always round up to 8 bytes.
1287 (define_insn "*pushhi2_rex64"
1288 [(set (match_operand:HI 0 "push_operand" "=X")
1289 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1292 [(set_attr "type" "push")
1293 (set_attr "mode" "QI")])
1295 (define_insn "*movhi_1"
1296 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1297 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1298 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1300 switch (get_attr_type (insn))
1303 /* movzwl is faster than movw on p2 due to partial word stalls,
1304 though not as fast as an aligned movl. */
1305 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1307 if (get_attr_mode (insn) == MODE_SI)
1308 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1310 return "mov{w}\t{%1, %0|%0, %1}";
1314 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1315 (const_string "imov")
1316 (and (eq_attr "alternative" "0")
1317 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1319 (eq (symbol_ref "TARGET_HIMODE_MATH")
1321 (const_string "imov")
1322 (and (eq_attr "alternative" "1,2")
1323 (match_operand:HI 1 "aligned_operand" ""))
1324 (const_string "imov")
1325 (and (ne (symbol_ref "TARGET_MOVX")
1327 (eq_attr "alternative" "0,2"))
1328 (const_string "imovx")
1330 (const_string "imov")))
1332 (cond [(eq_attr "type" "imovx")
1334 (and (eq_attr "alternative" "1,2")
1335 (match_operand:HI 1 "aligned_operand" ""))
1337 (and (eq_attr "alternative" "0")
1338 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1340 (eq (symbol_ref "TARGET_HIMODE_MATH")
1344 (const_string "HI")))])
1346 ;; Stores and loads of ax to arbitrary constant address.
1347 ;; We fake an second form of instruction to force reload to load address
1348 ;; into register when rax is not available
1349 (define_insn "*movabshi_1_rex64"
1350 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1351 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1352 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1354 movabs{w}\t{%1, %P0|%P0, %1}
1355 mov{w}\t{%1, %a0|%a0, %1}"
1356 [(set_attr "type" "imov")
1357 (set_attr "modrm" "0,*")
1358 (set_attr "length_address" "8,0")
1359 (set_attr "length_immediate" "0,*")
1360 (set_attr "memory" "store")
1361 (set_attr "mode" "HI")])
1363 (define_insn "*movabshi_2_rex64"
1364 [(set (match_operand:HI 0 "register_operand" "=a,r")
1365 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1366 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1368 movabs{w}\t{%P1, %0|%0, %P1}
1369 mov{w}\t{%a1, %0|%0, %a1}"
1370 [(set_attr "type" "imov")
1371 (set_attr "modrm" "0,*")
1372 (set_attr "length_address" "8,0")
1373 (set_attr "length_immediate" "0")
1374 (set_attr "memory" "load")
1375 (set_attr "mode" "HI")])
1377 (define_insn "*swaphi_1"
1378 [(set (match_operand:HI 0 "register_operand" "+r")
1379 (match_operand:HI 1 "register_operand" "+r"))
1382 "TARGET_PARTIAL_REG_STALL"
1384 [(set_attr "type" "imov")
1385 (set_attr "pent_pair" "np")
1386 (set_attr "mode" "HI")
1387 (set_attr "modrm" "0")
1388 (set_attr "ppro_uops" "few")])
1390 (define_insn "*swaphi_2"
1391 [(set (match_operand:HI 0 "register_operand" "+r")
1392 (match_operand:HI 1 "register_operand" "+r"))
1395 "! TARGET_PARTIAL_REG_STALL"
1397 [(set_attr "type" "imov")
1398 (set_attr "pent_pair" "np")
1399 (set_attr "mode" "SI")
1400 (set_attr "modrm" "0")
1401 (set_attr "ppro_uops" "few")])
1403 (define_expand "movstricthi"
1404 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1405 (match_operand:HI 1 "general_operand" ""))]
1406 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1408 /* Don't generate memory->memory moves, go through a register */
1409 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1410 operands[1] = force_reg (HImode, operands[1]);
1413 (define_insn "*movstricthi_1"
1414 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1415 (match_operand:HI 1 "general_operand" "rn,m"))]
1416 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1417 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1418 "mov{w}\t{%1, %0|%0, %1}"
1419 [(set_attr "type" "imov")
1420 (set_attr "mode" "HI")])
1422 (define_insn "*movstricthi_xor"
1423 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1424 (match_operand:HI 1 "const0_operand" "i"))
1425 (clobber (reg:CC 17))]
1427 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1428 "xor{w}\t{%0, %0|%0, %0}"
1429 [(set_attr "type" "alu1")
1430 (set_attr "mode" "HI")
1431 (set_attr "length_immediate" "0")])
1433 (define_expand "movqi"
1434 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1435 (match_operand:QI 1 "general_operand" ""))]
1437 "ix86_expand_move (QImode, operands); DONE;")
1439 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1440 ;; "push a byte". But actually we use pushw, which has the effect
1441 ;; of rounding the amount pushed up to a halfword.
1443 (define_insn "*pushqi2"
1444 [(set (match_operand:QI 0 "push_operand" "=X,X")
1445 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1448 push{w}\t{|word ptr }%1
1450 [(set_attr "type" "push")
1451 (set_attr "mode" "HI")])
1453 ;; For 64BIT abi we always round up to 8 bytes.
1454 (define_insn "*pushqi2_rex64"
1455 [(set (match_operand:QI 0 "push_operand" "=X")
1456 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1459 [(set_attr "type" "push")
1460 (set_attr "mode" "QI")])
1462 ;; Situation is quite tricky about when to choose full sized (SImode) move
1463 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1464 ;; partial register dependency machines (such as AMD Athlon), where QImode
1465 ;; moves issue extra dependency and for partial register stalls machines
1466 ;; that don't use QImode patterns (and QImode move cause stall on the next
1469 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1470 ;; register stall machines with, where we use QImode instructions, since
1471 ;; partial register stall can be caused there. Then we use movzx.
1472 (define_insn "*movqi_1"
1473 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1474 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1475 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1477 switch (get_attr_type (insn))
1480 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1482 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1484 if (get_attr_mode (insn) == MODE_SI)
1485 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1487 return "mov{b}\t{%1, %0|%0, %1}";
1491 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1492 (const_string "imov")
1493 (and (eq_attr "alternative" "3")
1494 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1496 (eq (symbol_ref "TARGET_QIMODE_MATH")
1498 (const_string "imov")
1499 (eq_attr "alternative" "3,5")
1500 (const_string "imovx")
1501 (and (ne (symbol_ref "TARGET_MOVX")
1503 (eq_attr "alternative" "2"))
1504 (const_string "imovx")
1506 (const_string "imov")))
1508 (cond [(eq_attr "alternative" "3,4,5")
1510 (eq_attr "alternative" "6")
1512 (eq_attr "type" "imovx")
1514 (and (eq_attr "type" "imov")
1515 (and (eq_attr "alternative" "0,1,2")
1516 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1519 ;; Avoid partial register stalls when not using QImode arithmetic
1520 (and (eq_attr "type" "imov")
1521 (and (eq_attr "alternative" "0,1,2")
1522 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1524 (eq (symbol_ref "TARGET_QIMODE_MATH")
1528 (const_string "QI")))])
1530 (define_expand "reload_outqi"
1531 [(parallel [(match_operand:QI 0 "" "=m")
1532 (match_operand:QI 1 "register_operand" "r")
1533 (match_operand:QI 2 "register_operand" "=&q")])]
1537 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1539 if (reg_overlap_mentioned_p (op2, op0))
1541 if (! q_regs_operand (op1, QImode))
1543 emit_insn (gen_movqi (op2, op1));
1546 emit_insn (gen_movqi (op0, op1));
1550 (define_insn "*swapqi"
1551 [(set (match_operand:QI 0 "register_operand" "+r")
1552 (match_operand:QI 1 "register_operand" "+r"))
1557 [(set_attr "type" "imov")
1558 (set_attr "pent_pair" "np")
1559 (set_attr "mode" "QI")
1560 (set_attr "modrm" "0")
1561 (set_attr "ppro_uops" "few")])
1563 (define_expand "movstrictqi"
1564 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1565 (match_operand:QI 1 "general_operand" ""))]
1566 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1568 /* Don't generate memory->memory moves, go through a register. */
1569 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1570 operands[1] = force_reg (QImode, operands[1]);
1573 (define_insn "*movstrictqi_1"
1574 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1575 (match_operand:QI 1 "general_operand" "*qn,m"))]
1576 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1577 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1578 "mov{b}\t{%1, %0|%0, %1}"
1579 [(set_attr "type" "imov")
1580 (set_attr "mode" "QI")])
1582 (define_insn "*movstrictqi_xor"
1583 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1584 (match_operand:QI 1 "const0_operand" "i"))
1585 (clobber (reg:CC 17))]
1586 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1587 "xor{b}\t{%0, %0|%0, %0}"
1588 [(set_attr "type" "alu1")
1589 (set_attr "mode" "QI")
1590 (set_attr "length_immediate" "0")])
1592 (define_insn "*movsi_extv_1"
1593 [(set (match_operand:SI 0 "register_operand" "=R")
1594 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1598 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1599 [(set_attr "type" "imovx")
1600 (set_attr "mode" "SI")])
1602 (define_insn "*movhi_extv_1"
1603 [(set (match_operand:HI 0 "register_operand" "=R")
1604 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1608 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1609 [(set_attr "type" "imovx")
1610 (set_attr "mode" "SI")])
1612 (define_insn "*movqi_extv_1"
1613 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1614 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1619 switch (get_attr_type (insn))
1622 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1624 return "mov{b}\t{%h1, %0|%0, %h1}";
1628 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1629 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1630 (ne (symbol_ref "TARGET_MOVX")
1632 (const_string "imovx")
1633 (const_string "imov")))
1635 (if_then_else (eq_attr "type" "imovx")
1637 (const_string "QI")))])
1639 (define_insn "*movqi_extv_1_rex64"
1640 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1641 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1646 switch (get_attr_type (insn))
1649 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1651 return "mov{b}\t{%h1, %0|%0, %h1}";
1655 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1656 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1657 (ne (symbol_ref "TARGET_MOVX")
1659 (const_string "imovx")
1660 (const_string "imov")))
1662 (if_then_else (eq_attr "type" "imovx")
1664 (const_string "QI")))])
1666 ;; Stores and loads of ax to arbitrary constant address.
1667 ;; We fake an second form of instruction to force reload to load address
1668 ;; into register when rax is not available
1669 (define_insn "*movabsqi_1_rex64"
1670 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1671 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1672 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1674 movabs{b}\t{%1, %P0|%P0, %1}
1675 mov{b}\t{%1, %a0|%a0, %1}"
1676 [(set_attr "type" "imov")
1677 (set_attr "modrm" "0,*")
1678 (set_attr "length_address" "8,0")
1679 (set_attr "length_immediate" "0,*")
1680 (set_attr "memory" "store")
1681 (set_attr "mode" "QI")])
1683 (define_insn "*movabsqi_2_rex64"
1684 [(set (match_operand:QI 0 "register_operand" "=a,r")
1685 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1686 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1688 movabs{b}\t{%P1, %0|%0, %P1}
1689 mov{b}\t{%a1, %0|%0, %a1}"
1690 [(set_attr "type" "imov")
1691 (set_attr "modrm" "0,*")
1692 (set_attr "length_address" "8,0")
1693 (set_attr "length_immediate" "0")
1694 (set_attr "memory" "load")
1695 (set_attr "mode" "QI")])
1697 (define_insn "*movsi_extzv_1"
1698 [(set (match_operand:SI 0 "register_operand" "=R")
1699 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1703 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1704 [(set_attr "type" "imovx")
1705 (set_attr "mode" "SI")])
1707 (define_insn "*movqi_extzv_2"
1708 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1709 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1714 switch (get_attr_type (insn))
1717 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1719 return "mov{b}\t{%h1, %0|%0, %h1}";
1723 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1724 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1725 (ne (symbol_ref "TARGET_MOVX")
1727 (const_string "imovx")
1728 (const_string "imov")))
1730 (if_then_else (eq_attr "type" "imovx")
1732 (const_string "QI")))])
1734 (define_insn "*movqi_extzv_2_rex64"
1735 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1736 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1741 switch (get_attr_type (insn))
1744 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1746 return "mov{b}\t{%h1, %0|%0, %h1}";
1750 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1751 (ne (symbol_ref "TARGET_MOVX")
1753 (const_string "imovx")
1754 (const_string "imov")))
1756 (if_then_else (eq_attr "type" "imovx")
1758 (const_string "QI")))])
1760 (define_insn "movsi_insv_1"
1761 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1764 (match_operand:SI 1 "general_operand" "Qmn"))]
1766 "mov{b}\t{%b1, %h0|%h0, %b1}"
1767 [(set_attr "type" "imov")
1768 (set_attr "mode" "QI")])
1770 (define_insn "*movsi_insv_1_rex64"
1771 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1774 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1776 "mov{b}\t{%b1, %h0|%h0, %b1}"
1777 [(set_attr "type" "imov")
1778 (set_attr "mode" "QI")])
1780 (define_insn "*movqi_insv_2"
1781 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1784 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1787 "mov{b}\t{%h1, %h0|%h0, %h1}"
1788 [(set_attr "type" "imov")
1789 (set_attr "mode" "QI")])
1791 (define_expand "movdi"
1792 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1793 (match_operand:DI 1 "general_operand" ""))]
1795 "ix86_expand_move (DImode, operands); DONE;")
1797 (define_insn "*pushdi"
1798 [(set (match_operand:DI 0 "push_operand" "=<")
1799 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1803 (define_insn "pushdi2_rex64"
1804 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1805 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1810 [(set_attr "type" "push,multi")
1811 (set_attr "mode" "DI")])
1813 ;; Convert impossible pushes of immediate to existing instructions.
1814 ;; First try to get scratch register and go through it. In case this
1815 ;; fails, push sign extended lower part first and then overwrite
1816 ;; upper part by 32bit move.
1818 [(match_scratch:DI 2 "r")
1819 (set (match_operand:DI 0 "push_operand" "")
1820 (match_operand:DI 1 "immediate_operand" ""))]
1821 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1822 && !x86_64_immediate_operand (operands[1], DImode)"
1823 [(set (match_dup 2) (match_dup 1))
1824 (set (match_dup 0) (match_dup 2))]
1827 ;; We need to define this as both peepholer and splitter for case
1828 ;; peephole2 pass is not run.
1830 [(set (match_operand:DI 0 "push_operand" "")
1831 (match_operand:DI 1 "immediate_operand" ""))]
1832 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1833 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1834 [(set (match_dup 0) (match_dup 1))
1835 (set (match_dup 2) (match_dup 3))]
1836 "split_di (operands + 1, 1, operands + 2, operands + 3);
1837 operands[1] = gen_lowpart (DImode, operands[2]);
1838 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1843 [(set (match_operand:DI 0 "push_operand" "")
1844 (match_operand:DI 1 "immediate_operand" ""))]
1845 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1846 && !symbolic_operand (operands[1], DImode)
1847 && !x86_64_immediate_operand (operands[1], DImode)"
1848 [(set (match_dup 0) (match_dup 1))
1849 (set (match_dup 2) (match_dup 3))]
1850 "split_di (operands + 1, 1, operands + 2, operands + 3);
1851 operands[1] = gen_lowpart (DImode, operands[2]);
1852 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1856 (define_insn "*pushdi2_prologue_rex64"
1857 [(set (match_operand:DI 0 "push_operand" "=<")
1858 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1859 (clobber (mem:BLK (scratch)))]
1862 [(set_attr "type" "push")
1863 (set_attr "mode" "DI")])
1865 (define_insn "*popdi1_epilogue_rex64"
1866 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1867 (mem:DI (reg:DI 7)))
1869 (plus:DI (reg:DI 7) (const_int 8)))
1870 (clobber (mem:BLK (scratch)))]
1873 [(set_attr "type" "pop")
1874 (set_attr "mode" "DI")])
1876 (define_insn "popdi1"
1877 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1878 (mem:DI (reg:DI 7)))
1880 (plus:DI (reg:DI 7) (const_int 8)))]
1883 [(set_attr "type" "pop")
1884 (set_attr "mode" "DI")])
1886 (define_insn "*movdi_xor_rex64"
1887 [(set (match_operand:DI 0 "register_operand" "=r")
1888 (match_operand:DI 1 "const0_operand" "i"))
1889 (clobber (reg:CC 17))]
1890 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1891 && reload_completed"
1892 "xor{l}\t{%k0, %k0|%k0, %k0}"
1893 [(set_attr "type" "alu1")
1894 (set_attr "mode" "SI")
1895 (set_attr "length_immediate" "0")])
1897 (define_insn "*movdi_or_rex64"
1898 [(set (match_operand:DI 0 "register_operand" "=r")
1899 (match_operand:DI 1 "const_int_operand" "i"))
1900 (clobber (reg:CC 17))]
1901 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1903 && operands[1] == constm1_rtx"
1905 operands[1] = constm1_rtx;
1906 return "or{q}\t{%1, %0|%0, %1}";
1908 [(set_attr "type" "alu1")
1909 (set_attr "mode" "DI")
1910 (set_attr "length_immediate" "1")])
1912 (define_insn "*movdi_2"
1913 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1914 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1916 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1920 movq\t{%1, %0|%0, %1}
1921 movq\t{%1, %0|%0, %1}
1922 movq\t{%1, %0|%0, %1}
1923 movdqa\t{%1, %0|%0, %1}
1924 movq\t{%1, %0|%0, %1}"
1925 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1926 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1929 [(set (match_operand:DI 0 "push_operand" "")
1930 (match_operand:DI 1 "general_operand" ""))]
1931 "!TARGET_64BIT && reload_completed
1932 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1934 "ix86_split_long_move (operands); DONE;")
1936 ;; %%% This multiword shite has got to go.
1938 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1939 (match_operand:DI 1 "general_operand" ""))]
1940 "!TARGET_64BIT && reload_completed
1941 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1942 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1944 "ix86_split_long_move (operands); DONE;")
1946 (define_insn "*movdi_1_rex64"
1947 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
1948 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
1950 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1951 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1953 switch (get_attr_type (insn))
1956 if (get_attr_mode (insn) == MODE_TI)
1957 return "movdqa\t{%1, %0|%0, %1}";
1960 /* Moves from and into integer register is done using movd opcode with
1962 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1963 return "movd\t{%1, %0|%0, %1}";
1964 return "movq\t{%1, %0|%0, %1}";
1968 return "lea{q}\t{%a1, %0|%0, %a1}";
1970 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1972 if (get_attr_mode (insn) == MODE_SI)
1973 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1974 else if (which_alternative == 2)
1975 return "movabs{q}\t{%1, %0|%0, %1}";
1977 return "mov{q}\t{%1, %0|%0, %1}";
1981 (cond [(eq_attr "alternative" "5,6,7")
1982 (const_string "mmxmov")
1983 (eq_attr "alternative" "8,9,10")
1984 (const_string "ssemov")
1985 (eq_attr "alternative" "4")
1986 (const_string "multi")
1987 (and (ne (symbol_ref "flag_pic") (const_int 0))
1988 (match_operand:DI 1 "symbolic_operand" ""))
1989 (const_string "lea")
1991 (const_string "imov")))
1992 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
1993 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
1994 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
1996 (define_insn "*movdi_1_rex64_nointerunit"
1997 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
1998 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2000 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2001 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2003 switch (get_attr_type (insn))
2006 if (get_attr_mode (insn) == MODE_TI)
2007 return "movdqa\t{%1, %0|%0, %1}";
2010 return "movq\t{%1, %0|%0, %1}";
2014 return "lea{q}\t{%a1, %0|%0, %a1}";
2016 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2018 if (get_attr_mode (insn) == MODE_SI)
2019 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2020 else if (which_alternative == 2)
2021 return "movabs{q}\t{%1, %0|%0, %1}";
2023 return "mov{q}\t{%1, %0|%0, %1}";
2027 (cond [(eq_attr "alternative" "5,6,7")
2028 (const_string "mmxmov")
2029 (eq_attr "alternative" "8,9,10")
2030 (const_string "ssemov")
2031 (eq_attr "alternative" "4")
2032 (const_string "multi")
2033 (and (ne (symbol_ref "flag_pic") (const_int 0))
2034 (match_operand:DI 1 "symbolic_operand" ""))
2035 (const_string "lea")
2037 (const_string "imov")))
2038 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2039 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2040 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2042 ;; Stores and loads of ax to arbitrary constant address.
2043 ;; We fake an second form of instruction to force reload to load address
2044 ;; into register when rax is not available
2045 (define_insn "*movabsdi_1_rex64"
2046 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2047 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2048 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2050 movabs{q}\t{%1, %P0|%P0, %1}
2051 mov{q}\t{%1, %a0|%a0, %1}"
2052 [(set_attr "type" "imov")
2053 (set_attr "modrm" "0,*")
2054 (set_attr "length_address" "8,0")
2055 (set_attr "length_immediate" "0,*")
2056 (set_attr "memory" "store")
2057 (set_attr "mode" "DI")])
2059 (define_insn "*movabsdi_2_rex64"
2060 [(set (match_operand:DI 0 "register_operand" "=a,r")
2061 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2062 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2064 movabs{q}\t{%P1, %0|%0, %P1}
2065 mov{q}\t{%a1, %0|%0, %a1}"
2066 [(set_attr "type" "imov")
2067 (set_attr "modrm" "0,*")
2068 (set_attr "length_address" "8,0")
2069 (set_attr "length_immediate" "0")
2070 (set_attr "memory" "load")
2071 (set_attr "mode" "DI")])
2073 ;; Convert impossible stores of immediate to existing instructions.
2074 ;; First try to get scratch register and go through it. In case this
2075 ;; fails, move by 32bit parts.
2077 [(match_scratch:DI 2 "r")
2078 (set (match_operand:DI 0 "memory_operand" "")
2079 (match_operand:DI 1 "immediate_operand" ""))]
2080 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2081 && !x86_64_immediate_operand (operands[1], DImode)"
2082 [(set (match_dup 2) (match_dup 1))
2083 (set (match_dup 0) (match_dup 2))]
2086 ;; We need to define this as both peepholer and splitter for case
2087 ;; peephole2 pass is not run.
2089 [(set (match_operand:DI 0 "memory_operand" "")
2090 (match_operand:DI 1 "immediate_operand" ""))]
2091 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2092 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2093 [(set (match_dup 2) (match_dup 3))
2094 (set (match_dup 4) (match_dup 5))]
2095 "split_di (operands, 2, operands + 2, operands + 4);")
2098 [(set (match_operand:DI 0 "memory_operand" "")
2099 (match_operand:DI 1 "immediate_operand" ""))]
2100 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2101 && !symbolic_operand (operands[1], DImode)
2102 && !x86_64_immediate_operand (operands[1], DImode)"
2103 [(set (match_dup 2) (match_dup 3))
2104 (set (match_dup 4) (match_dup 5))]
2105 "split_di (operands, 2, operands + 2, operands + 4);")
2107 (define_insn "*swapdi_rex64"
2108 [(set (match_operand:DI 0 "register_operand" "+r")
2109 (match_operand:DI 1 "register_operand" "+r"))
2114 [(set_attr "type" "imov")
2115 (set_attr "pent_pair" "np")
2116 (set_attr "athlon_decode" "vector")
2117 (set_attr "mode" "DI")
2118 (set_attr "modrm" "0")
2119 (set_attr "ppro_uops" "few")])
2122 (define_expand "movsf"
2123 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2124 (match_operand:SF 1 "general_operand" ""))]
2126 "ix86_expand_move (SFmode, operands); DONE;")
2128 (define_insn "*pushsf"
2129 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2130 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2133 switch (which_alternative)
2136 return "push{l}\t%1";
2139 /* This insn should be already split before reg-stack. */
2143 [(set_attr "type" "multi,push,multi")
2144 (set_attr "mode" "SF,SI,SF")])
2146 (define_insn "*pushsf_rex64"
2147 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2148 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2151 switch (which_alternative)
2154 return "push{q}\t%q1";
2157 /* This insn should be already split before reg-stack. */
2161 [(set_attr "type" "multi,push,multi")
2162 (set_attr "mode" "SF,DI,SF")])
2165 [(set (match_operand:SF 0 "push_operand" "")
2166 (match_operand:SF 1 "memory_operand" ""))]
2168 && GET_CODE (operands[1]) == MEM
2169 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2170 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2173 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2176 ;; %%% Kill this when call knows how to work this out.
2178 [(set (match_operand:SF 0 "push_operand" "")
2179 (match_operand:SF 1 "any_fp_register_operand" ""))]
2181 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2182 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2185 [(set (match_operand:SF 0 "push_operand" "")
2186 (match_operand:SF 1 "any_fp_register_operand" ""))]
2188 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2189 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2191 (define_insn "*movsf_1"
2192 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2193 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2194 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2195 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2196 && (reload_in_progress || reload_completed
2197 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2198 || GET_CODE (operands[1]) != CONST_DOUBLE
2199 || memory_operand (operands[0], SFmode))"
2201 switch (which_alternative)
2204 if (REG_P (operands[1])
2205 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2207 else if (STACK_TOP_P (operands[0]))
2208 return "fld%z1\t%y1";
2213 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2214 return "fstp%z0\t%y0";
2216 return "fst%z0\t%y0";
2219 return standard_80387_constant_opcode (operands[1]);
2223 return "mov{l}\t{%1, %0|%0, %1}";
2225 if (get_attr_mode (insn) == MODE_TI)
2226 return "pxor\t%0, %0";
2228 return "xorps\t%0, %0";
2230 if (get_attr_mode (insn) == MODE_V4SF)
2231 return "movaps\t{%1, %0|%0, %1}";
2233 return "movss\t{%1, %0|%0, %1}";
2236 return "movss\t{%1, %0|%0, %1}";
2240 return "movd\t{%1, %0|%0, %1}";
2243 return "movq\t{%1, %0|%0, %1}";
2249 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2251 (cond [(eq_attr "alternative" "3,4,9,10")
2253 (eq_attr "alternative" "5")
2255 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2257 (ne (symbol_ref "TARGET_SSE2")
2259 (eq (symbol_ref "optimize_size")
2262 (const_string "V4SF"))
2263 /* For architectures resolving dependencies on
2264 whole SSE registers use APS move to break dependency
2265 chains, otherwise use short move to avoid extra work.
2267 Do the same for architectures resolving dependencies on
2268 the parts. While in DF mode it is better to always handle
2269 just register parts, the SF mode is different due to lack
2270 of instructions to load just part of the register. It is
2271 better to maintain the whole registers in single format
2272 to avoid problems on using packed logical operations. */
2273 (eq_attr "alternative" "6")
2275 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2277 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2279 (const_string "V4SF")
2280 (const_string "SF"))
2281 (eq_attr "alternative" "11")
2282 (const_string "DI")]
2283 (const_string "SF")))])
2285 (define_insn "*movsf_1_nointerunit"
2286 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2287 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2288 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2289 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2290 && (reload_in_progress || reload_completed
2291 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2292 || GET_CODE (operands[1]) != CONST_DOUBLE
2293 || memory_operand (operands[0], SFmode))"
2295 switch (which_alternative)
2298 if (REG_P (operands[1])
2299 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2301 if (REGNO (operands[0]) == FIRST_STACK_REG
2302 && TARGET_USE_FFREEP)
2303 return "ffreep\t%y0";
2306 else if (STACK_TOP_P (operands[0]))
2307 return "fld%z1\t%y1";
2312 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2313 return "fstp%z0\t%y0";
2315 return "fst%z0\t%y0";
2318 return standard_80387_constant_opcode (operands[1]);
2322 return "mov{l}\t{%1, %0|%0, %1}";
2324 if (get_attr_mode (insn) == MODE_TI)
2325 return "pxor\t%0, %0";
2327 return "xorps\t%0, %0";
2329 if (get_attr_mode (insn) == MODE_V4SF)
2330 return "movaps\t{%1, %0|%0, %1}";
2332 return "movss\t{%1, %0|%0, %1}";
2335 return "movss\t{%1, %0|%0, %1}";
2339 return "movd\t{%1, %0|%0, %1}";
2342 return "movq\t{%1, %0|%0, %1}";
2348 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2350 (cond [(eq_attr "alternative" "3,4,9,10")
2352 (eq_attr "alternative" "5")
2354 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2356 (ne (symbol_ref "TARGET_SSE2")
2358 (eq (symbol_ref "optimize_size")
2361 (const_string "V4SF"))
2362 /* For architectures resolving dependencies on
2363 whole SSE registers use APS move to break dependency
2364 chains, otherwise use short move to avoid extra work.
2366 Do the same for architectures resolving dependencies on
2367 the parts. While in DF mode it is better to always handle
2368 just register parts, the SF mode is different due to lack
2369 of instructions to load just part of the register. It is
2370 better to maintain the whole registers in single format
2371 to avoid problems on using packed logical operations. */
2372 (eq_attr "alternative" "6")
2374 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2376 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2378 (const_string "V4SF")
2379 (const_string "SF"))
2380 (eq_attr "alternative" "11")
2381 (const_string "DI")]
2382 (const_string "SF")))])
2384 (define_insn "*swapsf"
2385 [(set (match_operand:SF 0 "register_operand" "+f")
2386 (match_operand:SF 1 "register_operand" "+f"))
2389 "reload_completed || !TARGET_SSE"
2391 if (STACK_TOP_P (operands[0]))
2396 [(set_attr "type" "fxch")
2397 (set_attr "mode" "SF")])
2399 (define_expand "movdf"
2400 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2401 (match_operand:DF 1 "general_operand" ""))]
2403 "ix86_expand_move (DFmode, operands); DONE;")
2405 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2406 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2407 ;; On the average, pushdf using integers can be still shorter. Allow this
2408 ;; pattern for optimize_size too.
2410 (define_insn "*pushdf_nointeger"
2411 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2412 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2413 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2415 /* This insn should be already split before reg-stack. */
2418 [(set_attr "type" "multi")
2419 (set_attr "mode" "DF,SI,SI,DF")])
2421 (define_insn "*pushdf_integer"
2422 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2423 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2424 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2426 /* This insn should be already split before reg-stack. */
2429 [(set_attr "type" "multi")
2430 (set_attr "mode" "DF,SI,DF")])
2432 ;; %%% Kill this when call knows how to work this out.
2434 [(set (match_operand:DF 0 "push_operand" "")
2435 (match_operand:DF 1 "any_fp_register_operand" ""))]
2436 "!TARGET_64BIT && reload_completed"
2437 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2438 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2442 [(set (match_operand:DF 0 "push_operand" "")
2443 (match_operand:DF 1 "any_fp_register_operand" ""))]
2444 "TARGET_64BIT && reload_completed"
2445 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2446 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2450 [(set (match_operand:DF 0 "push_operand" "")
2451 (match_operand:DF 1 "general_operand" ""))]
2454 "ix86_split_long_move (operands); DONE;")
2456 ;; Moving is usually shorter when only FP registers are used. This separate
2457 ;; movdf pattern avoids the use of integer registers for FP operations
2458 ;; when optimizing for size.
2460 (define_insn "*movdf_nointeger"
2461 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2462 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2463 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2464 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2465 && (reload_in_progress || reload_completed
2466 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2467 || GET_CODE (operands[1]) != CONST_DOUBLE
2468 || memory_operand (operands[0], DFmode))"
2470 switch (which_alternative)
2473 if (REG_P (operands[1])
2474 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2476 if (REGNO (operands[0]) == FIRST_STACK_REG
2477 && TARGET_USE_FFREEP)
2478 return "ffreep\t%y0";
2481 else if (STACK_TOP_P (operands[0]))
2482 return "fld%z1\t%y1";
2487 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2488 return "fstp%z0\t%y0";
2490 return "fst%z0\t%y0";
2493 return standard_80387_constant_opcode (operands[1]);
2499 switch (get_attr_mode (insn))
2502 return "xorps\t%0, %0";
2504 return "xorpd\t%0, %0";
2506 return "pxor\t%0, %0";
2511 switch (get_attr_mode (insn))
2514 return "movaps\t{%1, %0|%0, %1}";
2516 return "movapd\t{%1, %0|%0, %1}";
2518 return "movsd\t{%1, %0|%0, %1}";
2523 if (get_attr_mode (insn) == MODE_V2DF)
2524 return "movlpd\t{%1, %0|%0, %1}";
2526 return "movsd\t{%1, %0|%0, %1}";
2528 return "movsd\t{%1, %0|%0, %1}";
2534 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2536 (cond [(eq_attr "alternative" "3,4")
2538 /* xorps is one byte shorter. */
2539 (eq_attr "alternative" "5")
2540 (cond [(ne (symbol_ref "optimize_size")
2542 (const_string "V4SF")
2543 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2545 (const_string "TI")]
2546 (const_string "V2DF"))
2547 /* For architectures resolving dependencies on
2548 whole SSE registers use APD move to break dependency
2549 chains, otherwise use short move to avoid extra work.
2551 movaps encodes one byte shorter. */
2552 (eq_attr "alternative" "6")
2554 [(ne (symbol_ref "optimize_size")
2556 (const_string "V4SF")
2557 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2559 (const_string "V2DF")]
2560 (const_string "DF"))
2561 /* For architectures resolving dependencies on register
2562 parts we may avoid extra work to zero out upper part
2564 (eq_attr "alternative" "7")
2566 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2568 (const_string "V2DF")
2569 (const_string "DF"))]
2570 (const_string "DF")))])
2572 (define_insn "*movdf_integer"
2573 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2574 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2575 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2576 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2577 && (reload_in_progress || reload_completed
2578 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2579 || GET_CODE (operands[1]) != CONST_DOUBLE
2580 || memory_operand (operands[0], DFmode))"
2582 switch (which_alternative)
2585 if (REG_P (operands[1])
2586 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2588 if (REGNO (operands[0]) == FIRST_STACK_REG
2589 && TARGET_USE_FFREEP)
2590 return "ffreep\t%y0";
2593 else if (STACK_TOP_P (operands[0]))
2594 return "fld%z1\t%y1";
2599 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2600 return "fstp%z0\t%y0";
2602 return "fst%z0\t%y0";
2605 return standard_80387_constant_opcode (operands[1]);
2612 switch (get_attr_mode (insn))
2615 return "xorps\t%0, %0";
2617 return "xorpd\t%0, %0";
2619 return "pxor\t%0, %0";
2624 switch (get_attr_mode (insn))
2627 return "movaps\t{%1, %0|%0, %1}";
2629 return "movapd\t{%1, %0|%0, %1}";
2631 return "movsd\t{%1, %0|%0, %1}";
2636 if (get_attr_mode (insn) == MODE_V2DF)
2637 return "movlpd\t{%1, %0|%0, %1}";
2639 return "movsd\t{%1, %0|%0, %1}";
2641 return "movsd\t{%1, %0|%0, %1}";
2647 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2649 (cond [(eq_attr "alternative" "3,4")
2651 /* xorps is one byte shorter. */
2652 (eq_attr "alternative" "5")
2653 (cond [(ne (symbol_ref "optimize_size")
2655 (const_string "V4SF")
2656 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2658 (const_string "TI")]
2659 (const_string "V2DF"))
2660 /* For architectures resolving dependencies on
2661 whole SSE registers use APD move to break dependency
2662 chains, otherwise use short move to avoid extra work.
2664 movaps encodes one byte shorter. */
2665 (eq_attr "alternative" "6")
2667 [(ne (symbol_ref "optimize_size")
2669 (const_string "V4SF")
2670 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2672 (const_string "V2DF")]
2673 (const_string "DF"))
2674 /* For architectures resolving dependencies on register
2675 parts we may avoid extra work to zero out upper part
2677 (eq_attr "alternative" "7")
2679 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2681 (const_string "V2DF")
2682 (const_string "DF"))]
2683 (const_string "DF")))])
2686 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2687 (match_operand:DF 1 "general_operand" ""))]
2689 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2690 && ! (ANY_FP_REG_P (operands[0]) ||
2691 (GET_CODE (operands[0]) == SUBREG
2692 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2693 && ! (ANY_FP_REG_P (operands[1]) ||
2694 (GET_CODE (operands[1]) == SUBREG
2695 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2697 "ix86_split_long_move (operands); DONE;")
2699 (define_insn "*swapdf"
2700 [(set (match_operand:DF 0 "register_operand" "+f")
2701 (match_operand:DF 1 "register_operand" "+f"))
2704 "reload_completed || !TARGET_SSE2"
2706 if (STACK_TOP_P (operands[0]))
2711 [(set_attr "type" "fxch")
2712 (set_attr "mode" "DF")])
2714 (define_expand "movxf"
2715 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2716 (match_operand:XF 1 "general_operand" ""))]
2718 "ix86_expand_move (XFmode, operands); DONE;")
2720 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2721 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2722 ;; Pushing using integer instructions is longer except for constants
2723 ;; and direct memory references.
2724 ;; (assuming that any given constant is pushed only once, but this ought to be
2725 ;; handled elsewhere).
2727 (define_insn "*pushxf_nointeger"
2728 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2729 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2732 /* This insn should be already split before reg-stack. */
2735 [(set_attr "type" "multi")
2736 (set_attr "mode" "XF,SI,SI")])
2738 (define_insn "*pushxf_integer"
2739 [(set (match_operand:XF 0 "push_operand" "=<,<")
2740 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2743 /* This insn should be already split before reg-stack. */
2746 [(set_attr "type" "multi")
2747 (set_attr "mode" "XF,SI")])
2750 [(set (match_operand 0 "push_operand" "")
2751 (match_operand 1 "general_operand" ""))]
2753 && (GET_MODE (operands[0]) == XFmode
2754 || GET_MODE (operands[0]) == DFmode)
2755 && !ANY_FP_REG_P (operands[1])"
2757 "ix86_split_long_move (operands); DONE;")
2760 [(set (match_operand:XF 0 "push_operand" "")
2761 (match_operand:XF 1 "any_fp_register_operand" ""))]
2763 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
2764 (set (mem:XF (reg:SI 7)) (match_dup 1))]
2765 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2768 [(set (match_operand:XF 0 "push_operand" "")
2769 (match_operand:XF 1 "any_fp_register_operand" ""))]
2771 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
2772 (set (mem:XF (reg:DI 7)) (match_dup 1))]
2773 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2775 ;; Do not use integer registers when optimizing for size
2776 (define_insn "*movxf_nointeger"
2777 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2778 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2780 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2781 && (reload_in_progress || reload_completed
2782 || GET_CODE (operands[1]) != CONST_DOUBLE
2783 || memory_operand (operands[0], XFmode))"
2785 switch (which_alternative)
2788 if (REG_P (operands[1])
2789 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2791 if (REGNO (operands[0]) == FIRST_STACK_REG
2792 && TARGET_USE_FFREEP)
2793 return "ffreep\t%y0";
2796 else if (STACK_TOP_P (operands[0]))
2797 return "fld%z1\t%y1";
2802 /* There is no non-popping store to memory for XFmode. So if
2803 we need one, follow the store with a load. */
2804 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2805 return "fstp%z0\t%y0\;fld%z0\t%y0";
2807 return "fstp%z0\t%y0";
2810 return standard_80387_constant_opcode (operands[1]);
2817 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2818 (set_attr "mode" "XF,XF,XF,SI,SI")])
2820 (define_insn "*movxf_integer"
2821 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2822 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2824 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2825 && (reload_in_progress || reload_completed
2826 || GET_CODE (operands[1]) != CONST_DOUBLE
2827 || memory_operand (operands[0], XFmode))"
2829 switch (which_alternative)
2832 if (REG_P (operands[1])
2833 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2835 if (REGNO (operands[0]) == FIRST_STACK_REG
2836 && TARGET_USE_FFREEP)
2837 return "ffreep\t%y0";
2840 else if (STACK_TOP_P (operands[0]))
2841 return "fld%z1\t%y1";
2846 /* There is no non-popping store to memory for XFmode. So if
2847 we need one, follow the store with a load. */
2848 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2849 return "fstp%z0\t%y0\;fld%z0\t%y0";
2851 return "fstp%z0\t%y0";
2854 return standard_80387_constant_opcode (operands[1]);
2861 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2862 (set_attr "mode" "XF,XF,XF,SI,SI")])
2865 [(set (match_operand 0 "nonimmediate_operand" "")
2866 (match_operand 1 "general_operand" ""))]
2868 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2869 && GET_MODE (operands[0]) == XFmode
2870 && ! (ANY_FP_REG_P (operands[0]) ||
2871 (GET_CODE (operands[0]) == SUBREG
2872 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2873 && ! (ANY_FP_REG_P (operands[1]) ||
2874 (GET_CODE (operands[1]) == SUBREG
2875 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2877 "ix86_split_long_move (operands); DONE;")
2880 [(set (match_operand 0 "register_operand" "")
2881 (match_operand 1 "memory_operand" ""))]
2883 && GET_CODE (operands[1]) == MEM
2884 && (GET_MODE (operands[0]) == XFmode
2885 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2886 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2887 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2888 [(set (match_dup 0) (match_dup 1))]
2890 rtx c = get_pool_constant (XEXP (operands[1], 0));
2891 rtx r = operands[0];
2893 if (GET_CODE (r) == SUBREG)
2898 if (!standard_sse_constant_p (c))
2901 else if (FP_REG_P (r))
2903 if (!standard_80387_constant_p (c))
2906 else if (MMX_REG_P (r))
2912 (define_insn "swapxf"
2913 [(set (match_operand:XF 0 "register_operand" "+f")
2914 (match_operand:XF 1 "register_operand" "+f"))
2919 if (STACK_TOP_P (operands[0]))
2924 [(set_attr "type" "fxch")
2925 (set_attr "mode" "XF")])
2927 ;; Zero extension instructions
2929 (define_expand "zero_extendhisi2"
2930 [(set (match_operand:SI 0 "register_operand" "")
2931 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2934 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2936 operands[1] = force_reg (HImode, operands[1]);
2937 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2942 (define_insn "zero_extendhisi2_and"
2943 [(set (match_operand:SI 0 "register_operand" "=r")
2944 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2945 (clobber (reg:CC 17))]
2946 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2948 [(set_attr "type" "alu1")
2949 (set_attr "mode" "SI")])
2952 [(set (match_operand:SI 0 "register_operand" "")
2953 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2954 (clobber (reg:CC 17))]
2955 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2956 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2957 (clobber (reg:CC 17))])]
2960 (define_insn "*zero_extendhisi2_movzwl"
2961 [(set (match_operand:SI 0 "register_operand" "=r")
2962 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2963 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2964 "movz{wl|x}\t{%1, %0|%0, %1}"
2965 [(set_attr "type" "imovx")
2966 (set_attr "mode" "SI")])
2968 (define_expand "zero_extendqihi2"
2970 [(set (match_operand:HI 0 "register_operand" "")
2971 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2972 (clobber (reg:CC 17))])]
2976 (define_insn "*zero_extendqihi2_and"
2977 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2978 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2979 (clobber (reg:CC 17))]
2980 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2982 [(set_attr "type" "alu1")
2983 (set_attr "mode" "HI")])
2985 (define_insn "*zero_extendqihi2_movzbw_and"
2986 [(set (match_operand:HI 0 "register_operand" "=r,r")
2987 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2988 (clobber (reg:CC 17))]
2989 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2991 [(set_attr "type" "imovx,alu1")
2992 (set_attr "mode" "HI")])
2994 (define_insn "*zero_extendqihi2_movzbw"
2995 [(set (match_operand:HI 0 "register_operand" "=r")
2996 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2997 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2998 "movz{bw|x}\t{%1, %0|%0, %1}"
2999 [(set_attr "type" "imovx")
3000 (set_attr "mode" "HI")])
3002 ;; For the movzbw case strip only the clobber
3004 [(set (match_operand:HI 0 "register_operand" "")
3005 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3006 (clobber (reg:CC 17))]
3008 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3009 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3010 [(set (match_operand:HI 0 "register_operand" "")
3011 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3013 ;; When source and destination does not overlap, clear destination
3014 ;; first and then do the movb
3016 [(set (match_operand:HI 0 "register_operand" "")
3017 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3018 (clobber (reg:CC 17))]
3020 && ANY_QI_REG_P (operands[0])
3021 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3022 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3023 [(set (match_dup 0) (const_int 0))
3024 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3025 "operands[2] = gen_lowpart (QImode, operands[0]);")
3027 ;; Rest is handled by single and.
3029 [(set (match_operand:HI 0 "register_operand" "")
3030 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3031 (clobber (reg:CC 17))]
3033 && true_regnum (operands[0]) == true_regnum (operands[1])"
3034 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3035 (clobber (reg:CC 17))])]
3038 (define_expand "zero_extendqisi2"
3040 [(set (match_operand:SI 0 "register_operand" "")
3041 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3042 (clobber (reg:CC 17))])]
3046 (define_insn "*zero_extendqisi2_and"
3047 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3048 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3049 (clobber (reg:CC 17))]
3050 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3052 [(set_attr "type" "alu1")
3053 (set_attr "mode" "SI")])
3055 (define_insn "*zero_extendqisi2_movzbw_and"
3056 [(set (match_operand:SI 0 "register_operand" "=r,r")
3057 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3058 (clobber (reg:CC 17))]
3059 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3061 [(set_attr "type" "imovx,alu1")
3062 (set_attr "mode" "SI")])
3064 (define_insn "*zero_extendqisi2_movzbw"
3065 [(set (match_operand:SI 0 "register_operand" "=r")
3066 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3067 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3068 "movz{bl|x}\t{%1, %0|%0, %1}"
3069 [(set_attr "type" "imovx")
3070 (set_attr "mode" "SI")])
3072 ;; For the movzbl case strip only the clobber
3074 [(set (match_operand:SI 0 "register_operand" "")
3075 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3076 (clobber (reg:CC 17))]
3078 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3079 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3081 (zero_extend:SI (match_dup 1)))])
3083 ;; When source and destination does not overlap, clear destination
3084 ;; first and then do the movb
3086 [(set (match_operand:SI 0 "register_operand" "")
3087 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3088 (clobber (reg:CC 17))]
3090 && ANY_QI_REG_P (operands[0])
3091 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3092 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3093 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3094 [(set (match_dup 0) (const_int 0))
3095 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3096 "operands[2] = gen_lowpart (QImode, operands[0]);")
3098 ;; Rest is handled by single and.
3100 [(set (match_operand:SI 0 "register_operand" "")
3101 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3102 (clobber (reg:CC 17))]
3104 && true_regnum (operands[0]) == true_regnum (operands[1])"
3105 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3106 (clobber (reg:CC 17))])]
3109 ;; %%% Kill me once multi-word ops are sane.
3110 (define_expand "zero_extendsidi2"
3111 [(set (match_operand:DI 0 "register_operand" "=r")
3112 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3116 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3121 (define_insn "zero_extendsidi2_32"
3122 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3123 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3124 (clobber (reg:CC 17))]
3125 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3130 movd\t{%1, %0|%0, %1}
3131 movd\t{%1, %0|%0, %1}"
3132 [(set_attr "mode" "SI,SI,SI,DI,TI")
3133 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3135 (define_insn "*zero_extendsidi2_32_1"
3136 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3137 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3138 (clobber (reg:CC 17))]
3139 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3144 movd\t{%1, %0|%0, %1}
3145 movd\t{%1, %0|%0, %1}"
3146 [(set_attr "mode" "SI,SI,SI,DI,TI")
3147 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3149 (define_insn "zero_extendsidi2_rex64"
3150 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3151 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3152 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3154 mov\t{%k1, %k0|%k0, %k1}
3156 movd\t{%1, %0|%0, %1}
3157 movd\t{%1, %0|%0, %1}"
3158 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3159 (set_attr "mode" "SI,DI,DI,TI")])
3161 (define_insn "*zero_extendsidi2_rex64_1"
3162 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3163 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3164 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3166 mov\t{%k1, %k0|%k0, %k1}
3168 movd\t{%1, %0|%0, %1}
3169 movd\t{%1, %0|%0, %1}"
3170 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3171 (set_attr "mode" "SI,DI,SI,SI")])
3174 [(set (match_operand:DI 0 "memory_operand" "")
3175 (zero_extend:DI (match_dup 0)))]
3177 [(set (match_dup 4) (const_int 0))]
3178 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3181 [(set (match_operand:DI 0 "register_operand" "")
3182 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3183 (clobber (reg:CC 17))]
3184 "!TARGET_64BIT && reload_completed
3185 && true_regnum (operands[0]) == true_regnum (operands[1])"
3186 [(set (match_dup 4) (const_int 0))]
3187 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3190 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3191 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3192 (clobber (reg:CC 17))]
3193 "!TARGET_64BIT && reload_completed
3194 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3195 [(set (match_dup 3) (match_dup 1))
3196 (set (match_dup 4) (const_int 0))]
3197 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3199 (define_insn "zero_extendhidi2"
3200 [(set (match_operand:DI 0 "register_operand" "=r,r")
3201 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3204 movz{wl|x}\t{%1, %k0|%k0, %1}
3205 movz{wq|x}\t{%1, %0|%0, %1}"
3206 [(set_attr "type" "imovx")
3207 (set_attr "mode" "SI,DI")])
3209 (define_insn "zero_extendqidi2"
3210 [(set (match_operand:DI 0 "register_operand" "=r,r")
3211 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3214 movz{bl|x}\t{%1, %k0|%k0, %1}
3215 movz{bq|x}\t{%1, %0|%0, %1}"
3216 [(set_attr "type" "imovx")
3217 (set_attr "mode" "SI,DI")])
3219 ;; Sign extension instructions
3221 (define_expand "extendsidi2"
3222 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3223 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3224 (clobber (reg:CC 17))
3225 (clobber (match_scratch:SI 2 ""))])]
3230 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3235 (define_insn "*extendsidi2_1"
3236 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3237 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3238 (clobber (reg:CC 17))
3239 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3243 (define_insn "extendsidi2_rex64"
3244 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3245 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3249 movs{lq|x}\t{%1,%0|%0, %1}"
3250 [(set_attr "type" "imovx")
3251 (set_attr "mode" "DI")
3252 (set_attr "prefix_0f" "0")
3253 (set_attr "modrm" "0,1")])
3255 (define_insn "extendhidi2"
3256 [(set (match_operand:DI 0 "register_operand" "=r")
3257 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3259 "movs{wq|x}\t{%1,%0|%0, %1}"
3260 [(set_attr "type" "imovx")
3261 (set_attr "mode" "DI")])
3263 (define_insn "extendqidi2"
3264 [(set (match_operand:DI 0 "register_operand" "=r")
3265 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3267 "movs{bq|x}\t{%1,%0|%0, %1}"
3268 [(set_attr "type" "imovx")
3269 (set_attr "mode" "DI")])
3271 ;; Extend to memory case when source register does die.
3273 [(set (match_operand:DI 0 "memory_operand" "")
3274 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3275 (clobber (reg:CC 17))
3276 (clobber (match_operand:SI 2 "register_operand" ""))]
3278 && dead_or_set_p (insn, operands[1])
3279 && !reg_mentioned_p (operands[1], operands[0]))"
3280 [(set (match_dup 3) (match_dup 1))
3281 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3282 (clobber (reg:CC 17))])
3283 (set (match_dup 4) (match_dup 1))]
3284 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3286 ;; Extend to memory case when source register does not die.
3288 [(set (match_operand:DI 0 "memory_operand" "")
3289 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3290 (clobber (reg:CC 17))
3291 (clobber (match_operand:SI 2 "register_operand" ""))]
3295 split_di (&operands[0], 1, &operands[3], &operands[4]);
3297 emit_move_insn (operands[3], operands[1]);
3299 /* Generate a cltd if possible and doing so it profitable. */
3300 if (true_regnum (operands[1]) == 0
3301 && true_regnum (operands[2]) == 1
3302 && (optimize_size || TARGET_USE_CLTD))
3304 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3308 emit_move_insn (operands[2], operands[1]);
3309 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3311 emit_move_insn (operands[4], operands[2]);
3315 ;; Extend to register case. Optimize case where source and destination
3316 ;; registers match and cases where we can use cltd.
3318 [(set (match_operand:DI 0 "register_operand" "")
3319 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3320 (clobber (reg:CC 17))
3321 (clobber (match_scratch:SI 2 ""))]
3325 split_di (&operands[0], 1, &operands[3], &operands[4]);
3327 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3328 emit_move_insn (operands[3], operands[1]);
3330 /* Generate a cltd if possible and doing so it profitable. */
3331 if (true_regnum (operands[3]) == 0
3332 && (optimize_size || TARGET_USE_CLTD))
3334 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3338 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3339 emit_move_insn (operands[4], operands[1]);
3341 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3345 (define_insn "extendhisi2"
3346 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3347 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3350 switch (get_attr_prefix_0f (insn))
3353 return "{cwtl|cwde}";
3355 return "movs{wl|x}\t{%1,%0|%0, %1}";
3358 [(set_attr "type" "imovx")
3359 (set_attr "mode" "SI")
3360 (set (attr "prefix_0f")
3361 ;; movsx is short decodable while cwtl is vector decoded.
3362 (if_then_else (and (eq_attr "cpu" "!k6")
3363 (eq_attr "alternative" "0"))
3365 (const_string "1")))
3367 (if_then_else (eq_attr "prefix_0f" "0")
3369 (const_string "1")))])
3371 (define_insn "*extendhisi2_zext"
3372 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3374 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3377 switch (get_attr_prefix_0f (insn))
3380 return "{cwtl|cwde}";
3382 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3385 [(set_attr "type" "imovx")
3386 (set_attr "mode" "SI")
3387 (set (attr "prefix_0f")
3388 ;; movsx is short decodable while cwtl is vector decoded.
3389 (if_then_else (and (eq_attr "cpu" "!k6")
3390 (eq_attr "alternative" "0"))
3392 (const_string "1")))
3394 (if_then_else (eq_attr "prefix_0f" "0")
3396 (const_string "1")))])
3398 (define_insn "extendqihi2"
3399 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3400 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3403 switch (get_attr_prefix_0f (insn))
3406 return "{cbtw|cbw}";
3408 return "movs{bw|x}\t{%1,%0|%0, %1}";
3411 [(set_attr "type" "imovx")
3412 (set_attr "mode" "HI")
3413 (set (attr "prefix_0f")
3414 ;; movsx is short decodable while cwtl is vector decoded.
3415 (if_then_else (and (eq_attr "cpu" "!k6")
3416 (eq_attr "alternative" "0"))
3418 (const_string "1")))
3420 (if_then_else (eq_attr "prefix_0f" "0")
3422 (const_string "1")))])
3424 (define_insn "extendqisi2"
3425 [(set (match_operand:SI 0 "register_operand" "=r")
3426 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3428 "movs{bl|x}\t{%1,%0|%0, %1}"
3429 [(set_attr "type" "imovx")
3430 (set_attr "mode" "SI")])
3432 (define_insn "*extendqisi2_zext"
3433 [(set (match_operand:DI 0 "register_operand" "=r")
3435 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3437 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3438 [(set_attr "type" "imovx")
3439 (set_attr "mode" "SI")])
3441 ;; Conversions between float and double.
3443 ;; These are all no-ops in the model used for the 80387. So just
3446 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3447 (define_insn "*dummy_extendsfdf2"
3448 [(set (match_operand:DF 0 "push_operand" "=<")
3449 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3454 [(set (match_operand:DF 0 "push_operand" "")
3455 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3457 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3458 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3461 [(set (match_operand:DF 0 "push_operand" "")
3462 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3464 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3465 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3467 (define_insn "*dummy_extendsfxf2"
3468 [(set (match_operand:XF 0 "push_operand" "=<")
3469 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3474 [(set (match_operand:XF 0 "push_operand" "")
3475 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3477 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
3478 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
3479 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3482 [(set (match_operand:XF 0 "push_operand" "")
3483 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3485 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
3486 (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
3487 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3490 [(set (match_operand:XF 0 "push_operand" "")
3491 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3493 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
3494 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
3495 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3498 [(set (match_operand:XF 0 "push_operand" "")
3499 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3501 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
3502 (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
3503 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3505 (define_expand "extendsfdf2"
3506 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3507 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3508 "TARGET_80387 || TARGET_SSE2"
3510 /* ??? Needed for compress_float_constant since all fp constants
3511 are LEGITIMATE_CONSTANT_P. */
3512 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3513 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3514 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3515 operands[1] = force_reg (SFmode, operands[1]);
3518 (define_insn "*extendsfdf2_1"
3519 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3520 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3521 "(TARGET_80387 || TARGET_SSE2)
3522 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3524 switch (which_alternative)
3527 if (REG_P (operands[1])
3528 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3530 else if (STACK_TOP_P (operands[0]))
3531 return "fld%z1\t%y1";
3536 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3537 return "fstp%z0\t%y0";
3540 return "fst%z0\t%y0";
3542 return "cvtss2sd\t{%1, %0|%0, %1}";
3548 [(set_attr "type" "fmov,fmov,ssecvt")
3549 (set_attr "mode" "SF,XF,DF")])
3551 (define_insn "*extendsfdf2_1_sse_only"
3552 [(set (match_operand:DF 0 "register_operand" "=Y")
3553 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3554 "!TARGET_80387 && TARGET_SSE2
3555 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3556 "cvtss2sd\t{%1, %0|%0, %1}"
3557 [(set_attr "type" "ssecvt")
3558 (set_attr "mode" "DF")])
3560 (define_expand "extendsfxf2"
3561 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3562 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3565 /* ??? Needed for compress_float_constant since all fp constants
3566 are LEGITIMATE_CONSTANT_P. */
3567 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3568 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3569 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3570 operands[1] = force_reg (SFmode, operands[1]);
3573 (define_insn "*extendsfxf2_1"
3574 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3575 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3577 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3579 switch (which_alternative)
3582 if (REG_P (operands[1])
3583 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3585 else if (STACK_TOP_P (operands[0]))
3586 return "fld%z1\t%y1";
3591 /* There is no non-popping store to memory for XFmode. So if
3592 we need one, follow the store with a load. */
3593 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3594 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3596 return "fstp%z0\t%y0";
3602 [(set_attr "type" "fmov")
3603 (set_attr "mode" "SF,XF")])
3605 (define_expand "extenddfxf2"
3606 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3607 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3610 /* ??? Needed for compress_float_constant since all fp constants
3611 are LEGITIMATE_CONSTANT_P. */
3612 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3613 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3614 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3615 operands[1] = force_reg (DFmode, operands[1]);
3618 (define_insn "*extenddfxf2_1"
3619 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3620 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3622 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3624 switch (which_alternative)
3627 if (REG_P (operands[1])
3628 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3630 else if (STACK_TOP_P (operands[0]))
3631 return "fld%z1\t%y1";
3636 /* There is no non-popping store to memory for XFmode. So if
3637 we need one, follow the store with a load. */
3638 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3639 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3641 return "fstp%z0\t%y0";
3647 [(set_attr "type" "fmov")
3648 (set_attr "mode" "DF,XF")])
3650 ;; %%% This seems bad bad news.
3651 ;; This cannot output into an f-reg because there is no way to be sure
3652 ;; of truncating in that case. Otherwise this is just like a simple move
3653 ;; insn. So we pretend we can output to a reg in order to get better
3654 ;; register preferencing, but we really use a stack slot.
3656 (define_expand "truncdfsf2"
3657 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3659 (match_operand:DF 1 "register_operand" "")))
3660 (clobber (match_dup 2))])]
3661 "TARGET_80387 || TARGET_SSE2"
3664 operands[2] = assign_386_stack_local (SFmode, 0);
3667 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3672 (define_insn "*truncdfsf2_1"
3673 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3675 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3676 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3677 "TARGET_80387 && !TARGET_SSE2"
3679 switch (which_alternative)
3682 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3683 return "fstp%z0\t%y0";
3685 return "fst%z0\t%y0";
3690 [(set_attr "type" "fmov,multi,multi,multi")
3691 (set_attr "mode" "SF,SF,SF,SF")])
3693 (define_insn "*truncdfsf2_1_sse"
3694 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3696 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3697 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3698 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3700 switch (which_alternative)
3703 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3704 return "fstp%z0\t%y0";
3706 return "fst%z0\t%y0";
3713 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3714 (set_attr "mode" "SF,SF,SF,SF,DF")])
3716 (define_insn "*truncdfsf2_1_sse_nooverlap"
3717 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3719 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3720 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3721 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3723 switch (which_alternative)
3726 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3727 return "fstp%z0\t%y0";
3729 return "fst%z0\t%y0";
3736 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3737 (set_attr "mode" "SF,SF,SF,SF,DF")])
3739 (define_insn "*truncdfsf2_2"
3740 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3742 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3743 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3744 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3746 switch (which_alternative)
3750 return "cvtsd2ss\t{%1, %0|%0, %1}";
3752 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3753 return "fstp%z0\t%y0";
3755 return "fst%z0\t%y0";
3760 [(set_attr "type" "ssecvt,ssecvt,fmov")
3761 (set_attr "athlon_decode" "vector,double,*")
3762 (set_attr "mode" "SF,SF,SF")])
3764 (define_insn "*truncdfsf2_2_nooverlap"
3765 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3767 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3768 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3769 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3771 switch (which_alternative)
3776 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3777 return "fstp%z0\t%y0";
3779 return "fst%z0\t%y0";
3784 [(set_attr "type" "ssecvt,fmov")
3785 (set_attr "mode" "DF,SF")])
3787 (define_insn "*truncdfsf2_3"
3788 [(set (match_operand:SF 0 "memory_operand" "=m")
3790 (match_operand:DF 1 "register_operand" "f")))]
3793 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3794 return "fstp%z0\t%y0";
3796 return "fst%z0\t%y0";
3798 [(set_attr "type" "fmov")
3799 (set_attr "mode" "SF")])
3801 (define_insn "truncdfsf2_sse_only"
3802 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
3804 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
3805 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3806 "cvtsd2ss\t{%1, %0|%0, %1}"
3807 [(set_attr "type" "ssecvt")
3808 (set_attr "athlon_decode" "vector,double")
3809 (set_attr "mode" "SF")])
3811 (define_insn "*truncdfsf2_sse_only_nooverlap"
3812 [(set (match_operand:SF 0 "register_operand" "=&Y")
3814 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3815 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3817 [(set_attr "type" "ssecvt")
3818 (set_attr "mode" "DF")])
3821 [(set (match_operand:SF 0 "memory_operand" "")
3823 (match_operand:DF 1 "register_operand" "")))
3824 (clobber (match_operand:SF 2 "memory_operand" ""))]
3826 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3829 ; Avoid possible reformatting penalty on the destination by first
3832 [(set (match_operand:SF 0 "register_operand" "")
3834 (match_operand:DF 1 "nonimmediate_operand" "")))
3835 (clobber (match_operand 2 "" ""))]
3836 "TARGET_80387 && reload_completed
3837 && SSE_REG_P (operands[0])
3838 && !STACK_REG_P (operands[1])"
3842 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
3843 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3846 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3847 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3848 /* simplify_gen_subreg refuses to widen memory references. */
3849 if (GET_CODE (src) == SUBREG)
3850 alter_subreg (&src);
3851 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3853 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3854 emit_insn (gen_cvtsd2ss (dest, dest, src));
3860 [(set (match_operand:SF 0 "register_operand" "")
3862 (match_operand:DF 1 "nonimmediate_operand" "")))]
3863 "TARGET_80387 && reload_completed
3864 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3868 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3869 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3870 /* simplify_gen_subreg refuses to widen memory references. */
3871 if (GET_CODE (src) == SUBREG)
3872 alter_subreg (&src);
3873 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3875 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3876 emit_insn (gen_cvtsd2ss (dest, dest, src));
3881 [(set (match_operand:SF 0 "register_operand" "")
3883 (match_operand:DF 1 "fp_register_operand" "")))
3884 (clobber (match_operand:SF 2 "memory_operand" ""))]
3885 "TARGET_80387 && reload_completed"
3886 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3887 (set (match_dup 0) (match_dup 2))]
3890 (define_expand "truncxfsf2"
3891 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3893 (match_operand:XF 1 "register_operand" "")))
3894 (clobber (match_dup 2))])]
3896 "operands[2] = assign_386_stack_local (SFmode, 0);")
3898 (define_insn "*truncxfsf2_1"
3899 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3901 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3902 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3905 switch (which_alternative)
3908 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3909 return "fstp%z0\t%y0";
3911 return "fst%z0\t%y0";
3916 [(set_attr "type" "fmov,multi,multi,multi")
3917 (set_attr "mode" "SF")])
3919 (define_insn "*truncxfsf2_2"
3920 [(set (match_operand:SF 0 "memory_operand" "=m")
3922 (match_operand:XF 1 "register_operand" "f")))]
3925 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3926 return "fstp%z0\t%y0";
3928 return "fst%z0\t%y0";
3930 [(set_attr "type" "fmov")
3931 (set_attr "mode" "SF")])
3934 [(set (match_operand:SF 0 "memory_operand" "")
3936 (match_operand:XF 1 "register_operand" "")))
3937 (clobber (match_operand:SF 2 "memory_operand" ""))]
3939 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3943 [(set (match_operand:SF 0 "register_operand" "")
3945 (match_operand:XF 1 "register_operand" "")))
3946 (clobber (match_operand:SF 2 "memory_operand" ""))]
3947 "TARGET_80387 && reload_completed"
3948 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3949 (set (match_dup 0) (match_dup 2))]
3952 (define_expand "truncxfdf2"
3953 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3955 (match_operand:XF 1 "register_operand" "")))
3956 (clobber (match_dup 2))])]
3958 "operands[2] = assign_386_stack_local (DFmode, 0);")
3960 (define_insn "*truncxfdf2_1"
3961 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3963 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3964 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3967 switch (which_alternative)
3970 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3971 return "fstp%z0\t%y0";
3973 return "fst%z0\t%y0";
3979 [(set_attr "type" "fmov,multi,multi,multi")
3980 (set_attr "mode" "DF")])
3982 (define_insn "*truncxfdf2_2"
3983 [(set (match_operand:DF 0 "memory_operand" "=m")
3985 (match_operand:XF 1 "register_operand" "f")))]
3988 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3989 return "fstp%z0\t%y0";
3991 return "fst%z0\t%y0";
3993 [(set_attr "type" "fmov")
3994 (set_attr "mode" "DF")])
3997 [(set (match_operand:DF 0 "memory_operand" "")
3999 (match_operand:XF 1 "register_operand" "")))
4000 (clobber (match_operand:DF 2 "memory_operand" ""))]
4002 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4006 [(set (match_operand:DF 0 "register_operand" "")
4008 (match_operand:XF 1 "register_operand" "")))
4009 (clobber (match_operand:DF 2 "memory_operand" ""))]
4010 "TARGET_80387 && reload_completed"
4011 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4012 (set (match_dup 0) (match_dup 2))]
4016 ;; %%% Break up all these bad boys.
4018 ;; Signed conversion to DImode.
4020 (define_expand "fix_truncxfdi2"
4021 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4022 (fix:DI (match_operand:XF 1 "register_operand" "")))
4023 (clobber (reg:CC 17))])]
4027 (define_expand "fix_truncdfdi2"
4028 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4029 (fix:DI (match_operand:DF 1 "register_operand" "")))
4030 (clobber (reg:CC 17))])]
4031 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4033 if (TARGET_64BIT && TARGET_SSE2)
4035 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4036 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4037 if (out != operands[0])
4038 emit_move_insn (operands[0], out);
4043 (define_expand "fix_truncsfdi2"
4044 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4045 (fix:DI (match_operand:SF 1 "register_operand" "")))
4046 (clobber (reg:CC 17))])]
4047 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4049 if (TARGET_SSE && TARGET_64BIT)
4051 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4052 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4053 if (out != operands[0])
4054 emit_move_insn (operands[0], out);
4059 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4060 ;; of the machinery.
4061 (define_insn_and_split "*fix_truncdi_1"
4062 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4063 (fix:DI (match_operand 1 "register_operand" "f,f")))
4064 (clobber (reg:CC 17))]
4065 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4066 && !reload_completed && !reload_in_progress
4067 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4072 ix86_optimize_mode_switching = 1;
4073 operands[2] = assign_386_stack_local (HImode, 1);
4074 operands[3] = assign_386_stack_local (HImode, 2);
4075 if (memory_operand (operands[0], VOIDmode))
4076 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4077 operands[2], operands[3]));
4080 operands[4] = assign_386_stack_local (DImode, 0);
4081 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4082 operands[2], operands[3],
4087 [(set_attr "type" "fistp")
4088 (set_attr "mode" "DI")])
4090 (define_insn "fix_truncdi_nomemory"
4091 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4092 (fix:DI (match_operand 1 "register_operand" "f,f")))
4093 (use (match_operand:HI 2 "memory_operand" "m,m"))
4094 (use (match_operand:HI 3 "memory_operand" "m,m"))
4095 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4096 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4097 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4098 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4100 [(set_attr "type" "fistp")
4101 (set_attr "mode" "DI")])
4103 (define_insn "fix_truncdi_memory"
4104 [(set (match_operand:DI 0 "memory_operand" "=m")
4105 (fix:DI (match_operand 1 "register_operand" "f")))
4106 (use (match_operand:HI 2 "memory_operand" "m"))
4107 (use (match_operand:HI 3 "memory_operand" "m"))
4108 (clobber (match_scratch:DF 4 "=&1f"))]
4109 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4110 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4111 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4112 [(set_attr "type" "fistp")
4113 (set_attr "mode" "DI")])
4116 [(set (match_operand:DI 0 "register_operand" "")
4117 (fix:DI (match_operand 1 "register_operand" "")))
4118 (use (match_operand:HI 2 "memory_operand" ""))
4119 (use (match_operand:HI 3 "memory_operand" ""))
4120 (clobber (match_operand:DI 4 "memory_operand" ""))
4121 (clobber (match_scratch 5 ""))]
4123 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4126 (clobber (match_dup 5))])
4127 (set (match_dup 0) (match_dup 4))]
4131 [(set (match_operand:DI 0 "memory_operand" "")
4132 (fix:DI (match_operand 1 "register_operand" "")))
4133 (use (match_operand:HI 2 "memory_operand" ""))
4134 (use (match_operand:HI 3 "memory_operand" ""))
4135 (clobber (match_operand:DI 4 "memory_operand" ""))
4136 (clobber (match_scratch 5 ""))]
4138 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4141 (clobber (match_dup 5))])]
4144 ;; When SSE available, it is always faster to use it!
4145 (define_insn "fix_truncsfdi_sse"
4146 [(set (match_operand:DI 0 "register_operand" "=r,r")
4147 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4148 "TARGET_64BIT && TARGET_SSE"
4149 "cvttss2si{q}\t{%1, %0|%0, %1}"
4150 [(set_attr "type" "sseicvt")
4151 (set_attr "mode" "SF")
4152 (set_attr "athlon_decode" "double,vector")])
4154 ;; Avoid vector decoded form of the instruction.
4156 [(match_scratch:SF 2 "x")
4157 (set (match_operand:DI 0 "register_operand" "")
4158 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4159 "TARGET_K8 && !optimize_size"
4160 [(set (match_dup 2) (match_dup 1))
4161 (set (match_dup 0) (fix:DI (match_dup 2)))]
4164 (define_insn "fix_truncdfdi_sse"
4165 [(set (match_operand:DI 0 "register_operand" "=r,r")
4166 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4167 "TARGET_64BIT && TARGET_SSE2"
4168 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4169 [(set_attr "type" "sseicvt,sseicvt")
4170 (set_attr "mode" "DF")
4171 (set_attr "athlon_decode" "double,vector")])
4173 ;; Avoid vector decoded form of the instruction.
4175 [(match_scratch:DF 2 "Y")
4176 (set (match_operand:DI 0 "register_operand" "")
4177 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4178 "TARGET_K8 && !optimize_size"
4179 [(set (match_dup 2) (match_dup 1))
4180 (set (match_dup 0) (fix:DI (match_dup 2)))]
4183 ;; Signed conversion to SImode.
4185 (define_expand "fix_truncxfsi2"
4186 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4187 (fix:SI (match_operand:XF 1 "register_operand" "")))
4188 (clobber (reg:CC 17))])]
4192 (define_expand "fix_truncdfsi2"
4193 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4194 (fix:SI (match_operand:DF 1 "register_operand" "")))
4195 (clobber (reg:CC 17))])]
4196 "TARGET_80387 || TARGET_SSE2"
4200 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4201 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4202 if (out != operands[0])
4203 emit_move_insn (operands[0], out);
4208 (define_expand "fix_truncsfsi2"
4209 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4210 (fix:SI (match_operand:SF 1 "register_operand" "")))
4211 (clobber (reg:CC 17))])]
4212 "TARGET_80387 || TARGET_SSE"
4216 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4217 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4218 if (out != operands[0])
4219 emit_move_insn (operands[0], out);
4224 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4225 ;; of the machinery.
4226 (define_insn_and_split "*fix_truncsi_1"
4227 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4228 (fix:SI (match_operand 1 "register_operand" "f,f")))
4229 (clobber (reg:CC 17))]
4230 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4231 && !reload_completed && !reload_in_progress
4232 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4237 ix86_optimize_mode_switching = 1;
4238 operands[2] = assign_386_stack_local (HImode, 1);
4239 operands[3] = assign_386_stack_local (HImode, 2);
4240 if (memory_operand (operands[0], VOIDmode))
4241 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4242 operands[2], operands[3]));
4245 operands[4] = assign_386_stack_local (SImode, 0);
4246 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4247 operands[2], operands[3],
4252 [(set_attr "type" "fistp")
4253 (set_attr "mode" "SI")])
4255 (define_insn "fix_truncsi_nomemory"
4256 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4257 (fix:SI (match_operand 1 "register_operand" "f,f")))
4258 (use (match_operand:HI 2 "memory_operand" "m,m"))
4259 (use (match_operand:HI 3 "memory_operand" "m,m"))
4260 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4261 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4262 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4264 [(set_attr "type" "fistp")
4265 (set_attr "mode" "SI")])
4267 (define_insn "fix_truncsi_memory"
4268 [(set (match_operand:SI 0 "memory_operand" "=m")
4269 (fix:SI (match_operand 1 "register_operand" "f")))
4270 (use (match_operand:HI 2 "memory_operand" "m"))
4271 (use (match_operand:HI 3 "memory_operand" "m"))]
4272 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4273 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4274 "* return output_fix_trunc (insn, operands);"
4275 [(set_attr "type" "fistp")
4276 (set_attr "mode" "SI")])
4278 ;; When SSE available, it is always faster to use it!
4279 (define_insn "fix_truncsfsi_sse"
4280 [(set (match_operand:SI 0 "register_operand" "=r,r")
4281 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4283 "cvttss2si\t{%1, %0|%0, %1}"
4284 [(set_attr "type" "sseicvt")
4285 (set_attr "mode" "DF")
4286 (set_attr "athlon_decode" "double,vector")])
4288 ;; Avoid vector decoded form of the instruction.
4290 [(match_scratch:SF 2 "x")
4291 (set (match_operand:SI 0 "register_operand" "")
4292 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4293 "TARGET_K8 && !optimize_size"
4294 [(set (match_dup 2) (match_dup 1))
4295 (set (match_dup 0) (fix:SI (match_dup 2)))]
4298 (define_insn "fix_truncdfsi_sse"
4299 [(set (match_operand:SI 0 "register_operand" "=r,r")
4300 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4302 "cvttsd2si\t{%1, %0|%0, %1}"
4303 [(set_attr "type" "sseicvt")
4304 (set_attr "mode" "DF")
4305 (set_attr "athlon_decode" "double,vector")])
4307 ;; Avoid vector decoded form of the instruction.
4309 [(match_scratch:DF 2 "Y")
4310 (set (match_operand:SI 0 "register_operand" "")
4311 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4312 "TARGET_K8 && !optimize_size"
4313 [(set (match_dup 2) (match_dup 1))
4314 (set (match_dup 0) (fix:SI (match_dup 2)))]
4318 [(set (match_operand:SI 0 "register_operand" "")
4319 (fix:SI (match_operand 1 "register_operand" "")))
4320 (use (match_operand:HI 2 "memory_operand" ""))
4321 (use (match_operand:HI 3 "memory_operand" ""))
4322 (clobber (match_operand:SI 4 "memory_operand" ""))]
4324 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4326 (use (match_dup 3))])
4327 (set (match_dup 0) (match_dup 4))]
4331 [(set (match_operand:SI 0 "memory_operand" "")
4332 (fix:SI (match_operand 1 "register_operand" "")))
4333 (use (match_operand:HI 2 "memory_operand" ""))
4334 (use (match_operand:HI 3 "memory_operand" ""))
4335 (clobber (match_operand:SI 4 "memory_operand" ""))]
4337 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4339 (use (match_dup 3))])]
4342 ;; Signed conversion to HImode.
4344 (define_expand "fix_truncxfhi2"
4345 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4346 (fix:HI (match_operand:XF 1 "register_operand" "")))
4347 (clobber (reg:CC 17))])]
4351 (define_expand "fix_truncdfhi2"
4352 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4353 (fix:HI (match_operand:DF 1 "register_operand" "")))
4354 (clobber (reg:CC 17))])]
4355 "TARGET_80387 && !TARGET_SSE2"
4358 (define_expand "fix_truncsfhi2"
4359 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4360 (fix:HI (match_operand:SF 1 "register_operand" "")))
4361 (clobber (reg:CC 17))])]
4362 "TARGET_80387 && !TARGET_SSE"
4365 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4366 ;; of the machinery.
4367 (define_insn_and_split "*fix_trunchi_1"
4368 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4369 (fix:HI (match_operand 1 "register_operand" "f,f")))
4370 (clobber (reg:CC 17))]
4371 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4372 && !reload_completed && !reload_in_progress
4373 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4378 ix86_optimize_mode_switching = 1;
4379 operands[2] = assign_386_stack_local (HImode, 1);
4380 operands[3] = assign_386_stack_local (HImode, 2);
4381 if (memory_operand (operands[0], VOIDmode))
4382 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4383 operands[2], operands[3]));
4386 operands[4] = assign_386_stack_local (HImode, 0);
4387 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4388 operands[2], operands[3],
4393 [(set_attr "type" "fistp")
4394 (set_attr "mode" "HI")])
4396 (define_insn "fix_trunchi_nomemory"
4397 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4398 (fix:HI (match_operand 1 "register_operand" "f,f")))
4399 (use (match_operand:HI 2 "memory_operand" "m,m"))
4400 (use (match_operand:HI 3 "memory_operand" "m,m"))
4401 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4402 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4403 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4405 [(set_attr "type" "fistp")
4406 (set_attr "mode" "HI")])
4408 (define_insn "fix_trunchi_memory"
4409 [(set (match_operand:HI 0 "memory_operand" "=m")
4410 (fix:HI (match_operand 1 "register_operand" "f")))
4411 (use (match_operand:HI 2 "memory_operand" "m"))
4412 (use (match_operand:HI 3 "memory_operand" "m"))]
4413 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4414 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4415 "* return output_fix_trunc (insn, operands);"
4416 [(set_attr "type" "fistp")
4417 (set_attr "mode" "HI")])
4420 [(set (match_operand:HI 0 "memory_operand" "")
4421 (fix:HI (match_operand 1 "register_operand" "")))
4422 (use (match_operand:HI 2 "memory_operand" ""))
4423 (use (match_operand:HI 3 "memory_operand" ""))
4424 (clobber (match_operand:HI 4 "memory_operand" ""))]
4426 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4428 (use (match_dup 3))])]
4432 [(set (match_operand:HI 0 "register_operand" "")
4433 (fix:HI (match_operand 1 "register_operand" "")))
4434 (use (match_operand:HI 2 "memory_operand" ""))
4435 (use (match_operand:HI 3 "memory_operand" ""))
4436 (clobber (match_operand:HI 4 "memory_operand" ""))]
4438 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4441 (clobber (match_dup 4))])
4442 (set (match_dup 0) (match_dup 4))]
4446 (define_insn "x86_fnstcw_1"
4447 [(set (match_operand:HI 0 "memory_operand" "=m")
4448 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4451 [(set_attr "length" "2")
4452 (set_attr "mode" "HI")
4453 (set_attr "unit" "i387")
4454 (set_attr "ppro_uops" "few")])
4456 (define_insn "x86_fldcw_1"
4458 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4461 [(set_attr "length" "2")
4462 (set_attr "mode" "HI")
4463 (set_attr "unit" "i387")
4464 (set_attr "athlon_decode" "vector")
4465 (set_attr "ppro_uops" "few")])
4467 ;; Conversion between fixed point and floating point.
4469 ;; Even though we only accept memory inputs, the backend _really_
4470 ;; wants to be able to do this between registers.
4472 (define_expand "floathisf2"
4473 [(set (match_operand:SF 0 "register_operand" "")
4474 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4475 "TARGET_SSE || TARGET_80387"
4477 if (TARGET_SSE && TARGET_SSE_MATH)
4479 emit_insn (gen_floatsisf2 (operands[0],
4480 convert_to_mode (SImode, operands[1], 0)));
4485 (define_insn "*floathisf2_1"
4486 [(set (match_operand:SF 0 "register_operand" "=f,f")
4487 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4488 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4492 [(set_attr "type" "fmov,multi")
4493 (set_attr "mode" "SF")
4494 (set_attr "fp_int_src" "true")])
4496 (define_expand "floatsisf2"
4497 [(set (match_operand:SF 0 "register_operand" "")
4498 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4499 "TARGET_SSE || TARGET_80387"
4502 (define_insn "*floatsisf2_i387"
4503 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4504 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4505 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4509 cvtsi2ss\t{%1, %0|%0, %1}
4510 cvtsi2ss\t{%1, %0|%0, %1}"
4511 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4512 (set_attr "mode" "SF")
4513 (set_attr "athlon_decode" "*,*,vector,double")
4514 (set_attr "fp_int_src" "true")])
4516 (define_insn "*floatsisf2_sse"
4517 [(set (match_operand:SF 0 "register_operand" "=x,x")
4518 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4520 "cvtsi2ss\t{%1, %0|%0, %1}"
4521 [(set_attr "type" "sseicvt")
4522 (set_attr "mode" "SF")
4523 (set_attr "athlon_decode" "vector,double")
4524 (set_attr "fp_int_src" "true")])
4526 ; Avoid possible reformatting penalty on the destination by first
4529 [(set (match_operand:SF 0 "register_operand" "")
4530 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4531 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4532 && SSE_REG_P (operands[0])"
4536 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4537 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4538 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4542 (define_expand "floatdisf2"
4543 [(set (match_operand:SF 0 "register_operand" "")
4544 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4545 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4548 (define_insn "*floatdisf2_i387_only"
4549 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4550 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4551 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4555 [(set_attr "type" "fmov,multi")
4556 (set_attr "mode" "SF")
4557 (set_attr "fp_int_src" "true")])
4559 (define_insn "*floatdisf2_i387"
4560 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4561 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4562 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4566 cvtsi2ss{q}\t{%1, %0|%0, %1}
4567 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4568 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4569 (set_attr "mode" "SF")
4570 (set_attr "athlon_decode" "*,*,vector,double")
4571 (set_attr "fp_int_src" "true")])
4573 (define_insn "*floatdisf2_sse"
4574 [(set (match_operand:SF 0 "register_operand" "=x,x")
4575 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4576 "TARGET_64BIT && TARGET_SSE"
4577 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4578 [(set_attr "type" "sseicvt")
4579 (set_attr "mode" "SF")
4580 (set_attr "athlon_decode" "vector,double")
4581 (set_attr "fp_int_src" "true")])
4583 ; Avoid possible reformatting penalty on the destination by first
4586 [(set (match_operand:SF 0 "register_operand" "")
4587 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4588 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4589 && SSE_REG_P (operands[0])"
4593 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4594 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4595 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4599 (define_expand "floathidf2"
4600 [(set (match_operand:DF 0 "register_operand" "")
4601 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4602 "TARGET_SSE2 || TARGET_80387"
4604 if (TARGET_SSE && TARGET_SSE_MATH)
4606 emit_insn (gen_floatsidf2 (operands[0],
4607 convert_to_mode (SImode, operands[1], 0)));
4612 (define_insn "*floathidf2_1"
4613 [(set (match_operand:DF 0 "register_operand" "=f,f")
4614 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4615 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4619 [(set_attr "type" "fmov,multi")
4620 (set_attr "mode" "DF")
4621 (set_attr "fp_int_src" "true")])
4623 (define_expand "floatsidf2"
4624 [(set (match_operand:DF 0 "register_operand" "")
4625 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4626 "TARGET_80387 || TARGET_SSE2"
4629 (define_insn "*floatsidf2_i387"
4630 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4631 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4632 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4636 cvtsi2sd\t{%1, %0|%0, %1}
4637 cvtsi2sd\t{%1, %0|%0, %1}"
4638 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4639 (set_attr "mode" "DF")
4640 (set_attr "athlon_decode" "*,*,double,direct")
4641 (set_attr "fp_int_src" "true")])
4643 (define_insn "*floatsidf2_sse"
4644 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4645 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4647 "cvtsi2sd\t{%1, %0|%0, %1}"
4648 [(set_attr "type" "sseicvt")
4649 (set_attr "mode" "DF")
4650 (set_attr "athlon_decode" "double,direct")
4651 (set_attr "fp_int_src" "true")])
4653 (define_expand "floatdidf2"
4654 [(set (match_operand:DF 0 "register_operand" "")
4655 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4656 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4659 (define_insn "*floatdidf2_i387_only"
4660 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4661 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4662 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4666 [(set_attr "type" "fmov,multi")
4667 (set_attr "mode" "DF")
4668 (set_attr "fp_int_src" "true")])
4670 (define_insn "*floatdidf2_i387"
4671 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4672 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4673 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4677 cvtsi2sd{q}\t{%1, %0|%0, %1}
4678 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4679 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4680 (set_attr "mode" "DF")
4681 (set_attr "athlon_decode" "*,*,double,direct")
4682 (set_attr "fp_int_src" "true")])
4684 (define_insn "*floatdidf2_sse"
4685 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4686 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4688 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4689 [(set_attr "type" "sseicvt")
4690 (set_attr "mode" "DF")
4691 (set_attr "athlon_decode" "double,direct")
4692 (set_attr "fp_int_src" "true")])
4694 (define_insn "floathixf2"
4695 [(set (match_operand:XF 0 "register_operand" "=f,f")
4696 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4701 [(set_attr "type" "fmov,multi")
4702 (set_attr "mode" "XF")
4703 (set_attr "fp_int_src" "true")])
4705 (define_insn "floatsixf2"
4706 [(set (match_operand:XF 0 "register_operand" "=f,f")
4707 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4712 [(set_attr "type" "fmov,multi")
4713 (set_attr "mode" "XF")
4714 (set_attr "fp_int_src" "true")])
4716 (define_insn "floatdixf2"
4717 [(set (match_operand:XF 0 "register_operand" "=f,f")
4718 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4723 [(set_attr "type" "fmov,multi")
4724 (set_attr "mode" "XF")
4725 (set_attr "fp_int_src" "true")])
4727 ;; %%% Kill these when reload knows how to do it.
4729 [(set (match_operand 0 "fp_register_operand" "")
4730 (float (match_operand 1 "register_operand" "")))]
4731 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4734 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4735 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4736 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4737 ix86_free_from_memory (GET_MODE (operands[1]));
4741 (define_expand "floatunssisf2"
4742 [(use (match_operand:SF 0 "register_operand" ""))
4743 (use (match_operand:SI 1 "register_operand" ""))]
4744 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
4745 "x86_emit_floatuns (operands); DONE;")
4747 (define_expand "floatunsdisf2"
4748 [(use (match_operand:SF 0 "register_operand" ""))
4749 (use (match_operand:DI 1 "register_operand" ""))]
4750 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
4751 "x86_emit_floatuns (operands); DONE;")
4753 (define_expand "floatunsdidf2"
4754 [(use (match_operand:DF 0 "register_operand" ""))
4755 (use (match_operand:DI 1 "register_operand" ""))]
4756 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
4757 "x86_emit_floatuns (operands); DONE;")
4759 ;; SSE extract/set expanders
4761 (define_expand "vec_setv2df"
4762 [(match_operand:V2DF 0 "register_operand" "")
4763 (match_operand:DF 1 "register_operand" "")
4764 (match_operand 2 "const_int_operand" "")]
4767 switch (INTVAL (operands[2]))
4770 emit_insn (gen_sse2_movsd (operands[0], operands[0],
4771 simplify_gen_subreg (V2DFmode, operands[1],
4776 rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4778 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
4787 (define_expand "vec_extractv2df"
4788 [(match_operand:DF 0 "register_operand" "")
4789 (match_operand:V2DF 1 "register_operand" "")
4790 (match_operand 2 "const_int_operand" "")]
4793 switch (INTVAL (operands[2]))
4796 emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1]));
4800 rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
4802 emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
4811 (define_expand "vec_initv2df"
4812 [(match_operand:V2DF 0 "register_operand" "")
4813 (match_operand 1 "" "")]
4816 ix86_expand_vector_init (operands[0], operands[1]);
4820 (define_expand "vec_setv4sf"
4821 [(match_operand:V4SF 0 "register_operand" "")
4822 (match_operand:SF 1 "register_operand" "")
4823 (match_operand 2 "const_int_operand" "")]
4826 switch (INTVAL (operands[2]))
4829 emit_insn (gen_sse_movss (operands[0], operands[0],
4830 simplify_gen_subreg (V4SFmode, operands[1],
4835 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4836 rtx tmp = gen_reg_rtx (V4SFmode);
4838 emit_move_insn (tmp, operands[0]);
4839 emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
4840 emit_insn (gen_sse_movss (operands[0], operands[0], op1));
4841 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4842 GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
4846 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4847 rtx tmp = gen_reg_rtx (V4SFmode);
4849 emit_move_insn (tmp, operands[0]);
4850 emit_insn (gen_sse_movss (tmp, tmp, op1));
4851 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4852 GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
4857 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4858 rtx tmp = gen_reg_rtx (V4SFmode);
4860 emit_move_insn (tmp, operands[0]);
4861 emit_insn (gen_sse_movss (tmp, tmp, op1));
4862 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4863 GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
4872 (define_expand "vec_extractv4sf"
4873 [(match_operand:SF 0 "register_operand" "")
4874 (match_operand:V4SF 1 "register_operand" "")
4875 (match_operand 2 "const_int_operand" "")]
4878 switch (INTVAL (operands[2]))
4881 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
4885 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4886 rtx tmp = gen_reg_rtx (V4SFmode);
4888 emit_move_insn (tmp, operands[1]);
4889 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4894 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4895 rtx tmp = gen_reg_rtx (V4SFmode);
4897 emit_move_insn (tmp, operands[1]);
4898 emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
4902 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4903 rtx tmp = gen_reg_rtx (V4SFmode);
4905 emit_move_insn (tmp, operands[1]);
4906 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4915 (define_expand "vec_initv4sf"
4916 [(match_operand:V4SF 0 "register_operand" "")
4917 (match_operand 1 "" "")]
4920 ix86_expand_vector_init (operands[0], operands[1]);
4926 ;; %%% splits for addsidi3
4927 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4928 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4929 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4931 (define_expand "adddi3"
4932 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4933 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4934 (match_operand:DI 2 "x86_64_general_operand" "")))
4935 (clobber (reg:CC 17))]
4937 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4939 (define_insn "*adddi3_1"
4940 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4941 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4942 (match_operand:DI 2 "general_operand" "roiF,riF")))
4943 (clobber (reg:CC 17))]
4944 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4948 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4949 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4950 (match_operand:DI 2 "general_operand" "")))
4951 (clobber (reg:CC 17))]
4952 "!TARGET_64BIT && reload_completed"
4953 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4955 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4956 (parallel [(set (match_dup 3)
4957 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4960 (clobber (reg:CC 17))])]
4961 "split_di (operands+0, 1, operands+0, operands+3);
4962 split_di (operands+1, 1, operands+1, operands+4);
4963 split_di (operands+2, 1, operands+2, operands+5);")
4965 (define_insn "adddi3_carry_rex64"
4966 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4967 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4968 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4969 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4970 (clobber (reg:CC 17))]
4971 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4972 "adc{q}\t{%2, %0|%0, %2}"
4973 [(set_attr "type" "alu")
4974 (set_attr "pent_pair" "pu")
4975 (set_attr "mode" "DI")
4976 (set_attr "ppro_uops" "few")])
4978 (define_insn "*adddi3_cc_rex64"
4980 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4981 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4983 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4984 (plus:DI (match_dup 1) (match_dup 2)))]
4985 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4986 "add{q}\t{%2, %0|%0, %2}"
4987 [(set_attr "type" "alu")
4988 (set_attr "mode" "DI")])
4990 (define_insn "addqi3_carry"
4991 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4992 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
4993 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
4994 (match_operand:QI 2 "general_operand" "qi,qm")))
4995 (clobber (reg:CC 17))]
4996 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4997 "adc{b}\t{%2, %0|%0, %2}"
4998 [(set_attr "type" "alu")
4999 (set_attr "pent_pair" "pu")
5000 (set_attr "mode" "QI")
5001 (set_attr "ppro_uops" "few")])
5003 (define_insn "addhi3_carry"
5004 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5005 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5006 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5007 (match_operand:HI 2 "general_operand" "ri,rm")))
5008 (clobber (reg:CC 17))]
5009 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5010 "adc{w}\t{%2, %0|%0, %2}"
5011 [(set_attr "type" "alu")
5012 (set_attr "pent_pair" "pu")
5013 (set_attr "mode" "HI")
5014 (set_attr "ppro_uops" "few")])
5016 (define_insn "addsi3_carry"
5017 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5018 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5019 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5020 (match_operand:SI 2 "general_operand" "ri,rm")))
5021 (clobber (reg:CC 17))]
5022 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5023 "adc{l}\t{%2, %0|%0, %2}"
5024 [(set_attr "type" "alu")
5025 (set_attr "pent_pair" "pu")
5026 (set_attr "mode" "SI")
5027 (set_attr "ppro_uops" "few")])
5029 (define_insn "*addsi3_carry_zext"
5030 [(set (match_operand:DI 0 "register_operand" "=r")
5032 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5033 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5034 (match_operand:SI 2 "general_operand" "rim"))))
5035 (clobber (reg:CC 17))]
5036 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5037 "adc{l}\t{%2, %k0|%k0, %2}"
5038 [(set_attr "type" "alu")
5039 (set_attr "pent_pair" "pu")
5040 (set_attr "mode" "SI")
5041 (set_attr "ppro_uops" "few")])
5043 (define_insn "*addsi3_cc"
5045 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5046 (match_operand:SI 2 "general_operand" "ri,rm")]
5048 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5049 (plus:SI (match_dup 1) (match_dup 2)))]
5050 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5051 "add{l}\t{%2, %0|%0, %2}"
5052 [(set_attr "type" "alu")
5053 (set_attr "mode" "SI")])
5055 (define_insn "addqi3_cc"
5057 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5058 (match_operand:QI 2 "general_operand" "qi,qm")]
5060 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5061 (plus:QI (match_dup 1) (match_dup 2)))]
5062 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5063 "add{b}\t{%2, %0|%0, %2}"
5064 [(set_attr "type" "alu")
5065 (set_attr "mode" "QI")])
5067 (define_expand "addsi3"
5068 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5069 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5070 (match_operand:SI 2 "general_operand" "")))
5071 (clobber (reg:CC 17))])]
5073 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5075 (define_insn "*lea_1"
5076 [(set (match_operand:SI 0 "register_operand" "=r")
5077 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5079 "lea{l}\t{%a1, %0|%0, %a1}"
5080 [(set_attr "type" "lea")
5081 (set_attr "mode" "SI")])
5083 (define_insn "*lea_1_rex64"
5084 [(set (match_operand:SI 0 "register_operand" "=r")
5085 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5087 "lea{l}\t{%a1, %0|%0, %a1}"
5088 [(set_attr "type" "lea")
5089 (set_attr "mode" "SI")])
5091 (define_insn "*lea_1_zext"
5092 [(set (match_operand:DI 0 "register_operand" "=r")
5094 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5096 "lea{l}\t{%a1, %k0|%k0, %a1}"
5097 [(set_attr "type" "lea")
5098 (set_attr "mode" "SI")])
5100 (define_insn "*lea_2_rex64"
5101 [(set (match_operand:DI 0 "register_operand" "=r")
5102 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5104 "lea{q}\t{%a1, %0|%0, %a1}"
5105 [(set_attr "type" "lea")
5106 (set_attr "mode" "DI")])
5108 ;; The lea patterns for non-Pmodes needs to be matched by several
5109 ;; insns converted to real lea by splitters.
5111 (define_insn_and_split "*lea_general_1"
5112 [(set (match_operand 0 "register_operand" "=r")
5113 (plus (plus (match_operand 1 "index_register_operand" "r")
5114 (match_operand 2 "register_operand" "r"))
5115 (match_operand 3 "immediate_operand" "i")))]
5116 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5117 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5118 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5119 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5120 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5121 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5122 || GET_MODE (operands[3]) == VOIDmode)"
5124 "&& reload_completed"
5128 operands[0] = gen_lowpart (SImode, operands[0]);
5129 operands[1] = gen_lowpart (Pmode, operands[1]);
5130 operands[2] = gen_lowpart (Pmode, operands[2]);
5131 operands[3] = gen_lowpart (Pmode, operands[3]);
5132 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5134 if (Pmode != SImode)
5135 pat = gen_rtx_SUBREG (SImode, pat, 0);
5136 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5139 [(set_attr "type" "lea")
5140 (set_attr "mode" "SI")])
5142 (define_insn_and_split "*lea_general_1_zext"
5143 [(set (match_operand:DI 0 "register_operand" "=r")
5145 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5146 (match_operand:SI 2 "register_operand" "r"))
5147 (match_operand:SI 3 "immediate_operand" "i"))))]
5150 "&& reload_completed"
5152 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5154 (match_dup 3)) 0)))]
5156 operands[1] = gen_lowpart (Pmode, operands[1]);
5157 operands[2] = gen_lowpart (Pmode, operands[2]);
5158 operands[3] = gen_lowpart (Pmode, operands[3]);
5160 [(set_attr "type" "lea")
5161 (set_attr "mode" "SI")])
5163 (define_insn_and_split "*lea_general_2"
5164 [(set (match_operand 0 "register_operand" "=r")
5165 (plus (mult (match_operand 1 "index_register_operand" "r")
5166 (match_operand 2 "const248_operand" "i"))
5167 (match_operand 3 "nonmemory_operand" "ri")))]
5168 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5169 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5170 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5171 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5172 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5173 || GET_MODE (operands[3]) == VOIDmode)"
5175 "&& reload_completed"
5179 operands[0] = gen_lowpart (SImode, operands[0]);
5180 operands[1] = gen_lowpart (Pmode, operands[1]);
5181 operands[3] = gen_lowpart (Pmode, operands[3]);
5182 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5184 if (Pmode != SImode)
5185 pat = gen_rtx_SUBREG (SImode, pat, 0);
5186 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5189 [(set_attr "type" "lea")
5190 (set_attr "mode" "SI")])
5192 (define_insn_and_split "*lea_general_2_zext"
5193 [(set (match_operand:DI 0 "register_operand" "=r")
5195 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5196 (match_operand:SI 2 "const248_operand" "n"))
5197 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5200 "&& reload_completed"
5202 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5204 (match_dup 3)) 0)))]
5206 operands[1] = gen_lowpart (Pmode, operands[1]);
5207 operands[3] = gen_lowpart (Pmode, operands[3]);
5209 [(set_attr "type" "lea")
5210 (set_attr "mode" "SI")])
5212 (define_insn_and_split "*lea_general_3"
5213 [(set (match_operand 0 "register_operand" "=r")
5214 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5215 (match_operand 2 "const248_operand" "i"))
5216 (match_operand 3 "register_operand" "r"))
5217 (match_operand 4 "immediate_operand" "i")))]
5218 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5219 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5220 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5221 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5222 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5224 "&& reload_completed"
5228 operands[0] = gen_lowpart (SImode, operands[0]);
5229 operands[1] = gen_lowpart (Pmode, operands[1]);
5230 operands[3] = gen_lowpart (Pmode, operands[3]);
5231 operands[4] = gen_lowpart (Pmode, operands[4]);
5232 pat = gen_rtx_PLUS (Pmode,
5233 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5237 if (Pmode != SImode)
5238 pat = gen_rtx_SUBREG (SImode, pat, 0);
5239 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5242 [(set_attr "type" "lea")
5243 (set_attr "mode" "SI")])
5245 (define_insn_and_split "*lea_general_3_zext"
5246 [(set (match_operand:DI 0 "register_operand" "=r")
5248 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5249 (match_operand:SI 2 "const248_operand" "n"))
5250 (match_operand:SI 3 "register_operand" "r"))
5251 (match_operand:SI 4 "immediate_operand" "i"))))]
5254 "&& reload_completed"
5256 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5259 (match_dup 4)) 0)))]
5261 operands[1] = gen_lowpart (Pmode, operands[1]);
5262 operands[3] = gen_lowpart (Pmode, operands[3]);
5263 operands[4] = gen_lowpart (Pmode, operands[4]);
5265 [(set_attr "type" "lea")
5266 (set_attr "mode" "SI")])
5268 (define_insn "*adddi_1_rex64"
5269 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5270 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5271 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5272 (clobber (reg:CC 17))]
5273 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5275 switch (get_attr_type (insn))
5278 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5279 return "lea{q}\t{%a2, %0|%0, %a2}";
5282 if (! rtx_equal_p (operands[0], operands[1]))
5284 if (operands[2] == const1_rtx)
5285 return "inc{q}\t%0";
5286 else if (operands[2] == constm1_rtx)
5287 return "dec{q}\t%0";
5292 if (! rtx_equal_p (operands[0], operands[1]))
5295 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5296 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5297 if (GET_CODE (operands[2]) == CONST_INT
5298 /* Avoid overflows. */
5299 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5300 && (INTVAL (operands[2]) == 128
5301 || (INTVAL (operands[2]) < 0
5302 && INTVAL (operands[2]) != -128)))
5304 operands[2] = GEN_INT (-INTVAL (operands[2]));
5305 return "sub{q}\t{%2, %0|%0, %2}";
5307 return "add{q}\t{%2, %0|%0, %2}";
5311 (cond [(eq_attr "alternative" "2")
5312 (const_string "lea")
5313 ; Current assemblers are broken and do not allow @GOTOFF in
5314 ; ought but a memory context.
5315 (match_operand:DI 2 "pic_symbolic_operand" "")
5316 (const_string "lea")
5317 (match_operand:DI 2 "incdec_operand" "")
5318 (const_string "incdec")
5320 (const_string "alu")))
5321 (set_attr "mode" "DI")])
5323 ;; Convert lea to the lea pattern to avoid flags dependency.
5325 [(set (match_operand:DI 0 "register_operand" "")
5326 (plus:DI (match_operand:DI 1 "register_operand" "")
5327 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5328 (clobber (reg:CC 17))]
5329 "TARGET_64BIT && reload_completed
5330 && true_regnum (operands[0]) != true_regnum (operands[1])"
5332 (plus:DI (match_dup 1)
5336 (define_insn "*adddi_2_rex64"
5339 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5340 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5342 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5343 (plus:DI (match_dup 1) (match_dup 2)))]
5344 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5345 && ix86_binary_operator_ok (PLUS, DImode, operands)
5346 /* Current assemblers are broken and do not allow @GOTOFF in
5347 ought but a memory context. */
5348 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5350 switch (get_attr_type (insn))
5353 if (! rtx_equal_p (operands[0], operands[1]))
5355 if (operands[2] == const1_rtx)
5356 return "inc{q}\t%0";
5357 else if (operands[2] == constm1_rtx)
5358 return "dec{q}\t%0";
5363 if (! rtx_equal_p (operands[0], operands[1]))
5365 /* ???? We ought to handle there the 32bit case too
5366 - do we need new constraint? */
5367 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5368 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5369 if (GET_CODE (operands[2]) == CONST_INT
5370 /* Avoid overflows. */
5371 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5372 && (INTVAL (operands[2]) == 128
5373 || (INTVAL (operands[2]) < 0
5374 && INTVAL (operands[2]) != -128)))
5376 operands[2] = GEN_INT (-INTVAL (operands[2]));
5377 return "sub{q}\t{%2, %0|%0, %2}";
5379 return "add{q}\t{%2, %0|%0, %2}";
5383 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5384 (const_string "incdec")
5385 (const_string "alu")))
5386 (set_attr "mode" "DI")])
5388 (define_insn "*adddi_3_rex64"
5390 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5391 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5392 (clobber (match_scratch:DI 0 "=r"))]
5394 && ix86_match_ccmode (insn, CCZmode)
5395 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5396 /* Current assemblers are broken and do not allow @GOTOFF in
5397 ought but a memory context. */
5398 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5400 switch (get_attr_type (insn))
5403 if (! rtx_equal_p (operands[0], operands[1]))
5405 if (operands[2] == const1_rtx)
5406 return "inc{q}\t%0";
5407 else if (operands[2] == constm1_rtx)
5408 return "dec{q}\t%0";
5413 if (! rtx_equal_p (operands[0], operands[1]))
5415 /* ???? We ought to handle there the 32bit case too
5416 - do we need new constraint? */
5417 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5418 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5419 if (GET_CODE (operands[2]) == CONST_INT
5420 /* Avoid overflows. */
5421 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5422 && (INTVAL (operands[2]) == 128
5423 || (INTVAL (operands[2]) < 0
5424 && INTVAL (operands[2]) != -128)))
5426 operands[2] = GEN_INT (-INTVAL (operands[2]));
5427 return "sub{q}\t{%2, %0|%0, %2}";
5429 return "add{q}\t{%2, %0|%0, %2}";
5433 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5434 (const_string "incdec")
5435 (const_string "alu")))
5436 (set_attr "mode" "DI")])
5438 ; For comparisons against 1, -1 and 128, we may generate better code
5439 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5440 ; is matched then. We can't accept general immediate, because for
5441 ; case of overflows, the result is messed up.
5442 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5444 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5445 ; only for comparisons not depending on it.
5446 (define_insn "*adddi_4_rex64"
5448 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5449 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5450 (clobber (match_scratch:DI 0 "=rm"))]
5452 && ix86_match_ccmode (insn, CCGCmode)"
5454 switch (get_attr_type (insn))
5457 if (operands[2] == constm1_rtx)
5458 return "inc{q}\t%0";
5459 else if (operands[2] == const1_rtx)
5460 return "dec{q}\t%0";
5465 if (! rtx_equal_p (operands[0], operands[1]))
5467 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5468 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5469 if ((INTVAL (operands[2]) == -128
5470 || (INTVAL (operands[2]) > 0
5471 && INTVAL (operands[2]) != 128))
5472 /* Avoid overflows. */
5473 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5474 return "sub{q}\t{%2, %0|%0, %2}";
5475 operands[2] = GEN_INT (-INTVAL (operands[2]));
5476 return "add{q}\t{%2, %0|%0, %2}";
5480 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5481 (const_string "incdec")
5482 (const_string "alu")))
5483 (set_attr "mode" "DI")])
5485 (define_insn "*adddi_5_rex64"
5488 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5489 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5491 (clobber (match_scratch:DI 0 "=r"))]
5493 && ix86_match_ccmode (insn, CCGOCmode)
5494 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5495 /* Current assemblers are broken and do not allow @GOTOFF in
5496 ought but a memory context. */
5497 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5499 switch (get_attr_type (insn))
5502 if (! rtx_equal_p (operands[0], operands[1]))
5504 if (operands[2] == const1_rtx)
5505 return "inc{q}\t%0";
5506 else if (operands[2] == constm1_rtx)
5507 return "dec{q}\t%0";
5512 if (! rtx_equal_p (operands[0], operands[1]))
5514 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5515 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5516 if (GET_CODE (operands[2]) == CONST_INT
5517 /* Avoid overflows. */
5518 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5519 && (INTVAL (operands[2]) == 128
5520 || (INTVAL (operands[2]) < 0
5521 && INTVAL (operands[2]) != -128)))
5523 operands[2] = GEN_INT (-INTVAL (operands[2]));
5524 return "sub{q}\t{%2, %0|%0, %2}";
5526 return "add{q}\t{%2, %0|%0, %2}";
5530 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5531 (const_string "incdec")
5532 (const_string "alu")))
5533 (set_attr "mode" "DI")])
5536 (define_insn "*addsi_1"
5537 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5538 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5539 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5540 (clobber (reg:CC 17))]
5541 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5543 switch (get_attr_type (insn))
5546 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5547 return "lea{l}\t{%a2, %0|%0, %a2}";
5550 if (! rtx_equal_p (operands[0], operands[1]))
5552 if (operands[2] == const1_rtx)
5553 return "inc{l}\t%0";
5554 else if (operands[2] == constm1_rtx)
5555 return "dec{l}\t%0";
5560 if (! rtx_equal_p (operands[0], operands[1]))
5563 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5564 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5565 if (GET_CODE (operands[2]) == CONST_INT
5566 && (INTVAL (operands[2]) == 128
5567 || (INTVAL (operands[2]) < 0
5568 && INTVAL (operands[2]) != -128)))
5570 operands[2] = GEN_INT (-INTVAL (operands[2]));
5571 return "sub{l}\t{%2, %0|%0, %2}";
5573 return "add{l}\t{%2, %0|%0, %2}";
5577 (cond [(eq_attr "alternative" "2")
5578 (const_string "lea")
5579 ; Current assemblers are broken and do not allow @GOTOFF in
5580 ; ought but a memory context.
5581 (match_operand:SI 2 "pic_symbolic_operand" "")
5582 (const_string "lea")
5583 (match_operand:SI 2 "incdec_operand" "")
5584 (const_string "incdec")
5586 (const_string "alu")))
5587 (set_attr "mode" "SI")])
5589 ;; Convert lea to the lea pattern to avoid flags dependency.
5591 [(set (match_operand 0 "register_operand" "")
5592 (plus (match_operand 1 "register_operand" "")
5593 (match_operand 2 "nonmemory_operand" "")))
5594 (clobber (reg:CC 17))]
5596 && true_regnum (operands[0]) != true_regnum (operands[1])"
5600 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5601 may confuse gen_lowpart. */
5602 if (GET_MODE (operands[0]) != Pmode)
5604 operands[1] = gen_lowpart (Pmode, operands[1]);
5605 operands[2] = gen_lowpart (Pmode, operands[2]);
5607 operands[0] = gen_lowpart (SImode, operands[0]);
5608 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5609 if (Pmode != SImode)
5610 pat = gen_rtx_SUBREG (SImode, pat, 0);
5611 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5615 ;; It may seem that nonimmediate operand is proper one for operand 1.
5616 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5617 ;; we take care in ix86_binary_operator_ok to not allow two memory
5618 ;; operands so proper swapping will be done in reload. This allow
5619 ;; patterns constructed from addsi_1 to match.
5620 (define_insn "addsi_1_zext"
5621 [(set (match_operand:DI 0 "register_operand" "=r,r")
5623 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5624 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5625 (clobber (reg:CC 17))]
5626 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5628 switch (get_attr_type (insn))
5631 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5632 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5635 if (operands[2] == const1_rtx)
5636 return "inc{l}\t%k0";
5637 else if (operands[2] == constm1_rtx)
5638 return "dec{l}\t%k0";
5643 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5644 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5645 if (GET_CODE (operands[2]) == CONST_INT
5646 && (INTVAL (operands[2]) == 128
5647 || (INTVAL (operands[2]) < 0
5648 && INTVAL (operands[2]) != -128)))
5650 operands[2] = GEN_INT (-INTVAL (operands[2]));
5651 return "sub{l}\t{%2, %k0|%k0, %2}";
5653 return "add{l}\t{%2, %k0|%k0, %2}";
5657 (cond [(eq_attr "alternative" "1")
5658 (const_string "lea")
5659 ; Current assemblers are broken and do not allow @GOTOFF in
5660 ; ought but a memory context.
5661 (match_operand:SI 2 "pic_symbolic_operand" "")
5662 (const_string "lea")
5663 (match_operand:SI 2 "incdec_operand" "")
5664 (const_string "incdec")
5666 (const_string "alu")))
5667 (set_attr "mode" "SI")])
5669 ;; Convert lea to the lea pattern to avoid flags dependency.
5671 [(set (match_operand:DI 0 "register_operand" "")
5673 (plus:SI (match_operand:SI 1 "register_operand" "")
5674 (match_operand:SI 2 "nonmemory_operand" ""))))
5675 (clobber (reg:CC 17))]
5676 "TARGET_64BIT && reload_completed
5677 && true_regnum (operands[0]) != true_regnum (operands[1])"
5679 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5681 operands[1] = gen_lowpart (Pmode, operands[1]);
5682 operands[2] = gen_lowpart (Pmode, operands[2]);
5685 (define_insn "*addsi_2"
5688 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5689 (match_operand:SI 2 "general_operand" "rmni,rni"))
5691 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5692 (plus:SI (match_dup 1) (match_dup 2)))]
5693 "ix86_match_ccmode (insn, CCGOCmode)
5694 && ix86_binary_operator_ok (PLUS, SImode, operands)
5695 /* Current assemblers are broken and do not allow @GOTOFF in
5696 ought but a memory context. */
5697 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5699 switch (get_attr_type (insn))
5702 if (! rtx_equal_p (operands[0], operands[1]))
5704 if (operands[2] == const1_rtx)
5705 return "inc{l}\t%0";
5706 else if (operands[2] == constm1_rtx)
5707 return "dec{l}\t%0";
5712 if (! rtx_equal_p (operands[0], operands[1]))
5714 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5715 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5716 if (GET_CODE (operands[2]) == CONST_INT
5717 && (INTVAL (operands[2]) == 128
5718 || (INTVAL (operands[2]) < 0
5719 && INTVAL (operands[2]) != -128)))
5721 operands[2] = GEN_INT (-INTVAL (operands[2]));
5722 return "sub{l}\t{%2, %0|%0, %2}";
5724 return "add{l}\t{%2, %0|%0, %2}";
5728 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5729 (const_string "incdec")
5730 (const_string "alu")))
5731 (set_attr "mode" "SI")])
5733 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5734 (define_insn "*addsi_2_zext"
5737 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5738 (match_operand:SI 2 "general_operand" "rmni"))
5740 (set (match_operand:DI 0 "register_operand" "=r")
5741 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5742 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5743 && ix86_binary_operator_ok (PLUS, SImode, operands)
5744 /* Current assemblers are broken and do not allow @GOTOFF in
5745 ought but a memory context. */
5746 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5748 switch (get_attr_type (insn))
5751 if (operands[2] == const1_rtx)
5752 return "inc{l}\t%k0";
5753 else if (operands[2] == constm1_rtx)
5754 return "dec{l}\t%k0";
5759 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5760 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5761 if (GET_CODE (operands[2]) == CONST_INT
5762 && (INTVAL (operands[2]) == 128
5763 || (INTVAL (operands[2]) < 0
5764 && INTVAL (operands[2]) != -128)))
5766 operands[2] = GEN_INT (-INTVAL (operands[2]));
5767 return "sub{l}\t{%2, %k0|%k0, %2}";
5769 return "add{l}\t{%2, %k0|%k0, %2}";
5773 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5774 (const_string "incdec")
5775 (const_string "alu")))
5776 (set_attr "mode" "SI")])
5778 (define_insn "*addsi_3"
5780 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5781 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5782 (clobber (match_scratch:SI 0 "=r"))]
5783 "ix86_match_ccmode (insn, CCZmode)
5784 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5785 /* Current assemblers are broken and do not allow @GOTOFF in
5786 ought but a memory context. */
5787 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5789 switch (get_attr_type (insn))
5792 if (! rtx_equal_p (operands[0], operands[1]))
5794 if (operands[2] == const1_rtx)
5795 return "inc{l}\t%0";
5796 else if (operands[2] == constm1_rtx)
5797 return "dec{l}\t%0";
5802 if (! rtx_equal_p (operands[0], operands[1]))
5804 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5805 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5806 if (GET_CODE (operands[2]) == CONST_INT
5807 && (INTVAL (operands[2]) == 128
5808 || (INTVAL (operands[2]) < 0
5809 && INTVAL (operands[2]) != -128)))
5811 operands[2] = GEN_INT (-INTVAL (operands[2]));
5812 return "sub{l}\t{%2, %0|%0, %2}";
5814 return "add{l}\t{%2, %0|%0, %2}";
5818 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5819 (const_string "incdec")
5820 (const_string "alu")))
5821 (set_attr "mode" "SI")])
5823 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5824 (define_insn "*addsi_3_zext"
5826 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5827 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5828 (set (match_operand:DI 0 "register_operand" "=r")
5829 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5830 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5831 && ix86_binary_operator_ok (PLUS, SImode, operands)
5832 /* Current assemblers are broken and do not allow @GOTOFF in
5833 ought but a memory context. */
5834 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5836 switch (get_attr_type (insn))
5839 if (operands[2] == const1_rtx)
5840 return "inc{l}\t%k0";
5841 else if (operands[2] == constm1_rtx)
5842 return "dec{l}\t%k0";
5847 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5848 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5849 if (GET_CODE (operands[2]) == CONST_INT
5850 && (INTVAL (operands[2]) == 128
5851 || (INTVAL (operands[2]) < 0
5852 && INTVAL (operands[2]) != -128)))
5854 operands[2] = GEN_INT (-INTVAL (operands[2]));
5855 return "sub{l}\t{%2, %k0|%k0, %2}";
5857 return "add{l}\t{%2, %k0|%k0, %2}";
5861 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5862 (const_string "incdec")
5863 (const_string "alu")))
5864 (set_attr "mode" "SI")])
5866 ; For comparisons against 1, -1 and 128, we may generate better code
5867 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5868 ; is matched then. We can't accept general immediate, because for
5869 ; case of overflows, the result is messed up.
5870 ; This pattern also don't hold of 0x80000000, since the value overflows
5872 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5873 ; only for comparisons not depending on it.
5874 (define_insn "*addsi_4"
5876 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5877 (match_operand:SI 2 "const_int_operand" "n")))
5878 (clobber (match_scratch:SI 0 "=rm"))]
5879 "ix86_match_ccmode (insn, CCGCmode)
5880 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5882 switch (get_attr_type (insn))
5885 if (operands[2] == constm1_rtx)
5886 return "inc{l}\t%0";
5887 else if (operands[2] == const1_rtx)
5888 return "dec{l}\t%0";
5893 if (! rtx_equal_p (operands[0], operands[1]))
5895 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5896 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5897 if ((INTVAL (operands[2]) == -128
5898 || (INTVAL (operands[2]) > 0
5899 && INTVAL (operands[2]) != 128)))
5900 return "sub{l}\t{%2, %0|%0, %2}";
5901 operands[2] = GEN_INT (-INTVAL (operands[2]));
5902 return "add{l}\t{%2, %0|%0, %2}";
5906 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5907 (const_string "incdec")
5908 (const_string "alu")))
5909 (set_attr "mode" "SI")])
5911 (define_insn "*addsi_5"
5914 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5915 (match_operand:SI 2 "general_operand" "rmni"))
5917 (clobber (match_scratch:SI 0 "=r"))]
5918 "ix86_match_ccmode (insn, CCGOCmode)
5919 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5920 /* Current assemblers are broken and do not allow @GOTOFF in
5921 ought but a memory context. */
5922 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5924 switch (get_attr_type (insn))
5927 if (! rtx_equal_p (operands[0], operands[1]))
5929 if (operands[2] == const1_rtx)
5930 return "inc{l}\t%0";
5931 else if (operands[2] == constm1_rtx)
5932 return "dec{l}\t%0";
5937 if (! rtx_equal_p (operands[0], operands[1]))
5939 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5940 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5941 if (GET_CODE (operands[2]) == CONST_INT
5942 && (INTVAL (operands[2]) == 128
5943 || (INTVAL (operands[2]) < 0
5944 && INTVAL (operands[2]) != -128)))
5946 operands[2] = GEN_INT (-INTVAL (operands[2]));
5947 return "sub{l}\t{%2, %0|%0, %2}";
5949 return "add{l}\t{%2, %0|%0, %2}";
5953 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5954 (const_string "incdec")
5955 (const_string "alu")))
5956 (set_attr "mode" "SI")])
5958 (define_expand "addhi3"
5959 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5960 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5961 (match_operand:HI 2 "general_operand" "")))
5962 (clobber (reg:CC 17))])]
5963 "TARGET_HIMODE_MATH"
5964 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5966 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5967 ;; type optimizations enabled by define-splits. This is not important
5968 ;; for PII, and in fact harmful because of partial register stalls.
5970 (define_insn "*addhi_1_lea"
5971 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5972 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5973 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5974 (clobber (reg:CC 17))]
5975 "!TARGET_PARTIAL_REG_STALL
5976 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5978 switch (get_attr_type (insn))
5983 if (operands[2] == const1_rtx)
5984 return "inc{w}\t%0";
5985 else if (operands[2] == constm1_rtx)
5986 return "dec{w}\t%0";
5990 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5991 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5992 if (GET_CODE (operands[2]) == CONST_INT
5993 && (INTVAL (operands[2]) == 128
5994 || (INTVAL (operands[2]) < 0
5995 && INTVAL (operands[2]) != -128)))
5997 operands[2] = GEN_INT (-INTVAL (operands[2]));
5998 return "sub{w}\t{%2, %0|%0, %2}";
6000 return "add{w}\t{%2, %0|%0, %2}";
6004 (if_then_else (eq_attr "alternative" "2")
6005 (const_string "lea")
6006 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6007 (const_string "incdec")
6008 (const_string "alu"))))
6009 (set_attr "mode" "HI,HI,SI")])
6011 (define_insn "*addhi_1"
6012 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6013 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6014 (match_operand:HI 2 "general_operand" "ri,rm")))
6015 (clobber (reg:CC 17))]
6016 "TARGET_PARTIAL_REG_STALL
6017 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6019 switch (get_attr_type (insn))
6022 if (operands[2] == const1_rtx)
6023 return "inc{w}\t%0";
6024 else if (operands[2] == constm1_rtx)
6025 return "dec{w}\t%0";
6029 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6030 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6031 if (GET_CODE (operands[2]) == CONST_INT
6032 && (INTVAL (operands[2]) == 128
6033 || (INTVAL (operands[2]) < 0
6034 && INTVAL (operands[2]) != -128)))
6036 operands[2] = GEN_INT (-INTVAL (operands[2]));
6037 return "sub{w}\t{%2, %0|%0, %2}";
6039 return "add{w}\t{%2, %0|%0, %2}";
6043 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6044 (const_string "incdec")
6045 (const_string "alu")))
6046 (set_attr "mode" "HI")])
6048 (define_insn "*addhi_2"
6051 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6052 (match_operand:HI 2 "general_operand" "rmni,rni"))
6054 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6055 (plus:HI (match_dup 1) (match_dup 2)))]
6056 "ix86_match_ccmode (insn, CCGOCmode)
6057 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6059 switch (get_attr_type (insn))
6062 if (operands[2] == const1_rtx)
6063 return "inc{w}\t%0";
6064 else if (operands[2] == constm1_rtx)
6065 return "dec{w}\t%0";
6069 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6070 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6071 if (GET_CODE (operands[2]) == CONST_INT
6072 && (INTVAL (operands[2]) == 128
6073 || (INTVAL (operands[2]) < 0
6074 && INTVAL (operands[2]) != -128)))
6076 operands[2] = GEN_INT (-INTVAL (operands[2]));
6077 return "sub{w}\t{%2, %0|%0, %2}";
6079 return "add{w}\t{%2, %0|%0, %2}";
6083 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6084 (const_string "incdec")
6085 (const_string "alu")))
6086 (set_attr "mode" "HI")])
6088 (define_insn "*addhi_3"
6090 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6091 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6092 (clobber (match_scratch:HI 0 "=r"))]
6093 "ix86_match_ccmode (insn, CCZmode)
6094 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6096 switch (get_attr_type (insn))
6099 if (operands[2] == const1_rtx)
6100 return "inc{w}\t%0";
6101 else if (operands[2] == constm1_rtx)
6102 return "dec{w}\t%0";
6106 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6107 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6108 if (GET_CODE (operands[2]) == CONST_INT
6109 && (INTVAL (operands[2]) == 128
6110 || (INTVAL (operands[2]) < 0
6111 && INTVAL (operands[2]) != -128)))
6113 operands[2] = GEN_INT (-INTVAL (operands[2]));
6114 return "sub{w}\t{%2, %0|%0, %2}";
6116 return "add{w}\t{%2, %0|%0, %2}";
6120 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6121 (const_string "incdec")
6122 (const_string "alu")))
6123 (set_attr "mode" "HI")])
6125 ; See comments above addsi_3_imm for details.
6126 (define_insn "*addhi_4"
6128 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6129 (match_operand:HI 2 "const_int_operand" "n")))
6130 (clobber (match_scratch:HI 0 "=rm"))]
6131 "ix86_match_ccmode (insn, CCGCmode)
6132 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6134 switch (get_attr_type (insn))
6137 if (operands[2] == constm1_rtx)
6138 return "inc{w}\t%0";
6139 else if (operands[2] == const1_rtx)
6140 return "dec{w}\t%0";
6145 if (! rtx_equal_p (operands[0], operands[1]))
6147 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6148 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6149 if ((INTVAL (operands[2]) == -128
6150 || (INTVAL (operands[2]) > 0
6151 && INTVAL (operands[2]) != 128)))
6152 return "sub{w}\t{%2, %0|%0, %2}";
6153 operands[2] = GEN_INT (-INTVAL (operands[2]));
6154 return "add{w}\t{%2, %0|%0, %2}";
6158 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6159 (const_string "incdec")
6160 (const_string "alu")))
6161 (set_attr "mode" "SI")])
6164 (define_insn "*addhi_5"
6167 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6168 (match_operand:HI 2 "general_operand" "rmni"))
6170 (clobber (match_scratch:HI 0 "=r"))]
6171 "ix86_match_ccmode (insn, CCGOCmode)
6172 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6174 switch (get_attr_type (insn))
6177 if (operands[2] == const1_rtx)
6178 return "inc{w}\t%0";
6179 else if (operands[2] == constm1_rtx)
6180 return "dec{w}\t%0";
6184 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6185 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6186 if (GET_CODE (operands[2]) == CONST_INT
6187 && (INTVAL (operands[2]) == 128
6188 || (INTVAL (operands[2]) < 0
6189 && INTVAL (operands[2]) != -128)))
6191 operands[2] = GEN_INT (-INTVAL (operands[2]));
6192 return "sub{w}\t{%2, %0|%0, %2}";
6194 return "add{w}\t{%2, %0|%0, %2}";
6198 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6199 (const_string "incdec")
6200 (const_string "alu")))
6201 (set_attr "mode" "HI")])
6203 (define_expand "addqi3"
6204 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6205 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6206 (match_operand:QI 2 "general_operand" "")))
6207 (clobber (reg:CC 17))])]
6208 "TARGET_QIMODE_MATH"
6209 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6211 ;; %%% Potential partial reg stall on alternative 2. What to do?
6212 (define_insn "*addqi_1_lea"
6213 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6214 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6215 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6216 (clobber (reg:CC 17))]
6217 "!TARGET_PARTIAL_REG_STALL
6218 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6220 int widen = (which_alternative == 2);
6221 switch (get_attr_type (insn))
6226 if (operands[2] == const1_rtx)
6227 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6228 else if (operands[2] == constm1_rtx)
6229 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6233 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6234 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6235 if (GET_CODE (operands[2]) == CONST_INT
6236 && (INTVAL (operands[2]) == 128
6237 || (INTVAL (operands[2]) < 0
6238 && INTVAL (operands[2]) != -128)))
6240 operands[2] = GEN_INT (-INTVAL (operands[2]));
6242 return "sub{l}\t{%2, %k0|%k0, %2}";
6244 return "sub{b}\t{%2, %0|%0, %2}";
6247 return "add{l}\t{%k2, %k0|%k0, %k2}";
6249 return "add{b}\t{%2, %0|%0, %2}";
6253 (if_then_else (eq_attr "alternative" "3")
6254 (const_string "lea")
6255 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6256 (const_string "incdec")
6257 (const_string "alu"))))
6258 (set_attr "mode" "QI,QI,SI,SI")])
6260 (define_insn "*addqi_1"
6261 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6262 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6263 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6264 (clobber (reg:CC 17))]
6265 "TARGET_PARTIAL_REG_STALL
6266 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6268 int widen = (which_alternative == 2);
6269 switch (get_attr_type (insn))
6272 if (operands[2] == const1_rtx)
6273 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6274 else if (operands[2] == constm1_rtx)
6275 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6279 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6280 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6281 if (GET_CODE (operands[2]) == CONST_INT
6282 && (INTVAL (operands[2]) == 128
6283 || (INTVAL (operands[2]) < 0
6284 && INTVAL (operands[2]) != -128)))
6286 operands[2] = GEN_INT (-INTVAL (operands[2]));
6288 return "sub{l}\t{%2, %k0|%k0, %2}";
6290 return "sub{b}\t{%2, %0|%0, %2}";
6293 return "add{l}\t{%k2, %k0|%k0, %k2}";
6295 return "add{b}\t{%2, %0|%0, %2}";
6299 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6300 (const_string "incdec")
6301 (const_string "alu")))
6302 (set_attr "mode" "QI,QI,SI")])
6304 (define_insn "*addqi_1_slp"
6305 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6306 (plus:QI (match_dup 0)
6307 (match_operand:QI 1 "general_operand" "qn,qnm")))
6308 (clobber (reg:CC 17))]
6309 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6310 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6312 switch (get_attr_type (insn))
6315 if (operands[1] == const1_rtx)
6316 return "inc{b}\t%0";
6317 else if (operands[1] == constm1_rtx)
6318 return "dec{b}\t%0";
6322 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6323 if (GET_CODE (operands[1]) == CONST_INT
6324 && INTVAL (operands[1]) < 0)
6326 operands[1] = GEN_INT (-INTVAL (operands[1]));
6327 return "sub{b}\t{%1, %0|%0, %1}";
6329 return "add{b}\t{%1, %0|%0, %1}";
6333 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6334 (const_string "incdec")
6335 (const_string "alu1")))
6336 (set_attr "mode" "QI")])
6338 (define_insn "*addqi_2"
6341 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6342 (match_operand:QI 2 "general_operand" "qmni,qni"))
6344 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6345 (plus:QI (match_dup 1) (match_dup 2)))]
6346 "ix86_match_ccmode (insn, CCGOCmode)
6347 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6349 switch (get_attr_type (insn))
6352 if (operands[2] == const1_rtx)
6353 return "inc{b}\t%0";
6354 else if (operands[2] == constm1_rtx
6355 || (GET_CODE (operands[2]) == CONST_INT
6356 && INTVAL (operands[2]) == 255))
6357 return "dec{b}\t%0";
6361 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6362 if (GET_CODE (operands[2]) == CONST_INT
6363 && INTVAL (operands[2]) < 0)
6365 operands[2] = GEN_INT (-INTVAL (operands[2]));
6366 return "sub{b}\t{%2, %0|%0, %2}";
6368 return "add{b}\t{%2, %0|%0, %2}";
6372 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6373 (const_string "incdec")
6374 (const_string "alu")))
6375 (set_attr "mode" "QI")])
6377 (define_insn "*addqi_3"
6379 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6380 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6381 (clobber (match_scratch:QI 0 "=q"))]
6382 "ix86_match_ccmode (insn, CCZmode)
6383 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6385 switch (get_attr_type (insn))
6388 if (operands[2] == const1_rtx)
6389 return "inc{b}\t%0";
6390 else if (operands[2] == constm1_rtx
6391 || (GET_CODE (operands[2]) == CONST_INT
6392 && INTVAL (operands[2]) == 255))
6393 return "dec{b}\t%0";
6397 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6398 if (GET_CODE (operands[2]) == CONST_INT
6399 && INTVAL (operands[2]) < 0)
6401 operands[2] = GEN_INT (-INTVAL (operands[2]));
6402 return "sub{b}\t{%2, %0|%0, %2}";
6404 return "add{b}\t{%2, %0|%0, %2}";
6408 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6409 (const_string "incdec")
6410 (const_string "alu")))
6411 (set_attr "mode" "QI")])
6413 ; See comments above addsi_3_imm for details.
6414 (define_insn "*addqi_4"
6416 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6417 (match_operand:QI 2 "const_int_operand" "n")))
6418 (clobber (match_scratch:QI 0 "=qm"))]
6419 "ix86_match_ccmode (insn, CCGCmode)
6420 && (INTVAL (operands[2]) & 0xff) != 0x80"
6422 switch (get_attr_type (insn))
6425 if (operands[2] == constm1_rtx
6426 || (GET_CODE (operands[2]) == CONST_INT
6427 && INTVAL (operands[2]) == 255))
6428 return "inc{b}\t%0";
6429 else if (operands[2] == const1_rtx)
6430 return "dec{b}\t%0";
6435 if (! rtx_equal_p (operands[0], operands[1]))
6437 if (INTVAL (operands[2]) < 0)
6439 operands[2] = GEN_INT (-INTVAL (operands[2]));
6440 return "add{b}\t{%2, %0|%0, %2}";
6442 return "sub{b}\t{%2, %0|%0, %2}";
6446 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6447 (const_string "incdec")
6448 (const_string "alu")))
6449 (set_attr "mode" "QI")])
6452 (define_insn "*addqi_5"
6455 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6456 (match_operand:QI 2 "general_operand" "qmni"))
6458 (clobber (match_scratch:QI 0 "=q"))]
6459 "ix86_match_ccmode (insn, CCGOCmode)
6460 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6462 switch (get_attr_type (insn))
6465 if (operands[2] == const1_rtx)
6466 return "inc{b}\t%0";
6467 else if (operands[2] == constm1_rtx
6468 || (GET_CODE (operands[2]) == CONST_INT
6469 && INTVAL (operands[2]) == 255))
6470 return "dec{b}\t%0";
6474 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6475 if (GET_CODE (operands[2]) == CONST_INT
6476 && INTVAL (operands[2]) < 0)
6478 operands[2] = GEN_INT (-INTVAL (operands[2]));
6479 return "sub{b}\t{%2, %0|%0, %2}";
6481 return "add{b}\t{%2, %0|%0, %2}";
6485 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6486 (const_string "incdec")
6487 (const_string "alu")))
6488 (set_attr "mode" "QI")])
6491 (define_insn "addqi_ext_1"
6492 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6497 (match_operand 1 "ext_register_operand" "0")
6500 (match_operand:QI 2 "general_operand" "Qmn")))
6501 (clobber (reg:CC 17))]
6504 switch (get_attr_type (insn))
6507 if (operands[2] == const1_rtx)
6508 return "inc{b}\t%h0";
6509 else if (operands[2] == constm1_rtx
6510 || (GET_CODE (operands[2]) == CONST_INT
6511 && INTVAL (operands[2]) == 255))
6512 return "dec{b}\t%h0";
6516 return "add{b}\t{%2, %h0|%h0, %2}";
6520 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6521 (const_string "incdec")
6522 (const_string "alu")))
6523 (set_attr "mode" "QI")])
6525 (define_insn "*addqi_ext_1_rex64"
6526 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6531 (match_operand 1 "ext_register_operand" "0")
6534 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6535 (clobber (reg:CC 17))]
6538 switch (get_attr_type (insn))
6541 if (operands[2] == const1_rtx)
6542 return "inc{b}\t%h0";
6543 else if (operands[2] == constm1_rtx
6544 || (GET_CODE (operands[2]) == CONST_INT
6545 && INTVAL (operands[2]) == 255))
6546 return "dec{b}\t%h0";
6550 return "add{b}\t{%2, %h0|%h0, %2}";
6554 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6555 (const_string "incdec")
6556 (const_string "alu")))
6557 (set_attr "mode" "QI")])
6559 (define_insn "*addqi_ext_2"
6560 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6565 (match_operand 1 "ext_register_operand" "%0")
6569 (match_operand 2 "ext_register_operand" "Q")
6572 (clobber (reg:CC 17))]
6574 "add{b}\t{%h2, %h0|%h0, %h2}"
6575 [(set_attr "type" "alu")
6576 (set_attr "mode" "QI")])
6578 ;; The patterns that match these are at the end of this file.
6580 (define_expand "addxf3"
6581 [(set (match_operand:XF 0 "register_operand" "")
6582 (plus:XF (match_operand:XF 1 "register_operand" "")
6583 (match_operand:XF 2 "register_operand" "")))]
6587 (define_expand "adddf3"
6588 [(set (match_operand:DF 0 "register_operand" "")
6589 (plus:DF (match_operand:DF 1 "register_operand" "")
6590 (match_operand:DF 2 "nonimmediate_operand" "")))]
6591 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6594 (define_expand "addsf3"
6595 [(set (match_operand:SF 0 "register_operand" "")
6596 (plus:SF (match_operand:SF 1 "register_operand" "")
6597 (match_operand:SF 2 "nonimmediate_operand" "")))]
6598 "TARGET_80387 || TARGET_SSE_MATH"
6601 ;; Subtract instructions
6603 ;; %%% splits for subsidi3
6605 (define_expand "subdi3"
6606 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6607 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6608 (match_operand:DI 2 "x86_64_general_operand" "")))
6609 (clobber (reg:CC 17))])]
6611 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6613 (define_insn "*subdi3_1"
6614 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6615 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6616 (match_operand:DI 2 "general_operand" "roiF,riF")))
6617 (clobber (reg:CC 17))]
6618 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6622 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6623 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6624 (match_operand:DI 2 "general_operand" "")))
6625 (clobber (reg:CC 17))]
6626 "!TARGET_64BIT && reload_completed"
6627 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6628 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6629 (parallel [(set (match_dup 3)
6630 (minus:SI (match_dup 4)
6631 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6633 (clobber (reg:CC 17))])]
6634 "split_di (operands+0, 1, operands+0, operands+3);
6635 split_di (operands+1, 1, operands+1, operands+4);
6636 split_di (operands+2, 1, operands+2, operands+5);")
6638 (define_insn "subdi3_carry_rex64"
6639 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6640 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6641 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6642 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6643 (clobber (reg:CC 17))]
6644 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6645 "sbb{q}\t{%2, %0|%0, %2}"
6646 [(set_attr "type" "alu")
6647 (set_attr "pent_pair" "pu")
6648 (set_attr "ppro_uops" "few")
6649 (set_attr "mode" "DI")])
6651 (define_insn "*subdi_1_rex64"
6652 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6653 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6654 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6655 (clobber (reg:CC 17))]
6656 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6657 "sub{q}\t{%2, %0|%0, %2}"
6658 [(set_attr "type" "alu")
6659 (set_attr "mode" "DI")])
6661 (define_insn "*subdi_2_rex64"
6664 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6665 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6667 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6668 (minus:DI (match_dup 1) (match_dup 2)))]
6669 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6670 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6671 "sub{q}\t{%2, %0|%0, %2}"
6672 [(set_attr "type" "alu")
6673 (set_attr "mode" "DI")])
6675 (define_insn "*subdi_3_rex63"
6677 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6678 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6679 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6680 (minus:DI (match_dup 1) (match_dup 2)))]
6681 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6682 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6683 "sub{q}\t{%2, %0|%0, %2}"
6684 [(set_attr "type" "alu")
6685 (set_attr "mode" "DI")])
6687 (define_insn "subqi3_carry"
6688 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6689 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6690 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6691 (match_operand:QI 2 "general_operand" "qi,qm"))))
6692 (clobber (reg:CC 17))]
6693 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6694 "sbb{b}\t{%2, %0|%0, %2}"
6695 [(set_attr "type" "alu")
6696 (set_attr "pent_pair" "pu")
6697 (set_attr "ppro_uops" "few")
6698 (set_attr "mode" "QI")])
6700 (define_insn "subhi3_carry"
6701 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6702 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6703 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6704 (match_operand:HI 2 "general_operand" "ri,rm"))))
6705 (clobber (reg:CC 17))]
6706 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6707 "sbb{w}\t{%2, %0|%0, %2}"
6708 [(set_attr "type" "alu")
6709 (set_attr "pent_pair" "pu")
6710 (set_attr "ppro_uops" "few")
6711 (set_attr "mode" "HI")])
6713 (define_insn "subsi3_carry"
6714 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6715 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6716 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6717 (match_operand:SI 2 "general_operand" "ri,rm"))))
6718 (clobber (reg:CC 17))]
6719 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6720 "sbb{l}\t{%2, %0|%0, %2}"
6721 [(set_attr "type" "alu")
6722 (set_attr "pent_pair" "pu")
6723 (set_attr "ppro_uops" "few")
6724 (set_attr "mode" "SI")])
6726 (define_insn "subsi3_carry_zext"
6727 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6729 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6730 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6731 (match_operand:SI 2 "general_operand" "ri,rm")))))
6732 (clobber (reg:CC 17))]
6733 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6734 "sbb{l}\t{%2, %k0|%k0, %2}"
6735 [(set_attr "type" "alu")
6736 (set_attr "pent_pair" "pu")
6737 (set_attr "ppro_uops" "few")
6738 (set_attr "mode" "SI")])
6740 (define_expand "subsi3"
6741 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6742 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6743 (match_operand:SI 2 "general_operand" "")))
6744 (clobber (reg:CC 17))])]
6746 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6748 (define_insn "*subsi_1"
6749 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6750 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6751 (match_operand:SI 2 "general_operand" "ri,rm")))
6752 (clobber (reg:CC 17))]
6753 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6754 "sub{l}\t{%2, %0|%0, %2}"
6755 [(set_attr "type" "alu")
6756 (set_attr "mode" "SI")])
6758 (define_insn "*subsi_1_zext"
6759 [(set (match_operand:DI 0 "register_operand" "=r")
6761 (minus:SI (match_operand:SI 1 "register_operand" "0")
6762 (match_operand:SI 2 "general_operand" "rim"))))
6763 (clobber (reg:CC 17))]
6764 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6765 "sub{l}\t{%2, %k0|%k0, %2}"
6766 [(set_attr "type" "alu")
6767 (set_attr "mode" "SI")])
6769 (define_insn "*subsi_2"
6772 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6773 (match_operand:SI 2 "general_operand" "ri,rm"))
6775 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6776 (minus:SI (match_dup 1) (match_dup 2)))]
6777 "ix86_match_ccmode (insn, CCGOCmode)
6778 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6779 "sub{l}\t{%2, %0|%0, %2}"
6780 [(set_attr "type" "alu")
6781 (set_attr "mode" "SI")])
6783 (define_insn "*subsi_2_zext"
6786 (minus:SI (match_operand:SI 1 "register_operand" "0")
6787 (match_operand:SI 2 "general_operand" "rim"))
6789 (set (match_operand:DI 0 "register_operand" "=r")
6791 (minus:SI (match_dup 1)
6793 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6794 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6795 "sub{l}\t{%2, %k0|%k0, %2}"
6796 [(set_attr "type" "alu")
6797 (set_attr "mode" "SI")])
6799 (define_insn "*subsi_3"
6801 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6802 (match_operand:SI 2 "general_operand" "ri,rm")))
6803 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6804 (minus:SI (match_dup 1) (match_dup 2)))]
6805 "ix86_match_ccmode (insn, CCmode)
6806 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6807 "sub{l}\t{%2, %0|%0, %2}"
6808 [(set_attr "type" "alu")
6809 (set_attr "mode" "SI")])
6811 (define_insn "*subsi_3_zext"
6813 (compare (match_operand:SI 1 "register_operand" "0")
6814 (match_operand:SI 2 "general_operand" "rim")))
6815 (set (match_operand:DI 0 "register_operand" "=r")
6817 (minus:SI (match_dup 1)
6819 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6820 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6821 "sub{q}\t{%2, %0|%0, %2}"
6822 [(set_attr "type" "alu")
6823 (set_attr "mode" "DI")])
6825 (define_expand "subhi3"
6826 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6827 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6828 (match_operand:HI 2 "general_operand" "")))
6829 (clobber (reg:CC 17))])]
6830 "TARGET_HIMODE_MATH"
6831 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6833 (define_insn "*subhi_1"
6834 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6835 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6836 (match_operand:HI 2 "general_operand" "ri,rm")))
6837 (clobber (reg:CC 17))]
6838 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6839 "sub{w}\t{%2, %0|%0, %2}"
6840 [(set_attr "type" "alu")
6841 (set_attr "mode" "HI")])
6843 (define_insn "*subhi_2"
6846 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6847 (match_operand:HI 2 "general_operand" "ri,rm"))
6849 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6850 (minus:HI (match_dup 1) (match_dup 2)))]
6851 "ix86_match_ccmode (insn, CCGOCmode)
6852 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6853 "sub{w}\t{%2, %0|%0, %2}"
6854 [(set_attr "type" "alu")
6855 (set_attr "mode" "HI")])
6857 (define_insn "*subhi_3"
6859 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6860 (match_operand:HI 2 "general_operand" "ri,rm")))
6861 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6862 (minus:HI (match_dup 1) (match_dup 2)))]
6863 "ix86_match_ccmode (insn, CCmode)
6864 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6865 "sub{w}\t{%2, %0|%0, %2}"
6866 [(set_attr "type" "alu")
6867 (set_attr "mode" "HI")])
6869 (define_expand "subqi3"
6870 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6871 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6872 (match_operand:QI 2 "general_operand" "")))
6873 (clobber (reg:CC 17))])]
6874 "TARGET_QIMODE_MATH"
6875 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6877 (define_insn "*subqi_1"
6878 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6879 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6880 (match_operand:QI 2 "general_operand" "qn,qmn")))
6881 (clobber (reg:CC 17))]
6882 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6883 "sub{b}\t{%2, %0|%0, %2}"
6884 [(set_attr "type" "alu")
6885 (set_attr "mode" "QI")])
6887 (define_insn "*subqi_1_slp"
6888 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6889 (minus:QI (match_dup 0)
6890 (match_operand:QI 1 "general_operand" "qn,qmn")))
6891 (clobber (reg:CC 17))]
6892 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6893 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6894 "sub{b}\t{%1, %0|%0, %1}"
6895 [(set_attr "type" "alu1")
6896 (set_attr "mode" "QI")])
6898 (define_insn "*subqi_2"
6901 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6902 (match_operand:QI 2 "general_operand" "qi,qm"))
6904 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6905 (minus:HI (match_dup 1) (match_dup 2)))]
6906 "ix86_match_ccmode (insn, CCGOCmode)
6907 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6908 "sub{b}\t{%2, %0|%0, %2}"
6909 [(set_attr "type" "alu")
6910 (set_attr "mode" "QI")])
6912 (define_insn "*subqi_3"
6914 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6915 (match_operand:QI 2 "general_operand" "qi,qm")))
6916 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6917 (minus:HI (match_dup 1) (match_dup 2)))]
6918 "ix86_match_ccmode (insn, CCmode)
6919 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6920 "sub{b}\t{%2, %0|%0, %2}"
6921 [(set_attr "type" "alu")
6922 (set_attr "mode" "QI")])
6924 ;; The patterns that match these are at the end of this file.
6926 (define_expand "subxf3"
6927 [(set (match_operand:XF 0 "register_operand" "")
6928 (minus:XF (match_operand:XF 1 "register_operand" "")
6929 (match_operand:XF 2 "register_operand" "")))]
6933 (define_expand "subdf3"
6934 [(set (match_operand:DF 0 "register_operand" "")
6935 (minus:DF (match_operand:DF 1 "register_operand" "")
6936 (match_operand:DF 2 "nonimmediate_operand" "")))]
6937 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6940 (define_expand "subsf3"
6941 [(set (match_operand:SF 0 "register_operand" "")
6942 (minus:SF (match_operand:SF 1 "register_operand" "")
6943 (match_operand:SF 2 "nonimmediate_operand" "")))]
6944 "TARGET_80387 || TARGET_SSE_MATH"
6947 ;; Multiply instructions
6949 (define_expand "muldi3"
6950 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6951 (mult:DI (match_operand:DI 1 "register_operand" "")
6952 (match_operand:DI 2 "x86_64_general_operand" "")))
6953 (clobber (reg:CC 17))])]
6957 (define_insn "*muldi3_1_rex64"
6958 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6959 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6960 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6961 (clobber (reg:CC 17))]
6963 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6965 imul{q}\t{%2, %1, %0|%0, %1, %2}
6966 imul{q}\t{%2, %1, %0|%0, %1, %2}
6967 imul{q}\t{%2, %0|%0, %2}"
6968 [(set_attr "type" "imul")
6969 (set_attr "prefix_0f" "0,0,1")
6970 (set (attr "athlon_decode")
6971 (cond [(eq_attr "cpu" "athlon")
6972 (const_string "vector")
6973 (eq_attr "alternative" "1")
6974 (const_string "vector")
6975 (and (eq_attr "alternative" "2")
6976 (match_operand 1 "memory_operand" ""))
6977 (const_string "vector")]
6978 (const_string "direct")))
6979 (set_attr "mode" "DI")])
6981 (define_expand "mulsi3"
6982 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6983 (mult:SI (match_operand:SI 1 "register_operand" "")
6984 (match_operand:SI 2 "general_operand" "")))
6985 (clobber (reg:CC 17))])]
6989 (define_insn "*mulsi3_1"
6990 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6991 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6992 (match_operand:SI 2 "general_operand" "K,i,mr")))
6993 (clobber (reg:CC 17))]
6994 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6996 imul{l}\t{%2, %1, %0|%0, %1, %2}
6997 imul{l}\t{%2, %1, %0|%0, %1, %2}
6998 imul{l}\t{%2, %0|%0, %2}"
6999 [(set_attr "type" "imul")
7000 (set_attr "prefix_0f" "0,0,1")
7001 (set (attr "athlon_decode")
7002 (cond [(eq_attr "cpu" "athlon")
7003 (const_string "vector")
7004 (eq_attr "alternative" "1")
7005 (const_string "vector")
7006 (and (eq_attr "alternative" "2")
7007 (match_operand 1 "memory_operand" ""))
7008 (const_string "vector")]
7009 (const_string "direct")))
7010 (set_attr "mode" "SI")])
7012 (define_insn "*mulsi3_1_zext"
7013 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7015 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7016 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7017 (clobber (reg:CC 17))]
7019 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7021 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7022 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7023 imul{l}\t{%2, %k0|%k0, %2}"
7024 [(set_attr "type" "imul")
7025 (set_attr "prefix_0f" "0,0,1")
7026 (set (attr "athlon_decode")
7027 (cond [(eq_attr "cpu" "athlon")
7028 (const_string "vector")
7029 (eq_attr "alternative" "1")
7030 (const_string "vector")
7031 (and (eq_attr "alternative" "2")
7032 (match_operand 1 "memory_operand" ""))
7033 (const_string "vector")]
7034 (const_string "direct")))
7035 (set_attr "mode" "SI")])
7037 (define_expand "mulhi3"
7038 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7039 (mult:HI (match_operand:HI 1 "register_operand" "")
7040 (match_operand:HI 2 "general_operand" "")))
7041 (clobber (reg:CC 17))])]
7042 "TARGET_HIMODE_MATH"
7045 (define_insn "*mulhi3_1"
7046 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7047 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7048 (match_operand:HI 2 "general_operand" "K,i,mr")))
7049 (clobber (reg:CC 17))]
7050 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7052 imul{w}\t{%2, %1, %0|%0, %1, %2}
7053 imul{w}\t{%2, %1, %0|%0, %1, %2}
7054 imul{w}\t{%2, %0|%0, %2}"
7055 [(set_attr "type" "imul")
7056 (set_attr "prefix_0f" "0,0,1")
7057 (set (attr "athlon_decode")
7058 (cond [(eq_attr "cpu" "athlon")
7059 (const_string "vector")
7060 (eq_attr "alternative" "1,2")
7061 (const_string "vector")]
7062 (const_string "direct")))
7063 (set_attr "mode" "HI")])
7065 (define_expand "mulqi3"
7066 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7067 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7068 (match_operand:QI 2 "register_operand" "")))
7069 (clobber (reg:CC 17))])]
7070 "TARGET_QIMODE_MATH"
7073 (define_insn "*mulqi3_1"
7074 [(set (match_operand:QI 0 "register_operand" "=a")
7075 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7076 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7077 (clobber (reg:CC 17))]
7079 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7081 [(set_attr "type" "imul")
7082 (set_attr "length_immediate" "0")
7083 (set (attr "athlon_decode")
7084 (if_then_else (eq_attr "cpu" "athlon")
7085 (const_string "vector")
7086 (const_string "direct")))
7087 (set_attr "mode" "QI")])
7089 (define_expand "umulqihi3"
7090 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7091 (mult:HI (zero_extend:HI
7092 (match_operand:QI 1 "nonimmediate_operand" ""))
7094 (match_operand:QI 2 "register_operand" ""))))
7095 (clobber (reg:CC 17))])]
7096 "TARGET_QIMODE_MATH"
7099 (define_insn "*umulqihi3_1"
7100 [(set (match_operand:HI 0 "register_operand" "=a")
7101 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7102 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7103 (clobber (reg:CC 17))]
7105 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7107 [(set_attr "type" "imul")
7108 (set_attr "length_immediate" "0")
7109 (set (attr "athlon_decode")
7110 (if_then_else (eq_attr "cpu" "athlon")
7111 (const_string "vector")
7112 (const_string "direct")))
7113 (set_attr "mode" "QI")])
7115 (define_expand "mulqihi3"
7116 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7117 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7118 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7119 (clobber (reg:CC 17))])]
7120 "TARGET_QIMODE_MATH"
7123 (define_insn "*mulqihi3_insn"
7124 [(set (match_operand:HI 0 "register_operand" "=a")
7125 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7126 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7127 (clobber (reg:CC 17))]
7129 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7131 [(set_attr "type" "imul")
7132 (set_attr "length_immediate" "0")
7133 (set (attr "athlon_decode")
7134 (if_then_else (eq_attr "cpu" "athlon")
7135 (const_string "vector")
7136 (const_string "direct")))
7137 (set_attr "mode" "QI")])
7139 (define_expand "umulditi3"
7140 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7141 (mult:TI (zero_extend:TI
7142 (match_operand:DI 1 "nonimmediate_operand" ""))
7144 (match_operand:DI 2 "register_operand" ""))))
7145 (clobber (reg:CC 17))])]
7149 (define_insn "*umulditi3_insn"
7150 [(set (match_operand:TI 0 "register_operand" "=A")
7151 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7152 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7153 (clobber (reg:CC 17))]
7155 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7157 [(set_attr "type" "imul")
7158 (set_attr "ppro_uops" "few")
7159 (set_attr "length_immediate" "0")
7160 (set (attr "athlon_decode")
7161 (if_then_else (eq_attr "cpu" "athlon")
7162 (const_string "vector")
7163 (const_string "double")))
7164 (set_attr "mode" "DI")])
7166 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7167 (define_expand "umulsidi3"
7168 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7169 (mult:DI (zero_extend:DI
7170 (match_operand:SI 1 "nonimmediate_operand" ""))
7172 (match_operand:SI 2 "register_operand" ""))))
7173 (clobber (reg:CC 17))])]
7177 (define_insn "*umulsidi3_insn"
7178 [(set (match_operand:DI 0 "register_operand" "=A")
7179 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7180 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7181 (clobber (reg:CC 17))]
7183 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7185 [(set_attr "type" "imul")
7186 (set_attr "ppro_uops" "few")
7187 (set_attr "length_immediate" "0")
7188 (set (attr "athlon_decode")
7189 (if_then_else (eq_attr "cpu" "athlon")
7190 (const_string "vector")
7191 (const_string "double")))
7192 (set_attr "mode" "SI")])
7194 (define_expand "mulditi3"
7195 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7196 (mult:TI (sign_extend:TI
7197 (match_operand:DI 1 "nonimmediate_operand" ""))
7199 (match_operand:DI 2 "register_operand" ""))))
7200 (clobber (reg:CC 17))])]
7204 (define_insn "*mulditi3_insn"
7205 [(set (match_operand:TI 0 "register_operand" "=A")
7206 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7207 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7208 (clobber (reg:CC 17))]
7210 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7212 [(set_attr "type" "imul")
7213 (set_attr "length_immediate" "0")
7214 (set (attr "athlon_decode")
7215 (if_then_else (eq_attr "cpu" "athlon")
7216 (const_string "vector")
7217 (const_string "double")))
7218 (set_attr "mode" "DI")])
7220 (define_expand "mulsidi3"
7221 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7222 (mult:DI (sign_extend:DI
7223 (match_operand:SI 1 "nonimmediate_operand" ""))
7225 (match_operand:SI 2 "register_operand" ""))))
7226 (clobber (reg:CC 17))])]
7230 (define_insn "*mulsidi3_insn"
7231 [(set (match_operand:DI 0 "register_operand" "=A")
7232 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7233 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7234 (clobber (reg:CC 17))]
7236 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7238 [(set_attr "type" "imul")
7239 (set_attr "length_immediate" "0")
7240 (set (attr "athlon_decode")
7241 (if_then_else (eq_attr "cpu" "athlon")
7242 (const_string "vector")
7243 (const_string "double")))
7244 (set_attr "mode" "SI")])
7246 (define_expand "umuldi3_highpart"
7247 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7250 (mult:TI (zero_extend:TI
7251 (match_operand:DI 1 "nonimmediate_operand" ""))
7253 (match_operand:DI 2 "register_operand" "")))
7255 (clobber (match_scratch:DI 3 ""))
7256 (clobber (reg:CC 17))])]
7260 (define_insn "*umuldi3_highpart_rex64"
7261 [(set (match_operand:DI 0 "register_operand" "=d")
7264 (mult:TI (zero_extend:TI
7265 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7267 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7269 (clobber (match_scratch:DI 3 "=1"))
7270 (clobber (reg:CC 17))]
7272 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7274 [(set_attr "type" "imul")
7275 (set_attr "ppro_uops" "few")
7276 (set_attr "length_immediate" "0")
7277 (set (attr "athlon_decode")
7278 (if_then_else (eq_attr "cpu" "athlon")
7279 (const_string "vector")
7280 (const_string "double")))
7281 (set_attr "mode" "DI")])
7283 (define_expand "umulsi3_highpart"
7284 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7287 (mult:DI (zero_extend:DI
7288 (match_operand:SI 1 "nonimmediate_operand" ""))
7290 (match_operand:SI 2 "register_operand" "")))
7292 (clobber (match_scratch:SI 3 ""))
7293 (clobber (reg:CC 17))])]
7297 (define_insn "*umulsi3_highpart_insn"
7298 [(set (match_operand:SI 0 "register_operand" "=d")
7301 (mult:DI (zero_extend:DI
7302 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7304 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7306 (clobber (match_scratch:SI 3 "=1"))
7307 (clobber (reg:CC 17))]
7308 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7310 [(set_attr "type" "imul")
7311 (set_attr "ppro_uops" "few")
7312 (set_attr "length_immediate" "0")
7313 (set (attr "athlon_decode")
7314 (if_then_else (eq_attr "cpu" "athlon")
7315 (const_string "vector")
7316 (const_string "double")))
7317 (set_attr "mode" "SI")])
7319 (define_insn "*umulsi3_highpart_zext"
7320 [(set (match_operand:DI 0 "register_operand" "=d")
7321 (zero_extend:DI (truncate:SI
7323 (mult:DI (zero_extend:DI
7324 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7326 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7328 (clobber (match_scratch:SI 3 "=1"))
7329 (clobber (reg:CC 17))]
7331 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7333 [(set_attr "type" "imul")
7334 (set_attr "ppro_uops" "few")
7335 (set_attr "length_immediate" "0")
7336 (set (attr "athlon_decode")
7337 (if_then_else (eq_attr "cpu" "athlon")
7338 (const_string "vector")
7339 (const_string "double")))
7340 (set_attr "mode" "SI")])
7342 (define_expand "smuldi3_highpart"
7343 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7346 (mult:TI (sign_extend:TI
7347 (match_operand:DI 1 "nonimmediate_operand" ""))
7349 (match_operand:DI 2 "register_operand" "")))
7351 (clobber (match_scratch:DI 3 ""))
7352 (clobber (reg:CC 17))])]
7356 (define_insn "*smuldi3_highpart_rex64"
7357 [(set (match_operand:DI 0 "register_operand" "=d")
7360 (mult:TI (sign_extend:TI
7361 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7363 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7365 (clobber (match_scratch:DI 3 "=1"))
7366 (clobber (reg:CC 17))]
7368 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7370 [(set_attr "type" "imul")
7371 (set_attr "ppro_uops" "few")
7372 (set (attr "athlon_decode")
7373 (if_then_else (eq_attr "cpu" "athlon")
7374 (const_string "vector")
7375 (const_string "double")))
7376 (set_attr "mode" "DI")])
7378 (define_expand "smulsi3_highpart"
7379 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7382 (mult:DI (sign_extend:DI
7383 (match_operand:SI 1 "nonimmediate_operand" ""))
7385 (match_operand:SI 2 "register_operand" "")))
7387 (clobber (match_scratch:SI 3 ""))
7388 (clobber (reg:CC 17))])]
7392 (define_insn "*smulsi3_highpart_insn"
7393 [(set (match_operand:SI 0 "register_operand" "=d")
7396 (mult:DI (sign_extend:DI
7397 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7399 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7401 (clobber (match_scratch:SI 3 "=1"))
7402 (clobber (reg:CC 17))]
7403 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7405 [(set_attr "type" "imul")
7406 (set_attr "ppro_uops" "few")
7407 (set (attr "athlon_decode")
7408 (if_then_else (eq_attr "cpu" "athlon")
7409 (const_string "vector")
7410 (const_string "double")))
7411 (set_attr "mode" "SI")])
7413 (define_insn "*smulsi3_highpart_zext"
7414 [(set (match_operand:DI 0 "register_operand" "=d")
7415 (zero_extend:DI (truncate:SI
7417 (mult:DI (sign_extend:DI
7418 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7420 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7422 (clobber (match_scratch:SI 3 "=1"))
7423 (clobber (reg:CC 17))]
7425 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7427 [(set_attr "type" "imul")
7428 (set_attr "ppro_uops" "few")
7429 (set (attr "athlon_decode")
7430 (if_then_else (eq_attr "cpu" "athlon")
7431 (const_string "vector")
7432 (const_string "double")))
7433 (set_attr "mode" "SI")])
7435 ;; The patterns that match these are at the end of this file.
7437 (define_expand "mulxf3"
7438 [(set (match_operand:XF 0 "register_operand" "")
7439 (mult:XF (match_operand:XF 1 "register_operand" "")
7440 (match_operand:XF 2 "register_operand" "")))]
7444 (define_expand "muldf3"
7445 [(set (match_operand:DF 0 "register_operand" "")
7446 (mult:DF (match_operand:DF 1 "register_operand" "")
7447 (match_operand:DF 2 "nonimmediate_operand" "")))]
7448 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7451 (define_expand "mulsf3"
7452 [(set (match_operand:SF 0 "register_operand" "")
7453 (mult:SF (match_operand:SF 1 "register_operand" "")
7454 (match_operand:SF 2 "nonimmediate_operand" "")))]
7455 "TARGET_80387 || TARGET_SSE_MATH"
7458 ;; Divide instructions
7460 (define_insn "divqi3"
7461 [(set (match_operand:QI 0 "register_operand" "=a")
7462 (div:QI (match_operand:HI 1 "register_operand" "0")
7463 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7464 (clobber (reg:CC 17))]
7465 "TARGET_QIMODE_MATH"
7467 [(set_attr "type" "idiv")
7468 (set_attr "mode" "QI")
7469 (set_attr "ppro_uops" "few")])
7471 (define_insn "udivqi3"
7472 [(set (match_operand:QI 0 "register_operand" "=a")
7473 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7474 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7475 (clobber (reg:CC 17))]
7476 "TARGET_QIMODE_MATH"
7478 [(set_attr "type" "idiv")
7479 (set_attr "mode" "QI")
7480 (set_attr "ppro_uops" "few")])
7482 ;; The patterns that match these are at the end of this file.
7484 (define_expand "divxf3"
7485 [(set (match_operand:XF 0 "register_operand" "")
7486 (div:XF (match_operand:XF 1 "register_operand" "")
7487 (match_operand:XF 2 "register_operand" "")))]
7491 (define_expand "divdf3"
7492 [(set (match_operand:DF 0 "register_operand" "")
7493 (div:DF (match_operand:DF 1 "register_operand" "")
7494 (match_operand:DF 2 "nonimmediate_operand" "")))]
7495 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7498 (define_expand "divsf3"
7499 [(set (match_operand:SF 0 "register_operand" "")
7500 (div:SF (match_operand:SF 1 "register_operand" "")
7501 (match_operand:SF 2 "nonimmediate_operand" "")))]
7502 "TARGET_80387 || TARGET_SSE_MATH"
7505 ;; Remainder instructions.
7507 (define_expand "divmoddi4"
7508 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7509 (div:DI (match_operand:DI 1 "register_operand" "")
7510 (match_operand:DI 2 "nonimmediate_operand" "")))
7511 (set (match_operand:DI 3 "register_operand" "")
7512 (mod:DI (match_dup 1) (match_dup 2)))
7513 (clobber (reg:CC 17))])]
7517 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7518 ;; Penalize eax case slightly because it results in worse scheduling
7520 (define_insn "*divmoddi4_nocltd_rex64"
7521 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7522 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7523 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7524 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7525 (mod:DI (match_dup 2) (match_dup 3)))
7526 (clobber (reg:CC 17))]
7527 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7529 [(set_attr "type" "multi")])
7531 (define_insn "*divmoddi4_cltd_rex64"
7532 [(set (match_operand:DI 0 "register_operand" "=a")
7533 (div:DI (match_operand:DI 2 "register_operand" "a")
7534 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7535 (set (match_operand:DI 1 "register_operand" "=&d")
7536 (mod:DI (match_dup 2) (match_dup 3)))
7537 (clobber (reg:CC 17))]
7538 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7540 [(set_attr "type" "multi")])
7542 (define_insn "*divmoddi_noext_rex64"
7543 [(set (match_operand:DI 0 "register_operand" "=a")
7544 (div:DI (match_operand:DI 1 "register_operand" "0")
7545 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7546 (set (match_operand:DI 3 "register_operand" "=d")
7547 (mod:DI (match_dup 1) (match_dup 2)))
7548 (use (match_operand:DI 4 "register_operand" "3"))
7549 (clobber (reg:CC 17))]
7552 [(set_attr "type" "idiv")
7553 (set_attr "mode" "DI")
7554 (set_attr "ppro_uops" "few")])
7557 [(set (match_operand:DI 0 "register_operand" "")
7558 (div:DI (match_operand:DI 1 "register_operand" "")
7559 (match_operand:DI 2 "nonimmediate_operand" "")))
7560 (set (match_operand:DI 3 "register_operand" "")
7561 (mod:DI (match_dup 1) (match_dup 2)))
7562 (clobber (reg:CC 17))]
7563 "TARGET_64BIT && reload_completed"
7564 [(parallel [(set (match_dup 3)
7565 (ashiftrt:DI (match_dup 4) (const_int 63)))
7566 (clobber (reg:CC 17))])
7567 (parallel [(set (match_dup 0)
7568 (div:DI (reg:DI 0) (match_dup 2)))
7570 (mod:DI (reg:DI 0) (match_dup 2)))
7572 (clobber (reg:CC 17))])]
7574 /* Avoid use of cltd in favor of a mov+shift. */
7575 if (!TARGET_USE_CLTD && !optimize_size)
7577 if (true_regnum (operands[1]))
7578 emit_move_insn (operands[0], operands[1]);
7580 emit_move_insn (operands[3], operands[1]);
7581 operands[4] = operands[3];
7585 if (true_regnum (operands[1]))
7587 operands[4] = operands[1];
7592 (define_expand "divmodsi4"
7593 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7594 (div:SI (match_operand:SI 1 "register_operand" "")
7595 (match_operand:SI 2 "nonimmediate_operand" "")))
7596 (set (match_operand:SI 3 "register_operand" "")
7597 (mod:SI (match_dup 1) (match_dup 2)))
7598 (clobber (reg:CC 17))])]
7602 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7603 ;; Penalize eax case slightly because it results in worse scheduling
7605 (define_insn "*divmodsi4_nocltd"
7606 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7607 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7608 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7609 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7610 (mod:SI (match_dup 2) (match_dup 3)))
7611 (clobber (reg:CC 17))]
7612 "!optimize_size && !TARGET_USE_CLTD"
7614 [(set_attr "type" "multi")])
7616 (define_insn "*divmodsi4_cltd"
7617 [(set (match_operand:SI 0 "register_operand" "=a")
7618 (div:SI (match_operand:SI 2 "register_operand" "a")
7619 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7620 (set (match_operand:SI 1 "register_operand" "=&d")
7621 (mod:SI (match_dup 2) (match_dup 3)))
7622 (clobber (reg:CC 17))]
7623 "optimize_size || TARGET_USE_CLTD"
7625 [(set_attr "type" "multi")])
7627 (define_insn "*divmodsi_noext"
7628 [(set (match_operand:SI 0 "register_operand" "=a")
7629 (div:SI (match_operand:SI 1 "register_operand" "0")
7630 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7631 (set (match_operand:SI 3 "register_operand" "=d")
7632 (mod:SI (match_dup 1) (match_dup 2)))
7633 (use (match_operand:SI 4 "register_operand" "3"))
7634 (clobber (reg:CC 17))]
7637 [(set_attr "type" "idiv")
7638 (set_attr "mode" "SI")
7639 (set_attr "ppro_uops" "few")])
7642 [(set (match_operand:SI 0 "register_operand" "")
7643 (div:SI (match_operand:SI 1 "register_operand" "")
7644 (match_operand:SI 2 "nonimmediate_operand" "")))
7645 (set (match_operand:SI 3 "register_operand" "")
7646 (mod:SI (match_dup 1) (match_dup 2)))
7647 (clobber (reg:CC 17))]
7649 [(parallel [(set (match_dup 3)
7650 (ashiftrt:SI (match_dup 4) (const_int 31)))
7651 (clobber (reg:CC 17))])
7652 (parallel [(set (match_dup 0)
7653 (div:SI (reg:SI 0) (match_dup 2)))
7655 (mod:SI (reg:SI 0) (match_dup 2)))
7657 (clobber (reg:CC 17))])]
7659 /* Avoid use of cltd in favor of a mov+shift. */
7660 if (!TARGET_USE_CLTD && !optimize_size)
7662 if (true_regnum (operands[1]))
7663 emit_move_insn (operands[0], operands[1]);
7665 emit_move_insn (operands[3], operands[1]);
7666 operands[4] = operands[3];
7670 if (true_regnum (operands[1]))
7672 operands[4] = operands[1];
7676 (define_insn "divmodhi4"
7677 [(set (match_operand:HI 0 "register_operand" "=a")
7678 (div:HI (match_operand:HI 1 "register_operand" "0")
7679 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7680 (set (match_operand:HI 3 "register_operand" "=&d")
7681 (mod:HI (match_dup 1) (match_dup 2)))
7682 (clobber (reg:CC 17))]
7683 "TARGET_HIMODE_MATH"
7685 [(set_attr "type" "multi")
7686 (set_attr "length_immediate" "0")
7687 (set_attr "mode" "SI")])
7689 (define_insn "udivmoddi4"
7690 [(set (match_operand:DI 0 "register_operand" "=a")
7691 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7692 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7693 (set (match_operand:DI 3 "register_operand" "=&d")
7694 (umod:DI (match_dup 1) (match_dup 2)))
7695 (clobber (reg:CC 17))]
7697 "xor{q}\t%3, %3\;div{q}\t%2"
7698 [(set_attr "type" "multi")
7699 (set_attr "length_immediate" "0")
7700 (set_attr "mode" "DI")])
7702 (define_insn "*udivmoddi4_noext"
7703 [(set (match_operand:DI 0 "register_operand" "=a")
7704 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7705 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7706 (set (match_operand:DI 3 "register_operand" "=d")
7707 (umod:DI (match_dup 1) (match_dup 2)))
7709 (clobber (reg:CC 17))]
7712 [(set_attr "type" "idiv")
7713 (set_attr "ppro_uops" "few")
7714 (set_attr "mode" "DI")])
7717 [(set (match_operand:DI 0 "register_operand" "")
7718 (udiv:DI (match_operand:DI 1 "register_operand" "")
7719 (match_operand:DI 2 "nonimmediate_operand" "")))
7720 (set (match_operand:DI 3 "register_operand" "")
7721 (umod:DI (match_dup 1) (match_dup 2)))
7722 (clobber (reg:CC 17))]
7723 "TARGET_64BIT && reload_completed"
7724 [(set (match_dup 3) (const_int 0))
7725 (parallel [(set (match_dup 0)
7726 (udiv:DI (match_dup 1) (match_dup 2)))
7728 (umod:DI (match_dup 1) (match_dup 2)))
7730 (clobber (reg:CC 17))])]
7733 (define_insn "udivmodsi4"
7734 [(set (match_operand:SI 0 "register_operand" "=a")
7735 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7736 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7737 (set (match_operand:SI 3 "register_operand" "=&d")
7738 (umod:SI (match_dup 1) (match_dup 2)))
7739 (clobber (reg:CC 17))]
7741 "xor{l}\t%3, %3\;div{l}\t%2"
7742 [(set_attr "type" "multi")
7743 (set_attr "length_immediate" "0")
7744 (set_attr "mode" "SI")])
7746 (define_insn "*udivmodsi4_noext"
7747 [(set (match_operand:SI 0 "register_operand" "=a")
7748 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7749 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7750 (set (match_operand:SI 3 "register_operand" "=d")
7751 (umod:SI (match_dup 1) (match_dup 2)))
7753 (clobber (reg:CC 17))]
7756 [(set_attr "type" "idiv")
7757 (set_attr "ppro_uops" "few")
7758 (set_attr "mode" "SI")])
7761 [(set (match_operand:SI 0 "register_operand" "")
7762 (udiv:SI (match_operand:SI 1 "register_operand" "")
7763 (match_operand:SI 2 "nonimmediate_operand" "")))
7764 (set (match_operand:SI 3 "register_operand" "")
7765 (umod:SI (match_dup 1) (match_dup 2)))
7766 (clobber (reg:CC 17))]
7768 [(set (match_dup 3) (const_int 0))
7769 (parallel [(set (match_dup 0)
7770 (udiv:SI (match_dup 1) (match_dup 2)))
7772 (umod:SI (match_dup 1) (match_dup 2)))
7774 (clobber (reg:CC 17))])]
7777 (define_expand "udivmodhi4"
7778 [(set (match_dup 4) (const_int 0))
7779 (parallel [(set (match_operand:HI 0 "register_operand" "")
7780 (udiv:HI (match_operand:HI 1 "register_operand" "")
7781 (match_operand:HI 2 "nonimmediate_operand" "")))
7782 (set (match_operand:HI 3 "register_operand" "")
7783 (umod:HI (match_dup 1) (match_dup 2)))
7785 (clobber (reg:CC 17))])]
7786 "TARGET_HIMODE_MATH"
7787 "operands[4] = gen_reg_rtx (HImode);")
7789 (define_insn "*udivmodhi_noext"
7790 [(set (match_operand:HI 0 "register_operand" "=a")
7791 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7792 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7793 (set (match_operand:HI 3 "register_operand" "=d")
7794 (umod:HI (match_dup 1) (match_dup 2)))
7795 (use (match_operand:HI 4 "register_operand" "3"))
7796 (clobber (reg:CC 17))]
7799 [(set_attr "type" "idiv")
7800 (set_attr "mode" "HI")
7801 (set_attr "ppro_uops" "few")])
7803 ;; We can not use div/idiv for double division, because it causes
7804 ;; "division by zero" on the overflow and that's not what we expect
7805 ;; from truncate. Because true (non truncating) double division is
7806 ;; never generated, we can't create this insn anyway.
7809 ; [(set (match_operand:SI 0 "register_operand" "=a")
7811 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7813 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7814 ; (set (match_operand:SI 3 "register_operand" "=d")
7816 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7817 ; (clobber (reg:CC 17))]
7819 ; "div{l}\t{%2, %0|%0, %2}"
7820 ; [(set_attr "type" "idiv")
7821 ; (set_attr "ppro_uops" "few")])
7823 ;;- Logical AND instructions
7825 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7826 ;; Note that this excludes ah.
7828 (define_insn "*testdi_1_rex64"
7831 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7832 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7834 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7835 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7837 test{l}\t{%k1, %k0|%k0, %k1}
7838 test{l}\t{%k1, %k0|%k0, %k1}
7839 test{q}\t{%1, %0|%0, %1}
7840 test{q}\t{%1, %0|%0, %1}
7841 test{q}\t{%1, %0|%0, %1}"
7842 [(set_attr "type" "test")
7843 (set_attr "modrm" "0,1,0,1,1")
7844 (set_attr "mode" "SI,SI,DI,DI,DI")
7845 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7847 (define_insn "testsi_1"
7850 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7851 (match_operand:SI 1 "general_operand" "in,in,rin"))
7853 "ix86_match_ccmode (insn, CCNOmode)
7854 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7855 "test{l}\t{%1, %0|%0, %1}"
7856 [(set_attr "type" "test")
7857 (set_attr "modrm" "0,1,1")
7858 (set_attr "mode" "SI")
7859 (set_attr "pent_pair" "uv,np,uv")])
7861 (define_expand "testsi_ccno_1"
7864 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7865 (match_operand:SI 1 "nonmemory_operand" ""))
7870 (define_insn "*testhi_1"
7872 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7873 (match_operand:HI 1 "general_operand" "n,n,rn"))
7875 "ix86_match_ccmode (insn, CCNOmode)
7876 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7877 "test{w}\t{%1, %0|%0, %1}"
7878 [(set_attr "type" "test")
7879 (set_attr "modrm" "0,1,1")
7880 (set_attr "mode" "HI")
7881 (set_attr "pent_pair" "uv,np,uv")])
7883 (define_expand "testqi_ccz_1"
7885 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7886 (match_operand:QI 1 "nonmemory_operand" ""))
7891 (define_insn "*testqi_1"
7893 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7894 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7896 "ix86_match_ccmode (insn, CCNOmode)
7897 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7899 if (which_alternative == 3)
7901 if (GET_CODE (operands[1]) == CONST_INT
7902 && (INTVAL (operands[1]) & 0xffffff00))
7903 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7904 return "test{l}\t{%1, %k0|%k0, %1}";
7906 return "test{b}\t{%1, %0|%0, %1}";
7908 [(set_attr "type" "test")
7909 (set_attr "modrm" "0,1,1,1")
7910 (set_attr "mode" "QI,QI,QI,SI")
7911 (set_attr "pent_pair" "uv,np,uv,np")])
7913 (define_expand "testqi_ext_ccno_0"
7918 (match_operand 0 "ext_register_operand" "")
7921 (match_operand 1 "const_int_operand" ""))
7926 (define_insn "*testqi_ext_0"
7931 (match_operand 0 "ext_register_operand" "Q")
7934 (match_operand 1 "const_int_operand" "n"))
7936 "ix86_match_ccmode (insn, CCNOmode)"
7937 "test{b}\t{%1, %h0|%h0, %1}"
7938 [(set_attr "type" "test")
7939 (set_attr "mode" "QI")
7940 (set_attr "length_immediate" "1")
7941 (set_attr "pent_pair" "np")])
7943 (define_insn "*testqi_ext_1"
7948 (match_operand 0 "ext_register_operand" "Q")
7952 (match_operand:QI 1 "general_operand" "Qm")))
7954 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7955 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7956 "test{b}\t{%1, %h0|%h0, %1}"
7957 [(set_attr "type" "test")
7958 (set_attr "mode" "QI")])
7960 (define_insn "*testqi_ext_1_rex64"
7965 (match_operand 0 "ext_register_operand" "Q")
7969 (match_operand:QI 1 "register_operand" "Q")))
7971 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7972 "test{b}\t{%1, %h0|%h0, %1}"
7973 [(set_attr "type" "test")
7974 (set_attr "mode" "QI")])
7976 (define_insn "*testqi_ext_2"
7981 (match_operand 0 "ext_register_operand" "Q")
7985 (match_operand 1 "ext_register_operand" "Q")
7989 "ix86_match_ccmode (insn, CCNOmode)"
7990 "test{b}\t{%h1, %h0|%h0, %h1}"
7991 [(set_attr "type" "test")
7992 (set_attr "mode" "QI")])
7994 ;; Combine likes to form bit extractions for some tests. Humor it.
7995 (define_insn "*testqi_ext_3"
7997 (compare (zero_extract:SI
7998 (match_operand 0 "nonimmediate_operand" "rm")
7999 (match_operand:SI 1 "const_int_operand" "")
8000 (match_operand:SI 2 "const_int_operand" ""))
8002 "ix86_match_ccmode (insn, CCNOmode)
8003 && (GET_MODE (operands[0]) == SImode
8004 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8005 || GET_MODE (operands[0]) == HImode
8006 || GET_MODE (operands[0]) == QImode)"
8009 (define_insn "*testqi_ext_3_rex64"
8011 (compare (zero_extract:DI
8012 (match_operand 0 "nonimmediate_operand" "rm")
8013 (match_operand:DI 1 "const_int_operand" "")
8014 (match_operand:DI 2 "const_int_operand" ""))
8017 && ix86_match_ccmode (insn, CCNOmode)
8018 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8019 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8020 /* Ensure that resulting mask is zero or sign extended operand. */
8021 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8022 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8023 && INTVAL (operands[1]) > 32))
8024 && (GET_MODE (operands[0]) == SImode
8025 || GET_MODE (operands[0]) == DImode
8026 || GET_MODE (operands[0]) == HImode
8027 || GET_MODE (operands[0]) == QImode)"
8032 (compare (zero_extract
8033 (match_operand 0 "nonimmediate_operand" "")
8034 (match_operand 1 "const_int_operand" "")
8035 (match_operand 2 "const_int_operand" ""))
8037 "ix86_match_ccmode (insn, CCNOmode)"
8038 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8040 HOST_WIDE_INT len = INTVAL (operands[1]);
8041 HOST_WIDE_INT pos = INTVAL (operands[2]);
8043 enum machine_mode mode, submode;
8045 mode = GET_MODE (operands[0]);
8046 if (GET_CODE (operands[0]) == MEM)
8048 /* ??? Combine likes to put non-volatile mem extractions in QImode
8049 no matter the size of the test. So find a mode that works. */
8050 if (! MEM_VOLATILE_P (operands[0]))
8052 mode = smallest_mode_for_size (pos + len, MODE_INT);
8053 operands[0] = adjust_address (operands[0], mode, 0);
8056 else if (GET_CODE (operands[0]) == SUBREG
8057 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8058 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8059 && pos + len <= GET_MODE_BITSIZE (submode))
8061 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8063 operands[0] = SUBREG_REG (operands[0]);
8065 else if (mode == HImode && pos + len <= 8)
8067 /* Small HImode tests can be converted to QImode. */
8069 operands[0] = gen_lowpart (QImode, operands[0]);
8072 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8073 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8075 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8078 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8079 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8080 ;; this is relatively important trick.
8081 ;; Do the conversion only post-reload to avoid limiting of the register class
8086 (and (match_operand 0 "register_operand" "")
8087 (match_operand 1 "const_int_operand" ""))
8090 && QI_REG_P (operands[0])
8091 && ((ix86_match_ccmode (insn, CCZmode)
8092 && !(INTVAL (operands[1]) & ~(255 << 8)))
8093 || (ix86_match_ccmode (insn, CCNOmode)
8094 && !(INTVAL (operands[1]) & ~(127 << 8))))
8095 && GET_MODE (operands[0]) != QImode"
8098 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8101 "operands[0] = gen_lowpart (SImode, operands[0]);
8102 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8107 (and (match_operand 0 "nonimmediate_operand" "")
8108 (match_operand 1 "const_int_operand" ""))
8111 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8112 && ((ix86_match_ccmode (insn, CCZmode)
8113 && !(INTVAL (operands[1]) & ~255))
8114 || (ix86_match_ccmode (insn, CCNOmode)
8115 && !(INTVAL (operands[1]) & ~127)))
8116 && GET_MODE (operands[0]) != QImode"
8119 (and:QI (match_dup 0)
8122 "operands[0] = gen_lowpart (QImode, operands[0]);
8123 operands[1] = gen_lowpart (QImode, operands[1]);")
8126 ;; %%% This used to optimize known byte-wide and operations to memory,
8127 ;; and sometimes to QImode registers. If this is considered useful,
8128 ;; it should be done with splitters.
8130 (define_expand "anddi3"
8131 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8132 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8133 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8134 (clobber (reg:CC 17))]
8136 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8138 (define_insn "*anddi_1_rex64"
8139 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8140 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8141 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8142 (clobber (reg:CC 17))]
8143 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8145 switch (get_attr_type (insn))
8149 enum machine_mode mode;
8151 if (GET_CODE (operands[2]) != CONST_INT)
8153 if (INTVAL (operands[2]) == 0xff)
8155 else if (INTVAL (operands[2]) == 0xffff)
8160 operands[1] = gen_lowpart (mode, operands[1]);
8162 return "movz{bq|x}\t{%1,%0|%0, %1}";
8164 return "movz{wq|x}\t{%1,%0|%0, %1}";
8168 if (! rtx_equal_p (operands[0], operands[1]))
8170 if (get_attr_mode (insn) == MODE_SI)
8171 return "and{l}\t{%k2, %k0|%k0, %k2}";
8173 return "and{q}\t{%2, %0|%0, %2}";
8176 [(set_attr "type" "alu,alu,alu,imovx")
8177 (set_attr "length_immediate" "*,*,*,0")
8178 (set_attr "mode" "SI,DI,DI,DI")])
8180 (define_insn "*anddi_2"
8182 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8183 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8185 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8186 (and:DI (match_dup 1) (match_dup 2)))]
8187 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8188 && ix86_binary_operator_ok (AND, DImode, operands)"
8190 and{l}\t{%k2, %k0|%k0, %k2}
8191 and{q}\t{%2, %0|%0, %2}
8192 and{q}\t{%2, %0|%0, %2}"
8193 [(set_attr "type" "alu")
8194 (set_attr "mode" "SI,DI,DI")])
8196 (define_expand "andsi3"
8197 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8198 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8199 (match_operand:SI 2 "general_operand" "")))
8200 (clobber (reg:CC 17))]
8202 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8204 (define_insn "*andsi_1"
8205 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8206 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8207 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8208 (clobber (reg:CC 17))]
8209 "ix86_binary_operator_ok (AND, SImode, operands)"
8211 switch (get_attr_type (insn))
8215 enum machine_mode mode;
8217 if (GET_CODE (operands[2]) != CONST_INT)
8219 if (INTVAL (operands[2]) == 0xff)
8221 else if (INTVAL (operands[2]) == 0xffff)
8226 operands[1] = gen_lowpart (mode, operands[1]);
8228 return "movz{bl|x}\t{%1,%0|%0, %1}";
8230 return "movz{wl|x}\t{%1,%0|%0, %1}";
8234 if (! rtx_equal_p (operands[0], operands[1]))
8236 return "and{l}\t{%2, %0|%0, %2}";
8239 [(set_attr "type" "alu,alu,imovx")
8240 (set_attr "length_immediate" "*,*,0")
8241 (set_attr "mode" "SI")])
8244 [(set (match_operand 0 "register_operand" "")
8246 (const_int -65536)))
8247 (clobber (reg:CC 17))]
8248 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8249 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8250 "operands[1] = gen_lowpart (HImode, operands[0]);")
8253 [(set (match_operand 0 "ext_register_operand" "")
8256 (clobber (reg:CC 17))]
8257 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8258 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8259 "operands[1] = gen_lowpart (QImode, operands[0]);")
8262 [(set (match_operand 0 "ext_register_operand" "")
8264 (const_int -65281)))
8265 (clobber (reg:CC 17))]
8266 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8267 [(parallel [(set (zero_extract:SI (match_dup 0)
8271 (zero_extract:SI (match_dup 0)
8274 (zero_extract:SI (match_dup 0)
8277 (clobber (reg:CC 17))])]
8278 "operands[0] = gen_lowpart (SImode, operands[0]);")
8280 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8281 (define_insn "*andsi_1_zext"
8282 [(set (match_operand:DI 0 "register_operand" "=r")
8284 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8285 (match_operand:SI 2 "general_operand" "rim"))))
8286 (clobber (reg:CC 17))]
8287 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8288 "and{l}\t{%2, %k0|%k0, %2}"
8289 [(set_attr "type" "alu")
8290 (set_attr "mode" "SI")])
8292 (define_insn "*andsi_2"
8294 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8295 (match_operand:SI 2 "general_operand" "rim,ri"))
8297 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8298 (and:SI (match_dup 1) (match_dup 2)))]
8299 "ix86_match_ccmode (insn, CCNOmode)
8300 && ix86_binary_operator_ok (AND, SImode, operands)"
8301 "and{l}\t{%2, %0|%0, %2}"
8302 [(set_attr "type" "alu")
8303 (set_attr "mode" "SI")])
8305 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8306 (define_insn "*andsi_2_zext"
8308 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8309 (match_operand:SI 2 "general_operand" "rim"))
8311 (set (match_operand:DI 0 "register_operand" "=r")
8312 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8313 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8314 && ix86_binary_operator_ok (AND, SImode, operands)"
8315 "and{l}\t{%2, %k0|%k0, %2}"
8316 [(set_attr "type" "alu")
8317 (set_attr "mode" "SI")])
8319 (define_expand "andhi3"
8320 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8321 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8322 (match_operand:HI 2 "general_operand" "")))
8323 (clobber (reg:CC 17))]
8324 "TARGET_HIMODE_MATH"
8325 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8327 (define_insn "*andhi_1"
8328 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8329 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8330 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8331 (clobber (reg:CC 17))]
8332 "ix86_binary_operator_ok (AND, HImode, operands)"
8334 switch (get_attr_type (insn))
8337 if (GET_CODE (operands[2]) != CONST_INT)
8339 if (INTVAL (operands[2]) == 0xff)
8340 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8344 if (! rtx_equal_p (operands[0], operands[1]))
8347 return "and{w}\t{%2, %0|%0, %2}";
8350 [(set_attr "type" "alu,alu,imovx")
8351 (set_attr "length_immediate" "*,*,0")
8352 (set_attr "mode" "HI,HI,SI")])
8354 (define_insn "*andhi_2"
8356 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8357 (match_operand:HI 2 "general_operand" "rim,ri"))
8359 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8360 (and:HI (match_dup 1) (match_dup 2)))]
8361 "ix86_match_ccmode (insn, CCNOmode)
8362 && ix86_binary_operator_ok (AND, HImode, operands)"
8363 "and{w}\t{%2, %0|%0, %2}"
8364 [(set_attr "type" "alu")
8365 (set_attr "mode" "HI")])
8367 (define_expand "andqi3"
8368 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8369 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8370 (match_operand:QI 2 "general_operand" "")))
8371 (clobber (reg:CC 17))]
8372 "TARGET_QIMODE_MATH"
8373 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8375 ;; %%% Potential partial reg stall on alternative 2. What to do?
8376 (define_insn "*andqi_1"
8377 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8378 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8379 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8380 (clobber (reg:CC 17))]
8381 "ix86_binary_operator_ok (AND, QImode, operands)"
8383 and{b}\t{%2, %0|%0, %2}
8384 and{b}\t{%2, %0|%0, %2}
8385 and{l}\t{%k2, %k0|%k0, %k2}"
8386 [(set_attr "type" "alu")
8387 (set_attr "mode" "QI,QI,SI")])
8389 (define_insn "*andqi_1_slp"
8390 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8391 (and:QI (match_dup 0)
8392 (match_operand:QI 1 "general_operand" "qi,qmi")))
8393 (clobber (reg:CC 17))]
8394 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8395 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8396 "and{b}\t{%1, %0|%0, %1}"
8397 [(set_attr "type" "alu1")
8398 (set_attr "mode" "QI")])
8400 (define_insn "*andqi_2"
8403 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8404 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8406 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8407 (and:QI (match_dup 1) (match_dup 2)))]
8408 "ix86_match_ccmode (insn, CCNOmode)
8409 && ix86_binary_operator_ok (AND, QImode, operands)"
8411 if (which_alternative == 2)
8413 if (GET_CODE (operands[2]) == CONST_INT
8414 && (INTVAL (operands[2]) & 0xffffff00))
8415 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8416 return "and{l}\t{%2, %k0|%k0, %2}";
8418 return "and{b}\t{%2, %0|%0, %2}";
8420 [(set_attr "type" "alu")
8421 (set_attr "mode" "QI,QI,SI")])
8423 (define_insn "*andqi_2_slp"
8426 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8427 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8429 (set (strict_low_part (match_dup 0))
8430 (and:QI (match_dup 0) (match_dup 1)))]
8431 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8432 && ix86_match_ccmode (insn, CCNOmode)
8433 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8434 "and{b}\t{%1, %0|%0, %1}"
8435 [(set_attr "type" "alu1")
8436 (set_attr "mode" "QI")])
8438 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8439 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8440 ;; for a QImode operand, which of course failed.
8442 (define_insn "andqi_ext_0"
8443 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8448 (match_operand 1 "ext_register_operand" "0")
8451 (match_operand 2 "const_int_operand" "n")))
8452 (clobber (reg:CC 17))]
8454 "and{b}\t{%2, %h0|%h0, %2}"
8455 [(set_attr "type" "alu")
8456 (set_attr "length_immediate" "1")
8457 (set_attr "mode" "QI")])
8459 ;; Generated by peephole translating test to and. This shows up
8460 ;; often in fp comparisons.
8462 (define_insn "*andqi_ext_0_cc"
8467 (match_operand 1 "ext_register_operand" "0")
8470 (match_operand 2 "const_int_operand" "n"))
8472 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8481 "ix86_match_ccmode (insn, CCNOmode)"
8482 "and{b}\t{%2, %h0|%h0, %2}"
8483 [(set_attr "type" "alu")
8484 (set_attr "length_immediate" "1")
8485 (set_attr "mode" "QI")])
8487 (define_insn "*andqi_ext_1"
8488 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8493 (match_operand 1 "ext_register_operand" "0")
8497 (match_operand:QI 2 "general_operand" "Qm"))))
8498 (clobber (reg:CC 17))]
8500 "and{b}\t{%2, %h0|%h0, %2}"
8501 [(set_attr "type" "alu")
8502 (set_attr "length_immediate" "0")
8503 (set_attr "mode" "QI")])
8505 (define_insn "*andqi_ext_1_rex64"
8506 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8511 (match_operand 1 "ext_register_operand" "0")
8515 (match_operand 2 "ext_register_operand" "Q"))))
8516 (clobber (reg:CC 17))]
8518 "and{b}\t{%2, %h0|%h0, %2}"
8519 [(set_attr "type" "alu")
8520 (set_attr "length_immediate" "0")
8521 (set_attr "mode" "QI")])
8523 (define_insn "*andqi_ext_2"
8524 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8529 (match_operand 1 "ext_register_operand" "%0")
8533 (match_operand 2 "ext_register_operand" "Q")
8536 (clobber (reg:CC 17))]
8538 "and{b}\t{%h2, %h0|%h0, %h2}"
8539 [(set_attr "type" "alu")
8540 (set_attr "length_immediate" "0")
8541 (set_attr "mode" "QI")])
8543 ;; Convert wide AND instructions with immediate operand to shorter QImode
8544 ;; equivalents when possible.
8545 ;; Don't do the splitting with memory operands, since it introduces risk
8546 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8547 ;; for size, but that can (should?) be handled by generic code instead.
8549 [(set (match_operand 0 "register_operand" "")
8550 (and (match_operand 1 "register_operand" "")
8551 (match_operand 2 "const_int_operand" "")))
8552 (clobber (reg:CC 17))]
8554 && QI_REG_P (operands[0])
8555 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8556 && !(~INTVAL (operands[2]) & ~(255 << 8))
8557 && GET_MODE (operands[0]) != QImode"
8558 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8559 (and:SI (zero_extract:SI (match_dup 1)
8560 (const_int 8) (const_int 8))
8562 (clobber (reg:CC 17))])]
8563 "operands[0] = gen_lowpart (SImode, operands[0]);
8564 operands[1] = gen_lowpart (SImode, operands[1]);
8565 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8567 ;; Since AND can be encoded with sign extended immediate, this is only
8568 ;; profitable when 7th bit is not set.
8570 [(set (match_operand 0 "register_operand" "")
8571 (and (match_operand 1 "general_operand" "")
8572 (match_operand 2 "const_int_operand" "")))
8573 (clobber (reg:CC 17))]
8575 && ANY_QI_REG_P (operands[0])
8576 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8577 && !(~INTVAL (operands[2]) & ~255)
8578 && !(INTVAL (operands[2]) & 128)
8579 && GET_MODE (operands[0]) != QImode"
8580 [(parallel [(set (strict_low_part (match_dup 0))
8581 (and:QI (match_dup 1)
8583 (clobber (reg:CC 17))])]
8584 "operands[0] = gen_lowpart (QImode, operands[0]);
8585 operands[1] = gen_lowpart (QImode, operands[1]);
8586 operands[2] = gen_lowpart (QImode, operands[2]);")
8588 ;; Logical inclusive OR instructions
8590 ;; %%% This used to optimize known byte-wide and operations to memory.
8591 ;; If this is considered useful, it should be done with splitters.
8593 (define_expand "iordi3"
8594 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8595 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8596 (match_operand:DI 2 "x86_64_general_operand" "")))
8597 (clobber (reg:CC 17))]
8599 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8601 (define_insn "*iordi_1_rex64"
8602 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8603 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8604 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8605 (clobber (reg:CC 17))]
8607 && ix86_binary_operator_ok (IOR, DImode, operands)"
8608 "or{q}\t{%2, %0|%0, %2}"
8609 [(set_attr "type" "alu")
8610 (set_attr "mode" "DI")])
8612 (define_insn "*iordi_2_rex64"
8614 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8615 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8617 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8618 (ior:DI (match_dup 1) (match_dup 2)))]
8620 && ix86_match_ccmode (insn, CCNOmode)
8621 && ix86_binary_operator_ok (IOR, DImode, operands)"
8622 "or{q}\t{%2, %0|%0, %2}"
8623 [(set_attr "type" "alu")
8624 (set_attr "mode" "DI")])
8626 (define_insn "*iordi_3_rex64"
8628 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8629 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8631 (clobber (match_scratch:DI 0 "=r"))]
8633 && ix86_match_ccmode (insn, CCNOmode)
8634 && ix86_binary_operator_ok (IOR, DImode, operands)"
8635 "or{q}\t{%2, %0|%0, %2}"
8636 [(set_attr "type" "alu")
8637 (set_attr "mode" "DI")])
8640 (define_expand "iorsi3"
8641 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8642 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8643 (match_operand:SI 2 "general_operand" "")))
8644 (clobber (reg:CC 17))]
8646 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8648 (define_insn "*iorsi_1"
8649 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8650 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8651 (match_operand:SI 2 "general_operand" "ri,rmi")))
8652 (clobber (reg:CC 17))]
8653 "ix86_binary_operator_ok (IOR, SImode, operands)"
8654 "or{l}\t{%2, %0|%0, %2}"
8655 [(set_attr "type" "alu")
8656 (set_attr "mode" "SI")])
8658 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8659 (define_insn "*iorsi_1_zext"
8660 [(set (match_operand:DI 0 "register_operand" "=rm")
8662 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8663 (match_operand:SI 2 "general_operand" "rim"))))
8664 (clobber (reg:CC 17))]
8665 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8666 "or{l}\t{%2, %k0|%k0, %2}"
8667 [(set_attr "type" "alu")
8668 (set_attr "mode" "SI")])
8670 (define_insn "*iorsi_1_zext_imm"
8671 [(set (match_operand:DI 0 "register_operand" "=rm")
8672 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8673 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8674 (clobber (reg:CC 17))]
8676 "or{l}\t{%2, %k0|%k0, %2}"
8677 [(set_attr "type" "alu")
8678 (set_attr "mode" "SI")])
8680 (define_insn "*iorsi_2"
8682 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8683 (match_operand:SI 2 "general_operand" "rim,ri"))
8685 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8686 (ior:SI (match_dup 1) (match_dup 2)))]
8687 "ix86_match_ccmode (insn, CCNOmode)
8688 && ix86_binary_operator_ok (IOR, SImode, operands)"
8689 "or{l}\t{%2, %0|%0, %2}"
8690 [(set_attr "type" "alu")
8691 (set_attr "mode" "SI")])
8693 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8694 ;; ??? Special case for immediate operand is missing - it is tricky.
8695 (define_insn "*iorsi_2_zext"
8697 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8698 (match_operand:SI 2 "general_operand" "rim"))
8700 (set (match_operand:DI 0 "register_operand" "=r")
8701 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8702 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8703 && ix86_binary_operator_ok (IOR, SImode, operands)"
8704 "or{l}\t{%2, %k0|%k0, %2}"
8705 [(set_attr "type" "alu")
8706 (set_attr "mode" "SI")])
8708 (define_insn "*iorsi_2_zext_imm"
8710 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8711 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8713 (set (match_operand:DI 0 "register_operand" "=r")
8714 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8715 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8716 && ix86_binary_operator_ok (IOR, SImode, operands)"
8717 "or{l}\t{%2, %k0|%k0, %2}"
8718 [(set_attr "type" "alu")
8719 (set_attr "mode" "SI")])
8721 (define_insn "*iorsi_3"
8723 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8724 (match_operand:SI 2 "general_operand" "rim"))
8726 (clobber (match_scratch:SI 0 "=r"))]
8727 "ix86_match_ccmode (insn, CCNOmode)
8728 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8729 "or{l}\t{%2, %0|%0, %2}"
8730 [(set_attr "type" "alu")
8731 (set_attr "mode" "SI")])
8733 (define_expand "iorhi3"
8734 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8735 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8736 (match_operand:HI 2 "general_operand" "")))
8737 (clobber (reg:CC 17))]
8738 "TARGET_HIMODE_MATH"
8739 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8741 (define_insn "*iorhi_1"
8742 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8743 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8744 (match_operand:HI 2 "general_operand" "rmi,ri")))
8745 (clobber (reg:CC 17))]
8746 "ix86_binary_operator_ok (IOR, HImode, operands)"
8747 "or{w}\t{%2, %0|%0, %2}"
8748 [(set_attr "type" "alu")
8749 (set_attr "mode" "HI")])
8751 (define_insn "*iorhi_2"
8753 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8754 (match_operand:HI 2 "general_operand" "rim,ri"))
8756 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8757 (ior:HI (match_dup 1) (match_dup 2)))]
8758 "ix86_match_ccmode (insn, CCNOmode)
8759 && ix86_binary_operator_ok (IOR, HImode, operands)"
8760 "or{w}\t{%2, %0|%0, %2}"
8761 [(set_attr "type" "alu")
8762 (set_attr "mode" "HI")])
8764 (define_insn "*iorhi_3"
8766 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8767 (match_operand:HI 2 "general_operand" "rim"))
8769 (clobber (match_scratch:HI 0 "=r"))]
8770 "ix86_match_ccmode (insn, CCNOmode)
8771 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8772 "or{w}\t{%2, %0|%0, %2}"
8773 [(set_attr "type" "alu")
8774 (set_attr "mode" "HI")])
8776 (define_expand "iorqi3"
8777 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8778 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8779 (match_operand:QI 2 "general_operand" "")))
8780 (clobber (reg:CC 17))]
8781 "TARGET_QIMODE_MATH"
8782 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8784 ;; %%% Potential partial reg stall on alternative 2. What to do?
8785 (define_insn "*iorqi_1"
8786 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8787 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8788 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8789 (clobber (reg:CC 17))]
8790 "ix86_binary_operator_ok (IOR, QImode, operands)"
8792 or{b}\t{%2, %0|%0, %2}
8793 or{b}\t{%2, %0|%0, %2}
8794 or{l}\t{%k2, %k0|%k0, %k2}"
8795 [(set_attr "type" "alu")
8796 (set_attr "mode" "QI,QI,SI")])
8798 (define_insn "*iorqi_1_slp"
8799 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8800 (ior:QI (match_dup 0)
8801 (match_operand:QI 1 "general_operand" "qmi,qi")))
8802 (clobber (reg:CC 17))]
8803 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8804 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8805 "or{b}\t{%1, %0|%0, %1}"
8806 [(set_attr "type" "alu1")
8807 (set_attr "mode" "QI")])
8809 (define_insn "*iorqi_2"
8811 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8812 (match_operand:QI 2 "general_operand" "qim,qi"))
8814 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8815 (ior:QI (match_dup 1) (match_dup 2)))]
8816 "ix86_match_ccmode (insn, CCNOmode)
8817 && ix86_binary_operator_ok (IOR, QImode, operands)"
8818 "or{b}\t{%2, %0|%0, %2}"
8819 [(set_attr "type" "alu")
8820 (set_attr "mode" "QI")])
8822 (define_insn "*iorqi_2_slp"
8824 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8825 (match_operand:QI 1 "general_operand" "qim,qi"))
8827 (set (strict_low_part (match_dup 0))
8828 (ior:QI (match_dup 0) (match_dup 1)))]
8829 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8830 && ix86_match_ccmode (insn, CCNOmode)
8831 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8832 "or{b}\t{%1, %0|%0, %1}"
8833 [(set_attr "type" "alu1")
8834 (set_attr "mode" "QI")])
8836 (define_insn "*iorqi_3"
8838 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8839 (match_operand:QI 2 "general_operand" "qim"))
8841 (clobber (match_scratch:QI 0 "=q"))]
8842 "ix86_match_ccmode (insn, CCNOmode)
8843 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8844 "or{b}\t{%2, %0|%0, %2}"
8845 [(set_attr "type" "alu")
8846 (set_attr "mode" "QI")])
8848 (define_insn "iorqi_ext_0"
8849 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8854 (match_operand 1 "ext_register_operand" "0")
8857 (match_operand 2 "const_int_operand" "n")))
8858 (clobber (reg:CC 17))]
8859 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8860 "or{b}\t{%2, %h0|%h0, %2}"
8861 [(set_attr "type" "alu")
8862 (set_attr "length_immediate" "1")
8863 (set_attr "mode" "QI")])
8865 (define_insn "*iorqi_ext_1"
8866 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8871 (match_operand 1 "ext_register_operand" "0")
8875 (match_operand:QI 2 "general_operand" "Qm"))))
8876 (clobber (reg:CC 17))]
8878 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8879 "or{b}\t{%2, %h0|%h0, %2}"
8880 [(set_attr "type" "alu")
8881 (set_attr "length_immediate" "0")
8882 (set_attr "mode" "QI")])
8884 (define_insn "*iorqi_ext_1_rex64"
8885 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8890 (match_operand 1 "ext_register_operand" "0")
8894 (match_operand 2 "ext_register_operand" "Q"))))
8895 (clobber (reg:CC 17))]
8897 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8898 "or{b}\t{%2, %h0|%h0, %2}"
8899 [(set_attr "type" "alu")
8900 (set_attr "length_immediate" "0")
8901 (set_attr "mode" "QI")])
8903 (define_insn "*iorqi_ext_2"
8904 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8908 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8911 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8914 (clobber (reg:CC 17))]
8915 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8916 "ior{b}\t{%h2, %h0|%h0, %h2}"
8917 [(set_attr "type" "alu")
8918 (set_attr "length_immediate" "0")
8919 (set_attr "mode" "QI")])
8922 [(set (match_operand 0 "register_operand" "")
8923 (ior (match_operand 1 "register_operand" "")
8924 (match_operand 2 "const_int_operand" "")))
8925 (clobber (reg:CC 17))]
8927 && QI_REG_P (operands[0])
8928 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8929 && !(INTVAL (operands[2]) & ~(255 << 8))
8930 && GET_MODE (operands[0]) != QImode"
8931 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8932 (ior:SI (zero_extract:SI (match_dup 1)
8933 (const_int 8) (const_int 8))
8935 (clobber (reg:CC 17))])]
8936 "operands[0] = gen_lowpart (SImode, operands[0]);
8937 operands[1] = gen_lowpart (SImode, operands[1]);
8938 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8940 ;; Since OR can be encoded with sign extended immediate, this is only
8941 ;; profitable when 7th bit is set.
8943 [(set (match_operand 0 "register_operand" "")
8944 (ior (match_operand 1 "general_operand" "")
8945 (match_operand 2 "const_int_operand" "")))
8946 (clobber (reg:CC 17))]
8948 && ANY_QI_REG_P (operands[0])
8949 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8950 && !(INTVAL (operands[2]) & ~255)
8951 && (INTVAL (operands[2]) & 128)
8952 && GET_MODE (operands[0]) != QImode"
8953 [(parallel [(set (strict_low_part (match_dup 0))
8954 (ior:QI (match_dup 1)
8956 (clobber (reg:CC 17))])]
8957 "operands[0] = gen_lowpart (QImode, operands[0]);
8958 operands[1] = gen_lowpart (QImode, operands[1]);
8959 operands[2] = gen_lowpart (QImode, operands[2]);")
8961 ;; Logical XOR instructions
8963 ;; %%% This used to optimize known byte-wide and operations to memory.
8964 ;; If this is considered useful, it should be done with splitters.
8966 (define_expand "xordi3"
8967 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8968 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8969 (match_operand:DI 2 "x86_64_general_operand" "")))
8970 (clobber (reg:CC 17))]
8972 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8974 (define_insn "*xordi_1_rex64"
8975 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8976 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8977 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8978 (clobber (reg:CC 17))]
8980 && ix86_binary_operator_ok (XOR, DImode, operands)"
8982 xor{q}\t{%2, %0|%0, %2}
8983 xor{q}\t{%2, %0|%0, %2}"
8984 [(set_attr "type" "alu")
8985 (set_attr "mode" "DI,DI")])
8987 (define_insn "*xordi_2_rex64"
8989 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8990 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8992 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8993 (xor:DI (match_dup 1) (match_dup 2)))]
8995 && ix86_match_ccmode (insn, CCNOmode)
8996 && ix86_binary_operator_ok (XOR, DImode, operands)"
8998 xor{q}\t{%2, %0|%0, %2}
8999 xor{q}\t{%2, %0|%0, %2}"
9000 [(set_attr "type" "alu")
9001 (set_attr "mode" "DI,DI")])
9003 (define_insn "*xordi_3_rex64"
9005 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9006 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9008 (clobber (match_scratch:DI 0 "=r"))]
9010 && ix86_match_ccmode (insn, CCNOmode)
9011 && ix86_binary_operator_ok (XOR, DImode, operands)"
9012 "xor{q}\t{%2, %0|%0, %2}"
9013 [(set_attr "type" "alu")
9014 (set_attr "mode" "DI")])
9016 (define_expand "xorsi3"
9017 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9018 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9019 (match_operand:SI 2 "general_operand" "")))
9020 (clobber (reg:CC 17))]
9022 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9024 (define_insn "*xorsi_1"
9025 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9026 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9027 (match_operand:SI 2 "general_operand" "ri,rm")))
9028 (clobber (reg:CC 17))]
9029 "ix86_binary_operator_ok (XOR, SImode, operands)"
9030 "xor{l}\t{%2, %0|%0, %2}"
9031 [(set_attr "type" "alu")
9032 (set_attr "mode" "SI")])
9034 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9035 ;; Add speccase for immediates
9036 (define_insn "*xorsi_1_zext"
9037 [(set (match_operand:DI 0 "register_operand" "=r")
9039 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9040 (match_operand:SI 2 "general_operand" "rim"))))
9041 (clobber (reg:CC 17))]
9042 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9043 "xor{l}\t{%2, %k0|%k0, %2}"
9044 [(set_attr "type" "alu")
9045 (set_attr "mode" "SI")])
9047 (define_insn "*xorsi_1_zext_imm"
9048 [(set (match_operand:DI 0 "register_operand" "=r")
9049 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9050 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9051 (clobber (reg:CC 17))]
9052 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9053 "xor{l}\t{%2, %k0|%k0, %2}"
9054 [(set_attr "type" "alu")
9055 (set_attr "mode" "SI")])
9057 (define_insn "*xorsi_2"
9059 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9060 (match_operand:SI 2 "general_operand" "rim,ri"))
9062 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9063 (xor:SI (match_dup 1) (match_dup 2)))]
9064 "ix86_match_ccmode (insn, CCNOmode)
9065 && ix86_binary_operator_ok (XOR, SImode, operands)"
9066 "xor{l}\t{%2, %0|%0, %2}"
9067 [(set_attr "type" "alu")
9068 (set_attr "mode" "SI")])
9070 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9071 ;; ??? Special case for immediate operand is missing - it is tricky.
9072 (define_insn "*xorsi_2_zext"
9074 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9075 (match_operand:SI 2 "general_operand" "rim"))
9077 (set (match_operand:DI 0 "register_operand" "=r")
9078 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9079 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9080 && ix86_binary_operator_ok (XOR, SImode, operands)"
9081 "xor{l}\t{%2, %k0|%k0, %2}"
9082 [(set_attr "type" "alu")
9083 (set_attr "mode" "SI")])
9085 (define_insn "*xorsi_2_zext_imm"
9087 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9088 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9090 (set (match_operand:DI 0 "register_operand" "=r")
9091 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9092 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9093 && ix86_binary_operator_ok (XOR, SImode, operands)"
9094 "xor{l}\t{%2, %k0|%k0, %2}"
9095 [(set_attr "type" "alu")
9096 (set_attr "mode" "SI")])
9098 (define_insn "*xorsi_3"
9100 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9101 (match_operand:SI 2 "general_operand" "rim"))
9103 (clobber (match_scratch:SI 0 "=r"))]
9104 "ix86_match_ccmode (insn, CCNOmode)
9105 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9106 "xor{l}\t{%2, %0|%0, %2}"
9107 [(set_attr "type" "alu")
9108 (set_attr "mode" "SI")])
9110 (define_expand "xorhi3"
9111 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9112 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9113 (match_operand:HI 2 "general_operand" "")))
9114 (clobber (reg:CC 17))]
9115 "TARGET_HIMODE_MATH"
9116 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9118 (define_insn "*xorhi_1"
9119 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9120 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9121 (match_operand:HI 2 "general_operand" "rmi,ri")))
9122 (clobber (reg:CC 17))]
9123 "ix86_binary_operator_ok (XOR, HImode, operands)"
9124 "xor{w}\t{%2, %0|%0, %2}"
9125 [(set_attr "type" "alu")
9126 (set_attr "mode" "HI")])
9128 (define_insn "*xorhi_2"
9130 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9131 (match_operand:HI 2 "general_operand" "rim,ri"))
9133 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9134 (xor:HI (match_dup 1) (match_dup 2)))]
9135 "ix86_match_ccmode (insn, CCNOmode)
9136 && ix86_binary_operator_ok (XOR, HImode, operands)"
9137 "xor{w}\t{%2, %0|%0, %2}"
9138 [(set_attr "type" "alu")
9139 (set_attr "mode" "HI")])
9141 (define_insn "*xorhi_3"
9143 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9144 (match_operand:HI 2 "general_operand" "rim"))
9146 (clobber (match_scratch:HI 0 "=r"))]
9147 "ix86_match_ccmode (insn, CCNOmode)
9148 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9149 "xor{w}\t{%2, %0|%0, %2}"
9150 [(set_attr "type" "alu")
9151 (set_attr "mode" "HI")])
9153 (define_expand "xorqi3"
9154 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9155 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9156 (match_operand:QI 2 "general_operand" "")))
9157 (clobber (reg:CC 17))]
9158 "TARGET_QIMODE_MATH"
9159 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9161 ;; %%% Potential partial reg stall on alternative 2. What to do?
9162 (define_insn "*xorqi_1"
9163 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9164 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9165 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9166 (clobber (reg:CC 17))]
9167 "ix86_binary_operator_ok (XOR, QImode, operands)"
9169 xor{b}\t{%2, %0|%0, %2}
9170 xor{b}\t{%2, %0|%0, %2}
9171 xor{l}\t{%k2, %k0|%k0, %k2}"
9172 [(set_attr "type" "alu")
9173 (set_attr "mode" "QI,QI,SI")])
9175 (define_insn "*xorqi_1_slp"
9176 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9177 (xor:QI (match_dup 0)
9178 (match_operand:QI 1 "general_operand" "qi,qmi")))
9179 (clobber (reg:CC 17))]
9180 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9181 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9182 "xor{b}\t{%1, %0|%0, %1}"
9183 [(set_attr "type" "alu1")
9184 (set_attr "mode" "QI")])
9186 (define_insn "xorqi_ext_0"
9187 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9192 (match_operand 1 "ext_register_operand" "0")
9195 (match_operand 2 "const_int_operand" "n")))
9196 (clobber (reg:CC 17))]
9197 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9198 "xor{b}\t{%2, %h0|%h0, %2}"
9199 [(set_attr "type" "alu")
9200 (set_attr "length_immediate" "1")
9201 (set_attr "mode" "QI")])
9203 (define_insn "*xorqi_ext_1"
9204 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9209 (match_operand 1 "ext_register_operand" "0")
9213 (match_operand:QI 2 "general_operand" "Qm"))))
9214 (clobber (reg:CC 17))]
9216 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9217 "xor{b}\t{%2, %h0|%h0, %2}"
9218 [(set_attr "type" "alu")
9219 (set_attr "length_immediate" "0")
9220 (set_attr "mode" "QI")])
9222 (define_insn "*xorqi_ext_1_rex64"
9223 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9228 (match_operand 1 "ext_register_operand" "0")
9232 (match_operand 2 "ext_register_operand" "Q"))))
9233 (clobber (reg:CC 17))]
9235 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9236 "xor{b}\t{%2, %h0|%h0, %2}"
9237 [(set_attr "type" "alu")
9238 (set_attr "length_immediate" "0")
9239 (set_attr "mode" "QI")])
9241 (define_insn "*xorqi_ext_2"
9242 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9246 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9249 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9252 (clobber (reg:CC 17))]
9253 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9254 "xor{b}\t{%h2, %h0|%h0, %h2}"
9255 [(set_attr "type" "alu")
9256 (set_attr "length_immediate" "0")
9257 (set_attr "mode" "QI")])
9259 (define_insn "*xorqi_cc_1"
9262 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9263 (match_operand:QI 2 "general_operand" "qim,qi"))
9265 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9266 (xor:QI (match_dup 1) (match_dup 2)))]
9267 "ix86_match_ccmode (insn, CCNOmode)
9268 && ix86_binary_operator_ok (XOR, QImode, operands)"
9269 "xor{b}\t{%2, %0|%0, %2}"
9270 [(set_attr "type" "alu")
9271 (set_attr "mode" "QI")])
9273 (define_insn "*xorqi_2_slp"
9275 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9276 (match_operand:QI 1 "general_operand" "qim,qi"))
9278 (set (strict_low_part (match_dup 0))
9279 (xor:QI (match_dup 0) (match_dup 1)))]
9280 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9281 && ix86_match_ccmode (insn, CCNOmode)
9282 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9283 "xor{b}\t{%1, %0|%0, %1}"
9284 [(set_attr "type" "alu1")
9285 (set_attr "mode" "QI")])
9287 (define_insn "*xorqi_cc_2"
9290 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9291 (match_operand:QI 2 "general_operand" "qim"))
9293 (clobber (match_scratch:QI 0 "=q"))]
9294 "ix86_match_ccmode (insn, CCNOmode)
9295 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9296 "xor{b}\t{%2, %0|%0, %2}"
9297 [(set_attr "type" "alu")
9298 (set_attr "mode" "QI")])
9300 (define_insn "*xorqi_cc_ext_1"
9305 (match_operand 1 "ext_register_operand" "0")
9308 (match_operand:QI 2 "general_operand" "qmn"))
9310 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9314 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9316 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9317 "xor{b}\t{%2, %h0|%h0, %2}"
9318 [(set_attr "type" "alu")
9319 (set_attr "mode" "QI")])
9321 (define_insn "*xorqi_cc_ext_1_rex64"
9326 (match_operand 1 "ext_register_operand" "0")
9329 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9331 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9335 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9337 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9338 "xor{b}\t{%2, %h0|%h0, %2}"
9339 [(set_attr "type" "alu")
9340 (set_attr "mode" "QI")])
9342 (define_expand "xorqi_cc_ext_1"
9348 (match_operand 1 "ext_register_operand" "")
9351 (match_operand:QI 2 "general_operand" ""))
9353 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9357 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9363 [(set (match_operand 0 "register_operand" "")
9364 (xor (match_operand 1 "register_operand" "")
9365 (match_operand 2 "const_int_operand" "")))
9366 (clobber (reg:CC 17))]
9368 && QI_REG_P (operands[0])
9369 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9370 && !(INTVAL (operands[2]) & ~(255 << 8))
9371 && GET_MODE (operands[0]) != QImode"
9372 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9373 (xor:SI (zero_extract:SI (match_dup 1)
9374 (const_int 8) (const_int 8))
9376 (clobber (reg:CC 17))])]
9377 "operands[0] = gen_lowpart (SImode, operands[0]);
9378 operands[1] = gen_lowpart (SImode, operands[1]);
9379 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9381 ;; Since XOR can be encoded with sign extended immediate, this is only
9382 ;; profitable when 7th bit is set.
9384 [(set (match_operand 0 "register_operand" "")
9385 (xor (match_operand 1 "general_operand" "")
9386 (match_operand 2 "const_int_operand" "")))
9387 (clobber (reg:CC 17))]
9389 && ANY_QI_REG_P (operands[0])
9390 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9391 && !(INTVAL (operands[2]) & ~255)
9392 && (INTVAL (operands[2]) & 128)
9393 && GET_MODE (operands[0]) != QImode"
9394 [(parallel [(set (strict_low_part (match_dup 0))
9395 (xor:QI (match_dup 1)
9397 (clobber (reg:CC 17))])]
9398 "operands[0] = gen_lowpart (QImode, operands[0]);
9399 operands[1] = gen_lowpart (QImode, operands[1]);
9400 operands[2] = gen_lowpart (QImode, operands[2]);")
9402 ;; Negation instructions
9404 (define_expand "negdi2"
9405 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9406 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9407 (clobber (reg:CC 17))])]
9409 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9411 (define_insn "*negdi2_1"
9412 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9413 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9414 (clobber (reg:CC 17))]
9416 && ix86_unary_operator_ok (NEG, DImode, operands)"
9420 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9421 (neg:DI (match_operand:DI 1 "general_operand" "")))
9422 (clobber (reg:CC 17))]
9423 "!TARGET_64BIT && reload_completed"
9426 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9427 (set (match_dup 0) (neg:SI (match_dup 2)))])
9430 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9433 (clobber (reg:CC 17))])
9436 (neg:SI (match_dup 1)))
9437 (clobber (reg:CC 17))])]
9438 "split_di (operands+1, 1, operands+2, operands+3);
9439 split_di (operands+0, 1, operands+0, operands+1);")
9441 (define_insn "*negdi2_1_rex64"
9442 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9443 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9444 (clobber (reg:CC 17))]
9445 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9447 [(set_attr "type" "negnot")
9448 (set_attr "mode" "DI")])
9450 ;; The problem with neg is that it does not perform (compare x 0),
9451 ;; it really performs (compare 0 x), which leaves us with the zero
9452 ;; flag being the only useful item.
9454 (define_insn "*negdi2_cmpz_rex64"
9456 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9458 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9459 (neg:DI (match_dup 1)))]
9460 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9462 [(set_attr "type" "negnot")
9463 (set_attr "mode" "DI")])
9466 (define_expand "negsi2"
9467 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9468 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9469 (clobber (reg:CC 17))])]
9471 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9473 (define_insn "*negsi2_1"
9474 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9475 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9476 (clobber (reg:CC 17))]
9477 "ix86_unary_operator_ok (NEG, SImode, operands)"
9479 [(set_attr "type" "negnot")
9480 (set_attr "mode" "SI")])
9482 ;; Combine is quite creative about this pattern.
9483 (define_insn "*negsi2_1_zext"
9484 [(set (match_operand:DI 0 "register_operand" "=r")
9485 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9488 (clobber (reg:CC 17))]
9489 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9491 [(set_attr "type" "negnot")
9492 (set_attr "mode" "SI")])
9494 ;; The problem with neg is that it does not perform (compare x 0),
9495 ;; it really performs (compare 0 x), which leaves us with the zero
9496 ;; flag being the only useful item.
9498 (define_insn "*negsi2_cmpz"
9500 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9502 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9503 (neg:SI (match_dup 1)))]
9504 "ix86_unary_operator_ok (NEG, SImode, operands)"
9506 [(set_attr "type" "negnot")
9507 (set_attr "mode" "SI")])
9509 (define_insn "*negsi2_cmpz_zext"
9511 (compare:CCZ (lshiftrt:DI
9513 (match_operand:DI 1 "register_operand" "0")
9517 (set (match_operand:DI 0 "register_operand" "=r")
9518 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9521 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9523 [(set_attr "type" "negnot")
9524 (set_attr "mode" "SI")])
9526 (define_expand "neghi2"
9527 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9528 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9529 (clobber (reg:CC 17))])]
9530 "TARGET_HIMODE_MATH"
9531 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9533 (define_insn "*neghi2_1"
9534 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9535 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9536 (clobber (reg:CC 17))]
9537 "ix86_unary_operator_ok (NEG, HImode, operands)"
9539 [(set_attr "type" "negnot")
9540 (set_attr "mode" "HI")])
9542 (define_insn "*neghi2_cmpz"
9544 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9546 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9547 (neg:HI (match_dup 1)))]
9548 "ix86_unary_operator_ok (NEG, HImode, operands)"
9550 [(set_attr "type" "negnot")
9551 (set_attr "mode" "HI")])
9553 (define_expand "negqi2"
9554 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9555 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9556 (clobber (reg:CC 17))])]
9557 "TARGET_QIMODE_MATH"
9558 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9560 (define_insn "*negqi2_1"
9561 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9562 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9563 (clobber (reg:CC 17))]
9564 "ix86_unary_operator_ok (NEG, QImode, operands)"
9566 [(set_attr "type" "negnot")
9567 (set_attr "mode" "QI")])
9569 (define_insn "*negqi2_cmpz"
9571 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9573 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9574 (neg:QI (match_dup 1)))]
9575 "ix86_unary_operator_ok (NEG, QImode, operands)"
9577 [(set_attr "type" "negnot")
9578 (set_attr "mode" "QI")])
9580 ;; Changing of sign for FP values is doable using integer unit too.
9582 (define_expand "negsf2"
9583 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9584 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9585 (clobber (reg:CC 17))])]
9589 /* In case operand is in memory, we will not use SSE. */
9590 if (memory_operand (operands[0], VOIDmode)
9591 && rtx_equal_p (operands[0], operands[1]))
9592 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9595 /* Using SSE is tricky, since we need bitwise negation of -0
9597 rtx reg = gen_reg_rtx (SFmode);
9598 rtx dest = operands[0];
9599 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9601 operands[1] = force_reg (SFmode, operands[1]);
9602 operands[0] = force_reg (SFmode, operands[0]);
9603 reg = force_reg (V4SFmode,
9604 gen_rtx_CONST_VECTOR (V4SFmode,
9605 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9606 CONST0_RTX (SFmode),
9607 CONST0_RTX (SFmode))));
9608 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9609 if (dest != operands[0])
9610 emit_move_insn (dest, operands[0]);
9614 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9616 (define_insn "negsf2_memory"
9617 [(set (match_operand:SF 0 "memory_operand" "=m")
9618 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9619 (clobber (reg:CC 17))]
9620 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9623 (define_insn "negsf2_ifs"
9624 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9625 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9626 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9627 (clobber (reg:CC 17))]
9629 && (reload_in_progress || reload_completed
9630 || (register_operand (operands[0], VOIDmode)
9631 && register_operand (operands[1], VOIDmode)))"
9635 [(set (match_operand:SF 0 "memory_operand" "")
9636 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9637 (use (match_operand:SF 2 "" ""))
9638 (clobber (reg:CC 17))]
9640 [(parallel [(set (match_dup 0)
9641 (neg:SF (match_dup 1)))
9642 (clobber (reg:CC 17))])])
9645 [(set (match_operand:SF 0 "register_operand" "")
9646 (neg:SF (match_operand:SF 1 "register_operand" "")))
9647 (use (match_operand:V4SF 2 "" ""))
9648 (clobber (reg:CC 17))]
9649 "reload_completed && !SSE_REG_P (operands[0])"
9650 [(parallel [(set (match_dup 0)
9651 (neg:SF (match_dup 1)))
9652 (clobber (reg:CC 17))])])
9655 [(set (match_operand:SF 0 "register_operand" "")
9656 (neg:SF (match_operand:SF 1 "register_operand" "")))
9657 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9658 (clobber (reg:CC 17))]
9659 "reload_completed && SSE_REG_P (operands[0])"
9660 [(set (subreg:TI (match_dup 0) 0)
9661 (xor:TI (match_dup 1)
9664 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9665 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9666 if (operands_match_p (operands[0], operands[2]))
9670 operands[1] = operands[2];
9676 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9677 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9679 (define_insn "*negsf2_if"
9680 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9681 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9682 (clobber (reg:CC 17))]
9683 "TARGET_80387 && !TARGET_SSE
9684 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9688 [(set (match_operand:SF 0 "fp_register_operand" "")
9689 (neg:SF (match_operand:SF 1 "register_operand" "")))
9690 (clobber (reg:CC 17))]
9691 "TARGET_80387 && reload_completed"
9693 (neg:SF (match_dup 1)))]
9697 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9698 (neg:SF (match_operand:SF 1 "register_operand" "")))
9699 (clobber (reg:CC 17))]
9700 "TARGET_80387 && reload_completed"
9701 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9702 (clobber (reg:CC 17))])]
9703 "operands[1] = gen_int_mode (0x80000000, SImode);
9704 operands[0] = gen_lowpart (SImode, operands[0]);")
9707 [(set (match_operand 0 "memory_operand" "")
9708 (neg (match_operand 1 "memory_operand" "")))
9709 (clobber (reg:CC 17))]
9710 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9711 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9712 (clobber (reg:CC 17))])]
9714 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9716 if (GET_MODE (operands[1]) == XFmode)
9718 operands[0] = adjust_address (operands[0], QImode, size - 1);
9719 operands[1] = gen_int_mode (0x80, QImode);
9722 (define_expand "negdf2"
9723 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9724 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9725 (clobber (reg:CC 17))])]
9729 /* In case operand is in memory, we will not use SSE. */
9730 if (memory_operand (operands[0], VOIDmode)
9731 && rtx_equal_p (operands[0], operands[1]))
9732 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9735 /* Using SSE is tricky, since we need bitwise negation of -0
9738 #if HOST_BITS_PER_WIDE_INT >= 64
9739 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9741 rtx imm = immed_double_const (0, 0x80000000, DImode);
9743 rtx dest = operands[0];
9745 operands[1] = force_reg (DFmode, operands[1]);
9746 operands[0] = force_reg (DFmode, operands[0]);
9747 imm = gen_lowpart (DFmode, imm);
9748 reg = force_reg (V2DFmode,
9749 gen_rtx_CONST_VECTOR (V2DFmode,
9750 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
9751 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9752 if (dest != operands[0])
9753 emit_move_insn (dest, operands[0]);
9757 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9759 (define_insn "negdf2_memory"
9760 [(set (match_operand:DF 0 "memory_operand" "=m")
9761 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9762 (clobber (reg:CC 17))]
9763 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9766 (define_insn "negdf2_ifs"
9767 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9768 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9769 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
9770 (clobber (reg:CC 17))]
9771 "!TARGET_64BIT && TARGET_SSE2
9772 && (reload_in_progress || reload_completed
9773 || (register_operand (operands[0], VOIDmode)
9774 && register_operand (operands[1], VOIDmode)))"
9777 (define_insn "*negdf2_ifs_rex64"
9778 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
9779 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
9780 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
9781 (clobber (reg:CC 17))]
9782 "TARGET_64BIT && TARGET_SSE2
9783 && (reload_in_progress || reload_completed
9784 || (register_operand (operands[0], VOIDmode)
9785 && register_operand (operands[1], VOIDmode)))"
9789 [(set (match_operand:DF 0 "memory_operand" "")
9790 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9791 (use (match_operand:V2DF 2 "" ""))
9792 (clobber (reg:CC 17))]
9794 [(parallel [(set (match_dup 0)
9795 (neg:DF (match_dup 1)))
9796 (clobber (reg:CC 17))])])
9799 [(set (match_operand:DF 0 "register_operand" "")
9800 (neg:DF (match_operand:DF 1 "register_operand" "")))
9801 (use (match_operand:V2DF 2 "" ""))
9802 (clobber (reg:CC 17))]
9803 "reload_completed && !SSE_REG_P (operands[0])
9804 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9805 [(parallel [(set (match_dup 0)
9806 (neg:DF (match_dup 1)))
9807 (clobber (reg:CC 17))])])
9810 [(set (match_operand:DF 0 "register_operand" "")
9811 (neg:DF (match_operand:DF 1 "register_operand" "")))
9812 (use (match_operand:V2DF 2 "" ""))
9813 (clobber (reg:CC 17))]
9814 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9815 [(parallel [(set (match_dup 0)
9816 (xor:DI (match_dup 1) (match_dup 2)))
9817 (clobber (reg:CC 17))])]
9818 "operands[0] = gen_lowpart (DImode, operands[0]);
9819 operands[1] = gen_lowpart (DImode, operands[1]);
9820 operands[2] = gen_lowpart (DImode, operands[2]);")
9823 [(set (match_operand:DF 0 "register_operand" "")
9824 (neg:DF (match_operand:DF 1 "register_operand" "")))
9825 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9826 (clobber (reg:CC 17))]
9827 "reload_completed && SSE_REG_P (operands[0])"
9828 [(set (subreg:TI (match_dup 0) 0)
9829 (xor:TI (match_dup 1)
9832 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9833 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
9834 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
9835 /* Avoid possible reformatting on the operands. */
9836 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9837 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9838 if (operands_match_p (operands[0], operands[2]))
9842 operands[1] = operands[2];
9847 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9848 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9850 (define_insn "*negdf2_if"
9851 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9852 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9853 (clobber (reg:CC 17))]
9854 "!TARGET_64BIT && TARGET_80387
9855 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9858 ;; FIXME: We should to allow integer registers here. Problem is that
9859 ;; we need another scratch register to get constant from.
9860 ;; Forcing constant to mem if no register available in peep2 should be
9861 ;; safe even for PIC mode, because of RIP relative addressing.
9862 (define_insn "*negdf2_if_rex64"
9863 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9864 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9865 (clobber (reg:CC 17))]
9866 "TARGET_64BIT && TARGET_80387
9867 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9871 [(set (match_operand:DF 0 "fp_register_operand" "")
9872 (neg:DF (match_operand:DF 1 "register_operand" "")))
9873 (clobber (reg:CC 17))]
9874 "TARGET_80387 && reload_completed"
9876 (neg:DF (match_dup 1)))]
9880 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9881 (neg:DF (match_operand:DF 1 "register_operand" "")))
9882 (clobber (reg:CC 17))]
9883 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9884 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9885 (clobber (reg:CC 17))])]
9886 "operands[4] = gen_int_mode (0x80000000, SImode);
9887 split_di (operands+0, 1, operands+2, operands+3);")
9889 (define_expand "negxf2"
9890 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9891 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9892 (clobber (reg:CC 17))])]
9894 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9896 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9897 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9899 (define_insn "*negxf2_if"
9900 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9901 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9902 (clobber (reg:CC 17))]
9904 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9908 [(set (match_operand:XF 0 "fp_register_operand" "")
9909 (neg:XF (match_operand:XF 1 "register_operand" "")))
9910 (clobber (reg:CC 17))]
9911 "TARGET_80387 && reload_completed"
9913 (neg:XF (match_dup 1)))]
9917 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9918 (neg:XF (match_operand:XF 1 "register_operand" "")))
9919 (clobber (reg:CC 17))]
9920 "TARGET_80387 && reload_completed"
9921 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9922 (clobber (reg:CC 17))])]
9923 "operands[1] = GEN_INT (0x8000);
9924 operands[0] = gen_rtx_REG (SImode,
9925 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9927 ;; Conditionalize these after reload. If they matches before reload, we
9928 ;; lose the clobber and ability to use integer instructions.
9930 (define_insn "*negsf2_1"
9931 [(set (match_operand:SF 0 "register_operand" "=f")
9932 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9933 "TARGET_80387 && reload_completed"
9935 [(set_attr "type" "fsgn")
9936 (set_attr "mode" "SF")
9937 (set_attr "ppro_uops" "few")])
9939 (define_insn "*negdf2_1"
9940 [(set (match_operand:DF 0 "register_operand" "=f")
9941 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9942 "TARGET_80387 && reload_completed"
9944 [(set_attr "type" "fsgn")
9945 (set_attr "mode" "DF")
9946 (set_attr "ppro_uops" "few")])
9948 (define_insn "*negextendsfdf2"
9949 [(set (match_operand:DF 0 "register_operand" "=f")
9950 (neg:DF (float_extend:DF
9951 (match_operand:SF 1 "register_operand" "0"))))]
9954 [(set_attr "type" "fsgn")
9955 (set_attr "mode" "DF")
9956 (set_attr "ppro_uops" "few")])
9958 (define_insn "*negxf2_1"
9959 [(set (match_operand:XF 0 "register_operand" "=f")
9960 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9961 "TARGET_80387 && reload_completed"
9963 [(set_attr "type" "fsgn")
9964 (set_attr "mode" "XF")
9965 (set_attr "ppro_uops" "few")])
9967 (define_insn "*negextenddfxf2"
9968 [(set (match_operand:XF 0 "register_operand" "=f")
9969 (neg:XF (float_extend:XF
9970 (match_operand:DF 1 "register_operand" "0"))))]
9973 [(set_attr "type" "fsgn")
9974 (set_attr "mode" "XF")
9975 (set_attr "ppro_uops" "few")])
9977 (define_insn "*negextendsfxf2"
9978 [(set (match_operand:XF 0 "register_operand" "=f")
9979 (neg:XF (float_extend:XF
9980 (match_operand:SF 1 "register_operand" "0"))))]
9983 [(set_attr "type" "fsgn")
9984 (set_attr "mode" "XF")
9985 (set_attr "ppro_uops" "few")])
9987 ;; Absolute value instructions
9989 (define_expand "abssf2"
9990 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9991 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9992 (clobber (reg:CC 17))])]
9996 /* In case operand is in memory, we will not use SSE. */
9997 if (memory_operand (operands[0], VOIDmode)
9998 && rtx_equal_p (operands[0], operands[1]))
9999 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10002 /* Using SSE is tricky, since we need bitwise negation of -0
10004 rtx reg = gen_reg_rtx (V4SFmode);
10005 rtx dest = operands[0];
10008 operands[1] = force_reg (SFmode, operands[1]);
10009 operands[0] = force_reg (SFmode, operands[0]);
10010 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10011 reg = force_reg (V4SFmode,
10012 gen_rtx_CONST_VECTOR (V4SFmode,
10013 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10014 CONST0_RTX (SFmode),
10015 CONST0_RTX (SFmode))));
10016 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10017 if (dest != operands[0])
10018 emit_move_insn (dest, operands[0]);
10022 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10024 (define_insn "abssf2_memory"
10025 [(set (match_operand:SF 0 "memory_operand" "=m")
10026 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10027 (clobber (reg:CC 17))]
10028 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10031 (define_insn "abssf2_ifs"
10032 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10033 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10034 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10035 (clobber (reg:CC 17))]
10037 && (reload_in_progress || reload_completed
10038 || (register_operand (operands[0], VOIDmode)
10039 && register_operand (operands[1], VOIDmode)))"
10043 [(set (match_operand:SF 0 "memory_operand" "")
10044 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10045 (use (match_operand:V4SF 2 "" ""))
10046 (clobber (reg:CC 17))]
10048 [(parallel [(set (match_dup 0)
10049 (abs:SF (match_dup 1)))
10050 (clobber (reg:CC 17))])])
10053 [(set (match_operand:SF 0 "register_operand" "")
10054 (abs:SF (match_operand:SF 1 "register_operand" "")))
10055 (use (match_operand:V4SF 2 "" ""))
10056 (clobber (reg:CC 17))]
10057 "reload_completed && !SSE_REG_P (operands[0])"
10058 [(parallel [(set (match_dup 0)
10059 (abs:SF (match_dup 1)))
10060 (clobber (reg:CC 17))])])
10063 [(set (match_operand:SF 0 "register_operand" "")
10064 (abs:SF (match_operand:SF 1 "register_operand" "")))
10065 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10066 (clobber (reg:CC 17))]
10067 "reload_completed && SSE_REG_P (operands[0])"
10068 [(set (subreg:TI (match_dup 0) 0)
10069 (and:TI (match_dup 1)
10072 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10073 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10074 if (operands_match_p (operands[0], operands[2]))
10078 operands[1] = operands[2];
10083 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10084 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10086 (define_insn "*abssf2_if"
10087 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10088 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10089 (clobber (reg:CC 17))]
10090 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10094 [(set (match_operand:SF 0 "fp_register_operand" "")
10095 (abs:SF (match_operand:SF 1 "register_operand" "")))
10096 (clobber (reg:CC 17))]
10097 "TARGET_80387 && reload_completed"
10098 [(set (match_dup 0)
10099 (abs:SF (match_dup 1)))]
10103 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10104 (abs:SF (match_operand:SF 1 "register_operand" "")))
10105 (clobber (reg:CC 17))]
10106 "TARGET_80387 && reload_completed"
10107 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10108 (clobber (reg:CC 17))])]
10109 "operands[1] = gen_int_mode (~0x80000000, SImode);
10110 operands[0] = gen_lowpart (SImode, operands[0]);")
10113 [(set (match_operand 0 "memory_operand" "")
10114 (abs (match_operand 1 "memory_operand" "")))
10115 (clobber (reg:CC 17))]
10116 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10117 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10118 (clobber (reg:CC 17))])]
10120 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10122 if (GET_MODE (operands[1]) == XFmode)
10124 operands[0] = adjust_address (operands[0], QImode, size - 1);
10125 operands[1] = gen_int_mode (~0x80, QImode);
10128 (define_expand "absdf2"
10129 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10130 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10131 (clobber (reg:CC 17))])]
10135 /* In case operand is in memory, we will not use SSE. */
10136 if (memory_operand (operands[0], VOIDmode)
10137 && rtx_equal_p (operands[0], operands[1]))
10138 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10141 /* Using SSE is tricky, since we need bitwise negation of -0
10143 rtx reg = gen_reg_rtx (V2DFmode);
10144 #if HOST_BITS_PER_WIDE_INT >= 64
10145 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10147 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10149 rtx dest = operands[0];
10151 operands[1] = force_reg (DFmode, operands[1]);
10152 operands[0] = force_reg (DFmode, operands[0]);
10154 /* Produce LONG_DOUBLE with the proper immediate argument. */
10155 imm = gen_lowpart (DFmode, imm);
10156 reg = force_reg (V2DFmode,
10157 gen_rtx_CONST_VECTOR (V2DFmode,
10158 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10159 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10160 if (dest != operands[0])
10161 emit_move_insn (dest, operands[0]);
10165 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10167 (define_insn "absdf2_memory"
10168 [(set (match_operand:DF 0 "memory_operand" "=m")
10169 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10170 (clobber (reg:CC 17))]
10171 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10174 (define_insn "absdf2_ifs"
10175 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10176 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10177 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10178 (clobber (reg:CC 17))]
10179 "!TARGET_64BIT && TARGET_SSE2
10180 && (reload_in_progress || reload_completed
10181 || (register_operand (operands[0], VOIDmode)
10182 && register_operand (operands[1], VOIDmode)))"
10185 (define_insn "*absdf2_ifs_rex64"
10186 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10187 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10188 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10189 (clobber (reg:CC 17))]
10190 "TARGET_64BIT && TARGET_SSE2
10191 && (reload_in_progress || reload_completed
10192 || (register_operand (operands[0], VOIDmode)
10193 && register_operand (operands[1], VOIDmode)))"
10197 [(set (match_operand:DF 0 "memory_operand" "")
10198 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10199 (use (match_operand:V2DF 2 "" ""))
10200 (clobber (reg:CC 17))]
10202 [(parallel [(set (match_dup 0)
10203 (abs:DF (match_dup 1)))
10204 (clobber (reg:CC 17))])])
10207 [(set (match_operand:DF 0 "register_operand" "")
10208 (abs:DF (match_operand:DF 1 "register_operand" "")))
10209 (use (match_operand:V2DF 2 "" ""))
10210 (clobber (reg:CC 17))]
10211 "reload_completed && !SSE_REG_P (operands[0])"
10212 [(parallel [(set (match_dup 0)
10213 (abs:DF (match_dup 1)))
10214 (clobber (reg:CC 17))])])
10217 [(set (match_operand:DF 0 "register_operand" "")
10218 (abs:DF (match_operand:DF 1 "register_operand" "")))
10219 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10220 (clobber (reg:CC 17))]
10221 "reload_completed && SSE_REG_P (operands[0])"
10222 [(set (subreg:TI (match_dup 0) 0)
10223 (and:TI (match_dup 1)
10226 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10227 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10228 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10229 /* Avoid possible reformatting on the operands. */
10230 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10231 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10232 if (operands_match_p (operands[0], operands[2]))
10236 operands[1] = operands[2];
10242 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10243 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10245 (define_insn "*absdf2_if"
10246 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10247 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10248 (clobber (reg:CC 17))]
10249 "!TARGET_64BIT && TARGET_80387
10250 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10253 ;; FIXME: We should to allow integer registers here. Problem is that
10254 ;; we need another scratch register to get constant from.
10255 ;; Forcing constant to mem if no register available in peep2 should be
10256 ;; safe even for PIC mode, because of RIP relative addressing.
10257 (define_insn "*absdf2_if_rex64"
10258 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10259 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10260 (clobber (reg:CC 17))]
10261 "TARGET_64BIT && TARGET_80387
10262 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10266 [(set (match_operand:DF 0 "fp_register_operand" "")
10267 (abs:DF (match_operand:DF 1 "register_operand" "")))
10268 (clobber (reg:CC 17))]
10269 "TARGET_80387 && reload_completed"
10270 [(set (match_dup 0)
10271 (abs:DF (match_dup 1)))]
10275 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10276 (abs:DF (match_operand:DF 1 "register_operand" "")))
10277 (clobber (reg:CC 17))]
10278 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10279 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10280 (clobber (reg:CC 17))])]
10281 "operands[4] = gen_int_mode (~0x80000000, SImode);
10282 split_di (operands+0, 1, operands+2, operands+3);")
10284 (define_expand "absxf2"
10285 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10286 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10287 (clobber (reg:CC 17))])]
10289 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10291 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10292 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10294 (define_insn "*absxf2_if"
10295 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10296 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10297 (clobber (reg:CC 17))]
10299 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10303 [(set (match_operand:XF 0 "fp_register_operand" "")
10304 (abs:XF (match_operand:XF 1 "register_operand" "")))
10305 (clobber (reg:CC 17))]
10306 "TARGET_80387 && reload_completed"
10307 [(set (match_dup 0)
10308 (abs:XF (match_dup 1)))]
10312 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10313 (abs:XF (match_operand:XF 1 "register_operand" "")))
10314 (clobber (reg:CC 17))]
10315 "TARGET_80387 && reload_completed"
10316 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10317 (clobber (reg:CC 17))])]
10318 "operands[1] = GEN_INT (~0x8000);
10319 operands[0] = gen_rtx_REG (SImode,
10320 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10322 (define_insn "*abssf2_1"
10323 [(set (match_operand:SF 0 "register_operand" "=f")
10324 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10325 "TARGET_80387 && reload_completed"
10327 [(set_attr "type" "fsgn")
10328 (set_attr "mode" "SF")])
10330 (define_insn "*absdf2_1"
10331 [(set (match_operand:DF 0 "register_operand" "=f")
10332 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10333 "TARGET_80387 && reload_completed"
10335 [(set_attr "type" "fsgn")
10336 (set_attr "mode" "DF")])
10338 (define_insn "*absextendsfdf2"
10339 [(set (match_operand:DF 0 "register_operand" "=f")
10340 (abs:DF (float_extend:DF
10341 (match_operand:SF 1 "register_operand" "0"))))]
10344 [(set_attr "type" "fsgn")
10345 (set_attr "mode" "DF")])
10347 (define_insn "*absxf2_1"
10348 [(set (match_operand:XF 0 "register_operand" "=f")
10349 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10350 "TARGET_80387 && reload_completed"
10352 [(set_attr "type" "fsgn")
10353 (set_attr "mode" "DF")])
10355 (define_insn "*absextenddfxf2"
10356 [(set (match_operand:XF 0 "register_operand" "=f")
10357 (abs:XF (float_extend:XF
10358 (match_operand:DF 1 "register_operand" "0"))))]
10361 [(set_attr "type" "fsgn")
10362 (set_attr "mode" "XF")])
10364 (define_insn "*absextendsfxf2"
10365 [(set (match_operand:XF 0 "register_operand" "=f")
10366 (abs:XF (float_extend:XF
10367 (match_operand:SF 1 "register_operand" "0"))))]
10370 [(set_attr "type" "fsgn")
10371 (set_attr "mode" "XF")])
10373 ;; One complement instructions
10375 (define_expand "one_cmpldi2"
10376 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10377 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10379 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10381 (define_insn "*one_cmpldi2_1_rex64"
10382 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10383 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10384 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10386 [(set_attr "type" "negnot")
10387 (set_attr "mode" "DI")])
10389 (define_insn "*one_cmpldi2_2_rex64"
10391 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10393 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10394 (not:DI (match_dup 1)))]
10395 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10396 && ix86_unary_operator_ok (NOT, DImode, operands)"
10398 [(set_attr "type" "alu1")
10399 (set_attr "mode" "DI")])
10403 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10405 (set (match_operand:DI 0 "nonimmediate_operand" "")
10406 (not:DI (match_dup 1)))]
10407 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10408 [(parallel [(set (reg:CCNO 17)
10409 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10412 (xor:DI (match_dup 1) (const_int -1)))])]
10415 (define_expand "one_cmplsi2"
10416 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10417 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10419 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10421 (define_insn "*one_cmplsi2_1"
10422 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10423 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10424 "ix86_unary_operator_ok (NOT, SImode, operands)"
10426 [(set_attr "type" "negnot")
10427 (set_attr "mode" "SI")])
10429 ;; ??? Currently never generated - xor is used instead.
10430 (define_insn "*one_cmplsi2_1_zext"
10431 [(set (match_operand:DI 0 "register_operand" "=r")
10432 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10433 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10435 [(set_attr "type" "negnot")
10436 (set_attr "mode" "SI")])
10438 (define_insn "*one_cmplsi2_2"
10440 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10442 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10443 (not:SI (match_dup 1)))]
10444 "ix86_match_ccmode (insn, CCNOmode)
10445 && ix86_unary_operator_ok (NOT, SImode, operands)"
10447 [(set_attr "type" "alu1")
10448 (set_attr "mode" "SI")])
10452 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10454 (set (match_operand:SI 0 "nonimmediate_operand" "")
10455 (not:SI (match_dup 1)))]
10456 "ix86_match_ccmode (insn, CCNOmode)"
10457 [(parallel [(set (reg:CCNO 17)
10458 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10461 (xor:SI (match_dup 1) (const_int -1)))])]
10464 ;; ??? Currently never generated - xor is used instead.
10465 (define_insn "*one_cmplsi2_2_zext"
10467 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10469 (set (match_operand:DI 0 "register_operand" "=r")
10470 (zero_extend:DI (not:SI (match_dup 1))))]
10471 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10472 && ix86_unary_operator_ok (NOT, SImode, operands)"
10474 [(set_attr "type" "alu1")
10475 (set_attr "mode" "SI")])
10479 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10481 (set (match_operand:DI 0 "register_operand" "")
10482 (zero_extend:DI (not:SI (match_dup 1))))]
10483 "ix86_match_ccmode (insn, CCNOmode)"
10484 [(parallel [(set (reg:CCNO 17)
10485 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10488 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10491 (define_expand "one_cmplhi2"
10492 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10493 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10494 "TARGET_HIMODE_MATH"
10495 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10497 (define_insn "*one_cmplhi2_1"
10498 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10499 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10500 "ix86_unary_operator_ok (NOT, HImode, operands)"
10502 [(set_attr "type" "negnot")
10503 (set_attr "mode" "HI")])
10505 (define_insn "*one_cmplhi2_2"
10507 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10509 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10510 (not:HI (match_dup 1)))]
10511 "ix86_match_ccmode (insn, CCNOmode)
10512 && ix86_unary_operator_ok (NEG, HImode, operands)"
10514 [(set_attr "type" "alu1")
10515 (set_attr "mode" "HI")])
10519 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10521 (set (match_operand:HI 0 "nonimmediate_operand" "")
10522 (not:HI (match_dup 1)))]
10523 "ix86_match_ccmode (insn, CCNOmode)"
10524 [(parallel [(set (reg:CCNO 17)
10525 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10528 (xor:HI (match_dup 1) (const_int -1)))])]
10531 ;; %%% Potential partial reg stall on alternative 1. What to do?
10532 (define_expand "one_cmplqi2"
10533 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10534 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10535 "TARGET_QIMODE_MATH"
10536 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10538 (define_insn "*one_cmplqi2_1"
10539 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10540 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10541 "ix86_unary_operator_ok (NOT, QImode, operands)"
10545 [(set_attr "type" "negnot")
10546 (set_attr "mode" "QI,SI")])
10548 (define_insn "*one_cmplqi2_2"
10550 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10552 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10553 (not:QI (match_dup 1)))]
10554 "ix86_match_ccmode (insn, CCNOmode)
10555 && ix86_unary_operator_ok (NOT, QImode, operands)"
10557 [(set_attr "type" "alu1")
10558 (set_attr "mode" "QI")])
10562 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10564 (set (match_operand:QI 0 "nonimmediate_operand" "")
10565 (not:QI (match_dup 1)))]
10566 "ix86_match_ccmode (insn, CCNOmode)"
10567 [(parallel [(set (reg:CCNO 17)
10568 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10571 (xor:QI (match_dup 1) (const_int -1)))])]
10574 ;; Arithmetic shift instructions
10576 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10577 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10578 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10579 ;; from the assembler input.
10581 ;; This instruction shifts the target reg/mem as usual, but instead of
10582 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10583 ;; is a left shift double, bits are taken from the high order bits of
10584 ;; reg, else if the insn is a shift right double, bits are taken from the
10585 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10586 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10588 ;; Since sh[lr]d does not change the `reg' operand, that is done
10589 ;; separately, making all shifts emit pairs of shift double and normal
10590 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10591 ;; support a 63 bit shift, each shift where the count is in a reg expands
10592 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10594 ;; If the shift count is a constant, we need never emit more than one
10595 ;; shift pair, instead using moves and sign extension for counts greater
10598 (define_expand "ashldi3"
10599 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10600 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10601 (match_operand:QI 2 "nonmemory_operand" "")))
10602 (clobber (reg:CC 17))])]
10605 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10607 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10610 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10614 (define_insn "*ashldi3_1_rex64"
10615 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10616 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10617 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10618 (clobber (reg:CC 17))]
10619 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10621 switch (get_attr_type (insn))
10624 if (operands[2] != const1_rtx)
10626 if (!rtx_equal_p (operands[0], operands[1]))
10628 return "add{q}\t{%0, %0|%0, %0}";
10631 if (GET_CODE (operands[2]) != CONST_INT
10632 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10634 operands[1] = gen_rtx_MULT (DImode, operands[1],
10635 GEN_INT (1 << INTVAL (operands[2])));
10636 return "lea{q}\t{%a1, %0|%0, %a1}";
10639 if (REG_P (operands[2]))
10640 return "sal{q}\t{%b2, %0|%0, %b2}";
10641 else if (operands[2] == const1_rtx
10642 && (TARGET_SHIFT1 || optimize_size))
10643 return "sal{q}\t%0";
10645 return "sal{q}\t{%2, %0|%0, %2}";
10648 [(set (attr "type")
10649 (cond [(eq_attr "alternative" "1")
10650 (const_string "lea")
10651 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10653 (match_operand 0 "register_operand" ""))
10654 (match_operand 2 "const1_operand" ""))
10655 (const_string "alu")
10657 (const_string "ishift")))
10658 (set_attr "mode" "DI")])
10660 ;; Convert lea to the lea pattern to avoid flags dependency.
10662 [(set (match_operand:DI 0 "register_operand" "")
10663 (ashift:DI (match_operand:DI 1 "register_operand" "")
10664 (match_operand:QI 2 "immediate_operand" "")))
10665 (clobber (reg:CC 17))]
10666 "TARGET_64BIT && reload_completed
10667 && true_regnum (operands[0]) != true_regnum (operands[1])"
10668 [(set (match_dup 0)
10669 (mult:DI (match_dup 1)
10671 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10673 ;; This pattern can't accept a variable shift count, since shifts by
10674 ;; zero don't affect the flags. We assume that shifts by constant
10675 ;; zero are optimized away.
10676 (define_insn "*ashldi3_cmp_rex64"
10679 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10680 (match_operand:QI 2 "immediate_operand" "e"))
10682 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10683 (ashift:DI (match_dup 1) (match_dup 2)))]
10684 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10685 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10687 switch (get_attr_type (insn))
10690 if (operands[2] != const1_rtx)
10692 return "add{q}\t{%0, %0|%0, %0}";
10695 if (REG_P (operands[2]))
10696 return "sal{q}\t{%b2, %0|%0, %b2}";
10697 else if (operands[2] == const1_rtx
10698 && (TARGET_SHIFT1 || optimize_size))
10699 return "sal{q}\t%0";
10701 return "sal{q}\t{%2, %0|%0, %2}";
10704 [(set (attr "type")
10705 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10707 (match_operand 0 "register_operand" ""))
10708 (match_operand 2 "const1_operand" ""))
10709 (const_string "alu")
10711 (const_string "ishift")))
10712 (set_attr "mode" "DI")])
10714 (define_insn "ashldi3_1"
10715 [(set (match_operand:DI 0 "register_operand" "=r")
10716 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10717 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10718 (clobber (match_scratch:SI 3 "=&r"))
10719 (clobber (reg:CC 17))]
10720 "!TARGET_64BIT && TARGET_CMOVE"
10722 [(set_attr "type" "multi")])
10724 (define_insn "*ashldi3_2"
10725 [(set (match_operand:DI 0 "register_operand" "=r")
10726 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10727 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10728 (clobber (reg:CC 17))]
10731 [(set_attr "type" "multi")])
10734 [(set (match_operand:DI 0 "register_operand" "")
10735 (ashift:DI (match_operand:DI 1 "register_operand" "")
10736 (match_operand:QI 2 "nonmemory_operand" "")))
10737 (clobber (match_scratch:SI 3 ""))
10738 (clobber (reg:CC 17))]
10739 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10741 "ix86_split_ashldi (operands, operands[3]); DONE;")
10744 [(set (match_operand:DI 0 "register_operand" "")
10745 (ashift:DI (match_operand:DI 1 "register_operand" "")
10746 (match_operand:QI 2 "nonmemory_operand" "")))
10747 (clobber (reg:CC 17))]
10748 "!TARGET_64BIT && reload_completed"
10750 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10752 (define_insn "x86_shld_1"
10753 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10754 (ior:SI (ashift:SI (match_dup 0)
10755 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10756 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10757 (minus:QI (const_int 32) (match_dup 2)))))
10758 (clobber (reg:CC 17))]
10761 shld{l}\t{%2, %1, %0|%0, %1, %2}
10762 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10763 [(set_attr "type" "ishift")
10764 (set_attr "prefix_0f" "1")
10765 (set_attr "mode" "SI")
10766 (set_attr "pent_pair" "np")
10767 (set_attr "athlon_decode" "vector")
10768 (set_attr "ppro_uops" "few")])
10770 (define_expand "x86_shift_adj_1"
10772 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10775 (set (match_operand:SI 0 "register_operand" "")
10776 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10777 (match_operand:SI 1 "register_operand" "")
10780 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10781 (match_operand:SI 3 "register_operand" "r")
10786 (define_expand "x86_shift_adj_2"
10787 [(use (match_operand:SI 0 "register_operand" ""))
10788 (use (match_operand:SI 1 "register_operand" ""))
10789 (use (match_operand:QI 2 "register_operand" ""))]
10792 rtx label = gen_label_rtx ();
10795 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10797 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10798 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10799 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10800 gen_rtx_LABEL_REF (VOIDmode, label),
10802 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10803 JUMP_LABEL (tmp) = label;
10805 emit_move_insn (operands[0], operands[1]);
10806 emit_move_insn (operands[1], const0_rtx);
10808 emit_label (label);
10809 LABEL_NUSES (label) = 1;
10814 (define_expand "ashlsi3"
10815 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10816 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10817 (match_operand:QI 2 "nonmemory_operand" "")))
10818 (clobber (reg:CC 17))]
10820 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10822 (define_insn "*ashlsi3_1"
10823 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10824 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10825 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10826 (clobber (reg:CC 17))]
10827 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10829 switch (get_attr_type (insn))
10832 if (operands[2] != const1_rtx)
10834 if (!rtx_equal_p (operands[0], operands[1]))
10836 return "add{l}\t{%0, %0|%0, %0}";
10842 if (REG_P (operands[2]))
10843 return "sal{l}\t{%b2, %0|%0, %b2}";
10844 else if (operands[2] == const1_rtx
10845 && (TARGET_SHIFT1 || optimize_size))
10846 return "sal{l}\t%0";
10848 return "sal{l}\t{%2, %0|%0, %2}";
10851 [(set (attr "type")
10852 (cond [(eq_attr "alternative" "1")
10853 (const_string "lea")
10854 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10856 (match_operand 0 "register_operand" ""))
10857 (match_operand 2 "const1_operand" ""))
10858 (const_string "alu")
10860 (const_string "ishift")))
10861 (set_attr "mode" "SI")])
10863 ;; Convert lea to the lea pattern to avoid flags dependency.
10865 [(set (match_operand 0 "register_operand" "")
10866 (ashift (match_operand 1 "index_register_operand" "")
10867 (match_operand:QI 2 "const_int_operand" "")))
10868 (clobber (reg:CC 17))]
10870 && true_regnum (operands[0]) != true_regnum (operands[1])"
10874 operands[0] = gen_lowpart (SImode, operands[0]);
10875 operands[1] = gen_lowpart (Pmode, operands[1]);
10876 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10877 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10878 if (Pmode != SImode)
10879 pat = gen_rtx_SUBREG (SImode, pat, 0);
10880 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10884 ;; Rare case of shifting RSP is handled by generating move and shift
10886 [(set (match_operand 0 "register_operand" "")
10887 (ashift (match_operand 1 "register_operand" "")
10888 (match_operand:QI 2 "const_int_operand" "")))
10889 (clobber (reg:CC 17))]
10891 && true_regnum (operands[0]) != true_regnum (operands[1])"
10895 emit_move_insn (operands[1], operands[0]);
10896 pat = gen_rtx_SET (VOIDmode, operands[0],
10897 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10898 operands[0], operands[2]));
10899 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10900 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10904 (define_insn "*ashlsi3_1_zext"
10905 [(set (match_operand:DI 0 "register_operand" "=r,r")
10906 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10907 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10908 (clobber (reg:CC 17))]
10909 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10911 switch (get_attr_type (insn))
10914 if (operands[2] != const1_rtx)
10916 return "add{l}\t{%k0, %k0|%k0, %k0}";
10922 if (REG_P (operands[2]))
10923 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10924 else if (operands[2] == const1_rtx
10925 && (TARGET_SHIFT1 || optimize_size))
10926 return "sal{l}\t%k0";
10928 return "sal{l}\t{%2, %k0|%k0, %2}";
10931 [(set (attr "type")
10932 (cond [(eq_attr "alternative" "1")
10933 (const_string "lea")
10934 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10936 (match_operand 2 "const1_operand" ""))
10937 (const_string "alu")
10939 (const_string "ishift")))
10940 (set_attr "mode" "SI")])
10942 ;; Convert lea to the lea pattern to avoid flags dependency.
10944 [(set (match_operand:DI 0 "register_operand" "")
10945 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10946 (match_operand:QI 2 "const_int_operand" ""))))
10947 (clobber (reg:CC 17))]
10948 "TARGET_64BIT && reload_completed
10949 && true_regnum (operands[0]) != true_regnum (operands[1])"
10950 [(set (match_dup 0) (zero_extend:DI
10951 (subreg:SI (mult:SI (match_dup 1)
10952 (match_dup 2)) 0)))]
10954 operands[1] = gen_lowpart (Pmode, operands[1]);
10955 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10958 ;; This pattern can't accept a variable shift count, since shifts by
10959 ;; zero don't affect the flags. We assume that shifts by constant
10960 ;; zero are optimized away.
10961 (define_insn "*ashlsi3_cmp"
10964 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10965 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10967 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10968 (ashift:SI (match_dup 1) (match_dup 2)))]
10969 "ix86_match_ccmode (insn, CCGOCmode)
10970 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10972 switch (get_attr_type (insn))
10975 if (operands[2] != const1_rtx)
10977 return "add{l}\t{%0, %0|%0, %0}";
10980 if (REG_P (operands[2]))
10981 return "sal{l}\t{%b2, %0|%0, %b2}";
10982 else if (operands[2] == const1_rtx
10983 && (TARGET_SHIFT1 || optimize_size))
10984 return "sal{l}\t%0";
10986 return "sal{l}\t{%2, %0|%0, %2}";
10989 [(set (attr "type")
10990 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10992 (match_operand 0 "register_operand" ""))
10993 (match_operand 2 "const1_operand" ""))
10994 (const_string "alu")
10996 (const_string "ishift")))
10997 (set_attr "mode" "SI")])
10999 (define_insn "*ashlsi3_cmp_zext"
11002 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11003 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11005 (set (match_operand:DI 0 "register_operand" "=r")
11006 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11007 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11008 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11010 switch (get_attr_type (insn))
11013 if (operands[2] != const1_rtx)
11015 return "add{l}\t{%k0, %k0|%k0, %k0}";
11018 if (REG_P (operands[2]))
11019 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11020 else if (operands[2] == const1_rtx
11021 && (TARGET_SHIFT1 || optimize_size))
11022 return "sal{l}\t%k0";
11024 return "sal{l}\t{%2, %k0|%k0, %2}";
11027 [(set (attr "type")
11028 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11030 (match_operand 2 "const1_operand" ""))
11031 (const_string "alu")
11033 (const_string "ishift")))
11034 (set_attr "mode" "SI")])
11036 (define_expand "ashlhi3"
11037 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11038 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11039 (match_operand:QI 2 "nonmemory_operand" "")))
11040 (clobber (reg:CC 17))]
11041 "TARGET_HIMODE_MATH"
11042 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11044 (define_insn "*ashlhi3_1_lea"
11045 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11046 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11047 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11048 (clobber (reg:CC 17))]
11049 "!TARGET_PARTIAL_REG_STALL
11050 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11052 switch (get_attr_type (insn))
11057 if (operands[2] != const1_rtx)
11059 return "add{w}\t{%0, %0|%0, %0}";
11062 if (REG_P (operands[2]))
11063 return "sal{w}\t{%b2, %0|%0, %b2}";
11064 else if (operands[2] == const1_rtx
11065 && (TARGET_SHIFT1 || optimize_size))
11066 return "sal{w}\t%0";
11068 return "sal{w}\t{%2, %0|%0, %2}";
11071 [(set (attr "type")
11072 (cond [(eq_attr "alternative" "1")
11073 (const_string "lea")
11074 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11076 (match_operand 0 "register_operand" ""))
11077 (match_operand 2 "const1_operand" ""))
11078 (const_string "alu")
11080 (const_string "ishift")))
11081 (set_attr "mode" "HI,SI")])
11083 (define_insn "*ashlhi3_1"
11084 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11085 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11086 (match_operand:QI 2 "nonmemory_operand" "cI")))
11087 (clobber (reg:CC 17))]
11088 "TARGET_PARTIAL_REG_STALL
11089 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11091 switch (get_attr_type (insn))
11094 if (operands[2] != const1_rtx)
11096 return "add{w}\t{%0, %0|%0, %0}";
11099 if (REG_P (operands[2]))
11100 return "sal{w}\t{%b2, %0|%0, %b2}";
11101 else if (operands[2] == const1_rtx
11102 && (TARGET_SHIFT1 || optimize_size))
11103 return "sal{w}\t%0";
11105 return "sal{w}\t{%2, %0|%0, %2}";
11108 [(set (attr "type")
11109 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11111 (match_operand 0 "register_operand" ""))
11112 (match_operand 2 "const1_operand" ""))
11113 (const_string "alu")
11115 (const_string "ishift")))
11116 (set_attr "mode" "HI")])
11118 ;; This pattern can't accept a variable shift count, since shifts by
11119 ;; zero don't affect the flags. We assume that shifts by constant
11120 ;; zero are optimized away.
11121 (define_insn "*ashlhi3_cmp"
11124 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11125 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11127 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11128 (ashift:HI (match_dup 1) (match_dup 2)))]
11129 "ix86_match_ccmode (insn, CCGOCmode)
11130 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11132 switch (get_attr_type (insn))
11135 if (operands[2] != const1_rtx)
11137 return "add{w}\t{%0, %0|%0, %0}";
11140 if (REG_P (operands[2]))
11141 return "sal{w}\t{%b2, %0|%0, %b2}";
11142 else if (operands[2] == const1_rtx
11143 && (TARGET_SHIFT1 || optimize_size))
11144 return "sal{w}\t%0";
11146 return "sal{w}\t{%2, %0|%0, %2}";
11149 [(set (attr "type")
11150 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11152 (match_operand 0 "register_operand" ""))
11153 (match_operand 2 "const1_operand" ""))
11154 (const_string "alu")
11156 (const_string "ishift")))
11157 (set_attr "mode" "HI")])
11159 (define_expand "ashlqi3"
11160 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11161 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11162 (match_operand:QI 2 "nonmemory_operand" "")))
11163 (clobber (reg:CC 17))]
11164 "TARGET_QIMODE_MATH"
11165 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11167 ;; %%% Potential partial reg stall on alternative 2. What to do?
11169 (define_insn "*ashlqi3_1_lea"
11170 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11171 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11172 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11173 (clobber (reg:CC 17))]
11174 "!TARGET_PARTIAL_REG_STALL
11175 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11177 switch (get_attr_type (insn))
11182 if (operands[2] != const1_rtx)
11184 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11185 return "add{l}\t{%k0, %k0|%k0, %k0}";
11187 return "add{b}\t{%0, %0|%0, %0}";
11190 if (REG_P (operands[2]))
11192 if (get_attr_mode (insn) == MODE_SI)
11193 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11195 return "sal{b}\t{%b2, %0|%0, %b2}";
11197 else if (operands[2] == const1_rtx
11198 && (TARGET_SHIFT1 || optimize_size))
11200 if (get_attr_mode (insn) == MODE_SI)
11201 return "sal{l}\t%0";
11203 return "sal{b}\t%0";
11207 if (get_attr_mode (insn) == MODE_SI)
11208 return "sal{l}\t{%2, %k0|%k0, %2}";
11210 return "sal{b}\t{%2, %0|%0, %2}";
11214 [(set (attr "type")
11215 (cond [(eq_attr "alternative" "2")
11216 (const_string "lea")
11217 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11219 (match_operand 0 "register_operand" ""))
11220 (match_operand 2 "const1_operand" ""))
11221 (const_string "alu")
11223 (const_string "ishift")))
11224 (set_attr "mode" "QI,SI,SI")])
11226 (define_insn "*ashlqi3_1"
11227 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11228 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11229 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11230 (clobber (reg:CC 17))]
11231 "TARGET_PARTIAL_REG_STALL
11232 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11234 switch (get_attr_type (insn))
11237 if (operands[2] != const1_rtx)
11239 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11240 return "add{l}\t{%k0, %k0|%k0, %k0}";
11242 return "add{b}\t{%0, %0|%0, %0}";
11245 if (REG_P (operands[2]))
11247 if (get_attr_mode (insn) == MODE_SI)
11248 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11250 return "sal{b}\t{%b2, %0|%0, %b2}";
11252 else if (operands[2] == const1_rtx
11253 && (TARGET_SHIFT1 || optimize_size))
11255 if (get_attr_mode (insn) == MODE_SI)
11256 return "sal{l}\t%0";
11258 return "sal{b}\t%0";
11262 if (get_attr_mode (insn) == MODE_SI)
11263 return "sal{l}\t{%2, %k0|%k0, %2}";
11265 return "sal{b}\t{%2, %0|%0, %2}";
11269 [(set (attr "type")
11270 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11272 (match_operand 0 "register_operand" ""))
11273 (match_operand 2 "const1_operand" ""))
11274 (const_string "alu")
11276 (const_string "ishift")))
11277 (set_attr "mode" "QI,SI")])
11279 ;; This pattern can't accept a variable shift count, since shifts by
11280 ;; zero don't affect the flags. We assume that shifts by constant
11281 ;; zero are optimized away.
11282 (define_insn "*ashlqi3_cmp"
11285 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11286 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11288 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11289 (ashift:QI (match_dup 1) (match_dup 2)))]
11290 "ix86_match_ccmode (insn, CCGOCmode)
11291 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11293 switch (get_attr_type (insn))
11296 if (operands[2] != const1_rtx)
11298 return "add{b}\t{%0, %0|%0, %0}";
11301 if (REG_P (operands[2]))
11302 return "sal{b}\t{%b2, %0|%0, %b2}";
11303 else if (operands[2] == const1_rtx
11304 && (TARGET_SHIFT1 || optimize_size))
11305 return "sal{b}\t%0";
11307 return "sal{b}\t{%2, %0|%0, %2}";
11310 [(set (attr "type")
11311 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11313 (match_operand 0 "register_operand" ""))
11314 (match_operand 2 "const1_operand" ""))
11315 (const_string "alu")
11317 (const_string "ishift")))
11318 (set_attr "mode" "QI")])
11320 ;; See comment above `ashldi3' about how this works.
11322 (define_expand "ashrdi3"
11323 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11324 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11325 (match_operand:QI 2 "nonmemory_operand" "")))
11326 (clobber (reg:CC 17))])]
11329 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11331 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11334 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11338 (define_insn "ashrdi3_63_rex64"
11339 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11340 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11341 (match_operand:DI 2 "const_int_operand" "i,i")))
11342 (clobber (reg:CC 17))]
11343 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11344 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11347 sar{q}\t{%2, %0|%0, %2}"
11348 [(set_attr "type" "imovx,ishift")
11349 (set_attr "prefix_0f" "0,*")
11350 (set_attr "length_immediate" "0,*")
11351 (set_attr "modrm" "0,1")
11352 (set_attr "mode" "DI")])
11354 (define_insn "*ashrdi3_1_one_bit_rex64"
11355 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11356 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11357 (match_operand:QI 2 "const1_operand" "")))
11358 (clobber (reg:CC 17))]
11359 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11360 && (TARGET_SHIFT1 || optimize_size)"
11362 [(set_attr "type" "ishift")
11363 (set (attr "length")
11364 (if_then_else (match_operand:DI 0 "register_operand" "")
11366 (const_string "*")))])
11368 (define_insn "*ashrdi3_1_rex64"
11369 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11370 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11371 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11372 (clobber (reg:CC 17))]
11373 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11375 sar{q}\t{%2, %0|%0, %2}
11376 sar{q}\t{%b2, %0|%0, %b2}"
11377 [(set_attr "type" "ishift")
11378 (set_attr "mode" "DI")])
11380 ;; This pattern can't accept a variable shift count, since shifts by
11381 ;; zero don't affect the flags. We assume that shifts by constant
11382 ;; zero are optimized away.
11383 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11386 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11387 (match_operand:QI 2 "const1_operand" ""))
11389 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11390 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11391 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11392 && (TARGET_SHIFT1 || optimize_size)
11393 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11395 [(set_attr "type" "ishift")
11396 (set (attr "length")
11397 (if_then_else (match_operand:DI 0 "register_operand" "")
11399 (const_string "*")))])
11401 ;; This pattern can't accept a variable shift count, since shifts by
11402 ;; zero don't affect the flags. We assume that shifts by constant
11403 ;; zero are optimized away.
11404 (define_insn "*ashrdi3_cmp_rex64"
11407 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11408 (match_operand:QI 2 "const_int_operand" "n"))
11410 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11411 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11412 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11413 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11414 "sar{q}\t{%2, %0|%0, %2}"
11415 [(set_attr "type" "ishift")
11416 (set_attr "mode" "DI")])
11419 (define_insn "ashrdi3_1"
11420 [(set (match_operand:DI 0 "register_operand" "=r")
11421 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11422 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11423 (clobber (match_scratch:SI 3 "=&r"))
11424 (clobber (reg:CC 17))]
11425 "!TARGET_64BIT && TARGET_CMOVE"
11427 [(set_attr "type" "multi")])
11429 (define_insn "*ashrdi3_2"
11430 [(set (match_operand:DI 0 "register_operand" "=r")
11431 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11432 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11433 (clobber (reg:CC 17))]
11436 [(set_attr "type" "multi")])
11439 [(set (match_operand:DI 0 "register_operand" "")
11440 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11441 (match_operand:QI 2 "nonmemory_operand" "")))
11442 (clobber (match_scratch:SI 3 ""))
11443 (clobber (reg:CC 17))]
11444 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11446 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11449 [(set (match_operand:DI 0 "register_operand" "")
11450 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11451 (match_operand:QI 2 "nonmemory_operand" "")))
11452 (clobber (reg:CC 17))]
11453 "!TARGET_64BIT && reload_completed"
11455 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11457 (define_insn "x86_shrd_1"
11458 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11459 (ior:SI (ashiftrt:SI (match_dup 0)
11460 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11461 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11462 (minus:QI (const_int 32) (match_dup 2)))))
11463 (clobber (reg:CC 17))]
11466 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11467 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11468 [(set_attr "type" "ishift")
11469 (set_attr "prefix_0f" "1")
11470 (set_attr "pent_pair" "np")
11471 (set_attr "ppro_uops" "few")
11472 (set_attr "mode" "SI")])
11474 (define_expand "x86_shift_adj_3"
11475 [(use (match_operand:SI 0 "register_operand" ""))
11476 (use (match_operand:SI 1 "register_operand" ""))
11477 (use (match_operand:QI 2 "register_operand" ""))]
11480 rtx label = gen_label_rtx ();
11483 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11485 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11486 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11487 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11488 gen_rtx_LABEL_REF (VOIDmode, label),
11490 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11491 JUMP_LABEL (tmp) = label;
11493 emit_move_insn (operands[0], operands[1]);
11494 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11496 emit_label (label);
11497 LABEL_NUSES (label) = 1;
11502 (define_insn "ashrsi3_31"
11503 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11504 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11505 (match_operand:SI 2 "const_int_operand" "i,i")))
11506 (clobber (reg:CC 17))]
11507 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11508 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11511 sar{l}\t{%2, %0|%0, %2}"
11512 [(set_attr "type" "imovx,ishift")
11513 (set_attr "prefix_0f" "0,*")
11514 (set_attr "length_immediate" "0,*")
11515 (set_attr "modrm" "0,1")
11516 (set_attr "mode" "SI")])
11518 (define_insn "*ashrsi3_31_zext"
11519 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11520 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11521 (match_operand:SI 2 "const_int_operand" "i,i"))))
11522 (clobber (reg:CC 17))]
11523 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11524 && INTVAL (operands[2]) == 31
11525 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11528 sar{l}\t{%2, %k0|%k0, %2}"
11529 [(set_attr "type" "imovx,ishift")
11530 (set_attr "prefix_0f" "0,*")
11531 (set_attr "length_immediate" "0,*")
11532 (set_attr "modrm" "0,1")
11533 (set_attr "mode" "SI")])
11535 (define_expand "ashrsi3"
11536 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11537 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11538 (match_operand:QI 2 "nonmemory_operand" "")))
11539 (clobber (reg:CC 17))]
11541 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11543 (define_insn "*ashrsi3_1_one_bit"
11544 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11545 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11546 (match_operand:QI 2 "const1_operand" "")))
11547 (clobber (reg:CC 17))]
11548 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11549 && (TARGET_SHIFT1 || optimize_size)"
11551 [(set_attr "type" "ishift")
11552 (set (attr "length")
11553 (if_then_else (match_operand:SI 0 "register_operand" "")
11555 (const_string "*")))])
11557 (define_insn "*ashrsi3_1_one_bit_zext"
11558 [(set (match_operand:DI 0 "register_operand" "=r")
11559 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11560 (match_operand:QI 2 "const1_operand" ""))))
11561 (clobber (reg:CC 17))]
11562 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11563 && (TARGET_SHIFT1 || optimize_size)"
11565 [(set_attr "type" "ishift")
11566 (set_attr "length" "2")])
11568 (define_insn "*ashrsi3_1"
11569 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11570 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11571 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11572 (clobber (reg:CC 17))]
11573 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11575 sar{l}\t{%2, %0|%0, %2}
11576 sar{l}\t{%b2, %0|%0, %b2}"
11577 [(set_attr "type" "ishift")
11578 (set_attr "mode" "SI")])
11580 (define_insn "*ashrsi3_1_zext"
11581 [(set (match_operand:DI 0 "register_operand" "=r,r")
11582 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11583 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11584 (clobber (reg:CC 17))]
11585 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11587 sar{l}\t{%2, %k0|%k0, %2}
11588 sar{l}\t{%b2, %k0|%k0, %b2}"
11589 [(set_attr "type" "ishift")
11590 (set_attr "mode" "SI")])
11592 ;; This pattern can't accept a variable shift count, since shifts by
11593 ;; zero don't affect the flags. We assume that shifts by constant
11594 ;; zero are optimized away.
11595 (define_insn "*ashrsi3_one_bit_cmp"
11598 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11599 (match_operand:QI 2 "const1_operand" ""))
11601 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11602 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11603 "ix86_match_ccmode (insn, CCGOCmode)
11604 && (TARGET_SHIFT1 || optimize_size)
11605 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11607 [(set_attr "type" "ishift")
11608 (set (attr "length")
11609 (if_then_else (match_operand:SI 0 "register_operand" "")
11611 (const_string "*")))])
11613 (define_insn "*ashrsi3_one_bit_cmp_zext"
11616 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11617 (match_operand:QI 2 "const1_operand" ""))
11619 (set (match_operand:DI 0 "register_operand" "=r")
11620 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11621 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11622 && (TARGET_SHIFT1 || optimize_size)
11623 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11625 [(set_attr "type" "ishift")
11626 (set_attr "length" "2")])
11628 ;; This pattern can't accept a variable shift count, since shifts by
11629 ;; zero don't affect the flags. We assume that shifts by constant
11630 ;; zero are optimized away.
11631 (define_insn "*ashrsi3_cmp"
11634 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11635 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11637 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11638 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11639 "ix86_match_ccmode (insn, CCGOCmode)
11640 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11641 "sar{l}\t{%2, %0|%0, %2}"
11642 [(set_attr "type" "ishift")
11643 (set_attr "mode" "SI")])
11645 (define_insn "*ashrsi3_cmp_zext"
11648 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11649 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11651 (set (match_operand:DI 0 "register_operand" "=r")
11652 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11653 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11654 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11655 "sar{l}\t{%2, %k0|%k0, %2}"
11656 [(set_attr "type" "ishift")
11657 (set_attr "mode" "SI")])
11659 (define_expand "ashrhi3"
11660 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11661 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11662 (match_operand:QI 2 "nonmemory_operand" "")))
11663 (clobber (reg:CC 17))]
11664 "TARGET_HIMODE_MATH"
11665 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11667 (define_insn "*ashrhi3_1_one_bit"
11668 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11669 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11670 (match_operand:QI 2 "const1_operand" "")))
11671 (clobber (reg:CC 17))]
11672 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11673 && (TARGET_SHIFT1 || optimize_size)"
11675 [(set_attr "type" "ishift")
11676 (set (attr "length")
11677 (if_then_else (match_operand 0 "register_operand" "")
11679 (const_string "*")))])
11681 (define_insn "*ashrhi3_1"
11682 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11683 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11684 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11685 (clobber (reg:CC 17))]
11686 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11688 sar{w}\t{%2, %0|%0, %2}
11689 sar{w}\t{%b2, %0|%0, %b2}"
11690 [(set_attr "type" "ishift")
11691 (set_attr "mode" "HI")])
11693 ;; This pattern can't accept a variable shift count, since shifts by
11694 ;; zero don't affect the flags. We assume that shifts by constant
11695 ;; zero are optimized away.
11696 (define_insn "*ashrhi3_one_bit_cmp"
11699 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11700 (match_operand:QI 2 "const1_operand" ""))
11702 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11703 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11704 "ix86_match_ccmode (insn, CCGOCmode)
11705 && (TARGET_SHIFT1 || optimize_size)
11706 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11708 [(set_attr "type" "ishift")
11709 (set (attr "length")
11710 (if_then_else (match_operand 0 "register_operand" "")
11712 (const_string "*")))])
11714 ;; This pattern can't accept a variable shift count, since shifts by
11715 ;; zero don't affect the flags. We assume that shifts by constant
11716 ;; zero are optimized away.
11717 (define_insn "*ashrhi3_cmp"
11720 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11721 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11723 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11724 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11725 "ix86_match_ccmode (insn, CCGOCmode)
11726 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11727 "sar{w}\t{%2, %0|%0, %2}"
11728 [(set_attr "type" "ishift")
11729 (set_attr "mode" "HI")])
11731 (define_expand "ashrqi3"
11732 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11733 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11734 (match_operand:QI 2 "nonmemory_operand" "")))
11735 (clobber (reg:CC 17))]
11736 "TARGET_QIMODE_MATH"
11737 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11739 (define_insn "*ashrqi3_1_one_bit"
11740 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11741 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11742 (match_operand:QI 2 "const1_operand" "")))
11743 (clobber (reg:CC 17))]
11744 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11745 && (TARGET_SHIFT1 || optimize_size)"
11747 [(set_attr "type" "ishift")
11748 (set (attr "length")
11749 (if_then_else (match_operand 0 "register_operand" "")
11751 (const_string "*")))])
11753 (define_insn "*ashrqi3_1_one_bit_slp"
11754 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11755 (ashiftrt:QI (match_dup 0)
11756 (match_operand:QI 1 "const1_operand" "")))
11757 (clobber (reg:CC 17))]
11758 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11759 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11760 && (TARGET_SHIFT1 || optimize_size)"
11762 [(set_attr "type" "ishift1")
11763 (set (attr "length")
11764 (if_then_else (match_operand 0 "register_operand" "")
11766 (const_string "*")))])
11768 (define_insn "*ashrqi3_1"
11769 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11770 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11771 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11772 (clobber (reg:CC 17))]
11773 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11775 sar{b}\t{%2, %0|%0, %2}
11776 sar{b}\t{%b2, %0|%0, %b2}"
11777 [(set_attr "type" "ishift")
11778 (set_attr "mode" "QI")])
11780 (define_insn "*ashrqi3_1_slp"
11781 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11782 (ashiftrt:QI (match_dup 0)
11783 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11784 (clobber (reg:CC 17))]
11785 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11786 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11788 sar{b}\t{%1, %0|%0, %1}
11789 sar{b}\t{%b1, %0|%0, %b1}"
11790 [(set_attr "type" "ishift1")
11791 (set_attr "mode" "QI")])
11793 ;; This pattern can't accept a variable shift count, since shifts by
11794 ;; zero don't affect the flags. We assume that shifts by constant
11795 ;; zero are optimized away.
11796 (define_insn "*ashrqi3_one_bit_cmp"
11799 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11800 (match_operand:QI 2 "const1_operand" "I"))
11802 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11803 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11804 "ix86_match_ccmode (insn, CCGOCmode)
11805 && (TARGET_SHIFT1 || optimize_size)
11806 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11808 [(set_attr "type" "ishift")
11809 (set (attr "length")
11810 (if_then_else (match_operand 0 "register_operand" "")
11812 (const_string "*")))])
11814 ;; This pattern can't accept a variable shift count, since shifts by
11815 ;; zero don't affect the flags. We assume that shifts by constant
11816 ;; zero are optimized away.
11817 (define_insn "*ashrqi3_cmp"
11820 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11821 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11823 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11824 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11825 "ix86_match_ccmode (insn, CCGOCmode)
11826 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11827 "sar{b}\t{%2, %0|%0, %2}"
11828 [(set_attr "type" "ishift")
11829 (set_attr "mode" "QI")])
11831 ;; Logical shift instructions
11833 ;; See comment above `ashldi3' about how this works.
11835 (define_expand "lshrdi3"
11836 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11837 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11838 (match_operand:QI 2 "nonmemory_operand" "")))
11839 (clobber (reg:CC 17))])]
11842 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11844 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11847 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11851 (define_insn "*lshrdi3_1_one_bit_rex64"
11852 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11853 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11854 (match_operand:QI 2 "const1_operand" "")))
11855 (clobber (reg:CC 17))]
11856 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11857 && (TARGET_SHIFT1 || optimize_size)"
11859 [(set_attr "type" "ishift")
11860 (set (attr "length")
11861 (if_then_else (match_operand:DI 0 "register_operand" "")
11863 (const_string "*")))])
11865 (define_insn "*lshrdi3_1_rex64"
11866 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11867 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11868 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11869 (clobber (reg:CC 17))]
11870 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11872 shr{q}\t{%2, %0|%0, %2}
11873 shr{q}\t{%b2, %0|%0, %b2}"
11874 [(set_attr "type" "ishift")
11875 (set_attr "mode" "DI")])
11877 ;; This pattern can't accept a variable shift count, since shifts by
11878 ;; zero don't affect the flags. We assume that shifts by constant
11879 ;; zero are optimized away.
11880 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11883 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11884 (match_operand:QI 2 "const1_operand" ""))
11886 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11887 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11888 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11889 && (TARGET_SHIFT1 || optimize_size)
11890 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11892 [(set_attr "type" "ishift")
11893 (set (attr "length")
11894 (if_then_else (match_operand:DI 0 "register_operand" "")
11896 (const_string "*")))])
11898 ;; This pattern can't accept a variable shift count, since shifts by
11899 ;; zero don't affect the flags. We assume that shifts by constant
11900 ;; zero are optimized away.
11901 (define_insn "*lshrdi3_cmp_rex64"
11904 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11905 (match_operand:QI 2 "const_int_operand" "e"))
11907 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11908 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11909 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11910 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11911 "shr{q}\t{%2, %0|%0, %2}"
11912 [(set_attr "type" "ishift")
11913 (set_attr "mode" "DI")])
11915 (define_insn "lshrdi3_1"
11916 [(set (match_operand:DI 0 "register_operand" "=r")
11917 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11918 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11919 (clobber (match_scratch:SI 3 "=&r"))
11920 (clobber (reg:CC 17))]
11921 "!TARGET_64BIT && TARGET_CMOVE"
11923 [(set_attr "type" "multi")])
11925 (define_insn "*lshrdi3_2"
11926 [(set (match_operand:DI 0 "register_operand" "=r")
11927 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11928 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11929 (clobber (reg:CC 17))]
11932 [(set_attr "type" "multi")])
11935 [(set (match_operand:DI 0 "register_operand" "")
11936 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11937 (match_operand:QI 2 "nonmemory_operand" "")))
11938 (clobber (match_scratch:SI 3 ""))
11939 (clobber (reg:CC 17))]
11940 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11942 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11945 [(set (match_operand:DI 0 "register_operand" "")
11946 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11947 (match_operand:QI 2 "nonmemory_operand" "")))
11948 (clobber (reg:CC 17))]
11949 "!TARGET_64BIT && reload_completed"
11951 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11953 (define_expand "lshrsi3"
11954 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11955 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11956 (match_operand:QI 2 "nonmemory_operand" "")))
11957 (clobber (reg:CC 17))]
11959 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11961 (define_insn "*lshrsi3_1_one_bit"
11962 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11963 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11964 (match_operand:QI 2 "const1_operand" "")))
11965 (clobber (reg:CC 17))]
11966 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11967 && (TARGET_SHIFT1 || optimize_size)"
11969 [(set_attr "type" "ishift")
11970 (set (attr "length")
11971 (if_then_else (match_operand:SI 0 "register_operand" "")
11973 (const_string "*")))])
11975 (define_insn "*lshrsi3_1_one_bit_zext"
11976 [(set (match_operand:DI 0 "register_operand" "=r")
11977 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11978 (match_operand:QI 2 "const1_operand" "")))
11979 (clobber (reg:CC 17))]
11980 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11981 && (TARGET_SHIFT1 || optimize_size)"
11983 [(set_attr "type" "ishift")
11984 (set_attr "length" "2")])
11986 (define_insn "*lshrsi3_1"
11987 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11988 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11989 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11990 (clobber (reg:CC 17))]
11991 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11993 shr{l}\t{%2, %0|%0, %2}
11994 shr{l}\t{%b2, %0|%0, %b2}"
11995 [(set_attr "type" "ishift")
11996 (set_attr "mode" "SI")])
11998 (define_insn "*lshrsi3_1_zext"
11999 [(set (match_operand:DI 0 "register_operand" "=r,r")
12001 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12002 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12003 (clobber (reg:CC 17))]
12004 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12006 shr{l}\t{%2, %k0|%k0, %2}
12007 shr{l}\t{%b2, %k0|%k0, %b2}"
12008 [(set_attr "type" "ishift")
12009 (set_attr "mode" "SI")])
12011 ;; This pattern can't accept a variable shift count, since shifts by
12012 ;; zero don't affect the flags. We assume that shifts by constant
12013 ;; zero are optimized away.
12014 (define_insn "*lshrsi3_one_bit_cmp"
12017 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12018 (match_operand:QI 2 "const1_operand" ""))
12020 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12021 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12022 "ix86_match_ccmode (insn, CCGOCmode)
12023 && (TARGET_SHIFT1 || optimize_size)
12024 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12026 [(set_attr "type" "ishift")
12027 (set (attr "length")
12028 (if_then_else (match_operand:SI 0 "register_operand" "")
12030 (const_string "*")))])
12032 (define_insn "*lshrsi3_cmp_one_bit_zext"
12035 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12036 (match_operand:QI 2 "const1_operand" ""))
12038 (set (match_operand:DI 0 "register_operand" "=r")
12039 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12040 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12041 && (TARGET_SHIFT1 || optimize_size)
12042 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12044 [(set_attr "type" "ishift")
12045 (set_attr "length" "2")])
12047 ;; This pattern can't accept a variable shift count, since shifts by
12048 ;; zero don't affect the flags. We assume that shifts by constant
12049 ;; zero are optimized away.
12050 (define_insn "*lshrsi3_cmp"
12053 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12054 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12056 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12057 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12058 "ix86_match_ccmode (insn, CCGOCmode)
12059 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12060 "shr{l}\t{%2, %0|%0, %2}"
12061 [(set_attr "type" "ishift")
12062 (set_attr "mode" "SI")])
12064 (define_insn "*lshrsi3_cmp_zext"
12067 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12068 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12070 (set (match_operand:DI 0 "register_operand" "=r")
12071 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12072 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12073 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12074 "shr{l}\t{%2, %k0|%k0, %2}"
12075 [(set_attr "type" "ishift")
12076 (set_attr "mode" "SI")])
12078 (define_expand "lshrhi3"
12079 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12080 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12081 (match_operand:QI 2 "nonmemory_operand" "")))
12082 (clobber (reg:CC 17))]
12083 "TARGET_HIMODE_MATH"
12084 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12086 (define_insn "*lshrhi3_1_one_bit"
12087 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12088 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12089 (match_operand:QI 2 "const1_operand" "")))
12090 (clobber (reg:CC 17))]
12091 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12092 && (TARGET_SHIFT1 || optimize_size)"
12094 [(set_attr "type" "ishift")
12095 (set (attr "length")
12096 (if_then_else (match_operand 0 "register_operand" "")
12098 (const_string "*")))])
12100 (define_insn "*lshrhi3_1"
12101 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12102 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12103 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12104 (clobber (reg:CC 17))]
12105 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12107 shr{w}\t{%2, %0|%0, %2}
12108 shr{w}\t{%b2, %0|%0, %b2}"
12109 [(set_attr "type" "ishift")
12110 (set_attr "mode" "HI")])
12112 ;; This pattern can't accept a variable shift count, since shifts by
12113 ;; zero don't affect the flags. We assume that shifts by constant
12114 ;; zero are optimized away.
12115 (define_insn "*lshrhi3_one_bit_cmp"
12118 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12119 (match_operand:QI 2 "const1_operand" ""))
12121 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12122 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12123 "ix86_match_ccmode (insn, CCGOCmode)
12124 && (TARGET_SHIFT1 || optimize_size)
12125 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12127 [(set_attr "type" "ishift")
12128 (set (attr "length")
12129 (if_then_else (match_operand:SI 0 "register_operand" "")
12131 (const_string "*")))])
12133 ;; This pattern can't accept a variable shift count, since shifts by
12134 ;; zero don't affect the flags. We assume that shifts by constant
12135 ;; zero are optimized away.
12136 (define_insn "*lshrhi3_cmp"
12139 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12140 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12142 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12143 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12144 "ix86_match_ccmode (insn, CCGOCmode)
12145 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12146 "shr{w}\t{%2, %0|%0, %2}"
12147 [(set_attr "type" "ishift")
12148 (set_attr "mode" "HI")])
12150 (define_expand "lshrqi3"
12151 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12152 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12153 (match_operand:QI 2 "nonmemory_operand" "")))
12154 (clobber (reg:CC 17))]
12155 "TARGET_QIMODE_MATH"
12156 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12158 (define_insn "*lshrqi3_1_one_bit"
12159 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12160 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12161 (match_operand:QI 2 "const1_operand" "")))
12162 (clobber (reg:CC 17))]
12163 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12164 && (TARGET_SHIFT1 || optimize_size)"
12166 [(set_attr "type" "ishift")
12167 (set (attr "length")
12168 (if_then_else (match_operand 0 "register_operand" "")
12170 (const_string "*")))])
12172 (define_insn "*lshrqi3_1_one_bit_slp"
12173 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12174 (lshiftrt:QI (match_dup 0)
12175 (match_operand:QI 1 "const1_operand" "")))
12176 (clobber (reg:CC 17))]
12177 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12178 && (TARGET_SHIFT1 || optimize_size)"
12180 [(set_attr "type" "ishift1")
12181 (set (attr "length")
12182 (if_then_else (match_operand 0 "register_operand" "")
12184 (const_string "*")))])
12186 (define_insn "*lshrqi3_1"
12187 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12188 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12189 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12190 (clobber (reg:CC 17))]
12191 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12193 shr{b}\t{%2, %0|%0, %2}
12194 shr{b}\t{%b2, %0|%0, %b2}"
12195 [(set_attr "type" "ishift")
12196 (set_attr "mode" "QI")])
12198 (define_insn "*lshrqi3_1_slp"
12199 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12200 (lshiftrt:QI (match_dup 0)
12201 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12202 (clobber (reg:CC 17))]
12203 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12204 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12206 shr{b}\t{%1, %0|%0, %1}
12207 shr{b}\t{%b1, %0|%0, %b1}"
12208 [(set_attr "type" "ishift1")
12209 (set_attr "mode" "QI")])
12211 ;; This pattern can't accept a variable shift count, since shifts by
12212 ;; zero don't affect the flags. We assume that shifts by constant
12213 ;; zero are optimized away.
12214 (define_insn "*lshrqi2_one_bit_cmp"
12217 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12218 (match_operand:QI 2 "const1_operand" ""))
12220 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12221 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12222 "ix86_match_ccmode (insn, CCGOCmode)
12223 && (TARGET_SHIFT1 || optimize_size)
12224 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12226 [(set_attr "type" "ishift")
12227 (set (attr "length")
12228 (if_then_else (match_operand:SI 0 "register_operand" "")
12230 (const_string "*")))])
12232 ;; This pattern can't accept a variable shift count, since shifts by
12233 ;; zero don't affect the flags. We assume that shifts by constant
12234 ;; zero are optimized away.
12235 (define_insn "*lshrqi2_cmp"
12238 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12239 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12241 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12242 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12243 "ix86_match_ccmode (insn, CCGOCmode)
12244 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12245 "shr{b}\t{%2, %0|%0, %2}"
12246 [(set_attr "type" "ishift")
12247 (set_attr "mode" "QI")])
12249 ;; Rotate instructions
12251 (define_expand "rotldi3"
12252 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12253 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12254 (match_operand:QI 2 "nonmemory_operand" "")))
12255 (clobber (reg:CC 17))]
12257 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12259 (define_insn "*rotlsi3_1_one_bit_rex64"
12260 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12261 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12262 (match_operand:QI 2 "const1_operand" "")))
12263 (clobber (reg:CC 17))]
12264 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12265 && (TARGET_SHIFT1 || optimize_size)"
12267 [(set_attr "type" "rotate")
12268 (set (attr "length")
12269 (if_then_else (match_operand:DI 0 "register_operand" "")
12271 (const_string "*")))])
12273 (define_insn "*rotldi3_1_rex64"
12274 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12275 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12276 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12277 (clobber (reg:CC 17))]
12278 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12280 rol{q}\t{%2, %0|%0, %2}
12281 rol{q}\t{%b2, %0|%0, %b2}"
12282 [(set_attr "type" "rotate")
12283 (set_attr "mode" "DI")])
12285 (define_expand "rotlsi3"
12286 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12287 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12288 (match_operand:QI 2 "nonmemory_operand" "")))
12289 (clobber (reg:CC 17))]
12291 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12293 (define_insn "*rotlsi3_1_one_bit"
12294 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12295 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12296 (match_operand:QI 2 "const1_operand" "")))
12297 (clobber (reg:CC 17))]
12298 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12299 && (TARGET_SHIFT1 || optimize_size)"
12301 [(set_attr "type" "rotate")
12302 (set (attr "length")
12303 (if_then_else (match_operand:SI 0 "register_operand" "")
12305 (const_string "*")))])
12307 (define_insn "*rotlsi3_1_one_bit_zext"
12308 [(set (match_operand:DI 0 "register_operand" "=r")
12310 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12311 (match_operand:QI 2 "const1_operand" ""))))
12312 (clobber (reg:CC 17))]
12313 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12314 && (TARGET_SHIFT1 || optimize_size)"
12316 [(set_attr "type" "rotate")
12317 (set_attr "length" "2")])
12319 (define_insn "*rotlsi3_1"
12320 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12321 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12322 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12323 (clobber (reg:CC 17))]
12324 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12326 rol{l}\t{%2, %0|%0, %2}
12327 rol{l}\t{%b2, %0|%0, %b2}"
12328 [(set_attr "type" "rotate")
12329 (set_attr "mode" "SI")])
12331 (define_insn "*rotlsi3_1_zext"
12332 [(set (match_operand:DI 0 "register_operand" "=r,r")
12334 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12335 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12336 (clobber (reg:CC 17))]
12337 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12339 rol{l}\t{%2, %k0|%k0, %2}
12340 rol{l}\t{%b2, %k0|%k0, %b2}"
12341 [(set_attr "type" "rotate")
12342 (set_attr "mode" "SI")])
12344 (define_expand "rotlhi3"
12345 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12346 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12347 (match_operand:QI 2 "nonmemory_operand" "")))
12348 (clobber (reg:CC 17))]
12349 "TARGET_HIMODE_MATH"
12350 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12352 (define_insn "*rotlhi3_1_one_bit"
12353 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12354 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12355 (match_operand:QI 2 "const1_operand" "")))
12356 (clobber (reg:CC 17))]
12357 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12358 && (TARGET_SHIFT1 || optimize_size)"
12360 [(set_attr "type" "rotate")
12361 (set (attr "length")
12362 (if_then_else (match_operand 0 "register_operand" "")
12364 (const_string "*")))])
12366 (define_insn "*rotlhi3_1"
12367 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12368 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12369 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12370 (clobber (reg:CC 17))]
12371 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12373 rol{w}\t{%2, %0|%0, %2}
12374 rol{w}\t{%b2, %0|%0, %b2}"
12375 [(set_attr "type" "rotate")
12376 (set_attr "mode" "HI")])
12378 (define_expand "rotlqi3"
12379 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12380 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12381 (match_operand:QI 2 "nonmemory_operand" "")))
12382 (clobber (reg:CC 17))]
12383 "TARGET_QIMODE_MATH"
12384 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12386 (define_insn "*rotlqi3_1_one_bit_slp"
12387 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12388 (rotate:QI (match_dup 0)
12389 (match_operand:QI 1 "const1_operand" "")))
12390 (clobber (reg:CC 17))]
12391 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12392 && (TARGET_SHIFT1 || optimize_size)"
12394 [(set_attr "type" "rotate1")
12395 (set (attr "length")
12396 (if_then_else (match_operand 0 "register_operand" "")
12398 (const_string "*")))])
12400 (define_insn "*rotlqi3_1_one_bit"
12401 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12402 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12403 (match_operand:QI 2 "const1_operand" "")))
12404 (clobber (reg:CC 17))]
12405 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12406 && (TARGET_SHIFT1 || optimize_size)"
12408 [(set_attr "type" "rotate")
12409 (set (attr "length")
12410 (if_then_else (match_operand 0 "register_operand" "")
12412 (const_string "*")))])
12414 (define_insn "*rotlqi3_1_slp"
12415 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12416 (rotate:QI (match_dup 0)
12417 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12418 (clobber (reg:CC 17))]
12419 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12420 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12422 rol{b}\t{%1, %0|%0, %1}
12423 rol{b}\t{%b1, %0|%0, %b1}"
12424 [(set_attr "type" "rotate1")
12425 (set_attr "mode" "QI")])
12427 (define_insn "*rotlqi3_1"
12428 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12429 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12430 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12431 (clobber (reg:CC 17))]
12432 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12434 rol{b}\t{%2, %0|%0, %2}
12435 rol{b}\t{%b2, %0|%0, %b2}"
12436 [(set_attr "type" "rotate")
12437 (set_attr "mode" "QI")])
12439 (define_expand "rotrdi3"
12440 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12441 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12442 (match_operand:QI 2 "nonmemory_operand" "")))
12443 (clobber (reg:CC 17))]
12445 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12447 (define_insn "*rotrdi3_1_one_bit_rex64"
12448 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12449 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12450 (match_operand:QI 2 "const1_operand" "")))
12451 (clobber (reg:CC 17))]
12452 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12453 && (TARGET_SHIFT1 || optimize_size)"
12455 [(set_attr "type" "rotate")
12456 (set (attr "length")
12457 (if_then_else (match_operand:DI 0 "register_operand" "")
12459 (const_string "*")))])
12461 (define_insn "*rotrdi3_1_rex64"
12462 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12463 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12464 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12465 (clobber (reg:CC 17))]
12466 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12468 ror{q}\t{%2, %0|%0, %2}
12469 ror{q}\t{%b2, %0|%0, %b2}"
12470 [(set_attr "type" "rotate")
12471 (set_attr "mode" "DI")])
12473 (define_expand "rotrsi3"
12474 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12475 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12476 (match_operand:QI 2 "nonmemory_operand" "")))
12477 (clobber (reg:CC 17))]
12479 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12481 (define_insn "*rotrsi3_1_one_bit"
12482 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12483 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12484 (match_operand:QI 2 "const1_operand" "")))
12485 (clobber (reg:CC 17))]
12486 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12487 && (TARGET_SHIFT1 || optimize_size)"
12489 [(set_attr "type" "rotate")
12490 (set (attr "length")
12491 (if_then_else (match_operand:SI 0 "register_operand" "")
12493 (const_string "*")))])
12495 (define_insn "*rotrsi3_1_one_bit_zext"
12496 [(set (match_operand:DI 0 "register_operand" "=r")
12498 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12499 (match_operand:QI 2 "const1_operand" ""))))
12500 (clobber (reg:CC 17))]
12501 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12502 && (TARGET_SHIFT1 || optimize_size)"
12504 [(set_attr "type" "rotate")
12505 (set (attr "length")
12506 (if_then_else (match_operand:SI 0 "register_operand" "")
12508 (const_string "*")))])
12510 (define_insn "*rotrsi3_1"
12511 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12512 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12513 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12514 (clobber (reg:CC 17))]
12515 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12517 ror{l}\t{%2, %0|%0, %2}
12518 ror{l}\t{%b2, %0|%0, %b2}"
12519 [(set_attr "type" "rotate")
12520 (set_attr "mode" "SI")])
12522 (define_insn "*rotrsi3_1_zext"
12523 [(set (match_operand:DI 0 "register_operand" "=r,r")
12525 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12526 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12527 (clobber (reg:CC 17))]
12528 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12530 ror{l}\t{%2, %k0|%k0, %2}
12531 ror{l}\t{%b2, %k0|%k0, %b2}"
12532 [(set_attr "type" "rotate")
12533 (set_attr "mode" "SI")])
12535 (define_expand "rotrhi3"
12536 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12537 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12538 (match_operand:QI 2 "nonmemory_operand" "")))
12539 (clobber (reg:CC 17))]
12540 "TARGET_HIMODE_MATH"
12541 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12543 (define_insn "*rotrhi3_one_bit"
12544 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12545 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12546 (match_operand:QI 2 "const1_operand" "")))
12547 (clobber (reg:CC 17))]
12548 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12549 && (TARGET_SHIFT1 || optimize_size)"
12551 [(set_attr "type" "rotate")
12552 (set (attr "length")
12553 (if_then_else (match_operand 0 "register_operand" "")
12555 (const_string "*")))])
12557 (define_insn "*rotrhi3"
12558 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12559 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12560 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12561 (clobber (reg:CC 17))]
12562 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12564 ror{w}\t{%2, %0|%0, %2}
12565 ror{w}\t{%b2, %0|%0, %b2}"
12566 [(set_attr "type" "rotate")
12567 (set_attr "mode" "HI")])
12569 (define_expand "rotrqi3"
12570 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12571 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12572 (match_operand:QI 2 "nonmemory_operand" "")))
12573 (clobber (reg:CC 17))]
12574 "TARGET_QIMODE_MATH"
12575 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12577 (define_insn "*rotrqi3_1_one_bit"
12578 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12579 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12580 (match_operand:QI 2 "const1_operand" "")))
12581 (clobber (reg:CC 17))]
12582 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12583 && (TARGET_SHIFT1 || optimize_size)"
12585 [(set_attr "type" "rotate")
12586 (set (attr "length")
12587 (if_then_else (match_operand 0 "register_operand" "")
12589 (const_string "*")))])
12591 (define_insn "*rotrqi3_1_one_bit_slp"
12592 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12593 (rotatert:QI (match_dup 0)
12594 (match_operand:QI 1 "const1_operand" "")))
12595 (clobber (reg:CC 17))]
12596 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12597 && (TARGET_SHIFT1 || optimize_size)"
12599 [(set_attr "type" "rotate1")
12600 (set (attr "length")
12601 (if_then_else (match_operand 0 "register_operand" "")
12603 (const_string "*")))])
12605 (define_insn "*rotrqi3_1"
12606 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12607 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12608 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12609 (clobber (reg:CC 17))]
12610 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12612 ror{b}\t{%2, %0|%0, %2}
12613 ror{b}\t{%b2, %0|%0, %b2}"
12614 [(set_attr "type" "rotate")
12615 (set_attr "mode" "QI")])
12617 (define_insn "*rotrqi3_1_slp"
12618 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12619 (rotatert:QI (match_dup 0)
12620 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12621 (clobber (reg:CC 17))]
12622 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12623 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12625 ror{b}\t{%1, %0|%0, %1}
12626 ror{b}\t{%b1, %0|%0, %b1}"
12627 [(set_attr "type" "rotate1")
12628 (set_attr "mode" "QI")])
12630 ;; Bit set / bit test instructions
12632 (define_expand "extv"
12633 [(set (match_operand:SI 0 "register_operand" "")
12634 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12635 (match_operand:SI 2 "immediate_operand" "")
12636 (match_operand:SI 3 "immediate_operand" "")))]
12639 /* Handle extractions from %ah et al. */
12640 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12643 /* From mips.md: extract_bit_field doesn't verify that our source
12644 matches the predicate, so check it again here. */
12645 if (! register_operand (operands[1], VOIDmode))
12649 (define_expand "extzv"
12650 [(set (match_operand:SI 0 "register_operand" "")
12651 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12652 (match_operand:SI 2 "immediate_operand" "")
12653 (match_operand:SI 3 "immediate_operand" "")))]
12656 /* Handle extractions from %ah et al. */
12657 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12660 /* From mips.md: extract_bit_field doesn't verify that our source
12661 matches the predicate, so check it again here. */
12662 if (! register_operand (operands[1], VOIDmode))
12666 (define_expand "insv"
12667 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12668 (match_operand:SI 1 "immediate_operand" "")
12669 (match_operand:SI 2 "immediate_operand" ""))
12670 (match_operand:SI 3 "register_operand" ""))]
12673 /* Handle extractions from %ah et al. */
12674 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12677 /* From mips.md: insert_bit_field doesn't verify that our source
12678 matches the predicate, so check it again here. */
12679 if (! register_operand (operands[0], VOIDmode))
12683 ;; %%% bts, btr, btc, bt.
12685 ;; Store-flag instructions.
12687 ;; For all sCOND expanders, also expand the compare or test insn that
12688 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12690 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12691 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12692 ;; way, which can later delete the movzx if only QImode is needed.
12694 (define_expand "seq"
12695 [(set (match_operand:QI 0 "register_operand" "")
12696 (eq:QI (reg:CC 17) (const_int 0)))]
12698 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12700 (define_expand "sne"
12701 [(set (match_operand:QI 0 "register_operand" "")
12702 (ne:QI (reg:CC 17) (const_int 0)))]
12704 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12706 (define_expand "sgt"
12707 [(set (match_operand:QI 0 "register_operand" "")
12708 (gt:QI (reg:CC 17) (const_int 0)))]
12710 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12712 (define_expand "sgtu"
12713 [(set (match_operand:QI 0 "register_operand" "")
12714 (gtu:QI (reg:CC 17) (const_int 0)))]
12716 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12718 (define_expand "slt"
12719 [(set (match_operand:QI 0 "register_operand" "")
12720 (lt:QI (reg:CC 17) (const_int 0)))]
12722 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12724 (define_expand "sltu"
12725 [(set (match_operand:QI 0 "register_operand" "")
12726 (ltu:QI (reg:CC 17) (const_int 0)))]
12728 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12730 (define_expand "sge"
12731 [(set (match_operand:QI 0 "register_operand" "")
12732 (ge:QI (reg:CC 17) (const_int 0)))]
12734 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12736 (define_expand "sgeu"
12737 [(set (match_operand:QI 0 "register_operand" "")
12738 (geu:QI (reg:CC 17) (const_int 0)))]
12740 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12742 (define_expand "sle"
12743 [(set (match_operand:QI 0 "register_operand" "")
12744 (le:QI (reg:CC 17) (const_int 0)))]
12746 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12748 (define_expand "sleu"
12749 [(set (match_operand:QI 0 "register_operand" "")
12750 (leu:QI (reg:CC 17) (const_int 0)))]
12752 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12754 (define_expand "sunordered"
12755 [(set (match_operand:QI 0 "register_operand" "")
12756 (unordered:QI (reg:CC 17) (const_int 0)))]
12757 "TARGET_80387 || TARGET_SSE"
12758 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12760 (define_expand "sordered"
12761 [(set (match_operand:QI 0 "register_operand" "")
12762 (ordered:QI (reg:CC 17) (const_int 0)))]
12764 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12766 (define_expand "suneq"
12767 [(set (match_operand:QI 0 "register_operand" "")
12768 (uneq:QI (reg:CC 17) (const_int 0)))]
12769 "TARGET_80387 || TARGET_SSE"
12770 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12772 (define_expand "sunge"
12773 [(set (match_operand:QI 0 "register_operand" "")
12774 (unge:QI (reg:CC 17) (const_int 0)))]
12775 "TARGET_80387 || TARGET_SSE"
12776 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12778 (define_expand "sungt"
12779 [(set (match_operand:QI 0 "register_operand" "")
12780 (ungt:QI (reg:CC 17) (const_int 0)))]
12781 "TARGET_80387 || TARGET_SSE"
12782 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12784 (define_expand "sunle"
12785 [(set (match_operand:QI 0 "register_operand" "")
12786 (unle:QI (reg:CC 17) (const_int 0)))]
12787 "TARGET_80387 || TARGET_SSE"
12788 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12790 (define_expand "sunlt"
12791 [(set (match_operand:QI 0 "register_operand" "")
12792 (unlt:QI (reg:CC 17) (const_int 0)))]
12793 "TARGET_80387 || TARGET_SSE"
12794 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12796 (define_expand "sltgt"
12797 [(set (match_operand:QI 0 "register_operand" "")
12798 (ltgt:QI (reg:CC 17) (const_int 0)))]
12799 "TARGET_80387 || TARGET_SSE"
12800 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12802 (define_insn "*setcc_1"
12803 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12804 (match_operator:QI 1 "ix86_comparison_operator"
12805 [(reg 17) (const_int 0)]))]
12808 [(set_attr "type" "setcc")
12809 (set_attr "mode" "QI")])
12811 (define_insn "setcc_2"
12812 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12813 (match_operator:QI 1 "ix86_comparison_operator"
12814 [(reg 17) (const_int 0)]))]
12817 [(set_attr "type" "setcc")
12818 (set_attr "mode" "QI")])
12820 ;; In general it is not safe to assume too much about CCmode registers,
12821 ;; so simplify-rtx stops when it sees a second one. Under certain
12822 ;; conditions this is safe on x86, so help combine not create
12829 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12830 (ne:QI (match_operator 1 "ix86_comparison_operator"
12831 [(reg 17) (const_int 0)])
12834 [(set (match_dup 0) (match_dup 1))]
12836 PUT_MODE (operands[1], QImode);
12840 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12841 (ne:QI (match_operator 1 "ix86_comparison_operator"
12842 [(reg 17) (const_int 0)])
12845 [(set (match_dup 0) (match_dup 1))]
12847 PUT_MODE (operands[1], QImode);
12851 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12852 (eq:QI (match_operator 1 "ix86_comparison_operator"
12853 [(reg 17) (const_int 0)])
12856 [(set (match_dup 0) (match_dup 1))]
12858 rtx new_op1 = copy_rtx (operands[1]);
12859 operands[1] = new_op1;
12860 PUT_MODE (new_op1, QImode);
12861 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12862 GET_MODE (XEXP (new_op1, 0))));
12864 /* Make sure that (a) the CCmode we have for the flags is strong
12865 enough for the reversed compare or (b) we have a valid FP compare. */
12866 if (! ix86_comparison_operator (new_op1, VOIDmode))
12871 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12872 (eq:QI (match_operator 1 "ix86_comparison_operator"
12873 [(reg 17) (const_int 0)])
12876 [(set (match_dup 0) (match_dup 1))]
12878 rtx new_op1 = copy_rtx (operands[1]);
12879 operands[1] = new_op1;
12880 PUT_MODE (new_op1, QImode);
12881 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12882 GET_MODE (XEXP (new_op1, 0))));
12884 /* Make sure that (a) the CCmode we have for the flags is strong
12885 enough for the reversed compare or (b) we have a valid FP compare. */
12886 if (! ix86_comparison_operator (new_op1, VOIDmode))
12890 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12891 ;; subsequent logical operations are used to imitate conditional moves.
12892 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12893 ;; it directly. Further holding this value in pseudo register might bring
12894 ;; problem in implicit normalization in spill code.
12895 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12896 ;; instructions after reload by splitting the conditional move patterns.
12898 (define_insn "*sse_setccsf"
12899 [(set (match_operand:SF 0 "register_operand" "=x")
12900 (match_operator:SF 1 "sse_comparison_operator"
12901 [(match_operand:SF 2 "register_operand" "0")
12902 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12903 "TARGET_SSE && reload_completed"
12904 "cmp%D1ss\t{%3, %0|%0, %3}"
12905 [(set_attr "type" "ssecmp")
12906 (set_attr "mode" "SF")])
12908 (define_insn "*sse_setccdf"
12909 [(set (match_operand:DF 0 "register_operand" "=Y")
12910 (match_operator:DF 1 "sse_comparison_operator"
12911 [(match_operand:DF 2 "register_operand" "0")
12912 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12913 "TARGET_SSE2 && reload_completed"
12914 "cmp%D1sd\t{%3, %0|%0, %3}"
12915 [(set_attr "type" "ssecmp")
12916 (set_attr "mode" "DF")])
12918 ;; Basic conditional jump instructions.
12919 ;; We ignore the overflow flag for signed branch instructions.
12921 ;; For all bCOND expanders, also expand the compare or test insn that
12922 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12924 (define_expand "beq"
12926 (if_then_else (match_dup 1)
12927 (label_ref (match_operand 0 "" ""))
12930 "ix86_expand_branch (EQ, operands[0]); DONE;")
12932 (define_expand "bne"
12934 (if_then_else (match_dup 1)
12935 (label_ref (match_operand 0 "" ""))
12938 "ix86_expand_branch (NE, operands[0]); DONE;")
12940 (define_expand "bgt"
12942 (if_then_else (match_dup 1)
12943 (label_ref (match_operand 0 "" ""))
12946 "ix86_expand_branch (GT, operands[0]); DONE;")
12948 (define_expand "bgtu"
12950 (if_then_else (match_dup 1)
12951 (label_ref (match_operand 0 "" ""))
12954 "ix86_expand_branch (GTU, operands[0]); DONE;")
12956 (define_expand "blt"
12958 (if_then_else (match_dup 1)
12959 (label_ref (match_operand 0 "" ""))
12962 "ix86_expand_branch (LT, operands[0]); DONE;")
12964 (define_expand "bltu"
12966 (if_then_else (match_dup 1)
12967 (label_ref (match_operand 0 "" ""))
12970 "ix86_expand_branch (LTU, operands[0]); DONE;")
12972 (define_expand "bge"
12974 (if_then_else (match_dup 1)
12975 (label_ref (match_operand 0 "" ""))
12978 "ix86_expand_branch (GE, operands[0]); DONE;")
12980 (define_expand "bgeu"
12982 (if_then_else (match_dup 1)
12983 (label_ref (match_operand 0 "" ""))
12986 "ix86_expand_branch (GEU, operands[0]); DONE;")
12988 (define_expand "ble"
12990 (if_then_else (match_dup 1)
12991 (label_ref (match_operand 0 "" ""))
12994 "ix86_expand_branch (LE, operands[0]); DONE;")
12996 (define_expand "bleu"
12998 (if_then_else (match_dup 1)
12999 (label_ref (match_operand 0 "" ""))
13002 "ix86_expand_branch (LEU, operands[0]); DONE;")
13004 (define_expand "bunordered"
13006 (if_then_else (match_dup 1)
13007 (label_ref (match_operand 0 "" ""))
13009 "TARGET_80387 || TARGET_SSE"
13010 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13012 (define_expand "bordered"
13014 (if_then_else (match_dup 1)
13015 (label_ref (match_operand 0 "" ""))
13017 "TARGET_80387 || TARGET_SSE"
13018 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13020 (define_expand "buneq"
13022 (if_then_else (match_dup 1)
13023 (label_ref (match_operand 0 "" ""))
13025 "TARGET_80387 || TARGET_SSE"
13026 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13028 (define_expand "bunge"
13030 (if_then_else (match_dup 1)
13031 (label_ref (match_operand 0 "" ""))
13033 "TARGET_80387 || TARGET_SSE"
13034 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13036 (define_expand "bungt"
13038 (if_then_else (match_dup 1)
13039 (label_ref (match_operand 0 "" ""))
13041 "TARGET_80387 || TARGET_SSE"
13042 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13044 (define_expand "bunle"
13046 (if_then_else (match_dup 1)
13047 (label_ref (match_operand 0 "" ""))
13049 "TARGET_80387 || TARGET_SSE"
13050 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13052 (define_expand "bunlt"
13054 (if_then_else (match_dup 1)
13055 (label_ref (match_operand 0 "" ""))
13057 "TARGET_80387 || TARGET_SSE"
13058 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13060 (define_expand "bltgt"
13062 (if_then_else (match_dup 1)
13063 (label_ref (match_operand 0 "" ""))
13065 "TARGET_80387 || TARGET_SSE"
13066 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13068 (define_insn "*jcc_1"
13070 (if_then_else (match_operator 1 "ix86_comparison_operator"
13071 [(reg 17) (const_int 0)])
13072 (label_ref (match_operand 0 "" ""))
13076 [(set_attr "type" "ibr")
13077 (set_attr "modrm" "0")
13078 (set (attr "length")
13079 (if_then_else (and (ge (minus (match_dup 0) (pc))
13081 (lt (minus (match_dup 0) (pc))
13086 (define_insn "*jcc_2"
13088 (if_then_else (match_operator 1 "ix86_comparison_operator"
13089 [(reg 17) (const_int 0)])
13091 (label_ref (match_operand 0 "" ""))))]
13094 [(set_attr "type" "ibr")
13095 (set_attr "modrm" "0")
13096 (set (attr "length")
13097 (if_then_else (and (ge (minus (match_dup 0) (pc))
13099 (lt (minus (match_dup 0) (pc))
13104 ;; In general it is not safe to assume too much about CCmode registers,
13105 ;; so simplify-rtx stops when it sees a second one. Under certain
13106 ;; conditions this is safe on x86, so help combine not create
13114 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13115 [(reg 17) (const_int 0)])
13117 (label_ref (match_operand 1 "" ""))
13121 (if_then_else (match_dup 0)
13122 (label_ref (match_dup 1))
13125 PUT_MODE (operands[0], VOIDmode);
13130 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13131 [(reg 17) (const_int 0)])
13133 (label_ref (match_operand 1 "" ""))
13137 (if_then_else (match_dup 0)
13138 (label_ref (match_dup 1))
13141 rtx new_op0 = copy_rtx (operands[0]);
13142 operands[0] = new_op0;
13143 PUT_MODE (new_op0, VOIDmode);
13144 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13145 GET_MODE (XEXP (new_op0, 0))));
13147 /* Make sure that (a) the CCmode we have for the flags is strong
13148 enough for the reversed compare or (b) we have a valid FP compare. */
13149 if (! ix86_comparison_operator (new_op0, VOIDmode))
13153 ;; Define combination compare-and-branch fp compare instructions to use
13154 ;; during early optimization. Splitting the operation apart early makes
13155 ;; for bad code when we want to reverse the operation.
13157 (define_insn "*fp_jcc_1"
13159 (if_then_else (match_operator 0 "comparison_operator"
13160 [(match_operand 1 "register_operand" "f")
13161 (match_operand 2 "register_operand" "f")])
13162 (label_ref (match_operand 3 "" ""))
13164 (clobber (reg:CCFP 18))
13165 (clobber (reg:CCFP 17))]
13166 "TARGET_CMOVE && TARGET_80387
13167 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13168 && FLOAT_MODE_P (GET_MODE (operands[1]))
13169 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13170 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13173 (define_insn "*fp_jcc_1_sse"
13175 (if_then_else (match_operator 0 "comparison_operator"
13176 [(match_operand 1 "register_operand" "f#x,x#f")
13177 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13178 (label_ref (match_operand 3 "" ""))
13180 (clobber (reg:CCFP 18))
13181 (clobber (reg:CCFP 17))]
13183 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13184 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13185 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13188 (define_insn "*fp_jcc_1_sse_only"
13190 (if_then_else (match_operator 0 "comparison_operator"
13191 [(match_operand 1 "register_operand" "x")
13192 (match_operand 2 "nonimmediate_operand" "xm")])
13193 (label_ref (match_operand 3 "" ""))
13195 (clobber (reg:CCFP 18))
13196 (clobber (reg:CCFP 17))]
13197 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13198 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13199 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13202 (define_insn "*fp_jcc_2"
13204 (if_then_else (match_operator 0 "comparison_operator"
13205 [(match_operand 1 "register_operand" "f")
13206 (match_operand 2 "register_operand" "f")])
13208 (label_ref (match_operand 3 "" ""))))
13209 (clobber (reg:CCFP 18))
13210 (clobber (reg:CCFP 17))]
13211 "TARGET_CMOVE && TARGET_80387
13212 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13213 && FLOAT_MODE_P (GET_MODE (operands[1]))
13214 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13215 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13218 (define_insn "*fp_jcc_2_sse"
13220 (if_then_else (match_operator 0 "comparison_operator"
13221 [(match_operand 1 "register_operand" "f#x,x#f")
13222 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13224 (label_ref (match_operand 3 "" ""))))
13225 (clobber (reg:CCFP 18))
13226 (clobber (reg:CCFP 17))]
13228 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13229 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13230 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13233 (define_insn "*fp_jcc_2_sse_only"
13235 (if_then_else (match_operator 0 "comparison_operator"
13236 [(match_operand 1 "register_operand" "x")
13237 (match_operand 2 "nonimmediate_operand" "xm")])
13239 (label_ref (match_operand 3 "" ""))))
13240 (clobber (reg:CCFP 18))
13241 (clobber (reg:CCFP 17))]
13242 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13243 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13244 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13247 (define_insn "*fp_jcc_3"
13249 (if_then_else (match_operator 0 "comparison_operator"
13250 [(match_operand 1 "register_operand" "f")
13251 (match_operand 2 "nonimmediate_operand" "fm")])
13252 (label_ref (match_operand 3 "" ""))
13254 (clobber (reg:CCFP 18))
13255 (clobber (reg:CCFP 17))
13256 (clobber (match_scratch:HI 4 "=a"))]
13258 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13259 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13260 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13261 && SELECT_CC_MODE (GET_CODE (operands[0]),
13262 operands[1], operands[2]) == CCFPmode
13263 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13266 (define_insn "*fp_jcc_4"
13268 (if_then_else (match_operator 0 "comparison_operator"
13269 [(match_operand 1 "register_operand" "f")
13270 (match_operand 2 "nonimmediate_operand" "fm")])
13272 (label_ref (match_operand 3 "" ""))))
13273 (clobber (reg:CCFP 18))
13274 (clobber (reg:CCFP 17))
13275 (clobber (match_scratch:HI 4 "=a"))]
13277 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13278 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13279 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13280 && SELECT_CC_MODE (GET_CODE (operands[0]),
13281 operands[1], operands[2]) == CCFPmode
13282 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13285 (define_insn "*fp_jcc_5"
13287 (if_then_else (match_operator 0 "comparison_operator"
13288 [(match_operand 1 "register_operand" "f")
13289 (match_operand 2 "register_operand" "f")])
13290 (label_ref (match_operand 3 "" ""))
13292 (clobber (reg:CCFP 18))
13293 (clobber (reg:CCFP 17))
13294 (clobber (match_scratch:HI 4 "=a"))]
13296 && FLOAT_MODE_P (GET_MODE (operands[1]))
13297 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13298 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13301 (define_insn "*fp_jcc_6"
13303 (if_then_else (match_operator 0 "comparison_operator"
13304 [(match_operand 1 "register_operand" "f")
13305 (match_operand 2 "register_operand" "f")])
13307 (label_ref (match_operand 3 "" ""))))
13308 (clobber (reg:CCFP 18))
13309 (clobber (reg:CCFP 17))
13310 (clobber (match_scratch:HI 4 "=a"))]
13312 && FLOAT_MODE_P (GET_MODE (operands[1]))
13313 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13314 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13319 (if_then_else (match_operator 0 "comparison_operator"
13320 [(match_operand 1 "register_operand" "")
13321 (match_operand 2 "nonimmediate_operand" "")])
13322 (match_operand 3 "" "")
13323 (match_operand 4 "" "")))
13324 (clobber (reg:CCFP 18))
13325 (clobber (reg:CCFP 17))]
13329 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13330 operands[3], operands[4], NULL_RTX);
13336 (if_then_else (match_operator 0 "comparison_operator"
13337 [(match_operand 1 "register_operand" "")
13338 (match_operand 2 "nonimmediate_operand" "")])
13339 (match_operand 3 "" "")
13340 (match_operand 4 "" "")))
13341 (clobber (reg:CCFP 18))
13342 (clobber (reg:CCFP 17))
13343 (clobber (match_scratch:HI 5 "=a"))]
13346 (if_then_else (match_dup 6)
13350 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13351 operands[3], operands[4], operands[5]);
13355 ;; Unconditional and other jump instructions
13357 (define_insn "jump"
13359 (label_ref (match_operand 0 "" "")))]
13362 [(set_attr "type" "ibr")
13363 (set (attr "length")
13364 (if_then_else (and (ge (minus (match_dup 0) (pc))
13366 (lt (minus (match_dup 0) (pc))
13370 (set_attr "modrm" "0")])
13372 (define_expand "indirect_jump"
13373 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13377 (define_insn "*indirect_jump"
13378 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13381 [(set_attr "type" "ibr")
13382 (set_attr "length_immediate" "0")])
13384 (define_insn "*indirect_jump_rtx64"
13385 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13388 [(set_attr "type" "ibr")
13389 (set_attr "length_immediate" "0")])
13391 (define_expand "tablejump"
13392 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13393 (use (label_ref (match_operand 1 "" "")))])]
13396 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13397 relative. Convert the relative address to an absolute address. */
13401 enum rtx_code code;
13407 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13409 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13413 op1 = pic_offset_table_rtx;
13418 op0 = pic_offset_table_rtx;
13422 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13427 (define_insn "*tablejump_1"
13428 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13429 (use (label_ref (match_operand 1 "" "")))]
13432 [(set_attr "type" "ibr")
13433 (set_attr "length_immediate" "0")])
13435 (define_insn "*tablejump_1_rtx64"
13436 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13437 (use (label_ref (match_operand 1 "" "")))]
13440 [(set_attr "type" "ibr")
13441 (set_attr "length_immediate" "0")])
13443 ;; Loop instruction
13445 ;; This is all complicated by the fact that since this is a jump insn
13446 ;; we must handle our own reloads.
13448 (define_expand "doloop_end"
13449 [(use (match_operand 0 "" "")) ; loop pseudo
13450 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13451 (use (match_operand 2 "" "")) ; max iterations
13452 (use (match_operand 3 "" "")) ; loop level
13453 (use (match_operand 4 "" ""))] ; label
13454 "!TARGET_64BIT && TARGET_USE_LOOP"
13457 /* Only use cloop on innermost loops. */
13458 if (INTVAL (operands[3]) > 1)
13460 if (GET_MODE (operands[0]) != SImode)
13462 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13467 (define_insn "doloop_end_internal"
13469 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13471 (label_ref (match_operand 0 "" ""))
13473 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13474 (plus:SI (match_dup 1)
13476 (clobber (match_scratch:SI 3 "=X,X,r"))
13477 (clobber (reg:CC 17))]
13478 "!TARGET_64BIT && TARGET_USE_LOOP"
13480 if (which_alternative != 0)
13482 if (get_attr_length (insn) == 2)
13483 return "%+loop\t%l0";
13485 return "dec{l}\t%1\;%+jne\t%l0";
13487 [(set_attr "ppro_uops" "many")
13488 (set (attr "length")
13489 (if_then_else (and (eq_attr "alternative" "0")
13490 (and (ge (minus (match_dup 0) (pc))
13492 (lt (minus (match_dup 0) (pc))
13496 ;; We don't know the type before shorten branches. Optimistically expect
13497 ;; the loop instruction to match.
13498 (set (attr "type") (const_string "ibr"))])
13502 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13504 (match_operand 0 "" "")
13507 (plus:SI (match_dup 1)
13509 (clobber (match_scratch:SI 2 ""))
13510 (clobber (reg:CC 17))]
13511 "!TARGET_64BIT && TARGET_USE_LOOP
13512 && reload_completed
13513 && REGNO (operands[1]) != 2"
13514 [(parallel [(set (reg:CCZ 17)
13515 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13517 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13518 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13525 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13527 (match_operand 0 "" "")
13529 (set (match_operand:SI 2 "nonimmediate_operand" "")
13530 (plus:SI (match_dup 1)
13532 (clobber (match_scratch:SI 3 ""))
13533 (clobber (reg:CC 17))]
13534 "!TARGET_64BIT && TARGET_USE_LOOP
13535 && reload_completed
13536 && (! REG_P (operands[2])
13537 || ! rtx_equal_p (operands[1], operands[2]))"
13538 [(set (match_dup 3) (match_dup 1))
13539 (parallel [(set (reg:CCZ 17)
13540 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13542 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13543 (set (match_dup 2) (match_dup 3))
13544 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13549 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13552 [(set (reg 17) (match_operand 0 "" ""))
13553 (set (match_operand:QI 1 "register_operand" "")
13554 (match_operator:QI 2 "ix86_comparison_operator"
13555 [(reg 17) (const_int 0)]))
13556 (set (match_operand 3 "q_regs_operand" "")
13557 (zero_extend (match_dup 1)))]
13558 "(peep2_reg_dead_p (3, operands[1])
13559 || operands_match_p (operands[1], operands[3]))
13560 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13561 [(set (match_dup 4) (match_dup 0))
13562 (set (strict_low_part (match_dup 5))
13565 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13566 operands[5] = gen_lowpart (QImode, operands[3]);
13567 ix86_expand_clear (operands[3]);
13570 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13573 [(set (reg 17) (match_operand 0 "" ""))
13574 (set (match_operand:QI 1 "register_operand" "")
13575 (match_operator:QI 2 "ix86_comparison_operator"
13576 [(reg 17) (const_int 0)]))
13577 (parallel [(set (match_operand 3 "q_regs_operand" "")
13578 (zero_extend (match_dup 1)))
13579 (clobber (reg:CC 17))])]
13580 "(peep2_reg_dead_p (3, operands[1])
13581 || operands_match_p (operands[1], operands[3]))
13582 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13583 [(set (match_dup 4) (match_dup 0))
13584 (set (strict_low_part (match_dup 5))
13587 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13588 operands[5] = gen_lowpart (QImode, operands[3]);
13589 ix86_expand_clear (operands[3]);
13592 ;; Call instructions.
13594 ;; The predicates normally associated with named expanders are not properly
13595 ;; checked for calls. This is a bug in the generic code, but it isn't that
13596 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13598 ;; Call subroutine returning no value.
13600 (define_expand "call_pop"
13601 [(parallel [(call (match_operand:QI 0 "" "")
13602 (match_operand:SI 1 "" ""))
13604 (plus:SI (reg:SI 7)
13605 (match_operand:SI 3 "" "")))])]
13608 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13612 (define_insn "*call_pop_0"
13613 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13614 (match_operand:SI 1 "" ""))
13615 (set (reg:SI 7) (plus:SI (reg:SI 7)
13616 (match_operand:SI 2 "immediate_operand" "")))]
13619 if (SIBLING_CALL_P (insn))
13622 return "call\t%P0";
13624 [(set_attr "type" "call")])
13626 (define_insn "*call_pop_1"
13627 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13628 (match_operand:SI 1 "" ""))
13629 (set (reg:SI 7) (plus:SI (reg:SI 7)
13630 (match_operand:SI 2 "immediate_operand" "i")))]
13633 if (constant_call_address_operand (operands[0], Pmode))
13635 if (SIBLING_CALL_P (insn))
13638 return "call\t%P0";
13640 if (SIBLING_CALL_P (insn))
13643 return "call\t%A0";
13645 [(set_attr "type" "call")])
13647 (define_expand "call"
13648 [(call (match_operand:QI 0 "" "")
13649 (match_operand 1 "" ""))
13650 (use (match_operand 2 "" ""))]
13653 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13657 (define_expand "sibcall"
13658 [(call (match_operand:QI 0 "" "")
13659 (match_operand 1 "" ""))
13660 (use (match_operand 2 "" ""))]
13663 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13667 (define_insn "*call_0"
13668 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13669 (match_operand 1 "" ""))]
13672 if (SIBLING_CALL_P (insn))
13675 return "call\t%P0";
13677 [(set_attr "type" "call")])
13679 (define_insn "*call_1"
13680 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13681 (match_operand 1 "" ""))]
13682 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13684 if (constant_call_address_operand (operands[0], QImode))
13685 return "call\t%P0";
13686 return "call\t%A0";
13688 [(set_attr "type" "call")])
13690 (define_insn "*sibcall_1"
13691 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13692 (match_operand 1 "" ""))]
13693 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13695 if (constant_call_address_operand (operands[0], QImode))
13699 [(set_attr "type" "call")])
13701 (define_insn "*call_1_rex64"
13702 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13703 (match_operand 1 "" ""))]
13704 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13706 if (constant_call_address_operand (operands[0], QImode))
13707 return "call\t%P0";
13708 return "call\t%A0";
13710 [(set_attr "type" "call")])
13712 (define_insn "*sibcall_1_rex64"
13713 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13714 (match_operand 1 "" ""))]
13715 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13717 [(set_attr "type" "call")])
13719 (define_insn "*sibcall_1_rex64_v"
13720 [(call (mem:QI (reg:DI 40))
13721 (match_operand 0 "" ""))]
13722 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13724 [(set_attr "type" "call")])
13727 ;; Call subroutine, returning value in operand 0
13729 (define_expand "call_value_pop"
13730 [(parallel [(set (match_operand 0 "" "")
13731 (call (match_operand:QI 1 "" "")
13732 (match_operand:SI 2 "" "")))
13734 (plus:SI (reg:SI 7)
13735 (match_operand:SI 4 "" "")))])]
13738 ix86_expand_call (operands[0], operands[1], operands[2],
13739 operands[3], operands[4], 0);
13743 (define_expand "call_value"
13744 [(set (match_operand 0 "" "")
13745 (call (match_operand:QI 1 "" "")
13746 (match_operand:SI 2 "" "")))
13747 (use (match_operand:SI 3 "" ""))]
13748 ;; Operand 2 not used on the i386.
13751 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13755 (define_expand "sibcall_value"
13756 [(set (match_operand 0 "" "")
13757 (call (match_operand:QI 1 "" "")
13758 (match_operand:SI 2 "" "")))
13759 (use (match_operand:SI 3 "" ""))]
13760 ;; Operand 2 not used on the i386.
13763 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13767 ;; Call subroutine returning any type.
13769 (define_expand "untyped_call"
13770 [(parallel [(call (match_operand 0 "" "")
13772 (match_operand 1 "" "")
13773 (match_operand 2 "" "")])]
13778 /* In order to give reg-stack an easier job in validating two
13779 coprocessor registers as containing a possible return value,
13780 simply pretend the untyped call returns a complex long double
13783 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13784 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13785 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13788 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13790 rtx set = XVECEXP (operands[2], 0, i);
13791 emit_move_insn (SET_DEST (set), SET_SRC (set));
13794 /* The optimizer does not know that the call sets the function value
13795 registers we stored in the result block. We avoid problems by
13796 claiming that all hard registers are used and clobbered at this
13798 emit_insn (gen_blockage (const0_rtx));
13803 ;; Prologue and epilogue instructions
13805 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13806 ;; all of memory. This blocks insns from being moved across this point.
13808 (define_insn "blockage"
13809 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13812 [(set_attr "length" "0")])
13814 ;; Insn emitted into the body of a function to return from a function.
13815 ;; This is only done if the function's epilogue is known to be simple.
13816 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13818 (define_expand "return"
13820 "ix86_can_use_return_insn_p ()"
13822 if (current_function_pops_args)
13824 rtx popc = GEN_INT (current_function_pops_args);
13825 emit_jump_insn (gen_return_pop_internal (popc));
13830 (define_insn "return_internal"
13834 [(set_attr "length" "1")
13835 (set_attr "length_immediate" "0")
13836 (set_attr "modrm" "0")])
13838 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13839 ;; instruction Athlon and K8 have.
13841 (define_insn "return_internal_long"
13843 (unspec [(const_int 0)] UNSPEC_REP)]
13846 [(set_attr "length" "1")
13847 (set_attr "length_immediate" "0")
13848 (set_attr "prefix_rep" "1")
13849 (set_attr "modrm" "0")])
13851 (define_insn "return_pop_internal"
13853 (use (match_operand:SI 0 "const_int_operand" ""))]
13856 [(set_attr "length" "3")
13857 (set_attr "length_immediate" "2")
13858 (set_attr "modrm" "0")])
13860 (define_insn "return_indirect_internal"
13862 (use (match_operand:SI 0 "register_operand" "r"))]
13865 [(set_attr "type" "ibr")
13866 (set_attr "length_immediate" "0")])
13872 [(set_attr "length" "1")
13873 (set_attr "length_immediate" "0")
13874 (set_attr "modrm" "0")
13875 (set_attr "ppro_uops" "one")])
13877 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13878 ;; branch prediction penalty for the third jump in a 16-byte
13881 (define_insn "align"
13882 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13885 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13886 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13888 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13889 The align insn is used to avoid 3 jump instructions in the row to improve
13890 branch prediction and the benefits hardly outweight the cost of extra 8
13891 nops on the average inserted by full alignment pseudo operation. */
13895 [(set_attr "length" "16")])
13897 (define_expand "prologue"
13900 "ix86_expand_prologue (); DONE;")
13902 (define_insn "set_got"
13903 [(set (match_operand:SI 0 "register_operand" "=r")
13904 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13905 (clobber (reg:CC 17))]
13907 { return output_set_got (operands[0]); }
13908 [(set_attr "type" "multi")
13909 (set_attr "length" "12")])
13911 (define_expand "epilogue"
13914 "ix86_expand_epilogue (1); DONE;")
13916 (define_expand "sibcall_epilogue"
13919 "ix86_expand_epilogue (0); DONE;")
13921 (define_expand "eh_return"
13922 [(use (match_operand 0 "register_operand" ""))]
13925 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13927 /* Tricky bit: we write the address of the handler to which we will
13928 be returning into someone else's stack frame, one word below the
13929 stack address we wish to restore. */
13930 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13931 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13932 tmp = gen_rtx_MEM (Pmode, tmp);
13933 emit_move_insn (tmp, ra);
13935 if (Pmode == SImode)
13936 emit_insn (gen_eh_return_si (sa));
13938 emit_insn (gen_eh_return_di (sa));
13943 (define_insn_and_split "eh_return_si"
13944 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
13945 UNSPECV_EH_RETURN)]
13950 "ix86_expand_epilogue (2); DONE;")
13952 (define_insn_and_split "eh_return_di"
13953 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
13954 UNSPECV_EH_RETURN)]
13959 "ix86_expand_epilogue (2); DONE;")
13961 (define_insn "leave"
13962 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
13963 (set (reg:SI 6) (mem:SI (reg:SI 6)))
13964 (clobber (mem:BLK (scratch)))]
13967 [(set_attr "type" "leave")])
13969 (define_insn "leave_rex64"
13970 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
13971 (set (reg:DI 6) (mem:DI (reg:DI 6)))
13972 (clobber (mem:BLK (scratch)))]
13975 [(set_attr "type" "leave")])
13977 (define_expand "ffssi2"
13979 [(set (match_operand:SI 0 "register_operand" "")
13980 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13981 (clobber (match_scratch:SI 2 ""))
13982 (clobber (reg:CC 17))])]
13986 (define_insn_and_split "*ffs_cmove"
13987 [(set (match_operand:SI 0 "register_operand" "=r")
13988 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13989 (clobber (match_scratch:SI 2 "=&r"))
13990 (clobber (reg:CC 17))]
13993 "&& reload_completed"
13994 [(set (match_dup 2) (const_int -1))
13995 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
13996 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13997 (set (match_dup 0) (if_then_else:SI
13998 (eq (reg:CCZ 17) (const_int 0))
14001 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14002 (clobber (reg:CC 17))])]
14005 (define_insn_and_split "*ffs_no_cmove"
14006 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14007 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14008 (clobber (match_scratch:SI 2 "=&q"))
14009 (clobber (reg:CC 17))]
14013 [(parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14014 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14015 (set (strict_low_part (match_dup 3))
14016 (eq:QI (reg:CCZ 17) (const_int 0)))
14017 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14018 (clobber (reg:CC 17))])
14019 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14020 (clobber (reg:CC 17))])
14021 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14022 (clobber (reg:CC 17))])]
14024 operands[3] = gen_lowpart (QImode, operands[2]);
14025 ix86_expand_clear (operands[2]);
14028 (define_insn "*ffssi_1"
14030 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14032 (set (match_operand:SI 0 "register_operand" "=r")
14033 (ctz:SI (match_dup 1)))]
14035 "bsf{l}\t{%1, %0|%0, %1}"
14036 [(set_attr "prefix_0f" "1")
14037 (set_attr "ppro_uops" "few")])
14039 (define_insn "ctzsi2"
14040 [(set (match_operand:SI 0 "register_operand" "=r")
14041 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14042 (clobber (reg:CC 17))]
14044 "bsf{l}\t{%1, %0|%0, %1}"
14045 [(set_attr "prefix_0f" "1")
14046 (set_attr "ppro_uops" "few")])
14048 (define_expand "clzsi2"
14050 [(set (match_operand:SI 0 "register_operand" "")
14051 (minus:SI (const_int 31)
14052 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14053 (clobber (reg:CC 17))])
14055 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14056 (clobber (reg:CC 17))])]
14060 (define_insn "*bsr"
14061 [(set (match_operand:SI 0 "register_operand" "=r")
14062 (minus:SI (const_int 31)
14063 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14064 (clobber (reg:CC 17))]
14066 "bsr{l}\t{%1, %0|%0, %1}"
14067 [(set_attr "prefix_0f" "1")
14068 (set_attr "ppro_uops" "few")])
14070 ;; Thread-local storage patterns for ELF.
14072 ;; Note that these code sequences must appear exactly as shown
14073 ;; in order to allow linker relaxation.
14075 (define_insn "*tls_global_dynamic_32_gnu"
14076 [(set (match_operand:SI 0 "register_operand" "=a")
14077 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14078 (match_operand:SI 2 "tls_symbolic_operand" "")
14079 (match_operand:SI 3 "call_insn_operand" "")]
14081 (clobber (match_scratch:SI 4 "=d"))
14082 (clobber (match_scratch:SI 5 "=c"))
14083 (clobber (reg:CC 17))]
14084 "!TARGET_64BIT && TARGET_GNU_TLS"
14085 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14086 [(set_attr "type" "multi")
14087 (set_attr "length" "12")])
14089 (define_insn "*tls_global_dynamic_32_sun"
14090 [(set (match_operand:SI 0 "register_operand" "=a")
14091 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14092 (match_operand:SI 2 "tls_symbolic_operand" "")
14093 (match_operand:SI 3 "call_insn_operand" "")]
14095 (clobber (match_scratch:SI 4 "=d"))
14096 (clobber (match_scratch:SI 5 "=c"))
14097 (clobber (reg:CC 17))]
14098 "!TARGET_64BIT && TARGET_SUN_TLS"
14099 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14100 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14101 [(set_attr "type" "multi")
14102 (set_attr "length" "14")])
14104 (define_expand "tls_global_dynamic_32"
14105 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14108 (match_operand:SI 1 "tls_symbolic_operand" "")
14111 (clobber (match_scratch:SI 4 ""))
14112 (clobber (match_scratch:SI 5 ""))
14113 (clobber (reg:CC 17))])]
14117 operands[2] = pic_offset_table_rtx;
14120 operands[2] = gen_reg_rtx (Pmode);
14121 emit_insn (gen_set_got (operands[2]));
14123 operands[3] = ix86_tls_get_addr ();
14126 (define_insn "*tls_global_dynamic_64"
14127 [(set (match_operand:DI 0 "register_operand" "=a")
14128 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14129 (match_operand:DI 3 "" "")))
14130 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14133 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14134 [(set_attr "type" "multi")
14135 (set_attr "length" "16")])
14137 (define_expand "tls_global_dynamic_64"
14138 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14139 (call (mem:QI (match_dup 2)) (const_int 0)))
14140 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14144 operands[2] = ix86_tls_get_addr ();
14147 (define_insn "*tls_local_dynamic_base_32_gnu"
14148 [(set (match_operand:SI 0 "register_operand" "=a")
14149 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14150 (match_operand:SI 2 "call_insn_operand" "")]
14151 UNSPEC_TLS_LD_BASE))
14152 (clobber (match_scratch:SI 3 "=d"))
14153 (clobber (match_scratch:SI 4 "=c"))
14154 (clobber (reg:CC 17))]
14155 "!TARGET_64BIT && TARGET_GNU_TLS"
14156 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14157 [(set_attr "type" "multi")
14158 (set_attr "length" "11")])
14160 (define_insn "*tls_local_dynamic_base_32_sun"
14161 [(set (match_operand:SI 0 "register_operand" "=a")
14162 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14163 (match_operand:SI 2 "call_insn_operand" "")]
14164 UNSPEC_TLS_LD_BASE))
14165 (clobber (match_scratch:SI 3 "=d"))
14166 (clobber (match_scratch:SI 4 "=c"))
14167 (clobber (reg:CC 17))]
14168 "!TARGET_64BIT && TARGET_SUN_TLS"
14169 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14170 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14171 [(set_attr "type" "multi")
14172 (set_attr "length" "13")])
14174 (define_expand "tls_local_dynamic_base_32"
14175 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14176 (unspec:SI [(match_dup 1) (match_dup 2)]
14177 UNSPEC_TLS_LD_BASE))
14178 (clobber (match_scratch:SI 3 ""))
14179 (clobber (match_scratch:SI 4 ""))
14180 (clobber (reg:CC 17))])]
14184 operands[1] = pic_offset_table_rtx;
14187 operands[1] = gen_reg_rtx (Pmode);
14188 emit_insn (gen_set_got (operands[1]));
14190 operands[2] = ix86_tls_get_addr ();
14193 (define_insn "*tls_local_dynamic_base_64"
14194 [(set (match_operand:DI 0 "register_operand" "=a")
14195 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14196 (match_operand:DI 2 "" "")))
14197 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14199 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14200 [(set_attr "type" "multi")
14201 (set_attr "length" "12")])
14203 (define_expand "tls_local_dynamic_base_64"
14204 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14205 (call (mem:QI (match_dup 1)) (const_int 0)))
14206 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14209 operands[1] = ix86_tls_get_addr ();
14212 ;; Local dynamic of a single variable is a lose. Show combine how
14213 ;; to convert that back to global dynamic.
14215 (define_insn_and_split "*tls_local_dynamic_32_once"
14216 [(set (match_operand:SI 0 "register_operand" "=a")
14217 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14218 (match_operand:SI 2 "call_insn_operand" "")]
14219 UNSPEC_TLS_LD_BASE)
14220 (const:SI (unspec:SI
14221 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14223 (clobber (match_scratch:SI 4 "=d"))
14224 (clobber (match_scratch:SI 5 "=c"))
14225 (clobber (reg:CC 17))]
14229 [(parallel [(set (match_dup 0)
14230 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14232 (clobber (match_dup 4))
14233 (clobber (match_dup 5))
14234 (clobber (reg:CC 17))])]
14237 ;; Load and add the thread base pointer from %gs:0.
14239 (define_insn "*load_tp_si"
14240 [(set (match_operand:SI 0 "register_operand" "=r")
14241 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14243 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14244 [(set_attr "type" "imov")
14245 (set_attr "modrm" "0")
14246 (set_attr "length" "7")
14247 (set_attr "memory" "load")
14248 (set_attr "imm_disp" "false")])
14250 (define_insn "*add_tp_si"
14251 [(set (match_operand:SI 0 "register_operand" "=r")
14252 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14253 (match_operand:SI 1 "register_operand" "0")))
14254 (clobber (reg:CC 17))]
14256 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14257 [(set_attr "type" "alu")
14258 (set_attr "modrm" "0")
14259 (set_attr "length" "7")
14260 (set_attr "memory" "load")
14261 (set_attr "imm_disp" "false")])
14263 (define_insn "*load_tp_di"
14264 [(set (match_operand:DI 0 "register_operand" "=r")
14265 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14267 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14268 [(set_attr "type" "imov")
14269 (set_attr "modrm" "0")
14270 (set_attr "length" "7")
14271 (set_attr "memory" "load")
14272 (set_attr "imm_disp" "false")])
14274 (define_insn "*add_tp_di"
14275 [(set (match_operand:DI 0 "register_operand" "=r")
14276 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14277 (match_operand:DI 1 "register_operand" "0")))
14278 (clobber (reg:CC 17))]
14280 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14281 [(set_attr "type" "alu")
14282 (set_attr "modrm" "0")
14283 (set_attr "length" "7")
14284 (set_attr "memory" "load")
14285 (set_attr "imm_disp" "false")])
14287 ;; These patterns match the binary 387 instructions for addM3, subM3,
14288 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14289 ;; SFmode. The first is the normal insn, the second the same insn but
14290 ;; with one operand a conversion, and the third the same insn but with
14291 ;; the other operand a conversion. The conversion may be SFmode or
14292 ;; SImode if the target mode DFmode, but only SImode if the target mode
14295 ;; Gcc is slightly more smart about handling normal two address instructions
14296 ;; so use special patterns for add and mull.
14297 (define_insn "*fop_sf_comm_nosse"
14298 [(set (match_operand:SF 0 "register_operand" "=f")
14299 (match_operator:SF 3 "binary_fp_operator"
14300 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14301 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14302 "TARGET_80387 && !TARGET_SSE_MATH
14303 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14304 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14305 "* return output_387_binary_op (insn, operands);"
14306 [(set (attr "type")
14307 (if_then_else (match_operand:SF 3 "mult_operator" "")
14308 (const_string "fmul")
14309 (const_string "fop")))
14310 (set_attr "mode" "SF")])
14312 (define_insn "*fop_sf_comm"
14313 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14314 (match_operator:SF 3 "binary_fp_operator"
14315 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14316 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14317 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14318 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14319 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14320 "* return output_387_binary_op (insn, operands);"
14321 [(set (attr "type")
14322 (if_then_else (eq_attr "alternative" "1")
14323 (if_then_else (match_operand:SF 3 "mult_operator" "")
14324 (const_string "ssemul")
14325 (const_string "sseadd"))
14326 (if_then_else (match_operand:SF 3 "mult_operator" "")
14327 (const_string "fmul")
14328 (const_string "fop"))))
14329 (set_attr "mode" "SF")])
14331 (define_insn "*fop_sf_comm_sse"
14332 [(set (match_operand:SF 0 "register_operand" "=x")
14333 (match_operator:SF 3 "binary_fp_operator"
14334 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14335 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14336 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14337 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14338 "* return output_387_binary_op (insn, operands);"
14339 [(set (attr "type")
14340 (if_then_else (match_operand:SF 3 "mult_operator" "")
14341 (const_string "ssemul")
14342 (const_string "sseadd")))
14343 (set_attr "mode" "SF")])
14345 (define_insn "*fop_df_comm_nosse"
14346 [(set (match_operand:DF 0 "register_operand" "=f")
14347 (match_operator:DF 3 "binary_fp_operator"
14348 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14349 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14350 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14351 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14352 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14353 "* return output_387_binary_op (insn, operands);"
14354 [(set (attr "type")
14355 (if_then_else (match_operand:SF 3 "mult_operator" "")
14356 (const_string "fmul")
14357 (const_string "fop")))
14358 (set_attr "mode" "DF")])
14360 (define_insn "*fop_df_comm"
14361 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14362 (match_operator:DF 3 "binary_fp_operator"
14363 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14364 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14365 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14366 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14367 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14368 "* return output_387_binary_op (insn, operands);"
14369 [(set (attr "type")
14370 (if_then_else (eq_attr "alternative" "1")
14371 (if_then_else (match_operand:SF 3 "mult_operator" "")
14372 (const_string "ssemul")
14373 (const_string "sseadd"))
14374 (if_then_else (match_operand:SF 3 "mult_operator" "")
14375 (const_string "fmul")
14376 (const_string "fop"))))
14377 (set_attr "mode" "DF")])
14379 (define_insn "*fop_df_comm_sse"
14380 [(set (match_operand:DF 0 "register_operand" "=Y")
14381 (match_operator:DF 3 "binary_fp_operator"
14382 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14383 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14384 "TARGET_SSE2 && TARGET_SSE_MATH
14385 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14386 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14387 "* return output_387_binary_op (insn, operands);"
14388 [(set (attr "type")
14389 (if_then_else (match_operand:SF 3 "mult_operator" "")
14390 (const_string "ssemul")
14391 (const_string "sseadd")))
14392 (set_attr "mode" "DF")])
14394 (define_insn "*fop_xf_comm"
14395 [(set (match_operand:XF 0 "register_operand" "=f")
14396 (match_operator:XF 3 "binary_fp_operator"
14397 [(match_operand:XF 1 "register_operand" "%0")
14398 (match_operand:XF 2 "register_operand" "f")]))]
14400 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14401 "* return output_387_binary_op (insn, operands);"
14402 [(set (attr "type")
14403 (if_then_else (match_operand:XF 3 "mult_operator" "")
14404 (const_string "fmul")
14405 (const_string "fop")))
14406 (set_attr "mode" "XF")])
14408 (define_insn "*fop_sf_1_nosse"
14409 [(set (match_operand:SF 0 "register_operand" "=f,f")
14410 (match_operator:SF 3 "binary_fp_operator"
14411 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14412 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14413 "TARGET_80387 && !TARGET_SSE_MATH
14414 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14415 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14416 "* return output_387_binary_op (insn, operands);"
14417 [(set (attr "type")
14418 (cond [(match_operand:SF 3 "mult_operator" "")
14419 (const_string "fmul")
14420 (match_operand:SF 3 "div_operator" "")
14421 (const_string "fdiv")
14423 (const_string "fop")))
14424 (set_attr "mode" "SF")])
14426 (define_insn "*fop_sf_1"
14427 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14428 (match_operator:SF 3 "binary_fp_operator"
14429 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14430 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14431 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14432 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14433 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14434 "* return output_387_binary_op (insn, operands);"
14435 [(set (attr "type")
14436 (cond [(and (eq_attr "alternative" "2")
14437 (match_operand:SF 3 "mult_operator" ""))
14438 (const_string "ssemul")
14439 (and (eq_attr "alternative" "2")
14440 (match_operand:SF 3 "div_operator" ""))
14441 (const_string "ssediv")
14442 (eq_attr "alternative" "2")
14443 (const_string "sseadd")
14444 (match_operand:SF 3 "mult_operator" "")
14445 (const_string "fmul")
14446 (match_operand:SF 3 "div_operator" "")
14447 (const_string "fdiv")
14449 (const_string "fop")))
14450 (set_attr "mode" "SF")])
14452 (define_insn "*fop_sf_1_sse"
14453 [(set (match_operand:SF 0 "register_operand" "=x")
14454 (match_operator:SF 3 "binary_fp_operator"
14455 [(match_operand:SF 1 "register_operand" "0")
14456 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14458 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14459 "* return output_387_binary_op (insn, operands);"
14460 [(set (attr "type")
14461 (cond [(match_operand:SF 3 "mult_operator" "")
14462 (const_string "ssemul")
14463 (match_operand:SF 3 "div_operator" "")
14464 (const_string "ssediv")
14466 (const_string "sseadd")))
14467 (set_attr "mode" "SF")])
14469 ;; ??? Add SSE splitters for these!
14470 (define_insn "*fop_sf_2"
14471 [(set (match_operand:SF 0 "register_operand" "=f,f")
14472 (match_operator:SF 3 "binary_fp_operator"
14473 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14474 (match_operand:SF 2 "register_operand" "0,0")]))]
14475 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14476 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14477 [(set (attr "type")
14478 (cond [(match_operand:SF 3 "mult_operator" "")
14479 (const_string "fmul")
14480 (match_operand:SF 3 "div_operator" "")
14481 (const_string "fdiv")
14483 (const_string "fop")))
14484 (set_attr "fp_int_src" "true")
14485 (set_attr "ppro_uops" "many")
14486 (set_attr "mode" "SI")])
14488 (define_insn "*fop_sf_3"
14489 [(set (match_operand:SF 0 "register_operand" "=f,f")
14490 (match_operator:SF 3 "binary_fp_operator"
14491 [(match_operand:SF 1 "register_operand" "0,0")
14492 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14493 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14494 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14495 [(set (attr "type")
14496 (cond [(match_operand:SF 3 "mult_operator" "")
14497 (const_string "fmul")
14498 (match_operand:SF 3 "div_operator" "")
14499 (const_string "fdiv")
14501 (const_string "fop")))
14502 (set_attr "fp_int_src" "true")
14503 (set_attr "ppro_uops" "many")
14504 (set_attr "mode" "SI")])
14506 (define_insn "*fop_df_1_nosse"
14507 [(set (match_operand:DF 0 "register_operand" "=f,f")
14508 (match_operator:DF 3 "binary_fp_operator"
14509 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14510 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14511 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14512 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14513 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14514 "* return output_387_binary_op (insn, operands);"
14515 [(set (attr "type")
14516 (cond [(match_operand:DF 3 "mult_operator" "")
14517 (const_string "fmul")
14518 (match_operand:DF 3 "div_operator" "")
14519 (const_string "fdiv")
14521 (const_string "fop")))
14522 (set_attr "mode" "DF")])
14525 (define_insn "*fop_df_1"
14526 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14527 (match_operator:DF 3 "binary_fp_operator"
14528 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14529 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14530 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14531 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14532 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14533 "* return output_387_binary_op (insn, operands);"
14534 [(set (attr "type")
14535 (cond [(and (eq_attr "alternative" "2")
14536 (match_operand:SF 3 "mult_operator" ""))
14537 (const_string "ssemul")
14538 (and (eq_attr "alternative" "2")
14539 (match_operand:SF 3 "div_operator" ""))
14540 (const_string "ssediv")
14541 (eq_attr "alternative" "2")
14542 (const_string "sseadd")
14543 (match_operand:DF 3 "mult_operator" "")
14544 (const_string "fmul")
14545 (match_operand:DF 3 "div_operator" "")
14546 (const_string "fdiv")
14548 (const_string "fop")))
14549 (set_attr "mode" "DF")])
14551 (define_insn "*fop_df_1_sse"
14552 [(set (match_operand:DF 0 "register_operand" "=Y")
14553 (match_operator:DF 3 "binary_fp_operator"
14554 [(match_operand:DF 1 "register_operand" "0")
14555 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14556 "TARGET_SSE2 && TARGET_SSE_MATH
14557 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14558 "* return output_387_binary_op (insn, operands);"
14559 [(set_attr "mode" "DF")
14561 (cond [(match_operand:SF 3 "mult_operator" "")
14562 (const_string "ssemul")
14563 (match_operand:SF 3 "div_operator" "")
14564 (const_string "ssediv")
14566 (const_string "sseadd")))])
14568 ;; ??? Add SSE splitters for these!
14569 (define_insn "*fop_df_2"
14570 [(set (match_operand:DF 0 "register_operand" "=f,f")
14571 (match_operator:DF 3 "binary_fp_operator"
14572 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14573 (match_operand:DF 2 "register_operand" "0,0")]))]
14574 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14575 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14576 [(set (attr "type")
14577 (cond [(match_operand:DF 3 "mult_operator" "")
14578 (const_string "fmul")
14579 (match_operand:DF 3 "div_operator" "")
14580 (const_string "fdiv")
14582 (const_string "fop")))
14583 (set_attr "fp_int_src" "true")
14584 (set_attr "ppro_uops" "many")
14585 (set_attr "mode" "SI")])
14587 (define_insn "*fop_df_3"
14588 [(set (match_operand:DF 0 "register_operand" "=f,f")
14589 (match_operator:DF 3 "binary_fp_operator"
14590 [(match_operand:DF 1 "register_operand" "0,0")
14591 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14592 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14593 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14594 [(set (attr "type")
14595 (cond [(match_operand:DF 3 "mult_operator" "")
14596 (const_string "fmul")
14597 (match_operand:DF 3 "div_operator" "")
14598 (const_string "fdiv")
14600 (const_string "fop")))
14601 (set_attr "fp_int_src" "true")
14602 (set_attr "ppro_uops" "many")
14603 (set_attr "mode" "SI")])
14605 (define_insn "*fop_df_4"
14606 [(set (match_operand:DF 0 "register_operand" "=f,f")
14607 (match_operator:DF 3 "binary_fp_operator"
14608 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14609 (match_operand:DF 2 "register_operand" "0,f")]))]
14610 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14611 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14612 "* return output_387_binary_op (insn, operands);"
14613 [(set (attr "type")
14614 (cond [(match_operand:DF 3 "mult_operator" "")
14615 (const_string "fmul")
14616 (match_operand:DF 3 "div_operator" "")
14617 (const_string "fdiv")
14619 (const_string "fop")))
14620 (set_attr "mode" "SF")])
14622 (define_insn "*fop_df_5"
14623 [(set (match_operand:DF 0 "register_operand" "=f,f")
14624 (match_operator:DF 3 "binary_fp_operator"
14625 [(match_operand:DF 1 "register_operand" "0,f")
14627 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14628 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14629 "* return output_387_binary_op (insn, operands);"
14630 [(set (attr "type")
14631 (cond [(match_operand:DF 3 "mult_operator" "")
14632 (const_string "fmul")
14633 (match_operand:DF 3 "div_operator" "")
14634 (const_string "fdiv")
14636 (const_string "fop")))
14637 (set_attr "mode" "SF")])
14639 (define_insn "*fop_df_6"
14640 [(set (match_operand:DF 0 "register_operand" "=f,f")
14641 (match_operator:DF 3 "binary_fp_operator"
14643 (match_operand:SF 1 "register_operand" "0,f"))
14645 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14646 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14647 "* return output_387_binary_op (insn, operands);"
14648 [(set (attr "type")
14649 (cond [(match_operand:DF 3 "mult_operator" "")
14650 (const_string "fmul")
14651 (match_operand:DF 3 "div_operator" "")
14652 (const_string "fdiv")
14654 (const_string "fop")))
14655 (set_attr "mode" "SF")])
14657 (define_insn "*fop_xf_1"
14658 [(set (match_operand:XF 0 "register_operand" "=f,f")
14659 (match_operator:XF 3 "binary_fp_operator"
14660 [(match_operand:XF 1 "register_operand" "0,f")
14661 (match_operand:XF 2 "register_operand" "f,0")]))]
14663 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14664 "* return output_387_binary_op (insn, operands);"
14665 [(set (attr "type")
14666 (cond [(match_operand:XF 3 "mult_operator" "")
14667 (const_string "fmul")
14668 (match_operand:XF 3 "div_operator" "")
14669 (const_string "fdiv")
14671 (const_string "fop")))
14672 (set_attr "mode" "XF")])
14674 (define_insn "*fop_xf_2"
14675 [(set (match_operand:XF 0 "register_operand" "=f,f")
14676 (match_operator:XF 3 "binary_fp_operator"
14677 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14678 (match_operand:XF 2 "register_operand" "0,0")]))]
14679 "TARGET_80387 && TARGET_USE_FIOP"
14680 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14681 [(set (attr "type")
14682 (cond [(match_operand:XF 3 "mult_operator" "")
14683 (const_string "fmul")
14684 (match_operand:XF 3 "div_operator" "")
14685 (const_string "fdiv")
14687 (const_string "fop")))
14688 (set_attr "fp_int_src" "true")
14689 (set_attr "mode" "SI")
14690 (set_attr "ppro_uops" "many")])
14692 (define_insn "*fop_xf_3"
14693 [(set (match_operand:XF 0 "register_operand" "=f,f")
14694 (match_operator:XF 3 "binary_fp_operator"
14695 [(match_operand:XF 1 "register_operand" "0,0")
14696 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14697 "TARGET_80387 && TARGET_USE_FIOP"
14698 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14699 [(set (attr "type")
14700 (cond [(match_operand:XF 3 "mult_operator" "")
14701 (const_string "fmul")
14702 (match_operand:XF 3 "div_operator" "")
14703 (const_string "fdiv")
14705 (const_string "fop")))
14706 (set_attr "fp_int_src" "true")
14707 (set_attr "mode" "SI")
14708 (set_attr "ppro_uops" "many")])
14710 (define_insn "*fop_xf_4"
14711 [(set (match_operand:XF 0 "register_operand" "=f,f")
14712 (match_operator:XF 3 "binary_fp_operator"
14713 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14714 (match_operand:XF 2 "register_operand" "0,f")]))]
14716 "* return output_387_binary_op (insn, operands);"
14717 [(set (attr "type")
14718 (cond [(match_operand:XF 3 "mult_operator" "")
14719 (const_string "fmul")
14720 (match_operand:XF 3 "div_operator" "")
14721 (const_string "fdiv")
14723 (const_string "fop")))
14724 (set_attr "mode" "SF")])
14726 (define_insn "*fop_xf_5"
14727 [(set (match_operand:XF 0 "register_operand" "=f,f")
14728 (match_operator:XF 3 "binary_fp_operator"
14729 [(match_operand:XF 1 "register_operand" "0,f")
14731 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14733 "* return output_387_binary_op (insn, operands);"
14734 [(set (attr "type")
14735 (cond [(match_operand:XF 3 "mult_operator" "")
14736 (const_string "fmul")
14737 (match_operand:XF 3 "div_operator" "")
14738 (const_string "fdiv")
14740 (const_string "fop")))
14741 (set_attr "mode" "SF")])
14743 (define_insn "*fop_xf_6"
14744 [(set (match_operand:XF 0 "register_operand" "=f,f")
14745 (match_operator:XF 3 "binary_fp_operator"
14747 (match_operand 1 "register_operand" "0,f"))
14749 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14751 "* return output_387_binary_op (insn, operands);"
14752 [(set (attr "type")
14753 (cond [(match_operand:XF 3 "mult_operator" "")
14754 (const_string "fmul")
14755 (match_operand:XF 3 "div_operator" "")
14756 (const_string "fdiv")
14758 (const_string "fop")))
14759 (set_attr "mode" "SF")])
14762 [(set (match_operand 0 "register_operand" "")
14763 (match_operator 3 "binary_fp_operator"
14764 [(float (match_operand:SI 1 "register_operand" ""))
14765 (match_operand 2 "register_operand" "")]))]
14766 "TARGET_80387 && reload_completed
14767 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14770 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14771 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14772 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14773 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14774 GET_MODE (operands[3]),
14777 ix86_free_from_memory (GET_MODE (operands[1]));
14782 [(set (match_operand 0 "register_operand" "")
14783 (match_operator 3 "binary_fp_operator"
14784 [(match_operand 1 "register_operand" "")
14785 (float (match_operand:SI 2 "register_operand" ""))]))]
14786 "TARGET_80387 && reload_completed
14787 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14790 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14791 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14792 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14793 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14794 GET_MODE (operands[3]),
14797 ix86_free_from_memory (GET_MODE (operands[2]));
14801 ;; FPU special functions.
14803 (define_expand "sqrtsf2"
14804 [(set (match_operand:SF 0 "register_operand" "")
14805 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14806 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14808 if (!TARGET_SSE_MATH)
14809 operands[1] = force_reg (SFmode, operands[1]);
14812 (define_insn "sqrtsf2_1"
14813 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14814 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14815 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14816 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14819 sqrtss\t{%1, %0|%0, %1}"
14820 [(set_attr "type" "fpspc,sse")
14821 (set_attr "mode" "SF,SF")
14822 (set_attr "athlon_decode" "direct,*")])
14824 (define_insn "sqrtsf2_1_sse_only"
14825 [(set (match_operand:SF 0 "register_operand" "=x")
14826 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14827 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14828 "sqrtss\t{%1, %0|%0, %1}"
14829 [(set_attr "type" "sse")
14830 (set_attr "mode" "SF")
14831 (set_attr "athlon_decode" "*")])
14833 (define_insn "sqrtsf2_i387"
14834 [(set (match_operand:SF 0 "register_operand" "=f")
14835 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14836 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14837 && !TARGET_SSE_MATH"
14839 [(set_attr "type" "fpspc")
14840 (set_attr "mode" "SF")
14841 (set_attr "athlon_decode" "direct")])
14843 (define_expand "sqrtdf2"
14844 [(set (match_operand:DF 0 "register_operand" "")
14845 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14846 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14847 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14849 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14850 operands[1] = force_reg (DFmode, operands[1]);
14853 (define_insn "sqrtdf2_1"
14854 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14855 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14856 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14857 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14860 sqrtsd\t{%1, %0|%0, %1}"
14861 [(set_attr "type" "fpspc,sse")
14862 (set_attr "mode" "DF,DF")
14863 (set_attr "athlon_decode" "direct,*")])
14865 (define_insn "sqrtdf2_1_sse_only"
14866 [(set (match_operand:DF 0 "register_operand" "=Y")
14867 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14868 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14869 "sqrtsd\t{%1, %0|%0, %1}"
14870 [(set_attr "type" "sse")
14871 (set_attr "mode" "DF")
14872 (set_attr "athlon_decode" "*")])
14874 (define_insn "sqrtdf2_i387"
14875 [(set (match_operand:DF 0 "register_operand" "=f")
14876 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14877 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14878 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14880 [(set_attr "type" "fpspc")
14881 (set_attr "mode" "DF")
14882 (set_attr "athlon_decode" "direct")])
14884 (define_insn "*sqrtextendsfdf2"
14885 [(set (match_operand:DF 0 "register_operand" "=f")
14886 (sqrt:DF (float_extend:DF
14887 (match_operand:SF 1 "register_operand" "0"))))]
14888 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14889 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14891 [(set_attr "type" "fpspc")
14892 (set_attr "mode" "DF")
14893 (set_attr "athlon_decode" "direct")])
14895 (define_insn "sqrtxf2"
14896 [(set (match_operand:XF 0 "register_operand" "=f")
14897 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14898 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14899 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14901 [(set_attr "type" "fpspc")
14902 (set_attr "mode" "XF")
14903 (set_attr "athlon_decode" "direct")])
14905 (define_insn "*sqrtextenddfxf2"
14906 [(set (match_operand:XF 0 "register_operand" "=f")
14907 (sqrt:XF (float_extend:XF
14908 (match_operand:DF 1 "register_operand" "0"))))]
14909 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14911 [(set_attr "type" "fpspc")
14912 (set_attr "mode" "XF")
14913 (set_attr "athlon_decode" "direct")])
14915 (define_insn "*sqrtextendsfxf2"
14916 [(set (match_operand:XF 0 "register_operand" "=f")
14917 (sqrt:XF (float_extend:XF
14918 (match_operand:SF 1 "register_operand" "0"))))]
14919 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14921 [(set_attr "type" "fpspc")
14922 (set_attr "mode" "XF")
14923 (set_attr "athlon_decode" "direct")])
14925 (define_insn "sindf2"
14926 [(set (match_operand:DF 0 "register_operand" "=f")
14927 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14928 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14929 && flag_unsafe_math_optimizations"
14931 [(set_attr "type" "fpspc")
14932 (set_attr "mode" "DF")])
14934 (define_insn "sinsf2"
14935 [(set (match_operand:SF 0 "register_operand" "=f")
14936 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14937 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14938 && flag_unsafe_math_optimizations"
14940 [(set_attr "type" "fpspc")
14941 (set_attr "mode" "SF")])
14943 (define_insn "*sinextendsfdf2"
14944 [(set (match_operand:DF 0 "register_operand" "=f")
14945 (unspec:DF [(float_extend:DF
14946 (match_operand:SF 1 "register_operand" "0"))]
14948 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14949 && flag_unsafe_math_optimizations"
14951 [(set_attr "type" "fpspc")
14952 (set_attr "mode" "DF")])
14954 (define_insn "sinxf2"
14955 [(set (match_operand:XF 0 "register_operand" "=f")
14956 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14957 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14958 && flag_unsafe_math_optimizations"
14960 [(set_attr "type" "fpspc")
14961 (set_attr "mode" "XF")])
14963 (define_insn "cosdf2"
14964 [(set (match_operand:DF 0 "register_operand" "=f")
14965 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14966 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14967 && flag_unsafe_math_optimizations"
14969 [(set_attr "type" "fpspc")
14970 (set_attr "mode" "DF")])
14972 (define_insn "cossf2"
14973 [(set (match_operand:SF 0 "register_operand" "=f")
14974 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14975 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14976 && flag_unsafe_math_optimizations"
14978 [(set_attr "type" "fpspc")
14979 (set_attr "mode" "SF")])
14981 (define_insn "*cosextendsfdf2"
14982 [(set (match_operand:DF 0 "register_operand" "=f")
14983 (unspec:DF [(float_extend:DF
14984 (match_operand:SF 1 "register_operand" "0"))]
14986 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14987 && flag_unsafe_math_optimizations"
14989 [(set_attr "type" "fpspc")
14990 (set_attr "mode" "DF")])
14992 (define_insn "cosxf2"
14993 [(set (match_operand:XF 0 "register_operand" "=f")
14994 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14995 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14996 && flag_unsafe_math_optimizations"
14998 [(set_attr "type" "fpspc")
14999 (set_attr "mode" "XF")])
15001 (define_insn "atan2df3_1"
15002 [(set (match_operand:DF 0 "register_operand" "=f")
15003 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15004 (match_operand:DF 1 "register_operand" "u")]
15006 (clobber (match_scratch:DF 3 "=1"))]
15007 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15008 && flag_unsafe_math_optimizations"
15010 [(set_attr "type" "fpspc")
15011 (set_attr "mode" "DF")])
15013 (define_expand "atan2df3"
15014 [(use (match_operand:DF 0 "register_operand" "=f"))
15015 (use (match_operand:DF 2 "register_operand" "0"))
15016 (use (match_operand:DF 1 "register_operand" "u"))]
15017 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15018 && flag_unsafe_math_optimizations"
15020 rtx copy = gen_reg_rtx (DFmode);
15021 emit_move_insn (copy, operands[1]);
15022 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15026 (define_insn "atan2sf3_1"
15027 [(set (match_operand:SF 0 "register_operand" "=f")
15028 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15029 (match_operand:SF 1 "register_operand" "u")]
15031 (clobber (match_scratch:SF 3 "=1"))]
15032 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15033 && flag_unsafe_math_optimizations"
15035 [(set_attr "type" "fpspc")
15036 (set_attr "mode" "SF")])
15038 (define_expand "atan2sf3"
15039 [(use (match_operand:SF 0 "register_operand" "=f"))
15040 (use (match_operand:SF 2 "register_operand" "0"))
15041 (use (match_operand:SF 1 "register_operand" "u"))]
15042 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15043 && flag_unsafe_math_optimizations"
15045 rtx copy = gen_reg_rtx (SFmode);
15046 emit_move_insn (copy, operands[1]);
15047 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15051 (define_insn "atan2xf3_1"
15052 [(set (match_operand:XF 0 "register_operand" "=f")
15053 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15054 (match_operand:XF 1 "register_operand" "u")]
15056 (clobber (match_scratch:XF 3 "=1"))]
15057 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15058 && flag_unsafe_math_optimizations"
15060 [(set_attr "type" "fpspc")
15061 (set_attr "mode" "XF")])
15063 (define_expand "atan2xf3"
15064 [(use (match_operand:XF 0 "register_operand" "=f"))
15065 (use (match_operand:XF 2 "register_operand" "0"))
15066 (use (match_operand:XF 1 "register_operand" "u"))]
15067 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15068 && flag_unsafe_math_optimizations"
15070 rtx copy = gen_reg_rtx (XFmode);
15071 emit_move_insn (copy, operands[1]);
15072 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15076 (define_insn "*fyl2x_sfxf3"
15077 [(set (match_operand:SF 0 "register_operand" "=f")
15078 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15079 (match_operand:XF 1 "register_operand" "u")]
15081 (clobber (match_scratch:SF 3 "=1"))]
15082 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15083 && flag_unsafe_math_optimizations"
15085 [(set_attr "type" "fpspc")
15086 (set_attr "mode" "SF")])
15088 (define_insn "*fyl2x_dfxf3"
15089 [(set (match_operand:DF 0 "register_operand" "=f")
15090 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15091 (match_operand:XF 1 "register_operand" "u")]
15093 (clobber (match_scratch:DF 3 "=1"))]
15094 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15095 && flag_unsafe_math_optimizations"
15097 [(set_attr "type" "fpspc")
15098 (set_attr "mode" "DF")])
15100 (define_insn "*fyl2x_xf3"
15101 [(set (match_operand:XF 0 "register_operand" "=f")
15102 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15103 (match_operand:XF 1 "register_operand" "u")]
15105 (clobber (match_scratch:XF 3 "=1"))]
15106 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15107 && flag_unsafe_math_optimizations"
15109 [(set_attr "type" "fpspc")
15110 (set_attr "mode" "XF")])
15112 (define_expand "logsf2"
15113 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15114 (unspec:SF [(match_operand:SF 1 "register_operand" "")
15115 (match_dup 2)] UNSPEC_FYL2X))
15116 (clobber (match_scratch:SF 3 ""))])]
15117 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15118 && flag_unsafe_math_optimizations"
15122 operands[2] = gen_reg_rtx (XFmode);
15123 temp = standard_80387_constant_rtx (4); /* fldln2 */
15124 emit_move_insn (operands[2], temp);
15127 (define_expand "logdf2"
15128 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15129 (unspec:DF [(match_operand:DF 1 "register_operand" "")
15130 (match_dup 2)] UNSPEC_FYL2X))
15131 (clobber (match_scratch:DF 3 ""))])]
15132 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15133 && flag_unsafe_math_optimizations"
15137 operands[2] = gen_reg_rtx (XFmode);
15138 temp = standard_80387_constant_rtx (4); /* fldln2 */
15139 emit_move_insn (operands[2], temp);
15142 (define_expand "logxf2"
15143 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15144 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15145 (match_dup 2)] UNSPEC_FYL2X))
15146 (clobber (match_scratch:XF 3 ""))])]
15147 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15148 && flag_unsafe_math_optimizations"
15152 operands[2] = gen_reg_rtx (XFmode);
15153 temp = standard_80387_constant_rtx (4); /* fldln2 */
15154 emit_move_insn (operands[2], temp);
15157 (define_insn "*fscale_sfxf3"
15158 [(set (match_operand:SF 0 "register_operand" "=f")
15159 (unspec:SF [(match_operand:XF 2 "register_operand" "0")
15160 (match_operand:XF 1 "register_operand" "u")]
15162 (clobber (match_scratch:SF 3 "=1"))]
15163 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15164 && flag_unsafe_math_optimizations"
15165 "fscale\;fstp\t%y1"
15166 [(set_attr "type" "fpspc")
15167 (set_attr "mode" "SF")])
15169 (define_insn "*fscale_dfxf3"
15170 [(set (match_operand:DF 0 "register_operand" "=f")
15171 (unspec:DF [(match_operand:XF 2 "register_operand" "0")
15172 (match_operand:XF 1 "register_operand" "u")]
15174 (clobber (match_scratch:DF 3 "=1"))]
15175 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15176 && flag_unsafe_math_optimizations"
15177 "fscale\;fstp\t%y1"
15178 [(set_attr "type" "fpspc")
15179 (set_attr "mode" "DF")])
15181 (define_insn "*fscale_xf3"
15182 [(set (match_operand:XF 0 "register_operand" "=f")
15183 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15184 (match_operand:XF 1 "register_operand" "u")]
15186 (clobber (match_scratch:XF 3 "=1"))]
15187 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15188 && flag_unsafe_math_optimizations"
15189 "fscale\;fstp\t%y1"
15190 [(set_attr "type" "fpspc")
15191 (set_attr "mode" "XF")])
15193 (define_insn "*frndintxf2"
15194 [(set (match_operand:XF 0 "register_operand" "=f")
15195 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15197 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15198 && flag_unsafe_math_optimizations"
15200 [(set_attr "type" "fpspc")
15201 (set_attr "mode" "XF")])
15203 (define_insn "*f2xm1xf2"
15204 [(set (match_operand:XF 0 "register_operand" "=f")
15205 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15207 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15208 && flag_unsafe_math_optimizations"
15210 [(set_attr "type" "fpspc")
15211 (set_attr "mode" "XF")])
15213 (define_expand "expsf2"
15214 [(set (match_dup 2)
15215 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15216 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15217 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15218 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15219 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15220 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15221 (parallel [(set (match_operand:SF 0 "register_operand" "")
15222 (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
15223 (clobber (match_scratch:SF 5 ""))])]
15224 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15225 && flag_unsafe_math_optimizations"
15230 for (i=2; i<10; i++)
15231 operands[i] = gen_reg_rtx (XFmode);
15232 temp = standard_80387_constant_rtx (5); /* fldl2e */
15233 emit_move_insn (operands[3], temp);
15234 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15237 (define_expand "expdf2"
15238 [(set (match_dup 2)
15239 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15240 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15241 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15242 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15243 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15244 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15245 (parallel [(set (match_operand:DF 0 "register_operand" "")
15246 (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
15247 (clobber (match_scratch:DF 5 ""))])]
15248 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15249 && flag_unsafe_math_optimizations"
15254 for (i=2; i<10; i++)
15255 operands[i] = gen_reg_rtx (XFmode);
15256 temp = standard_80387_constant_rtx (5); /* fldl2e */
15257 emit_move_insn (operands[3], temp);
15258 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15261 (define_expand "expxf2"
15262 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15264 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15265 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15266 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15267 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15268 (parallel [(set (match_operand:XF 0 "register_operand" "")
15269 (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
15270 (clobber (match_scratch:XF 5 ""))])]
15271 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15272 && flag_unsafe_math_optimizations"
15277 for (i=2; i<9; i++)
15278 operands[i] = gen_reg_rtx (XFmode);
15279 temp = standard_80387_constant_rtx (5); /* fldl2e */
15280 emit_move_insn (operands[2], temp);
15281 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15284 (define_expand "atansf2"
15285 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15286 (unspec:SF [(match_dup 2)
15287 (match_operand:SF 1 "register_operand" "")]
15289 (clobber (match_scratch:SF 3 ""))])]
15290 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15291 && flag_unsafe_math_optimizations"
15293 operands[2] = gen_reg_rtx (SFmode);
15294 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15297 (define_expand "atandf2"
15298 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15299 (unspec:DF [(match_dup 2)
15300 (match_operand:DF 1 "register_operand" "")]
15302 (clobber (match_scratch:DF 3 ""))])]
15303 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15304 && flag_unsafe_math_optimizations"
15306 operands[2] = gen_reg_rtx (DFmode);
15307 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15310 (define_expand "atanxf2"
15311 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15312 (unspec:XF [(match_dup 2)
15313 (match_operand:XF 1 "register_operand" "")]
15315 (clobber (match_scratch:XF 3 ""))])]
15316 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15317 && flag_unsafe_math_optimizations"
15319 operands[2] = gen_reg_rtx (XFmode);
15320 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15323 ;; Block operation instructions
15326 [(set (reg:SI 19) (const_int 0))]
15329 [(set_attr "type" "cld")])
15331 (define_expand "movstrsi"
15332 [(use (match_operand:BLK 0 "memory_operand" ""))
15333 (use (match_operand:BLK 1 "memory_operand" ""))
15334 (use (match_operand:SI 2 "nonmemory_operand" ""))
15335 (use (match_operand:SI 3 "const_int_operand" ""))]
15338 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15344 (define_expand "movstrdi"
15345 [(use (match_operand:BLK 0 "memory_operand" ""))
15346 (use (match_operand:BLK 1 "memory_operand" ""))
15347 (use (match_operand:DI 2 "nonmemory_operand" ""))
15348 (use (match_operand:DI 3 "const_int_operand" ""))]
15351 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15357 ;; Most CPUs don't like single string operations
15358 ;; Handle this case here to simplify previous expander.
15360 (define_expand "strmov"
15361 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
15362 (set (match_operand 1 "memory_operand" "") (match_dup 4))
15363 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
15364 (clobber (reg:CC 17))])
15365 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
15366 (clobber (reg:CC 17))])]
15369 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
15371 /* If .md ever supports :P for Pmode, these can be directly
15372 in the pattern above. */
15373 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
15374 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
15376 if (TARGET_SINGLE_STRINGOP || optimize_size)
15378 emit_insn (gen_strmov_singleop (operands[0], operands[1],
15379 operands[2], operands[3],
15380 operands[5], operands[6]));
15384 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
15387 (define_expand "strmov_singleop"
15388 [(parallel [(set (match_operand 1 "memory_operand" "")
15389 (match_operand 3 "memory_operand" ""))
15390 (set (match_operand 0 "register_operand" "")
15391 (match_operand 4 "" ""))
15392 (set (match_operand 2 "register_operand" "")
15393 (match_operand 5 "" ""))
15394 (use (reg:SI 19))])]
15395 "TARGET_SINGLE_STRINGOP || optimize_size"
15398 (define_insn "*strmovdi_rex_1"
15399 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15400 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15401 (set (match_operand:DI 0 "register_operand" "=D")
15402 (plus:DI (match_dup 2)
15404 (set (match_operand:DI 1 "register_operand" "=S")
15405 (plus:DI (match_dup 3)
15408 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15410 [(set_attr "type" "str")
15411 (set_attr "mode" "DI")
15412 (set_attr "memory" "both")])
15414 (define_insn "*strmovsi_1"
15415 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15416 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15417 (set (match_operand:SI 0 "register_operand" "=D")
15418 (plus:SI (match_dup 2)
15420 (set (match_operand:SI 1 "register_operand" "=S")
15421 (plus:SI (match_dup 3)
15424 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15426 [(set_attr "type" "str")
15427 (set_attr "mode" "SI")
15428 (set_attr "memory" "both")])
15430 (define_insn "*strmovsi_rex_1"
15431 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15432 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15433 (set (match_operand:DI 0 "register_operand" "=D")
15434 (plus:DI (match_dup 2)
15436 (set (match_operand:DI 1 "register_operand" "=S")
15437 (plus:DI (match_dup 3)
15440 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15442 [(set_attr "type" "str")
15443 (set_attr "mode" "SI")
15444 (set_attr "memory" "both")])
15446 (define_insn "*strmovhi_1"
15447 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15448 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15449 (set (match_operand:SI 0 "register_operand" "=D")
15450 (plus:SI (match_dup 2)
15452 (set (match_operand:SI 1 "register_operand" "=S")
15453 (plus:SI (match_dup 3)
15456 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15458 [(set_attr "type" "str")
15459 (set_attr "memory" "both")
15460 (set_attr "mode" "HI")])
15462 (define_insn "*strmovhi_rex_1"
15463 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15464 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15465 (set (match_operand:DI 0 "register_operand" "=D")
15466 (plus:DI (match_dup 2)
15468 (set (match_operand:DI 1 "register_operand" "=S")
15469 (plus:DI (match_dup 3)
15472 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15474 [(set_attr "type" "str")
15475 (set_attr "memory" "both")
15476 (set_attr "mode" "HI")])
15478 (define_insn "*strmovqi_1"
15479 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15480 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15481 (set (match_operand:SI 0 "register_operand" "=D")
15482 (plus:SI (match_dup 2)
15484 (set (match_operand:SI 1 "register_operand" "=S")
15485 (plus:SI (match_dup 3)
15488 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15490 [(set_attr "type" "str")
15491 (set_attr "memory" "both")
15492 (set_attr "mode" "QI")])
15494 (define_insn "*strmovqi_rex_1"
15495 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15496 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15497 (set (match_operand:DI 0 "register_operand" "=D")
15498 (plus:DI (match_dup 2)
15500 (set (match_operand:DI 1 "register_operand" "=S")
15501 (plus:DI (match_dup 3)
15504 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15506 [(set_attr "type" "str")
15507 (set_attr "memory" "both")
15508 (set_attr "mode" "QI")])
15510 (define_expand "rep_mov"
15511 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
15512 (set (match_operand 0 "register_operand" "")
15513 (match_operand 5 "" ""))
15514 (set (match_operand 2 "register_operand" "")
15515 (match_operand 6 "" ""))
15516 (set (match_operand 1 "memory_operand" "")
15517 (match_operand 3 "memory_operand" ""))
15518 (use (match_dup 4))
15519 (use (reg:SI 19))])]
15523 (define_insn "*rep_movdi_rex64"
15524 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15525 (set (match_operand:DI 0 "register_operand" "=D")
15526 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15528 (match_operand:DI 3 "register_operand" "0")))
15529 (set (match_operand:DI 1 "register_operand" "=S")
15530 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15531 (match_operand:DI 4 "register_operand" "1")))
15532 (set (mem:BLK (match_dup 3))
15533 (mem:BLK (match_dup 4)))
15534 (use (match_dup 5))
15537 "{rep\;movsq|rep movsq}"
15538 [(set_attr "type" "str")
15539 (set_attr "prefix_rep" "1")
15540 (set_attr "memory" "both")
15541 (set_attr "mode" "DI")])
15543 (define_insn "*rep_movsi"
15544 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15545 (set (match_operand:SI 0 "register_operand" "=D")
15546 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15548 (match_operand:SI 3 "register_operand" "0")))
15549 (set (match_operand:SI 1 "register_operand" "=S")
15550 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15551 (match_operand:SI 4 "register_operand" "1")))
15552 (set (mem:BLK (match_dup 3))
15553 (mem:BLK (match_dup 4)))
15554 (use (match_dup 5))
15557 "{rep\;movsl|rep movsd}"
15558 [(set_attr "type" "str")
15559 (set_attr "prefix_rep" "1")
15560 (set_attr "memory" "both")
15561 (set_attr "mode" "SI")])
15563 (define_insn "*rep_movsi_rex64"
15564 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15565 (set (match_operand:DI 0 "register_operand" "=D")
15566 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15568 (match_operand:DI 3 "register_operand" "0")))
15569 (set (match_operand:DI 1 "register_operand" "=S")
15570 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
15571 (match_operand:DI 4 "register_operand" "1")))
15572 (set (mem:BLK (match_dup 3))
15573 (mem:BLK (match_dup 4)))
15574 (use (match_dup 5))
15577 "{rep\;movsl|rep movsd}"
15578 [(set_attr "type" "str")
15579 (set_attr "prefix_rep" "1")
15580 (set_attr "memory" "both")
15581 (set_attr "mode" "SI")])
15583 (define_insn "*rep_movqi"
15584 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15585 (set (match_operand:SI 0 "register_operand" "=D")
15586 (plus:SI (match_operand:SI 3 "register_operand" "0")
15587 (match_operand:SI 5 "register_operand" "2")))
15588 (set (match_operand:SI 1 "register_operand" "=S")
15589 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15590 (set (mem:BLK (match_dup 3))
15591 (mem:BLK (match_dup 4)))
15592 (use (match_dup 5))
15595 "{rep\;movsb|rep movsb}"
15596 [(set_attr "type" "str")
15597 (set_attr "prefix_rep" "1")
15598 (set_attr "memory" "both")
15599 (set_attr "mode" "SI")])
15601 (define_insn "*rep_movqi_rex64"
15602 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15603 (set (match_operand:DI 0 "register_operand" "=D")
15604 (plus:DI (match_operand:DI 3 "register_operand" "0")
15605 (match_operand:DI 5 "register_operand" "2")))
15606 (set (match_operand:DI 1 "register_operand" "=S")
15607 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15608 (set (mem:BLK (match_dup 3))
15609 (mem:BLK (match_dup 4)))
15610 (use (match_dup 5))
15613 "{rep\;movsb|rep movsb}"
15614 [(set_attr "type" "str")
15615 (set_attr "prefix_rep" "1")
15616 (set_attr "memory" "both")
15617 (set_attr "mode" "SI")])
15619 (define_expand "clrstrsi"
15620 [(use (match_operand:BLK 0 "memory_operand" ""))
15621 (use (match_operand:SI 1 "nonmemory_operand" ""))
15622 (use (match_operand 2 "const_int_operand" ""))]
15625 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15631 (define_expand "clrstrdi"
15632 [(use (match_operand:BLK 0 "memory_operand" ""))
15633 (use (match_operand:DI 1 "nonmemory_operand" ""))
15634 (use (match_operand 2 "const_int_operand" ""))]
15637 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15643 ;; Most CPUs don't like single string operations
15644 ;; Handle this case here to simplify previous expander.
15646 (define_expand "strset"
15647 [(set (match_operand 1 "memory_operand" "")
15648 (match_operand 2 "register_operand" ""))
15649 (parallel [(set (match_operand 0 "register_operand" "")
15651 (clobber (reg:CC 17))])]
15654 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
15655 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
15657 /* If .md ever supports :P for Pmode, this can be directly
15658 in the pattern above. */
15659 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
15660 GEN_INT (GET_MODE_SIZE (GET_MODE
15662 if (TARGET_SINGLE_STRINGOP || optimize_size)
15664 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
15670 (define_expand "strset_singleop"
15671 [(parallel [(set (match_operand 1 "memory_operand" "")
15672 (match_operand 2 "register_operand" ""))
15673 (set (match_operand 0 "register_operand" "")
15674 (match_operand 3 "" ""))
15675 (use (reg:SI 19))])]
15676 "TARGET_SINGLE_STRINGOP || optimize_size"
15679 (define_insn "*strsetdi_rex_1"
15680 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15681 (match_operand:SI 2 "register_operand" "a"))
15682 (set (match_operand:DI 0 "register_operand" "=D")
15683 (plus:DI (match_dup 1)
15686 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15688 [(set_attr "type" "str")
15689 (set_attr "memory" "store")
15690 (set_attr "mode" "DI")])
15692 (define_insn "*strsetsi_1"
15693 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15694 (match_operand:SI 2 "register_operand" "a"))
15695 (set (match_operand:SI 0 "register_operand" "=D")
15696 (plus:SI (match_dup 1)
15699 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15701 [(set_attr "type" "str")
15702 (set_attr "memory" "store")
15703 (set_attr "mode" "SI")])
15705 (define_insn "*strsetsi_rex_1"
15706 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15707 (match_operand:SI 2 "register_operand" "a"))
15708 (set (match_operand:DI 0 "register_operand" "=D")
15709 (plus:DI (match_dup 1)
15712 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15714 [(set_attr "type" "str")
15715 (set_attr "memory" "store")
15716 (set_attr "mode" "SI")])
15718 (define_insn "*strsethi_1"
15719 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15720 (match_operand:HI 2 "register_operand" "a"))
15721 (set (match_operand:SI 0 "register_operand" "=D")
15722 (plus:SI (match_dup 1)
15725 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15727 [(set_attr "type" "str")
15728 (set_attr "memory" "store")
15729 (set_attr "mode" "HI")])
15731 (define_insn "*strsethi_rex_1"
15732 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15733 (match_operand:HI 2 "register_operand" "a"))
15734 (set (match_operand:DI 0 "register_operand" "=D")
15735 (plus:DI (match_dup 1)
15738 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15740 [(set_attr "type" "str")
15741 (set_attr "memory" "store")
15742 (set_attr "mode" "HI")])
15744 (define_insn "*strsetqi_1"
15745 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15746 (match_operand:QI 2 "register_operand" "a"))
15747 (set (match_operand:SI 0 "register_operand" "=D")
15748 (plus:SI (match_dup 1)
15751 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15753 [(set_attr "type" "str")
15754 (set_attr "memory" "store")
15755 (set_attr "mode" "QI")])
15757 (define_insn "*strsetqi_rex_1"
15758 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15759 (match_operand:QI 2 "register_operand" "a"))
15760 (set (match_operand:DI 0 "register_operand" "=D")
15761 (plus:DI (match_dup 1)
15764 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15766 [(set_attr "type" "str")
15767 (set_attr "memory" "store")
15768 (set_attr "mode" "QI")])
15770 (define_expand "rep_stos"
15771 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
15772 (set (match_operand 0 "register_operand" "")
15773 (match_operand 4 "" ""))
15774 (set (match_operand 2 "memory_operand" "") (const_int 0))
15775 (use (match_operand 3 "register_operand" ""))
15776 (use (match_dup 1))
15777 (use (reg:SI 19))])]
15781 (define_insn "*rep_stosdi_rex64"
15782 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15783 (set (match_operand:DI 0 "register_operand" "=D")
15784 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15786 (match_operand:DI 3 "register_operand" "0")))
15787 (set (mem:BLK (match_dup 3))
15789 (use (match_operand:DI 2 "register_operand" "a"))
15790 (use (match_dup 4))
15793 "{rep\;stosq|rep stosq}"
15794 [(set_attr "type" "str")
15795 (set_attr "prefix_rep" "1")
15796 (set_attr "memory" "store")
15797 (set_attr "mode" "DI")])
15799 (define_insn "*rep_stossi"
15800 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15801 (set (match_operand:SI 0 "register_operand" "=D")
15802 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15804 (match_operand:SI 3 "register_operand" "0")))
15805 (set (mem:BLK (match_dup 3))
15807 (use (match_operand:SI 2 "register_operand" "a"))
15808 (use (match_dup 4))
15811 "{rep\;stosl|rep stosd}"
15812 [(set_attr "type" "str")
15813 (set_attr "prefix_rep" "1")
15814 (set_attr "memory" "store")
15815 (set_attr "mode" "SI")])
15817 (define_insn "*rep_stossi_rex64"
15818 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15819 (set (match_operand:DI 0 "register_operand" "=D")
15820 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15822 (match_operand:DI 3 "register_operand" "0")))
15823 (set (mem:BLK (match_dup 3))
15825 (use (match_operand:SI 2 "register_operand" "a"))
15826 (use (match_dup 4))
15829 "{rep\;stosl|rep stosd}"
15830 [(set_attr "type" "str")
15831 (set_attr "prefix_rep" "1")
15832 (set_attr "memory" "store")
15833 (set_attr "mode" "SI")])
15835 (define_insn "*rep_stosqi"
15836 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15837 (set (match_operand:SI 0 "register_operand" "=D")
15838 (plus:SI (match_operand:SI 3 "register_operand" "0")
15839 (match_operand:SI 4 "register_operand" "1")))
15840 (set (mem:BLK (match_dup 3))
15842 (use (match_operand:QI 2 "register_operand" "a"))
15843 (use (match_dup 4))
15846 "{rep\;stosb|rep stosb}"
15847 [(set_attr "type" "str")
15848 (set_attr "prefix_rep" "1")
15849 (set_attr "memory" "store")
15850 (set_attr "mode" "QI")])
15852 (define_insn "*rep_stosqi_rex64"
15853 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15854 (set (match_operand:DI 0 "register_operand" "=D")
15855 (plus:DI (match_operand:DI 3 "register_operand" "0")
15856 (match_operand:DI 4 "register_operand" "1")))
15857 (set (mem:BLK (match_dup 3))
15859 (use (match_operand:QI 2 "register_operand" "a"))
15860 (use (match_dup 4))
15863 "{rep\;stosb|rep stosb}"
15864 [(set_attr "type" "str")
15865 (set_attr "prefix_rep" "1")
15866 (set_attr "memory" "store")
15867 (set_attr "mode" "QI")])
15869 (define_expand "cmpstrsi"
15870 [(set (match_operand:SI 0 "register_operand" "")
15871 (compare:SI (match_operand:BLK 1 "general_operand" "")
15872 (match_operand:BLK 2 "general_operand" "")))
15873 (use (match_operand 3 "general_operand" ""))
15874 (use (match_operand 4 "immediate_operand" ""))]
15875 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
15877 rtx addr1, addr2, out, outlow, count, countreg, align;
15879 /* Can't use this if the user has appropriated esi or edi. */
15880 if (global_regs[4] || global_regs[5])
15884 if (GET_CODE (out) != REG)
15885 out = gen_reg_rtx (SImode);
15887 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15888 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15889 if (addr1 != XEXP (operands[1], 0))
15890 operands[1] = replace_equiv_address_nv (operands[1], addr1);
15891 if (addr2 != XEXP (operands[2], 0))
15892 operands[2] = replace_equiv_address_nv (operands[2], addr2);
15894 count = operands[3];
15895 countreg = ix86_zero_extend_to_Pmode (count);
15897 /* %%% Iff we are testing strict equality, we can use known alignment
15898 to good advantage. This may be possible with combine, particularly
15899 once cc0 is dead. */
15900 align = operands[4];
15902 emit_insn (gen_cld ());
15903 if (GET_CODE (count) == CONST_INT)
15905 if (INTVAL (count) == 0)
15907 emit_move_insn (operands[0], const0_rtx);
15910 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15911 operands[1], operands[2]));
15916 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15918 emit_insn (gen_cmpsi_1 (countreg, countreg));
15919 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15920 operands[1], operands[2]));
15923 outlow = gen_lowpart (QImode, out);
15924 emit_insn (gen_cmpintqi (outlow));
15925 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15927 if (operands[0] != out)
15928 emit_move_insn (operands[0], out);
15933 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15935 (define_expand "cmpintqi"
15936 [(set (match_dup 1)
15937 (gtu:QI (reg:CC 17) (const_int 0)))
15939 (ltu:QI (reg:CC 17) (const_int 0)))
15940 (parallel [(set (match_operand:QI 0 "register_operand" "")
15941 (minus:QI (match_dup 1)
15943 (clobber (reg:CC 17))])]
15945 "operands[1] = gen_reg_rtx (QImode);
15946 operands[2] = gen_reg_rtx (QImode);")
15948 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15949 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15951 (define_expand "cmpstrqi_nz_1"
15952 [(parallel [(set (reg:CC 17)
15953 (compare:CC (match_operand 4 "memory_operand" "")
15954 (match_operand 5 "memory_operand" "")))
15955 (use (match_operand 2 "register_operand" ""))
15956 (use (match_operand:SI 3 "immediate_operand" ""))
15958 (clobber (match_operand 0 "register_operand" ""))
15959 (clobber (match_operand 1 "register_operand" ""))
15960 (clobber (match_dup 2))])]
15964 (define_insn "*cmpstrqi_nz_1"
15966 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15967 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15968 (use (match_operand:SI 6 "register_operand" "2"))
15969 (use (match_operand:SI 3 "immediate_operand" "i"))
15971 (clobber (match_operand:SI 0 "register_operand" "=S"))
15972 (clobber (match_operand:SI 1 "register_operand" "=D"))
15973 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15976 [(set_attr "type" "str")
15977 (set_attr "mode" "QI")
15978 (set_attr "prefix_rep" "1")])
15980 (define_insn "*cmpstrqi_nz_rex_1"
15982 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15983 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15984 (use (match_operand:DI 6 "register_operand" "2"))
15985 (use (match_operand:SI 3 "immediate_operand" "i"))
15987 (clobber (match_operand:DI 0 "register_operand" "=S"))
15988 (clobber (match_operand:DI 1 "register_operand" "=D"))
15989 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15992 [(set_attr "type" "str")
15993 (set_attr "mode" "QI")
15994 (set_attr "prefix_rep" "1")])
15996 ;; The same, but the count is not known to not be zero.
15998 (define_expand "cmpstrqi_1"
15999 [(parallel [(set (reg:CC 17)
16000 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
16002 (compare:CC (match_operand 4 "memory_operand" "")
16003 (match_operand 5 "memory_operand" ""))
16005 (use (match_operand:SI 3 "immediate_operand" ""))
16008 (clobber (match_operand 0 "register_operand" ""))
16009 (clobber (match_operand 1 "register_operand" ""))
16010 (clobber (match_dup 2))])]
16014 (define_insn "*cmpstrqi_1"
16016 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16018 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16019 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16021 (use (match_operand:SI 3 "immediate_operand" "i"))
16024 (clobber (match_operand:SI 0 "register_operand" "=S"))
16025 (clobber (match_operand:SI 1 "register_operand" "=D"))
16026 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16029 [(set_attr "type" "str")
16030 (set_attr "mode" "QI")
16031 (set_attr "prefix_rep" "1")])
16033 (define_insn "*cmpstrqi_rex_1"
16035 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16037 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16038 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16040 (use (match_operand:SI 3 "immediate_operand" "i"))
16043 (clobber (match_operand:DI 0 "register_operand" "=S"))
16044 (clobber (match_operand:DI 1 "register_operand" "=D"))
16045 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16048 [(set_attr "type" "str")
16049 (set_attr "mode" "QI")
16050 (set_attr "prefix_rep" "1")])
16052 (define_expand "strlensi"
16053 [(set (match_operand:SI 0 "register_operand" "")
16054 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16055 (match_operand:QI 2 "immediate_operand" "")
16056 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16059 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16065 (define_expand "strlendi"
16066 [(set (match_operand:DI 0 "register_operand" "")
16067 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16068 (match_operand:QI 2 "immediate_operand" "")
16069 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16072 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16078 (define_expand "strlenqi_1"
16079 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
16081 (clobber (match_operand 1 "register_operand" ""))
16082 (clobber (reg:CC 17))])]
16086 (define_insn "*strlenqi_1"
16087 [(set (match_operand:SI 0 "register_operand" "=&c")
16088 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16089 (match_operand:QI 2 "register_operand" "a")
16090 (match_operand:SI 3 "immediate_operand" "i")
16091 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16093 (clobber (match_operand:SI 1 "register_operand" "=D"))
16094 (clobber (reg:CC 17))]
16097 [(set_attr "type" "str")
16098 (set_attr "mode" "QI")
16099 (set_attr "prefix_rep" "1")])
16101 (define_insn "*strlenqi_rex_1"
16102 [(set (match_operand:DI 0 "register_operand" "=&c")
16103 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16104 (match_operand:QI 2 "register_operand" "a")
16105 (match_operand:DI 3 "immediate_operand" "i")
16106 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16108 (clobber (match_operand:DI 1 "register_operand" "=D"))
16109 (clobber (reg:CC 17))]
16112 [(set_attr "type" "str")
16113 (set_attr "mode" "QI")
16114 (set_attr "prefix_rep" "1")])
16116 ;; Peephole optimizations to clean up after cmpstr*. This should be
16117 ;; handled in combine, but it is not currently up to the task.
16118 ;; When used for their truth value, the cmpstr* expanders generate
16127 ;; The intermediate three instructions are unnecessary.
16129 ;; This one handles cmpstr*_nz_1...
16133 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16134 (mem:BLK (match_operand 5 "register_operand" ""))))
16135 (use (match_operand 6 "register_operand" ""))
16136 (use (match_operand:SI 3 "immediate_operand" ""))
16138 (clobber (match_operand 0 "register_operand" ""))
16139 (clobber (match_operand 1 "register_operand" ""))
16140 (clobber (match_operand 2 "register_operand" ""))])
16141 (set (match_operand:QI 7 "register_operand" "")
16142 (gtu:QI (reg:CC 17) (const_int 0)))
16143 (set (match_operand:QI 8 "register_operand" "")
16144 (ltu:QI (reg:CC 17) (const_int 0)))
16146 (compare (match_dup 7) (match_dup 8)))
16148 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16151 (compare:CC (mem:BLK (match_dup 4))
16152 (mem:BLK (match_dup 5))))
16153 (use (match_dup 6))
16154 (use (match_dup 3))
16156 (clobber (match_dup 0))
16157 (clobber (match_dup 1))
16158 (clobber (match_dup 2))])]
16161 ;; ...and this one handles cmpstr*_1.
16165 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16167 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16168 (mem:BLK (match_operand 5 "register_operand" "")))
16170 (use (match_operand:SI 3 "immediate_operand" ""))
16173 (clobber (match_operand 0 "register_operand" ""))
16174 (clobber (match_operand 1 "register_operand" ""))
16175 (clobber (match_operand 2 "register_operand" ""))])
16176 (set (match_operand:QI 7 "register_operand" "")
16177 (gtu:QI (reg:CC 17) (const_int 0)))
16178 (set (match_operand:QI 8 "register_operand" "")
16179 (ltu:QI (reg:CC 17) (const_int 0)))
16181 (compare (match_dup 7) (match_dup 8)))
16183 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16186 (if_then_else:CC (ne (match_dup 6)
16188 (compare:CC (mem:BLK (match_dup 4))
16189 (mem:BLK (match_dup 5)))
16191 (use (match_dup 3))
16194 (clobber (match_dup 0))
16195 (clobber (match_dup 1))
16196 (clobber (match_dup 2))])]
16201 ;; Conditional move instructions.
16203 (define_expand "movdicc"
16204 [(set (match_operand:DI 0 "register_operand" "")
16205 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16206 (match_operand:DI 2 "general_operand" "")
16207 (match_operand:DI 3 "general_operand" "")))]
16209 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16211 (define_insn "x86_movdicc_0_m1_rex64"
16212 [(set (match_operand:DI 0 "register_operand" "=r")
16213 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16216 (clobber (reg:CC 17))]
16219 ; Since we don't have the proper number of operands for an alu insn,
16220 ; fill in all the blanks.
16221 [(set_attr "type" "alu")
16222 (set_attr "pent_pair" "pu")
16223 (set_attr "memory" "none")
16224 (set_attr "imm_disp" "false")
16225 (set_attr "mode" "DI")
16226 (set_attr "length_immediate" "0")])
16228 (define_insn "movdicc_c_rex64"
16229 [(set (match_operand:DI 0 "register_operand" "=r,r")
16230 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16231 [(reg 17) (const_int 0)])
16232 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16233 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16234 "TARGET_64BIT && TARGET_CMOVE
16235 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16237 cmov%O2%C1\t{%2, %0|%0, %2}
16238 cmov%O2%c1\t{%3, %0|%0, %3}"
16239 [(set_attr "type" "icmov")
16240 (set_attr "mode" "DI")])
16242 (define_expand "movsicc"
16243 [(set (match_operand:SI 0 "register_operand" "")
16244 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16245 (match_operand:SI 2 "general_operand" "")
16246 (match_operand:SI 3 "general_operand" "")))]
16248 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16250 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16251 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16252 ;; So just document what we're doing explicitly.
16254 (define_insn "x86_movsicc_0_m1"
16255 [(set (match_operand:SI 0 "register_operand" "=r")
16256 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16259 (clobber (reg:CC 17))]
16262 ; Since we don't have the proper number of operands for an alu insn,
16263 ; fill in all the blanks.
16264 [(set_attr "type" "alu")
16265 (set_attr "pent_pair" "pu")
16266 (set_attr "memory" "none")
16267 (set_attr "imm_disp" "false")
16268 (set_attr "mode" "SI")
16269 (set_attr "length_immediate" "0")])
16271 (define_insn "*movsicc_noc"
16272 [(set (match_operand:SI 0 "register_operand" "=r,r")
16273 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
16274 [(reg 17) (const_int 0)])
16275 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
16276 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
16278 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16280 cmov%O2%C1\t{%2, %0|%0, %2}
16281 cmov%O2%c1\t{%3, %0|%0, %3}"
16282 [(set_attr "type" "icmov")
16283 (set_attr "mode" "SI")])
16285 (define_expand "movhicc"
16286 [(set (match_operand:HI 0 "register_operand" "")
16287 (if_then_else:HI (match_operand 1 "comparison_operator" "")
16288 (match_operand:HI 2 "general_operand" "")
16289 (match_operand:HI 3 "general_operand" "")))]
16290 "TARGET_HIMODE_MATH"
16291 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16293 (define_insn "*movhicc_noc"
16294 [(set (match_operand:HI 0 "register_operand" "=r,r")
16295 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
16296 [(reg 17) (const_int 0)])
16297 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
16298 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
16300 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16302 cmov%O2%C1\t{%2, %0|%0, %2}
16303 cmov%O2%c1\t{%3, %0|%0, %3}"
16304 [(set_attr "type" "icmov")
16305 (set_attr "mode" "HI")])
16307 (define_expand "movqicc"
16308 [(set (match_operand:QI 0 "register_operand" "")
16309 (if_then_else:QI (match_operand 1 "comparison_operator" "")
16310 (match_operand:QI 2 "general_operand" "")
16311 (match_operand:QI 3 "general_operand" "")))]
16312 "TARGET_QIMODE_MATH"
16313 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16315 (define_insn_and_split "*movqicc_noc"
16316 [(set (match_operand:QI 0 "register_operand" "=r,r")
16317 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16318 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16319 (match_operand:QI 2 "register_operand" "r,0")
16320 (match_operand:QI 3 "register_operand" "0,r")))]
16321 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16323 "&& reload_completed"
16324 [(set (match_dup 0)
16325 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16328 "operands[0] = gen_lowpart (SImode, operands[0]);
16329 operands[2] = gen_lowpart (SImode, operands[2]);
16330 operands[3] = gen_lowpart (SImode, operands[3]);"
16331 [(set_attr "type" "icmov")
16332 (set_attr "mode" "SI")])
16334 (define_expand "movsfcc"
16335 [(set (match_operand:SF 0 "register_operand" "")
16336 (if_then_else:SF (match_operand 1 "comparison_operator" "")
16337 (match_operand:SF 2 "register_operand" "")
16338 (match_operand:SF 3 "register_operand" "")))]
16340 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16342 (define_insn "*movsfcc_1"
16343 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16344 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16345 [(reg 17) (const_int 0)])
16346 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16347 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16349 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16351 fcmov%F1\t{%2, %0|%0, %2}
16352 fcmov%f1\t{%3, %0|%0, %3}
16353 cmov%O2%C1\t{%2, %0|%0, %2}
16354 cmov%O2%c1\t{%3, %0|%0, %3}"
16355 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16356 (set_attr "mode" "SF,SF,SI,SI")])
16358 (define_expand "movdfcc"
16359 [(set (match_operand:DF 0 "register_operand" "")
16360 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16361 (match_operand:DF 2 "register_operand" "")
16362 (match_operand:DF 3 "register_operand" "")))]
16364 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16366 (define_insn "*movdfcc_1"
16367 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
16368 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16369 [(reg 17) (const_int 0)])
16370 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16371 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16372 "!TARGET_64BIT && TARGET_CMOVE
16373 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16375 fcmov%F1\t{%2, %0|%0, %2}
16376 fcmov%f1\t{%3, %0|%0, %3}
16379 [(set_attr "type" "fcmov,fcmov,multi,multi")
16380 (set_attr "mode" "DF")])
16382 (define_insn "*movdfcc_1_rex64"
16383 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16384 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16385 [(reg 17) (const_int 0)])
16386 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
16387 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
16388 "TARGET_64BIT && TARGET_CMOVE
16389 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16391 fcmov%F1\t{%2, %0|%0, %2}
16392 fcmov%f1\t{%3, %0|%0, %3}
16393 cmov%O2%C1\t{%2, %0|%0, %2}
16394 cmov%O2%c1\t{%3, %0|%0, %3}"
16395 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16396 (set_attr "mode" "DF")])
16399 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16400 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16401 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16402 (match_operand:DF 2 "nonimmediate_operand" "")
16403 (match_operand:DF 3 "nonimmediate_operand" "")))]
16404 "!TARGET_64BIT && reload_completed"
16405 [(set (match_dup 2)
16406 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16410 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16413 "split_di (operands+2, 1, operands+5, operands+6);
16414 split_di (operands+3, 1, operands+7, operands+8);
16415 split_di (operands, 1, operands+2, operands+3);")
16417 (define_expand "movxfcc"
16418 [(set (match_operand:XF 0 "register_operand" "")
16419 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16420 (match_operand:XF 2 "register_operand" "")
16421 (match_operand:XF 3 "register_operand" "")))]
16423 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16425 (define_insn "*movxfcc_1"
16426 [(set (match_operand:XF 0 "register_operand" "=f,f")
16427 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16428 [(reg 17) (const_int 0)])
16429 (match_operand:XF 2 "register_operand" "f,0")
16430 (match_operand:XF 3 "register_operand" "0,f")))]
16433 fcmov%F1\t{%2, %0|%0, %2}
16434 fcmov%f1\t{%3, %0|%0, %3}"
16435 [(set_attr "type" "fcmov")
16436 (set_attr "mode" "XF")])
16438 (define_expand "minsf3"
16440 (set (match_operand:SF 0 "register_operand" "")
16441 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16442 (match_operand:SF 2 "nonimmediate_operand" ""))
16445 (clobber (reg:CC 17))])]
16449 (define_insn "*minsf"
16450 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16451 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16452 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16455 (clobber (reg:CC 17))]
16456 "TARGET_SSE && TARGET_IEEE_FP"
16459 (define_insn "*minsf_nonieee"
16460 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16461 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16462 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16465 (clobber (reg:CC 17))]
16466 "TARGET_SSE && !TARGET_IEEE_FP
16467 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16471 [(set (match_operand:SF 0 "register_operand" "")
16472 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16473 (match_operand:SF 2 "nonimmediate_operand" ""))
16474 (match_operand:SF 3 "register_operand" "")
16475 (match_operand:SF 4 "nonimmediate_operand" "")))
16476 (clobber (reg:CC 17))]
16477 "SSE_REG_P (operands[0]) && reload_completed
16478 && ((operands_match_p (operands[1], operands[3])
16479 && operands_match_p (operands[2], operands[4]))
16480 || (operands_match_p (operands[1], operands[4])
16481 && operands_match_p (operands[2], operands[3])))"
16482 [(set (match_dup 0)
16483 (if_then_else:SF (lt (match_dup 1)
16488 ;; Conditional addition patterns
16489 (define_expand "addqicc"
16490 [(match_operand:QI 0 "register_operand" "")
16491 (match_operand 1 "comparison_operator" "")
16492 (match_operand:QI 2 "register_operand" "")
16493 (match_operand:QI 3 "const_int_operand" "")]
16495 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16497 (define_expand "addhicc"
16498 [(match_operand:HI 0 "register_operand" "")
16499 (match_operand 1 "comparison_operator" "")
16500 (match_operand:HI 2 "register_operand" "")
16501 (match_operand:HI 3 "const_int_operand" "")]
16503 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16505 (define_expand "addsicc"
16506 [(match_operand:SI 0 "register_operand" "")
16507 (match_operand 1 "comparison_operator" "")
16508 (match_operand:SI 2 "register_operand" "")
16509 (match_operand:SI 3 "const_int_operand" "")]
16511 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16513 (define_expand "adddicc"
16514 [(match_operand:DI 0 "register_operand" "")
16515 (match_operand 1 "comparison_operator" "")
16516 (match_operand:DI 2 "register_operand" "")
16517 (match_operand:DI 3 "const_int_operand" "")]
16519 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16521 ;; We can't represent the LT test directly. Do this by swapping the operands.
16524 [(set (match_operand:SF 0 "fp_register_operand" "")
16525 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16526 (match_operand:SF 2 "register_operand" ""))
16527 (match_operand:SF 3 "register_operand" "")
16528 (match_operand:SF 4 "register_operand" "")))
16529 (clobber (reg:CC 17))]
16531 && ((operands_match_p (operands[1], operands[3])
16532 && operands_match_p (operands[2], operands[4]))
16533 || (operands_match_p (operands[1], operands[4])
16534 && operands_match_p (operands[2], operands[3])))"
16535 [(set (reg:CCFP 17)
16536 (compare:CCFP (match_dup 2)
16539 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
16543 (define_insn "*minsf_sse"
16544 [(set (match_operand:SF 0 "register_operand" "=x")
16545 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
16546 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16549 "TARGET_SSE && reload_completed"
16550 "minss\t{%2, %0|%0, %2}"
16551 [(set_attr "type" "sse")
16552 (set_attr "mode" "SF")])
16554 (define_expand "mindf3"
16556 (set (match_operand:DF 0 "register_operand" "")
16557 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16558 (match_operand:DF 2 "nonimmediate_operand" ""))
16561 (clobber (reg:CC 17))])]
16562 "TARGET_SSE2 && TARGET_SSE_MATH"
16565 (define_insn "*mindf"
16566 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16567 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16568 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16571 (clobber (reg:CC 17))]
16572 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16575 (define_insn "*mindf_nonieee"
16576 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16577 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16578 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16581 (clobber (reg:CC 17))]
16582 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16583 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16587 [(set (match_operand:DF 0 "register_operand" "")
16588 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16589 (match_operand:DF 2 "nonimmediate_operand" ""))
16590 (match_operand:DF 3 "register_operand" "")
16591 (match_operand:DF 4 "nonimmediate_operand" "")))
16592 (clobber (reg:CC 17))]
16593 "SSE_REG_P (operands[0]) && reload_completed
16594 && ((operands_match_p (operands[1], operands[3])
16595 && operands_match_p (operands[2], operands[4]))
16596 || (operands_match_p (operands[1], operands[4])
16597 && operands_match_p (operands[2], operands[3])))"
16598 [(set (match_dup 0)
16599 (if_then_else:DF (lt (match_dup 1)
16604 ;; We can't represent the LT test directly. Do this by swapping the operands.
16606 [(set (match_operand:DF 0 "fp_register_operand" "")
16607 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16608 (match_operand:DF 2 "register_operand" ""))
16609 (match_operand:DF 3 "register_operand" "")
16610 (match_operand:DF 4 "register_operand" "")))
16611 (clobber (reg:CC 17))]
16613 && ((operands_match_p (operands[1], operands[3])
16614 && operands_match_p (operands[2], operands[4]))
16615 || (operands_match_p (operands[1], operands[4])
16616 && operands_match_p (operands[2], operands[3])))"
16617 [(set (reg:CCFP 17)
16618 (compare:CCFP (match_dup 2)
16621 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
16625 (define_insn "*mindf_sse"
16626 [(set (match_operand:DF 0 "register_operand" "=Y")
16627 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
16628 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16631 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16632 "minsd\t{%2, %0|%0, %2}"
16633 [(set_attr "type" "sse")
16634 (set_attr "mode" "DF")])
16636 (define_expand "maxsf3"
16638 (set (match_operand:SF 0 "register_operand" "")
16639 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16640 (match_operand:SF 2 "nonimmediate_operand" ""))
16643 (clobber (reg:CC 17))])]
16647 (define_insn "*maxsf"
16648 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16649 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
16650 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16653 (clobber (reg:CC 17))]
16654 "TARGET_SSE && TARGET_IEEE_FP"
16657 (define_insn "*maxsf_nonieee"
16658 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16659 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16660 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16663 (clobber (reg:CC 17))]
16664 "TARGET_SSE && !TARGET_IEEE_FP
16665 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16669 [(set (match_operand:SF 0 "register_operand" "")
16670 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16671 (match_operand:SF 2 "nonimmediate_operand" ""))
16672 (match_operand:SF 3 "register_operand" "")
16673 (match_operand:SF 4 "nonimmediate_operand" "")))
16674 (clobber (reg:CC 17))]
16675 "SSE_REG_P (operands[0]) && reload_completed
16676 && ((operands_match_p (operands[1], operands[3])
16677 && operands_match_p (operands[2], operands[4]))
16678 || (operands_match_p (operands[1], operands[4])
16679 && operands_match_p (operands[2], operands[3])))"
16680 [(set (match_dup 0)
16681 (if_then_else:SF (gt (match_dup 1)
16687 [(set (match_operand:SF 0 "fp_register_operand" "")
16688 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16689 (match_operand:SF 2 "register_operand" ""))
16690 (match_operand:SF 3 "register_operand" "")
16691 (match_operand:SF 4 "register_operand" "")))
16692 (clobber (reg:CC 17))]
16694 && ((operands_match_p (operands[1], operands[3])
16695 && operands_match_p (operands[2], operands[4]))
16696 || (operands_match_p (operands[1], operands[4])
16697 && operands_match_p (operands[2], operands[3])))"
16698 [(set (reg:CCFP 17)
16699 (compare:CCFP (match_dup 1)
16702 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16706 (define_insn "*maxsf_sse"
16707 [(set (match_operand:SF 0 "register_operand" "=x")
16708 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16709 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16712 "TARGET_SSE && reload_completed"
16713 "maxss\t{%2, %0|%0, %2}"
16714 [(set_attr "type" "sse")
16715 (set_attr "mode" "SF")])
16717 (define_expand "maxdf3"
16719 (set (match_operand:DF 0 "register_operand" "")
16720 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16721 (match_operand:DF 2 "nonimmediate_operand" ""))
16724 (clobber (reg:CC 17))])]
16725 "TARGET_SSE2 && TARGET_SSE_MATH"
16728 (define_insn "*maxdf"
16729 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16730 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16731 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16734 (clobber (reg:CC 17))]
16735 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16738 (define_insn "*maxdf_nonieee"
16739 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16740 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16741 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16744 (clobber (reg:CC 17))]
16745 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16746 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16750 [(set (match_operand:DF 0 "register_operand" "")
16751 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16752 (match_operand:DF 2 "nonimmediate_operand" ""))
16753 (match_operand:DF 3 "register_operand" "")
16754 (match_operand:DF 4 "nonimmediate_operand" "")))
16755 (clobber (reg:CC 17))]
16756 "SSE_REG_P (operands[0]) && reload_completed
16757 && ((operands_match_p (operands[1], operands[3])
16758 && operands_match_p (operands[2], operands[4]))
16759 || (operands_match_p (operands[1], operands[4])
16760 && operands_match_p (operands[2], operands[3])))"
16761 [(set (match_dup 0)
16762 (if_then_else:DF (gt (match_dup 1)
16768 [(set (match_operand:DF 0 "fp_register_operand" "")
16769 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16770 (match_operand:DF 2 "register_operand" ""))
16771 (match_operand:DF 3 "register_operand" "")
16772 (match_operand:DF 4 "register_operand" "")))
16773 (clobber (reg:CC 17))]
16775 && ((operands_match_p (operands[1], operands[3])
16776 && operands_match_p (operands[2], operands[4]))
16777 || (operands_match_p (operands[1], operands[4])
16778 && operands_match_p (operands[2], operands[3])))"
16779 [(set (reg:CCFP 17)
16780 (compare:CCFP (match_dup 1)
16783 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16787 (define_insn "*maxdf_sse"
16788 [(set (match_operand:DF 0 "register_operand" "=Y")
16789 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16790 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16793 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16794 "maxsd\t{%2, %0|%0, %2}"
16795 [(set_attr "type" "sse")
16796 (set_attr "mode" "DF")])
16798 ;; Misc patterns (?)
16800 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16801 ;; Otherwise there will be nothing to keep
16803 ;; [(set (reg ebp) (reg esp))]
16804 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16805 ;; (clobber (eflags)]
16806 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16808 ;; in proper program order.
16809 (define_insn "pro_epilogue_adjust_stack_1"
16810 [(set (match_operand:SI 0 "register_operand" "=r,r")
16811 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16812 (match_operand:SI 2 "immediate_operand" "i,i")))
16813 (clobber (reg:CC 17))
16814 (clobber (mem:BLK (scratch)))]
16817 switch (get_attr_type (insn))
16820 return "mov{l}\t{%1, %0|%0, %1}";
16823 if (GET_CODE (operands[2]) == CONST_INT
16824 && (INTVAL (operands[2]) == 128
16825 || (INTVAL (operands[2]) < 0
16826 && INTVAL (operands[2]) != -128)))
16828 operands[2] = GEN_INT (-INTVAL (operands[2]));
16829 return "sub{l}\t{%2, %0|%0, %2}";
16831 return "add{l}\t{%2, %0|%0, %2}";
16834 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16835 return "lea{l}\t{%a2, %0|%0, %a2}";
16841 [(set (attr "type")
16842 (cond [(eq_attr "alternative" "0")
16843 (const_string "alu")
16844 (match_operand:SI 2 "const0_operand" "")
16845 (const_string "imov")
16847 (const_string "lea")))
16848 (set_attr "mode" "SI")])
16850 (define_insn "pro_epilogue_adjust_stack_rex64"
16851 [(set (match_operand:DI 0 "register_operand" "=r,r")
16852 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16853 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16854 (clobber (reg:CC 17))
16855 (clobber (mem:BLK (scratch)))]
16858 switch (get_attr_type (insn))
16861 return "mov{q}\t{%1, %0|%0, %1}";
16864 if (GET_CODE (operands[2]) == CONST_INT
16865 /* Avoid overflows. */
16866 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
16867 && (INTVAL (operands[2]) == 128
16868 || (INTVAL (operands[2]) < 0
16869 && INTVAL (operands[2]) != -128)))
16871 operands[2] = GEN_INT (-INTVAL (operands[2]));
16872 return "sub{q}\t{%2, %0|%0, %2}";
16874 return "add{q}\t{%2, %0|%0, %2}";
16877 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16878 return "lea{q}\t{%a2, %0|%0, %a2}";
16884 [(set (attr "type")
16885 (cond [(eq_attr "alternative" "0")
16886 (const_string "alu")
16887 (match_operand:DI 2 "const0_operand" "")
16888 (const_string "imov")
16890 (const_string "lea")))
16891 (set_attr "mode" "DI")])
16893 (define_insn "pro_epilogue_adjust_stack_rex64_2"
16894 [(set (match_operand:DI 0 "register_operand" "=r,r")
16895 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16896 (match_operand:DI 3 "immediate_operand" "i,i")))
16897 (use (match_operand:DI 2 "register_operand" "r,r"))
16898 (clobber (reg:CC 17))
16899 (clobber (mem:BLK (scratch)))]
16902 switch (get_attr_type (insn))
16905 return "add{q}\t{%2, %0|%0, %2}";
16908 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
16909 return "lea{q}\t{%a2, %0|%0, %a2}";
16915 [(set_attr "type" "alu,lea")
16916 (set_attr "mode" "DI")])
16918 ;; Placeholder for the conditional moves. This one is split either to SSE
16919 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16920 ;; fact is that compares supported by the cmp??ss instructions are exactly
16921 ;; swapped of those supported by cmove sequence.
16922 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16923 ;; supported by i387 comparisons and we do need to emit two conditional moves
16926 (define_insn "sse_movsfcc"
16927 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16928 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16929 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16930 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16931 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16932 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16933 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16934 (clobber (reg:CC 17))]
16936 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16937 /* Avoid combine from being smart and converting min/max
16938 instruction patterns into conditional moves. */
16939 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
16940 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
16941 || !rtx_equal_p (operands[4], operands[2])
16942 || !rtx_equal_p (operands[5], operands[3]))
16943 && (!TARGET_IEEE_FP
16944 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16947 (define_insn "sse_movsfcc_eq"
16948 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16949 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16950 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16951 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16952 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16953 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16954 (clobber (reg:CC 17))]
16956 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16959 (define_insn "sse_movdfcc"
16960 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
16961 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16962 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
16963 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
16964 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
16965 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
16966 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16967 (clobber (reg:CC 17))]
16969 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16970 /* Avoid combine from being smart and converting min/max
16971 instruction patterns into conditional moves. */
16972 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
16973 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
16974 || !rtx_equal_p (operands[4], operands[2])
16975 || !rtx_equal_p (operands[5], operands[3]))
16976 && (!TARGET_IEEE_FP
16977 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16980 (define_insn "sse_movdfcc_eq"
16981 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
16982 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
16983 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
16984 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
16985 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
16986 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16987 (clobber (reg:CC 17))]
16989 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16992 ;; For non-sse moves just expand the usual cmove sequence.
16994 [(set (match_operand 0 "register_operand" "")
16995 (if_then_else (match_operator 1 "comparison_operator"
16996 [(match_operand 4 "nonimmediate_operand" "")
16997 (match_operand 5 "register_operand" "")])
16998 (match_operand 2 "nonimmediate_operand" "")
16999 (match_operand 3 "nonimmediate_operand" "")))
17000 (clobber (match_operand 6 "" ""))
17001 (clobber (reg:CC 17))]
17002 "!SSE_REG_P (operands[0]) && reload_completed
17003 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17006 ix86_compare_op0 = operands[5];
17007 ix86_compare_op1 = operands[4];
17008 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17009 VOIDmode, operands[5], operands[4]);
17010 ix86_expand_fp_movcc (operands);
17014 ;; Split SSE based conditional move into sequence:
17015 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17016 ;; and op2, op0 - zero op2 if comparison was false
17017 ;; nand op0, op3 - load op3 to op0 if comparison was false
17018 ;; or op2, op0 - get the nonzero one into the result.
17020 [(set (match_operand 0 "register_operand" "")
17021 (if_then_else (match_operator 1 "sse_comparison_operator"
17022 [(match_operand 4 "register_operand" "")
17023 (match_operand 5 "nonimmediate_operand" "")])
17024 (match_operand 2 "register_operand" "")
17025 (match_operand 3 "register_operand" "")))
17026 (clobber (match_operand 6 "" ""))
17027 (clobber (reg:CC 17))]
17028 "SSE_REG_P (operands[0]) && reload_completed"
17029 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17030 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17031 (subreg:TI (match_dup 4) 0)))
17032 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17033 (subreg:TI (match_dup 3) 0)))
17034 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17035 (subreg:TI (match_dup 7) 0)))]
17037 if (GET_MODE (operands[2]) == DFmode
17038 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17040 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17041 emit_insn (gen_sse2_unpcklpd (op, op, op));
17042 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17043 emit_insn (gen_sse2_unpcklpd (op, op, op));
17046 /* If op2 == op3, op3 would be clobbered before it is used. */
17047 if (operands_match_p (operands[2], operands[3]))
17049 emit_move_insn (operands[0], operands[2]);
17053 PUT_MODE (operands[1], GET_MODE (operands[0]));
17054 if (operands_match_p (operands[0], operands[4]))
17055 operands[6] = operands[4], operands[7] = operands[2];
17057 operands[6] = operands[2], operands[7] = operands[4];
17060 ;; Special case of conditional move we can handle effectively.
17061 ;; Do not brother with the integer/floating point case, since these are
17062 ;; bot considerably slower, unlike in the generic case.
17063 (define_insn "*sse_movsfcc_const0_1"
17064 [(set (match_operand:SF 0 "register_operand" "=&x")
17065 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17066 [(match_operand:SF 4 "register_operand" "0")
17067 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17068 (match_operand:SF 2 "register_operand" "x")
17069 (match_operand:SF 3 "const0_operand" "X")))]
17073 (define_insn "*sse_movsfcc_const0_2"
17074 [(set (match_operand:SF 0 "register_operand" "=&x")
17075 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17076 [(match_operand:SF 4 "register_operand" "0")
17077 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17078 (match_operand:SF 2 "const0_operand" "X")
17079 (match_operand:SF 3 "register_operand" "x")))]
17083 (define_insn "*sse_movsfcc_const0_3"
17084 [(set (match_operand:SF 0 "register_operand" "=&x")
17085 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17086 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17087 (match_operand:SF 5 "register_operand" "0")])
17088 (match_operand:SF 2 "register_operand" "x")
17089 (match_operand:SF 3 "const0_operand" "X")))]
17093 (define_insn "*sse_movsfcc_const0_4"
17094 [(set (match_operand:SF 0 "register_operand" "=&x")
17095 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17096 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17097 (match_operand:SF 5 "register_operand" "0")])
17098 (match_operand:SF 2 "const0_operand" "X")
17099 (match_operand:SF 3 "register_operand" "x")))]
17103 (define_insn "*sse_movdfcc_const0_1"
17104 [(set (match_operand:DF 0 "register_operand" "=&Y")
17105 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17106 [(match_operand:DF 4 "register_operand" "0")
17107 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17108 (match_operand:DF 2 "register_operand" "Y")
17109 (match_operand:DF 3 "const0_operand" "X")))]
17113 (define_insn "*sse_movdfcc_const0_2"
17114 [(set (match_operand:DF 0 "register_operand" "=&Y")
17115 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17116 [(match_operand:DF 4 "register_operand" "0")
17117 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17118 (match_operand:DF 2 "const0_operand" "X")
17119 (match_operand:DF 3 "register_operand" "Y")))]
17123 (define_insn "*sse_movdfcc_const0_3"
17124 [(set (match_operand:DF 0 "register_operand" "=&Y")
17125 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17126 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17127 (match_operand:DF 5 "register_operand" "0")])
17128 (match_operand:DF 2 "register_operand" "Y")
17129 (match_operand:DF 3 "const0_operand" "X")))]
17133 (define_insn "*sse_movdfcc_const0_4"
17134 [(set (match_operand:DF 0 "register_operand" "=&Y")
17135 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17136 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17137 (match_operand:DF 5 "register_operand" "0")])
17138 (match_operand:DF 2 "const0_operand" "X")
17139 (match_operand:DF 3 "register_operand" "Y")))]
17144 [(set (match_operand 0 "register_operand" "")
17145 (if_then_else (match_operator 1 "comparison_operator"
17146 [(match_operand 4 "nonimmediate_operand" "")
17147 (match_operand 5 "nonimmediate_operand" "")])
17148 (match_operand 2 "nonmemory_operand" "")
17149 (match_operand 3 "nonmemory_operand" "")))]
17150 "SSE_REG_P (operands[0]) && reload_completed
17151 && (const0_operand (operands[2], GET_MODE (operands[0]))
17152 || const0_operand (operands[3], GET_MODE (operands[0])))"
17153 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17154 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17157 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17158 && GET_MODE (operands[2]) == DFmode)
17160 if (REG_P (operands[2]))
17162 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17163 emit_insn (gen_sse2_unpcklpd (op, op, op));
17165 if (REG_P (operands[3]))
17167 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17168 emit_insn (gen_sse2_unpcklpd (op, op, op));
17171 PUT_MODE (operands[1], GET_MODE (operands[0]));
17172 if (!sse_comparison_operator (operands[1], VOIDmode)
17173 || !rtx_equal_p (operands[0], operands[4]))
17175 rtx tmp = operands[5];
17176 operands[5] = operands[4];
17178 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17180 if (!rtx_equal_p (operands[0], operands[4]))
17182 if (const0_operand (operands[2], GET_MODE (operands[0])))
17184 operands[7] = operands[3];
17185 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17190 operands[7] = operands[2];
17191 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17193 operands[7] = simplify_gen_subreg (TImode, operands[7],
17194 GET_MODE (operands[7]), 0);
17197 (define_expand "allocate_stack_worker"
17198 [(match_operand:SI 0 "register_operand" "")]
17199 "TARGET_STACK_PROBE"
17201 if (reload_completed)
17204 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
17206 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
17211 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17213 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17218 (define_insn "allocate_stack_worker_1"
17219 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17220 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17221 (clobber (match_scratch:SI 1 "=0"))
17222 (clobber (reg:CC 17))]
17223 "!TARGET_64BIT && TARGET_STACK_PROBE"
17225 [(set_attr "type" "multi")
17226 (set_attr "length" "5")])
17228 (define_expand "allocate_stack_worker_postreload"
17229 [(parallel [(unspec:SI [(match_operand:SI 0 "register_operand" "a")]
17230 UNSPEC_STACK_PROBE)
17231 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17232 (clobber (match_dup 0))
17233 (clobber (reg:CC 17))])]
17237 (define_insn "allocate_stack_worker_rex64"
17238 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17239 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17240 (clobber (match_scratch:DI 1 "=0"))
17241 (clobber (reg:CC 17))]
17242 "TARGET_64BIT && TARGET_STACK_PROBE"
17244 [(set_attr "type" "multi")
17245 (set_attr "length" "5")])
17247 (define_expand "allocate_stack_worker_rex64_postreload"
17248 [(parallel [(unspec:DI [(match_operand:DI 0 "register_operand" "a")]
17249 UNSPEC_STACK_PROBE)
17250 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17251 (clobber (match_dup 0))
17252 (clobber (reg:CC 17))])]
17256 (define_expand "allocate_stack"
17257 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17258 (minus:SI (reg:SI 7)
17259 (match_operand:SI 1 "general_operand" "")))
17260 (clobber (reg:CC 17))])
17261 (parallel [(set (reg:SI 7)
17262 (minus:SI (reg:SI 7) (match_dup 1)))
17263 (clobber (reg:CC 17))])]
17264 "TARGET_STACK_PROBE"
17266 #ifdef CHECK_STACK_LIMIT
17267 if (GET_CODE (operands[1]) == CONST_INT
17268 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17269 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17273 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17276 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
17280 (define_expand "builtin_setjmp_receiver"
17281 [(label_ref (match_operand 0 "" ""))]
17282 "!TARGET_64BIT && flag_pic"
17284 emit_insn (gen_set_got (pic_offset_table_rtx));
17288 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
17291 [(set (match_operand 0 "register_operand" "")
17292 (match_operator 3 "promotable_binary_operator"
17293 [(match_operand 1 "register_operand" "")
17294 (match_operand 2 "aligned_operand" "")]))
17295 (clobber (reg:CC 17))]
17296 "! TARGET_PARTIAL_REG_STALL && reload_completed
17297 && ((GET_MODE (operands[0]) == HImode
17298 && ((!optimize_size && !TARGET_FAST_PREFIX)
17299 || GET_CODE (operands[2]) != CONST_INT
17300 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
17301 || (GET_MODE (operands[0]) == QImode
17302 && (TARGET_PROMOTE_QImode || optimize_size)))"
17303 [(parallel [(set (match_dup 0)
17304 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17305 (clobber (reg:CC 17))])]
17306 "operands[0] = gen_lowpart (SImode, operands[0]);
17307 operands[1] = gen_lowpart (SImode, operands[1]);
17308 if (GET_CODE (operands[3]) != ASHIFT)
17309 operands[2] = gen_lowpart (SImode, operands[2]);
17310 PUT_MODE (operands[3], SImode);")
17312 ; Promote the QImode tests, as i386 has encoding of the AND
17313 ; instruction with 32-bit sign-extended immediate and thus the
17314 ; instruction size is unchanged, except in the %eax case for
17315 ; which it is increased by one byte, hence the ! optimize_size.
17318 (compare (and (match_operand 1 "aligned_operand" "")
17319 (match_operand 2 "const_int_operand" ""))
17321 (set (match_operand 0 "register_operand" "")
17322 (and (match_dup 1) (match_dup 2)))]
17323 "! TARGET_PARTIAL_REG_STALL && reload_completed
17324 /* Ensure that the operand will remain sign-extended immediate. */
17325 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
17327 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
17328 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
17329 [(parallel [(set (reg:CCNO 17)
17330 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17333 (and:SI (match_dup 1) (match_dup 2)))])]
17335 = gen_int_mode (INTVAL (operands[2])
17336 & GET_MODE_MASK (GET_MODE (operands[0])),
17338 operands[0] = gen_lowpart (SImode, operands[0]);
17339 operands[1] = gen_lowpart (SImode, operands[1]);")
17341 ; Don't promote the QImode tests, as i386 doesn't have encoding of
17342 ; the TEST instruction with 32-bit sign-extended immediate and thus
17343 ; the instruction size would at least double, which is not what we
17344 ; want even with ! optimize_size.
17347 (compare (and (match_operand:HI 0 "aligned_operand" "")
17348 (match_operand:HI 1 "const_int_operand" ""))
17350 "! TARGET_PARTIAL_REG_STALL && reload_completed
17351 /* Ensure that the operand will remain sign-extended immediate. */
17352 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
17353 && ! TARGET_FAST_PREFIX
17354 && ! optimize_size"
17355 [(set (reg:CCNO 17)
17356 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17359 = gen_int_mode (INTVAL (operands[1])
17360 & GET_MODE_MASK (GET_MODE (operands[0])),
17362 operands[0] = gen_lowpart (SImode, operands[0]);")
17365 [(set (match_operand 0 "register_operand" "")
17366 (neg (match_operand 1 "register_operand" "")))
17367 (clobber (reg:CC 17))]
17368 "! TARGET_PARTIAL_REG_STALL && reload_completed
17369 && (GET_MODE (operands[0]) == HImode
17370 || (GET_MODE (operands[0]) == QImode
17371 && (TARGET_PROMOTE_QImode || optimize_size)))"
17372 [(parallel [(set (match_dup 0)
17373 (neg:SI (match_dup 1)))
17374 (clobber (reg:CC 17))])]
17375 "operands[0] = gen_lowpart (SImode, operands[0]);
17376 operands[1] = gen_lowpart (SImode, operands[1]);")
17379 [(set (match_operand 0 "register_operand" "")
17380 (not (match_operand 1 "register_operand" "")))]
17381 "! TARGET_PARTIAL_REG_STALL && reload_completed
17382 && (GET_MODE (operands[0]) == HImode
17383 || (GET_MODE (operands[0]) == QImode
17384 && (TARGET_PROMOTE_QImode || optimize_size)))"
17385 [(set (match_dup 0)
17386 (not:SI (match_dup 1)))]
17387 "operands[0] = gen_lowpart (SImode, operands[0]);
17388 operands[1] = gen_lowpart (SImode, operands[1]);")
17391 [(set (match_operand 0 "register_operand" "")
17392 (if_then_else (match_operator 1 "comparison_operator"
17393 [(reg 17) (const_int 0)])
17394 (match_operand 2 "register_operand" "")
17395 (match_operand 3 "register_operand" "")))]
17396 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
17397 && (GET_MODE (operands[0]) == HImode
17398 || (GET_MODE (operands[0]) == QImode
17399 && (TARGET_PROMOTE_QImode || optimize_size)))"
17400 [(set (match_dup 0)
17401 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
17402 "operands[0] = gen_lowpart (SImode, operands[0]);
17403 operands[2] = gen_lowpart (SImode, operands[2]);
17404 operands[3] = gen_lowpart (SImode, operands[3]);")
17407 ;; RTL Peephole optimizations, run before sched2. These primarily look to
17408 ;; transform a complex memory operation into two memory to register operations.
17410 ;; Don't push memory operands
17412 [(set (match_operand:SI 0 "push_operand" "")
17413 (match_operand:SI 1 "memory_operand" ""))
17414 (match_scratch:SI 2 "r")]
17415 "! optimize_size && ! TARGET_PUSH_MEMORY"
17416 [(set (match_dup 2) (match_dup 1))
17417 (set (match_dup 0) (match_dup 2))]
17421 [(set (match_operand:DI 0 "push_operand" "")
17422 (match_operand:DI 1 "memory_operand" ""))
17423 (match_scratch:DI 2 "r")]
17424 "! optimize_size && ! TARGET_PUSH_MEMORY"
17425 [(set (match_dup 2) (match_dup 1))
17426 (set (match_dup 0) (match_dup 2))]
17429 ;; We need to handle SFmode only, because DFmode and XFmode is split to
17432 [(set (match_operand:SF 0 "push_operand" "")
17433 (match_operand:SF 1 "memory_operand" ""))
17434 (match_scratch:SF 2 "r")]
17435 "! optimize_size && ! TARGET_PUSH_MEMORY"
17436 [(set (match_dup 2) (match_dup 1))
17437 (set (match_dup 0) (match_dup 2))]
17441 [(set (match_operand:HI 0 "push_operand" "")
17442 (match_operand:HI 1 "memory_operand" ""))
17443 (match_scratch:HI 2 "r")]
17444 "! optimize_size && ! TARGET_PUSH_MEMORY"
17445 [(set (match_dup 2) (match_dup 1))
17446 (set (match_dup 0) (match_dup 2))]
17450 [(set (match_operand:QI 0 "push_operand" "")
17451 (match_operand:QI 1 "memory_operand" ""))
17452 (match_scratch:QI 2 "q")]
17453 "! optimize_size && ! TARGET_PUSH_MEMORY"
17454 [(set (match_dup 2) (match_dup 1))
17455 (set (match_dup 0) (match_dup 2))]
17458 ;; Don't move an immediate directly to memory when the instruction
17461 [(match_scratch:SI 1 "r")
17462 (set (match_operand:SI 0 "memory_operand" "")
17465 && ! TARGET_USE_MOV0
17466 && TARGET_SPLIT_LONG_MOVES
17467 && get_attr_length (insn) >= ix86_cost->large_insn
17468 && peep2_regno_dead_p (0, FLAGS_REG)"
17469 [(parallel [(set (match_dup 1) (const_int 0))
17470 (clobber (reg:CC 17))])
17471 (set (match_dup 0) (match_dup 1))]
17475 [(match_scratch:HI 1 "r")
17476 (set (match_operand:HI 0 "memory_operand" "")
17479 && ! TARGET_USE_MOV0
17480 && TARGET_SPLIT_LONG_MOVES
17481 && get_attr_length (insn) >= ix86_cost->large_insn
17482 && peep2_regno_dead_p (0, FLAGS_REG)"
17483 [(parallel [(set (match_dup 2) (const_int 0))
17484 (clobber (reg:CC 17))])
17485 (set (match_dup 0) (match_dup 1))]
17486 "operands[2] = gen_lowpart (SImode, operands[1]);")
17489 [(match_scratch:QI 1 "q")
17490 (set (match_operand:QI 0 "memory_operand" "")
17493 && ! TARGET_USE_MOV0
17494 && TARGET_SPLIT_LONG_MOVES
17495 && get_attr_length (insn) >= ix86_cost->large_insn
17496 && peep2_regno_dead_p (0, FLAGS_REG)"
17497 [(parallel [(set (match_dup 2) (const_int 0))
17498 (clobber (reg:CC 17))])
17499 (set (match_dup 0) (match_dup 1))]
17500 "operands[2] = gen_lowpart (SImode, operands[1]);")
17503 [(match_scratch:SI 2 "r")
17504 (set (match_operand:SI 0 "memory_operand" "")
17505 (match_operand:SI 1 "immediate_operand" ""))]
17507 && get_attr_length (insn) >= ix86_cost->large_insn
17508 && TARGET_SPLIT_LONG_MOVES"
17509 [(set (match_dup 2) (match_dup 1))
17510 (set (match_dup 0) (match_dup 2))]
17514 [(match_scratch:HI 2 "r")
17515 (set (match_operand:HI 0 "memory_operand" "")
17516 (match_operand:HI 1 "immediate_operand" ""))]
17517 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17518 && TARGET_SPLIT_LONG_MOVES"
17519 [(set (match_dup 2) (match_dup 1))
17520 (set (match_dup 0) (match_dup 2))]
17524 [(match_scratch:QI 2 "q")
17525 (set (match_operand:QI 0 "memory_operand" "")
17526 (match_operand:QI 1 "immediate_operand" ""))]
17527 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17528 && TARGET_SPLIT_LONG_MOVES"
17529 [(set (match_dup 2) (match_dup 1))
17530 (set (match_dup 0) (match_dup 2))]
17533 ;; Don't compare memory with zero, load and use a test instead.
17536 (compare (match_operand:SI 0 "memory_operand" "")
17538 (match_scratch:SI 3 "r")]
17539 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17540 [(set (match_dup 3) (match_dup 0))
17541 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17544 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17545 ;; Don't split NOTs with a displacement operand, because resulting XOR
17546 ;; will not be pairable anyway.
17548 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
17549 ;; represented using a modRM byte. The XOR replacement is long decoded,
17550 ;; so this split helps here as well.
17552 ;; Note: Can't do this as a regular split because we can't get proper
17553 ;; lifetime information then.
17556 [(set (match_operand:SI 0 "nonimmediate_operand" "")
17557 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
17559 && peep2_regno_dead_p (0, FLAGS_REG)
17560 && ((TARGET_PENTIUM
17561 && (GET_CODE (operands[0]) != MEM
17562 || !memory_displacement_operand (operands[0], SImode)))
17563 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
17564 [(parallel [(set (match_dup 0)
17565 (xor:SI (match_dup 1) (const_int -1)))
17566 (clobber (reg:CC 17))])]
17570 [(set (match_operand:HI 0 "nonimmediate_operand" "")
17571 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
17573 && peep2_regno_dead_p (0, FLAGS_REG)
17574 && ((TARGET_PENTIUM
17575 && (GET_CODE (operands[0]) != MEM
17576 || !memory_displacement_operand (operands[0], HImode)))
17577 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
17578 [(parallel [(set (match_dup 0)
17579 (xor:HI (match_dup 1) (const_int -1)))
17580 (clobber (reg:CC 17))])]
17584 [(set (match_operand:QI 0 "nonimmediate_operand" "")
17585 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
17587 && peep2_regno_dead_p (0, FLAGS_REG)
17588 && ((TARGET_PENTIUM
17589 && (GET_CODE (operands[0]) != MEM
17590 || !memory_displacement_operand (operands[0], QImode)))
17591 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
17592 [(parallel [(set (match_dup 0)
17593 (xor:QI (match_dup 1) (const_int -1)))
17594 (clobber (reg:CC 17))])]
17597 ;; Non pairable "test imm, reg" instructions can be translated to
17598 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17599 ;; byte opcode instead of two, have a short form for byte operands),
17600 ;; so do it for other CPUs as well. Given that the value was dead,
17601 ;; this should not create any new dependencies. Pass on the sub-word
17602 ;; versions if we're concerned about partial register stalls.
17606 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17607 (match_operand:SI 1 "immediate_operand" ""))
17609 "ix86_match_ccmode (insn, CCNOmode)
17610 && (true_regnum (operands[0]) != 0
17611 || (GET_CODE (operands[1]) == CONST_INT
17612 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17613 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17615 [(set (reg:CCNO 17)
17616 (compare:CCNO (and:SI (match_dup 0)
17620 (and:SI (match_dup 0) (match_dup 1)))])]
17623 ;; We don't need to handle HImode case, because it will be promoted to SImode
17624 ;; on ! TARGET_PARTIAL_REG_STALL
17628 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17629 (match_operand:QI 1 "immediate_operand" ""))
17631 "! TARGET_PARTIAL_REG_STALL
17632 && ix86_match_ccmode (insn, CCNOmode)
17633 && true_regnum (operands[0]) != 0
17634 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17636 [(set (reg:CCNO 17)
17637 (compare:CCNO (and:QI (match_dup 0)
17641 (and:QI (match_dup 0) (match_dup 1)))])]
17649 (match_operand 0 "ext_register_operand" "")
17652 (match_operand 1 "const_int_operand" ""))
17654 "! TARGET_PARTIAL_REG_STALL
17655 && ix86_match_ccmode (insn, CCNOmode)
17656 && true_regnum (operands[0]) != 0
17657 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17658 [(parallel [(set (reg:CCNO 17)
17667 (set (zero_extract:SI (match_dup 0)
17678 ;; Don't do logical operations with memory inputs.
17680 [(match_scratch:SI 2 "r")
17681 (parallel [(set (match_operand:SI 0 "register_operand" "")
17682 (match_operator:SI 3 "arith_or_logical_operator"
17684 (match_operand:SI 1 "memory_operand" "")]))
17685 (clobber (reg:CC 17))])]
17686 "! optimize_size && ! TARGET_READ_MODIFY"
17687 [(set (match_dup 2) (match_dup 1))
17688 (parallel [(set (match_dup 0)
17689 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
17690 (clobber (reg:CC 17))])]
17694 [(match_scratch:SI 2 "r")
17695 (parallel [(set (match_operand:SI 0 "register_operand" "")
17696 (match_operator:SI 3 "arith_or_logical_operator"
17697 [(match_operand:SI 1 "memory_operand" "")
17699 (clobber (reg:CC 17))])]
17700 "! optimize_size && ! TARGET_READ_MODIFY"
17701 [(set (match_dup 2) (match_dup 1))
17702 (parallel [(set (match_dup 0)
17703 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17704 (clobber (reg:CC 17))])]
17707 ; Don't do logical operations with memory outputs
17709 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17710 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17711 ; the same decoder scheduling characteristics as the original.
17714 [(match_scratch:SI 2 "r")
17715 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17716 (match_operator:SI 3 "arith_or_logical_operator"
17718 (match_operand:SI 1 "nonmemory_operand" "")]))
17719 (clobber (reg:CC 17))])]
17720 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17721 [(set (match_dup 2) (match_dup 0))
17722 (parallel [(set (match_dup 2)
17723 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17724 (clobber (reg:CC 17))])
17725 (set (match_dup 0) (match_dup 2))]
17729 [(match_scratch:SI 2 "r")
17730 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17731 (match_operator:SI 3 "arith_or_logical_operator"
17732 [(match_operand:SI 1 "nonmemory_operand" "")
17734 (clobber (reg:CC 17))])]
17735 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17736 [(set (match_dup 2) (match_dup 0))
17737 (parallel [(set (match_dup 2)
17738 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17739 (clobber (reg:CC 17))])
17740 (set (match_dup 0) (match_dup 2))]
17743 ;; Attempt to always use XOR for zeroing registers.
17745 [(set (match_operand 0 "register_operand" "")
17747 "(GET_MODE (operands[0]) == QImode
17748 || GET_MODE (operands[0]) == HImode
17749 || GET_MODE (operands[0]) == SImode
17750 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17751 && (! TARGET_USE_MOV0 || optimize_size)
17752 && peep2_regno_dead_p (0, FLAGS_REG)"
17753 [(parallel [(set (match_dup 0) (const_int 0))
17754 (clobber (reg:CC 17))])]
17755 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17759 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17761 "(GET_MODE (operands[0]) == QImode
17762 || GET_MODE (operands[0]) == HImode)
17763 && (! TARGET_USE_MOV0 || optimize_size)
17764 && peep2_regno_dead_p (0, FLAGS_REG)"
17765 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17766 (clobber (reg:CC 17))])])
17768 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17770 [(set (match_operand 0 "register_operand" "")
17772 "(GET_MODE (operands[0]) == HImode
17773 || GET_MODE (operands[0]) == SImode
17774 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17775 && (optimize_size || TARGET_PENTIUM)
17776 && peep2_regno_dead_p (0, FLAGS_REG)"
17777 [(parallel [(set (match_dup 0) (const_int -1))
17778 (clobber (reg:CC 17))])]
17779 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17782 ;; Attempt to convert simple leas to adds. These can be created by
17785 [(set (match_operand:SI 0 "register_operand" "")
17786 (plus:SI (match_dup 0)
17787 (match_operand:SI 1 "nonmemory_operand" "")))]
17788 "peep2_regno_dead_p (0, FLAGS_REG)"
17789 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17790 (clobber (reg:CC 17))])]
17794 [(set (match_operand:SI 0 "register_operand" "")
17795 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17796 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17797 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17798 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17799 (clobber (reg:CC 17))])]
17800 "operands[2] = gen_lowpart (SImode, operands[2]);")
17803 [(set (match_operand:DI 0 "register_operand" "")
17804 (plus:DI (match_dup 0)
17805 (match_operand:DI 1 "x86_64_general_operand" "")))]
17806 "peep2_regno_dead_p (0, FLAGS_REG)"
17807 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17808 (clobber (reg:CC 17))])]
17812 [(set (match_operand:SI 0 "register_operand" "")
17813 (mult:SI (match_dup 0)
17814 (match_operand:SI 1 "const_int_operand" "")))]
17815 "exact_log2 (INTVAL (operands[1])) >= 0
17816 && peep2_regno_dead_p (0, FLAGS_REG)"
17817 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17818 (clobber (reg:CC 17))])]
17819 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17822 [(set (match_operand:DI 0 "register_operand" "")
17823 (mult:DI (match_dup 0)
17824 (match_operand:DI 1 "const_int_operand" "")))]
17825 "exact_log2 (INTVAL (operands[1])) >= 0
17826 && peep2_regno_dead_p (0, FLAGS_REG)"
17827 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17828 (clobber (reg:CC 17))])]
17829 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17832 [(set (match_operand:SI 0 "register_operand" "")
17833 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17834 (match_operand:DI 2 "const_int_operand" "")) 0))]
17835 "exact_log2 (INTVAL (operands[2])) >= 0
17836 && REGNO (operands[0]) == REGNO (operands[1])
17837 && peep2_regno_dead_p (0, FLAGS_REG)"
17838 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17839 (clobber (reg:CC 17))])]
17840 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17842 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17843 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17844 ;; many CPUs it is also faster, since special hardware to avoid esp
17845 ;; dependencies is present.
17847 ;; While some of these conversions may be done using splitters, we use peepholes
17848 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17850 ;; Convert prologue esp subtractions to push.
17851 ;; We need register to push. In order to keep verify_flow_info happy we have
17853 ;; - use scratch and clobber it in order to avoid dependencies
17854 ;; - use already live register
17855 ;; We can't use the second way right now, since there is no reliable way how to
17856 ;; verify that given register is live. First choice will also most likely in
17857 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17858 ;; call clobbered registers are dead. We may want to use base pointer as an
17859 ;; alternative when no register is available later.
17862 [(match_scratch:SI 0 "r")
17863 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17864 (clobber (reg:CC 17))
17865 (clobber (mem:BLK (scratch)))])]
17866 "optimize_size || !TARGET_SUB_ESP_4"
17867 [(clobber (match_dup 0))
17868 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17869 (clobber (mem:BLK (scratch)))])])
17872 [(match_scratch:SI 0 "r")
17873 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17874 (clobber (reg:CC 17))
17875 (clobber (mem:BLK (scratch)))])]
17876 "optimize_size || !TARGET_SUB_ESP_8"
17877 [(clobber (match_dup 0))
17878 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17879 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17880 (clobber (mem:BLK (scratch)))])])
17882 ;; Convert esp subtractions to push.
17884 [(match_scratch:SI 0 "r")
17885 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17886 (clobber (reg:CC 17))])]
17887 "optimize_size || !TARGET_SUB_ESP_4"
17888 [(clobber (match_dup 0))
17889 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17892 [(match_scratch:SI 0 "r")
17893 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17894 (clobber (reg:CC 17))])]
17895 "optimize_size || !TARGET_SUB_ESP_8"
17896 [(clobber (match_dup 0))
17897 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17898 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17900 ;; Convert epilogue deallocator to pop.
17902 [(match_scratch:SI 0 "r")
17903 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17904 (clobber (reg:CC 17))
17905 (clobber (mem:BLK (scratch)))])]
17906 "optimize_size || !TARGET_ADD_ESP_4"
17907 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17908 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17909 (clobber (mem:BLK (scratch)))])]
17912 ;; Two pops case is tricky, since pop causes dependency on destination register.
17913 ;; We use two registers if available.
17915 [(match_scratch:SI 0 "r")
17916 (match_scratch:SI 1 "r")
17917 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17918 (clobber (reg:CC 17))
17919 (clobber (mem:BLK (scratch)))])]
17920 "optimize_size || !TARGET_ADD_ESP_8"
17921 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17922 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17923 (clobber (mem:BLK (scratch)))])
17924 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17925 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17929 [(match_scratch:SI 0 "r")
17930 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17931 (clobber (reg:CC 17))
17932 (clobber (mem:BLK (scratch)))])]
17934 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17935 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17936 (clobber (mem:BLK (scratch)))])
17937 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17938 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17941 ;; Convert esp additions to pop.
17943 [(match_scratch:SI 0 "r")
17944 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17945 (clobber (reg:CC 17))])]
17947 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17948 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17951 ;; Two pops case is tricky, since pop causes dependency on destination register.
17952 ;; We use two registers if available.
17954 [(match_scratch:SI 0 "r")
17955 (match_scratch:SI 1 "r")
17956 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17957 (clobber (reg:CC 17))])]
17959 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17960 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17961 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17962 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17966 [(match_scratch:SI 0 "r")
17967 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17968 (clobber (reg:CC 17))])]
17970 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17971 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17972 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17973 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17976 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17977 ;; required and register dies.
17980 (compare (match_operand:SI 0 "register_operand" "")
17981 (match_operand:SI 1 "incdec_operand" "")))]
17982 "ix86_match_ccmode (insn, CCGCmode)
17983 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17984 [(parallel [(set (reg:CCGC 17)
17985 (compare:CCGC (match_dup 0)
17987 (clobber (match_dup 0))])]
17992 (compare (match_operand:HI 0 "register_operand" "")
17993 (match_operand:HI 1 "incdec_operand" "")))]
17994 "ix86_match_ccmode (insn, CCGCmode)
17995 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17996 [(parallel [(set (reg:CCGC 17)
17997 (compare:CCGC (match_dup 0)
17999 (clobber (match_dup 0))])]
18004 (compare (match_operand:QI 0 "register_operand" "")
18005 (match_operand:QI 1 "incdec_operand" "")))]
18006 "ix86_match_ccmode (insn, CCGCmode)
18007 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18008 [(parallel [(set (reg:CCGC 17)
18009 (compare:CCGC (match_dup 0)
18011 (clobber (match_dup 0))])]
18014 ;; Convert compares with 128 to shorter add -128
18017 (compare (match_operand:SI 0 "register_operand" "")
18019 "ix86_match_ccmode (insn, CCGCmode)
18020 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18021 [(parallel [(set (reg:CCGC 17)
18022 (compare:CCGC (match_dup 0)
18024 (clobber (match_dup 0))])]
18029 (compare (match_operand:HI 0 "register_operand" "")
18031 "ix86_match_ccmode (insn, CCGCmode)
18032 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18033 [(parallel [(set (reg:CCGC 17)
18034 (compare:CCGC (match_dup 0)
18036 (clobber (match_dup 0))])]
18040 [(match_scratch:DI 0 "r")
18041 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18042 (clobber (reg:CC 17))
18043 (clobber (mem:BLK (scratch)))])]
18044 "optimize_size || !TARGET_SUB_ESP_4"
18045 [(clobber (match_dup 0))
18046 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18047 (clobber (mem:BLK (scratch)))])])
18050 [(match_scratch:DI 0 "r")
18051 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18052 (clobber (reg:CC 17))
18053 (clobber (mem:BLK (scratch)))])]
18054 "optimize_size || !TARGET_SUB_ESP_8"
18055 [(clobber (match_dup 0))
18056 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18057 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18058 (clobber (mem:BLK (scratch)))])])
18060 ;; Convert esp subtractions to push.
18062 [(match_scratch:DI 0 "r")
18063 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18064 (clobber (reg:CC 17))])]
18065 "optimize_size || !TARGET_SUB_ESP_4"
18066 [(clobber (match_dup 0))
18067 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18070 [(match_scratch:DI 0 "r")
18071 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18072 (clobber (reg:CC 17))])]
18073 "optimize_size || !TARGET_SUB_ESP_8"
18074 [(clobber (match_dup 0))
18075 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18076 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18078 ;; Convert epilogue deallocator to pop.
18080 [(match_scratch:DI 0 "r")
18081 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18082 (clobber (reg:CC 17))
18083 (clobber (mem:BLK (scratch)))])]
18084 "optimize_size || !TARGET_ADD_ESP_4"
18085 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18086 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18087 (clobber (mem:BLK (scratch)))])]
18090 ;; Two pops case is tricky, since pop causes dependency on destination register.
18091 ;; We use two registers if available.
18093 [(match_scratch:DI 0 "r")
18094 (match_scratch:DI 1 "r")
18095 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18096 (clobber (reg:CC 17))
18097 (clobber (mem:BLK (scratch)))])]
18098 "optimize_size || !TARGET_ADD_ESP_8"
18099 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18100 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18101 (clobber (mem:BLK (scratch)))])
18102 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18103 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18107 [(match_scratch:DI 0 "r")
18108 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18109 (clobber (reg:CC 17))
18110 (clobber (mem:BLK (scratch)))])]
18112 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18113 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18114 (clobber (mem:BLK (scratch)))])
18115 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18116 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18119 ;; Convert esp additions to pop.
18121 [(match_scratch:DI 0 "r")
18122 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18123 (clobber (reg:CC 17))])]
18125 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18126 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18129 ;; Two pops case is tricky, since pop causes dependency on destination register.
18130 ;; We use two registers if available.
18132 [(match_scratch:DI 0 "r")
18133 (match_scratch:DI 1 "r")
18134 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18135 (clobber (reg:CC 17))])]
18137 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18138 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18139 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18140 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18144 [(match_scratch:DI 0 "r")
18145 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18146 (clobber (reg:CC 17))])]
18148 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18149 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18150 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18151 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18154 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18155 ;; imul $32bit_imm, reg, reg is direct decoded.
18157 [(match_scratch:DI 3 "r")
18158 (parallel [(set (match_operand:DI 0 "register_operand" "")
18159 (mult:DI (match_operand:DI 1 "memory_operand" "")
18160 (match_operand:DI 2 "immediate_operand" "")))
18161 (clobber (reg:CC 17))])]
18162 "TARGET_K8 && !optimize_size
18163 && (GET_CODE (operands[2]) != CONST_INT
18164 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18165 [(set (match_dup 3) (match_dup 1))
18166 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18167 (clobber (reg:CC 17))])]
18171 [(match_scratch:SI 3 "r")
18172 (parallel [(set (match_operand:SI 0 "register_operand" "")
18173 (mult:SI (match_operand:SI 1 "memory_operand" "")
18174 (match_operand:SI 2 "immediate_operand" "")))
18175 (clobber (reg:CC 17))])]
18176 "TARGET_K8 && !optimize_size
18177 && (GET_CODE (operands[2]) != CONST_INT
18178 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18179 [(set (match_dup 3) (match_dup 1))
18180 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18181 (clobber (reg:CC 17))])]
18185 [(match_scratch:SI 3 "r")
18186 (parallel [(set (match_operand:DI 0 "register_operand" "")
18188 (mult:SI (match_operand:SI 1 "memory_operand" "")
18189 (match_operand:SI 2 "immediate_operand" ""))))
18190 (clobber (reg:CC 17))])]
18191 "TARGET_K8 && !optimize_size
18192 && (GET_CODE (operands[2]) != CONST_INT
18193 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18194 [(set (match_dup 3) (match_dup 1))
18195 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18196 (clobber (reg:CC 17))])]
18199 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18200 ;; Convert it into imul reg, reg
18201 ;; It would be better to force assembler to encode instruction using long
18202 ;; immediate, but there is apparently no way to do so.
18204 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18205 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18206 (match_operand:DI 2 "const_int_operand" "")))
18207 (clobber (reg:CC 17))])
18208 (match_scratch:DI 3 "r")]
18209 "TARGET_K8 && !optimize_size
18210 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18211 [(set (match_dup 3) (match_dup 2))
18212 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18213 (clobber (reg:CC 17))])]
18215 if (!rtx_equal_p (operands[0], operands[1]))
18216 emit_move_insn (operands[0], operands[1]);
18220 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18221 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18222 (match_operand:SI 2 "const_int_operand" "")))
18223 (clobber (reg:CC 17))])
18224 (match_scratch:SI 3 "r")]
18225 "TARGET_K8 && !optimize_size
18226 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18227 [(set (match_dup 3) (match_dup 2))
18228 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18229 (clobber (reg:CC 17))])]
18231 if (!rtx_equal_p (operands[0], operands[1]))
18232 emit_move_insn (operands[0], operands[1]);
18236 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18237 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18238 (match_operand:HI 2 "immediate_operand" "")))
18239 (clobber (reg:CC 17))])
18240 (match_scratch:HI 3 "r")]
18241 "TARGET_K8 && !optimize_size"
18242 [(set (match_dup 3) (match_dup 2))
18243 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18244 (clobber (reg:CC 17))])]
18246 if (!rtx_equal_p (operands[0], operands[1]))
18247 emit_move_insn (operands[0], operands[1]);
18250 ;; Call-value patterns last so that the wildcard operand does not
18251 ;; disrupt insn-recog's switch tables.
18253 (define_insn "*call_value_pop_0"
18254 [(set (match_operand 0 "" "")
18255 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18256 (match_operand:SI 2 "" "")))
18257 (set (reg:SI 7) (plus:SI (reg:SI 7)
18258 (match_operand:SI 3 "immediate_operand" "")))]
18261 if (SIBLING_CALL_P (insn))
18264 return "call\t%P1";
18266 [(set_attr "type" "callv")])
18268 (define_insn "*call_value_pop_1"
18269 [(set (match_operand 0 "" "")
18270 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18271 (match_operand:SI 2 "" "")))
18272 (set (reg:SI 7) (plus:SI (reg:SI 7)
18273 (match_operand:SI 3 "immediate_operand" "i")))]
18276 if (constant_call_address_operand (operands[1], QImode))
18278 if (SIBLING_CALL_P (insn))
18281 return "call\t%P1";
18283 if (SIBLING_CALL_P (insn))
18286 return "call\t%A1";
18288 [(set_attr "type" "callv")])
18290 (define_insn "*call_value_0"
18291 [(set (match_operand 0 "" "")
18292 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18293 (match_operand:SI 2 "" "")))]
18296 if (SIBLING_CALL_P (insn))
18299 return "call\t%P1";
18301 [(set_attr "type" "callv")])
18303 (define_insn "*call_value_0_rex64"
18304 [(set (match_operand 0 "" "")
18305 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18306 (match_operand:DI 2 "const_int_operand" "")))]
18309 if (SIBLING_CALL_P (insn))
18312 return "call\t%P1";
18314 [(set_attr "type" "callv")])
18316 (define_insn "*call_value_1"
18317 [(set (match_operand 0 "" "")
18318 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18319 (match_operand:SI 2 "" "")))]
18320 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18322 if (constant_call_address_operand (operands[1], QImode))
18323 return "call\t%P1";
18324 return "call\t%*%1";
18326 [(set_attr "type" "callv")])
18328 (define_insn "*sibcall_value_1"
18329 [(set (match_operand 0 "" "")
18330 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18331 (match_operand:SI 2 "" "")))]
18332 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18334 if (constant_call_address_operand (operands[1], QImode))
18336 return "jmp\t%*%1";
18338 [(set_attr "type" "callv")])
18340 (define_insn "*call_value_1_rex64"
18341 [(set (match_operand 0 "" "")
18342 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18343 (match_operand:DI 2 "" "")))]
18344 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
18346 if (constant_call_address_operand (operands[1], QImode))
18347 return "call\t%P1";
18348 return "call\t%A1";
18350 [(set_attr "type" "callv")])
18352 (define_insn "*sibcall_value_1_rex64"
18353 [(set (match_operand 0 "" "")
18354 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18355 (match_operand:DI 2 "" "")))]
18356 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18358 [(set_attr "type" "callv")])
18360 (define_insn "*sibcall_value_1_rex64_v"
18361 [(set (match_operand 0 "" "")
18362 (call (mem:QI (reg:DI 40))
18363 (match_operand:DI 1 "" "")))]
18364 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18366 [(set_attr "type" "callv")])
18368 (define_insn "trap"
18369 [(trap_if (const_int 1) (const_int 5))]
18373 ;;; ix86 doesn't have conditional trap instructions, but we fake them
18374 ;;; for the sake of bounds checking. By emitting bounds checks as
18375 ;;; conditional traps rather than as conditional jumps around
18376 ;;; unconditional traps we avoid introducing spurious basic-block
18377 ;;; boundaries and facilitate elimination of redundant checks. In
18378 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
18381 ;;; FIXME: Static branch prediction rules for ix86 are such that
18382 ;;; forward conditional branches predict as untaken. As implemented
18383 ;;; below, pseudo conditional traps violate that rule. We should use
18384 ;;; .pushsection/.popsection to place all of the `int 5's in a special
18385 ;;; section loaded at the end of the text segment and branch forward
18386 ;;; there on bounds-failure, and then jump back immediately (in case
18387 ;;; the system chooses to ignore bounds violations, or to report
18388 ;;; violations and continue execution).
18390 (define_expand "conditional_trap"
18391 [(trap_if (match_operator 0 "comparison_operator"
18392 [(match_dup 2) (const_int 0)])
18393 (match_operand 1 "const_int_operand" ""))]
18396 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
18397 ix86_expand_compare (GET_CODE (operands[0]),
18403 (define_insn "*conditional_trap_1"
18404 [(trap_if (match_operator 0 "comparison_operator"
18405 [(reg 17) (const_int 0)])
18406 (match_operand 1 "const_int_operand" ""))]
18409 operands[2] = gen_label_rtx ();
18410 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
18411 (*targetm.asm_out.internal_label) (asm_out_file, "L",
18412 CODE_LABEL_NUMBER (operands[2]));
18416 ;; Pentium III SIMD instructions.
18418 ;; Moves for SSE/MMX regs.
18420 (define_insn "movv4sf_internal"
18421 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18422 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18426 movaps\t{%1, %0|%0, %1}
18427 movaps\t{%1, %0|%0, %1}"
18428 [(set_attr "type" "ssemov")
18429 (set_attr "mode" "V4SF")])
18432 [(set (match_operand:V4SF 0 "register_operand" "")
18433 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18435 [(set (match_dup 0)
18437 (vec_duplicate:V4SF (match_dup 1))
18441 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18442 operands[2] = CONST0_RTX (V4SFmode);
18445 (define_insn "movv4si_internal"
18446 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18447 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18450 switch (which_alternative)
18453 if (get_attr_mode (insn) == MODE_V4SF)
18454 return "xorps\t%0, %0";
18456 return "pxor\t%0, %0";
18459 if (get_attr_mode (insn) == MODE_V4SF)
18460 return "movaps\t{%1, %0|%0, %1}";
18462 return "movdqa\t{%1, %0|%0, %1}";
18467 [(set_attr "type" "ssemov")
18469 (cond [(eq_attr "alternative" "0,1")
18471 (ne (symbol_ref "optimize_size")
18473 (const_string "V4SF")
18474 (const_string "TI"))
18475 (eq_attr "alternative" "2")
18477 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18479 (ne (symbol_ref "optimize_size")
18481 (const_string "V4SF")
18482 (const_string "TI"))]
18483 (const_string "TI")))])
18485 (define_insn "movv2di_internal"
18486 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18487 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18490 switch (which_alternative)
18493 if (get_attr_mode (insn) == MODE_V4SF)
18494 return "xorps\t%0, %0";
18496 return "pxor\t%0, %0";
18499 if (get_attr_mode (insn) == MODE_V4SF)
18500 return "movaps\t{%1, %0|%0, %1}";
18502 return "movdqa\t{%1, %0|%0, %1}";
18507 [(set_attr "type" "ssemov")
18509 (cond [(eq_attr "alternative" "0,1")
18511 (ne (symbol_ref "optimize_size")
18513 (const_string "V4SF")
18514 (const_string "TI"))
18515 (eq_attr "alternative" "2")
18517 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18519 (ne (symbol_ref "optimize_size")
18521 (const_string "V4SF")
18522 (const_string "TI"))]
18523 (const_string "TI")))])
18526 [(set (match_operand:V2DF 0 "register_operand" "")
18527 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18529 [(set (match_dup 0)
18531 (vec_duplicate:V2DF (match_dup 1))
18535 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18536 operands[2] = CONST0_RTX (V2DFmode);
18539 (define_insn "movv8qi_internal"
18540 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
18541 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
18543 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18546 movq\t{%1, %0|%0, %1}
18547 movq\t{%1, %0|%0, %1}"
18548 [(set_attr "type" "mmxmov")
18549 (set_attr "mode" "DI")])
18551 (define_insn "movv4hi_internal"
18552 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
18553 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
18555 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18558 movq\t{%1, %0|%0, %1}
18559 movq\t{%1, %0|%0, %1}"
18560 [(set_attr "type" "mmxmov")
18561 (set_attr "mode" "DI")])
18563 (define_insn "movv2si_internal"
18564 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
18565 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
18567 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18570 movq\t{%1, %0|%0, %1}
18571 movq\t{%1, %0|%0, %1}"
18572 [(set_attr "type" "mmxcvt")
18573 (set_attr "mode" "DI")])
18575 (define_insn "movv2sf_internal"
18576 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
18577 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
18579 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18582 movq\t{%1, %0|%0, %1}
18583 movq\t{%1, %0|%0, %1}"
18584 [(set_attr "type" "mmxcvt")
18585 (set_attr "mode" "DI")])
18587 (define_expand "movti"
18588 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18589 (match_operand:TI 1 "nonimmediate_operand" ""))]
18590 "TARGET_SSE || TARGET_64BIT"
18593 ix86_expand_move (TImode, operands);
18595 ix86_expand_vector_move (TImode, operands);
18599 (define_expand "movtf"
18600 [(set (match_operand:TF 0 "nonimmediate_operand" "")
18601 (match_operand:TF 1 "nonimmediate_operand" ""))]
18605 ix86_expand_move (TFmode, operands);
18607 ix86_expand_vector_move (TFmode, operands);
18611 (define_insn "movv2df_internal"
18612 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
18613 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
18615 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18617 switch (which_alternative)
18620 if (get_attr_mode (insn) == MODE_V4SF)
18621 return "xorps\t%0, %0";
18623 return "xorpd\t%0, %0";
18626 if (get_attr_mode (insn) == MODE_V4SF)
18627 return "movaps\t{%1, %0|%0, %1}";
18629 return "movapd\t{%1, %0|%0, %1}";
18634 [(set_attr "type" "ssemov")
18636 (cond [(eq_attr "alternative" "0,1")
18638 (ne (symbol_ref "optimize_size")
18640 (const_string "V4SF")
18641 (const_string "V2DF"))
18642 (eq_attr "alternative" "2")
18644 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18646 (ne (symbol_ref "optimize_size")
18648 (const_string "V4SF")
18649 (const_string "V2DF"))]
18650 (const_string "V2DF")))])
18652 (define_insn "movv8hi_internal"
18653 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
18654 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
18656 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18658 switch (which_alternative)
18661 if (get_attr_mode (insn) == MODE_V4SF)
18662 return "xorps\t%0, %0";
18664 return "pxor\t%0, %0";
18667 if (get_attr_mode (insn) == MODE_V4SF)
18668 return "movaps\t{%1, %0|%0, %1}";
18670 return "movdqa\t{%1, %0|%0, %1}";
18675 [(set_attr "type" "ssemov")
18677 (cond [(eq_attr "alternative" "0,1")
18679 (ne (symbol_ref "optimize_size")
18681 (const_string "V4SF")
18682 (const_string "TI"))
18683 (eq_attr "alternative" "2")
18685 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18687 (ne (symbol_ref "optimize_size")
18689 (const_string "V4SF")
18690 (const_string "TI"))]
18691 (const_string "TI")))])
18693 (define_insn "movv16qi_internal"
18694 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
18695 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
18697 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18699 switch (which_alternative)
18702 if (get_attr_mode (insn) == MODE_V4SF)
18703 return "xorps\t%0, %0";
18705 return "pxor\t%0, %0";
18708 if (get_attr_mode (insn) == MODE_V4SF)
18709 return "movaps\t{%1, %0|%0, %1}";
18711 return "movdqa\t{%1, %0|%0, %1}";
18716 [(set_attr "type" "ssemov")
18718 (cond [(eq_attr "alternative" "0,1")
18720 (ne (symbol_ref "optimize_size")
18722 (const_string "V4SF")
18723 (const_string "TI"))
18724 (eq_attr "alternative" "2")
18726 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18728 (ne (symbol_ref "optimize_size")
18730 (const_string "V4SF")
18731 (const_string "TI"))]
18732 (const_string "TI")))])
18734 (define_expand "movv2df"
18735 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
18736 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
18739 ix86_expand_vector_move (V2DFmode, operands);
18743 (define_expand "movv8hi"
18744 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
18745 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
18748 ix86_expand_vector_move (V8HImode, operands);
18752 (define_expand "movv16qi"
18753 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
18754 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
18757 ix86_expand_vector_move (V16QImode, operands);
18761 (define_expand "movv4sf"
18762 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18763 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
18766 ix86_expand_vector_move (V4SFmode, operands);
18770 (define_expand "movv4si"
18771 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
18772 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
18775 ix86_expand_vector_move (V4SImode, operands);
18779 (define_expand "movv2di"
18780 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
18781 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
18784 ix86_expand_vector_move (V2DImode, operands);
18788 (define_expand "movv2si"
18789 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
18790 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
18793 ix86_expand_vector_move (V2SImode, operands);
18797 (define_expand "movv4hi"
18798 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
18799 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
18802 ix86_expand_vector_move (V4HImode, operands);
18806 (define_expand "movv8qi"
18807 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
18808 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
18811 ix86_expand_vector_move (V8QImode, operands);
18815 (define_expand "movv2sf"
18816 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
18817 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
18820 ix86_expand_vector_move (V2SFmode, operands);
18824 (define_insn "*pushti"
18825 [(set (match_operand:TI 0 "push_operand" "=<")
18826 (match_operand:TI 1 "register_operand" "x"))]
18830 (define_insn "*pushv2df"
18831 [(set (match_operand:V2DF 0 "push_operand" "=<")
18832 (match_operand:V2DF 1 "register_operand" "x"))]
18836 (define_insn "*pushv2di"
18837 [(set (match_operand:V2DI 0 "push_operand" "=<")
18838 (match_operand:V2DI 1 "register_operand" "x"))]
18842 (define_insn "*pushv8hi"
18843 [(set (match_operand:V8HI 0 "push_operand" "=<")
18844 (match_operand:V8HI 1 "register_operand" "x"))]
18848 (define_insn "*pushv16qi"
18849 [(set (match_operand:V16QI 0 "push_operand" "=<")
18850 (match_operand:V16QI 1 "register_operand" "x"))]
18854 (define_insn "*pushv4sf"
18855 [(set (match_operand:V4SF 0 "push_operand" "=<")
18856 (match_operand:V4SF 1 "register_operand" "x"))]
18860 (define_insn "*pushv4si"
18861 [(set (match_operand:V4SI 0 "push_operand" "=<")
18862 (match_operand:V4SI 1 "register_operand" "x"))]
18866 (define_insn "*pushv2si"
18867 [(set (match_operand:V2SI 0 "push_operand" "=<")
18868 (match_operand:V2SI 1 "register_operand" "y"))]
18872 (define_insn "*pushv4hi"
18873 [(set (match_operand:V4HI 0 "push_operand" "=<")
18874 (match_operand:V4HI 1 "register_operand" "y"))]
18878 (define_insn "*pushv8qi"
18879 [(set (match_operand:V8QI 0 "push_operand" "=<")
18880 (match_operand:V8QI 1 "register_operand" "y"))]
18884 (define_insn "*pushv2sf"
18885 [(set (match_operand:V2SF 0 "push_operand" "=<")
18886 (match_operand:V2SF 1 "register_operand" "y"))]
18891 [(set (match_operand 0 "push_operand" "")
18892 (match_operand 1 "register_operand" ""))]
18893 "!TARGET_64BIT && reload_completed
18894 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18895 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
18896 (set (match_dup 2) (match_dup 1))]
18897 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18898 stack_pointer_rtx);
18899 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18902 [(set (match_operand 0 "push_operand" "")
18903 (match_operand 1 "register_operand" ""))]
18904 "TARGET_64BIT && reload_completed
18905 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18906 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
18907 (set (match_dup 2) (match_dup 1))]
18908 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18909 stack_pointer_rtx);
18910 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18913 (define_insn "movti_internal"
18914 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18915 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
18916 "TARGET_SSE && !TARGET_64BIT
18917 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18919 switch (which_alternative)
18922 if (get_attr_mode (insn) == MODE_V4SF)
18923 return "xorps\t%0, %0";
18925 return "pxor\t%0, %0";
18928 if (get_attr_mode (insn) == MODE_V4SF)
18929 return "movaps\t{%1, %0|%0, %1}";
18931 return "movdqa\t{%1, %0|%0, %1}";
18936 [(set_attr "type" "ssemov,ssemov,ssemov")
18938 (cond [(eq_attr "alternative" "0,1")
18940 (ne (symbol_ref "optimize_size")
18942 (const_string "V4SF")
18943 (const_string "TI"))
18944 (eq_attr "alternative" "2")
18946 (ne (symbol_ref "optimize_size")
18948 (const_string "V4SF")
18949 (const_string "TI"))]
18950 (const_string "TI")))])
18952 (define_insn "*movti_rex64"
18953 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
18954 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
18956 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18958 switch (which_alternative)
18964 if (get_attr_mode (insn) == MODE_V4SF)
18965 return "xorps\t%0, %0";
18967 return "pxor\t%0, %0";
18970 if (get_attr_mode (insn) == MODE_V4SF)
18971 return "movaps\t{%1, %0|%0, %1}";
18973 return "movdqa\t{%1, %0|%0, %1}";
18978 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
18980 (cond [(eq_attr "alternative" "2,3")
18982 (ne (symbol_ref "optimize_size")
18984 (const_string "V4SF")
18985 (const_string "TI"))
18986 (eq_attr "alternative" "4")
18988 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18990 (ne (symbol_ref "optimize_size")
18992 (const_string "V4SF")
18993 (const_string "TI"))]
18994 (const_string "DI")))])
18996 (define_insn "*movtf_rex64"
18997 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
18998 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
19000 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19002 switch (which_alternative)
19008 if (get_attr_mode (insn) == MODE_V4SF)
19009 return "xorps\t%0, %0";
19011 return "pxor\t%0, %0";
19014 if (get_attr_mode (insn) == MODE_V4SF)
19015 return "movaps\t{%1, %0|%0, %1}";
19017 return "movdqa\t{%1, %0|%0, %1}";
19022 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19024 (cond [(eq_attr "alternative" "2,3")
19026 (ne (symbol_ref "optimize_size")
19028 (const_string "V4SF")
19029 (const_string "TI"))
19030 (eq_attr "alternative" "4")
19032 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19034 (ne (symbol_ref "optimize_size")
19036 (const_string "V4SF")
19037 (const_string "TI"))]
19038 (const_string "DI")))])
19041 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19042 (match_operand:TI 1 "general_operand" ""))]
19043 "reload_completed && !SSE_REG_P (operands[0])
19044 && !SSE_REG_P (operands[1])"
19046 "ix86_split_long_move (operands); DONE;")
19049 [(set (match_operand:TF 0 "nonimmediate_operand" "")
19050 (match_operand:TF 1 "general_operand" ""))]
19051 "reload_completed && !SSE_REG_P (operands[0])
19052 && !SSE_REG_P (operands[1])"
19054 "ix86_split_long_move (operands); DONE;")
19056 ;; These two patterns are useful for specifying exactly whether to use
19057 ;; movaps or movups
19058 (define_expand "sse_movaps"
19059 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19060 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
19064 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
19066 rtx tmp = gen_reg_rtx (V4SFmode);
19067 emit_insn (gen_sse_movaps (tmp, operands[1]));
19068 emit_move_insn (operands[0], tmp);
19073 (define_insn "*sse_movaps_1"
19074 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19075 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19078 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19079 "movaps\t{%1, %0|%0, %1}"
19080 [(set_attr "type" "ssemov,ssemov")
19081 (set_attr "mode" "V4SF")])
19083 (define_expand "sse_movups"
19084 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19085 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
19089 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
19091 rtx tmp = gen_reg_rtx (V4SFmode);
19092 emit_insn (gen_sse_movups (tmp, operands[1]));
19093 emit_move_insn (operands[0], tmp);
19098 (define_insn "*sse_movups_1"
19099 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19100 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19103 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19104 "movups\t{%1, %0|%0, %1}"
19105 [(set_attr "type" "ssecvt,ssecvt")
19106 (set_attr "mode" "V4SF")])
19108 ;; SSE Strange Moves.
19110 (define_insn "sse_movmskps"
19111 [(set (match_operand:SI 0 "register_operand" "=r")
19112 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19115 "movmskps\t{%1, %0|%0, %1}"
19116 [(set_attr "type" "ssecvt")
19117 (set_attr "mode" "V4SF")])
19119 (define_insn "mmx_pmovmskb"
19120 [(set (match_operand:SI 0 "register_operand" "=r")
19121 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19123 "TARGET_SSE || TARGET_3DNOW_A"
19124 "pmovmskb\t{%1, %0|%0, %1}"
19125 [(set_attr "type" "ssecvt")
19126 (set_attr "mode" "V4SF")])
19129 (define_insn "mmx_maskmovq"
19130 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19131 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19132 (match_operand:V8QI 2 "register_operand" "y")]
19134 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19135 ;; @@@ check ordering of operands in intel/nonintel syntax
19136 "maskmovq\t{%2, %1|%1, %2}"
19137 [(set_attr "type" "mmxcvt")
19138 (set_attr "mode" "DI")])
19140 (define_insn "mmx_maskmovq_rex"
19141 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19142 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19143 (match_operand:V8QI 2 "register_operand" "y")]
19145 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19146 ;; @@@ check ordering of operands in intel/nonintel syntax
19147 "maskmovq\t{%2, %1|%1, %2}"
19148 [(set_attr "type" "mmxcvt")
19149 (set_attr "mode" "DI")])
19151 (define_insn "sse_movntv4sf"
19152 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19153 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19156 "movntps\t{%1, %0|%0, %1}"
19157 [(set_attr "type" "ssemov")
19158 (set_attr "mode" "V4SF")])
19160 (define_insn "sse_movntdi"
19161 [(set (match_operand:DI 0 "memory_operand" "=m")
19162 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19164 "TARGET_SSE || TARGET_3DNOW_A"
19165 "movntq\t{%1, %0|%0, %1}"
19166 [(set_attr "type" "mmxmov")
19167 (set_attr "mode" "DI")])
19169 (define_insn "sse_movhlps"
19170 [(set (match_operand:V4SF 0 "register_operand" "=x")
19172 (match_operand:V4SF 1 "register_operand" "0")
19173 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19174 (parallel [(const_int 2)
19180 "movhlps\t{%2, %0|%0, %2}"
19181 [(set_attr "type" "ssecvt")
19182 (set_attr "mode" "V4SF")])
19184 (define_insn "sse_movlhps"
19185 [(set (match_operand:V4SF 0 "register_operand" "=x")
19187 (match_operand:V4SF 1 "register_operand" "0")
19188 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19189 (parallel [(const_int 2)
19195 "movlhps\t{%2, %0|%0, %2}"
19196 [(set_attr "type" "ssecvt")
19197 (set_attr "mode" "V4SF")])
19199 (define_insn "sse_movhps"
19200 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19202 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19203 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19206 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19207 "movhps\t{%2, %0|%0, %2}"
19208 [(set_attr "type" "ssecvt")
19209 (set_attr "mode" "V4SF")])
19211 (define_insn "sse_movlps"
19212 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19214 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19215 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19218 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19219 "movlps\t{%2, %0|%0, %2}"
19220 [(set_attr "type" "ssecvt")
19221 (set_attr "mode" "V4SF")])
19223 (define_expand "sse_loadss"
19224 [(match_operand:V4SF 0 "register_operand" "")
19225 (match_operand:SF 1 "memory_operand" "")]
19228 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19229 CONST0_RTX (V4SFmode)));
19233 (define_insn "sse_loadss_1"
19234 [(set (match_operand:V4SF 0 "register_operand" "=x")
19236 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19237 (match_operand:V4SF 2 "const0_operand" "X")
19240 "movss\t{%1, %0|%0, %1}"
19241 [(set_attr "type" "ssemov")
19242 (set_attr "mode" "SF")])
19244 (define_insn "sse_movss"
19245 [(set (match_operand:V4SF 0 "register_operand" "=x")
19247 (match_operand:V4SF 1 "register_operand" "0")
19248 (match_operand:V4SF 2 "register_operand" "x")
19251 "movss\t{%2, %0|%0, %2}"
19252 [(set_attr "type" "ssemov")
19253 (set_attr "mode" "SF")])
19255 (define_insn "sse_storess"
19256 [(set (match_operand:SF 0 "memory_operand" "=m")
19258 (match_operand:V4SF 1 "register_operand" "x")
19259 (parallel [(const_int 0)])))]
19261 "movss\t{%1, %0|%0, %1}"
19262 [(set_attr "type" "ssemov")
19263 (set_attr "mode" "SF")])
19265 (define_insn "sse_shufps"
19266 [(set (match_operand:V4SF 0 "register_operand" "=x")
19267 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19268 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19269 (match_operand:SI 3 "immediate_operand" "i")]
19272 ;; @@@ check operand order for intel/nonintel syntax
19273 "shufps\t{%3, %2, %0|%0, %2, %3}"
19274 [(set_attr "type" "ssecvt")
19275 (set_attr "mode" "V4SF")])
19280 (define_insn "addv4sf3"
19281 [(set (match_operand:V4SF 0 "register_operand" "=x")
19282 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19283 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19285 "addps\t{%2, %0|%0, %2}"
19286 [(set_attr "type" "sseadd")
19287 (set_attr "mode" "V4SF")])
19289 (define_insn "vmaddv4sf3"
19290 [(set (match_operand:V4SF 0 "register_operand" "=x")
19292 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19293 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19297 "addss\t{%2, %0|%0, %2}"
19298 [(set_attr "type" "sseadd")
19299 (set_attr "mode" "SF")])
19301 (define_insn "subv4sf3"
19302 [(set (match_operand:V4SF 0 "register_operand" "=x")
19303 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19304 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19306 "subps\t{%2, %0|%0, %2}"
19307 [(set_attr "type" "sseadd")
19308 (set_attr "mode" "V4SF")])
19310 (define_insn "vmsubv4sf3"
19311 [(set (match_operand:V4SF 0 "register_operand" "=x")
19313 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19314 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19318 "subss\t{%2, %0|%0, %2}"
19319 [(set_attr "type" "sseadd")
19320 (set_attr "mode" "SF")])
19322 (define_insn "mulv4sf3"
19323 [(set (match_operand:V4SF 0 "register_operand" "=x")
19324 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19325 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19327 "mulps\t{%2, %0|%0, %2}"
19328 [(set_attr "type" "ssemul")
19329 (set_attr "mode" "V4SF")])
19331 (define_insn "vmmulv4sf3"
19332 [(set (match_operand:V4SF 0 "register_operand" "=x")
19334 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19335 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19339 "mulss\t{%2, %0|%0, %2}"
19340 [(set_attr "type" "ssemul")
19341 (set_attr "mode" "SF")])
19343 (define_insn "divv4sf3"
19344 [(set (match_operand:V4SF 0 "register_operand" "=x")
19345 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19346 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19348 "divps\t{%2, %0|%0, %2}"
19349 [(set_attr "type" "ssediv")
19350 (set_attr "mode" "V4SF")])
19352 (define_insn "vmdivv4sf3"
19353 [(set (match_operand:V4SF 0 "register_operand" "=x")
19355 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19356 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19360 "divss\t{%2, %0|%0, %2}"
19361 [(set_attr "type" "ssediv")
19362 (set_attr "mode" "SF")])
19365 ;; SSE square root/reciprocal
19367 (define_insn "rcpv4sf2"
19368 [(set (match_operand:V4SF 0 "register_operand" "=x")
19370 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
19372 "rcpps\t{%1, %0|%0, %1}"
19373 [(set_attr "type" "sse")
19374 (set_attr "mode" "V4SF")])
19376 (define_insn "vmrcpv4sf2"
19377 [(set (match_operand:V4SF 0 "register_operand" "=x")
19379 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19381 (match_operand:V4SF 2 "register_operand" "0")
19384 "rcpss\t{%1, %0|%0, %1}"
19385 [(set_attr "type" "sse")
19386 (set_attr "mode" "SF")])
19388 (define_insn "rsqrtv4sf2"
19389 [(set (match_operand:V4SF 0 "register_operand" "=x")
19391 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
19393 "rsqrtps\t{%1, %0|%0, %1}"
19394 [(set_attr "type" "sse")
19395 (set_attr "mode" "V4SF")])
19397 (define_insn "vmrsqrtv4sf2"
19398 [(set (match_operand:V4SF 0 "register_operand" "=x")
19400 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19402 (match_operand:V4SF 2 "register_operand" "0")
19405 "rsqrtss\t{%1, %0|%0, %1}"
19406 [(set_attr "type" "sse")
19407 (set_attr "mode" "SF")])
19409 (define_insn "sqrtv4sf2"
19410 [(set (match_operand:V4SF 0 "register_operand" "=x")
19411 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19413 "sqrtps\t{%1, %0|%0, %1}"
19414 [(set_attr "type" "sse")
19415 (set_attr "mode" "V4SF")])
19417 (define_insn "vmsqrtv4sf2"
19418 [(set (match_operand:V4SF 0 "register_operand" "=x")
19420 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19421 (match_operand:V4SF 2 "register_operand" "0")
19424 "sqrtss\t{%1, %0|%0, %1}"
19425 [(set_attr "type" "sse")
19426 (set_attr "mode" "SF")])
19428 ;; SSE logical operations.
19430 ;; SSE defines logical operations on floating point values. This brings
19431 ;; interesting challenge to RTL representation where logicals are only valid
19432 ;; on integral types. We deal with this by representing the floating point
19433 ;; logical as logical on arguments casted to TImode as this is what hardware
19434 ;; really does. Unfortunately hardware requires the type information to be
19435 ;; present and thus we must avoid subregs from being simplified and eliminated
19436 ;; in later compilation phases.
19438 ;; We have following variants from each instruction:
19439 ;; sse_andsf3 - the operation taking V4SF vector operands
19440 ;; and doing TImode cast on them
19441 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
19442 ;; TImode, since backend insist on eliminating casts
19443 ;; on memory operands
19444 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
19445 ;; We can not accept memory operand here as instruction reads
19446 ;; whole scalar. This is generated only post reload by GCC
19447 ;; scalar float operations that expands to logicals (fabs)
19448 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
19449 ;; memory operand. Eventually combine can be able
19450 ;; to synthesize these using splitter.
19451 ;; sse2_anddf3, *sse2_anddf3_memory
19454 ;; These are not called andti3 etc. because we really really don't want
19455 ;; the compiler to widen DImode ands to TImode ands and then try to move
19456 ;; into DImode subregs of SSE registers, and them together, and move out
19457 ;; of DImode subregs again!
19458 ;; SSE1 single precision floating point logical operation
19459 (define_expand "sse_andv4sf3"
19460 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19461 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19462 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19466 (define_insn "*sse_andv4sf3"
19467 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19468 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19469 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19471 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19472 "andps\t{%2, %0|%0, %2}"
19473 [(set_attr "type" "sselog")
19474 (set_attr "mode" "V4SF")])
19476 (define_insn "*sse_andsf3"
19477 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19478 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19479 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19481 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19482 "andps\t{%2, %0|%0, %2}"
19483 [(set_attr "type" "sselog")
19484 (set_attr "mode" "V4SF")])
19486 (define_expand "sse_nandv4sf3"
19487 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19488 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19489 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19493 (define_insn "*sse_nandv4sf3"
19494 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19495 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19496 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19498 "andnps\t{%2, %0|%0, %2}"
19499 [(set_attr "type" "sselog")
19500 (set_attr "mode" "V4SF")])
19502 (define_insn "*sse_nandsf3"
19503 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19504 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19505 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19507 "andnps\t{%2, %0|%0, %2}"
19508 [(set_attr "type" "sselog")
19509 (set_attr "mode" "V4SF")])
19511 (define_expand "sse_iorv4sf3"
19512 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19513 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19514 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19518 (define_insn "*sse_iorv4sf3"
19519 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19520 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19521 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19523 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19524 "orps\t{%2, %0|%0, %2}"
19525 [(set_attr "type" "sselog")
19526 (set_attr "mode" "V4SF")])
19528 (define_insn "*sse_iorsf3"
19529 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19530 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19531 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19533 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19534 "orps\t{%2, %0|%0, %2}"
19535 [(set_attr "type" "sselog")
19536 (set_attr "mode" "V4SF")])
19538 (define_expand "sse_xorv4sf3"
19539 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19540 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19541 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19543 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19546 (define_insn "*sse_xorv4sf3"
19547 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19548 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19549 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19551 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19552 "xorps\t{%2, %0|%0, %2}"
19553 [(set_attr "type" "sselog")
19554 (set_attr "mode" "V4SF")])
19556 (define_insn "*sse_xorsf3"
19557 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19558 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19559 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19561 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19562 "xorps\t{%2, %0|%0, %2}"
19563 [(set_attr "type" "sselog")
19564 (set_attr "mode" "V4SF")])
19566 ;; SSE2 double precision floating point logical operation
19568 (define_expand "sse2_andv2df3"
19569 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19570 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19571 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19575 (define_insn "*sse2_andv2df3"
19576 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19577 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19578 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19580 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19581 "andpd\t{%2, %0|%0, %2}"
19582 [(set_attr "type" "sselog")
19583 (set_attr "mode" "V2DF")])
19585 (define_insn "*sse2_andv2df3"
19586 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19587 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19588 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19590 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19591 "andpd\t{%2, %0|%0, %2}"
19592 [(set_attr "type" "sselog")
19593 (set_attr "mode" "V2DF")])
19595 (define_expand "sse2_nandv2df3"
19596 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19597 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19598 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19602 (define_insn "*sse2_nandv2df3"
19603 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19604 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19605 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19607 "andnpd\t{%2, %0|%0, %2}"
19608 [(set_attr "type" "sselog")
19609 (set_attr "mode" "V2DF")])
19611 (define_insn "*sse_nandti3_df"
19612 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
19613 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19614 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
19616 "andnpd\t{%2, %0|%0, %2}"
19617 [(set_attr "type" "sselog")
19618 (set_attr "mode" "V2DF")])
19620 (define_expand "sse2_iorv2df3"
19621 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19622 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19623 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19627 (define_insn "*sse2_iorv2df3"
19628 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19629 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19630 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19632 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19633 "orpd\t{%2, %0|%0, %2}"
19634 [(set_attr "type" "sselog")
19635 (set_attr "mode" "V2DF")])
19637 (define_insn "*sse2_iordf3"
19638 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19639 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19640 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19642 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19643 "orpd\t{%2, %0|%0, %2}"
19644 [(set_attr "type" "sselog")
19645 (set_attr "mode" "V2DF")])
19647 (define_expand "sse2_xorv2df3"
19648 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19649 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
19650 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19654 (define_insn "*sse2_xorv2df3"
19655 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19656 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19657 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19659 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19660 "xorpd\t{%2, %0|%0, %2}"
19661 [(set_attr "type" "sselog")
19662 (set_attr "mode" "V2DF")])
19664 (define_insn "*sse2_xordf3"
19665 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19666 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19667 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19669 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19670 "xorpd\t{%2, %0|%0, %2}"
19671 [(set_attr "type" "sselog")
19672 (set_attr "mode" "V2DF")])
19674 ;; SSE2 integral logicals. These patterns must always come after floating
19675 ;; point ones since we don't want compiler to use integer opcodes on floating
19676 ;; point SSE values to avoid matching of subregs in the match_operand.
19677 (define_insn "*sse2_andti3"
19678 [(set (match_operand:TI 0 "register_operand" "=x")
19679 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19680 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19682 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19683 "pand\t{%2, %0|%0, %2}"
19684 [(set_attr "type" "sselog")
19685 (set_attr "mode" "TI")])
19687 (define_insn "sse2_andv2di3"
19688 [(set (match_operand:V2DI 0 "register_operand" "=x")
19689 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19690 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19692 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19693 "pand\t{%2, %0|%0, %2}"
19694 [(set_attr "type" "sselog")
19695 (set_attr "mode" "TI")])
19697 (define_insn "*sse2_nandti3"
19698 [(set (match_operand:TI 0 "register_operand" "=x")
19699 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19700 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19702 "pandn\t{%2, %0|%0, %2}"
19703 [(set_attr "type" "sselog")
19704 (set_attr "mode" "TI")])
19706 (define_insn "sse2_nandv2di3"
19707 [(set (match_operand:V2DI 0 "register_operand" "=x")
19708 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
19709 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19711 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19712 "pandn\t{%2, %0|%0, %2}"
19713 [(set_attr "type" "sselog")
19714 (set_attr "mode" "TI")])
19716 (define_insn "*sse2_iorti3"
19717 [(set (match_operand:TI 0 "register_operand" "=x")
19718 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19719 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19721 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19722 "por\t{%2, %0|%0, %2}"
19723 [(set_attr "type" "sselog")
19724 (set_attr "mode" "TI")])
19726 (define_insn "sse2_iorv2di3"
19727 [(set (match_operand:V2DI 0 "register_operand" "=x")
19728 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19729 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19731 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19732 "por\t{%2, %0|%0, %2}"
19733 [(set_attr "type" "sselog")
19734 (set_attr "mode" "TI")])
19736 (define_insn "*sse2_xorti3"
19737 [(set (match_operand:TI 0 "register_operand" "=x")
19738 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19739 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19741 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19742 "pxor\t{%2, %0|%0, %2}"
19743 [(set_attr "type" "sselog")
19744 (set_attr "mode" "TI")])
19746 (define_insn "sse2_xorv2di3"
19747 [(set (match_operand:V2DI 0 "register_operand" "=x")
19748 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19749 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19751 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19752 "pxor\t{%2, %0|%0, %2}"
19753 [(set_attr "type" "sselog")
19754 (set_attr "mode" "TI")])
19756 ;; Use xor, but don't show input operands so they aren't live before
19758 (define_insn "sse_clrv4sf"
19759 [(set (match_operand:V4SF 0 "register_operand" "=x")
19760 (match_operand:V4SF 1 "const0_operand" "X"))]
19763 if (get_attr_mode (insn) == MODE_TI)
19764 return "pxor\t{%0, %0|%0, %0}";
19766 return "xorps\t{%0, %0|%0, %0}";
19768 [(set_attr "type" "sselog")
19769 (set_attr "memory" "none")
19772 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
19774 (ne (symbol_ref "TARGET_SSE2")
19776 (eq (symbol_ref "optimize_size")
19778 (const_string "TI")
19779 (const_string "V4SF")))])
19781 ;; Use xor, but don't show input operands so they aren't live before
19783 (define_insn "sse_clrv2df"
19784 [(set (match_operand:V2DF 0 "register_operand" "=x")
19785 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
19787 "xorpd\t{%0, %0|%0, %0}"
19788 [(set_attr "type" "sselog")
19789 (set_attr "memory" "none")
19790 (set_attr "mode" "V4SF")])
19792 ;; SSE mask-generating compares
19794 (define_insn "maskcmpv4sf3"
19795 [(set (match_operand:V4SI 0 "register_operand" "=x")
19796 (match_operator:V4SI 3 "sse_comparison_operator"
19797 [(match_operand:V4SF 1 "register_operand" "0")
19798 (match_operand:V4SF 2 "register_operand" "x")]))]
19800 "cmp%D3ps\t{%2, %0|%0, %2}"
19801 [(set_attr "type" "ssecmp")
19802 (set_attr "mode" "V4SF")])
19804 (define_insn "maskncmpv4sf3"
19805 [(set (match_operand:V4SI 0 "register_operand" "=x")
19807 (match_operator:V4SI 3 "sse_comparison_operator"
19808 [(match_operand:V4SF 1 "register_operand" "0")
19809 (match_operand:V4SF 2 "register_operand" "x")])))]
19812 if (GET_CODE (operands[3]) == UNORDERED)
19813 return "cmpordps\t{%2, %0|%0, %2}";
19815 return "cmpn%D3ps\t{%2, %0|%0, %2}";
19817 [(set_attr "type" "ssecmp")
19818 (set_attr "mode" "V4SF")])
19820 (define_insn "vmmaskcmpv4sf3"
19821 [(set (match_operand:V4SI 0 "register_operand" "=x")
19823 (match_operator:V4SI 3 "sse_comparison_operator"
19824 [(match_operand:V4SF 1 "register_operand" "0")
19825 (match_operand:V4SF 2 "register_operand" "x")])
19826 (subreg:V4SI (match_dup 1) 0)
19829 "cmp%D3ss\t{%2, %0|%0, %2}"
19830 [(set_attr "type" "ssecmp")
19831 (set_attr "mode" "SF")])
19833 (define_insn "vmmaskncmpv4sf3"
19834 [(set (match_operand:V4SI 0 "register_operand" "=x")
19837 (match_operator:V4SI 3 "sse_comparison_operator"
19838 [(match_operand:V4SF 1 "register_operand" "0")
19839 (match_operand:V4SF 2 "register_operand" "x")]))
19840 (subreg:V4SI (match_dup 1) 0)
19844 if (GET_CODE (operands[3]) == UNORDERED)
19845 return "cmpordss\t{%2, %0|%0, %2}";
19847 return "cmpn%D3ss\t{%2, %0|%0, %2}";
19849 [(set_attr "type" "ssecmp")
19850 (set_attr "mode" "SF")])
19852 (define_insn "sse_comi"
19853 [(set (reg:CCFP 17)
19854 (compare:CCFP (vec_select:SF
19855 (match_operand:V4SF 0 "register_operand" "x")
19856 (parallel [(const_int 0)]))
19858 (match_operand:V4SF 1 "register_operand" "x")
19859 (parallel [(const_int 0)]))))]
19861 "comiss\t{%1, %0|%0, %1}"
19862 [(set_attr "type" "ssecomi")
19863 (set_attr "mode" "SF")])
19865 (define_insn "sse_ucomi"
19866 [(set (reg:CCFPU 17)
19867 (compare:CCFPU (vec_select:SF
19868 (match_operand:V4SF 0 "register_operand" "x")
19869 (parallel [(const_int 0)]))
19871 (match_operand:V4SF 1 "register_operand" "x")
19872 (parallel [(const_int 0)]))))]
19874 "ucomiss\t{%1, %0|%0, %1}"
19875 [(set_attr "type" "ssecomi")
19876 (set_attr "mode" "SF")])
19881 (define_insn "sse_unpckhps"
19882 [(set (match_operand:V4SF 0 "register_operand" "=x")
19884 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19885 (parallel [(const_int 2)
19889 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19890 (parallel [(const_int 0)
19896 "unpckhps\t{%2, %0|%0, %2}"
19897 [(set_attr "type" "ssecvt")
19898 (set_attr "mode" "V4SF")])
19900 (define_insn "sse_unpcklps"
19901 [(set (match_operand:V4SF 0 "register_operand" "=x")
19903 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19904 (parallel [(const_int 0)
19908 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19909 (parallel [(const_int 2)
19915 "unpcklps\t{%2, %0|%0, %2}"
19916 [(set_attr "type" "ssecvt")
19917 (set_attr "mode" "V4SF")])
19922 (define_insn "smaxv4sf3"
19923 [(set (match_operand:V4SF 0 "register_operand" "=x")
19924 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19925 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19927 "maxps\t{%2, %0|%0, %2}"
19928 [(set_attr "type" "sse")
19929 (set_attr "mode" "V4SF")])
19931 (define_insn "vmsmaxv4sf3"
19932 [(set (match_operand:V4SF 0 "register_operand" "=x")
19934 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19935 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19939 "maxss\t{%2, %0|%0, %2}"
19940 [(set_attr "type" "sse")
19941 (set_attr "mode" "SF")])
19943 (define_insn "sminv4sf3"
19944 [(set (match_operand:V4SF 0 "register_operand" "=x")
19945 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19946 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19948 "minps\t{%2, %0|%0, %2}"
19949 [(set_attr "type" "sse")
19950 (set_attr "mode" "V4SF")])
19952 (define_insn "vmsminv4sf3"
19953 [(set (match_operand:V4SF 0 "register_operand" "=x")
19955 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19956 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19960 "minss\t{%2, %0|%0, %2}"
19961 [(set_attr "type" "sse")
19962 (set_attr "mode" "SF")])
19964 ;; SSE <-> integer/MMX conversions
19966 (define_insn "cvtpi2ps"
19967 [(set (match_operand:V4SF 0 "register_operand" "=x")
19969 (match_operand:V4SF 1 "register_operand" "0")
19970 (vec_duplicate:V4SF
19971 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
19974 "cvtpi2ps\t{%2, %0|%0, %2}"
19975 [(set_attr "type" "ssecvt")
19976 (set_attr "mode" "V4SF")])
19978 (define_insn "cvtps2pi"
19979 [(set (match_operand:V2SI 0 "register_operand" "=y")
19981 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19982 (parallel [(const_int 0) (const_int 1)])))]
19984 "cvtps2pi\t{%1, %0|%0, %1}"
19985 [(set_attr "type" "ssecvt")
19986 (set_attr "mode" "V4SF")])
19988 (define_insn "cvttps2pi"
19989 [(set (match_operand:V2SI 0 "register_operand" "=y")
19991 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19993 (parallel [(const_int 0) (const_int 1)])))]
19995 "cvttps2pi\t{%1, %0|%0, %1}"
19996 [(set_attr "type" "ssecvt")
19997 (set_attr "mode" "SF")])
19999 (define_insn "cvtsi2ss"
20000 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20002 (match_operand:V4SF 1 "register_operand" "0,0")
20003 (vec_duplicate:V4SF
20004 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
20007 "cvtsi2ss\t{%2, %0|%0, %2}"
20008 [(set_attr "type" "sseicvt")
20009 (set_attr "athlon_decode" "vector,double")
20010 (set_attr "mode" "SF")])
20012 (define_insn "cvtsi2ssq"
20013 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20015 (match_operand:V4SF 1 "register_operand" "0,0")
20016 (vec_duplicate:V4SF
20017 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20019 "TARGET_SSE && TARGET_64BIT"
20020 "cvtsi2ssq\t{%2, %0|%0, %2}"
20021 [(set_attr "type" "sseicvt")
20022 (set_attr "athlon_decode" "vector,double")
20023 (set_attr "mode" "SF")])
20025 (define_insn "cvtss2si"
20026 [(set (match_operand:SI 0 "register_operand" "=r,r")
20028 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20029 (parallel [(const_int 0)])))]
20031 "cvtss2si\t{%1, %0|%0, %1}"
20032 [(set_attr "type" "sseicvt")
20033 (set_attr "athlon_decode" "double,vector")
20034 (set_attr "mode" "SI")])
20036 (define_insn "cvtss2siq"
20037 [(set (match_operand:DI 0 "register_operand" "=r,r")
20039 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20040 (parallel [(const_int 0)])))]
20042 "cvtss2siq\t{%1, %0|%0, %1}"
20043 [(set_attr "type" "sseicvt")
20044 (set_attr "athlon_decode" "double,vector")
20045 (set_attr "mode" "DI")])
20047 (define_insn "cvttss2si"
20048 [(set (match_operand:SI 0 "register_operand" "=r,r")
20050 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20052 (parallel [(const_int 0)])))]
20054 "cvttss2si\t{%1, %0|%0, %1}"
20055 [(set_attr "type" "sseicvt")
20056 (set_attr "mode" "SF")
20057 (set_attr "athlon_decode" "double,vector")])
20059 (define_insn "cvttss2siq"
20060 [(set (match_operand:DI 0 "register_operand" "=r,r")
20062 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20064 (parallel [(const_int 0)])))]
20065 "TARGET_SSE && TARGET_64BIT"
20066 "cvttss2siq\t{%1, %0|%0, %1}"
20067 [(set_attr "type" "sseicvt")
20068 (set_attr "mode" "SF")
20069 (set_attr "athlon_decode" "double,vector")])
20076 (define_insn "addv8qi3"
20077 [(set (match_operand:V8QI 0 "register_operand" "=y")
20078 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20079 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20081 "paddb\t{%2, %0|%0, %2}"
20082 [(set_attr "type" "mmxadd")
20083 (set_attr "mode" "DI")])
20085 (define_insn "addv4hi3"
20086 [(set (match_operand:V4HI 0 "register_operand" "=y")
20087 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20088 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20090 "paddw\t{%2, %0|%0, %2}"
20091 [(set_attr "type" "mmxadd")
20092 (set_attr "mode" "DI")])
20094 (define_insn "addv2si3"
20095 [(set (match_operand:V2SI 0 "register_operand" "=y")
20096 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
20097 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20099 "paddd\t{%2, %0|%0, %2}"
20100 [(set_attr "type" "mmxadd")
20101 (set_attr "mode" "DI")])
20103 (define_insn "mmx_adddi3"
20104 [(set (match_operand:DI 0 "register_operand" "=y")
20106 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
20107 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20110 "paddq\t{%2, %0|%0, %2}"
20111 [(set_attr "type" "mmxadd")
20112 (set_attr "mode" "DI")])
20114 (define_insn "ssaddv8qi3"
20115 [(set (match_operand:V8QI 0 "register_operand" "=y")
20116 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20117 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20119 "paddsb\t{%2, %0|%0, %2}"
20120 [(set_attr "type" "mmxadd")
20121 (set_attr "mode" "DI")])
20123 (define_insn "ssaddv4hi3"
20124 [(set (match_operand:V4HI 0 "register_operand" "=y")
20125 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20126 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20128 "paddsw\t{%2, %0|%0, %2}"
20129 [(set_attr "type" "mmxadd")
20130 (set_attr "mode" "DI")])
20132 (define_insn "usaddv8qi3"
20133 [(set (match_operand:V8QI 0 "register_operand" "=y")
20134 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20135 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20137 "paddusb\t{%2, %0|%0, %2}"
20138 [(set_attr "type" "mmxadd")
20139 (set_attr "mode" "DI")])
20141 (define_insn "usaddv4hi3"
20142 [(set (match_operand:V4HI 0 "register_operand" "=y")
20143 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20144 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20146 "paddusw\t{%2, %0|%0, %2}"
20147 [(set_attr "type" "mmxadd")
20148 (set_attr "mode" "DI")])
20150 (define_insn "subv8qi3"
20151 [(set (match_operand:V8QI 0 "register_operand" "=y")
20152 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20153 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20155 "psubb\t{%2, %0|%0, %2}"
20156 [(set_attr "type" "mmxadd")
20157 (set_attr "mode" "DI")])
20159 (define_insn "subv4hi3"
20160 [(set (match_operand:V4HI 0 "register_operand" "=y")
20161 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20162 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20164 "psubw\t{%2, %0|%0, %2}"
20165 [(set_attr "type" "mmxadd")
20166 (set_attr "mode" "DI")])
20168 (define_insn "subv2si3"
20169 [(set (match_operand:V2SI 0 "register_operand" "=y")
20170 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20171 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20173 "psubd\t{%2, %0|%0, %2}"
20174 [(set_attr "type" "mmxadd")
20175 (set_attr "mode" "DI")])
20177 (define_insn "mmx_subdi3"
20178 [(set (match_operand:DI 0 "register_operand" "=y")
20180 [(minus:DI (match_operand:DI 1 "register_operand" "0")
20181 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20184 "psubq\t{%2, %0|%0, %2}"
20185 [(set_attr "type" "mmxadd")
20186 (set_attr "mode" "DI")])
20188 (define_insn "sssubv8qi3"
20189 [(set (match_operand:V8QI 0 "register_operand" "=y")
20190 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20191 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20193 "psubsb\t{%2, %0|%0, %2}"
20194 [(set_attr "type" "mmxadd")
20195 (set_attr "mode" "DI")])
20197 (define_insn "sssubv4hi3"
20198 [(set (match_operand:V4HI 0 "register_operand" "=y")
20199 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20200 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20202 "psubsw\t{%2, %0|%0, %2}"
20203 [(set_attr "type" "mmxadd")
20204 (set_attr "mode" "DI")])
20206 (define_insn "ussubv8qi3"
20207 [(set (match_operand:V8QI 0 "register_operand" "=y")
20208 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20209 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20211 "psubusb\t{%2, %0|%0, %2}"
20212 [(set_attr "type" "mmxadd")
20213 (set_attr "mode" "DI")])
20215 (define_insn "ussubv4hi3"
20216 [(set (match_operand:V4HI 0 "register_operand" "=y")
20217 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20218 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20220 "psubusw\t{%2, %0|%0, %2}"
20221 [(set_attr "type" "mmxadd")
20222 (set_attr "mode" "DI")])
20224 (define_insn "mulv4hi3"
20225 [(set (match_operand:V4HI 0 "register_operand" "=y")
20226 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20227 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20229 "pmullw\t{%2, %0|%0, %2}"
20230 [(set_attr "type" "mmxmul")
20231 (set_attr "mode" "DI")])
20233 (define_insn "smulv4hi3_highpart"
20234 [(set (match_operand:V4HI 0 "register_operand" "=y")
20237 (mult:V4SI (sign_extend:V4SI
20238 (match_operand:V4HI 1 "register_operand" "0"))
20240 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20243 "pmulhw\t{%2, %0|%0, %2}"
20244 [(set_attr "type" "mmxmul")
20245 (set_attr "mode" "DI")])
20247 (define_insn "umulv4hi3_highpart"
20248 [(set (match_operand:V4HI 0 "register_operand" "=y")
20251 (mult:V4SI (zero_extend:V4SI
20252 (match_operand:V4HI 1 "register_operand" "0"))
20254 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20256 "TARGET_SSE || TARGET_3DNOW_A"
20257 "pmulhuw\t{%2, %0|%0, %2}"
20258 [(set_attr "type" "mmxmul")
20259 (set_attr "mode" "DI")])
20261 (define_insn "mmx_pmaddwd"
20262 [(set (match_operand:V2SI 0 "register_operand" "=y")
20266 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20267 (parallel [(const_int 0) (const_int 2)])))
20269 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20270 (parallel [(const_int 0) (const_int 2)]))))
20272 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20273 (parallel [(const_int 1)
20275 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20276 (parallel [(const_int 1)
20277 (const_int 3)]))))))]
20279 "pmaddwd\t{%2, %0|%0, %2}"
20280 [(set_attr "type" "mmxmul")
20281 (set_attr "mode" "DI")])
20284 ;; MMX logical operations
20285 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20286 ;; normal code that also wants to use the FPU from getting broken.
20287 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20288 (define_insn "mmx_iordi3"
20289 [(set (match_operand:DI 0 "register_operand" "=y")
20291 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20292 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20295 "por\t{%2, %0|%0, %2}"
20296 [(set_attr "type" "mmxadd")
20297 (set_attr "mode" "DI")])
20299 (define_insn "mmx_xordi3"
20300 [(set (match_operand:DI 0 "register_operand" "=y")
20302 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20303 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20306 "pxor\t{%2, %0|%0, %2}"
20307 [(set_attr "type" "mmxadd")
20308 (set_attr "mode" "DI")
20309 (set_attr "memory" "none")])
20311 ;; Same as pxor, but don't show input operands so that we don't think
20313 (define_insn "mmx_clrdi"
20314 [(set (match_operand:DI 0 "register_operand" "=y")
20315 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20317 "pxor\t{%0, %0|%0, %0}"
20318 [(set_attr "type" "mmxadd")
20319 (set_attr "mode" "DI")
20320 (set_attr "memory" "none")])
20322 (define_insn "mmx_anddi3"
20323 [(set (match_operand:DI 0 "register_operand" "=y")
20325 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20326 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20329 "pand\t{%2, %0|%0, %2}"
20330 [(set_attr "type" "mmxadd")
20331 (set_attr "mode" "DI")])
20333 (define_insn "mmx_nanddi3"
20334 [(set (match_operand:DI 0 "register_operand" "=y")
20336 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20337 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20340 "pandn\t{%2, %0|%0, %2}"
20341 [(set_attr "type" "mmxadd")
20342 (set_attr "mode" "DI")])
20345 ;; MMX unsigned averages/sum of absolute differences
20347 (define_insn "mmx_uavgv8qi3"
20348 [(set (match_operand:V8QI 0 "register_operand" "=y")
20350 (plus:V8QI (plus:V8QI
20351 (match_operand:V8QI 1 "register_operand" "0")
20352 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20353 (const_vector:V8QI [(const_int 1)
20362 "TARGET_SSE || TARGET_3DNOW_A"
20363 "pavgb\t{%2, %0|%0, %2}"
20364 [(set_attr "type" "mmxshft")
20365 (set_attr "mode" "DI")])
20367 (define_insn "mmx_uavgv4hi3"
20368 [(set (match_operand:V4HI 0 "register_operand" "=y")
20370 (plus:V4HI (plus:V4HI
20371 (match_operand:V4HI 1 "register_operand" "0")
20372 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20373 (const_vector:V4HI [(const_int 1)
20378 "TARGET_SSE || TARGET_3DNOW_A"
20379 "pavgw\t{%2, %0|%0, %2}"
20380 [(set_attr "type" "mmxshft")
20381 (set_attr "mode" "DI")])
20383 (define_insn "mmx_psadbw"
20384 [(set (match_operand:DI 0 "register_operand" "=y")
20385 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20386 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20388 "TARGET_SSE || TARGET_3DNOW_A"
20389 "psadbw\t{%2, %0|%0, %2}"
20390 [(set_attr "type" "mmxshft")
20391 (set_attr "mode" "DI")])
20394 ;; MMX insert/extract/shuffle
20396 (define_insn "mmx_pinsrw"
20397 [(set (match_operand:V4HI 0 "register_operand" "=y")
20398 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
20399 (vec_duplicate:V4HI
20400 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
20401 (match_operand:SI 3 "const_0_to_15_operand" "N")))]
20402 "TARGET_SSE || TARGET_3DNOW_A"
20403 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20404 [(set_attr "type" "mmxcvt")
20405 (set_attr "mode" "DI")])
20407 (define_insn "mmx_pextrw"
20408 [(set (match_operand:SI 0 "register_operand" "=r")
20409 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20411 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
20412 "TARGET_SSE || TARGET_3DNOW_A"
20413 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20414 [(set_attr "type" "mmxcvt")
20415 (set_attr "mode" "DI")])
20417 (define_insn "mmx_pshufw"
20418 [(set (match_operand:V4HI 0 "register_operand" "=y")
20419 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
20420 (match_operand:SI 2 "immediate_operand" "i")]
20422 "TARGET_SSE || TARGET_3DNOW_A"
20423 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20424 [(set_attr "type" "mmxcvt")
20425 (set_attr "mode" "DI")])
20428 ;; MMX mask-generating comparisons
20430 (define_insn "eqv8qi3"
20431 [(set (match_operand:V8QI 0 "register_operand" "=y")
20432 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20433 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20435 "pcmpeqb\t{%2, %0|%0, %2}"
20436 [(set_attr "type" "mmxcmp")
20437 (set_attr "mode" "DI")])
20439 (define_insn "eqv4hi3"
20440 [(set (match_operand:V4HI 0 "register_operand" "=y")
20441 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20442 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20444 "pcmpeqw\t{%2, %0|%0, %2}"
20445 [(set_attr "type" "mmxcmp")
20446 (set_attr "mode" "DI")])
20448 (define_insn "eqv2si3"
20449 [(set (match_operand:V2SI 0 "register_operand" "=y")
20450 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20451 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20453 "pcmpeqd\t{%2, %0|%0, %2}"
20454 [(set_attr "type" "mmxcmp")
20455 (set_attr "mode" "DI")])
20457 (define_insn "gtv8qi3"
20458 [(set (match_operand:V8QI 0 "register_operand" "=y")
20459 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20460 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20462 "pcmpgtb\t{%2, %0|%0, %2}"
20463 [(set_attr "type" "mmxcmp")
20464 (set_attr "mode" "DI")])
20466 (define_insn "gtv4hi3"
20467 [(set (match_operand:V4HI 0 "register_operand" "=y")
20468 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20469 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20471 "pcmpgtw\t{%2, %0|%0, %2}"
20472 [(set_attr "type" "mmxcmp")
20473 (set_attr "mode" "DI")])
20475 (define_insn "gtv2si3"
20476 [(set (match_operand:V2SI 0 "register_operand" "=y")
20477 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20478 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20480 "pcmpgtd\t{%2, %0|%0, %2}"
20481 [(set_attr "type" "mmxcmp")
20482 (set_attr "mode" "DI")])
20485 ;; MMX max/min insns
20487 (define_insn "umaxv8qi3"
20488 [(set (match_operand:V8QI 0 "register_operand" "=y")
20489 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20490 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20491 "TARGET_SSE || TARGET_3DNOW_A"
20492 "pmaxub\t{%2, %0|%0, %2}"
20493 [(set_attr "type" "mmxadd")
20494 (set_attr "mode" "DI")])
20496 (define_insn "smaxv4hi3"
20497 [(set (match_operand:V4HI 0 "register_operand" "=y")
20498 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20499 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20500 "TARGET_SSE || TARGET_3DNOW_A"
20501 "pmaxsw\t{%2, %0|%0, %2}"
20502 [(set_attr "type" "mmxadd")
20503 (set_attr "mode" "DI")])
20505 (define_insn "uminv8qi3"
20506 [(set (match_operand:V8QI 0 "register_operand" "=y")
20507 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20508 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20509 "TARGET_SSE || TARGET_3DNOW_A"
20510 "pminub\t{%2, %0|%0, %2}"
20511 [(set_attr "type" "mmxadd")
20512 (set_attr "mode" "DI")])
20514 (define_insn "sminv4hi3"
20515 [(set (match_operand:V4HI 0 "register_operand" "=y")
20516 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20517 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20518 "TARGET_SSE || TARGET_3DNOW_A"
20519 "pminsw\t{%2, %0|%0, %2}"
20520 [(set_attr "type" "mmxadd")
20521 (set_attr "mode" "DI")])
20526 (define_insn "ashrv4hi3"
20527 [(set (match_operand:V4HI 0 "register_operand" "=y")
20528 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20529 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20531 "psraw\t{%2, %0|%0, %2}"
20532 [(set_attr "type" "mmxshft")
20533 (set_attr "mode" "DI")])
20535 (define_insn "ashrv2si3"
20536 [(set (match_operand:V2SI 0 "register_operand" "=y")
20537 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20538 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20540 "psrad\t{%2, %0|%0, %2}"
20541 [(set_attr "type" "mmxshft")
20542 (set_attr "mode" "DI")])
20544 (define_insn "lshrv4hi3"
20545 [(set (match_operand:V4HI 0 "register_operand" "=y")
20546 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20547 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20549 "psrlw\t{%2, %0|%0, %2}"
20550 [(set_attr "type" "mmxshft")
20551 (set_attr "mode" "DI")])
20553 (define_insn "lshrv2si3"
20554 [(set (match_operand:V2SI 0 "register_operand" "=y")
20555 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20556 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20558 "psrld\t{%2, %0|%0, %2}"
20559 [(set_attr "type" "mmxshft")
20560 (set_attr "mode" "DI")])
20562 ;; See logical MMX insns.
20563 (define_insn "mmx_lshrdi3"
20564 [(set (match_operand:DI 0 "register_operand" "=y")
20566 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20567 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20570 "psrlq\t{%2, %0|%0, %2}"
20571 [(set_attr "type" "mmxshft")
20572 (set_attr "mode" "DI")])
20574 (define_insn "ashlv4hi3"
20575 [(set (match_operand:V4HI 0 "register_operand" "=y")
20576 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20577 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20579 "psllw\t{%2, %0|%0, %2}"
20580 [(set_attr "type" "mmxshft")
20581 (set_attr "mode" "DI")])
20583 (define_insn "ashlv2si3"
20584 [(set (match_operand:V2SI 0 "register_operand" "=y")
20585 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20586 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20588 "pslld\t{%2, %0|%0, %2}"
20589 [(set_attr "type" "mmxshft")
20590 (set_attr "mode" "DI")])
20592 ;; See logical MMX insns.
20593 (define_insn "mmx_ashldi3"
20594 [(set (match_operand:DI 0 "register_operand" "=y")
20596 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20597 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20600 "psllq\t{%2, %0|%0, %2}"
20601 [(set_attr "type" "mmxshft")
20602 (set_attr "mode" "DI")])
20605 ;; MMX pack/unpack insns.
20607 (define_insn "mmx_packsswb"
20608 [(set (match_operand:V8QI 0 "register_operand" "=y")
20610 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20611 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20613 "packsswb\t{%2, %0|%0, %2}"
20614 [(set_attr "type" "mmxshft")
20615 (set_attr "mode" "DI")])
20617 (define_insn "mmx_packssdw"
20618 [(set (match_operand:V4HI 0 "register_operand" "=y")
20620 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
20621 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
20623 "packssdw\t{%2, %0|%0, %2}"
20624 [(set_attr "type" "mmxshft")
20625 (set_attr "mode" "DI")])
20627 (define_insn "mmx_packuswb"
20628 [(set (match_operand:V8QI 0 "register_operand" "=y")
20630 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20631 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20633 "packuswb\t{%2, %0|%0, %2}"
20634 [(set_attr "type" "mmxshft")
20635 (set_attr "mode" "DI")])
20637 (define_insn "mmx_punpckhbw"
20638 [(set (match_operand:V8QI 0 "register_operand" "=y")
20640 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20641 (parallel [(const_int 4)
20649 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20650 (parallel [(const_int 0)
20660 "punpckhbw\t{%2, %0|%0, %2}"
20661 [(set_attr "type" "mmxcvt")
20662 (set_attr "mode" "DI")])
20664 (define_insn "mmx_punpckhwd"
20665 [(set (match_operand:V4HI 0 "register_operand" "=y")
20667 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20668 (parallel [(const_int 0)
20672 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20673 (parallel [(const_int 2)
20679 "punpckhwd\t{%2, %0|%0, %2}"
20680 [(set_attr "type" "mmxcvt")
20681 (set_attr "mode" "DI")])
20683 (define_insn "mmx_punpckhdq"
20684 [(set (match_operand:V2SI 0 "register_operand" "=y")
20686 (match_operand:V2SI 1 "register_operand" "0")
20687 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
20688 (parallel [(const_int 1)
20692 "punpckhdq\t{%2, %0|%0, %2}"
20693 [(set_attr "type" "mmxcvt")
20694 (set_attr "mode" "DI")])
20696 (define_insn "mmx_punpcklbw"
20697 [(set (match_operand:V8QI 0 "register_operand" "=y")
20699 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20700 (parallel [(const_int 0)
20708 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20709 (parallel [(const_int 4)
20719 "punpcklbw\t{%2, %0|%0, %2}"
20720 [(set_attr "type" "mmxcvt")
20721 (set_attr "mode" "DI")])
20723 (define_insn "mmx_punpcklwd"
20724 [(set (match_operand:V4HI 0 "register_operand" "=y")
20726 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20727 (parallel [(const_int 2)
20731 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20732 (parallel [(const_int 0)
20738 "punpcklwd\t{%2, %0|%0, %2}"
20739 [(set_attr "type" "mmxcvt")
20740 (set_attr "mode" "DI")])
20742 (define_insn "mmx_punpckldq"
20743 [(set (match_operand:V2SI 0 "register_operand" "=y")
20745 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
20746 (parallel [(const_int 1)
20748 (match_operand:V2SI 2 "register_operand" "y")
20751 "punpckldq\t{%2, %0|%0, %2}"
20752 [(set_attr "type" "mmxcvt")
20753 (set_attr "mode" "DI")])
20756 ;; Miscellaneous stuff
20758 (define_insn "emms"
20759 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
20760 (clobber (reg:XF 8))
20761 (clobber (reg:XF 9))
20762 (clobber (reg:XF 10))
20763 (clobber (reg:XF 11))
20764 (clobber (reg:XF 12))
20765 (clobber (reg:XF 13))
20766 (clobber (reg:XF 14))
20767 (clobber (reg:XF 15))
20768 (clobber (reg:DI 29))
20769 (clobber (reg:DI 30))
20770 (clobber (reg:DI 31))
20771 (clobber (reg:DI 32))
20772 (clobber (reg:DI 33))
20773 (clobber (reg:DI 34))
20774 (clobber (reg:DI 35))
20775 (clobber (reg:DI 36))]
20778 [(set_attr "type" "mmx")
20779 (set_attr "memory" "unknown")])
20781 (define_insn "ldmxcsr"
20782 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
20786 [(set_attr "type" "sse")
20787 (set_attr "memory" "load")])
20789 (define_insn "stmxcsr"
20790 [(set (match_operand:SI 0 "memory_operand" "=m")
20791 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
20794 [(set_attr "type" "sse")
20795 (set_attr "memory" "store")])
20797 (define_expand "sfence"
20798 [(set (match_dup 0)
20799 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20800 "TARGET_SSE || TARGET_3DNOW_A"
20802 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
20803 MEM_VOLATILE_P (operands[0]) = 1;
20806 (define_insn "*sfence_insn"
20807 [(set (match_operand:BLK 0 "" "")
20808 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20809 "TARGET_SSE || TARGET_3DNOW_A"
20811 [(set_attr "type" "sse")
20812 (set_attr "memory" "unknown")])
20814 (define_expand "sse_prologue_save"
20815 [(parallel [(set (match_operand:BLK 0 "" "")
20816 (unspec:BLK [(reg:DI 21)
20823 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20824 (use (match_operand:DI 1 "register_operand" ""))
20825 (use (match_operand:DI 2 "immediate_operand" ""))
20826 (use (label_ref:DI (match_operand 3 "" "")))])]
20830 (define_insn "*sse_prologue_save_insn"
20831 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
20832 (match_operand:DI 4 "const_int_operand" "n")))
20833 (unspec:BLK [(reg:DI 21)
20840 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20841 (use (match_operand:DI 1 "register_operand" "r"))
20842 (use (match_operand:DI 2 "const_int_operand" "i"))
20843 (use (label_ref:DI (match_operand 3 "" "X")))]
20845 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
20846 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
20850 operands[0] = gen_rtx_MEM (Pmode,
20851 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
20852 output_asm_insn (\"jmp\\t%A1\", operands);
20853 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
20855 operands[4] = adjust_address (operands[0], DImode, i*16);
20856 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
20857 PUT_MODE (operands[4], TImode);
20858 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
20859 output_asm_insn (\"rex\", operands);
20860 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
20862 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
20863 CODE_LABEL_NUMBER (operands[3]));
20867 [(set_attr "type" "other")
20868 (set_attr "length_immediate" "0")
20869 (set_attr "length_address" "0")
20870 (set_attr "length" "135")
20871 (set_attr "memory" "store")
20872 (set_attr "modrm" "0")
20873 (set_attr "mode" "DI")])
20875 ;; 3Dnow! instructions
20877 (define_insn "addv2sf3"
20878 [(set (match_operand:V2SF 0 "register_operand" "=y")
20879 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20880 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20882 "pfadd\\t{%2, %0|%0, %2}"
20883 [(set_attr "type" "mmxadd")
20884 (set_attr "mode" "V2SF")])
20886 (define_insn "subv2sf3"
20887 [(set (match_operand:V2SF 0 "register_operand" "=y")
20888 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20889 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20891 "pfsub\\t{%2, %0|%0, %2}"
20892 [(set_attr "type" "mmxadd")
20893 (set_attr "mode" "V2SF")])
20895 (define_insn "subrv2sf3"
20896 [(set (match_operand:V2SF 0 "register_operand" "=y")
20897 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
20898 (match_operand:V2SF 1 "register_operand" "0")))]
20900 "pfsubr\\t{%2, %0|%0, %2}"
20901 [(set_attr "type" "mmxadd")
20902 (set_attr "mode" "V2SF")])
20904 (define_insn "gtv2sf3"
20905 [(set (match_operand:V2SI 0 "register_operand" "=y")
20906 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
20907 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20909 "pfcmpgt\\t{%2, %0|%0, %2}"
20910 [(set_attr "type" "mmxcmp")
20911 (set_attr "mode" "V2SF")])
20913 (define_insn "gev2sf3"
20914 [(set (match_operand:V2SI 0 "register_operand" "=y")
20915 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
20916 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20918 "pfcmpge\\t{%2, %0|%0, %2}"
20919 [(set_attr "type" "mmxcmp")
20920 (set_attr "mode" "V2SF")])
20922 (define_insn "eqv2sf3"
20923 [(set (match_operand:V2SI 0 "register_operand" "=y")
20924 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
20925 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20927 "pfcmpeq\\t{%2, %0|%0, %2}"
20928 [(set_attr "type" "mmxcmp")
20929 (set_attr "mode" "V2SF")])
20931 (define_insn "pfmaxv2sf3"
20932 [(set (match_operand:V2SF 0 "register_operand" "=y")
20933 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
20934 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20936 "pfmax\\t{%2, %0|%0, %2}"
20937 [(set_attr "type" "mmxadd")
20938 (set_attr "mode" "V2SF")])
20940 (define_insn "pfminv2sf3"
20941 [(set (match_operand:V2SF 0 "register_operand" "=y")
20942 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
20943 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20945 "pfmin\\t{%2, %0|%0, %2}"
20946 [(set_attr "type" "mmxadd")
20947 (set_attr "mode" "V2SF")])
20949 (define_insn "mulv2sf3"
20950 [(set (match_operand:V2SF 0 "register_operand" "=y")
20951 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
20952 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20954 "pfmul\\t{%2, %0|%0, %2}"
20955 [(set_attr "type" "mmxmul")
20956 (set_attr "mode" "V2SF")])
20958 (define_insn "femms"
20959 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
20960 (clobber (reg:XF 8))
20961 (clobber (reg:XF 9))
20962 (clobber (reg:XF 10))
20963 (clobber (reg:XF 11))
20964 (clobber (reg:XF 12))
20965 (clobber (reg:XF 13))
20966 (clobber (reg:XF 14))
20967 (clobber (reg:XF 15))
20968 (clobber (reg:DI 29))
20969 (clobber (reg:DI 30))
20970 (clobber (reg:DI 31))
20971 (clobber (reg:DI 32))
20972 (clobber (reg:DI 33))
20973 (clobber (reg:DI 34))
20974 (clobber (reg:DI 35))
20975 (clobber (reg:DI 36))]
20978 [(set_attr "type" "mmx")
20979 (set_attr "memory" "none")])
20981 (define_insn "pf2id"
20982 [(set (match_operand:V2SI 0 "register_operand" "=y")
20983 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
20985 "pf2id\\t{%1, %0|%0, %1}"
20986 [(set_attr "type" "mmxcvt")
20987 (set_attr "mode" "V2SF")])
20989 (define_insn "pf2iw"
20990 [(set (match_operand:V2SI 0 "register_operand" "=y")
20993 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
20995 "pf2iw\\t{%1, %0|%0, %1}"
20996 [(set_attr "type" "mmxcvt")
20997 (set_attr "mode" "V2SF")])
20999 (define_insn "pfacc"
21000 [(set (match_operand:V2SF 0 "register_operand" "=y")
21003 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21004 (parallel [(const_int 0)]))
21005 (vec_select:SF (match_dup 1)
21006 (parallel [(const_int 1)])))
21008 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21009 (parallel [(const_int 0)]))
21010 (vec_select:SF (match_dup 2)
21011 (parallel [(const_int 1)])))))]
21013 "pfacc\\t{%2, %0|%0, %2}"
21014 [(set_attr "type" "mmxadd")
21015 (set_attr "mode" "V2SF")])
21017 (define_insn "pfnacc"
21018 [(set (match_operand:V2SF 0 "register_operand" "=y")
21021 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21022 (parallel [(const_int 0)]))
21023 (vec_select:SF (match_dup 1)
21024 (parallel [(const_int 1)])))
21026 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21027 (parallel [(const_int 0)]))
21028 (vec_select:SF (match_dup 2)
21029 (parallel [(const_int 1)])))))]
21031 "pfnacc\\t{%2, %0|%0, %2}"
21032 [(set_attr "type" "mmxadd")
21033 (set_attr "mode" "V2SF")])
21035 (define_insn "pfpnacc"
21036 [(set (match_operand:V2SF 0 "register_operand" "=y")
21039 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21040 (parallel [(const_int 0)]))
21041 (vec_select:SF (match_dup 1)
21042 (parallel [(const_int 1)])))
21044 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21045 (parallel [(const_int 0)]))
21046 (vec_select:SF (match_dup 2)
21047 (parallel [(const_int 1)])))))]
21049 "pfpnacc\\t{%2, %0|%0, %2}"
21050 [(set_attr "type" "mmxadd")
21051 (set_attr "mode" "V2SF")])
21053 (define_insn "pi2fw"
21054 [(set (match_operand:V2SF 0 "register_operand" "=y")
21059 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21060 (parallel [(const_int 0)]))))
21063 (vec_select:SI (match_dup 1)
21064 (parallel [(const_int 1)])))))))]
21066 "pi2fw\\t{%1, %0|%0, %1}"
21067 [(set_attr "type" "mmxcvt")
21068 (set_attr "mode" "V2SF")])
21070 (define_insn "floatv2si2"
21071 [(set (match_operand:V2SF 0 "register_operand" "=y")
21072 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21074 "pi2fd\\t{%1, %0|%0, %1}"
21075 [(set_attr "type" "mmxcvt")
21076 (set_attr "mode" "V2SF")])
21078 ;; This insn is identical to pavgb in operation, but the opcode is
21079 ;; different. To avoid accidentally matching pavgb, use an unspec.
21081 (define_insn "pavgusb"
21082 [(set (match_operand:V8QI 0 "register_operand" "=y")
21084 [(match_operand:V8QI 1 "register_operand" "0")
21085 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21088 "pavgusb\\t{%2, %0|%0, %2}"
21089 [(set_attr "type" "mmxshft")
21090 (set_attr "mode" "TI")])
21092 ;; 3DNow reciprocal and sqrt
21094 (define_insn "pfrcpv2sf2"
21095 [(set (match_operand:V2SF 0 "register_operand" "=y")
21096 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21099 "pfrcp\\t{%1, %0|%0, %1}"
21100 [(set_attr "type" "mmx")
21101 (set_attr "mode" "TI")])
21103 (define_insn "pfrcpit1v2sf3"
21104 [(set (match_operand:V2SF 0 "register_operand" "=y")
21105 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21106 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21109 "pfrcpit1\\t{%2, %0|%0, %2}"
21110 [(set_attr "type" "mmx")
21111 (set_attr "mode" "TI")])
21113 (define_insn "pfrcpit2v2sf3"
21114 [(set (match_operand:V2SF 0 "register_operand" "=y")
21115 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21116 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21119 "pfrcpit2\\t{%2, %0|%0, %2}"
21120 [(set_attr "type" "mmx")
21121 (set_attr "mode" "TI")])
21123 (define_insn "pfrsqrtv2sf2"
21124 [(set (match_operand:V2SF 0 "register_operand" "=y")
21125 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21128 "pfrsqrt\\t{%1, %0|%0, %1}"
21129 [(set_attr "type" "mmx")
21130 (set_attr "mode" "TI")])
21132 (define_insn "pfrsqit1v2sf3"
21133 [(set (match_operand:V2SF 0 "register_operand" "=y")
21134 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21135 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21138 "pfrsqit1\\t{%2, %0|%0, %2}"
21139 [(set_attr "type" "mmx")
21140 (set_attr "mode" "TI")])
21142 (define_insn "pmulhrwv4hi3"
21143 [(set (match_operand:V4HI 0 "register_operand" "=y")
21149 (match_operand:V4HI 1 "register_operand" "0"))
21151 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21152 (const_vector:V4SI [(const_int 32768)
21155 (const_int 32768)]))
21158 "pmulhrw\\t{%2, %0|%0, %2}"
21159 [(set_attr "type" "mmxmul")
21160 (set_attr "mode" "TI")])
21162 (define_insn "pswapdv2si2"
21163 [(set (match_operand:V2SI 0 "register_operand" "=y")
21164 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21165 (parallel [(const_int 1) (const_int 0)])))]
21167 "pswapd\\t{%1, %0|%0, %1}"
21168 [(set_attr "type" "mmxcvt")
21169 (set_attr "mode" "TI")])
21171 (define_insn "pswapdv2sf2"
21172 [(set (match_operand:V2SF 0 "register_operand" "=y")
21173 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21174 (parallel [(const_int 1) (const_int 0)])))]
21176 "pswapd\\t{%1, %0|%0, %1}"
21177 [(set_attr "type" "mmxcvt")
21178 (set_attr "mode" "TI")])
21180 (define_expand "prefetch"
21181 [(prefetch (match_operand 0 "address_operand" "")
21182 (match_operand:SI 1 "const_int_operand" "")
21183 (match_operand:SI 2 "const_int_operand" ""))]
21184 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21186 int rw = INTVAL (operands[1]);
21187 int locality = INTVAL (operands[2]);
21189 if (rw != 0 && rw != 1)
21191 if (locality < 0 || locality > 3)
21193 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21196 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21197 suported by SSE counterpart or the SSE prefetch is not available
21198 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21200 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21201 operands[2] = GEN_INT (3);
21203 operands[1] = const0_rtx;
21206 (define_insn "*prefetch_sse"
21207 [(prefetch (match_operand:SI 0 "address_operand" "p")
21209 (match_operand:SI 1 "const_int_operand" ""))]
21210 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21212 static const char * const patterns[4] = {
21213 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21216 int locality = INTVAL (operands[1]);
21217 if (locality < 0 || locality > 3)
21220 return patterns[locality];
21222 [(set_attr "type" "sse")
21223 (set_attr "memory" "none")])
21225 (define_insn "*prefetch_sse_rex"
21226 [(prefetch (match_operand:DI 0 "address_operand" "p")
21228 (match_operand:SI 1 "const_int_operand" ""))]
21229 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21231 static const char * const patterns[4] = {
21232 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21235 int locality = INTVAL (operands[1]);
21236 if (locality < 0 || locality > 3)
21239 return patterns[locality];
21241 [(set_attr "type" "sse")
21242 (set_attr "memory" "none")])
21244 (define_insn "*prefetch_3dnow"
21245 [(prefetch (match_operand:SI 0 "address_operand" "p")
21246 (match_operand:SI 1 "const_int_operand" "n")
21248 "TARGET_3DNOW && !TARGET_64BIT"
21250 if (INTVAL (operands[1]) == 0)
21251 return "prefetch\t%a0";
21253 return "prefetchw\t%a0";
21255 [(set_attr "type" "mmx")
21256 (set_attr "memory" "none")])
21258 (define_insn "*prefetch_3dnow_rex"
21259 [(prefetch (match_operand:DI 0 "address_operand" "p")
21260 (match_operand:SI 1 "const_int_operand" "n")
21262 "TARGET_3DNOW && TARGET_64BIT"
21264 if (INTVAL (operands[1]) == 0)
21265 return "prefetch\t%a0";
21267 return "prefetchw\t%a0";
21269 [(set_attr "type" "mmx")
21270 (set_attr "memory" "none")])
21274 (define_insn "addv2df3"
21275 [(set (match_operand:V2DF 0 "register_operand" "=x")
21276 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21277 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21279 "addpd\t{%2, %0|%0, %2}"
21280 [(set_attr "type" "sseadd")
21281 (set_attr "mode" "V2DF")])
21283 (define_insn "vmaddv2df3"
21284 [(set (match_operand:V2DF 0 "register_operand" "=x")
21285 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21286 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21290 "addsd\t{%2, %0|%0, %2}"
21291 [(set_attr "type" "sseadd")
21292 (set_attr "mode" "DF")])
21294 (define_insn "subv2df3"
21295 [(set (match_operand:V2DF 0 "register_operand" "=x")
21296 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21297 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21299 "subpd\t{%2, %0|%0, %2}"
21300 [(set_attr "type" "sseadd")
21301 (set_attr "mode" "V2DF")])
21303 (define_insn "vmsubv2df3"
21304 [(set (match_operand:V2DF 0 "register_operand" "=x")
21305 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21306 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21310 "subsd\t{%2, %0|%0, %2}"
21311 [(set_attr "type" "sseadd")
21312 (set_attr "mode" "DF")])
21314 (define_insn "mulv2df3"
21315 [(set (match_operand:V2DF 0 "register_operand" "=x")
21316 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21317 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21319 "mulpd\t{%2, %0|%0, %2}"
21320 [(set_attr "type" "ssemul")
21321 (set_attr "mode" "V2DF")])
21323 (define_insn "vmmulv2df3"
21324 [(set (match_operand:V2DF 0 "register_operand" "=x")
21325 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21326 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21330 "mulsd\t{%2, %0|%0, %2}"
21331 [(set_attr "type" "ssemul")
21332 (set_attr "mode" "DF")])
21334 (define_insn "divv2df3"
21335 [(set (match_operand:V2DF 0 "register_operand" "=x")
21336 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21337 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21339 "divpd\t{%2, %0|%0, %2}"
21340 [(set_attr "type" "ssediv")
21341 (set_attr "mode" "V2DF")])
21343 (define_insn "vmdivv2df3"
21344 [(set (match_operand:V2DF 0 "register_operand" "=x")
21345 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21346 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21350 "divsd\t{%2, %0|%0, %2}"
21351 [(set_attr "type" "ssediv")
21352 (set_attr "mode" "DF")])
21356 (define_insn "smaxv2df3"
21357 [(set (match_operand:V2DF 0 "register_operand" "=x")
21358 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21359 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21361 "maxpd\t{%2, %0|%0, %2}"
21362 [(set_attr "type" "sseadd")
21363 (set_attr "mode" "V2DF")])
21365 (define_insn "vmsmaxv2df3"
21366 [(set (match_operand:V2DF 0 "register_operand" "=x")
21367 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21368 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21372 "maxsd\t{%2, %0|%0, %2}"
21373 [(set_attr "type" "sseadd")
21374 (set_attr "mode" "DF")])
21376 (define_insn "sminv2df3"
21377 [(set (match_operand:V2DF 0 "register_operand" "=x")
21378 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21379 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21381 "minpd\t{%2, %0|%0, %2}"
21382 [(set_attr "type" "sseadd")
21383 (set_attr "mode" "V2DF")])
21385 (define_insn "vmsminv2df3"
21386 [(set (match_operand:V2DF 0 "register_operand" "=x")
21387 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21388 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21392 "minsd\t{%2, %0|%0, %2}"
21393 [(set_attr "type" "sseadd")
21394 (set_attr "mode" "DF")])
21395 ;; SSE2 square root. There doesn't appear to be an extension for the
21396 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
21398 (define_insn "sqrtv2df2"
21399 [(set (match_operand:V2DF 0 "register_operand" "=x")
21400 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
21402 "sqrtpd\t{%1, %0|%0, %1}"
21403 [(set_attr "type" "sse")
21404 (set_attr "mode" "V2DF")])
21406 (define_insn "vmsqrtv2df2"
21407 [(set (match_operand:V2DF 0 "register_operand" "=x")
21408 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
21409 (match_operand:V2DF 2 "register_operand" "0")
21412 "sqrtsd\t{%1, %0|%0, %1}"
21413 [(set_attr "type" "sse")
21414 (set_attr "mode" "SF")])
21416 ;; SSE mask-generating compares
21418 (define_insn "maskcmpv2df3"
21419 [(set (match_operand:V2DI 0 "register_operand" "=x")
21420 (match_operator:V2DI 3 "sse_comparison_operator"
21421 [(match_operand:V2DF 1 "register_operand" "0")
21422 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
21424 "cmp%D3pd\t{%2, %0|%0, %2}"
21425 [(set_attr "type" "ssecmp")
21426 (set_attr "mode" "V2DF")])
21428 (define_insn "maskncmpv2df3"
21429 [(set (match_operand:V2DI 0 "register_operand" "=x")
21431 (match_operator:V2DI 3 "sse_comparison_operator"
21432 [(match_operand:V2DF 1 "register_operand" "0")
21433 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
21436 if (GET_CODE (operands[3]) == UNORDERED)
21437 return "cmpordps\t{%2, %0|%0, %2}";
21439 return "cmpn%D3pd\t{%2, %0|%0, %2}";
21441 [(set_attr "type" "ssecmp")
21442 (set_attr "mode" "V2DF")])
21444 (define_insn "vmmaskcmpv2df3"
21445 [(set (match_operand:V2DI 0 "register_operand" "=x")
21447 (match_operator:V2DI 3 "sse_comparison_operator"
21448 [(match_operand:V2DF 1 "register_operand" "0")
21449 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
21450 (subreg:V2DI (match_dup 1) 0)
21453 "cmp%D3sd\t{%2, %0|%0, %2}"
21454 [(set_attr "type" "ssecmp")
21455 (set_attr "mode" "DF")])
21457 (define_insn "vmmaskncmpv2df3"
21458 [(set (match_operand:V2DI 0 "register_operand" "=x")
21461 (match_operator:V2DI 3 "sse_comparison_operator"
21462 [(match_operand:V2DF 1 "register_operand" "0")
21463 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
21464 (subreg:V2DI (match_dup 1) 0)
21468 if (GET_CODE (operands[3]) == UNORDERED)
21469 return "cmpordsd\t{%2, %0|%0, %2}";
21471 return "cmpn%D3sd\t{%2, %0|%0, %2}";
21473 [(set_attr "type" "ssecmp")
21474 (set_attr "mode" "DF")])
21476 (define_insn "sse2_comi"
21477 [(set (reg:CCFP 17)
21478 (compare:CCFP (vec_select:DF
21479 (match_operand:V2DF 0 "register_operand" "x")
21480 (parallel [(const_int 0)]))
21482 (match_operand:V2DF 1 "register_operand" "x")
21483 (parallel [(const_int 0)]))))]
21485 "comisd\t{%1, %0|%0, %1}"
21486 [(set_attr "type" "ssecomi")
21487 (set_attr "mode" "DF")])
21489 (define_insn "sse2_ucomi"
21490 [(set (reg:CCFPU 17)
21491 (compare:CCFPU (vec_select:DF
21492 (match_operand:V2DF 0 "register_operand" "x")
21493 (parallel [(const_int 0)]))
21495 (match_operand:V2DF 1 "register_operand" "x")
21496 (parallel [(const_int 0)]))))]
21498 "ucomisd\t{%1, %0|%0, %1}"
21499 [(set_attr "type" "ssecomi")
21500 (set_attr "mode" "DF")])
21502 ;; SSE Strange Moves.
21504 (define_insn "sse2_movmskpd"
21505 [(set (match_operand:SI 0 "register_operand" "=r")
21506 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
21509 "movmskpd\t{%1, %0|%0, %1}"
21510 [(set_attr "type" "ssecvt")
21511 (set_attr "mode" "V2DF")])
21513 (define_insn "sse2_pmovmskb"
21514 [(set (match_operand:SI 0 "register_operand" "=r")
21515 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
21518 "pmovmskb\t{%1, %0|%0, %1}"
21519 [(set_attr "type" "ssecvt")
21520 (set_attr "mode" "V2DF")])
21522 (define_insn "sse2_maskmovdqu"
21523 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
21524 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21525 (match_operand:V16QI 2 "register_operand" "x")]
21528 ;; @@@ check ordering of operands in intel/nonintel syntax
21529 "maskmovdqu\t{%2, %1|%1, %2}"
21530 [(set_attr "type" "ssecvt")
21531 (set_attr "mode" "TI")])
21533 (define_insn "sse2_maskmovdqu_rex64"
21534 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
21535 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21536 (match_operand:V16QI 2 "register_operand" "x")]
21539 ;; @@@ check ordering of operands in intel/nonintel syntax
21540 "maskmovdqu\t{%2, %1|%1, %2}"
21541 [(set_attr "type" "ssecvt")
21542 (set_attr "mode" "TI")])
21544 (define_insn "sse2_movntv2df"
21545 [(set (match_operand:V2DF 0 "memory_operand" "=m")
21546 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
21549 "movntpd\t{%1, %0|%0, %1}"
21550 [(set_attr "type" "ssecvt")
21551 (set_attr "mode" "V2DF")])
21553 (define_insn "sse2_movntv2di"
21554 [(set (match_operand:V2DI 0 "memory_operand" "=m")
21555 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
21558 "movntdq\t{%1, %0|%0, %1}"
21559 [(set_attr "type" "ssecvt")
21560 (set_attr "mode" "TI")])
21562 (define_insn "sse2_movntsi"
21563 [(set (match_operand:SI 0 "memory_operand" "=m")
21564 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
21567 "movnti\t{%1, %0|%0, %1}"
21568 [(set_attr "type" "ssecvt")
21569 (set_attr "mode" "V2DF")])
21571 ;; SSE <-> integer/MMX conversions
21573 ;; Conversions between SI and SF
21575 (define_insn "cvtdq2ps"
21576 [(set (match_operand:V4SF 0 "register_operand" "=x")
21577 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
21579 "cvtdq2ps\t{%1, %0|%0, %1}"
21580 [(set_attr "type" "ssecvt")
21581 (set_attr "mode" "V2DF")])
21583 (define_insn "cvtps2dq"
21584 [(set (match_operand:V4SI 0 "register_operand" "=x")
21585 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21587 "cvtps2dq\t{%1, %0|%0, %1}"
21588 [(set_attr "type" "ssecvt")
21589 (set_attr "mode" "TI")])
21591 (define_insn "cvttps2dq"
21592 [(set (match_operand:V4SI 0 "register_operand" "=x")
21593 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21596 "cvttps2dq\t{%1, %0|%0, %1}"
21597 [(set_attr "type" "ssecvt")
21598 (set_attr "mode" "TI")])
21600 ;; Conversions between SI and DF
21602 (define_insn "cvtdq2pd"
21603 [(set (match_operand:V2DF 0 "register_operand" "=x")
21604 (float:V2DF (vec_select:V2SI
21605 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
21608 (const_int 1)]))))]
21610 "cvtdq2pd\t{%1, %0|%0, %1}"
21611 [(set_attr "type" "ssecvt")
21612 (set_attr "mode" "V2DF")])
21614 (define_insn "cvtpd2dq"
21615 [(set (match_operand:V4SI 0 "register_operand" "=x")
21617 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
21618 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21620 "cvtpd2dq\t{%1, %0|%0, %1}"
21621 [(set_attr "type" "ssecvt")
21622 (set_attr "mode" "TI")])
21624 (define_insn "cvttpd2dq"
21625 [(set (match_operand:V4SI 0 "register_operand" "=x")
21627 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21629 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21631 "cvttpd2dq\t{%1, %0|%0, %1}"
21632 [(set_attr "type" "ssecvt")
21633 (set_attr "mode" "TI")])
21635 (define_insn "cvtpd2pi"
21636 [(set (match_operand:V2SI 0 "register_operand" "=y")
21637 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
21639 "cvtpd2pi\t{%1, %0|%0, %1}"
21640 [(set_attr "type" "ssecvt")
21641 (set_attr "mode" "TI")])
21643 (define_insn "cvttpd2pi"
21644 [(set (match_operand:V2SI 0 "register_operand" "=y")
21645 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21648 "cvttpd2pi\t{%1, %0|%0, %1}"
21649 [(set_attr "type" "ssecvt")
21650 (set_attr "mode" "TI")])
21652 (define_insn "cvtpi2pd"
21653 [(set (match_operand:V2DF 0 "register_operand" "=x")
21654 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21656 "cvtpi2pd\t{%1, %0|%0, %1}"
21657 [(set_attr "type" "ssecvt")
21658 (set_attr "mode" "TI")])
21660 ;; Conversions between SI and DF
21662 (define_insn "cvtsd2si"
21663 [(set (match_operand:SI 0 "register_operand" "=r,r")
21664 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
21665 (parallel [(const_int 0)]))))]
21667 "cvtsd2si\t{%1, %0|%0, %1}"
21668 [(set_attr "type" "sseicvt")
21669 (set_attr "athlon_decode" "double,vector")
21670 (set_attr "mode" "SI")])
21672 (define_insn "cvtsd2siq"
21673 [(set (match_operand:DI 0 "register_operand" "=r,r")
21674 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
21675 (parallel [(const_int 0)]))))]
21676 "TARGET_SSE2 && TARGET_64BIT"
21677 "cvtsd2siq\t{%1, %0|%0, %1}"
21678 [(set_attr "type" "sseicvt")
21679 (set_attr "athlon_decode" "double,vector")
21680 (set_attr "mode" "DI")])
21682 (define_insn "cvttsd2si"
21683 [(set (match_operand:SI 0 "register_operand" "=r,r")
21684 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21685 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21687 "cvttsd2si\t{%1, %0|%0, %1}"
21688 [(set_attr "type" "sseicvt")
21689 (set_attr "mode" "SI")
21690 (set_attr "athlon_decode" "double,vector")])
21692 (define_insn "cvttsd2siq"
21693 [(set (match_operand:DI 0 "register_operand" "=r,r")
21694 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21695 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21696 "TARGET_SSE2 && TARGET_64BIT"
21697 "cvttsd2siq\t{%1, %0|%0, %1}"
21698 [(set_attr "type" "sseicvt")
21699 (set_attr "mode" "DI")
21700 (set_attr "athlon_decode" "double,vector")])
21702 (define_insn "cvtsi2sd"
21703 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21704 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21705 (vec_duplicate:V2DF
21707 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21710 "cvtsi2sd\t{%2, %0|%0, %2}"
21711 [(set_attr "type" "sseicvt")
21712 (set_attr "mode" "DF")
21713 (set_attr "athlon_decode" "double,direct")])
21715 (define_insn "cvtsi2sdq"
21716 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21717 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21718 (vec_duplicate:V2DF
21720 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21722 "TARGET_SSE2 && TARGET_64BIT"
21723 "cvtsi2sdq\t{%2, %0|%0, %2}"
21724 [(set_attr "type" "sseicvt")
21725 (set_attr "mode" "DF")
21726 (set_attr "athlon_decode" "double,direct")])
21728 ;; Conversions between SF and DF
21730 (define_insn "cvtsd2ss"
21731 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21732 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
21733 (vec_duplicate:V4SF
21734 (float_truncate:V2SF
21735 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
21738 "cvtsd2ss\t{%2, %0|%0, %2}"
21739 [(set_attr "type" "ssecvt")
21740 (set_attr "athlon_decode" "vector,double")
21741 (set_attr "mode" "SF")])
21743 (define_insn "cvtss2sd"
21744 [(set (match_operand:V2DF 0 "register_operand" "=x")
21745 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
21748 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
21749 (parallel [(const_int 0)
21753 "cvtss2sd\t{%2, %0|%0, %2}"
21754 [(set_attr "type" "ssecvt")
21755 (set_attr "mode" "DF")])
21757 (define_insn "cvtpd2ps"
21758 [(set (match_operand:V4SF 0 "register_operand" "=x")
21761 (subreg:V2SI (float_truncate:V2SF
21762 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
21763 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
21765 "cvtpd2ps\t{%1, %0|%0, %1}"
21766 [(set_attr "type" "ssecvt")
21767 (set_attr "mode" "V4SF")])
21769 (define_insn "cvtps2pd"
21770 [(set (match_operand:V2DF 0 "register_operand" "=x")
21772 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
21773 (parallel [(const_int 0)
21774 (const_int 1)]))))]
21776 "cvtps2pd\t{%1, %0|%0, %1}"
21777 [(set_attr "type" "ssecvt")
21778 (set_attr "mode" "V2DF")])
21780 ;; SSE2 variants of MMX insns
21784 (define_insn "addv16qi3"
21785 [(set (match_operand:V16QI 0 "register_operand" "=x")
21786 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21787 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21789 "paddb\t{%2, %0|%0, %2}"
21790 [(set_attr "type" "sseiadd")
21791 (set_attr "mode" "TI")])
21793 (define_insn "addv8hi3"
21794 [(set (match_operand:V8HI 0 "register_operand" "=x")
21795 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21796 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21798 "paddw\t{%2, %0|%0, %2}"
21799 [(set_attr "type" "sseiadd")
21800 (set_attr "mode" "TI")])
21802 (define_insn "addv4si3"
21803 [(set (match_operand:V4SI 0 "register_operand" "=x")
21804 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
21805 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21807 "paddd\t{%2, %0|%0, %2}"
21808 [(set_attr "type" "sseiadd")
21809 (set_attr "mode" "TI")])
21811 (define_insn "addv2di3"
21812 [(set (match_operand:V2DI 0 "register_operand" "=x")
21813 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
21814 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21816 "paddq\t{%2, %0|%0, %2}"
21817 [(set_attr "type" "sseiadd")
21818 (set_attr "mode" "TI")])
21820 (define_insn "ssaddv16qi3"
21821 [(set (match_operand:V16QI 0 "register_operand" "=x")
21822 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21823 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21825 "paddsb\t{%2, %0|%0, %2}"
21826 [(set_attr "type" "sseiadd")
21827 (set_attr "mode" "TI")])
21829 (define_insn "ssaddv8hi3"
21830 [(set (match_operand:V8HI 0 "register_operand" "=x")
21831 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21832 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21834 "paddsw\t{%2, %0|%0, %2}"
21835 [(set_attr "type" "sseiadd")
21836 (set_attr "mode" "TI")])
21838 (define_insn "usaddv16qi3"
21839 [(set (match_operand:V16QI 0 "register_operand" "=x")
21840 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21841 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21843 "paddusb\t{%2, %0|%0, %2}"
21844 [(set_attr "type" "sseiadd")
21845 (set_attr "mode" "TI")])
21847 (define_insn "usaddv8hi3"
21848 [(set (match_operand:V8HI 0 "register_operand" "=x")
21849 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21850 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21852 "paddusw\t{%2, %0|%0, %2}"
21853 [(set_attr "type" "sseiadd")
21854 (set_attr "mode" "TI")])
21856 (define_insn "subv16qi3"
21857 [(set (match_operand:V16QI 0 "register_operand" "=x")
21858 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21859 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21861 "psubb\t{%2, %0|%0, %2}"
21862 [(set_attr "type" "sseiadd")
21863 (set_attr "mode" "TI")])
21865 (define_insn "subv8hi3"
21866 [(set (match_operand:V8HI 0 "register_operand" "=x")
21867 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21868 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21870 "psubw\t{%2, %0|%0, %2}"
21871 [(set_attr "type" "sseiadd")
21872 (set_attr "mode" "TI")])
21874 (define_insn "subv4si3"
21875 [(set (match_operand:V4SI 0 "register_operand" "=x")
21876 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
21877 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21879 "psubd\t{%2, %0|%0, %2}"
21880 [(set_attr "type" "sseiadd")
21881 (set_attr "mode" "TI")])
21883 (define_insn "subv2di3"
21884 [(set (match_operand:V2DI 0 "register_operand" "=x")
21885 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
21886 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21888 "psubq\t{%2, %0|%0, %2}"
21889 [(set_attr "type" "sseiadd")
21890 (set_attr "mode" "TI")])
21892 (define_insn "sssubv16qi3"
21893 [(set (match_operand:V16QI 0 "register_operand" "=x")
21894 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21895 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21897 "psubsb\t{%2, %0|%0, %2}"
21898 [(set_attr "type" "sseiadd")
21899 (set_attr "mode" "TI")])
21901 (define_insn "sssubv8hi3"
21902 [(set (match_operand:V8HI 0 "register_operand" "=x")
21903 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21904 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21906 "psubsw\t{%2, %0|%0, %2}"
21907 [(set_attr "type" "sseiadd")
21908 (set_attr "mode" "TI")])
21910 (define_insn "ussubv16qi3"
21911 [(set (match_operand:V16QI 0 "register_operand" "=x")
21912 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21913 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21915 "psubusb\t{%2, %0|%0, %2}"
21916 [(set_attr "type" "sseiadd")
21917 (set_attr "mode" "TI")])
21919 (define_insn "ussubv8hi3"
21920 [(set (match_operand:V8HI 0 "register_operand" "=x")
21921 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21922 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21924 "psubusw\t{%2, %0|%0, %2}"
21925 [(set_attr "type" "sseiadd")
21926 (set_attr "mode" "TI")])
21928 (define_insn "mulv8hi3"
21929 [(set (match_operand:V8HI 0 "register_operand" "=x")
21930 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
21931 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21933 "pmullw\t{%2, %0|%0, %2}"
21934 [(set_attr "type" "sseimul")
21935 (set_attr "mode" "TI")])
21937 (define_insn "smulv8hi3_highpart"
21938 [(set (match_operand:V8HI 0 "register_operand" "=x")
21941 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21942 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21945 "pmulhw\t{%2, %0|%0, %2}"
21946 [(set_attr "type" "sseimul")
21947 (set_attr "mode" "TI")])
21949 (define_insn "umulv8hi3_highpart"
21950 [(set (match_operand:V8HI 0 "register_operand" "=x")
21953 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21954 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21957 "pmulhuw\t{%2, %0|%0, %2}"
21958 [(set_attr "type" "sseimul")
21959 (set_attr "mode" "TI")])
21961 (define_insn "sse2_umulsidi3"
21962 [(set (match_operand:DI 0 "register_operand" "=y")
21963 (mult:DI (zero_extend:DI (vec_select:SI
21964 (match_operand:V2SI 1 "register_operand" "0")
21965 (parallel [(const_int 0)])))
21966 (zero_extend:DI (vec_select:SI
21967 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
21968 (parallel [(const_int 0)])))))]
21970 "pmuludq\t{%2, %0|%0, %2}"
21971 [(set_attr "type" "sseimul")
21972 (set_attr "mode" "TI")])
21974 (define_insn "sse2_umulv2siv2di3"
21975 [(set (match_operand:V2DI 0 "register_operand" "=x")
21976 (mult:V2DI (zero_extend:V2DI
21978 (match_operand:V4SI 1 "register_operand" "0")
21979 (parallel [(const_int 0) (const_int 2)])))
21982 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
21983 (parallel [(const_int 0) (const_int 2)])))))]
21985 "pmuludq\t{%2, %0|%0, %2}"
21986 [(set_attr "type" "sseimul")
21987 (set_attr "mode" "TI")])
21989 (define_insn "sse2_pmaddwd"
21990 [(set (match_operand:V4SI 0 "register_operand" "=x")
21993 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
21994 (parallel [(const_int 0)
21998 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
21999 (parallel [(const_int 0)
22004 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
22005 (parallel [(const_int 1)
22009 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
22010 (parallel [(const_int 1)
22013 (const_int 7)]))))))]
22015 "pmaddwd\t{%2, %0|%0, %2}"
22016 [(set_attr "type" "sseiadd")
22017 (set_attr "mode" "TI")])
22019 ;; Same as pxor, but don't show input operands so that we don't think
22021 (define_insn "sse2_clrti"
22022 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
22025 if (get_attr_mode (insn) == MODE_TI)
22026 return "pxor\t%0, %0";
22028 return "xorps\t%0, %0";
22030 [(set_attr "type" "ssemov")
22031 (set_attr "memory" "none")
22034 (ne (symbol_ref "optimize_size")
22036 (const_string "V4SF")
22037 (const_string "TI")))])
22039 ;; MMX unsigned averages/sum of absolute differences
22041 (define_insn "sse2_uavgv16qi3"
22042 [(set (match_operand:V16QI 0 "register_operand" "=x")
22044 (plus:V16QI (plus:V16QI
22045 (match_operand:V16QI 1 "register_operand" "0")
22046 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
22047 (const_vector:V16QI [(const_int 1) (const_int 1)
22048 (const_int 1) (const_int 1)
22049 (const_int 1) (const_int 1)
22050 (const_int 1) (const_int 1)
22051 (const_int 1) (const_int 1)
22052 (const_int 1) (const_int 1)
22053 (const_int 1) (const_int 1)
22054 (const_int 1) (const_int 1)]))
22057 "pavgb\t{%2, %0|%0, %2}"
22058 [(set_attr "type" "sseiadd")
22059 (set_attr "mode" "TI")])
22061 (define_insn "sse2_uavgv8hi3"
22062 [(set (match_operand:V8HI 0 "register_operand" "=x")
22064 (plus:V8HI (plus:V8HI
22065 (match_operand:V8HI 1 "register_operand" "0")
22066 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
22067 (const_vector:V8HI [(const_int 1) (const_int 1)
22068 (const_int 1) (const_int 1)
22069 (const_int 1) (const_int 1)
22070 (const_int 1) (const_int 1)]))
22073 "pavgw\t{%2, %0|%0, %2}"
22074 [(set_attr "type" "sseiadd")
22075 (set_attr "mode" "TI")])
22077 ;; @@@ this isn't the right representation.
22078 (define_insn "sse2_psadbw"
22079 [(set (match_operand:V2DI 0 "register_operand" "=x")
22080 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
22081 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
22084 "psadbw\t{%2, %0|%0, %2}"
22085 [(set_attr "type" "sseiadd")
22086 (set_attr "mode" "TI")])
22089 ;; MMX insert/extract/shuffle
22091 (define_insn "sse2_pinsrw"
22092 [(set (match_operand:V8HI 0 "register_operand" "=x")
22093 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
22094 (vec_duplicate:V8HI
22096 (match_operand:SI 2 "nonimmediate_operand" "rm")))
22097 (match_operand:SI 3 "const_0_to_255_operand" "N")))]
22099 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
22100 [(set_attr "type" "ssecvt")
22101 (set_attr "mode" "TI")])
22103 (define_insn "sse2_pextrw"
22104 [(set (match_operand:SI 0 "register_operand" "=r")
22106 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
22108 [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
22110 "pextrw\t{%2, %1, %0|%0, %1, %2}"
22111 [(set_attr "type" "ssecvt")
22112 (set_attr "mode" "TI")])
22114 (define_insn "sse2_pshufd"
22115 [(set (match_operand:V4SI 0 "register_operand" "=x")
22116 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
22117 (match_operand:SI 2 "immediate_operand" "i")]
22120 "pshufd\t{%2, %1, %0|%0, %1, %2}"
22121 [(set_attr "type" "ssecvt")
22122 (set_attr "mode" "TI")])
22124 (define_insn "sse2_pshuflw"
22125 [(set (match_operand:V8HI 0 "register_operand" "=x")
22126 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22127 (match_operand:SI 2 "immediate_operand" "i")]
22130 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
22131 [(set_attr "type" "ssecvt")
22132 (set_attr "mode" "TI")])
22134 (define_insn "sse2_pshufhw"
22135 [(set (match_operand:V8HI 0 "register_operand" "=x")
22136 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22137 (match_operand:SI 2 "immediate_operand" "i")]
22140 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
22141 [(set_attr "type" "ssecvt")
22142 (set_attr "mode" "TI")])
22144 ;; MMX mask-generating comparisons
22146 (define_insn "eqv16qi3"
22147 [(set (match_operand:V16QI 0 "register_operand" "=x")
22148 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
22149 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22151 "pcmpeqb\t{%2, %0|%0, %2}"
22152 [(set_attr "type" "ssecmp")
22153 (set_attr "mode" "TI")])
22155 (define_insn "eqv8hi3"
22156 [(set (match_operand:V8HI 0 "register_operand" "=x")
22157 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
22158 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22160 "pcmpeqw\t{%2, %0|%0, %2}"
22161 [(set_attr "type" "ssecmp")
22162 (set_attr "mode" "TI")])
22164 (define_insn "eqv4si3"
22165 [(set (match_operand:V4SI 0 "register_operand" "=x")
22166 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
22167 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22169 "pcmpeqd\t{%2, %0|%0, %2}"
22170 [(set_attr "type" "ssecmp")
22171 (set_attr "mode" "TI")])
22173 (define_insn "gtv16qi3"
22174 [(set (match_operand:V16QI 0 "register_operand" "=x")
22175 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
22176 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22178 "pcmpgtb\t{%2, %0|%0, %2}"
22179 [(set_attr "type" "ssecmp")
22180 (set_attr "mode" "TI")])
22182 (define_insn "gtv8hi3"
22183 [(set (match_operand:V8HI 0 "register_operand" "=x")
22184 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22185 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22187 "pcmpgtw\t{%2, %0|%0, %2}"
22188 [(set_attr "type" "ssecmp")
22189 (set_attr "mode" "TI")])
22191 (define_insn "gtv4si3"
22192 [(set (match_operand:V4SI 0 "register_operand" "=x")
22193 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22194 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22196 "pcmpgtd\t{%2, %0|%0, %2}"
22197 [(set_attr "type" "ssecmp")
22198 (set_attr "mode" "TI")])
22201 ;; MMX max/min insns
22203 (define_insn "umaxv16qi3"
22204 [(set (match_operand:V16QI 0 "register_operand" "=x")
22205 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22206 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22208 "pmaxub\t{%2, %0|%0, %2}"
22209 [(set_attr "type" "sseiadd")
22210 (set_attr "mode" "TI")])
22212 (define_insn "smaxv8hi3"
22213 [(set (match_operand:V8HI 0 "register_operand" "=x")
22214 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22215 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22217 "pmaxsw\t{%2, %0|%0, %2}"
22218 [(set_attr "type" "sseiadd")
22219 (set_attr "mode" "TI")])
22221 (define_insn "uminv16qi3"
22222 [(set (match_operand:V16QI 0 "register_operand" "=x")
22223 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22224 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22226 "pminub\t{%2, %0|%0, %2}"
22227 [(set_attr "type" "sseiadd")
22228 (set_attr "mode" "TI")])
22230 (define_insn "sminv8hi3"
22231 [(set (match_operand:V8HI 0 "register_operand" "=x")
22232 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22233 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22235 "pminsw\t{%2, %0|%0, %2}"
22236 [(set_attr "type" "sseiadd")
22237 (set_attr "mode" "TI")])
22242 (define_insn "ashrv8hi3"
22243 [(set (match_operand:V8HI 0 "register_operand" "=x")
22244 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22245 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22247 "psraw\t{%2, %0|%0, %2}"
22248 [(set_attr "type" "sseishft")
22249 (set_attr "mode" "TI")])
22251 (define_insn "ashrv4si3"
22252 [(set (match_operand:V4SI 0 "register_operand" "=x")
22253 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22254 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22256 "psrad\t{%2, %0|%0, %2}"
22257 [(set_attr "type" "sseishft")
22258 (set_attr "mode" "TI")])
22260 (define_insn "lshrv8hi3"
22261 [(set (match_operand:V8HI 0 "register_operand" "=x")
22262 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22263 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22265 "psrlw\t{%2, %0|%0, %2}"
22266 [(set_attr "type" "sseishft")
22267 (set_attr "mode" "TI")])
22269 (define_insn "lshrv4si3"
22270 [(set (match_operand:V4SI 0 "register_operand" "=x")
22271 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22272 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22274 "psrld\t{%2, %0|%0, %2}"
22275 [(set_attr "type" "sseishft")
22276 (set_attr "mode" "TI")])
22278 (define_insn "lshrv2di3"
22279 [(set (match_operand:V2DI 0 "register_operand" "=x")
22280 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22281 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22283 "psrlq\t{%2, %0|%0, %2}"
22284 [(set_attr "type" "sseishft")
22285 (set_attr "mode" "TI")])
22287 (define_insn "ashlv8hi3"
22288 [(set (match_operand:V8HI 0 "register_operand" "=x")
22289 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22290 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22292 "psllw\t{%2, %0|%0, %2}"
22293 [(set_attr "type" "sseishft")
22294 (set_attr "mode" "TI")])
22296 (define_insn "ashlv4si3"
22297 [(set (match_operand:V4SI 0 "register_operand" "=x")
22298 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22299 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22301 "pslld\t{%2, %0|%0, %2}"
22302 [(set_attr "type" "sseishft")
22303 (set_attr "mode" "TI")])
22305 (define_insn "ashlv2di3"
22306 [(set (match_operand:V2DI 0 "register_operand" "=x")
22307 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22308 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22310 "psllq\t{%2, %0|%0, %2}"
22311 [(set_attr "type" "sseishft")
22312 (set_attr "mode" "TI")])
22314 (define_insn "ashrv8hi3_ti"
22315 [(set (match_operand:V8HI 0 "register_operand" "=x")
22316 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22317 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22319 "psraw\t{%2, %0|%0, %2}"
22320 [(set_attr "type" "sseishft")
22321 (set_attr "mode" "TI")])
22323 (define_insn "ashrv4si3_ti"
22324 [(set (match_operand:V4SI 0 "register_operand" "=x")
22325 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22326 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22328 "psrad\t{%2, %0|%0, %2}"
22329 [(set_attr "type" "sseishft")
22330 (set_attr "mode" "TI")])
22332 (define_insn "lshrv8hi3_ti"
22333 [(set (match_operand:V8HI 0 "register_operand" "=x")
22334 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22335 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22337 "psrlw\t{%2, %0|%0, %2}"
22338 [(set_attr "type" "sseishft")
22339 (set_attr "mode" "TI")])
22341 (define_insn "lshrv4si3_ti"
22342 [(set (match_operand:V4SI 0 "register_operand" "=x")
22343 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22344 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22346 "psrld\t{%2, %0|%0, %2}"
22347 [(set_attr "type" "sseishft")
22348 (set_attr "mode" "TI")])
22350 (define_insn "lshrv2di3_ti"
22351 [(set (match_operand:V2DI 0 "register_operand" "=x")
22352 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22353 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22355 "psrlq\t{%2, %0|%0, %2}"
22356 [(set_attr "type" "sseishft")
22357 (set_attr "mode" "TI")])
22359 (define_insn "ashlv8hi3_ti"
22360 [(set (match_operand:V8HI 0 "register_operand" "=x")
22361 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22362 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22364 "psllw\t{%2, %0|%0, %2}"
22365 [(set_attr "type" "sseishft")
22366 (set_attr "mode" "TI")])
22368 (define_insn "ashlv4si3_ti"
22369 [(set (match_operand:V4SI 0 "register_operand" "=x")
22370 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22371 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22373 "pslld\t{%2, %0|%0, %2}"
22374 [(set_attr "type" "sseishft")
22375 (set_attr "mode" "TI")])
22377 (define_insn "ashlv2di3_ti"
22378 [(set (match_operand:V2DI 0 "register_operand" "=x")
22379 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22380 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22382 "psllq\t{%2, %0|%0, %2}"
22383 [(set_attr "type" "sseishft")
22384 (set_attr "mode" "TI")])
22386 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
22387 ;; we wouldn't need here it since we never generate TImode arithmetic.
22389 ;; There has to be some kind of prize for the weirdest new instruction...
22390 (define_insn "sse2_ashlti3"
22391 [(set (match_operand:TI 0 "register_operand" "=x")
22393 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
22394 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22395 (const_int 8)))] UNSPEC_NOP))]
22397 "pslldq\t{%2, %0|%0, %2}"
22398 [(set_attr "type" "sseishft")
22399 (set_attr "mode" "TI")])
22401 (define_insn "sse2_lshrti3"
22402 [(set (match_operand:TI 0 "register_operand" "=x")
22404 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
22405 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22406 (const_int 8)))] UNSPEC_NOP))]
22408 "psrldq\t{%2, %0|%0, %2}"
22409 [(set_attr "type" "sseishft")
22410 (set_attr "mode" "TI")])
22414 (define_insn "sse2_unpckhpd"
22415 [(set (match_operand:V2DF 0 "register_operand" "=x")
22417 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22418 (parallel [(const_int 1)]))
22419 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22420 (parallel [(const_int 1)]))))]
22422 "unpckhpd\t{%2, %0|%0, %2}"
22423 [(set_attr "type" "ssecvt")
22424 (set_attr "mode" "V2DF")])
22426 (define_insn "sse2_unpcklpd"
22427 [(set (match_operand:V2DF 0 "register_operand" "=x")
22429 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22430 (parallel [(const_int 0)]))
22431 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22432 (parallel [(const_int 0)]))))]
22434 "unpcklpd\t{%2, %0|%0, %2}"
22435 [(set_attr "type" "ssecvt")
22436 (set_attr "mode" "V2DF")])
22438 ;; MMX pack/unpack insns.
22440 (define_insn "sse2_packsswb"
22441 [(set (match_operand:V16QI 0 "register_operand" "=x")
22443 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22444 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22446 "packsswb\t{%2, %0|%0, %2}"
22447 [(set_attr "type" "ssecvt")
22448 (set_attr "mode" "TI")])
22450 (define_insn "sse2_packssdw"
22451 [(set (match_operand:V8HI 0 "register_operand" "=x")
22453 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
22454 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
22456 "packssdw\t{%2, %0|%0, %2}"
22457 [(set_attr "type" "ssecvt")
22458 (set_attr "mode" "TI")])
22460 (define_insn "sse2_packuswb"
22461 [(set (match_operand:V16QI 0 "register_operand" "=x")
22463 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22464 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22466 "packuswb\t{%2, %0|%0, %2}"
22467 [(set_attr "type" "ssecvt")
22468 (set_attr "mode" "TI")])
22470 (define_insn "sse2_punpckhbw"
22471 [(set (match_operand:V16QI 0 "register_operand" "=x")
22473 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22474 (parallel [(const_int 8) (const_int 0)
22475 (const_int 9) (const_int 1)
22476 (const_int 10) (const_int 2)
22477 (const_int 11) (const_int 3)
22478 (const_int 12) (const_int 4)
22479 (const_int 13) (const_int 5)
22480 (const_int 14) (const_int 6)
22481 (const_int 15) (const_int 7)]))
22482 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22483 (parallel [(const_int 0) (const_int 8)
22484 (const_int 1) (const_int 9)
22485 (const_int 2) (const_int 10)
22486 (const_int 3) (const_int 11)
22487 (const_int 4) (const_int 12)
22488 (const_int 5) (const_int 13)
22489 (const_int 6) (const_int 14)
22490 (const_int 7) (const_int 15)]))
22491 (const_int 21845)))]
22493 "punpckhbw\t{%2, %0|%0, %2}"
22494 [(set_attr "type" "ssecvt")
22495 (set_attr "mode" "TI")])
22497 (define_insn "sse2_punpckhwd"
22498 [(set (match_operand:V8HI 0 "register_operand" "=x")
22500 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22501 (parallel [(const_int 4) (const_int 0)
22502 (const_int 5) (const_int 1)
22503 (const_int 6) (const_int 2)
22504 (const_int 7) (const_int 3)]))
22505 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22506 (parallel [(const_int 0) (const_int 4)
22507 (const_int 1) (const_int 5)
22508 (const_int 2) (const_int 6)
22509 (const_int 3) (const_int 7)]))
22512 "punpckhwd\t{%2, %0|%0, %2}"
22513 [(set_attr "type" "ssecvt")
22514 (set_attr "mode" "TI")])
22516 (define_insn "sse2_punpckhdq"
22517 [(set (match_operand:V4SI 0 "register_operand" "=x")
22519 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22520 (parallel [(const_int 2) (const_int 0)
22521 (const_int 3) (const_int 1)]))
22522 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22523 (parallel [(const_int 0) (const_int 2)
22524 (const_int 1) (const_int 3)]))
22527 "punpckhdq\t{%2, %0|%0, %2}"
22528 [(set_attr "type" "ssecvt")
22529 (set_attr "mode" "TI")])
22531 (define_insn "sse2_punpcklbw"
22532 [(set (match_operand:V16QI 0 "register_operand" "=x")
22534 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22535 (parallel [(const_int 0) (const_int 8)
22536 (const_int 1) (const_int 9)
22537 (const_int 2) (const_int 10)
22538 (const_int 3) (const_int 11)
22539 (const_int 4) (const_int 12)
22540 (const_int 5) (const_int 13)
22541 (const_int 6) (const_int 14)
22542 (const_int 7) (const_int 15)]))
22543 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22544 (parallel [(const_int 8) (const_int 0)
22545 (const_int 9) (const_int 1)
22546 (const_int 10) (const_int 2)
22547 (const_int 11) (const_int 3)
22548 (const_int 12) (const_int 4)
22549 (const_int 13) (const_int 5)
22550 (const_int 14) (const_int 6)
22551 (const_int 15) (const_int 7)]))
22552 (const_int 21845)))]
22554 "punpcklbw\t{%2, %0|%0, %2}"
22555 [(set_attr "type" "ssecvt")
22556 (set_attr "mode" "TI")])
22558 (define_insn "sse2_punpcklwd"
22559 [(set (match_operand:V8HI 0 "register_operand" "=x")
22561 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22562 (parallel [(const_int 0) (const_int 4)
22563 (const_int 1) (const_int 5)
22564 (const_int 2) (const_int 6)
22565 (const_int 3) (const_int 7)]))
22566 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22567 (parallel [(const_int 4) (const_int 0)
22568 (const_int 5) (const_int 1)
22569 (const_int 6) (const_int 2)
22570 (const_int 7) (const_int 3)]))
22573 "punpcklwd\t{%2, %0|%0, %2}"
22574 [(set_attr "type" "ssecvt")
22575 (set_attr "mode" "TI")])
22577 (define_insn "sse2_punpckldq"
22578 [(set (match_operand:V4SI 0 "register_operand" "=x")
22580 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22581 (parallel [(const_int 0) (const_int 2)
22582 (const_int 1) (const_int 3)]))
22583 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22584 (parallel [(const_int 2) (const_int 0)
22585 (const_int 3) (const_int 1)]))
22588 "punpckldq\t{%2, %0|%0, %2}"
22589 [(set_attr "type" "ssecvt")
22590 (set_attr "mode" "TI")])
22592 (define_insn "sse2_punpcklqdq"
22593 [(set (match_operand:V2DI 0 "register_operand" "=x")
22595 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22596 (parallel [(const_int 1)
22598 (match_operand:V2DI 1 "register_operand" "0")
22601 "punpcklqdq\t{%2, %0|%0, %2}"
22602 [(set_attr "type" "ssecvt")
22603 (set_attr "mode" "TI")])
22605 (define_insn "sse2_punpckhqdq"
22606 [(set (match_operand:V2DI 0 "register_operand" "=x")
22608 (match_operand:V2DI 1 "register_operand" "0")
22609 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22610 (parallel [(const_int 1)
22614 "punpckhqdq\t{%2, %0|%0, %2}"
22615 [(set_attr "type" "ssecvt")
22616 (set_attr "mode" "TI")])
22620 (define_insn "sse2_movapd"
22621 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22622 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22625 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22626 "movapd\t{%1, %0|%0, %1}"
22627 [(set_attr "type" "ssemov")
22628 (set_attr "mode" "V2DF")])
22630 (define_insn "sse2_movupd"
22631 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22632 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22635 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22636 "movupd\t{%1, %0|%0, %1}"
22637 [(set_attr "type" "ssecvt")
22638 (set_attr "mode" "V2DF")])
22640 (define_insn "sse2_movdqa"
22641 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22642 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22645 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22646 "movdqa\t{%1, %0|%0, %1}"
22647 [(set_attr "type" "ssemov")
22648 (set_attr "mode" "TI")])
22650 (define_insn "sse2_movdqu"
22651 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22652 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22655 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22656 "movdqu\t{%1, %0|%0, %1}"
22657 [(set_attr "type" "ssecvt")
22658 (set_attr "mode" "TI")])
22660 (define_insn "sse2_movdq2q"
22661 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
22662 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
22663 (parallel [(const_int 0)])))]
22664 "TARGET_SSE2 && !TARGET_64BIT"
22666 movq\t{%1, %0|%0, %1}
22667 movdq2q\t{%1, %0|%0, %1}"
22668 [(set_attr "type" "ssecvt")
22669 (set_attr "mode" "TI")])
22671 (define_insn "sse2_movdq2q_rex64"
22672 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
22673 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
22674 (parallel [(const_int 0)])))]
22675 "TARGET_SSE2 && TARGET_64BIT"
22677 movq\t{%1, %0|%0, %1}
22678 movdq2q\t{%1, %0|%0, %1}
22679 movd\t{%1, %0|%0, %1}"
22680 [(set_attr "type" "ssecvt")
22681 (set_attr "mode" "TI")])
22683 (define_insn "sse2_movq2dq"
22684 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
22685 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
22687 "TARGET_SSE2 && !TARGET_64BIT"
22689 movq\t{%1, %0|%0, %1}
22690 movq2dq\t{%1, %0|%0, %1}"
22691 [(set_attr "type" "ssecvt,ssemov")
22692 (set_attr "mode" "TI")])
22694 (define_insn "sse2_movq2dq_rex64"
22695 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
22696 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
22698 "TARGET_SSE2 && TARGET_64BIT"
22700 movq\t{%1, %0|%0, %1}
22701 movq2dq\t{%1, %0|%0, %1}
22702 movd\t{%1, %0|%0, %1}"
22703 [(set_attr "type" "ssecvt,ssemov,ssecvt")
22704 (set_attr "mode" "TI")])
22706 (define_insn "sse2_movq"
22707 [(set (match_operand:V2DI 0 "register_operand" "=x")
22708 (vec_concat:V2DI (vec_select:DI
22709 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
22710 (parallel [(const_int 0)]))
22713 "movq\t{%1, %0|%0, %1}"
22714 [(set_attr "type" "ssemov")
22715 (set_attr "mode" "TI")])
22717 (define_insn "sse2_loadd"
22718 [(set (match_operand:V4SI 0 "register_operand" "=x")
22720 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
22721 (const_vector:V4SI [(const_int 0)
22727 "movd\t{%1, %0|%0, %1}"
22728 [(set_attr "type" "ssemov")
22729 (set_attr "mode" "TI")])
22731 (define_insn "sse2_stored"
22732 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
22734 (match_operand:V4SI 1 "register_operand" "x")
22735 (parallel [(const_int 0)])))]
22737 "movd\t{%1, %0|%0, %1}"
22738 [(set_attr "type" "ssemov")
22739 (set_attr "mode" "TI")])
22741 (define_insn "sse2_movhpd"
22742 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22744 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
22745 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
22747 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
22748 "movhpd\t{%2, %0|%0, %2}"
22749 [(set_attr "type" "ssecvt")
22750 (set_attr "mode" "V2DF")])
22752 (define_expand "sse2_loadsd"
22753 [(match_operand:V2DF 0 "register_operand" "")
22754 (match_operand:DF 1 "memory_operand" "")]
22757 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
22758 CONST0_RTX (V2DFmode)));
22762 (define_insn "sse2_loadsd_1"
22763 [(set (match_operand:V2DF 0 "register_operand" "=x")
22765 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
22766 (match_operand:V2DF 2 "const0_operand" "X")
22769 "movsd\t{%1, %0|%0, %1}"
22770 [(set_attr "type" "ssecvt")
22771 (set_attr "mode" "DF")])
22773 (define_insn "sse2_movsd"
22774 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
22776 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
22777 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,x")
22779 "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
22780 "@movsd\t{%2, %0|%0, %2}
22781 movlpd\t{%2, %0|%0, %2}
22782 movlpd\t{%2, %0|%0, %2}"
22783 [(set_attr "type" "ssecvt")
22784 (set_attr "mode" "DF,V2DF,V2DF")])
22786 (define_insn "sse2_storesd"
22787 [(set (match_operand:DF 0 "memory_operand" "=m")
22789 (match_operand:V2DF 1 "register_operand" "x")
22790 (parallel [(const_int 0)])))]
22792 "movsd\t{%1, %0|%0, %1}"
22793 [(set_attr "type" "ssecvt")
22794 (set_attr "mode" "DF")])
22796 (define_insn "sse2_shufpd"
22797 [(set (match_operand:V2DF 0 "register_operand" "=x")
22798 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22799 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
22800 (match_operand:SI 3 "immediate_operand" "i")]
22803 ;; @@@ check operand order for intel/nonintel syntax
22804 "shufpd\t{%3, %2, %0|%0, %2, %3}"
22805 [(set_attr "type" "ssecvt")
22806 (set_attr "mode" "V2DF")])
22808 (define_insn "sse2_clflush"
22809 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
22813 [(set_attr "type" "sse")
22814 (set_attr "memory" "unknown")])
22816 (define_expand "sse2_mfence"
22817 [(set (match_dup 0)
22818 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22821 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22822 MEM_VOLATILE_P (operands[0]) = 1;
22825 (define_insn "*mfence_insn"
22826 [(set (match_operand:BLK 0 "" "")
22827 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22830 [(set_attr "type" "sse")
22831 (set_attr "memory" "unknown")])
22833 (define_expand "sse2_lfence"
22834 [(set (match_dup 0)
22835 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22838 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22839 MEM_VOLATILE_P (operands[0]) = 1;
22842 (define_insn "*lfence_insn"
22843 [(set (match_operand:BLK 0 "" "")
22844 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22847 [(set_attr "type" "sse")
22848 (set_attr "memory" "unknown")])
22852 (define_insn "mwait"
22853 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
22854 (match_operand:SI 1 "register_operand" "c")]
22858 [(set_attr "length" "3")])
22860 (define_insn "monitor"
22861 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
22862 (match_operand:SI 1 "register_operand" "c")
22863 (match_operand:SI 2 "register_operand" "d")]
22866 "monitor\t%0, %1, %2"
22867 [(set_attr "length" "3")])
22871 (define_insn "addsubv4sf3"
22872 [(set (match_operand:V4SF 0 "register_operand" "=x")
22873 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
22874 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
22877 "addsubps\t{%2, %0|%0, %2}"
22878 [(set_attr "type" "sseadd")
22879 (set_attr "mode" "V4SF")])
22881 (define_insn "addsubv2df3"
22882 [(set (match_operand:V2DF 0 "register_operand" "=x")
22883 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22884 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
22887 "addsubpd\t{%2, %0|%0, %2}"
22888 [(set_attr "type" "sseadd")
22889 (set_attr "mode" "V2DF")])
22891 (define_insn "haddv4sf3"
22892 [(set (match_operand:V4SF 0 "register_operand" "=x")
22893 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
22894 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
22897 "haddps\t{%2, %0|%0, %2}"
22898 [(set_attr "type" "sseadd")
22899 (set_attr "mode" "V4SF")])
22901 (define_insn "haddv2df3"
22902 [(set (match_operand:V2DF 0 "register_operand" "=x")
22903 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22904 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
22907 "haddpd\t{%2, %0|%0, %2}"
22908 [(set_attr "type" "sseadd")
22909 (set_attr "mode" "V2DF")])
22911 (define_insn "hsubv4sf3"
22912 [(set (match_operand:V4SF 0 "register_operand" "=x")
22913 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
22914 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
22917 "hsubps\t{%2, %0|%0, %2}"
22918 [(set_attr "type" "sseadd")
22919 (set_attr "mode" "V4SF")])
22921 (define_insn "hsubv2df3"
22922 [(set (match_operand:V2DF 0 "register_operand" "=x")
22923 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22924 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
22927 "hsubpd\t{%2, %0|%0, %2}"
22928 [(set_attr "type" "sseadd")
22929 (set_attr "mode" "V2DF")])
22931 (define_insn "movshdup"
22932 [(set (match_operand:V4SF 0 "register_operand" "=x")
22934 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
22936 "movshdup\t{%1, %0|%0, %1}"
22937 [(set_attr "type" "sse")
22938 (set_attr "mode" "V4SF")])
22940 (define_insn "movsldup"
22941 [(set (match_operand:V4SF 0 "register_operand" "=x")
22943 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
22945 "movsldup\t{%1, %0|%0, %1}"
22946 [(set_attr "type" "sse")
22947 (set_attr "mode" "V4SF")])
22949 (define_insn "lddqu"
22950 [(set (match_operand:V16QI 0 "register_operand" "=x")
22951 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
22954 "lddqu\t{%1, %0|%0, %1}"
22955 [(set_attr "type" "ssecvt")
22956 (set_attr "mode" "TI")])
22958 (define_insn "loadddup"
22959 [(set (match_operand:V2DF 0 "register_operand" "=x")
22960 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
22962 "movddup\t{%1, %0|%0, %1}"
22963 [(set_attr "type" "ssecvt")
22964 (set_attr "mode" "DF")])
22966 (define_insn "movddup"
22967 [(set (match_operand:V2DF 0 "register_operand" "=x")
22968 (vec_duplicate:V2DF
22969 (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
22970 (parallel [(const_int 0)]))))]
22972 "movddup\t{%1, %0|%0, %1}"
22973 [(set_attr "type" "ssecvt")
22974 (set_attr "mode" "DF")])