1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
31 ;; updates for most instructions.
33 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
34 ;; constraint letters.
36 ;; The special asm out single letter directives following a '%' are:
37 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
39 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
40 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
41 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
42 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
43 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
44 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
45 ;; 'J' Print the appropriate jump operand.
47 ;; 'b' Print the QImode name of the register for the indicated operand.
48 ;; %b0 would print %al if operands[0] is reg 0.
49 ;; 'w' Likewise, print the HImode name of the register.
50 ;; 'k' Likewise, print the SImode name of the register.
51 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
52 ;; 'y' Print "st(0)" instead of "st" as a register.
57 [; Relocation specifiers
69 (UNSPEC_STACK_PROBE 10)
70 (UNSPEC_STACK_ALLOC 11)
72 (UNSPEC_SSE_PROLOGUE_SAVE 13)
77 (UNSPEC_TLS_LD_BASE 17)
79 ; Other random patterns
89 ; For SSE/MMX support:
100 (UNSPEC_NOP 45) ; prevents combiner cleverness
122 [(UNSPECV_BLOCKAGE 0)
123 (UNSPECV_EH_RETURN 13)
132 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
135 ;; In C guard expressions, put expressions which may be compile-time
136 ;; constants first. This allows for better optimization. For
137 ;; example, write "TARGET_64BIT && reload_completed", not
138 ;; "reload_completed && TARGET_64BIT".
141 ;; Processor type. This attribute must exactly match the processor_type
142 ;; enumeration in i386.h.
143 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
144 (const (symbol_ref "ix86_tune")))
146 ;; A basic instruction type. Refinements due to arguments to be
147 ;; provided in other attributes.
150 alu,alu1,negnot,imov,imovx,lea,
151 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
152 icmp,test,ibr,setcc,icmov,
153 push,pop,call,callv,leave,
155 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
156 sselog,sseiadd,sseishft,sseimul,
157 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
158 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
159 (const_string "other"))
161 ;; Main data type used by the insn
163 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
164 (const_string "unknown"))
166 ;; The CPU unit operations uses.
167 (define_attr "unit" "integer,i387,sse,mmx,unknown"
168 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
169 (const_string "i387")
170 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
171 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
173 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
175 (eq_attr "type" "other")
176 (const_string "unknown")]
177 (const_string "integer")))
179 ;; The (bounding maximum) length of an instruction immediate.
180 (define_attr "length_immediate" ""
181 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
183 (eq_attr "unit" "i387,sse,mmx")
185 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
187 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
188 (eq_attr "type" "imov,test")
189 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
190 (eq_attr "type" "call")
191 (if_then_else (match_operand 0 "constant_call_address_operand" "")
194 (eq_attr "type" "callv")
195 (if_then_else (match_operand 1 "constant_call_address_operand" "")
198 ;; We don't know the size before shorten_branches. Expect
199 ;; the instruction to fit for better scheduling.
200 (eq_attr "type" "ibr")
203 (symbol_ref "/* Update immediate_length and other attributes! */
206 ;; The (bounding maximum) length of an instruction address.
207 (define_attr "length_address" ""
208 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
210 (and (eq_attr "type" "call")
211 (match_operand 0 "constant_call_address_operand" ""))
213 (and (eq_attr "type" "callv")
214 (match_operand 1 "constant_call_address_operand" ""))
217 (symbol_ref "ix86_attr_length_address_default (insn)")))
219 ;; Set when length prefix is used.
220 (define_attr "prefix_data16" ""
221 (if_then_else (ior (eq_attr "mode" "HI")
222 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
226 ;; Set when string REP prefix is used.
227 (define_attr "prefix_rep" ""
228 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
232 ;; Set when 0f opcode prefix is used.
233 (define_attr "prefix_0f" ""
235 (ior (eq_attr "type" "imovx,setcc,icmov")
236 (eq_attr "unit" "sse,mmx"))
240 ;; Set when 0f opcode prefix is used.
241 (define_attr "prefix_rex" ""
242 (cond [(and (eq_attr "mode" "DI")
243 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
245 (and (eq_attr "mode" "QI")
246 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
249 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
255 ;; Set when modrm byte is used.
256 (define_attr "modrm" ""
257 (cond [(eq_attr "type" "str,cld,leave")
259 (eq_attr "unit" "i387")
261 (and (eq_attr "type" "incdec")
262 (ior (match_operand:SI 1 "register_operand" "")
263 (match_operand:HI 1 "register_operand" "")))
265 (and (eq_attr "type" "push")
266 (not (match_operand 1 "memory_operand" "")))
268 (and (eq_attr "type" "pop")
269 (not (match_operand 0 "memory_operand" "")))
271 (and (eq_attr "type" "imov")
272 (and (match_operand 0 "register_operand" "")
273 (match_operand 1 "immediate_operand" "")))
275 (and (eq_attr "type" "call")
276 (match_operand 0 "constant_call_address_operand" ""))
278 (and (eq_attr "type" "callv")
279 (match_operand 1 "constant_call_address_operand" ""))
284 ;; The (bounding maximum) length of an instruction in bytes.
285 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
286 ;; to split it and compute proper length as for other insns.
287 (define_attr "length" ""
288 (cond [(eq_attr "type" "other,multi,fistp")
290 (eq_attr "type" "fcmp")
292 (eq_attr "unit" "i387")
294 (plus (attr "prefix_data16")
295 (attr "length_address")))]
296 (plus (plus (attr "modrm")
297 (plus (attr "prefix_0f")
298 (plus (attr "prefix_rex")
300 (plus (attr "prefix_rep")
301 (plus (attr "prefix_data16")
302 (plus (attr "length_immediate")
303 (attr "length_address")))))))
305 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
306 ;; `store' if there is a simple memory reference therein, or `unknown'
307 ;; if the instruction is complex.
309 (define_attr "memory" "none,load,store,both,unknown"
310 (cond [(eq_attr "type" "other,multi,str")
311 (const_string "unknown")
312 (eq_attr "type" "lea,fcmov,fpspc,cld")
313 (const_string "none")
314 (eq_attr "type" "fistp,leave")
315 (const_string "both")
316 (eq_attr "type" "push")
317 (if_then_else (match_operand 1 "memory_operand" "")
318 (const_string "both")
319 (const_string "store"))
320 (eq_attr "type" "pop")
321 (if_then_else (match_operand 0 "memory_operand" "")
322 (const_string "both")
323 (const_string "load"))
324 (eq_attr "type" "setcc")
325 (if_then_else (match_operand 0 "memory_operand" "")
326 (const_string "store")
327 (const_string "none"))
328 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
329 (if_then_else (ior (match_operand 0 "memory_operand" "")
330 (match_operand 1 "memory_operand" ""))
331 (const_string "load")
332 (const_string "none"))
333 (eq_attr "type" "ibr")
334 (if_then_else (match_operand 0 "memory_operand" "")
335 (const_string "load")
336 (const_string "none"))
337 (eq_attr "type" "call")
338 (if_then_else (match_operand 0 "constant_call_address_operand" "")
339 (const_string "none")
340 (const_string "load"))
341 (eq_attr "type" "callv")
342 (if_then_else (match_operand 1 "constant_call_address_operand" "")
343 (const_string "none")
344 (const_string "load"))
345 (and (eq_attr "type" "alu1,negnot")
346 (match_operand 1 "memory_operand" ""))
347 (const_string "both")
348 (and (match_operand 0 "memory_operand" "")
349 (match_operand 1 "memory_operand" ""))
350 (const_string "both")
351 (match_operand 0 "memory_operand" "")
352 (const_string "store")
353 (match_operand 1 "memory_operand" "")
354 (const_string "load")
357 imov,imovx,icmp,test,
359 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
360 mmx,mmxmov,mmxcmp,mmxcvt")
361 (match_operand 2 "memory_operand" ""))
362 (const_string "load")
363 (and (eq_attr "type" "icmov")
364 (match_operand 3 "memory_operand" ""))
365 (const_string "load")
367 (const_string "none")))
369 ;; Indicates if an instruction has both an immediate and a displacement.
371 (define_attr "imm_disp" "false,true,unknown"
372 (cond [(eq_attr "type" "other,multi")
373 (const_string "unknown")
374 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
375 (and (match_operand 0 "memory_displacement_operand" "")
376 (match_operand 1 "immediate_operand" "")))
377 (const_string "true")
378 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
379 (and (match_operand 0 "memory_displacement_operand" "")
380 (match_operand 2 "immediate_operand" "")))
381 (const_string "true")
383 (const_string "false")))
385 ;; Indicates if an FP operation has an integer source.
387 (define_attr "fp_int_src" "false,true"
388 (const_string "false"))
390 ;; Describe a user's asm statement.
391 (define_asm_attributes
392 [(set_attr "length" "128")
393 (set_attr "type" "multi")])
395 (include "pentium.md")
398 (include "athlon.md")
400 ;; Compare instructions.
402 ;; All compare insns have expanders that save the operands away without
403 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
404 ;; after the cmp) will actually emit the cmpM.
406 (define_expand "cmpdi"
408 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
409 (match_operand:DI 1 "x86_64_general_operand" "")))]
412 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
413 operands[0] = force_reg (DImode, operands[0]);
414 ix86_compare_op0 = operands[0];
415 ix86_compare_op1 = operands[1];
419 (define_expand "cmpsi"
421 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
422 (match_operand:SI 1 "general_operand" "")))]
425 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
426 operands[0] = force_reg (SImode, operands[0]);
427 ix86_compare_op0 = operands[0];
428 ix86_compare_op1 = operands[1];
432 (define_expand "cmphi"
434 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
435 (match_operand:HI 1 "general_operand" "")))]
438 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
439 operands[0] = force_reg (HImode, operands[0]);
440 ix86_compare_op0 = operands[0];
441 ix86_compare_op1 = operands[1];
445 (define_expand "cmpqi"
447 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
448 (match_operand:QI 1 "general_operand" "")))]
451 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
452 operands[0] = force_reg (QImode, operands[0]);
453 ix86_compare_op0 = operands[0];
454 ix86_compare_op1 = operands[1];
458 (define_insn "cmpdi_ccno_1_rex64"
460 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
461 (match_operand:DI 1 "const0_operand" "n,n")))]
462 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
464 test{q}\t{%0, %0|%0, %0}
465 cmp{q}\t{%1, %0|%0, %1}"
466 [(set_attr "type" "test,icmp")
467 (set_attr "length_immediate" "0,1")
468 (set_attr "mode" "DI")])
470 (define_insn "*cmpdi_minus_1_rex64"
472 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
473 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
475 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
476 "cmp{q}\t{%1, %0|%0, %1}"
477 [(set_attr "type" "icmp")
478 (set_attr "mode" "DI")])
480 (define_expand "cmpdi_1_rex64"
482 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
483 (match_operand:DI 1 "general_operand" "")))]
487 (define_insn "cmpdi_1_insn_rex64"
489 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
490 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
491 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
492 "cmp{q}\t{%1, %0|%0, %1}"
493 [(set_attr "type" "icmp")
494 (set_attr "mode" "DI")])
497 (define_insn "*cmpsi_ccno_1"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
500 (match_operand:SI 1 "const0_operand" "n,n")))]
501 "ix86_match_ccmode (insn, CCNOmode)"
503 test{l}\t{%0, %0|%0, %0}
504 cmp{l}\t{%1, %0|%0, %1}"
505 [(set_attr "type" "test,icmp")
506 (set_attr "length_immediate" "0,1")
507 (set_attr "mode" "SI")])
509 (define_insn "*cmpsi_minus_1"
511 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
512 (match_operand:SI 1 "general_operand" "ri,mr"))
514 "ix86_match_ccmode (insn, CCGOCmode)"
515 "cmp{l}\t{%1, %0|%0, %1}"
516 [(set_attr "type" "icmp")
517 (set_attr "mode" "SI")])
519 (define_expand "cmpsi_1"
521 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
522 (match_operand:SI 1 "general_operand" "ri,mr")))]
526 (define_insn "*cmpsi_1_insn"
528 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
529 (match_operand:SI 1 "general_operand" "ri,mr")))]
530 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
531 && ix86_match_ccmode (insn, CCmode)"
532 "cmp{l}\t{%1, %0|%0, %1}"
533 [(set_attr "type" "icmp")
534 (set_attr "mode" "SI")])
536 (define_insn "*cmphi_ccno_1"
538 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
539 (match_operand:HI 1 "const0_operand" "n,n")))]
540 "ix86_match_ccmode (insn, CCNOmode)"
542 test{w}\t{%0, %0|%0, %0}
543 cmp{w}\t{%1, %0|%0, %1}"
544 [(set_attr "type" "test,icmp")
545 (set_attr "length_immediate" "0,1")
546 (set_attr "mode" "HI")])
548 (define_insn "*cmphi_minus_1"
550 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
551 (match_operand:HI 1 "general_operand" "ri,mr"))
553 "ix86_match_ccmode (insn, CCGOCmode)"
554 "cmp{w}\t{%1, %0|%0, %1}"
555 [(set_attr "type" "icmp")
556 (set_attr "mode" "HI")])
558 (define_insn "*cmphi_1"
560 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
561 (match_operand:HI 1 "general_operand" "ri,mr")))]
562 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
563 && ix86_match_ccmode (insn, CCmode)"
564 "cmp{w}\t{%1, %0|%0, %1}"
565 [(set_attr "type" "icmp")
566 (set_attr "mode" "HI")])
568 (define_insn "*cmpqi_ccno_1"
570 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
571 (match_operand:QI 1 "const0_operand" "n,n")))]
572 "ix86_match_ccmode (insn, CCNOmode)"
574 test{b}\t{%0, %0|%0, %0}
575 cmp{b}\t{$0, %0|%0, 0}"
576 [(set_attr "type" "test,icmp")
577 (set_attr "length_immediate" "0,1")
578 (set_attr "mode" "QI")])
580 (define_insn "*cmpqi_1"
582 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
583 (match_operand:QI 1 "general_operand" "qi,mq")))]
584 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
585 && ix86_match_ccmode (insn, CCmode)"
586 "cmp{b}\t{%1, %0|%0, %1}"
587 [(set_attr "type" "icmp")
588 (set_attr "mode" "QI")])
590 (define_insn "*cmpqi_minus_1"
592 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
593 (match_operand:QI 1 "general_operand" "qi,mq"))
595 "ix86_match_ccmode (insn, CCGOCmode)"
596 "cmp{b}\t{%1, %0|%0, %1}"
597 [(set_attr "type" "icmp")
598 (set_attr "mode" "QI")])
600 (define_insn "*cmpqi_ext_1"
603 (match_operand:QI 0 "general_operand" "Qm")
606 (match_operand 1 "ext_register_operand" "Q")
609 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
610 "cmp{b}\t{%h1, %0|%0, %h1}"
611 [(set_attr "type" "icmp")
612 (set_attr "mode" "QI")])
614 (define_insn "*cmpqi_ext_1_rex64"
617 (match_operand:QI 0 "register_operand" "Q")
620 (match_operand 1 "ext_register_operand" "Q")
623 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
624 "cmp{b}\t{%h1, %0|%0, %h1}"
625 [(set_attr "type" "icmp")
626 (set_attr "mode" "QI")])
628 (define_insn "*cmpqi_ext_2"
633 (match_operand 0 "ext_register_operand" "Q")
636 (match_operand:QI 1 "const0_operand" "n")))]
637 "ix86_match_ccmode (insn, CCNOmode)"
639 [(set_attr "type" "test")
640 (set_attr "length_immediate" "0")
641 (set_attr "mode" "QI")])
643 (define_expand "cmpqi_ext_3"
648 (match_operand 0 "ext_register_operand" "")
651 (match_operand:QI 1 "general_operand" "")))]
655 (define_insn "cmpqi_ext_3_insn"
660 (match_operand 0 "ext_register_operand" "Q")
663 (match_operand:QI 1 "general_operand" "Qmn")))]
664 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
665 "cmp{b}\t{%1, %h0|%h0, %1}"
666 [(set_attr "type" "icmp")
667 (set_attr "mode" "QI")])
669 (define_insn "cmpqi_ext_3_insn_rex64"
674 (match_operand 0 "ext_register_operand" "Q")
677 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
678 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
679 "cmp{b}\t{%1, %h0|%h0, %1}"
680 [(set_attr "type" "icmp")
681 (set_attr "mode" "QI")])
683 (define_insn "*cmpqi_ext_4"
688 (match_operand 0 "ext_register_operand" "Q")
693 (match_operand 1 "ext_register_operand" "Q")
696 "ix86_match_ccmode (insn, CCmode)"
697 "cmp{b}\t{%h1, %h0|%h0, %h1}"
698 [(set_attr "type" "icmp")
699 (set_attr "mode" "QI")])
701 ;; These implement float point compares.
702 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
703 ;; which would allow mix and match FP modes on the compares. Which is what
704 ;; the old patterns did, but with many more of them.
706 (define_expand "cmpxf"
708 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
709 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
710 "!TARGET_64BIT && TARGET_80387"
712 ix86_compare_op0 = operands[0];
713 ix86_compare_op1 = operands[1];
717 (define_expand "cmptf"
719 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
720 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
723 ix86_compare_op0 = operands[0];
724 ix86_compare_op1 = operands[1];
728 (define_expand "cmpdf"
730 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
731 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
732 "TARGET_80387 || TARGET_SSE2"
734 ix86_compare_op0 = operands[0];
735 ix86_compare_op1 = operands[1];
739 (define_expand "cmpsf"
741 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
742 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
743 "TARGET_80387 || TARGET_SSE"
745 ix86_compare_op0 = operands[0];
746 ix86_compare_op1 = operands[1];
750 ;; FP compares, step 1:
751 ;; Set the FP condition codes.
753 ;; CCFPmode compare with exceptions
754 ;; CCFPUmode compare with no exceptions
756 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
757 ;; and that fp moves clobber the condition codes, and that there is
758 ;; currently no way to describe this fact to reg-stack. So there are
759 ;; no splitters yet for this.
761 ;; %%% YIKES! This scheme does not retain a strong connection between
762 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
763 ;; work! Only allow tos/mem with tos in op 0.
765 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
766 ;; things aren't as bad as they sound...
768 (define_insn "*cmpfp_0"
769 [(set (match_operand:HI 0 "register_operand" "=a")
771 [(compare:CCFP (match_operand 1 "register_operand" "f")
772 (match_operand 2 "const0_operand" "X"))]
775 && FLOAT_MODE_P (GET_MODE (operands[1]))
776 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
778 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
779 return "ftst\;fnstsw\t%0\;fstp\t%y0";
781 return "ftst\;fnstsw\t%0";
783 [(set_attr "type" "multi")
785 (cond [(match_operand:SF 1 "" "")
787 (match_operand:DF 1 "" "")
790 (const_string "XF")))])
792 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
793 ;; used to manage the reg stack popping would not be preserved.
795 (define_insn "*cmpfp_2_sf"
798 (match_operand:SF 0 "register_operand" "f")
799 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
801 "* return output_fp_compare (insn, operands, 0, 0);"
802 [(set_attr "type" "fcmp")
803 (set_attr "mode" "SF")])
805 (define_insn "*cmpfp_2_sf_1"
806 [(set (match_operand:HI 0 "register_operand" "=a")
809 (match_operand:SF 1 "register_operand" "f")
810 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
813 "* return output_fp_compare (insn, operands, 2, 0);"
814 [(set_attr "type" "fcmp")
815 (set_attr "mode" "SF")])
817 (define_insn "*cmpfp_2_df"
820 (match_operand:DF 0 "register_operand" "f")
821 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
823 "* return output_fp_compare (insn, operands, 0, 0);"
824 [(set_attr "type" "fcmp")
825 (set_attr "mode" "DF")])
827 (define_insn "*cmpfp_2_df_1"
828 [(set (match_operand:HI 0 "register_operand" "=a")
831 (match_operand:DF 1 "register_operand" "f")
832 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
835 "* return output_fp_compare (insn, operands, 2, 0);"
836 [(set_attr "type" "multi")
837 (set_attr "mode" "DF")])
839 (define_insn "*cmpfp_2_xf"
842 (match_operand:XF 0 "register_operand" "f")
843 (match_operand:XF 1 "register_operand" "f")))]
844 "!TARGET_64BIT && TARGET_80387"
845 "* return output_fp_compare (insn, operands, 0, 0);"
846 [(set_attr "type" "fcmp")
847 (set_attr "mode" "XF")])
849 (define_insn "*cmpfp_2_tf"
852 (match_operand:TF 0 "register_operand" "f")
853 (match_operand:TF 1 "register_operand" "f")))]
855 "* return output_fp_compare (insn, operands, 0, 0);"
856 [(set_attr "type" "fcmp")
857 (set_attr "mode" "XF")])
859 (define_insn "*cmpfp_2_xf_1"
860 [(set (match_operand:HI 0 "register_operand" "=a")
863 (match_operand:XF 1 "register_operand" "f")
864 (match_operand:XF 2 "register_operand" "f"))]
866 "!TARGET_64BIT && TARGET_80387"
867 "* return output_fp_compare (insn, operands, 2, 0);"
868 [(set_attr "type" "multi")
869 (set_attr "mode" "XF")])
871 (define_insn "*cmpfp_2_tf_1"
872 [(set (match_operand:HI 0 "register_operand" "=a")
875 (match_operand:TF 1 "register_operand" "f")
876 (match_operand:TF 2 "register_operand" "f"))]
879 "* return output_fp_compare (insn, operands, 2, 0);"
880 [(set_attr "type" "multi")
881 (set_attr "mode" "XF")])
883 (define_insn "*cmpfp_2u"
886 (match_operand 0 "register_operand" "f")
887 (match_operand 1 "register_operand" "f")))]
889 && FLOAT_MODE_P (GET_MODE (operands[0]))
890 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
891 "* return output_fp_compare (insn, operands, 0, 1);"
892 [(set_attr "type" "fcmp")
894 (cond [(match_operand:SF 1 "" "")
896 (match_operand:DF 1 "" "")
899 (const_string "XF")))])
901 (define_insn "*cmpfp_2u_1"
902 [(set (match_operand:HI 0 "register_operand" "=a")
905 (match_operand 1 "register_operand" "f")
906 (match_operand 2 "register_operand" "f"))]
909 && FLOAT_MODE_P (GET_MODE (operands[1]))
910 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
911 "* return output_fp_compare (insn, operands, 2, 1);"
912 [(set_attr "type" "multi")
914 (cond [(match_operand:SF 1 "" "")
916 (match_operand:DF 1 "" "")
919 (const_string "XF")))])
921 ;; Patterns to match the SImode-in-memory ficom instructions.
923 ;; %%% Play games with accepting gp registers, as otherwise we have to
924 ;; force them to memory during rtl generation, which is no good. We
925 ;; can get rid of this once we teach reload to do memory input reloads
928 (define_insn "*ficom_1"
931 (match_operand 0 "register_operand" "f,f")
932 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
933 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
934 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
937 ;; Split the not-really-implemented gp register case into a
938 ;; push-op-pop sequence.
940 ;; %%% This is most efficient, but am I gonna get in trouble
941 ;; for separating cc0_setter and cc0_user?
946 (match_operand:SF 0 "register_operand" "")
947 (float (match_operand:SI 1 "register_operand" ""))))]
948 "0 && TARGET_80387 && reload_completed"
949 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
950 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
951 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
952 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
953 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
954 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
956 ;; FP compares, step 2
957 ;; Move the fpsw to ax.
959 (define_insn "*x86_fnstsw_1"
960 [(set (match_operand:HI 0 "register_operand" "=a")
961 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
964 [(set_attr "length" "2")
965 (set_attr "mode" "SI")
966 (set_attr "unit" "i387")
967 (set_attr "ppro_uops" "few")])
969 ;; FP compares, step 3
970 ;; Get ax into flags, general case.
972 (define_insn "x86_sahf_1"
974 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
977 [(set_attr "length" "1")
978 (set_attr "athlon_decode" "vector")
979 (set_attr "mode" "SI")
980 (set_attr "ppro_uops" "one")])
982 ;; Pentium Pro can do steps 1 through 3 in one go.
984 (define_insn "*cmpfp_i"
986 (compare:CCFP (match_operand 0 "register_operand" "f")
987 (match_operand 1 "register_operand" "f")))]
988 "TARGET_80387 && TARGET_CMOVE
989 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
990 && FLOAT_MODE_P (GET_MODE (operands[0]))
991 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
992 "* return output_fp_compare (insn, operands, 1, 0);"
993 [(set_attr "type" "fcmp")
995 (cond [(match_operand:SF 1 "" "")
997 (match_operand:DF 1 "" "")
1000 (const_string "XF")))
1001 (set_attr "athlon_decode" "vector")])
1003 (define_insn "*cmpfp_i_sse"
1005 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1006 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1008 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1009 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1010 "* return output_fp_compare (insn, operands, 1, 0);"
1011 [(set_attr "type" "fcmp,ssecomi")
1013 (if_then_else (match_operand:SF 1 "" "")
1015 (const_string "DF")))
1016 (set_attr "athlon_decode" "vector")])
1018 (define_insn "*cmpfp_i_sse_only"
1020 (compare:CCFP (match_operand 0 "register_operand" "x")
1021 (match_operand 1 "nonimmediate_operand" "xm")))]
1022 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1023 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1024 "* return output_fp_compare (insn, operands, 1, 0);"
1025 [(set_attr "type" "ssecomi")
1027 (if_then_else (match_operand:SF 1 "" "")
1029 (const_string "DF")))
1030 (set_attr "athlon_decode" "vector")])
1032 (define_insn "*cmpfp_iu"
1033 [(set (reg:CCFPU 17)
1034 (compare:CCFPU (match_operand 0 "register_operand" "f")
1035 (match_operand 1 "register_operand" "f")))]
1036 "TARGET_80387 && TARGET_CMOVE
1037 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1038 && FLOAT_MODE_P (GET_MODE (operands[0]))
1039 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1040 "* return output_fp_compare (insn, operands, 1, 1);"
1041 [(set_attr "type" "fcmp")
1043 (cond [(match_operand:SF 1 "" "")
1045 (match_operand:DF 1 "" "")
1048 (const_string "XF")))
1049 (set_attr "athlon_decode" "vector")])
1051 (define_insn "*cmpfp_iu_sse"
1052 [(set (reg:CCFPU 17)
1053 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1054 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1056 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1057 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1058 "* return output_fp_compare (insn, operands, 1, 1);"
1059 [(set_attr "type" "fcmp,ssecomi")
1061 (if_then_else (match_operand:SF 1 "" "")
1063 (const_string "DF")))
1064 (set_attr "athlon_decode" "vector")])
1066 (define_insn "*cmpfp_iu_sse_only"
1067 [(set (reg:CCFPU 17)
1068 (compare:CCFPU (match_operand 0 "register_operand" "x")
1069 (match_operand 1 "nonimmediate_operand" "xm")))]
1070 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1071 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1072 "* return output_fp_compare (insn, operands, 1, 1);"
1073 [(set_attr "type" "ssecomi")
1075 (if_then_else (match_operand:SF 1 "" "")
1077 (const_string "DF")))
1078 (set_attr "athlon_decode" "vector")])
1080 ;; Move instructions.
1082 ;; General case of fullword move.
1084 (define_expand "movsi"
1085 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1086 (match_operand:SI 1 "general_operand" ""))]
1088 "ix86_expand_move (SImode, operands); DONE;")
1090 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1093 ;; %%% We don't use a post-inc memory reference because x86 is not a
1094 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1095 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1096 ;; targets without our curiosities, and it is just as easy to represent
1097 ;; this differently.
1099 (define_insn "*pushsi2"
1100 [(set (match_operand:SI 0 "push_operand" "=<")
1101 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1104 [(set_attr "type" "push")
1105 (set_attr "mode" "SI")])
1107 ;; For 64BIT abi we always round up to 8 bytes.
1108 (define_insn "*pushsi2_rex64"
1109 [(set (match_operand:SI 0 "push_operand" "=X")
1110 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1113 [(set_attr "type" "push")
1114 (set_attr "mode" "SI")])
1116 (define_insn "*pushsi2_prologue"
1117 [(set (match_operand:SI 0 "push_operand" "=<")
1118 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1119 (clobber (mem:BLK (scratch)))]
1122 [(set_attr "type" "push")
1123 (set_attr "mode" "SI")])
1125 (define_insn "*popsi1_epilogue"
1126 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1127 (mem:SI (reg:SI 7)))
1129 (plus:SI (reg:SI 7) (const_int 4)))
1130 (clobber (mem:BLK (scratch)))]
1133 [(set_attr "type" "pop")
1134 (set_attr "mode" "SI")])
1136 (define_insn "popsi1"
1137 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1138 (mem:SI (reg:SI 7)))
1140 (plus:SI (reg:SI 7) (const_int 4)))]
1143 [(set_attr "type" "pop")
1144 (set_attr "mode" "SI")])
1146 (define_insn "*movsi_xor"
1147 [(set (match_operand:SI 0 "register_operand" "=r")
1148 (match_operand:SI 1 "const0_operand" "i"))
1149 (clobber (reg:CC 17))]
1150 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1151 "xor{l}\t{%0, %0|%0, %0}"
1152 [(set_attr "type" "alu1")
1153 (set_attr "mode" "SI")
1154 (set_attr "length_immediate" "0")])
1156 (define_insn "*movsi_or"
1157 [(set (match_operand:SI 0 "register_operand" "=r")
1158 (match_operand:SI 1 "immediate_operand" "i"))
1159 (clobber (reg:CC 17))]
1160 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1161 && INTVAL (operands[1]) == -1
1162 && (TARGET_PENTIUM || optimize_size)"
1164 operands[1] = constm1_rtx;
1165 return "or{l}\t{%1, %0|%0, %1}";
1167 [(set_attr "type" "alu1")
1168 (set_attr "mode" "SI")
1169 (set_attr "length_immediate" "1")])
1171 (define_insn "*movsi_1"
1172 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1173 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1174 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1175 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1177 switch (get_attr_type (insn))
1180 if (get_attr_mode (insn) == MODE_TI)
1181 return "movdqa\t{%1, %0|%0, %1}";
1182 return "movd\t{%1, %0|%0, %1}";
1185 if (get_attr_mode (insn) == MODE_DI)
1186 return "movq\t{%1, %0|%0, %1}";
1187 return "movd\t{%1, %0|%0, %1}";
1190 return "lea{l}\t{%1, %0|%0, %1}";
1193 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1195 return "mov{l}\t{%1, %0|%0, %1}";
1199 (cond [(eq_attr "alternative" "2,3,4")
1200 (const_string "mmxmov")
1201 (eq_attr "alternative" "5,6,7")
1202 (const_string "ssemov")
1203 (and (ne (symbol_ref "flag_pic") (const_int 0))
1204 (match_operand:SI 1 "symbolic_operand" ""))
1205 (const_string "lea")
1207 (const_string "imov")))
1208 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1210 (define_insn "*movsi_1_nointernunit"
1211 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1212 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1213 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1214 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1216 switch (get_attr_type (insn))
1219 if (get_attr_mode (insn) == MODE_TI)
1220 return "movdqa\t{%1, %0|%0, %1}";
1221 return "movd\t{%1, %0|%0, %1}";
1224 if (get_attr_mode (insn) == MODE_DI)
1225 return "movq\t{%1, %0|%0, %1}";
1226 return "movd\t{%1, %0|%0, %1}";
1229 return "lea{l}\t{%1, %0|%0, %1}";
1232 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1234 return "mov{l}\t{%1, %0|%0, %1}";
1238 (cond [(eq_attr "alternative" "2,3,4")
1239 (const_string "mmxmov")
1240 (eq_attr "alternative" "5,6,7")
1241 (const_string "ssemov")
1242 (and (ne (symbol_ref "flag_pic") (const_int 0))
1243 (match_operand:SI 1 "symbolic_operand" ""))
1244 (const_string "lea")
1246 (const_string "imov")))
1247 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1249 ;; Stores and loads of ax to arbitrary constant address.
1250 ;; We fake an second form of instruction to force reload to load address
1251 ;; into register when rax is not available
1252 (define_insn "*movabssi_1_rex64"
1253 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1254 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1257 movabs{l}\t{%1, %P0|%P0, %1}
1258 mov{l}\t{%1, %a0|%a0, %1}
1259 movabs{l}\t{%1, %a0|%a0, %1}"
1260 [(set_attr "type" "imov")
1261 (set_attr "modrm" "0,*,*")
1262 (set_attr "length_address" "8,0,0")
1263 (set_attr "length_immediate" "0,*,*")
1264 (set_attr "memory" "store")
1265 (set_attr "mode" "SI")])
1267 (define_insn "*movabssi_2_rex64"
1268 [(set (match_operand:SI 0 "register_operand" "=a,r")
1269 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1272 movabs{l}\t{%P1, %0|%0, %P1}
1273 mov{l}\t{%a1, %0|%0, %a1}"
1274 [(set_attr "type" "imov")
1275 (set_attr "modrm" "0,*")
1276 (set_attr "length_address" "8,0")
1277 (set_attr "length_immediate" "0")
1278 (set_attr "memory" "load")
1279 (set_attr "mode" "SI")])
1281 (define_insn "*swapsi"
1282 [(set (match_operand:SI 0 "register_operand" "+r")
1283 (match_operand:SI 1 "register_operand" "+r"))
1288 [(set_attr "type" "imov")
1289 (set_attr "pent_pair" "np")
1290 (set_attr "athlon_decode" "vector")
1291 (set_attr "mode" "SI")
1292 (set_attr "modrm" "0")
1293 (set_attr "ppro_uops" "few")])
1295 (define_expand "movhi"
1296 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1297 (match_operand:HI 1 "general_operand" ""))]
1299 "ix86_expand_move (HImode, operands); DONE;")
1301 (define_insn "*pushhi2"
1302 [(set (match_operand:HI 0 "push_operand" "=<,<")
1303 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1306 push{w}\t{|WORD PTR }%1
1308 [(set_attr "type" "push")
1309 (set_attr "mode" "HI")])
1311 ;; For 64BIT abi we always round up to 8 bytes.
1312 (define_insn "*pushhi2_rex64"
1313 [(set (match_operand:HI 0 "push_operand" "=X")
1314 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1317 [(set_attr "type" "push")
1318 (set_attr "mode" "QI")])
1320 (define_insn "*movhi_1"
1321 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1322 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1323 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1325 switch (get_attr_type (insn))
1328 /* movzwl is faster than movw on p2 due to partial word stalls,
1329 though not as fast as an aligned movl. */
1330 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1332 if (get_attr_mode (insn) == MODE_SI)
1333 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1335 return "mov{w}\t{%1, %0|%0, %1}";
1339 (cond [(and (eq_attr "alternative" "0")
1340 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1342 (eq (symbol_ref "TARGET_HIMODE_MATH")
1344 (const_string "imov")
1345 (and (eq_attr "alternative" "1,2")
1346 (match_operand:HI 1 "aligned_operand" ""))
1347 (const_string "imov")
1348 (and (ne (symbol_ref "TARGET_MOVX")
1350 (eq_attr "alternative" "0,2"))
1351 (const_string "imovx")
1353 (const_string "imov")))
1355 (cond [(eq_attr "type" "imovx")
1357 (and (eq_attr "alternative" "1,2")
1358 (match_operand:HI 1 "aligned_operand" ""))
1360 (and (eq_attr "alternative" "0")
1361 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1363 (eq (symbol_ref "TARGET_HIMODE_MATH")
1367 (const_string "HI")))])
1369 ;; Stores and loads of ax to arbitrary constant address.
1370 ;; We fake an second form of instruction to force reload to load address
1371 ;; into register when rax is not available
1372 (define_insn "*movabshi_1_rex64"
1373 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1374 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1377 movabs{w}\t{%1, %P0|%P0, %1}
1378 mov{w}\t{%1, %a0|%a0, %1}
1379 movabs{w}\t{%1, %a0|%a0, %1}"
1380 [(set_attr "type" "imov")
1381 (set_attr "modrm" "0,*,*")
1382 (set_attr "length_address" "8,0,0")
1383 (set_attr "length_immediate" "0,*,*")
1384 (set_attr "memory" "store")
1385 (set_attr "mode" "HI")])
1387 (define_insn "*movabshi_2_rex64"
1388 [(set (match_operand:HI 0 "register_operand" "=a,r")
1389 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1392 movabs{w}\t{%P1, %0|%0, %P1}
1393 mov{w}\t{%a1, %0|%0, %a1}"
1394 [(set_attr "type" "imov")
1395 (set_attr "modrm" "0,*")
1396 (set_attr "length_address" "8,0")
1397 (set_attr "length_immediate" "0")
1398 (set_attr "memory" "load")
1399 (set_attr "mode" "HI")])
1401 (define_insn "*swaphi_1"
1402 [(set (match_operand:HI 0 "register_operand" "+r")
1403 (match_operand:HI 1 "register_operand" "+r"))
1406 "TARGET_PARTIAL_REG_STALL"
1408 [(set_attr "type" "imov")
1409 (set_attr "pent_pair" "np")
1410 (set_attr "mode" "HI")
1411 (set_attr "modrm" "0")
1412 (set_attr "ppro_uops" "few")])
1414 (define_insn "*swaphi_2"
1415 [(set (match_operand:HI 0 "register_operand" "+r")
1416 (match_operand:HI 1 "register_operand" "+r"))
1419 "! TARGET_PARTIAL_REG_STALL"
1421 [(set_attr "type" "imov")
1422 (set_attr "pent_pair" "np")
1423 (set_attr "mode" "SI")
1424 (set_attr "modrm" "0")
1425 (set_attr "ppro_uops" "few")])
1427 (define_expand "movstricthi"
1428 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1429 (match_operand:HI 1 "general_operand" ""))]
1430 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1432 /* Don't generate memory->memory moves, go through a register */
1433 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1434 operands[1] = force_reg (HImode, operands[1]);
1437 (define_insn "*movstricthi_1"
1438 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1439 (match_operand:HI 1 "general_operand" "rn,m"))]
1440 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1441 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1442 "mov{w}\t{%1, %0|%0, %1}"
1443 [(set_attr "type" "imov")
1444 (set_attr "mode" "HI")])
1446 (define_insn "*movstricthi_xor"
1447 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1448 (match_operand:HI 1 "const0_operand" "i"))
1449 (clobber (reg:CC 17))]
1451 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1452 "xor{w}\t{%0, %0|%0, %0}"
1453 [(set_attr "type" "alu1")
1454 (set_attr "mode" "HI")
1455 (set_attr "length_immediate" "0")])
1457 (define_expand "movqi"
1458 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1459 (match_operand:QI 1 "general_operand" ""))]
1461 "ix86_expand_move (QImode, operands); DONE;")
1463 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1464 ;; "push a byte". But actually we use pushw, which has the effect
1465 ;; of rounding the amount pushed up to a halfword.
1467 (define_insn "*pushqi2"
1468 [(set (match_operand:QI 0 "push_operand" "=X,X")
1469 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1472 push{w}\t{|word ptr }%1
1474 [(set_attr "type" "push")
1475 (set_attr "mode" "HI")])
1477 ;; For 64BIT abi we always round up to 8 bytes.
1478 (define_insn "*pushqi2_rex64"
1479 [(set (match_operand:QI 0 "push_operand" "=X")
1480 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1483 [(set_attr "type" "push")
1484 (set_attr "mode" "QI")])
1486 ;; Situation is quite tricky about when to choose full sized (SImode) move
1487 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1488 ;; partial register dependency machines (such as AMD Athlon), where QImode
1489 ;; moves issue extra dependency and for partial register stalls machines
1490 ;; that don't use QImode patterns (and QImode move cause stall on the next
1493 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1494 ;; register stall machines with, where we use QImode instructions, since
1495 ;; partial register stall can be caused there. Then we use movzx.
1496 (define_insn "*movqi_1"
1497 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1498 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1499 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1501 switch (get_attr_type (insn))
1504 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1506 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1508 if (get_attr_mode (insn) == MODE_SI)
1509 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1511 return "mov{b}\t{%1, %0|%0, %1}";
1515 (cond [(and (eq_attr "alternative" "3")
1516 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1518 (eq (symbol_ref "TARGET_QIMODE_MATH")
1520 (const_string "imov")
1521 (eq_attr "alternative" "3,5")
1522 (const_string "imovx")
1523 (and (ne (symbol_ref "TARGET_MOVX")
1525 (eq_attr "alternative" "2"))
1526 (const_string "imovx")
1528 (const_string "imov")))
1530 (cond [(eq_attr "alternative" "3,4,5")
1532 (eq_attr "alternative" "6")
1534 (eq_attr "type" "imovx")
1536 (and (eq_attr "type" "imov")
1537 (and (eq_attr "alternative" "0,1,2")
1538 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1541 ;; Avoid partial register stalls when not using QImode arithmetic
1542 (and (eq_attr "type" "imov")
1543 (and (eq_attr "alternative" "0,1,2")
1544 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1546 (eq (symbol_ref "TARGET_QIMODE_MATH")
1550 (const_string "QI")))])
1552 (define_expand "reload_outqi"
1553 [(parallel [(match_operand:QI 0 "" "=m")
1554 (match_operand:QI 1 "register_operand" "r")
1555 (match_operand:QI 2 "register_operand" "=&q")])]
1559 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1561 if (reg_overlap_mentioned_p (op2, op0))
1563 if (! q_regs_operand (op1, QImode))
1565 emit_insn (gen_movqi (op2, op1));
1568 emit_insn (gen_movqi (op0, op1));
1572 (define_insn "*swapqi"
1573 [(set (match_operand:QI 0 "register_operand" "+r")
1574 (match_operand:QI 1 "register_operand" "+r"))
1579 [(set_attr "type" "imov")
1580 (set_attr "pent_pair" "np")
1581 (set_attr "mode" "QI")
1582 (set_attr "modrm" "0")
1583 (set_attr "ppro_uops" "few")])
1585 (define_expand "movstrictqi"
1586 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1587 (match_operand:QI 1 "general_operand" ""))]
1588 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1590 /* Don't generate memory->memory moves, go through a register. */
1591 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1592 operands[1] = force_reg (QImode, operands[1]);
1595 (define_insn "*movstrictqi_1"
1596 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1597 (match_operand:QI 1 "general_operand" "*qn,m"))]
1598 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1599 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1600 "mov{b}\t{%1, %0|%0, %1}"
1601 [(set_attr "type" "imov")
1602 (set_attr "mode" "QI")])
1604 (define_insn "*movstrictqi_xor"
1605 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1606 (match_operand:QI 1 "const0_operand" "i"))
1607 (clobber (reg:CC 17))]
1608 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1609 "xor{b}\t{%0, %0|%0, %0}"
1610 [(set_attr "type" "alu1")
1611 (set_attr "mode" "QI")
1612 (set_attr "length_immediate" "0")])
1614 (define_insn "*movsi_extv_1"
1615 [(set (match_operand:SI 0 "register_operand" "=R")
1616 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1620 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1621 [(set_attr "type" "imovx")
1622 (set_attr "mode" "SI")])
1624 (define_insn "*movhi_extv_1"
1625 [(set (match_operand:HI 0 "register_operand" "=R")
1626 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1630 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1631 [(set_attr "type" "imovx")
1632 (set_attr "mode" "SI")])
1634 (define_insn "*movqi_extv_1"
1635 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1636 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1641 switch (get_attr_type (insn))
1644 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1646 return "mov{b}\t{%h1, %0|%0, %h1}";
1650 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1651 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1652 (ne (symbol_ref "TARGET_MOVX")
1654 (const_string "imovx")
1655 (const_string "imov")))
1657 (if_then_else (eq_attr "type" "imovx")
1659 (const_string "QI")))])
1661 (define_insn "*movqi_extv_1_rex64"
1662 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1663 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1668 switch (get_attr_type (insn))
1671 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1673 return "mov{b}\t{%h1, %0|%0, %h1}";
1677 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1678 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1679 (ne (symbol_ref "TARGET_MOVX")
1681 (const_string "imovx")
1682 (const_string "imov")))
1684 (if_then_else (eq_attr "type" "imovx")
1686 (const_string "QI")))])
1688 ;; Stores and loads of ax to arbitrary constant address.
1689 ;; We fake an second form of instruction to force reload to load address
1690 ;; into register when rax is not available
1691 (define_insn "*movabsqi_1_rex64"
1692 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1693 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1696 movabs{b}\t{%1, %P0|%P0, %1}
1697 mov{b}\t{%1, %a0|%a0, %1}
1698 movabs{b}\t{%1, %a0|%a0, %1}"
1699 [(set_attr "type" "imov")
1700 (set_attr "modrm" "0,*,*")
1701 (set_attr "length_address" "8,0,0")
1702 (set_attr "length_immediate" "0,*,*")
1703 (set_attr "memory" "store")
1704 (set_attr "mode" "QI")])
1706 (define_insn "*movabsqi_2_rex64"
1707 [(set (match_operand:QI 0 "register_operand" "=a,r")
1708 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1711 movabs{b}\t{%P1, %0|%0, %P1}
1712 mov{b}\t{%a1, %0|%0, %a1}"
1713 [(set_attr "type" "imov")
1714 (set_attr "modrm" "0,*")
1715 (set_attr "length_address" "8,0")
1716 (set_attr "length_immediate" "0")
1717 (set_attr "memory" "load")
1718 (set_attr "mode" "QI")])
1720 (define_insn "*movsi_extzv_1"
1721 [(set (match_operand:SI 0 "register_operand" "=R")
1722 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1726 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1727 [(set_attr "type" "imovx")
1728 (set_attr "mode" "SI")])
1730 (define_insn "*movqi_extzv_2"
1731 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1732 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1737 switch (get_attr_type (insn))
1740 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1742 return "mov{b}\t{%h1, %0|%0, %h1}";
1746 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1747 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1748 (ne (symbol_ref "TARGET_MOVX")
1750 (const_string "imovx")
1751 (const_string "imov")))
1753 (if_then_else (eq_attr "type" "imovx")
1755 (const_string "QI")))])
1757 (define_insn "*movqi_extzv_2_rex64"
1758 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1759 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1764 switch (get_attr_type (insn))
1767 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1769 return "mov{b}\t{%h1, %0|%0, %h1}";
1773 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1774 (ne (symbol_ref "TARGET_MOVX")
1776 (const_string "imovx")
1777 (const_string "imov")))
1779 (if_then_else (eq_attr "type" "imovx")
1781 (const_string "QI")))])
1783 (define_insn "movsi_insv_1"
1784 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1787 (match_operand:SI 1 "general_operand" "Qmn"))]
1789 "mov{b}\t{%b1, %h0|%h0, %b1}"
1790 [(set_attr "type" "imov")
1791 (set_attr "mode" "QI")])
1793 (define_insn "*movsi_insv_1_rex64"
1794 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1797 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1799 "mov{b}\t{%b1, %h0|%h0, %b1}"
1800 [(set_attr "type" "imov")
1801 (set_attr "mode" "QI")])
1803 (define_insn "*movqi_insv_2"
1804 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1807 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1811 "mov{b}\t{%h1, %h0|%h0, %h1}"
1812 [(set_attr "type" "imov")
1813 (set_attr "mode" "QI")])
1815 (define_expand "movdi"
1816 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1817 (match_operand:DI 1 "general_operand" ""))]
1819 "ix86_expand_move (DImode, operands); DONE;")
1821 (define_insn "*pushdi"
1822 [(set (match_operand:DI 0 "push_operand" "=<")
1823 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1827 (define_insn "pushdi2_rex64"
1828 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1829 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1834 [(set_attr "type" "push,multi")
1835 (set_attr "mode" "DI")])
1837 ;; Convert impossible pushes of immediate to existing instructions.
1838 ;; First try to get scratch register and go through it. In case this
1839 ;; fails, push sign extended lower part first and then overwrite
1840 ;; upper part by 32bit move.
1842 [(match_scratch:DI 2 "r")
1843 (set (match_operand:DI 0 "push_operand" "")
1844 (match_operand:DI 1 "immediate_operand" ""))]
1845 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1846 && !x86_64_immediate_operand (operands[1], DImode)"
1847 [(set (match_dup 2) (match_dup 1))
1848 (set (match_dup 0) (match_dup 2))]
1851 ;; We need to define this as both peepholer and splitter for case
1852 ;; peephole2 pass is not run.
1854 [(set (match_operand:DI 0 "push_operand" "")
1855 (match_operand:DI 1 "immediate_operand" ""))]
1856 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1857 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1858 [(set (match_dup 0) (match_dup 1))
1859 (set (match_dup 2) (match_dup 3))]
1860 "split_di (operands + 1, 1, operands + 2, operands + 3);
1861 operands[1] = gen_lowpart (DImode, operands[2]);
1862 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1867 [(set (match_operand:DI 0 "push_operand" "")
1868 (match_operand:DI 1 "immediate_operand" ""))]
1869 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1870 && !symbolic_operand (operands[1], DImode)
1871 && !x86_64_immediate_operand (operands[1], DImode)"
1872 [(set (match_dup 0) (match_dup 1))
1873 (set (match_dup 2) (match_dup 3))]
1874 "split_di (operands + 1, 1, operands + 2, operands + 3);
1875 operands[1] = gen_lowpart (DImode, operands[2]);
1876 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1880 (define_insn "*pushdi2_prologue_rex64"
1881 [(set (match_operand:DI 0 "push_operand" "=<")
1882 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1883 (clobber (mem:BLK (scratch)))]
1886 [(set_attr "type" "push")
1887 (set_attr "mode" "DI")])
1889 (define_insn "*popdi1_epilogue_rex64"
1890 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1891 (mem:DI (reg:DI 7)))
1893 (plus:DI (reg:DI 7) (const_int 8)))
1894 (clobber (mem:BLK (scratch)))]
1897 [(set_attr "type" "pop")
1898 (set_attr "mode" "DI")])
1900 (define_insn "popdi1"
1901 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1902 (mem:DI (reg:DI 7)))
1904 (plus:DI (reg:DI 7) (const_int 8)))]
1907 [(set_attr "type" "pop")
1908 (set_attr "mode" "DI")])
1910 (define_insn "*movdi_xor_rex64"
1911 [(set (match_operand:DI 0 "register_operand" "=r")
1912 (match_operand:DI 1 "const0_operand" "i"))
1913 (clobber (reg:CC 17))]
1914 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1915 && reload_completed"
1916 "xor{l}\t{%k0, %k0|%k0, %k0}"
1917 [(set_attr "type" "alu1")
1918 (set_attr "mode" "SI")
1919 (set_attr "length_immediate" "0")])
1921 (define_insn "*movdi_or_rex64"
1922 [(set (match_operand:DI 0 "register_operand" "=r")
1923 (match_operand:DI 1 "const_int_operand" "i"))
1924 (clobber (reg:CC 17))]
1925 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1927 && GET_CODE (operands[1]) == CONST_INT
1928 && INTVAL (operands[1]) == -1"
1930 operands[1] = constm1_rtx;
1931 return "or{q}\t{%1, %0|%0, %1}";
1933 [(set_attr "type" "alu1")
1934 (set_attr "mode" "DI")
1935 (set_attr "length_immediate" "1")])
1937 (define_insn "*movdi_2"
1938 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1939 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1941 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1945 movq\t{%1, %0|%0, %1}
1946 movq\t{%1, %0|%0, %1}
1947 movq\t{%1, %0|%0, %1}
1948 movdqa\t{%1, %0|%0, %1}
1949 movq\t{%1, %0|%0, %1}"
1950 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1951 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1954 [(set (match_operand:DI 0 "push_operand" "")
1955 (match_operand:DI 1 "general_operand" ""))]
1956 "!TARGET_64BIT && reload_completed
1957 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1959 "ix86_split_long_move (operands); DONE;")
1961 ;; %%% This multiword shite has got to go.
1963 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1964 (match_operand:DI 1 "general_operand" ""))]
1965 "!TARGET_64BIT && reload_completed
1966 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1967 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1969 "ix86_split_long_move (operands); DONE;")
1971 (define_insn "*movdi_1_rex64"
1972 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
1973 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
1975 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1976 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1978 switch (get_attr_type (insn))
1981 if (get_attr_mode (insn) == MODE_TI)
1982 return "movdqa\t{%1, %0|%0, %1}";
1985 /* Moves from and into integer register is done using movd opcode with
1987 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1988 return "movd\t{%1, %0|%0, %1}";
1989 return "movq\t{%1, %0|%0, %1}";
1993 return "lea{q}\t{%a1, %0|%0, %a1}";
1995 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1997 if (get_attr_mode (insn) == MODE_SI)
1998 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1999 else if (which_alternative == 2)
2000 return "movabs{q}\t{%1, %0|%0, %1}";
2002 return "mov{q}\t{%1, %0|%0, %1}";
2006 (cond [(eq_attr "alternative" "5,6,7")
2007 (const_string "mmxmov")
2008 (eq_attr "alternative" "8,9,10")
2009 (const_string "ssemov")
2010 (eq_attr "alternative" "4")
2011 (const_string "multi")
2012 (and (ne (symbol_ref "flag_pic") (const_int 0))
2013 (match_operand:DI 1 "symbolic_operand" ""))
2014 (const_string "lea")
2016 (const_string "imov")))
2017 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2018 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2019 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2021 (define_insn "*movdi_1_rex64_nointerunit"
2022 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2023 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2025 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2026 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2028 switch (get_attr_type (insn))
2031 if (get_attr_mode (insn) == MODE_TI)
2032 return "movdqa\t{%1, %0|%0, %1}";
2035 return "movq\t{%1, %0|%0, %1}";
2039 return "lea{q}\t{%a1, %0|%0, %a1}";
2041 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2043 if (get_attr_mode (insn) == MODE_SI)
2044 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2045 else if (which_alternative == 2)
2046 return "movabs{q}\t{%1, %0|%0, %1}";
2048 return "mov{q}\t{%1, %0|%0, %1}";
2052 (cond [(eq_attr "alternative" "5,6,7")
2053 (const_string "mmxmov")
2054 (eq_attr "alternative" "8,9,10")
2055 (const_string "ssemov")
2056 (eq_attr "alternative" "4")
2057 (const_string "multi")
2058 (and (ne (symbol_ref "flag_pic") (const_int 0))
2059 (match_operand:DI 1 "symbolic_operand" ""))
2060 (const_string "lea")
2062 (const_string "imov")))
2063 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2064 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2065 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2067 ;; Stores and loads of ax to arbitrary constant address.
2068 ;; We fake an second form of instruction to force reload to load address
2069 ;; into register when rax is not available
2070 (define_insn "*movabsdi_1_rex64"
2071 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2072 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2075 movabs{q}\t{%1, %P0|%P0, %1}
2076 mov{q}\t{%1, %a0|%a0, %1}
2077 movabs{q}\t{%1, %a0|%a0, %1}"
2078 [(set_attr "type" "imov")
2079 (set_attr "modrm" "0,*,*")
2080 (set_attr "length_address" "8,0,0")
2081 (set_attr "length_immediate" "0,*,*")
2082 (set_attr "memory" "store")
2083 (set_attr "mode" "DI")])
2085 (define_insn "*movabsdi_2_rex64"
2086 [(set (match_operand:DI 0 "register_operand" "=a,r")
2087 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2090 movabs{q}\t{%P1, %0|%0, %P1}
2091 mov{q}\t{%a1, %0|%0, %a1}"
2092 [(set_attr "type" "imov")
2093 (set_attr "modrm" "0,*")
2094 (set_attr "length_address" "8,0")
2095 (set_attr "length_immediate" "0")
2096 (set_attr "memory" "load")
2097 (set_attr "mode" "DI")])
2099 ;; Convert impossible stores of immediate to existing instructions.
2100 ;; First try to get scratch register and go through it. In case this
2101 ;; fails, move by 32bit parts.
2103 [(match_scratch:DI 2 "r")
2104 (set (match_operand:DI 0 "memory_operand" "")
2105 (match_operand:DI 1 "immediate_operand" ""))]
2106 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2107 && !x86_64_immediate_operand (operands[1], DImode)"
2108 [(set (match_dup 2) (match_dup 1))
2109 (set (match_dup 0) (match_dup 2))]
2112 ;; We need to define this as both peepholer and splitter for case
2113 ;; peephole2 pass is not run.
2115 [(set (match_operand:DI 0 "memory_operand" "")
2116 (match_operand:DI 1 "immediate_operand" ""))]
2117 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2118 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2119 [(set (match_dup 2) (match_dup 3))
2120 (set (match_dup 4) (match_dup 5))]
2121 "split_di (operands, 2, operands + 2, operands + 4);")
2124 [(set (match_operand:DI 0 "memory_operand" "")
2125 (match_operand:DI 1 "immediate_operand" ""))]
2126 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2127 && !symbolic_operand (operands[1], DImode)
2128 && !x86_64_immediate_operand (operands[1], DImode)"
2129 [(set (match_dup 2) (match_dup 3))
2130 (set (match_dup 4) (match_dup 5))]
2131 "split_di (operands, 2, operands + 2, operands + 4);")
2133 (define_insn "*swapdi_rex64"
2134 [(set (match_operand:DI 0 "register_operand" "+r")
2135 (match_operand:DI 1 "register_operand" "+r"))
2140 [(set_attr "type" "imov")
2141 (set_attr "pent_pair" "np")
2142 (set_attr "athlon_decode" "vector")
2143 (set_attr "mode" "DI")
2144 (set_attr "modrm" "0")
2145 (set_attr "ppro_uops" "few")])
2148 (define_expand "movsf"
2149 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2150 (match_operand:SF 1 "general_operand" ""))]
2152 "ix86_expand_move (SFmode, operands); DONE;")
2154 (define_insn "*pushsf"
2155 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2156 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2159 switch (which_alternative)
2162 return "push{l}\t%1";
2165 /* This insn should be already splitted before reg-stack. */
2169 [(set_attr "type" "multi,push,multi")
2170 (set_attr "mode" "SF,SI,SF")])
2172 (define_insn "*pushsf_rex64"
2173 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2174 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2177 switch (which_alternative)
2180 return "push{q}\t%q1";
2183 /* This insn should be already splitted before reg-stack. */
2187 [(set_attr "type" "multi,push,multi")
2188 (set_attr "mode" "SF,DI,SF")])
2191 [(set (match_operand:SF 0 "push_operand" "")
2192 (match_operand:SF 1 "memory_operand" ""))]
2194 && GET_CODE (operands[1]) == MEM
2195 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2196 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2199 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2202 ;; %%% Kill this when call knows how to work this out.
2204 [(set (match_operand:SF 0 "push_operand" "")
2205 (match_operand:SF 1 "any_fp_register_operand" ""))]
2207 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2208 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2211 [(set (match_operand:SF 0 "push_operand" "")
2212 (match_operand:SF 1 "any_fp_register_operand" ""))]
2214 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2215 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2217 (define_insn "*movsf_1"
2218 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2219 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2220 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2221 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2222 && (reload_in_progress || reload_completed
2223 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2224 || GET_CODE (operands[1]) != CONST_DOUBLE
2225 || memory_operand (operands[0], SFmode))"
2227 switch (which_alternative)
2230 if (REG_P (operands[1])
2231 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2233 else if (STACK_TOP_P (operands[0]))
2234 return "fld%z1\t%y1";
2239 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2240 return "fstp%z0\t%y0";
2242 return "fst%z0\t%y0";
2245 return standard_80387_constant_opcode (operands[1]);
2249 return "mov{l}\t{%1, %0|%0, %1}";
2251 if (get_attr_mode (insn) == MODE_TI)
2252 return "pxor\t%0, %0";
2254 return "xorps\t%0, %0";
2256 if (get_attr_mode (insn) == MODE_V4SF)
2257 return "movaps\t{%1, %0|%0, %1}";
2259 return "movss\t{%1, %0|%0, %1}";
2262 return "movss\t{%1, %0|%0, %1}";
2266 return "movd\t{%1, %0|%0, %1}";
2269 return "movq\t{%1, %0|%0, %1}";
2275 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2277 (cond [(eq_attr "alternative" "3,4,9,10")
2279 (eq_attr "alternative" "5")
2281 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2283 (ne (symbol_ref "TARGET_SSE2")
2285 (eq (symbol_ref "optimize_size")
2288 (const_string "V4SF"))
2289 /* For architectures resolving dependencies on
2290 whole SSE registers use APS move to break dependency
2291 chains, otherwise use short move to avoid extra work.
2293 Do the same for architectures resolving dependencies on
2294 the parts. While in DF mode it is better to always handle
2295 just register parts, the SF mode is different due to lack
2296 of instructions to load just part of the register. It is
2297 better to maintain the whole registers in single format
2298 to avoid problems on using packed logical operations. */
2299 (eq_attr "alternative" "6")
2301 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2303 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2305 (const_string "V4SF")
2306 (const_string "SF"))
2307 (eq_attr "alternative" "11")
2308 (const_string "DI")]
2309 (const_string "SF")))])
2311 (define_insn "*movsf_1_nointerunit"
2312 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2313 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2314 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2315 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2316 && (reload_in_progress || reload_completed
2317 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2318 || GET_CODE (operands[1]) != CONST_DOUBLE
2319 || memory_operand (operands[0], SFmode))"
2321 switch (which_alternative)
2324 if (REG_P (operands[1])
2325 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2327 if (REGNO (operands[0]) == FIRST_STACK_REG
2328 && TARGET_USE_FFREEP)
2329 return "ffreep\t%y0";
2332 else if (STACK_TOP_P (operands[0]))
2333 return "fld%z1\t%y1";
2338 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2339 return "fstp%z0\t%y0";
2341 return "fst%z0\t%y0";
2344 return standard_80387_constant_opcode (operands[1]);
2348 return "mov{l}\t{%1, %0|%0, %1}";
2350 if (get_attr_mode (insn) == MODE_TI)
2351 return "pxor\t%0, %0";
2353 return "xorps\t%0, %0";
2355 if (get_attr_mode (insn) == MODE_V4SF)
2356 return "movaps\t{%1, %0|%0, %1}";
2358 return "movss\t{%1, %0|%0, %1}";
2361 return "movss\t{%1, %0|%0, %1}";
2365 return "movd\t{%1, %0|%0, %1}";
2368 return "movq\t{%1, %0|%0, %1}";
2374 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2376 (cond [(eq_attr "alternative" "3,4,9,10")
2378 (eq_attr "alternative" "5")
2380 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2382 (ne (symbol_ref "TARGET_SSE2")
2384 (eq (symbol_ref "optimize_size")
2387 (const_string "V4SF"))
2388 /* For architectures resolving dependencies on
2389 whole SSE registers use APS move to break dependency
2390 chains, otherwise use short move to avoid extra work.
2392 Do the same for architectures resolving dependencies on
2393 the parts. While in DF mode it is better to always handle
2394 just register parts, the SF mode is different due to lack
2395 of instructions to load just part of the register. It is
2396 better to maintain the whole registers in single format
2397 to avoid problems on using packed logical operations. */
2398 (eq_attr "alternative" "6")
2400 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2402 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2404 (const_string "V4SF")
2405 (const_string "SF"))
2406 (eq_attr "alternative" "11")
2407 (const_string "DI")]
2408 (const_string "SF")))])
2410 (define_insn "*swapsf"
2411 [(set (match_operand:SF 0 "register_operand" "+f")
2412 (match_operand:SF 1 "register_operand" "+f"))
2415 "reload_completed || !TARGET_SSE"
2417 if (STACK_TOP_P (operands[0]))
2422 [(set_attr "type" "fxch")
2423 (set_attr "mode" "SF")])
2425 (define_expand "movdf"
2426 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2427 (match_operand:DF 1 "general_operand" ""))]
2429 "ix86_expand_move (DFmode, operands); DONE;")
2431 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2432 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2433 ;; On the average, pushdf using integers can be still shorter. Allow this
2434 ;; pattern for optimize_size too.
2436 (define_insn "*pushdf_nointeger"
2437 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2438 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2439 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2441 /* This insn should be already splitted before reg-stack. */
2444 [(set_attr "type" "multi")
2445 (set_attr "mode" "DF,SI,SI,DF")])
2447 (define_insn "*pushdf_integer"
2448 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2449 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2450 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2452 /* This insn should be already splitted before reg-stack. */
2455 [(set_attr "type" "multi")
2456 (set_attr "mode" "DF,SI,DF")])
2458 ;; %%% Kill this when call knows how to work this out.
2460 [(set (match_operand:DF 0 "push_operand" "")
2461 (match_operand:DF 1 "any_fp_register_operand" ""))]
2462 "!TARGET_64BIT && reload_completed"
2463 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2464 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2468 [(set (match_operand:DF 0 "push_operand" "")
2469 (match_operand:DF 1 "any_fp_register_operand" ""))]
2470 "TARGET_64BIT && reload_completed"
2471 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2472 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2476 [(set (match_operand:DF 0 "push_operand" "")
2477 (match_operand:DF 1 "general_operand" ""))]
2480 "ix86_split_long_move (operands); DONE;")
2482 ;; Moving is usually shorter when only FP registers are used. This separate
2483 ;; movdf pattern avoids the use of integer registers for FP operations
2484 ;; when optimizing for size.
2486 (define_insn "*movdf_nointeger"
2487 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2488 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2489 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2490 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2491 && (reload_in_progress || reload_completed
2492 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2493 || GET_CODE (operands[1]) != CONST_DOUBLE
2494 || memory_operand (operands[0], DFmode))"
2496 switch (which_alternative)
2499 if (REG_P (operands[1])
2500 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2502 if (REGNO (operands[0]) == FIRST_STACK_REG
2503 && TARGET_USE_FFREEP)
2504 return "ffreep\t%y0";
2507 else if (STACK_TOP_P (operands[0]))
2508 return "fld%z1\t%y1";
2513 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2514 return "fstp%z0\t%y0";
2516 return "fst%z0\t%y0";
2519 return standard_80387_constant_opcode (operands[1]);
2525 switch (get_attr_mode (insn))
2528 return "xorps\t%0, %0";
2530 return "xorpd\t%0, %0";
2532 return "pxor\t%0, %0";
2537 switch (get_attr_mode (insn))
2540 return "movaps\t{%1, %0|%0, %1}";
2542 return "movapd\t{%1, %0|%0, %1}";
2544 return "movsd\t{%1, %0|%0, %1}";
2549 if (get_attr_mode (insn) == MODE_V2DF)
2550 return "movlpd\t{%1, %0|%0, %1}";
2552 return "movsd\t{%1, %0|%0, %1}";
2554 return "movsd\t{%1, %0|%0, %1}";
2560 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2562 (cond [(eq_attr "alternative" "3,4")
2564 /* xorps is one byte shorter. */
2565 (eq_attr "alternative" "5")
2566 (cond [(ne (symbol_ref "optimize_size")
2568 (const_string "V4SF")
2569 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2571 (const_string "TI")]
2572 (const_string "V2DF"))
2573 /* For architectures resolving dependencies on
2574 whole SSE registers use APD move to break dependency
2575 chains, otherwise use short move to avoid extra work.
2577 movaps encodes one byte shorter. */
2578 (eq_attr "alternative" "6")
2580 [(ne (symbol_ref "optimize_size")
2582 (const_string "V4SF")
2583 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2585 (const_string "V2DF")]
2586 (const_string "DF"))
2587 /* For architectures resolving dependencies on register
2588 parts we may avoid extra work to zero out upper part
2590 (eq_attr "alternative" "7")
2592 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2594 (const_string "V2DF")
2595 (const_string "DF"))]
2596 (const_string "DF")))])
2598 (define_insn "*movdf_integer"
2599 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2600 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2601 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2602 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2603 && (reload_in_progress || reload_completed
2604 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2605 || GET_CODE (operands[1]) != CONST_DOUBLE
2606 || memory_operand (operands[0], DFmode))"
2608 switch (which_alternative)
2611 if (REG_P (operands[1])
2612 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2614 if (REGNO (operands[0]) == FIRST_STACK_REG
2615 && TARGET_USE_FFREEP)
2616 return "ffreep\t%y0";
2619 else if (STACK_TOP_P (operands[0]))
2620 return "fld%z1\t%y1";
2625 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2626 return "fstp%z0\t%y0";
2628 return "fst%z0\t%y0";
2631 return standard_80387_constant_opcode (operands[1]);
2638 switch (get_attr_mode (insn))
2641 return "xorps\t%0, %0";
2643 return "xorpd\t%0, %0";
2645 return "pxor\t%0, %0";
2650 switch (get_attr_mode (insn))
2653 return "movaps\t{%1, %0|%0, %1}";
2655 return "movapd\t{%1, %0|%0, %1}";
2657 return "movsd\t{%1, %0|%0, %1}";
2662 if (get_attr_mode (insn) == MODE_V2DF)
2663 return "movlpd\t{%1, %0|%0, %1}";
2665 return "movsd\t{%1, %0|%0, %1}";
2667 return "movsd\t{%1, %0|%0, %1}";
2673 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2675 (cond [(eq_attr "alternative" "3,4")
2677 /* xorps is one byte shorter. */
2678 (eq_attr "alternative" "5")
2679 (cond [(ne (symbol_ref "optimize_size")
2681 (const_string "V4SF")
2682 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2684 (const_string "TI")]
2685 (const_string "V2DF"))
2686 /* For architectures resolving dependencies on
2687 whole SSE registers use APD move to break dependency
2688 chains, otherwise use short move to avoid extra work.
2690 movaps encodes one byte shorter. */
2691 (eq_attr "alternative" "6")
2693 [(ne (symbol_ref "optimize_size")
2695 (const_string "V4SF")
2696 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2698 (const_string "V2DF")]
2699 (const_string "DF"))
2700 /* For architectures resolving dependencies on register
2701 parts we may avoid extra work to zero out upper part
2703 (eq_attr "alternative" "7")
2705 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2707 (const_string "V2DF")
2708 (const_string "DF"))]
2709 (const_string "DF")))])
2712 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2713 (match_operand:DF 1 "general_operand" ""))]
2715 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2716 && ! (ANY_FP_REG_P (operands[0]) ||
2717 (GET_CODE (operands[0]) == SUBREG
2718 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2719 && ! (ANY_FP_REG_P (operands[1]) ||
2720 (GET_CODE (operands[1]) == SUBREG
2721 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2723 "ix86_split_long_move (operands); DONE;")
2725 (define_insn "*swapdf"
2726 [(set (match_operand:DF 0 "register_operand" "+f")
2727 (match_operand:DF 1 "register_operand" "+f"))
2730 "reload_completed || !TARGET_SSE2"
2732 if (STACK_TOP_P (operands[0]))
2737 [(set_attr "type" "fxch")
2738 (set_attr "mode" "DF")])
2740 (define_expand "movxf"
2741 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2742 (match_operand:XF 1 "general_operand" ""))]
2744 "ix86_expand_move (XFmode, operands); DONE;")
2746 (define_expand "movtf"
2747 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2748 (match_operand:TF 1 "general_operand" ""))]
2750 "ix86_expand_move (TFmode, operands); DONE;")
2752 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2753 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2754 ;; Pushing using integer instructions is longer except for constants
2755 ;; and direct memory references.
2756 ;; (assuming that any given constant is pushed only once, but this ought to be
2757 ;; handled elsewhere).
2759 (define_insn "*pushxf_nointeger"
2760 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2761 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2762 "!TARGET_64BIT && optimize_size"
2764 /* This insn should be already splitted before reg-stack. */
2767 [(set_attr "type" "multi")
2768 (set_attr "mode" "XF,SI,SI")])
2770 (define_insn "*pushtf_nointeger"
2771 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2772 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2775 /* This insn should be already splitted before reg-stack. */
2778 [(set_attr "type" "multi")
2779 (set_attr "mode" "XF,SI,SI")])
2781 (define_insn "*pushxf_integer"
2782 [(set (match_operand:XF 0 "push_operand" "=<,<")
2783 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2784 "!TARGET_64BIT && !optimize_size"
2786 /* This insn should be already splitted before reg-stack. */
2789 [(set_attr "type" "multi")
2790 (set_attr "mode" "XF,SI")])
2792 (define_insn "*pushtf_integer"
2793 [(set (match_operand:TF 0 "push_operand" "=<,<")
2794 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2797 /* This insn should be already splitted before reg-stack. */
2800 [(set_attr "type" "multi")
2801 (set_attr "mode" "XF,SI")])
2804 [(set (match_operand 0 "push_operand" "")
2805 (match_operand 1 "general_operand" ""))]
2807 && (GET_MODE (operands[0]) == XFmode
2808 || GET_MODE (operands[0]) == TFmode
2809 || GET_MODE (operands[0]) == DFmode)
2810 && !ANY_FP_REG_P (operands[1])"
2812 "ix86_split_long_move (operands); DONE;")
2815 [(set (match_operand:XF 0 "push_operand" "")
2816 (match_operand:XF 1 "any_fp_register_operand" ""))]
2818 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2819 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2822 [(set (match_operand:TF 0 "push_operand" "")
2823 (match_operand:TF 1 "any_fp_register_operand" ""))]
2825 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2826 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2829 [(set (match_operand:TF 0 "push_operand" "")
2830 (match_operand:TF 1 "any_fp_register_operand" ""))]
2832 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2833 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2835 ;; Do not use integer registers when optimizing for size
2836 (define_insn "*movxf_nointeger"
2837 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2838 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2841 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2842 && (reload_in_progress || reload_completed
2843 || GET_CODE (operands[1]) != CONST_DOUBLE
2844 || memory_operand (operands[0], XFmode))"
2846 switch (which_alternative)
2849 if (REG_P (operands[1])
2850 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2852 if (REGNO (operands[0]) == FIRST_STACK_REG
2853 && TARGET_USE_FFREEP)
2854 return "ffreep\t%y0";
2857 else if (STACK_TOP_P (operands[0]))
2858 return "fld%z1\t%y1";
2863 /* There is no non-popping store to memory for XFmode. So if
2864 we need one, follow the store with a load. */
2865 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2866 return "fstp%z0\t%y0\;fld%z0\t%y0";
2868 return "fstp%z0\t%y0";
2871 return standard_80387_constant_opcode (operands[1]);
2878 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2879 (set_attr "mode" "XF,XF,XF,SI,SI")])
2881 (define_insn "*movtf_nointeger"
2882 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2883 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2884 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2886 && (reload_in_progress || reload_completed
2887 || GET_CODE (operands[1]) != CONST_DOUBLE
2888 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2889 || memory_operand (operands[0], TFmode))"
2891 switch (which_alternative)
2894 if (REG_P (operands[1])
2895 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2897 if (REGNO (operands[0]) == FIRST_STACK_REG
2898 && TARGET_USE_FFREEP)
2899 return "ffreep\t%y0";
2902 else if (STACK_TOP_P (operands[0]))
2903 return "fld%z1\t%y1";
2908 /* There is no non-popping store to memory for XFmode. So if
2909 we need one, follow the store with a load. */
2910 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2911 return "fstp%z0\t%y0\;fld%z0\t%y0";
2913 return "fstp%z0\t%y0";
2916 return standard_80387_constant_opcode (operands[1]);
2923 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2924 (set_attr "mode" "XF,XF,XF,SI,SI")])
2926 (define_insn "*movxf_integer"
2927 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2928 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2931 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2932 && (reload_in_progress || reload_completed
2933 || GET_CODE (operands[1]) != CONST_DOUBLE
2934 || memory_operand (operands[0], XFmode))"
2936 switch (which_alternative)
2939 if (REG_P (operands[1])
2940 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2942 if (REGNO (operands[0]) == FIRST_STACK_REG
2943 && TARGET_USE_FFREEP)
2944 return "ffreep\t%y0";
2947 else if (STACK_TOP_P (operands[0]))
2948 return "fld%z1\t%y1";
2953 /* There is no non-popping store to memory for XFmode. So if
2954 we need one, follow the store with a load. */
2955 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2956 return "fstp%z0\t%y0\;fld%z0\t%y0";
2958 return "fstp%z0\t%y0";
2961 return standard_80387_constant_opcode (operands[1]);
2968 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2969 (set_attr "mode" "XF,XF,XF,SI,SI")])
2971 (define_insn "*movtf_integer"
2972 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2973 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2974 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2976 && (reload_in_progress || reload_completed
2977 || GET_CODE (operands[1]) != CONST_DOUBLE
2978 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2979 || memory_operand (operands[0], TFmode))"
2981 switch (which_alternative)
2984 if (REG_P (operands[1])
2985 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2987 if (REGNO (operands[0]) == FIRST_STACK_REG
2988 && TARGET_USE_FFREEP)
2989 return "ffreep\t%y0";
2992 else if (STACK_TOP_P (operands[0]))
2993 return "fld%z1\t%y1";
2998 /* There is no non-popping store to memory for XFmode. So if
2999 we need one, follow the store with a load. */
3000 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3001 return "fstp%z0\t%y0\;fld%z0\t%y0";
3003 return "fstp%z0\t%y0";
3006 return standard_80387_constant_opcode (operands[1]);
3013 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3014 (set_attr "mode" "XF,XF,XF,SI,SI")])
3017 [(set (match_operand 0 "nonimmediate_operand" "")
3018 (match_operand 1 "general_operand" ""))]
3020 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3021 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3022 && ! (ANY_FP_REG_P (operands[0]) ||
3023 (GET_CODE (operands[0]) == SUBREG
3024 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3025 && ! (ANY_FP_REG_P (operands[1]) ||
3026 (GET_CODE (operands[1]) == SUBREG
3027 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3029 "ix86_split_long_move (operands); DONE;")
3032 [(set (match_operand 0 "register_operand" "")
3033 (match_operand 1 "memory_operand" ""))]
3035 && GET_CODE (operands[1]) == MEM
3036 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3037 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3038 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3039 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3040 && (!(SSE_REG_P (operands[0]) ||
3041 (GET_CODE (operands[0]) == SUBREG
3042 && SSE_REG_P (SUBREG_REG (operands[0]))))
3043 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3044 && (!(FP_REG_P (operands[0]) ||
3045 (GET_CODE (operands[0]) == SUBREG
3046 && FP_REG_P (SUBREG_REG (operands[0]))))
3047 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3050 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3052 (define_insn "swapxf"
3053 [(set (match_operand:XF 0 "register_operand" "+f")
3054 (match_operand:XF 1 "register_operand" "+f"))
3059 if (STACK_TOP_P (operands[0]))
3064 [(set_attr "type" "fxch")
3065 (set_attr "mode" "XF")])
3067 (define_insn "swaptf"
3068 [(set (match_operand:TF 0 "register_operand" "+f")
3069 (match_operand:TF 1 "register_operand" "+f"))
3074 if (STACK_TOP_P (operands[0]))
3079 [(set_attr "type" "fxch")
3080 (set_attr "mode" "XF")])
3082 ;; Zero extension instructions
3084 (define_expand "zero_extendhisi2"
3085 [(set (match_operand:SI 0 "register_operand" "")
3086 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3089 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3091 operands[1] = force_reg (HImode, operands[1]);
3092 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3097 (define_insn "zero_extendhisi2_and"
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3100 (clobber (reg:CC 17))]
3101 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3103 [(set_attr "type" "alu1")
3104 (set_attr "mode" "SI")])
3107 [(set (match_operand:SI 0 "register_operand" "")
3108 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3109 (clobber (reg:CC 17))]
3110 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3111 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3112 (clobber (reg:CC 17))])]
3115 (define_insn "*zero_extendhisi2_movzwl"
3116 [(set (match_operand:SI 0 "register_operand" "=r")
3117 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3118 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3119 "movz{wl|x}\t{%1, %0|%0, %1}"
3120 [(set_attr "type" "imovx")
3121 (set_attr "mode" "SI")])
3123 (define_expand "zero_extendqihi2"
3125 [(set (match_operand:HI 0 "register_operand" "")
3126 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3127 (clobber (reg:CC 17))])]
3131 (define_insn "*zero_extendqihi2_and"
3132 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3133 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3134 (clobber (reg:CC 17))]
3135 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3137 [(set_attr "type" "alu1")
3138 (set_attr "mode" "HI")])
3140 (define_insn "*zero_extendqihi2_movzbw_and"
3141 [(set (match_operand:HI 0 "register_operand" "=r,r")
3142 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3143 (clobber (reg:CC 17))]
3144 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3146 [(set_attr "type" "imovx,alu1")
3147 (set_attr "mode" "HI")])
3149 (define_insn "*zero_extendqihi2_movzbw"
3150 [(set (match_operand:HI 0 "register_operand" "=r")
3151 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3152 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3153 "movz{bw|x}\t{%1, %0|%0, %1}"
3154 [(set_attr "type" "imovx")
3155 (set_attr "mode" "HI")])
3157 ;; For the movzbw case strip only the clobber
3159 [(set (match_operand:HI 0 "register_operand" "")
3160 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3161 (clobber (reg:CC 17))]
3163 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3164 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3165 [(set (match_operand:HI 0 "register_operand" "")
3166 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3168 ;; When source and destination does not overlap, clear destination
3169 ;; first and then do the movb
3171 [(set (match_operand:HI 0 "register_operand" "")
3172 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3173 (clobber (reg:CC 17))]
3175 && ANY_QI_REG_P (operands[0])
3176 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3177 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3178 [(set (match_dup 0) (const_int 0))
3179 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3180 "operands[2] = gen_lowpart (QImode, operands[0]);")
3182 ;; Rest is handled by single and.
3184 [(set (match_operand:HI 0 "register_operand" "")
3185 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3186 (clobber (reg:CC 17))]
3188 && true_regnum (operands[0]) == true_regnum (operands[1])"
3189 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3190 (clobber (reg:CC 17))])]
3193 (define_expand "zero_extendqisi2"
3195 [(set (match_operand:SI 0 "register_operand" "")
3196 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3197 (clobber (reg:CC 17))])]
3201 (define_insn "*zero_extendqisi2_and"
3202 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3203 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3204 (clobber (reg:CC 17))]
3205 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3207 [(set_attr "type" "alu1")
3208 (set_attr "mode" "SI")])
3210 (define_insn "*zero_extendqisi2_movzbw_and"
3211 [(set (match_operand:SI 0 "register_operand" "=r,r")
3212 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3213 (clobber (reg:CC 17))]
3214 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3216 [(set_attr "type" "imovx,alu1")
3217 (set_attr "mode" "SI")])
3219 (define_insn "*zero_extendqisi2_movzbw"
3220 [(set (match_operand:SI 0 "register_operand" "=r")
3221 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3222 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3223 "movz{bl|x}\t{%1, %0|%0, %1}"
3224 [(set_attr "type" "imovx")
3225 (set_attr "mode" "SI")])
3227 ;; For the movzbl case strip only the clobber
3229 [(set (match_operand:SI 0 "register_operand" "")
3230 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3231 (clobber (reg:CC 17))]
3233 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3234 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3236 (zero_extend:SI (match_dup 1)))])
3238 ;; When source and destination does not overlap, clear destination
3239 ;; first and then do the movb
3241 [(set (match_operand:SI 0 "register_operand" "")
3242 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3243 (clobber (reg:CC 17))]
3245 && ANY_QI_REG_P (operands[0])
3246 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3247 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3248 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3249 [(set (match_dup 0) (const_int 0))
3250 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3251 "operands[2] = gen_lowpart (QImode, operands[0]);")
3253 ;; Rest is handled by single and.
3255 [(set (match_operand:SI 0 "register_operand" "")
3256 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3257 (clobber (reg:CC 17))]
3259 && true_regnum (operands[0]) == true_regnum (operands[1])"
3260 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3261 (clobber (reg:CC 17))])]
3264 ;; %%% Kill me once multi-word ops are sane.
3265 (define_expand "zero_extendsidi2"
3266 [(set (match_operand:DI 0 "register_operand" "=r")
3267 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3271 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3276 (define_insn "zero_extendsidi2_32"
3277 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3278 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3279 (clobber (reg:CC 17))]
3282 [(set_attr "mode" "SI")])
3284 (define_insn "zero_extendsidi2_rex64"
3285 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3286 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3289 mov\t{%k1, %k0|%k0, %k1}
3291 [(set_attr "type" "imovx,imov")
3292 (set_attr "mode" "SI,DI")])
3295 [(set (match_operand:DI 0 "memory_operand" "")
3296 (zero_extend:DI (match_dup 0)))]
3298 [(set (match_dup 4) (const_int 0))]
3299 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3302 [(set (match_operand:DI 0 "register_operand" "")
3303 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3304 (clobber (reg:CC 17))]
3305 "!TARGET_64BIT && reload_completed
3306 && true_regnum (operands[0]) == true_regnum (operands[1])"
3307 [(set (match_dup 4) (const_int 0))]
3308 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3311 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3312 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3313 (clobber (reg:CC 17))]
3314 "!TARGET_64BIT && reload_completed"
3315 [(set (match_dup 3) (match_dup 1))
3316 (set (match_dup 4) (const_int 0))]
3317 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3319 (define_insn "zero_extendhidi2"
3320 [(set (match_operand:DI 0 "register_operand" "=r,r")
3321 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3324 movz{wl|x}\t{%1, %k0|%k0, %1}
3325 movz{wq|x}\t{%1, %0|%0, %1}"
3326 [(set_attr "type" "imovx")
3327 (set_attr "mode" "SI,DI")])
3329 (define_insn "zero_extendqidi2"
3330 [(set (match_operand:DI 0 "register_operand" "=r,r")
3331 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3334 movz{bl|x}\t{%1, %k0|%k0, %1}
3335 movz{bq|x}\t{%1, %0|%0, %1}"
3336 [(set_attr "type" "imovx")
3337 (set_attr "mode" "SI,DI")])
3339 ;; Sign extension instructions
3341 (define_expand "extendsidi2"
3342 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3343 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3344 (clobber (reg:CC 17))
3345 (clobber (match_scratch:SI 2 ""))])]
3350 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3355 (define_insn "*extendsidi2_1"
3356 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3357 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3358 (clobber (reg:CC 17))
3359 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3363 (define_insn "extendsidi2_rex64"
3364 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3365 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3369 movs{lq|x}\t{%1,%0|%0, %1}"
3370 [(set_attr "type" "imovx")
3371 (set_attr "mode" "DI")
3372 (set_attr "prefix_0f" "0")
3373 (set_attr "modrm" "0,1")])
3375 (define_insn "extendhidi2"
3376 [(set (match_operand:DI 0 "register_operand" "=r")
3377 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3379 "movs{wq|x}\t{%1,%0|%0, %1}"
3380 [(set_attr "type" "imovx")
3381 (set_attr "mode" "DI")])
3383 (define_insn "extendqidi2"
3384 [(set (match_operand:DI 0 "register_operand" "=r")
3385 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3387 "movs{bq|x}\t{%1,%0|%0, %1}"
3388 [(set_attr "type" "imovx")
3389 (set_attr "mode" "DI")])
3391 ;; Extend to memory case when source register does die.
3393 [(set (match_operand:DI 0 "memory_operand" "")
3394 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3395 (clobber (reg:CC 17))
3396 (clobber (match_operand:SI 2 "register_operand" ""))]
3398 && dead_or_set_p (insn, operands[1])
3399 && !reg_mentioned_p (operands[1], operands[0]))"
3400 [(set (match_dup 3) (match_dup 1))
3401 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3402 (clobber (reg:CC 17))])
3403 (set (match_dup 4) (match_dup 1))]
3404 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3406 ;; Extend to memory case when source register does not die.
3408 [(set (match_operand:DI 0 "memory_operand" "")
3409 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3410 (clobber (reg:CC 17))
3411 (clobber (match_operand:SI 2 "register_operand" ""))]
3415 split_di (&operands[0], 1, &operands[3], &operands[4]);
3417 emit_move_insn (operands[3], operands[1]);
3419 /* Generate a cltd if possible and doing so it profitable. */
3420 if (true_regnum (operands[1]) == 0
3421 && true_regnum (operands[2]) == 1
3422 && (optimize_size || TARGET_USE_CLTD))
3424 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3428 emit_move_insn (operands[2], operands[1]);
3429 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3431 emit_move_insn (operands[4], operands[2]);
3435 ;; Extend to register case. Optimize case where source and destination
3436 ;; registers match and cases where we can use cltd.
3438 [(set (match_operand:DI 0 "register_operand" "")
3439 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3440 (clobber (reg:CC 17))
3441 (clobber (match_scratch:SI 2 ""))]
3445 split_di (&operands[0], 1, &operands[3], &operands[4]);
3447 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3448 emit_move_insn (operands[3], operands[1]);
3450 /* Generate a cltd if possible and doing so it profitable. */
3451 if (true_regnum (operands[3]) == 0
3452 && (optimize_size || TARGET_USE_CLTD))
3454 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3458 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3459 emit_move_insn (operands[4], operands[1]);
3461 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3465 (define_insn "extendhisi2"
3466 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3467 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3470 switch (get_attr_prefix_0f (insn))
3473 return "{cwtl|cwde}";
3475 return "movs{wl|x}\t{%1,%0|%0, %1}";
3478 [(set_attr "type" "imovx")
3479 (set_attr "mode" "SI")
3480 (set (attr "prefix_0f")
3481 ;; movsx is short decodable while cwtl is vector decoded.
3482 (if_then_else (and (eq_attr "cpu" "!k6")
3483 (eq_attr "alternative" "0"))
3485 (const_string "1")))
3487 (if_then_else (eq_attr "prefix_0f" "0")
3489 (const_string "1")))])
3491 (define_insn "*extendhisi2_zext"
3492 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3494 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3497 switch (get_attr_prefix_0f (insn))
3500 return "{cwtl|cwde}";
3502 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3505 [(set_attr "type" "imovx")
3506 (set_attr "mode" "SI")
3507 (set (attr "prefix_0f")
3508 ;; movsx is short decodable while cwtl is vector decoded.
3509 (if_then_else (and (eq_attr "cpu" "!k6")
3510 (eq_attr "alternative" "0"))
3512 (const_string "1")))
3514 (if_then_else (eq_attr "prefix_0f" "0")
3516 (const_string "1")))])
3518 (define_insn "extendqihi2"
3519 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3520 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3523 switch (get_attr_prefix_0f (insn))
3526 return "{cbtw|cbw}";
3528 return "movs{bw|x}\t{%1,%0|%0, %1}";
3531 [(set_attr "type" "imovx")
3532 (set_attr "mode" "HI")
3533 (set (attr "prefix_0f")
3534 ;; movsx is short decodable while cwtl is vector decoded.
3535 (if_then_else (and (eq_attr "cpu" "!k6")
3536 (eq_attr "alternative" "0"))
3538 (const_string "1")))
3540 (if_then_else (eq_attr "prefix_0f" "0")
3542 (const_string "1")))])
3544 (define_insn "extendqisi2"
3545 [(set (match_operand:SI 0 "register_operand" "=r")
3546 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3548 "movs{bl|x}\t{%1,%0|%0, %1}"
3549 [(set_attr "type" "imovx")
3550 (set_attr "mode" "SI")])
3552 (define_insn "*extendqisi2_zext"
3553 [(set (match_operand:DI 0 "register_operand" "=r")
3555 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3557 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3558 [(set_attr "type" "imovx")
3559 (set_attr "mode" "SI")])
3561 ;; Conversions between float and double.
3563 ;; These are all no-ops in the model used for the 80387. So just
3566 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3567 (define_insn "*dummy_extendsfdf2"
3568 [(set (match_operand:DF 0 "push_operand" "=<")
3569 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3574 [(set (match_operand:DF 0 "push_operand" "")
3575 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3577 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3578 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3581 [(set (match_operand:DF 0 "push_operand" "")
3582 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3584 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3585 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3587 (define_insn "*dummy_extendsfxf2"
3588 [(set (match_operand:XF 0 "push_operand" "=<")
3589 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3594 [(set (match_operand:XF 0 "push_operand" "")
3595 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3597 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3598 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3600 (define_insn "*dummy_extendsftf2"
3601 [(set (match_operand:TF 0 "push_operand" "=<")
3602 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3607 [(set (match_operand:TF 0 "push_operand" "")
3608 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3610 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3611 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3614 [(set (match_operand:TF 0 "push_operand" "")
3615 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3617 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3618 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3620 (define_insn "*dummy_extenddfxf2"
3621 [(set (match_operand:XF 0 "push_operand" "=<")
3622 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3627 [(set (match_operand:XF 0 "push_operand" "")
3628 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3630 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3631 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3633 (define_insn "*dummy_extenddftf2"
3634 [(set (match_operand:TF 0 "push_operand" "=<")
3635 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3640 [(set (match_operand:TF 0 "push_operand" "")
3641 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3643 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3644 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3647 [(set (match_operand:TF 0 "push_operand" "")
3648 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3650 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3651 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3653 (define_expand "extendsfdf2"
3654 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3655 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3656 "TARGET_80387 || TARGET_SSE2"
3658 /* ??? Needed for compress_float_constant since all fp constants
3659 are LEGITIMATE_CONSTANT_P. */
3660 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3661 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3662 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3663 operands[1] = force_reg (SFmode, operands[1]);
3666 (define_insn "*extendsfdf2_1"
3667 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3668 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3669 "(TARGET_80387 || TARGET_SSE2)
3670 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3672 switch (which_alternative)
3675 if (REG_P (operands[1])
3676 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3678 else if (STACK_TOP_P (operands[0]))
3679 return "fld%z1\t%y1";
3684 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3685 return "fstp%z0\t%y0";
3688 return "fst%z0\t%y0";
3690 return "cvtss2sd\t{%1, %0|%0, %1}";
3696 [(set_attr "type" "fmov,fmov,ssecvt")
3697 (set_attr "mode" "SF,XF,DF")])
3699 (define_insn "*extendsfdf2_1_sse_only"
3700 [(set (match_operand:DF 0 "register_operand" "=Y")
3701 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3702 "!TARGET_80387 && TARGET_SSE2
3703 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3704 "cvtss2sd\t{%1, %0|%0, %1}"
3705 [(set_attr "type" "ssecvt")
3706 (set_attr "mode" "DF")])
3708 (define_expand "extendsfxf2"
3709 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3710 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3711 "!TARGET_64BIT && TARGET_80387"
3713 /* ??? Needed for compress_float_constant since all fp constants
3714 are LEGITIMATE_CONSTANT_P. */
3715 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3716 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3717 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3718 operands[1] = force_reg (SFmode, operands[1]);
3721 (define_insn "*extendsfxf2_1"
3722 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3723 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3724 "!TARGET_64BIT && TARGET_80387
3725 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3727 switch (which_alternative)
3730 if (REG_P (operands[1])
3731 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3733 else if (STACK_TOP_P (operands[0]))
3734 return "fld%z1\t%y1";
3739 /* There is no non-popping store to memory for XFmode. So if
3740 we need one, follow the store with a load. */
3741 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3742 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3744 return "fstp%z0\t%y0";
3750 [(set_attr "type" "fmov")
3751 (set_attr "mode" "SF,XF")])
3753 (define_expand "extendsftf2"
3754 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3755 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3758 /* ??? Needed for compress_float_constant since all fp constants
3759 are LEGITIMATE_CONSTANT_P. */
3760 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3761 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3762 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3763 operands[1] = force_reg (SFmode, operands[1]);
3766 (define_insn "*extendsftf2_1"
3767 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3768 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3770 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3772 switch (which_alternative)
3775 if (REG_P (operands[1])
3776 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3778 else if (STACK_TOP_P (operands[0]))
3779 return "fld%z1\t%y1";
3784 /* There is no non-popping store to memory for XFmode. So if
3785 we need one, follow the store with a load. */
3786 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3787 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3789 return "fstp%z0\t%y0";
3795 [(set_attr "type" "fmov")
3796 (set_attr "mode" "SF,XF")])
3798 (define_expand "extenddfxf2"
3799 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3800 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3801 "!TARGET_64BIT && TARGET_80387"
3803 /* ??? Needed for compress_float_constant since all fp constants
3804 are LEGITIMATE_CONSTANT_P. */
3805 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3806 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3807 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3808 operands[1] = force_reg (DFmode, operands[1]);
3811 (define_insn "*extenddfxf2_1"
3812 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3813 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3814 "!TARGET_64BIT && TARGET_80387
3815 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3817 switch (which_alternative)
3820 if (REG_P (operands[1])
3821 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3823 else if (STACK_TOP_P (operands[0]))
3824 return "fld%z1\t%y1";
3829 /* There is no non-popping store to memory for XFmode. So if
3830 we need one, follow the store with a load. */
3831 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3832 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3834 return "fstp%z0\t%y0";
3840 [(set_attr "type" "fmov")
3841 (set_attr "mode" "DF,XF")])
3843 (define_expand "extenddftf2"
3844 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3845 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3848 /* ??? Needed for compress_float_constant since all fp constants
3849 are LEGITIMATE_CONSTANT_P. */
3850 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3851 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3852 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3853 operands[1] = force_reg (DFmode, operands[1]);
3856 (define_insn "*extenddftf2_1"
3857 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3858 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3860 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3862 switch (which_alternative)
3865 if (REG_P (operands[1])
3866 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3868 else if (STACK_TOP_P (operands[0]))
3869 return "fld%z1\t%y1";
3874 /* There is no non-popping store to memory for XFmode. So if
3875 we need one, follow the store with a load. */
3876 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3877 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3879 return "fstp%z0\t%y0";
3885 [(set_attr "type" "fmov")
3886 (set_attr "mode" "DF,XF")])
3888 ;; %%% This seems bad bad news.
3889 ;; This cannot output into an f-reg because there is no way to be sure
3890 ;; of truncating in that case. Otherwise this is just like a simple move
3891 ;; insn. So we pretend we can output to a reg in order to get better
3892 ;; register preferencing, but we really use a stack slot.
3894 (define_expand "truncdfsf2"
3895 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3897 (match_operand:DF 1 "register_operand" "")))
3898 (clobber (match_dup 2))])]
3899 "TARGET_80387 || TARGET_SSE2"
3902 operands[2] = assign_386_stack_local (SFmode, 0);
3905 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3910 (define_insn "*truncdfsf2_1"
3911 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3913 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3914 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3915 "TARGET_80387 && !TARGET_SSE2"
3917 switch (which_alternative)
3920 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3921 return "fstp%z0\t%y0";
3923 return "fst%z0\t%y0";
3928 [(set_attr "type" "fmov,multi,multi,multi")
3929 (set_attr "mode" "SF,SF,SF,SF")])
3931 (define_insn "*truncdfsf2_1_sse"
3932 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3934 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3935 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3936 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3938 switch (which_alternative)
3941 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3942 return "fstp%z0\t%y0";
3944 return "fst%z0\t%y0";
3951 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3952 (set_attr "mode" "SF,SF,SF,SF,DF")])
3954 (define_insn "*truncdfsf2_1_sse_nooverlap"
3955 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3957 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3958 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3959 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3961 switch (which_alternative)
3964 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3965 return "fstp%z0\t%y0";
3967 return "fst%z0\t%y0";
3974 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3975 (set_attr "mode" "SF,SF,SF,SF,DF")])
3977 (define_insn "*truncdfsf2_2"
3978 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3980 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3981 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3982 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3984 switch (which_alternative)
3988 return "cvtsd2ss\t{%1, %0|%0, %1}";
3990 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3991 return "fstp%z0\t%y0";
3993 return "fst%z0\t%y0";
3998 [(set_attr "type" "ssecvt,ssecvt,fmov")
3999 (set_attr "athlon_decode" "vector,double,*")
4000 (set_attr "mode" "SF,SF,SF")])
4002 (define_insn "*truncdfsf2_2_nooverlap"
4003 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
4005 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4006 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
4007 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4009 switch (which_alternative)
4014 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4015 return "fstp%z0\t%y0";
4017 return "fst%z0\t%y0";
4022 [(set_attr "type" "ssecvt,fmov")
4023 (set_attr "mode" "DF,SF")])
4025 (define_insn "*truncdfsf2_3"
4026 [(set (match_operand:SF 0 "memory_operand" "=m")
4028 (match_operand:DF 1 "register_operand" "f")))]
4031 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4032 return "fstp%z0\t%y0";
4034 return "fst%z0\t%y0";
4036 [(set_attr "type" "fmov")
4037 (set_attr "mode" "SF")])
4039 (define_insn "truncdfsf2_sse_only"
4040 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
4042 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
4043 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4044 "cvtsd2ss\t{%1, %0|%0, %1}"
4045 [(set_attr "type" "ssecvt")
4046 (set_attr "athlon_decode" "vector,double")
4047 (set_attr "mode" "SF")])
4049 (define_insn "*truncdfsf2_sse_only_nooverlap"
4050 [(set (match_operand:SF 0 "register_operand" "=&Y")
4052 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4053 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4055 [(set_attr "type" "ssecvt")
4056 (set_attr "mode" "DF")])
4059 [(set (match_operand:SF 0 "memory_operand" "")
4061 (match_operand:DF 1 "register_operand" "")))
4062 (clobber (match_operand:SF 2 "memory_operand" ""))]
4064 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4067 ; Avoid possible reformatting penalty on the destination by first
4070 [(set (match_operand:SF 0 "register_operand" "")
4072 (match_operand:DF 1 "nonimmediate_operand" "")))
4073 (clobber (match_operand 2 "" ""))]
4074 "TARGET_80387 && reload_completed
4075 && SSE_REG_P (operands[0])
4076 && !STACK_REG_P (operands[1])"
4080 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
4081 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4084 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4085 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4086 /* simplify_gen_subreg refuses to widen memory references. */
4087 if (GET_CODE (src) == SUBREG)
4088 alter_subreg (&src);
4089 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4091 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4092 emit_insn (gen_cvtsd2ss (dest, dest, src));
4098 [(set (match_operand:SF 0 "register_operand" "")
4100 (match_operand:DF 1 "nonimmediate_operand" "")))]
4101 "TARGET_80387 && reload_completed
4102 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4106 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4107 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4108 /* simplify_gen_subreg refuses to widen memory references. */
4109 if (GET_CODE (src) == SUBREG)
4110 alter_subreg (&src);
4111 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4113 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4114 emit_insn (gen_cvtsd2ss (dest, dest, src));
4119 [(set (match_operand:SF 0 "register_operand" "")
4121 (match_operand:DF 1 "fp_register_operand" "")))
4122 (clobber (match_operand:SF 2 "memory_operand" ""))]
4123 "TARGET_80387 && reload_completed"
4124 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4125 (set (match_dup 0) (match_dup 2))]
4128 (define_expand "truncxfsf2"
4129 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4131 (match_operand:XF 1 "register_operand" "")))
4132 (clobber (match_dup 2))])]
4133 "!TARGET_64BIT && TARGET_80387"
4134 "operands[2] = assign_386_stack_local (SFmode, 0);")
4136 (define_insn "*truncxfsf2_1"
4137 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4139 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4140 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4141 "!TARGET_64BIT && TARGET_80387"
4143 switch (which_alternative)
4146 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4147 return "fstp%z0\t%y0";
4149 return "fst%z0\t%y0";
4154 [(set_attr "type" "fmov,multi,multi,multi")
4155 (set_attr "mode" "SF")])
4157 (define_insn "*truncxfsf2_2"
4158 [(set (match_operand:SF 0 "memory_operand" "=m")
4160 (match_operand:XF 1 "register_operand" "f")))]
4161 "!TARGET_64BIT && TARGET_80387"
4163 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4164 return "fstp%z0\t%y0";
4166 return "fst%z0\t%y0";
4168 [(set_attr "type" "fmov")
4169 (set_attr "mode" "SF")])
4172 [(set (match_operand:SF 0 "memory_operand" "")
4174 (match_operand:XF 1 "register_operand" "")))
4175 (clobber (match_operand:SF 2 "memory_operand" ""))]
4177 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4181 [(set (match_operand:SF 0 "register_operand" "")
4183 (match_operand:XF 1 "register_operand" "")))
4184 (clobber (match_operand:SF 2 "memory_operand" ""))]
4185 "TARGET_80387 && reload_completed"
4186 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4187 (set (match_dup 0) (match_dup 2))]
4190 (define_expand "trunctfsf2"
4191 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4193 (match_operand:TF 1 "register_operand" "")))
4194 (clobber (match_dup 2))])]
4196 "operands[2] = assign_386_stack_local (SFmode, 0);")
4198 (define_insn "*trunctfsf2_1"
4199 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4201 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4202 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4205 switch (which_alternative)
4208 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4209 return "fstp%z0\t%y0";
4211 return "fst%z0\t%y0";
4216 [(set_attr "type" "fmov,multi,multi,multi")
4217 (set_attr "mode" "SF")])
4219 (define_insn "*trunctfsf2_2"
4220 [(set (match_operand:SF 0 "memory_operand" "=m")
4222 (match_operand:TF 1 "register_operand" "f")))]
4225 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4226 return "fstp%z0\t%y0";
4228 return "fst%z0\t%y0";
4230 [(set_attr "type" "fmov")
4231 (set_attr "mode" "SF")])
4234 [(set (match_operand:SF 0 "memory_operand" "")
4236 (match_operand:TF 1 "register_operand" "")))
4237 (clobber (match_operand:SF 2 "memory_operand" ""))]
4239 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4243 [(set (match_operand:SF 0 "register_operand" "")
4245 (match_operand:TF 1 "register_operand" "")))
4246 (clobber (match_operand:SF 2 "memory_operand" ""))]
4247 "TARGET_80387 && reload_completed"
4248 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4249 (set (match_dup 0) (match_dup 2))]
4253 (define_expand "truncxfdf2"
4254 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4256 (match_operand:XF 1 "register_operand" "")))
4257 (clobber (match_dup 2))])]
4258 "!TARGET_64BIT && TARGET_80387"
4259 "operands[2] = assign_386_stack_local (DFmode, 0);")
4261 (define_insn "*truncxfdf2_1"
4262 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4264 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4265 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4266 "!TARGET_64BIT && TARGET_80387"
4268 switch (which_alternative)
4271 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4272 return "fstp%z0\t%y0";
4274 return "fst%z0\t%y0";
4280 [(set_attr "type" "fmov,multi,multi,multi")
4281 (set_attr "mode" "DF")])
4283 (define_insn "*truncxfdf2_2"
4284 [(set (match_operand:DF 0 "memory_operand" "=m")
4286 (match_operand:XF 1 "register_operand" "f")))]
4287 "!TARGET_64BIT && TARGET_80387"
4289 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4290 return "fstp%z0\t%y0";
4292 return "fst%z0\t%y0";
4294 [(set_attr "type" "fmov")
4295 (set_attr "mode" "DF")])
4298 [(set (match_operand:DF 0 "memory_operand" "")
4300 (match_operand:XF 1 "register_operand" "")))
4301 (clobber (match_operand:DF 2 "memory_operand" ""))]
4303 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4307 [(set (match_operand:DF 0 "register_operand" "")
4309 (match_operand:XF 1 "register_operand" "")))
4310 (clobber (match_operand:DF 2 "memory_operand" ""))]
4311 "TARGET_80387 && reload_completed"
4312 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4313 (set (match_dup 0) (match_dup 2))]
4316 (define_expand "trunctfdf2"
4317 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4319 (match_operand:TF 1 "register_operand" "")))
4320 (clobber (match_dup 2))])]
4322 "operands[2] = assign_386_stack_local (DFmode, 0);")
4324 (define_insn "*trunctfdf2_1"
4325 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4327 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4328 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4331 switch (which_alternative)
4334 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4335 return "fstp%z0\t%y0";
4337 return "fst%z0\t%y0";
4343 [(set_attr "type" "fmov,multi,multi,multi")
4344 (set_attr "mode" "DF")])
4346 (define_insn "*trunctfdf2_2"
4347 [(set (match_operand:DF 0 "memory_operand" "=m")
4349 (match_operand:TF 1 "register_operand" "f")))]
4352 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4353 return "fstp%z0\t%y0";
4355 return "fst%z0\t%y0";
4357 [(set_attr "type" "fmov")
4358 (set_attr "mode" "DF")])
4361 [(set (match_operand:DF 0 "memory_operand" "")
4363 (match_operand:TF 1 "register_operand" "")))
4364 (clobber (match_operand:DF 2 "memory_operand" ""))]
4366 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4370 [(set (match_operand:DF 0 "register_operand" "")
4372 (match_operand:TF 1 "register_operand" "")))
4373 (clobber (match_operand:DF 2 "memory_operand" ""))]
4374 "TARGET_80387 && reload_completed"
4375 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4376 (set (match_dup 0) (match_dup 2))]
4380 ;; %%% Break up all these bad boys.
4382 ;; Signed conversion to DImode.
4384 (define_expand "fix_truncxfdi2"
4385 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4386 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4387 "!TARGET_64BIT && TARGET_80387"
4390 (define_expand "fix_trunctfdi2"
4391 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4392 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4396 (define_expand "fix_truncdfdi2"
4397 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4398 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4399 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4401 if (TARGET_64BIT && TARGET_SSE2)
4403 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4404 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4405 if (out != operands[0])
4406 emit_move_insn (operands[0], out);
4411 (define_expand "fix_truncsfdi2"
4412 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4413 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4414 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4416 if (TARGET_SSE && TARGET_64BIT)
4418 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4419 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4420 if (out != operands[0])
4421 emit_move_insn (operands[0], out);
4426 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4427 ;; of the machinery.
4428 (define_insn_and_split "*fix_truncdi_1"
4429 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4430 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4431 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4432 && !reload_completed && !reload_in_progress
4433 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4438 ix86_optimize_mode_switching = 1;
4439 operands[2] = assign_386_stack_local (HImode, 1);
4440 operands[3] = assign_386_stack_local (HImode, 2);
4441 if (memory_operand (operands[0], VOIDmode))
4442 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4443 operands[2], operands[3]));
4446 operands[4] = assign_386_stack_local (DImode, 0);
4447 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4448 operands[2], operands[3],
4453 [(set_attr "type" "fistp")
4454 (set_attr "mode" "DI")])
4456 (define_insn "fix_truncdi_nomemory"
4457 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4458 (fix:DI (match_operand 1 "register_operand" "f,f")))
4459 (use (match_operand:HI 2 "memory_operand" "m,m"))
4460 (use (match_operand:HI 3 "memory_operand" "m,m"))
4461 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4462 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4463 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4464 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4466 [(set_attr "type" "fistp")
4467 (set_attr "mode" "DI")])
4469 (define_insn "fix_truncdi_memory"
4470 [(set (match_operand:DI 0 "memory_operand" "=m")
4471 (fix:DI (match_operand 1 "register_operand" "f")))
4472 (use (match_operand:HI 2 "memory_operand" "m"))
4473 (use (match_operand:HI 3 "memory_operand" "m"))
4474 (clobber (match_scratch:DF 4 "=&1f"))]
4475 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4476 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4477 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4478 [(set_attr "type" "fistp")
4479 (set_attr "mode" "DI")])
4482 [(set (match_operand:DI 0 "register_operand" "")
4483 (fix:DI (match_operand 1 "register_operand" "")))
4484 (use (match_operand:HI 2 "memory_operand" ""))
4485 (use (match_operand:HI 3 "memory_operand" ""))
4486 (clobber (match_operand:DI 4 "memory_operand" ""))
4487 (clobber (match_scratch 5 ""))]
4489 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4492 (clobber (match_dup 5))])
4493 (set (match_dup 0) (match_dup 4))]
4497 [(set (match_operand:DI 0 "memory_operand" "")
4498 (fix:DI (match_operand 1 "register_operand" "")))
4499 (use (match_operand:HI 2 "memory_operand" ""))
4500 (use (match_operand:HI 3 "memory_operand" ""))
4501 (clobber (match_operand:DI 4 "memory_operand" ""))
4502 (clobber (match_scratch 5 ""))]
4504 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4507 (clobber (match_dup 5))])]
4510 ;; When SSE available, it is always faster to use it!
4511 (define_insn "fix_truncsfdi_sse"
4512 [(set (match_operand:DI 0 "register_operand" "=r,r")
4513 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4514 "TARGET_64BIT && TARGET_SSE"
4515 "cvttss2si{q}\t{%1, %0|%0, %1}"
4516 [(set_attr "type" "sseicvt")
4517 (set_attr "mode" "SF")
4518 (set_attr "athlon_decode" "double,vector")])
4520 ;; Avoid vector decoded form of the instruction.
4522 [(match_scratch:SF 2 "x")
4523 (set (match_operand:DI 0 "register_operand" "")
4524 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4525 "TARGET_K8 && !optimize_size"
4526 [(set (match_dup 2) (match_dup 1))
4527 (set (match_dup 0) (fix:DI (match_dup 2)))]
4530 (define_insn "fix_truncdfdi_sse"
4531 [(set (match_operand:DI 0 "register_operand" "=r,r")
4532 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4533 "TARGET_64BIT && TARGET_SSE2"
4534 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4535 [(set_attr "type" "sseicvt,sseicvt")
4536 (set_attr "mode" "DF")
4537 (set_attr "athlon_decode" "double,vector")])
4539 ;; Avoid vector decoded form of the instruction.
4541 [(match_scratch:DF 2 "Y")
4542 (set (match_operand:DI 0 "register_operand" "")
4543 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4544 "TARGET_K8 && !optimize_size"
4545 [(set (match_dup 2) (match_dup 1))
4546 (set (match_dup 0) (fix:DI (match_dup 2)))]
4549 ;; Signed conversion to SImode.
4551 (define_expand "fix_truncxfsi2"
4552 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4553 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4554 "!TARGET_64BIT && TARGET_80387"
4557 (define_expand "fix_trunctfsi2"
4558 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4559 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4563 (define_expand "fix_truncdfsi2"
4564 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4565 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4566 "TARGET_80387 || TARGET_SSE2"
4570 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4571 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4572 if (out != operands[0])
4573 emit_move_insn (operands[0], out);
4578 (define_expand "fix_truncsfsi2"
4579 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4580 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4581 "TARGET_80387 || TARGET_SSE"
4585 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4586 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4587 if (out != operands[0])
4588 emit_move_insn (operands[0], out);
4593 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4594 ;; of the machinery.
4595 (define_insn_and_split "*fix_truncsi_1"
4596 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4597 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4598 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4599 && !reload_completed && !reload_in_progress
4600 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4605 ix86_optimize_mode_switching = 1;
4606 operands[2] = assign_386_stack_local (HImode, 1);
4607 operands[3] = assign_386_stack_local (HImode, 2);
4608 if (memory_operand (operands[0], VOIDmode))
4609 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4610 operands[2], operands[3]));
4613 operands[4] = assign_386_stack_local (SImode, 0);
4614 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4615 operands[2], operands[3],
4620 [(set_attr "type" "fistp")
4621 (set_attr "mode" "SI")])
4623 (define_insn "fix_truncsi_nomemory"
4624 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4625 (fix:SI (match_operand 1 "register_operand" "f,f")))
4626 (use (match_operand:HI 2 "memory_operand" "m,m"))
4627 (use (match_operand:HI 3 "memory_operand" "m,m"))
4628 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4629 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4630 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4632 [(set_attr "type" "fistp")
4633 (set_attr "mode" "SI")])
4635 (define_insn "fix_truncsi_memory"
4636 [(set (match_operand:SI 0 "memory_operand" "=m")
4637 (fix:SI (match_operand 1 "register_operand" "f")))
4638 (use (match_operand:HI 2 "memory_operand" "m"))
4639 (use (match_operand:HI 3 "memory_operand" "m"))]
4640 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4641 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4642 "* return output_fix_trunc (insn, operands);"
4643 [(set_attr "type" "fistp")
4644 (set_attr "mode" "SI")])
4646 ;; When SSE available, it is always faster to use it!
4647 (define_insn "fix_truncsfsi_sse"
4648 [(set (match_operand:SI 0 "register_operand" "=r,r")
4649 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4651 "cvttss2si\t{%1, %0|%0, %1}"
4652 [(set_attr "type" "sseicvt")
4653 (set_attr "mode" "DF")
4654 (set_attr "athlon_decode" "double,vector")])
4656 ;; Avoid vector decoded form of the instruction.
4658 [(match_scratch:SF 2 "x")
4659 (set (match_operand:SI 0 "register_operand" "")
4660 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4661 "TARGET_K8 && !optimize_size"
4662 [(set (match_dup 2) (match_dup 1))
4663 (set (match_dup 0) (fix:SI (match_dup 2)))]
4666 (define_insn "fix_truncdfsi_sse"
4667 [(set (match_operand:SI 0 "register_operand" "=r,r")
4668 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4670 "cvttsd2si\t{%1, %0|%0, %1}"
4671 [(set_attr "type" "sseicvt")
4672 (set_attr "mode" "DF")
4673 (set_attr "athlon_decode" "double,vector")])
4675 ;; Avoid vector decoded form of the instruction.
4677 [(match_scratch:DF 2 "Y")
4678 (set (match_operand:SI 0 "register_operand" "")
4679 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4680 "TARGET_K8 && !optimize_size"
4681 [(set (match_dup 2) (match_dup 1))
4682 (set (match_dup 0) (fix:SI (match_dup 2)))]
4686 [(set (match_operand:SI 0 "register_operand" "")
4687 (fix:SI (match_operand 1 "register_operand" "")))
4688 (use (match_operand:HI 2 "memory_operand" ""))
4689 (use (match_operand:HI 3 "memory_operand" ""))
4690 (clobber (match_operand:SI 4 "memory_operand" ""))]
4692 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4694 (use (match_dup 3))])
4695 (set (match_dup 0) (match_dup 4))]
4699 [(set (match_operand:SI 0 "memory_operand" "")
4700 (fix:SI (match_operand 1 "register_operand" "")))
4701 (use (match_operand:HI 2 "memory_operand" ""))
4702 (use (match_operand:HI 3 "memory_operand" ""))
4703 (clobber (match_operand:SI 4 "memory_operand" ""))]
4705 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4707 (use (match_dup 3))])]
4710 ;; Signed conversion to HImode.
4712 (define_expand "fix_truncxfhi2"
4713 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4714 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4715 "!TARGET_64BIT && TARGET_80387"
4718 (define_expand "fix_trunctfhi2"
4719 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4720 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4724 (define_expand "fix_truncdfhi2"
4725 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4726 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4727 "TARGET_80387 && !TARGET_SSE2"
4730 (define_expand "fix_truncsfhi2"
4731 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4732 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4733 "TARGET_80387 && !TARGET_SSE"
4736 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4737 ;; of the machinery.
4738 (define_insn_and_split "*fix_trunchi_1"
4739 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4740 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4741 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4742 && !reload_completed && !reload_in_progress
4743 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4748 ix86_optimize_mode_switching = 1;
4749 operands[2] = assign_386_stack_local (HImode, 1);
4750 operands[3] = assign_386_stack_local (HImode, 2);
4751 if (memory_operand (operands[0], VOIDmode))
4752 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4753 operands[2], operands[3]));
4756 operands[4] = assign_386_stack_local (HImode, 0);
4757 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4758 operands[2], operands[3],
4763 [(set_attr "type" "fistp")
4764 (set_attr "mode" "HI")])
4766 (define_insn "fix_trunchi_nomemory"
4767 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4768 (fix:HI (match_operand 1 "register_operand" "f,f")))
4769 (use (match_operand:HI 2 "memory_operand" "m,m"))
4770 (use (match_operand:HI 3 "memory_operand" "m,m"))
4771 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4772 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4773 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4775 [(set_attr "type" "fistp")
4776 (set_attr "mode" "HI")])
4778 (define_insn "fix_trunchi_memory"
4779 [(set (match_operand:HI 0 "memory_operand" "=m")
4780 (fix:HI (match_operand 1 "register_operand" "f")))
4781 (use (match_operand:HI 2 "memory_operand" "m"))
4782 (use (match_operand:HI 3 "memory_operand" "m"))]
4783 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4784 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4785 "* return output_fix_trunc (insn, operands);"
4786 [(set_attr "type" "fistp")
4787 (set_attr "mode" "HI")])
4790 [(set (match_operand:HI 0 "memory_operand" "")
4791 (fix:HI (match_operand 1 "register_operand" "")))
4792 (use (match_operand:HI 2 "memory_operand" ""))
4793 (use (match_operand:HI 3 "memory_operand" ""))
4794 (clobber (match_operand:HI 4 "memory_operand" ""))]
4796 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4798 (use (match_dup 3))])]
4802 [(set (match_operand:HI 0 "register_operand" "")
4803 (fix:HI (match_operand 1 "register_operand" "")))
4804 (use (match_operand:HI 2 "memory_operand" ""))
4805 (use (match_operand:HI 3 "memory_operand" ""))
4806 (clobber (match_operand:HI 4 "memory_operand" ""))]
4808 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4811 (clobber (match_dup 4))])
4812 (set (match_dup 0) (match_dup 4))]
4816 (define_insn "x86_fnstcw_1"
4817 [(set (match_operand:HI 0 "memory_operand" "=m")
4818 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4821 [(set_attr "length" "2")
4822 (set_attr "mode" "HI")
4823 (set_attr "unit" "i387")
4824 (set_attr "ppro_uops" "few")])
4826 (define_insn "x86_fldcw_1"
4828 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4831 [(set_attr "length" "2")
4832 (set_attr "mode" "HI")
4833 (set_attr "unit" "i387")
4834 (set_attr "athlon_decode" "vector")
4835 (set_attr "ppro_uops" "few")])
4837 ;; Conversion between fixed point and floating point.
4839 ;; Even though we only accept memory inputs, the backend _really_
4840 ;; wants to be able to do this between registers.
4842 (define_expand "floathisf2"
4843 [(set (match_operand:SF 0 "register_operand" "")
4844 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4845 "TARGET_SSE || TARGET_80387"
4847 if (TARGET_SSE && TARGET_SSE_MATH)
4849 emit_insn (gen_floatsisf2 (operands[0],
4850 convert_to_mode (SImode, operands[1], 0)));
4855 (define_insn "*floathisf2_1"
4856 [(set (match_operand:SF 0 "register_operand" "=f,f")
4857 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4858 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4862 [(set_attr "type" "fmov,multi")
4863 (set_attr "mode" "SF")
4864 (set_attr "fp_int_src" "true")])
4866 (define_expand "floatsisf2"
4867 [(set (match_operand:SF 0 "register_operand" "")
4868 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4869 "TARGET_SSE || TARGET_80387"
4872 (define_insn "*floatsisf2_i387"
4873 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4874 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4875 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4879 cvtsi2ss\t{%1, %0|%0, %1}
4880 cvtsi2ss\t{%1, %0|%0, %1}"
4881 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4882 (set_attr "mode" "SF")
4883 (set_attr "athlon_decode" "*,*,vector,double")
4884 (set_attr "fp_int_src" "true")])
4886 (define_insn "*floatsisf2_sse"
4887 [(set (match_operand:SF 0 "register_operand" "=x,x")
4888 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4890 "cvtsi2ss\t{%1, %0|%0, %1}"
4891 [(set_attr "type" "sseicvt")
4892 (set_attr "mode" "SF")
4893 (set_attr "athlon_decode" "vector,double")
4894 (set_attr "fp_int_src" "true")])
4896 ; Avoid possible reformatting penalty on the destination by first
4899 [(set (match_operand:SF 0 "register_operand" "")
4900 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4901 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4902 && SSE_REG_P (operands[0])"
4906 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4907 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4908 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4912 (define_expand "floatdisf2"
4913 [(set (match_operand:SF 0 "register_operand" "")
4914 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4915 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4918 (define_insn "*floatdisf2_i387_only"
4919 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4920 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4921 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4925 [(set_attr "type" "fmov,multi")
4926 (set_attr "mode" "SF")
4927 (set_attr "fp_int_src" "true")])
4929 (define_insn "*floatdisf2_i387"
4930 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4931 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4932 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4936 cvtsi2ss{q}\t{%1, %0|%0, %1}
4937 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4938 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4939 (set_attr "mode" "SF")
4940 (set_attr "athlon_decode" "*,*,vector,double")
4941 (set_attr "fp_int_src" "true")])
4943 (define_insn "*floatdisf2_sse"
4944 [(set (match_operand:SF 0 "register_operand" "=x,x")
4945 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4946 "TARGET_64BIT && TARGET_SSE"
4947 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4948 [(set_attr "type" "sseicvt")
4949 (set_attr "mode" "SF")
4950 (set_attr "athlon_decode" "vector,double")
4951 (set_attr "fp_int_src" "true")])
4953 ; Avoid possible reformatting penalty on the destination by first
4956 [(set (match_operand:SF 0 "register_operand" "")
4957 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4958 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4959 && SSE_REG_P (operands[0])"
4963 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4964 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4965 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4969 (define_expand "floathidf2"
4970 [(set (match_operand:DF 0 "register_operand" "")
4971 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4972 "TARGET_SSE2 || TARGET_80387"
4974 if (TARGET_SSE && TARGET_SSE_MATH)
4976 emit_insn (gen_floatsidf2 (operands[0],
4977 convert_to_mode (SImode, operands[1], 0)));
4982 (define_insn "*floathidf2_1"
4983 [(set (match_operand:DF 0 "register_operand" "=f,f")
4984 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4985 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4989 [(set_attr "type" "fmov,multi")
4990 (set_attr "mode" "DF")
4991 (set_attr "fp_int_src" "true")])
4993 (define_expand "floatsidf2"
4994 [(set (match_operand:DF 0 "register_operand" "")
4995 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4996 "TARGET_80387 || TARGET_SSE2"
4999 (define_insn "*floatsidf2_i387"
5000 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
5001 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
5002 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5006 cvtsi2sd\t{%1, %0|%0, %1}
5007 cvtsi2sd\t{%1, %0|%0, %1}"
5008 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5009 (set_attr "mode" "DF")
5010 (set_attr "athlon_decode" "*,*,double,direct")
5011 (set_attr "fp_int_src" "true")])
5013 (define_insn "*floatsidf2_sse"
5014 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5015 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
5017 "cvtsi2sd\t{%1, %0|%0, %1}"
5018 [(set_attr "type" "sseicvt")
5019 (set_attr "mode" "DF")
5020 (set_attr "athlon_decode" "double,direct")
5021 (set_attr "fp_int_src" "true")])
5023 (define_expand "floatdidf2"
5024 [(set (match_operand:DF 0 "register_operand" "")
5025 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5026 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
5029 (define_insn "*floatdidf2_i387_only"
5030 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5031 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5032 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5036 [(set_attr "type" "fmov,multi")
5037 (set_attr "mode" "DF")
5038 (set_attr "fp_int_src" "true")])
5040 (define_insn "*floatdidf2_i387"
5041 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
5042 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
5043 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5047 cvtsi2sd{q}\t{%1, %0|%0, %1}
5048 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5049 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5050 (set_attr "mode" "DF")
5051 (set_attr "athlon_decode" "*,*,double,direct")
5052 (set_attr "fp_int_src" "true")])
5054 (define_insn "*floatdidf2_sse"
5055 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5056 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
5058 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5059 [(set_attr "type" "sseicvt")
5060 (set_attr "mode" "DF")
5061 (set_attr "athlon_decode" "double,direct")
5062 (set_attr "fp_int_src" "true")])
5064 (define_insn "floathixf2"
5065 [(set (match_operand:XF 0 "register_operand" "=f,f")
5066 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5067 "!TARGET_64BIT && TARGET_80387"
5071 [(set_attr "type" "fmov,multi")
5072 (set_attr "mode" "XF")
5073 (set_attr "fp_int_src" "true")])
5075 (define_insn "floathitf2"
5076 [(set (match_operand:TF 0 "register_operand" "=f,f")
5077 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5082 [(set_attr "type" "fmov,multi")
5083 (set_attr "mode" "XF")
5084 (set_attr "fp_int_src" "true")])
5086 (define_insn "floatsixf2"
5087 [(set (match_operand:XF 0 "register_operand" "=f,f")
5088 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5089 "!TARGET_64BIT && TARGET_80387"
5093 [(set_attr "type" "fmov,multi")
5094 (set_attr "mode" "XF")
5095 (set_attr "fp_int_src" "true")])
5097 (define_insn "floatsitf2"
5098 [(set (match_operand:TF 0 "register_operand" "=f,f")
5099 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5104 [(set_attr "type" "fmov,multi")
5105 (set_attr "mode" "XF")
5106 (set_attr "fp_int_src" "true")])
5108 (define_insn "floatdixf2"
5109 [(set (match_operand:XF 0 "register_operand" "=f,f")
5110 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5111 "!TARGET_64BIT && TARGET_80387"
5115 [(set_attr "type" "fmov,multi")
5116 (set_attr "mode" "XF")
5117 (set_attr "fp_int_src" "true")])
5119 (define_insn "floatditf2"
5120 [(set (match_operand:TF 0 "register_operand" "=f,f")
5121 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5126 [(set_attr "type" "fmov,multi")
5127 (set_attr "mode" "XF")
5128 (set_attr "fp_int_src" "true")])
5130 ;; %%% Kill these when reload knows how to do it.
5132 [(set (match_operand 0 "fp_register_operand" "")
5133 (float (match_operand 1 "register_operand" "")))]
5134 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
5137 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5138 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5139 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5140 ix86_free_from_memory (GET_MODE (operands[1]));
5144 (define_expand "floatunssisf2"
5145 [(use (match_operand:SF 0 "register_operand" ""))
5146 (use (match_operand:SI 1 "register_operand" ""))]
5147 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
5148 "x86_emit_floatuns (operands); DONE;")
5150 (define_expand "floatunsdisf2"
5151 [(use (match_operand:SF 0 "register_operand" ""))
5152 (use (match_operand:DI 1 "register_operand" ""))]
5153 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
5154 "x86_emit_floatuns (operands); DONE;")
5156 (define_expand "floatunsdidf2"
5157 [(use (match_operand:DF 0 "register_operand" ""))
5158 (use (match_operand:DI 1 "register_operand" ""))]
5159 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
5160 "x86_emit_floatuns (operands); DONE;")
5164 ;; %%% splits for addsidi3
5165 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5166 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5167 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5169 (define_expand "adddi3"
5170 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5171 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5172 (match_operand:DI 2 "x86_64_general_operand" "")))
5173 (clobber (reg:CC 17))]
5175 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5177 (define_insn "*adddi3_1"
5178 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5179 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5180 (match_operand:DI 2 "general_operand" "roiF,riF")))
5181 (clobber (reg:CC 17))]
5182 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5186 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5187 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5188 (match_operand:DI 2 "general_operand" "")))
5189 (clobber (reg:CC 17))]
5190 "!TARGET_64BIT && reload_completed"
5191 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
5193 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5194 (parallel [(set (match_dup 3)
5195 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5198 (clobber (reg:CC 17))])]
5199 "split_di (operands+0, 1, operands+0, operands+3);
5200 split_di (operands+1, 1, operands+1, operands+4);
5201 split_di (operands+2, 1, operands+2, operands+5);")
5203 (define_insn "adddi3_carry_rex64"
5204 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5205 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5206 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5207 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5208 (clobber (reg:CC 17))]
5209 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5210 "adc{q}\t{%2, %0|%0, %2}"
5211 [(set_attr "type" "alu")
5212 (set_attr "pent_pair" "pu")
5213 (set_attr "mode" "DI")
5214 (set_attr "ppro_uops" "few")])
5216 (define_insn "*adddi3_cc_rex64"
5218 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5219 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5221 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5222 (plus:DI (match_dup 1) (match_dup 2)))]
5223 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5224 "add{q}\t{%2, %0|%0, %2}"
5225 [(set_attr "type" "alu")
5226 (set_attr "mode" "DI")])
5228 (define_insn "addqi3_carry"
5229 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
5230 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5231 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5232 (match_operand:QI 2 "general_operand" "ri,rm")))
5233 (clobber (reg:CC 17))]
5234 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5235 "adc{b}\t{%2, %0|%0, %2}"
5236 [(set_attr "type" "alu")
5237 (set_attr "pent_pair" "pu")
5238 (set_attr "mode" "QI")
5239 (set_attr "ppro_uops" "few")])
5241 (define_insn "addhi3_carry"
5242 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5243 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5244 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5245 (match_operand:HI 2 "general_operand" "ri,rm")))
5246 (clobber (reg:CC 17))]
5247 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5248 "adc{w}\t{%2, %0|%0, %2}"
5249 [(set_attr "type" "alu")
5250 (set_attr "pent_pair" "pu")
5251 (set_attr "mode" "HI")
5252 (set_attr "ppro_uops" "few")])
5254 (define_insn "addsi3_carry"
5255 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5256 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5257 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5258 (match_operand:SI 2 "general_operand" "ri,rm")))
5259 (clobber (reg:CC 17))]
5260 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5261 "adc{l}\t{%2, %0|%0, %2}"
5262 [(set_attr "type" "alu")
5263 (set_attr "pent_pair" "pu")
5264 (set_attr "mode" "SI")
5265 (set_attr "ppro_uops" "few")])
5267 (define_insn "*addsi3_carry_zext"
5268 [(set (match_operand:DI 0 "register_operand" "=r")
5270 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5271 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5272 (match_operand:SI 2 "general_operand" "rim"))))
5273 (clobber (reg:CC 17))]
5274 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5275 "adc{l}\t{%2, %k0|%k0, %2}"
5276 [(set_attr "type" "alu")
5277 (set_attr "pent_pair" "pu")
5278 (set_attr "mode" "SI")
5279 (set_attr "ppro_uops" "few")])
5281 (define_insn "*addsi3_cc"
5283 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5284 (match_operand:SI 2 "general_operand" "ri,rm")]
5286 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5287 (plus:SI (match_dup 1) (match_dup 2)))]
5288 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5289 "add{l}\t{%2, %0|%0, %2}"
5290 [(set_attr "type" "alu")
5291 (set_attr "mode" "SI")])
5293 (define_insn "addqi3_cc"
5295 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5296 (match_operand:QI 2 "general_operand" "qi,qm")]
5298 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5299 (plus:QI (match_dup 1) (match_dup 2)))]
5300 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5301 "add{b}\t{%2, %0|%0, %2}"
5302 [(set_attr "type" "alu")
5303 (set_attr "mode" "QI")])
5305 (define_expand "addsi3"
5306 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5307 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5308 (match_operand:SI 2 "general_operand" "")))
5309 (clobber (reg:CC 17))])]
5311 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5313 (define_insn "*lea_1"
5314 [(set (match_operand:SI 0 "register_operand" "=r")
5315 (match_operand:SI 1 "address_operand" "p"))]
5317 "lea{l}\t{%a1, %0|%0, %a1}"
5318 [(set_attr "type" "lea")
5319 (set_attr "mode" "SI")])
5321 (define_insn "*lea_1_rex64"
5322 [(set (match_operand:SI 0 "register_operand" "=r")
5323 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5325 "lea{l}\t{%a1, %0|%0, %a1}"
5326 [(set_attr "type" "lea")
5327 (set_attr "mode" "SI")])
5329 (define_insn "*lea_1_zext"
5330 [(set (match_operand:DI 0 "register_operand" "=r")
5331 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5333 "lea{l}\t{%a1, %k0|%k0, %a1}"
5334 [(set_attr "type" "lea")
5335 (set_attr "mode" "SI")])
5337 (define_insn "*lea_2_rex64"
5338 [(set (match_operand:DI 0 "register_operand" "=r")
5339 (match_operand:DI 1 "address_operand" "p"))]
5341 "lea{q}\t{%a1, %0|%0, %a1}"
5342 [(set_attr "type" "lea")
5343 (set_attr "mode" "DI")])
5345 ;; The lea patterns for non-Pmodes needs to be matched by several
5346 ;; insns converted to real lea by splitters.
5348 (define_insn_and_split "*lea_general_1"
5349 [(set (match_operand 0 "register_operand" "=r")
5350 (plus (plus (match_operand 1 "index_register_operand" "r")
5351 (match_operand 2 "register_operand" "r"))
5352 (match_operand 3 "immediate_operand" "i")))]
5353 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5354 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5355 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5356 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5357 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5358 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5359 || GET_MODE (operands[3]) == VOIDmode)"
5361 "&& reload_completed"
5365 operands[0] = gen_lowpart (SImode, operands[0]);
5366 operands[1] = gen_lowpart (Pmode, operands[1]);
5367 operands[2] = gen_lowpart (Pmode, operands[2]);
5368 operands[3] = gen_lowpart (Pmode, operands[3]);
5369 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5371 if (Pmode != SImode)
5372 pat = gen_rtx_SUBREG (SImode, pat, 0);
5373 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5376 [(set_attr "type" "lea")
5377 (set_attr "mode" "SI")])
5379 (define_insn_and_split "*lea_general_1_zext"
5380 [(set (match_operand:DI 0 "register_operand" "=r")
5382 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5383 (match_operand:SI 2 "register_operand" "r"))
5384 (match_operand:SI 3 "immediate_operand" "i"))))]
5387 "&& reload_completed"
5389 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5391 (match_dup 3)) 0)))]
5393 operands[1] = gen_lowpart (Pmode, operands[1]);
5394 operands[2] = gen_lowpart (Pmode, operands[2]);
5395 operands[3] = gen_lowpart (Pmode, operands[3]);
5397 [(set_attr "type" "lea")
5398 (set_attr "mode" "SI")])
5400 (define_insn_and_split "*lea_general_2"
5401 [(set (match_operand 0 "register_operand" "=r")
5402 (plus (mult (match_operand 1 "index_register_operand" "r")
5403 (match_operand 2 "const248_operand" "i"))
5404 (match_operand 3 "nonmemory_operand" "ri")))]
5405 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5406 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5407 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5408 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5409 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5410 || GET_MODE (operands[3]) == VOIDmode)"
5412 "&& reload_completed"
5416 operands[0] = gen_lowpart (SImode, operands[0]);
5417 operands[1] = gen_lowpart (Pmode, operands[1]);
5418 operands[3] = gen_lowpart (Pmode, operands[3]);
5419 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5421 if (Pmode != SImode)
5422 pat = gen_rtx_SUBREG (SImode, pat, 0);
5423 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5426 [(set_attr "type" "lea")
5427 (set_attr "mode" "SI")])
5429 (define_insn_and_split "*lea_general_2_zext"
5430 [(set (match_operand:DI 0 "register_operand" "=r")
5432 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5433 (match_operand:SI 2 "const248_operand" "n"))
5434 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5437 "&& reload_completed"
5439 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5441 (match_dup 3)) 0)))]
5443 operands[1] = gen_lowpart (Pmode, operands[1]);
5444 operands[3] = gen_lowpart (Pmode, operands[3]);
5446 [(set_attr "type" "lea")
5447 (set_attr "mode" "SI")])
5449 (define_insn_and_split "*lea_general_3"
5450 [(set (match_operand 0 "register_operand" "=r")
5451 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5452 (match_operand 2 "const248_operand" "i"))
5453 (match_operand 3 "register_operand" "r"))
5454 (match_operand 4 "immediate_operand" "i")))]
5455 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5456 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5457 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5458 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5459 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5461 "&& reload_completed"
5465 operands[0] = gen_lowpart (SImode, operands[0]);
5466 operands[1] = gen_lowpart (Pmode, operands[1]);
5467 operands[3] = gen_lowpart (Pmode, operands[3]);
5468 operands[4] = gen_lowpart (Pmode, operands[4]);
5469 pat = gen_rtx_PLUS (Pmode,
5470 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5474 if (Pmode != SImode)
5475 pat = gen_rtx_SUBREG (SImode, pat, 0);
5476 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5479 [(set_attr "type" "lea")
5480 (set_attr "mode" "SI")])
5482 (define_insn_and_split "*lea_general_3_zext"
5483 [(set (match_operand:DI 0 "register_operand" "=r")
5485 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5486 (match_operand:SI 2 "const248_operand" "n"))
5487 (match_operand:SI 3 "register_operand" "r"))
5488 (match_operand:SI 4 "immediate_operand" "i"))))]
5491 "&& reload_completed"
5493 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5496 (match_dup 4)) 0)))]
5498 operands[1] = gen_lowpart (Pmode, operands[1]);
5499 operands[3] = gen_lowpart (Pmode, operands[3]);
5500 operands[4] = gen_lowpart (Pmode, operands[4]);
5502 [(set_attr "type" "lea")
5503 (set_attr "mode" "SI")])
5505 (define_insn "*adddi_1_rex64"
5506 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5507 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5508 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5509 (clobber (reg:CC 17))]
5510 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5512 switch (get_attr_type (insn))
5515 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5516 return "lea{q}\t{%a2, %0|%0, %a2}";
5519 if (! rtx_equal_p (operands[0], operands[1]))
5521 if (operands[2] == const1_rtx)
5522 return "inc{q}\t%0";
5523 else if (operands[2] == constm1_rtx)
5524 return "dec{q}\t%0";
5529 if (! rtx_equal_p (operands[0], operands[1]))
5532 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5533 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5534 if (GET_CODE (operands[2]) == CONST_INT
5535 /* Avoid overflows. */
5536 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5537 && (INTVAL (operands[2]) == 128
5538 || (INTVAL (operands[2]) < 0
5539 && INTVAL (operands[2]) != -128)))
5541 operands[2] = GEN_INT (-INTVAL (operands[2]));
5542 return "sub{q}\t{%2, %0|%0, %2}";
5544 return "add{q}\t{%2, %0|%0, %2}";
5548 (cond [(eq_attr "alternative" "2")
5549 (const_string "lea")
5550 ; Current assemblers are broken and do not allow @GOTOFF in
5551 ; ought but a memory context.
5552 (match_operand:DI 2 "pic_symbolic_operand" "")
5553 (const_string "lea")
5554 (match_operand:DI 2 "incdec_operand" "")
5555 (const_string "incdec")
5557 (const_string "alu")))
5558 (set_attr "mode" "DI")])
5560 ;; Convert lea to the lea pattern to avoid flags dependency.
5562 [(set (match_operand:DI 0 "register_operand" "")
5563 (plus:DI (match_operand:DI 1 "register_operand" "")
5564 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5565 (clobber (reg:CC 17))]
5566 "TARGET_64BIT && reload_completed
5567 && true_regnum (operands[0]) != true_regnum (operands[1])"
5569 (plus:DI (match_dup 1)
5573 (define_insn "*adddi_2_rex64"
5576 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5577 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5579 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5580 (plus:DI (match_dup 1) (match_dup 2)))]
5581 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5582 && ix86_binary_operator_ok (PLUS, DImode, operands)
5583 /* Current assemblers are broken and do not allow @GOTOFF in
5584 ought but a memory context. */
5585 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5587 switch (get_attr_type (insn))
5590 if (! rtx_equal_p (operands[0], operands[1]))
5592 if (operands[2] == const1_rtx)
5593 return "inc{q}\t%0";
5594 else if (operands[2] == constm1_rtx)
5595 return "dec{q}\t%0";
5600 if (! rtx_equal_p (operands[0], operands[1]))
5602 /* ???? We ought to handle there the 32bit case too
5603 - do we need new constraint? */
5604 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5605 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5606 if (GET_CODE (operands[2]) == CONST_INT
5607 /* Avoid overflows. */
5608 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5609 && (INTVAL (operands[2]) == 128
5610 || (INTVAL (operands[2]) < 0
5611 && INTVAL (operands[2]) != -128)))
5613 operands[2] = GEN_INT (-INTVAL (operands[2]));
5614 return "sub{q}\t{%2, %0|%0, %2}";
5616 return "add{q}\t{%2, %0|%0, %2}";
5620 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5621 (const_string "incdec")
5622 (const_string "alu")))
5623 (set_attr "mode" "DI")])
5625 (define_insn "*adddi_3_rex64"
5627 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5628 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5629 (clobber (match_scratch:DI 0 "=r"))]
5631 && ix86_match_ccmode (insn, CCZmode)
5632 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5633 /* Current assemblers are broken and do not allow @GOTOFF in
5634 ought but a memory context. */
5635 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5637 switch (get_attr_type (insn))
5640 if (! rtx_equal_p (operands[0], operands[1]))
5642 if (operands[2] == const1_rtx)
5643 return "inc{q}\t%0";
5644 else if (operands[2] == constm1_rtx)
5645 return "dec{q}\t%0";
5650 if (! rtx_equal_p (operands[0], operands[1]))
5652 /* ???? We ought to handle there the 32bit case too
5653 - do we need new constraint? */
5654 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5655 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5656 if (GET_CODE (operands[2]) == CONST_INT
5657 /* Avoid overflows. */
5658 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5659 && (INTVAL (operands[2]) == 128
5660 || (INTVAL (operands[2]) < 0
5661 && INTVAL (operands[2]) != -128)))
5663 operands[2] = GEN_INT (-INTVAL (operands[2]));
5664 return "sub{q}\t{%2, %0|%0, %2}";
5666 return "add{q}\t{%2, %0|%0, %2}";
5670 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5671 (const_string "incdec")
5672 (const_string "alu")))
5673 (set_attr "mode" "DI")])
5675 ; For comparisons against 1, -1 and 128, we may generate better code
5676 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5677 ; is matched then. We can't accept general immediate, because for
5678 ; case of overflows, the result is messed up.
5679 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5681 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5682 ; only for comparisons not depending on it.
5683 (define_insn "*adddi_4_rex64"
5685 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5686 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5687 (clobber (match_scratch:DI 0 "=rm"))]
5689 && ix86_match_ccmode (insn, CCGCmode)"
5691 switch (get_attr_type (insn))
5694 if (operands[2] == constm1_rtx)
5695 return "inc{q}\t%0";
5696 else if (operands[2] == const1_rtx)
5697 return "dec{q}\t%0";
5702 if (! rtx_equal_p (operands[0], operands[1]))
5704 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5705 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5706 if ((INTVAL (operands[2]) == -128
5707 || (INTVAL (operands[2]) > 0
5708 && INTVAL (operands[2]) != 128))
5709 /* Avoid overflows. */
5710 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5711 return "sub{q}\t{%2, %0|%0, %2}";
5712 operands[2] = GEN_INT (-INTVAL (operands[2]));
5713 return "add{q}\t{%2, %0|%0, %2}";
5717 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5718 (const_string "incdec")
5719 (const_string "alu")))
5720 (set_attr "mode" "DI")])
5722 (define_insn "*adddi_5_rex64"
5725 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5726 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5728 (clobber (match_scratch:DI 0 "=r"))]
5730 && ix86_match_ccmode (insn, CCGOCmode)
5731 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5732 /* Current assemblers are broken and do not allow @GOTOFF in
5733 ought but a memory context. */
5734 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5736 switch (get_attr_type (insn))
5739 if (! rtx_equal_p (operands[0], operands[1]))
5741 if (operands[2] == const1_rtx)
5742 return "inc{q}\t%0";
5743 else if (operands[2] == constm1_rtx)
5744 return "dec{q}\t%0";
5749 if (! rtx_equal_p (operands[0], operands[1]))
5751 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5752 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5753 if (GET_CODE (operands[2]) == CONST_INT
5754 /* Avoid overflows. */
5755 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5756 && (INTVAL (operands[2]) == 128
5757 || (INTVAL (operands[2]) < 0
5758 && INTVAL (operands[2]) != -128)))
5760 operands[2] = GEN_INT (-INTVAL (operands[2]));
5761 return "sub{q}\t{%2, %0|%0, %2}";
5763 return "add{q}\t{%2, %0|%0, %2}";
5767 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5768 (const_string "incdec")
5769 (const_string "alu")))
5770 (set_attr "mode" "DI")])
5773 (define_insn "*addsi_1"
5774 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5775 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5776 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5777 (clobber (reg:CC 17))]
5778 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5780 switch (get_attr_type (insn))
5783 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5784 return "lea{l}\t{%a2, %0|%0, %a2}";
5787 if (! rtx_equal_p (operands[0], operands[1]))
5789 if (operands[2] == const1_rtx)
5790 return "inc{l}\t%0";
5791 else if (operands[2] == constm1_rtx)
5792 return "dec{l}\t%0";
5797 if (! rtx_equal_p (operands[0], operands[1]))
5800 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5801 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5802 if (GET_CODE (operands[2]) == CONST_INT
5803 && (INTVAL (operands[2]) == 128
5804 || (INTVAL (operands[2]) < 0
5805 && INTVAL (operands[2]) != -128)))
5807 operands[2] = GEN_INT (-INTVAL (operands[2]));
5808 return "sub{l}\t{%2, %0|%0, %2}";
5810 return "add{l}\t{%2, %0|%0, %2}";
5814 (cond [(eq_attr "alternative" "2")
5815 (const_string "lea")
5816 ; Current assemblers are broken and do not allow @GOTOFF in
5817 ; ought but a memory context.
5818 (match_operand:SI 2 "pic_symbolic_operand" "")
5819 (const_string "lea")
5820 (match_operand:SI 2 "incdec_operand" "")
5821 (const_string "incdec")
5823 (const_string "alu")))
5824 (set_attr "mode" "SI")])
5826 ;; Convert lea to the lea pattern to avoid flags dependency.
5828 [(set (match_operand 0 "register_operand" "")
5829 (plus (match_operand 1 "register_operand" "")
5830 (match_operand 2 "nonmemory_operand" "")))
5831 (clobber (reg:CC 17))]
5833 && true_regnum (operands[0]) != true_regnum (operands[1])"
5837 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5838 may confuse gen_lowpart. */
5839 if (GET_MODE (operands[0]) != Pmode)
5841 operands[1] = gen_lowpart (Pmode, operands[1]);
5842 operands[2] = gen_lowpart (Pmode, operands[2]);
5844 operands[0] = gen_lowpart (SImode, operands[0]);
5845 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5846 if (Pmode != SImode)
5847 pat = gen_rtx_SUBREG (SImode, pat, 0);
5848 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5852 ;; It may seem that nonimmediate operand is proper one for operand 1.
5853 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5854 ;; we take care in ix86_binary_operator_ok to not allow two memory
5855 ;; operands so proper swapping will be done in reload. This allow
5856 ;; patterns constructed from addsi_1 to match.
5857 (define_insn "addsi_1_zext"
5858 [(set (match_operand:DI 0 "register_operand" "=r,r")
5860 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5861 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5862 (clobber (reg:CC 17))]
5863 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5865 switch (get_attr_type (insn))
5868 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5869 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5872 if (operands[2] == const1_rtx)
5873 return "inc{l}\t%k0";
5874 else if (operands[2] == constm1_rtx)
5875 return "dec{l}\t%k0";
5880 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5881 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5882 if (GET_CODE (operands[2]) == CONST_INT
5883 && (INTVAL (operands[2]) == 128
5884 || (INTVAL (operands[2]) < 0
5885 && INTVAL (operands[2]) != -128)))
5887 operands[2] = GEN_INT (-INTVAL (operands[2]));
5888 return "sub{l}\t{%2, %k0|%k0, %2}";
5890 return "add{l}\t{%2, %k0|%k0, %2}";
5894 (cond [(eq_attr "alternative" "1")
5895 (const_string "lea")
5896 ; Current assemblers are broken and do not allow @GOTOFF in
5897 ; ought but a memory context.
5898 (match_operand:SI 2 "pic_symbolic_operand" "")
5899 (const_string "lea")
5900 (match_operand:SI 2 "incdec_operand" "")
5901 (const_string "incdec")
5903 (const_string "alu")))
5904 (set_attr "mode" "SI")])
5906 ;; Convert lea to the lea pattern to avoid flags dependency.
5908 [(set (match_operand:DI 0 "register_operand" "")
5910 (plus:SI (match_operand:SI 1 "register_operand" "")
5911 (match_operand:SI 2 "nonmemory_operand" ""))))
5912 (clobber (reg:CC 17))]
5913 "TARGET_64BIT && reload_completed
5914 && true_regnum (operands[0]) != true_regnum (operands[1])"
5916 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5918 operands[1] = gen_lowpart (Pmode, operands[1]);
5919 operands[2] = gen_lowpart (Pmode, operands[2]);
5922 (define_insn "*addsi_2"
5925 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5926 (match_operand:SI 2 "general_operand" "rmni,rni"))
5928 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5929 (plus:SI (match_dup 1) (match_dup 2)))]
5930 "ix86_match_ccmode (insn, CCGOCmode)
5931 && ix86_binary_operator_ok (PLUS, SImode, operands)
5932 /* Current assemblers are broken and do not allow @GOTOFF in
5933 ought but a memory context. */
5934 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5936 switch (get_attr_type (insn))
5939 if (! rtx_equal_p (operands[0], operands[1]))
5941 if (operands[2] == const1_rtx)
5942 return "inc{l}\t%0";
5943 else if (operands[2] == constm1_rtx)
5944 return "dec{l}\t%0";
5949 if (! rtx_equal_p (operands[0], operands[1]))
5951 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5952 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5953 if (GET_CODE (operands[2]) == CONST_INT
5954 && (INTVAL (operands[2]) == 128
5955 || (INTVAL (operands[2]) < 0
5956 && INTVAL (operands[2]) != -128)))
5958 operands[2] = GEN_INT (-INTVAL (operands[2]));
5959 return "sub{l}\t{%2, %0|%0, %2}";
5961 return "add{l}\t{%2, %0|%0, %2}";
5965 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5966 (const_string "incdec")
5967 (const_string "alu")))
5968 (set_attr "mode" "SI")])
5970 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5971 (define_insn "*addsi_2_zext"
5974 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5975 (match_operand:SI 2 "general_operand" "rmni"))
5977 (set (match_operand:DI 0 "register_operand" "=r")
5978 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5979 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5980 && ix86_binary_operator_ok (PLUS, SImode, operands)
5981 /* Current assemblers are broken and do not allow @GOTOFF in
5982 ought but a memory context. */
5983 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5985 switch (get_attr_type (insn))
5988 if (operands[2] == const1_rtx)
5989 return "inc{l}\t%k0";
5990 else if (operands[2] == constm1_rtx)
5991 return "dec{l}\t%k0";
5996 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5997 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5998 if (GET_CODE (operands[2]) == CONST_INT
5999 && (INTVAL (operands[2]) == 128
6000 || (INTVAL (operands[2]) < 0
6001 && INTVAL (operands[2]) != -128)))
6003 operands[2] = GEN_INT (-INTVAL (operands[2]));
6004 return "sub{l}\t{%2, %k0|%k0, %2}";
6006 return "add{l}\t{%2, %k0|%k0, %2}";
6010 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6011 (const_string "incdec")
6012 (const_string "alu")))
6013 (set_attr "mode" "SI")])
6015 (define_insn "*addsi_3"
6017 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6018 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6019 (clobber (match_scratch:SI 0 "=r"))]
6020 "ix86_match_ccmode (insn, CCZmode)
6021 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6022 /* Current assemblers are broken and do not allow @GOTOFF in
6023 ought but a memory context. */
6024 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6026 switch (get_attr_type (insn))
6029 if (! rtx_equal_p (operands[0], operands[1]))
6031 if (operands[2] == const1_rtx)
6032 return "inc{l}\t%0";
6033 else if (operands[2] == constm1_rtx)
6034 return "dec{l}\t%0";
6039 if (! rtx_equal_p (operands[0], operands[1]))
6041 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6042 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6043 if (GET_CODE (operands[2]) == CONST_INT
6044 && (INTVAL (operands[2]) == 128
6045 || (INTVAL (operands[2]) < 0
6046 && INTVAL (operands[2]) != -128)))
6048 operands[2] = GEN_INT (-INTVAL (operands[2]));
6049 return "sub{l}\t{%2, %0|%0, %2}";
6051 return "add{l}\t{%2, %0|%0, %2}";
6055 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6056 (const_string "incdec")
6057 (const_string "alu")))
6058 (set_attr "mode" "SI")])
6060 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6061 (define_insn "*addsi_3_zext"
6063 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6064 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6065 (set (match_operand:DI 0 "register_operand" "=r")
6066 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6067 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6068 && ix86_binary_operator_ok (PLUS, SImode, operands)
6069 /* Current assemblers are broken and do not allow @GOTOFF in
6070 ought but a memory context. */
6071 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6073 switch (get_attr_type (insn))
6076 if (operands[2] == const1_rtx)
6077 return "inc{l}\t%k0";
6078 else if (operands[2] == constm1_rtx)
6079 return "dec{l}\t%k0";
6084 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6085 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6086 if (GET_CODE (operands[2]) == CONST_INT
6087 && (INTVAL (operands[2]) == 128
6088 || (INTVAL (operands[2]) < 0
6089 && INTVAL (operands[2]) != -128)))
6091 operands[2] = GEN_INT (-INTVAL (operands[2]));
6092 return "sub{l}\t{%2, %k0|%k0, %2}";
6094 return "add{l}\t{%2, %k0|%k0, %2}";
6098 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6099 (const_string "incdec")
6100 (const_string "alu")))
6101 (set_attr "mode" "SI")])
6103 ; For comparisons against 1, -1 and 128, we may generate better code
6104 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6105 ; is matched then. We can't accept general immediate, because for
6106 ; case of overflows, the result is messed up.
6107 ; This pattern also don't hold of 0x80000000, since the value overflows
6109 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6110 ; only for comparisons not depending on it.
6111 (define_insn "*addsi_4"
6113 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6114 (match_operand:SI 2 "const_int_operand" "n")))
6115 (clobber (match_scratch:SI 0 "=rm"))]
6116 "ix86_match_ccmode (insn, CCGCmode)
6117 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6119 switch (get_attr_type (insn))
6122 if (operands[2] == constm1_rtx)
6123 return "inc{l}\t%0";
6124 else if (operands[2] == const1_rtx)
6125 return "dec{l}\t%0";
6130 if (! rtx_equal_p (operands[0], operands[1]))
6132 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6133 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6134 if ((INTVAL (operands[2]) == -128
6135 || (INTVAL (operands[2]) > 0
6136 && INTVAL (operands[2]) != 128)))
6137 return "sub{l}\t{%2, %0|%0, %2}";
6138 operands[2] = GEN_INT (-INTVAL (operands[2]));
6139 return "add{l}\t{%2, %0|%0, %2}";
6143 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6144 (const_string "incdec")
6145 (const_string "alu")))
6146 (set_attr "mode" "SI")])
6148 (define_insn "*addsi_5"
6151 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6152 (match_operand:SI 2 "general_operand" "rmni"))
6154 (clobber (match_scratch:SI 0 "=r"))]
6155 "ix86_match_ccmode (insn, CCGOCmode)
6156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6157 /* Current assemblers are broken and do not allow @GOTOFF in
6158 ought but a memory context. */
6159 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6161 switch (get_attr_type (insn))
6164 if (! rtx_equal_p (operands[0], operands[1]))
6166 if (operands[2] == const1_rtx)
6167 return "inc{l}\t%0";
6168 else if (operands[2] == constm1_rtx)
6169 return "dec{l}\t%0";
6174 if (! rtx_equal_p (operands[0], operands[1]))
6176 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6177 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6178 if (GET_CODE (operands[2]) == CONST_INT
6179 && (INTVAL (operands[2]) == 128
6180 || (INTVAL (operands[2]) < 0
6181 && INTVAL (operands[2]) != -128)))
6183 operands[2] = GEN_INT (-INTVAL (operands[2]));
6184 return "sub{l}\t{%2, %0|%0, %2}";
6186 return "add{l}\t{%2, %0|%0, %2}";
6190 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6191 (const_string "incdec")
6192 (const_string "alu")))
6193 (set_attr "mode" "SI")])
6195 (define_expand "addhi3"
6196 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6197 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6198 (match_operand:HI 2 "general_operand" "")))
6199 (clobber (reg:CC 17))])]
6200 "TARGET_HIMODE_MATH"
6201 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6203 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6204 ;; type optimizations enabled by define-splits. This is not important
6205 ;; for PII, and in fact harmful because of partial register stalls.
6207 (define_insn "*addhi_1_lea"
6208 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6209 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6210 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6211 (clobber (reg:CC 17))]
6212 "!TARGET_PARTIAL_REG_STALL
6213 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6215 switch (get_attr_type (insn))
6220 if (operands[2] == const1_rtx)
6221 return "inc{w}\t%0";
6222 else if (operands[2] == constm1_rtx)
6223 return "dec{w}\t%0";
6227 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6228 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6229 if (GET_CODE (operands[2]) == CONST_INT
6230 && (INTVAL (operands[2]) == 128
6231 || (INTVAL (operands[2]) < 0
6232 && INTVAL (operands[2]) != -128)))
6234 operands[2] = GEN_INT (-INTVAL (operands[2]));
6235 return "sub{w}\t{%2, %0|%0, %2}";
6237 return "add{w}\t{%2, %0|%0, %2}";
6241 (if_then_else (eq_attr "alternative" "2")
6242 (const_string "lea")
6243 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6244 (const_string "incdec")
6245 (const_string "alu"))))
6246 (set_attr "mode" "HI,HI,SI")])
6248 (define_insn "*addhi_1"
6249 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6250 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6251 (match_operand:HI 2 "general_operand" "ri,rm")))
6252 (clobber (reg:CC 17))]
6253 "TARGET_PARTIAL_REG_STALL
6254 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6256 switch (get_attr_type (insn))
6259 if (operands[2] == const1_rtx)
6260 return "inc{w}\t%0";
6261 else if (operands[2] == constm1_rtx)
6262 return "dec{w}\t%0";
6266 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6267 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6268 if (GET_CODE (operands[2]) == CONST_INT
6269 && (INTVAL (operands[2]) == 128
6270 || (INTVAL (operands[2]) < 0
6271 && INTVAL (operands[2]) != -128)))
6273 operands[2] = GEN_INT (-INTVAL (operands[2]));
6274 return "sub{w}\t{%2, %0|%0, %2}";
6276 return "add{w}\t{%2, %0|%0, %2}";
6280 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6281 (const_string "incdec")
6282 (const_string "alu")))
6283 (set_attr "mode" "HI")])
6285 (define_insn "*addhi_2"
6288 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6289 (match_operand:HI 2 "general_operand" "rmni,rni"))
6291 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6292 (plus:HI (match_dup 1) (match_dup 2)))]
6293 "ix86_match_ccmode (insn, CCGOCmode)
6294 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6296 switch (get_attr_type (insn))
6299 if (operands[2] == const1_rtx)
6300 return "inc{w}\t%0";
6301 else if (operands[2] == constm1_rtx)
6302 return "dec{w}\t%0";
6306 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6307 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6308 if (GET_CODE (operands[2]) == CONST_INT
6309 && (INTVAL (operands[2]) == 128
6310 || (INTVAL (operands[2]) < 0
6311 && INTVAL (operands[2]) != -128)))
6313 operands[2] = GEN_INT (-INTVAL (operands[2]));
6314 return "sub{w}\t{%2, %0|%0, %2}";
6316 return "add{w}\t{%2, %0|%0, %2}";
6320 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6321 (const_string "incdec")
6322 (const_string "alu")))
6323 (set_attr "mode" "HI")])
6325 (define_insn "*addhi_3"
6327 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6328 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6329 (clobber (match_scratch:HI 0 "=r"))]
6330 "ix86_match_ccmode (insn, CCZmode)
6331 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6333 switch (get_attr_type (insn))
6336 if (operands[2] == const1_rtx)
6337 return "inc{w}\t%0";
6338 else if (operands[2] == constm1_rtx)
6339 return "dec{w}\t%0";
6343 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6344 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6345 if (GET_CODE (operands[2]) == CONST_INT
6346 && (INTVAL (operands[2]) == 128
6347 || (INTVAL (operands[2]) < 0
6348 && INTVAL (operands[2]) != -128)))
6350 operands[2] = GEN_INT (-INTVAL (operands[2]));
6351 return "sub{w}\t{%2, %0|%0, %2}";
6353 return "add{w}\t{%2, %0|%0, %2}";
6357 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6358 (const_string "incdec")
6359 (const_string "alu")))
6360 (set_attr "mode" "HI")])
6362 ; See comments above addsi_3_imm for details.
6363 (define_insn "*addhi_4"
6365 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6366 (match_operand:HI 2 "const_int_operand" "n")))
6367 (clobber (match_scratch:HI 0 "=rm"))]
6368 "ix86_match_ccmode (insn, CCGCmode)
6369 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6371 switch (get_attr_type (insn))
6374 if (operands[2] == constm1_rtx)
6375 return "inc{w}\t%0";
6376 else if (operands[2] == const1_rtx)
6377 return "dec{w}\t%0";
6382 if (! rtx_equal_p (operands[0], operands[1]))
6384 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6385 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6386 if ((INTVAL (operands[2]) == -128
6387 || (INTVAL (operands[2]) > 0
6388 && INTVAL (operands[2]) != 128)))
6389 return "sub{w}\t{%2, %0|%0, %2}";
6390 operands[2] = GEN_INT (-INTVAL (operands[2]));
6391 return "add{w}\t{%2, %0|%0, %2}";
6395 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6396 (const_string "incdec")
6397 (const_string "alu")))
6398 (set_attr "mode" "SI")])
6401 (define_insn "*addhi_5"
6404 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6405 (match_operand:HI 2 "general_operand" "rmni"))
6407 (clobber (match_scratch:HI 0 "=r"))]
6408 "ix86_match_ccmode (insn, CCGOCmode)
6409 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6411 switch (get_attr_type (insn))
6414 if (operands[2] == const1_rtx)
6415 return "inc{w}\t%0";
6416 else if (operands[2] == constm1_rtx)
6417 return "dec{w}\t%0";
6421 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6422 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6423 if (GET_CODE (operands[2]) == CONST_INT
6424 && (INTVAL (operands[2]) == 128
6425 || (INTVAL (operands[2]) < 0
6426 && INTVAL (operands[2]) != -128)))
6428 operands[2] = GEN_INT (-INTVAL (operands[2]));
6429 return "sub{w}\t{%2, %0|%0, %2}";
6431 return "add{w}\t{%2, %0|%0, %2}";
6435 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6436 (const_string "incdec")
6437 (const_string "alu")))
6438 (set_attr "mode" "HI")])
6440 (define_expand "addqi3"
6441 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6442 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6443 (match_operand:QI 2 "general_operand" "")))
6444 (clobber (reg:CC 17))])]
6445 "TARGET_QIMODE_MATH"
6446 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6448 ;; %%% Potential partial reg stall on alternative 2. What to do?
6449 (define_insn "*addqi_1_lea"
6450 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6451 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6452 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6453 (clobber (reg:CC 17))]
6454 "!TARGET_PARTIAL_REG_STALL
6455 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6457 int widen = (which_alternative == 2);
6458 switch (get_attr_type (insn))
6463 if (operands[2] == const1_rtx)
6464 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6465 else if (operands[2] == constm1_rtx)
6466 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6470 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6471 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6472 if (GET_CODE (operands[2]) == CONST_INT
6473 && (INTVAL (operands[2]) == 128
6474 || (INTVAL (operands[2]) < 0
6475 && INTVAL (operands[2]) != -128)))
6477 operands[2] = GEN_INT (-INTVAL (operands[2]));
6479 return "sub{l}\t{%2, %k0|%k0, %2}";
6481 return "sub{b}\t{%2, %0|%0, %2}";
6484 return "add{l}\t{%k2, %k0|%k0, %k2}";
6486 return "add{b}\t{%2, %0|%0, %2}";
6490 (if_then_else (eq_attr "alternative" "3")
6491 (const_string "lea")
6492 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6493 (const_string "incdec")
6494 (const_string "alu"))))
6495 (set_attr "mode" "QI,QI,SI,SI")])
6497 (define_insn "*addqi_1"
6498 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6499 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6500 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6501 (clobber (reg:CC 17))]
6502 "TARGET_PARTIAL_REG_STALL
6503 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6505 int widen = (which_alternative == 2);
6506 switch (get_attr_type (insn))
6509 if (operands[2] == const1_rtx)
6510 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6511 else if (operands[2] == constm1_rtx)
6512 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6516 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6517 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6518 if (GET_CODE (operands[2]) == CONST_INT
6519 && (INTVAL (operands[2]) == 128
6520 || (INTVAL (operands[2]) < 0
6521 && INTVAL (operands[2]) != -128)))
6523 operands[2] = GEN_INT (-INTVAL (operands[2]));
6525 return "sub{l}\t{%2, %k0|%k0, %2}";
6527 return "sub{b}\t{%2, %0|%0, %2}";
6530 return "add{l}\t{%k2, %k0|%k0, %k2}";
6532 return "add{b}\t{%2, %0|%0, %2}";
6536 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6537 (const_string "incdec")
6538 (const_string "alu")))
6539 (set_attr "mode" "QI,QI,SI")])
6541 (define_insn "*addqi_1_slp"
6542 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6543 (plus:QI (match_dup 0)
6544 (match_operand:QI 1 "general_operand" "qn,qnm")))
6545 (clobber (reg:CC 17))]
6546 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6547 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6549 switch (get_attr_type (insn))
6552 if (operands[1] == const1_rtx)
6553 return "inc{b}\t%0";
6554 else if (operands[1] == constm1_rtx)
6555 return "dec{b}\t%0";
6559 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6560 if (GET_CODE (operands[1]) == CONST_INT
6561 && INTVAL (operands[1]) < 0)
6563 operands[2] = GEN_INT (-INTVAL (operands[2]));
6564 return "sub{b}\t{%1, %0|%0, %1}";
6566 return "add{b}\t{%1, %0|%0, %1}";
6570 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6571 (const_string "incdec")
6572 (const_string "alu1")))
6573 (set_attr "mode" "QI")])
6575 (define_insn "*addqi_2"
6578 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6579 (match_operand:QI 2 "general_operand" "qmni,qni"))
6581 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6582 (plus:QI (match_dup 1) (match_dup 2)))]
6583 "ix86_match_ccmode (insn, CCGOCmode)
6584 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6586 switch (get_attr_type (insn))
6589 if (operands[2] == const1_rtx)
6590 return "inc{b}\t%0";
6591 else if (operands[2] == constm1_rtx
6592 || (GET_CODE (operands[2]) == CONST_INT
6593 && INTVAL (operands[2]) == 255))
6594 return "dec{b}\t%0";
6598 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6599 if (GET_CODE (operands[2]) == CONST_INT
6600 && INTVAL (operands[2]) < 0)
6602 operands[2] = GEN_INT (-INTVAL (operands[2]));
6603 return "sub{b}\t{%2, %0|%0, %2}";
6605 return "add{b}\t{%2, %0|%0, %2}";
6609 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6610 (const_string "incdec")
6611 (const_string "alu")))
6612 (set_attr "mode" "QI")])
6614 (define_insn "*addqi_3"
6616 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6617 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6618 (clobber (match_scratch:QI 0 "=q"))]
6619 "ix86_match_ccmode (insn, CCZmode)
6620 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6622 switch (get_attr_type (insn))
6625 if (operands[2] == const1_rtx)
6626 return "inc{b}\t%0";
6627 else if (operands[2] == constm1_rtx
6628 || (GET_CODE (operands[2]) == CONST_INT
6629 && INTVAL (operands[2]) == 255))
6630 return "dec{b}\t%0";
6634 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6635 if (GET_CODE (operands[2]) == CONST_INT
6636 && INTVAL (operands[2]) < 0)
6638 operands[2] = GEN_INT (-INTVAL (operands[2]));
6639 return "sub{b}\t{%2, %0|%0, %2}";
6641 return "add{b}\t{%2, %0|%0, %2}";
6645 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6646 (const_string "incdec")
6647 (const_string "alu")))
6648 (set_attr "mode" "QI")])
6650 ; See comments above addsi_3_imm for details.
6651 (define_insn "*addqi_4"
6653 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6654 (match_operand:QI 2 "const_int_operand" "n")))
6655 (clobber (match_scratch:QI 0 "=qm"))]
6656 "ix86_match_ccmode (insn, CCGCmode)
6657 && (INTVAL (operands[2]) & 0xff) != 0x80"
6659 switch (get_attr_type (insn))
6662 if (operands[2] == constm1_rtx
6663 || (GET_CODE (operands[2]) == CONST_INT
6664 && INTVAL (operands[2]) == 255))
6665 return "inc{b}\t%0";
6666 else if (operands[2] == const1_rtx)
6667 return "dec{b}\t%0";
6672 if (! rtx_equal_p (operands[0], operands[1]))
6674 if (INTVAL (operands[2]) < 0)
6676 operands[2] = GEN_INT (-INTVAL (operands[2]));
6677 return "add{b}\t{%2, %0|%0, %2}";
6679 return "sub{b}\t{%2, %0|%0, %2}";
6683 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6684 (const_string "incdec")
6685 (const_string "alu")))
6686 (set_attr "mode" "QI")])
6689 (define_insn "*addqi_5"
6692 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6693 (match_operand:QI 2 "general_operand" "qmni"))
6695 (clobber (match_scratch:QI 0 "=q"))]
6696 "ix86_match_ccmode (insn, CCGOCmode)
6697 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6699 switch (get_attr_type (insn))
6702 if (operands[2] == const1_rtx)
6703 return "inc{b}\t%0";
6704 else if (operands[2] == constm1_rtx
6705 || (GET_CODE (operands[2]) == CONST_INT
6706 && INTVAL (operands[2]) == 255))
6707 return "dec{b}\t%0";
6711 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6712 if (GET_CODE (operands[2]) == CONST_INT
6713 && INTVAL (operands[2]) < 0)
6715 operands[2] = GEN_INT (-INTVAL (operands[2]));
6716 return "sub{b}\t{%2, %0|%0, %2}";
6718 return "add{b}\t{%2, %0|%0, %2}";
6722 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6723 (const_string "incdec")
6724 (const_string "alu")))
6725 (set_attr "mode" "QI")])
6728 (define_insn "addqi_ext_1"
6729 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6734 (match_operand 1 "ext_register_operand" "0")
6737 (match_operand:QI 2 "general_operand" "Qmn")))
6738 (clobber (reg:CC 17))]
6741 switch (get_attr_type (insn))
6744 if (operands[2] == const1_rtx)
6745 return "inc{b}\t%h0";
6746 else if (operands[2] == constm1_rtx
6747 || (GET_CODE (operands[2]) == CONST_INT
6748 && INTVAL (operands[2]) == 255))
6749 return "dec{b}\t%h0";
6753 return "add{b}\t{%2, %h0|%h0, %2}";
6757 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6758 (const_string "incdec")
6759 (const_string "alu")))
6760 (set_attr "mode" "QI")])
6762 (define_insn "*addqi_ext_1_rex64"
6763 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6768 (match_operand 1 "ext_register_operand" "0")
6771 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6772 (clobber (reg:CC 17))]
6775 switch (get_attr_type (insn))
6778 if (operands[2] == const1_rtx)
6779 return "inc{b}\t%h0";
6780 else if (operands[2] == constm1_rtx
6781 || (GET_CODE (operands[2]) == CONST_INT
6782 && INTVAL (operands[2]) == 255))
6783 return "dec{b}\t%h0";
6787 return "add{b}\t{%2, %h0|%h0, %2}";
6791 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6792 (const_string "incdec")
6793 (const_string "alu")))
6794 (set_attr "mode" "QI")])
6796 (define_insn "*addqi_ext_2"
6797 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6802 (match_operand 1 "ext_register_operand" "%0")
6806 (match_operand 2 "ext_register_operand" "Q")
6809 (clobber (reg:CC 17))]
6811 "add{b}\t{%h2, %h0|%h0, %h2}"
6812 [(set_attr "type" "alu")
6813 (set_attr "mode" "QI")])
6815 ;; The patterns that match these are at the end of this file.
6817 (define_expand "addxf3"
6818 [(set (match_operand:XF 0 "register_operand" "")
6819 (plus:XF (match_operand:XF 1 "register_operand" "")
6820 (match_operand:XF 2 "register_operand" "")))]
6821 "!TARGET_64BIT && TARGET_80387"
6824 (define_expand "addtf3"
6825 [(set (match_operand:TF 0 "register_operand" "")
6826 (plus:TF (match_operand:TF 1 "register_operand" "")
6827 (match_operand:TF 2 "register_operand" "")))]
6831 (define_expand "adddf3"
6832 [(set (match_operand:DF 0 "register_operand" "")
6833 (plus:DF (match_operand:DF 1 "register_operand" "")
6834 (match_operand:DF 2 "nonimmediate_operand" "")))]
6835 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6838 (define_expand "addsf3"
6839 [(set (match_operand:SF 0 "register_operand" "")
6840 (plus:SF (match_operand:SF 1 "register_operand" "")
6841 (match_operand:SF 2 "nonimmediate_operand" "")))]
6842 "TARGET_80387 || TARGET_SSE_MATH"
6845 ;; Subtract instructions
6847 ;; %%% splits for subsidi3
6849 (define_expand "subdi3"
6850 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6851 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6852 (match_operand:DI 2 "x86_64_general_operand" "")))
6853 (clobber (reg:CC 17))])]
6855 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6857 (define_insn "*subdi3_1"
6858 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6859 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6860 (match_operand:DI 2 "general_operand" "roiF,riF")))
6861 (clobber (reg:CC 17))]
6862 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6866 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6867 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6868 (match_operand:DI 2 "general_operand" "")))
6869 (clobber (reg:CC 17))]
6870 "!TARGET_64BIT && reload_completed"
6871 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6872 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6873 (parallel [(set (match_dup 3)
6874 (minus:SI (match_dup 4)
6875 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6877 (clobber (reg:CC 17))])]
6878 "split_di (operands+0, 1, operands+0, operands+3);
6879 split_di (operands+1, 1, operands+1, operands+4);
6880 split_di (operands+2, 1, operands+2, operands+5);")
6882 (define_insn "subdi3_carry_rex64"
6883 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6884 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6885 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6886 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6887 (clobber (reg:CC 17))]
6888 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6889 "sbb{q}\t{%2, %0|%0, %2}"
6890 [(set_attr "type" "alu")
6891 (set_attr "pent_pair" "pu")
6892 (set_attr "ppro_uops" "few")
6893 (set_attr "mode" "DI")])
6895 (define_insn "*subdi_1_rex64"
6896 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6897 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6898 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6899 (clobber (reg:CC 17))]
6900 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6901 "sub{q}\t{%2, %0|%0, %2}"
6902 [(set_attr "type" "alu")
6903 (set_attr "mode" "DI")])
6905 (define_insn "*subdi_2_rex64"
6908 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6909 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6911 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6912 (minus:DI (match_dup 1) (match_dup 2)))]
6913 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6914 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6915 "sub{q}\t{%2, %0|%0, %2}"
6916 [(set_attr "type" "alu")
6917 (set_attr "mode" "DI")])
6919 (define_insn "*subdi_3_rex63"
6921 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6922 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6923 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6924 (minus:DI (match_dup 1) (match_dup 2)))]
6925 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6926 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6927 "sub{q}\t{%2, %0|%0, %2}"
6928 [(set_attr "type" "alu")
6929 (set_attr "mode" "DI")])
6931 (define_insn "subqi3_carry"
6932 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
6933 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6934 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6935 (match_operand:QI 2 "general_operand" "ri,rm"))))
6936 (clobber (reg:CC 17))]
6937 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6938 "sbb{b}\t{%2, %0|%0, %2}"
6939 [(set_attr "type" "alu")
6940 (set_attr "pent_pair" "pu")
6941 (set_attr "ppro_uops" "few")
6942 (set_attr "mode" "QI")])
6944 (define_insn "subhi3_carry"
6945 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6946 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6947 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6948 (match_operand:HI 2 "general_operand" "ri,rm"))))
6949 (clobber (reg:CC 17))]
6950 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6951 "sbb{w}\t{%2, %0|%0, %2}"
6952 [(set_attr "type" "alu")
6953 (set_attr "pent_pair" "pu")
6954 (set_attr "ppro_uops" "few")
6955 (set_attr "mode" "HI")])
6957 (define_insn "subsi3_carry"
6958 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6959 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6960 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6961 (match_operand:SI 2 "general_operand" "ri,rm"))))
6962 (clobber (reg:CC 17))]
6963 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6964 "sbb{l}\t{%2, %0|%0, %2}"
6965 [(set_attr "type" "alu")
6966 (set_attr "pent_pair" "pu")
6967 (set_attr "ppro_uops" "few")
6968 (set_attr "mode" "SI")])
6970 (define_insn "subsi3_carry_zext"
6971 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6973 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6974 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6975 (match_operand:SI 2 "general_operand" "ri,rm")))))
6976 (clobber (reg:CC 17))]
6977 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6978 "sbb{l}\t{%2, %k0|%k0, %2}"
6979 [(set_attr "type" "alu")
6980 (set_attr "pent_pair" "pu")
6981 (set_attr "ppro_uops" "few")
6982 (set_attr "mode" "SI")])
6984 (define_expand "subsi3"
6985 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6986 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6987 (match_operand:SI 2 "general_operand" "")))
6988 (clobber (reg:CC 17))])]
6990 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6992 (define_insn "*subsi_1"
6993 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6994 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6995 (match_operand:SI 2 "general_operand" "ri,rm")))
6996 (clobber (reg:CC 17))]
6997 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6998 "sub{l}\t{%2, %0|%0, %2}"
6999 [(set_attr "type" "alu")
7000 (set_attr "mode" "SI")])
7002 (define_insn "*subsi_1_zext"
7003 [(set (match_operand:DI 0 "register_operand" "=r")
7005 (minus:SI (match_operand:SI 1 "register_operand" "0")
7006 (match_operand:SI 2 "general_operand" "rim"))))
7007 (clobber (reg:CC 17))]
7008 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7009 "sub{l}\t{%2, %k0|%k0, %2}"
7010 [(set_attr "type" "alu")
7011 (set_attr "mode" "SI")])
7013 (define_insn "*subsi_2"
7016 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7017 (match_operand:SI 2 "general_operand" "ri,rm"))
7019 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7020 (minus:SI (match_dup 1) (match_dup 2)))]
7021 "ix86_match_ccmode (insn, CCGOCmode)
7022 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7023 "sub{l}\t{%2, %0|%0, %2}"
7024 [(set_attr "type" "alu")
7025 (set_attr "mode" "SI")])
7027 (define_insn "*subsi_2_zext"
7030 (minus:SI (match_operand:SI 1 "register_operand" "0")
7031 (match_operand:SI 2 "general_operand" "rim"))
7033 (set (match_operand:DI 0 "register_operand" "=r")
7035 (minus:SI (match_dup 1)
7037 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7038 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7039 "sub{l}\t{%2, %k0|%k0, %2}"
7040 [(set_attr "type" "alu")
7041 (set_attr "mode" "SI")])
7043 (define_insn "*subsi_3"
7045 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7046 (match_operand:SI 2 "general_operand" "ri,rm")))
7047 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7048 (minus:SI (match_dup 1) (match_dup 2)))]
7049 "ix86_match_ccmode (insn, CCmode)
7050 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7051 "sub{l}\t{%2, %0|%0, %2}"
7052 [(set_attr "type" "alu")
7053 (set_attr "mode" "SI")])
7055 (define_insn "*subsi_3_zext"
7057 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7058 (match_operand:SI 2 "general_operand" "rim")))
7059 (set (match_operand:DI 0 "register_operand" "=r")
7061 (minus:SI (match_dup 1)
7063 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7064 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7065 "sub{q}\t{%2, %0|%0, %2}"
7066 [(set_attr "type" "alu")
7067 (set_attr "mode" "DI")])
7069 (define_expand "subhi3"
7070 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7071 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7072 (match_operand:HI 2 "general_operand" "")))
7073 (clobber (reg:CC 17))])]
7074 "TARGET_HIMODE_MATH"
7075 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7077 (define_insn "*subhi_1"
7078 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7079 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7080 (match_operand:HI 2 "general_operand" "ri,rm")))
7081 (clobber (reg:CC 17))]
7082 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7083 "sub{w}\t{%2, %0|%0, %2}"
7084 [(set_attr "type" "alu")
7085 (set_attr "mode" "HI")])
7087 (define_insn "*subhi_2"
7090 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7091 (match_operand:HI 2 "general_operand" "ri,rm"))
7093 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7094 (minus:HI (match_dup 1) (match_dup 2)))]
7095 "ix86_match_ccmode (insn, CCGOCmode)
7096 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7097 "sub{w}\t{%2, %0|%0, %2}"
7098 [(set_attr "type" "alu")
7099 (set_attr "mode" "HI")])
7101 (define_insn "*subhi_3"
7103 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7104 (match_operand:HI 2 "general_operand" "ri,rm")))
7105 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7106 (minus:HI (match_dup 1) (match_dup 2)))]
7107 "ix86_match_ccmode (insn, CCmode)
7108 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7109 "sub{w}\t{%2, %0|%0, %2}"
7110 [(set_attr "type" "alu")
7111 (set_attr "mode" "HI")])
7113 (define_expand "subqi3"
7114 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7115 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7116 (match_operand:QI 2 "general_operand" "")))
7117 (clobber (reg:CC 17))])]
7118 "TARGET_QIMODE_MATH"
7119 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7121 (define_insn "*subqi_1"
7122 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7123 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7124 (match_operand:QI 2 "general_operand" "qn,qmn")))
7125 (clobber (reg:CC 17))]
7126 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7127 "sub{b}\t{%2, %0|%0, %2}"
7128 [(set_attr "type" "alu")
7129 (set_attr "mode" "QI")])
7131 (define_insn "*subqi_1_slp"
7132 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7133 (minus:QI (match_dup 0)
7134 (match_operand:QI 1 "general_operand" "qn,qmn")))
7135 (clobber (reg:CC 17))]
7136 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
7137 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7138 "sub{b}\t{%1, %0|%0, %1}"
7139 [(set_attr "type" "alu1")
7140 (set_attr "mode" "QI")])
7142 (define_insn "*subqi_2"
7145 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7146 (match_operand:QI 2 "general_operand" "qi,qm"))
7148 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7149 (minus:HI (match_dup 1) (match_dup 2)))]
7150 "ix86_match_ccmode (insn, CCGOCmode)
7151 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7152 "sub{b}\t{%2, %0|%0, %2}"
7153 [(set_attr "type" "alu")
7154 (set_attr "mode" "QI")])
7156 (define_insn "*subqi_3"
7158 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7159 (match_operand:QI 2 "general_operand" "qi,qm")))
7160 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7161 (minus:HI (match_dup 1) (match_dup 2)))]
7162 "ix86_match_ccmode (insn, CCmode)
7163 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7164 "sub{b}\t{%2, %0|%0, %2}"
7165 [(set_attr "type" "alu")
7166 (set_attr "mode" "QI")])
7168 ;; The patterns that match these are at the end of this file.
7170 (define_expand "subxf3"
7171 [(set (match_operand:XF 0 "register_operand" "")
7172 (minus:XF (match_operand:XF 1 "register_operand" "")
7173 (match_operand:XF 2 "register_operand" "")))]
7174 "!TARGET_64BIT && TARGET_80387"
7177 (define_expand "subtf3"
7178 [(set (match_operand:TF 0 "register_operand" "")
7179 (minus:TF (match_operand:TF 1 "register_operand" "")
7180 (match_operand:TF 2 "register_operand" "")))]
7184 (define_expand "subdf3"
7185 [(set (match_operand:DF 0 "register_operand" "")
7186 (minus:DF (match_operand:DF 1 "register_operand" "")
7187 (match_operand:DF 2 "nonimmediate_operand" "")))]
7188 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7191 (define_expand "subsf3"
7192 [(set (match_operand:SF 0 "register_operand" "")
7193 (minus:SF (match_operand:SF 1 "register_operand" "")
7194 (match_operand:SF 2 "nonimmediate_operand" "")))]
7195 "TARGET_80387 || TARGET_SSE_MATH"
7198 ;; Multiply instructions
7200 (define_expand "muldi3"
7201 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7202 (mult:DI (match_operand:DI 1 "register_operand" "")
7203 (match_operand:DI 2 "x86_64_general_operand" "")))
7204 (clobber (reg:CC 17))])]
7208 (define_insn "*muldi3_1_rex64"
7209 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7210 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
7211 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7212 (clobber (reg:CC 17))]
7214 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7216 imul{q}\t{%2, %1, %0|%0, %1, %2}
7217 imul{q}\t{%2, %1, %0|%0, %1, %2}
7218 imul{q}\t{%2, %0|%0, %2}"
7219 [(set_attr "type" "imul")
7220 (set_attr "prefix_0f" "0,0,1")
7221 (set (attr "athlon_decode")
7222 (cond [(eq_attr "cpu" "athlon")
7223 (const_string "vector")
7224 (eq_attr "alternative" "1")
7225 (const_string "vector")
7226 (and (eq_attr "alternative" "2")
7227 (match_operand 1 "memory_operand" ""))
7228 (const_string "vector")]
7229 (const_string "direct")))
7230 (set_attr "mode" "DI")])
7232 (define_expand "mulsi3"
7233 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7234 (mult:SI (match_operand:SI 1 "register_operand" "")
7235 (match_operand:SI 2 "general_operand" "")))
7236 (clobber (reg:CC 17))])]
7240 (define_insn "*mulsi3_1"
7241 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7242 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7243 (match_operand:SI 2 "general_operand" "K,i,mr")))
7244 (clobber (reg:CC 17))]
7245 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7247 imul{l}\t{%2, %1, %0|%0, %1, %2}
7248 imul{l}\t{%2, %1, %0|%0, %1, %2}
7249 imul{l}\t{%2, %0|%0, %2}"
7250 [(set_attr "type" "imul")
7251 (set_attr "prefix_0f" "0,0,1")
7252 (set (attr "athlon_decode")
7253 (cond [(eq_attr "cpu" "athlon")
7254 (const_string "vector")
7255 (eq_attr "alternative" "1")
7256 (const_string "vector")
7257 (and (eq_attr "alternative" "2")
7258 (match_operand 1 "memory_operand" ""))
7259 (const_string "vector")]
7260 (const_string "direct")))
7261 (set_attr "mode" "SI")])
7263 (define_insn "*mulsi3_1_zext"
7264 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7266 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7267 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7268 (clobber (reg:CC 17))]
7270 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7272 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7273 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7274 imul{l}\t{%2, %k0|%k0, %2}"
7275 [(set_attr "type" "imul")
7276 (set_attr "prefix_0f" "0,0,1")
7277 (set (attr "athlon_decode")
7278 (cond [(eq_attr "cpu" "athlon")
7279 (const_string "vector")
7280 (eq_attr "alternative" "1")
7281 (const_string "vector")
7282 (and (eq_attr "alternative" "2")
7283 (match_operand 1 "memory_operand" ""))
7284 (const_string "vector")]
7285 (const_string "direct")))
7286 (set_attr "mode" "SI")])
7288 (define_expand "mulhi3"
7289 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7290 (mult:HI (match_operand:HI 1 "register_operand" "")
7291 (match_operand:HI 2 "general_operand" "")))
7292 (clobber (reg:CC 17))])]
7293 "TARGET_HIMODE_MATH"
7296 (define_insn "*mulhi3_1"
7297 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7298 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7299 (match_operand:HI 2 "general_operand" "K,i,mr")))
7300 (clobber (reg:CC 17))]
7301 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7303 imul{w}\t{%2, %1, %0|%0, %1, %2}
7304 imul{w}\t{%2, %1, %0|%0, %1, %2}
7305 imul{w}\t{%2, %0|%0, %2}"
7306 [(set_attr "type" "imul")
7307 (set_attr "prefix_0f" "0,0,1")
7308 (set (attr "athlon_decode")
7309 (cond [(eq_attr "cpu" "athlon")
7310 (const_string "vector")
7311 (eq_attr "alternative" "1,2")
7312 (const_string "vector")]
7313 (const_string "direct")))
7314 (set_attr "mode" "HI")])
7316 (define_expand "mulqi3"
7317 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7318 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7319 (match_operand:QI 2 "register_operand" "")))
7320 (clobber (reg:CC 17))])]
7321 "TARGET_QIMODE_MATH"
7324 (define_insn "*mulqi3_1"
7325 [(set (match_operand:QI 0 "register_operand" "=a")
7326 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7327 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7328 (clobber (reg:CC 17))]
7330 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7332 [(set_attr "type" "imul")
7333 (set_attr "length_immediate" "0")
7334 (set (attr "athlon_decode")
7335 (if_then_else (eq_attr "cpu" "athlon")
7336 (const_string "vector")
7337 (const_string "direct")))
7338 (set_attr "mode" "QI")])
7340 (define_expand "umulqihi3"
7341 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7342 (mult:HI (zero_extend:HI
7343 (match_operand:QI 1 "nonimmediate_operand" ""))
7345 (match_operand:QI 2 "register_operand" ""))))
7346 (clobber (reg:CC 17))])]
7347 "TARGET_QIMODE_MATH"
7350 (define_insn "*umulqihi3_1"
7351 [(set (match_operand:HI 0 "register_operand" "=a")
7352 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7353 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7354 (clobber (reg:CC 17))]
7356 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7358 [(set_attr "type" "imul")
7359 (set_attr "length_immediate" "0")
7360 (set (attr "athlon_decode")
7361 (if_then_else (eq_attr "cpu" "athlon")
7362 (const_string "vector")
7363 (const_string "direct")))
7364 (set_attr "mode" "QI")])
7366 (define_expand "mulqihi3"
7367 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7368 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7369 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7370 (clobber (reg:CC 17))])]
7371 "TARGET_QIMODE_MATH"
7374 (define_insn "*mulqihi3_insn"
7375 [(set (match_operand:HI 0 "register_operand" "=a")
7376 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7377 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7378 (clobber (reg:CC 17))]
7380 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7382 [(set_attr "type" "imul")
7383 (set_attr "length_immediate" "0")
7384 (set (attr "athlon_decode")
7385 (if_then_else (eq_attr "cpu" "athlon")
7386 (const_string "vector")
7387 (const_string "direct")))
7388 (set_attr "mode" "QI")])
7390 (define_expand "umulditi3"
7391 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7392 (mult:TI (zero_extend:TI
7393 (match_operand:DI 1 "nonimmediate_operand" ""))
7395 (match_operand:DI 2 "register_operand" ""))))
7396 (clobber (reg:CC 17))])]
7400 (define_insn "*umulditi3_insn"
7401 [(set (match_operand:TI 0 "register_operand" "=A")
7402 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7403 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7404 (clobber (reg:CC 17))]
7406 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7408 [(set_attr "type" "imul")
7409 (set_attr "ppro_uops" "few")
7410 (set_attr "length_immediate" "0")
7411 (set (attr "athlon_decode")
7412 (if_then_else (eq_attr "cpu" "athlon")
7413 (const_string "vector")
7414 (const_string "double")))
7415 (set_attr "mode" "DI")])
7417 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7418 (define_expand "umulsidi3"
7419 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7420 (mult:DI (zero_extend:DI
7421 (match_operand:SI 1 "nonimmediate_operand" ""))
7423 (match_operand:SI 2 "register_operand" ""))))
7424 (clobber (reg:CC 17))])]
7428 (define_insn "*umulsidi3_insn"
7429 [(set (match_operand:DI 0 "register_operand" "=A")
7430 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7431 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7432 (clobber (reg:CC 17))]
7434 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7436 [(set_attr "type" "imul")
7437 (set_attr "ppro_uops" "few")
7438 (set_attr "length_immediate" "0")
7439 (set (attr "athlon_decode")
7440 (if_then_else (eq_attr "cpu" "athlon")
7441 (const_string "vector")
7442 (const_string "double")))
7443 (set_attr "mode" "SI")])
7445 (define_expand "mulditi3"
7446 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7447 (mult:TI (sign_extend:TI
7448 (match_operand:DI 1 "nonimmediate_operand" ""))
7450 (match_operand:DI 2 "register_operand" ""))))
7451 (clobber (reg:CC 17))])]
7455 (define_insn "*mulditi3_insn"
7456 [(set (match_operand:TI 0 "register_operand" "=A")
7457 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7458 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7459 (clobber (reg:CC 17))]
7461 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7463 [(set_attr "type" "imul")
7464 (set_attr "length_immediate" "0")
7465 (set (attr "athlon_decode")
7466 (if_then_else (eq_attr "cpu" "athlon")
7467 (const_string "vector")
7468 (const_string "double")))
7469 (set_attr "mode" "DI")])
7471 (define_expand "mulsidi3"
7472 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7473 (mult:DI (sign_extend:DI
7474 (match_operand:SI 1 "nonimmediate_operand" ""))
7476 (match_operand:SI 2 "register_operand" ""))))
7477 (clobber (reg:CC 17))])]
7481 (define_insn "*mulsidi3_insn"
7482 [(set (match_operand:DI 0 "register_operand" "=A")
7483 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7484 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7485 (clobber (reg:CC 17))]
7487 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7489 [(set_attr "type" "imul")
7490 (set_attr "length_immediate" "0")
7491 (set (attr "athlon_decode")
7492 (if_then_else (eq_attr "cpu" "athlon")
7493 (const_string "vector")
7494 (const_string "double")))
7495 (set_attr "mode" "SI")])
7497 (define_expand "umuldi3_highpart"
7498 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7501 (mult:TI (zero_extend:TI
7502 (match_operand:DI 1 "nonimmediate_operand" ""))
7504 (match_operand:DI 2 "register_operand" "")))
7506 (clobber (match_scratch:DI 3 ""))
7507 (clobber (reg:CC 17))])]
7511 (define_insn "*umuldi3_highpart_rex64"
7512 [(set (match_operand:DI 0 "register_operand" "=d")
7515 (mult:TI (zero_extend:TI
7516 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7518 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7520 (clobber (match_scratch:DI 3 "=1"))
7521 (clobber (reg:CC 17))]
7523 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7525 [(set_attr "type" "imul")
7526 (set_attr "ppro_uops" "few")
7527 (set_attr "length_immediate" "0")
7528 (set (attr "athlon_decode")
7529 (if_then_else (eq_attr "cpu" "athlon")
7530 (const_string "vector")
7531 (const_string "double")))
7532 (set_attr "mode" "DI")])
7534 (define_expand "umulsi3_highpart"
7535 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7538 (mult:DI (zero_extend:DI
7539 (match_operand:SI 1 "nonimmediate_operand" ""))
7541 (match_operand:SI 2 "register_operand" "")))
7543 (clobber (match_scratch:SI 3 ""))
7544 (clobber (reg:CC 17))])]
7548 (define_insn "*umulsi3_highpart_insn"
7549 [(set (match_operand:SI 0 "register_operand" "=d")
7552 (mult:DI (zero_extend:DI
7553 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7555 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7557 (clobber (match_scratch:SI 3 "=1"))
7558 (clobber (reg:CC 17))]
7559 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7561 [(set_attr "type" "imul")
7562 (set_attr "ppro_uops" "few")
7563 (set_attr "length_immediate" "0")
7564 (set (attr "athlon_decode")
7565 (if_then_else (eq_attr "cpu" "athlon")
7566 (const_string "vector")
7567 (const_string "double")))
7568 (set_attr "mode" "SI")])
7570 (define_insn "*umulsi3_highpart_zext"
7571 [(set (match_operand:DI 0 "register_operand" "=d")
7572 (zero_extend:DI (truncate:SI
7574 (mult:DI (zero_extend:DI
7575 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7577 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7579 (clobber (match_scratch:SI 3 "=1"))
7580 (clobber (reg:CC 17))]
7582 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7584 [(set_attr "type" "imul")
7585 (set_attr "ppro_uops" "few")
7586 (set_attr "length_immediate" "0")
7587 (set (attr "athlon_decode")
7588 (if_then_else (eq_attr "cpu" "athlon")
7589 (const_string "vector")
7590 (const_string "double")))
7591 (set_attr "mode" "SI")])
7593 (define_expand "smuldi3_highpart"
7594 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7597 (mult:TI (sign_extend:TI
7598 (match_operand:DI 1 "nonimmediate_operand" ""))
7600 (match_operand:DI 2 "register_operand" "")))
7602 (clobber (match_scratch:DI 3 ""))
7603 (clobber (reg:CC 17))])]
7607 (define_insn "*smuldi3_highpart_rex64"
7608 [(set (match_operand:DI 0 "register_operand" "=d")
7611 (mult:TI (sign_extend:TI
7612 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7614 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7616 (clobber (match_scratch:DI 3 "=1"))
7617 (clobber (reg:CC 17))]
7619 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7621 [(set_attr "type" "imul")
7622 (set_attr "ppro_uops" "few")
7623 (set (attr "athlon_decode")
7624 (if_then_else (eq_attr "cpu" "athlon")
7625 (const_string "vector")
7626 (const_string "double")))
7627 (set_attr "mode" "DI")])
7629 (define_expand "smulsi3_highpart"
7630 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7633 (mult:DI (sign_extend:DI
7634 (match_operand:SI 1 "nonimmediate_operand" ""))
7636 (match_operand:SI 2 "register_operand" "")))
7638 (clobber (match_scratch:SI 3 ""))
7639 (clobber (reg:CC 17))])]
7643 (define_insn "*smulsi3_highpart_insn"
7644 [(set (match_operand:SI 0 "register_operand" "=d")
7647 (mult:DI (sign_extend:DI
7648 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7650 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7652 (clobber (match_scratch:SI 3 "=1"))
7653 (clobber (reg:CC 17))]
7654 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7656 [(set_attr "type" "imul")
7657 (set_attr "ppro_uops" "few")
7658 (set (attr "athlon_decode")
7659 (if_then_else (eq_attr "cpu" "athlon")
7660 (const_string "vector")
7661 (const_string "double")))
7662 (set_attr "mode" "SI")])
7664 (define_insn "*smulsi3_highpart_zext"
7665 [(set (match_operand:DI 0 "register_operand" "=d")
7666 (zero_extend:DI (truncate:SI
7668 (mult:DI (sign_extend:DI
7669 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7671 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7673 (clobber (match_scratch:SI 3 "=1"))
7674 (clobber (reg:CC 17))]
7676 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7678 [(set_attr "type" "imul")
7679 (set_attr "ppro_uops" "few")
7680 (set (attr "athlon_decode")
7681 (if_then_else (eq_attr "cpu" "athlon")
7682 (const_string "vector")
7683 (const_string "double")))
7684 (set_attr "mode" "SI")])
7686 ;; The patterns that match these are at the end of this file.
7688 (define_expand "mulxf3"
7689 [(set (match_operand:XF 0 "register_operand" "")
7690 (mult:XF (match_operand:XF 1 "register_operand" "")
7691 (match_operand:XF 2 "register_operand" "")))]
7692 "!TARGET_64BIT && TARGET_80387"
7695 (define_expand "multf3"
7696 [(set (match_operand:TF 0 "register_operand" "")
7697 (mult:TF (match_operand:TF 1 "register_operand" "")
7698 (match_operand:TF 2 "register_operand" "")))]
7702 (define_expand "muldf3"
7703 [(set (match_operand:DF 0 "register_operand" "")
7704 (mult:DF (match_operand:DF 1 "register_operand" "")
7705 (match_operand:DF 2 "nonimmediate_operand" "")))]
7706 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7709 (define_expand "mulsf3"
7710 [(set (match_operand:SF 0 "register_operand" "")
7711 (mult:SF (match_operand:SF 1 "register_operand" "")
7712 (match_operand:SF 2 "nonimmediate_operand" "")))]
7713 "TARGET_80387 || TARGET_SSE_MATH"
7716 ;; Divide instructions
7718 (define_insn "divqi3"
7719 [(set (match_operand:QI 0 "register_operand" "=a")
7720 (div:QI (match_operand:HI 1 "register_operand" "0")
7721 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7722 (clobber (reg:CC 17))]
7723 "TARGET_QIMODE_MATH"
7725 [(set_attr "type" "idiv")
7726 (set_attr "mode" "QI")
7727 (set_attr "ppro_uops" "few")])
7729 (define_insn "udivqi3"
7730 [(set (match_operand:QI 0 "register_operand" "=a")
7731 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7732 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7733 (clobber (reg:CC 17))]
7734 "TARGET_QIMODE_MATH"
7736 [(set_attr "type" "idiv")
7737 (set_attr "mode" "QI")
7738 (set_attr "ppro_uops" "few")])
7740 ;; The patterns that match these are at the end of this file.
7742 (define_expand "divxf3"
7743 [(set (match_operand:XF 0 "register_operand" "")
7744 (div:XF (match_operand:XF 1 "register_operand" "")
7745 (match_operand:XF 2 "register_operand" "")))]
7746 "!TARGET_64BIT && TARGET_80387"
7749 (define_expand "divtf3"
7750 [(set (match_operand:TF 0 "register_operand" "")
7751 (div:TF (match_operand:TF 1 "register_operand" "")
7752 (match_operand:TF 2 "register_operand" "")))]
7756 (define_expand "divdf3"
7757 [(set (match_operand:DF 0 "register_operand" "")
7758 (div:DF (match_operand:DF 1 "register_operand" "")
7759 (match_operand:DF 2 "nonimmediate_operand" "")))]
7760 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7763 (define_expand "divsf3"
7764 [(set (match_operand:SF 0 "register_operand" "")
7765 (div:SF (match_operand:SF 1 "register_operand" "")
7766 (match_operand:SF 2 "nonimmediate_operand" "")))]
7767 "TARGET_80387 || TARGET_SSE_MATH"
7770 ;; Remainder instructions.
7772 (define_expand "divmoddi4"
7773 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7774 (div:DI (match_operand:DI 1 "register_operand" "")
7775 (match_operand:DI 2 "nonimmediate_operand" "")))
7776 (set (match_operand:DI 3 "register_operand" "")
7777 (mod:DI (match_dup 1) (match_dup 2)))
7778 (clobber (reg:CC 17))])]
7782 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7783 ;; Penalize eax case slightly because it results in worse scheduling
7785 (define_insn "*divmoddi4_nocltd_rex64"
7786 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7787 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7788 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7789 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7790 (mod:DI (match_dup 2) (match_dup 3)))
7791 (clobber (reg:CC 17))]
7792 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7794 [(set_attr "type" "multi")])
7796 (define_insn "*divmoddi4_cltd_rex64"
7797 [(set (match_operand:DI 0 "register_operand" "=a")
7798 (div:DI (match_operand:DI 2 "register_operand" "a")
7799 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7800 (set (match_operand:DI 1 "register_operand" "=&d")
7801 (mod:DI (match_dup 2) (match_dup 3)))
7802 (clobber (reg:CC 17))]
7803 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7805 [(set_attr "type" "multi")])
7807 (define_insn "*divmoddi_noext_rex64"
7808 [(set (match_operand:DI 0 "register_operand" "=a")
7809 (div:DI (match_operand:DI 1 "register_operand" "0")
7810 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7811 (set (match_operand:DI 3 "register_operand" "=d")
7812 (mod:DI (match_dup 1) (match_dup 2)))
7813 (use (match_operand:DI 4 "register_operand" "3"))
7814 (clobber (reg:CC 17))]
7817 [(set_attr "type" "idiv")
7818 (set_attr "mode" "DI")
7819 (set_attr "ppro_uops" "few")])
7822 [(set (match_operand:DI 0 "register_operand" "")
7823 (div:DI (match_operand:DI 1 "register_operand" "")
7824 (match_operand:DI 2 "nonimmediate_operand" "")))
7825 (set (match_operand:DI 3 "register_operand" "")
7826 (mod:DI (match_dup 1) (match_dup 2)))
7827 (clobber (reg:CC 17))]
7828 "TARGET_64BIT && reload_completed"
7829 [(parallel [(set (match_dup 3)
7830 (ashiftrt:DI (match_dup 4) (const_int 63)))
7831 (clobber (reg:CC 17))])
7832 (parallel [(set (match_dup 0)
7833 (div:DI (reg:DI 0) (match_dup 2)))
7835 (mod:DI (reg:DI 0) (match_dup 2)))
7837 (clobber (reg:CC 17))])]
7839 /* Avoid use of cltd in favor of a mov+shift. */
7840 if (!TARGET_USE_CLTD && !optimize_size)
7842 if (true_regnum (operands[1]))
7843 emit_move_insn (operands[0], operands[1]);
7845 emit_move_insn (operands[3], operands[1]);
7846 operands[4] = operands[3];
7850 if (true_regnum (operands[1]))
7852 operands[4] = operands[1];
7857 (define_expand "divmodsi4"
7858 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7859 (div:SI (match_operand:SI 1 "register_operand" "")
7860 (match_operand:SI 2 "nonimmediate_operand" "")))
7861 (set (match_operand:SI 3 "register_operand" "")
7862 (mod:SI (match_dup 1) (match_dup 2)))
7863 (clobber (reg:CC 17))])]
7867 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7868 ;; Penalize eax case slightly because it results in worse scheduling
7870 (define_insn "*divmodsi4_nocltd"
7871 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7872 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7873 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7874 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7875 (mod:SI (match_dup 2) (match_dup 3)))
7876 (clobber (reg:CC 17))]
7877 "!optimize_size && !TARGET_USE_CLTD"
7879 [(set_attr "type" "multi")])
7881 (define_insn "*divmodsi4_cltd"
7882 [(set (match_operand:SI 0 "register_operand" "=a")
7883 (div:SI (match_operand:SI 2 "register_operand" "a")
7884 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7885 (set (match_operand:SI 1 "register_operand" "=&d")
7886 (mod:SI (match_dup 2) (match_dup 3)))
7887 (clobber (reg:CC 17))]
7888 "optimize_size || TARGET_USE_CLTD"
7890 [(set_attr "type" "multi")])
7892 (define_insn "*divmodsi_noext"
7893 [(set (match_operand:SI 0 "register_operand" "=a")
7894 (div:SI (match_operand:SI 1 "register_operand" "0")
7895 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7896 (set (match_operand:SI 3 "register_operand" "=d")
7897 (mod:SI (match_dup 1) (match_dup 2)))
7898 (use (match_operand:SI 4 "register_operand" "3"))
7899 (clobber (reg:CC 17))]
7902 [(set_attr "type" "idiv")
7903 (set_attr "mode" "SI")
7904 (set_attr "ppro_uops" "few")])
7907 [(set (match_operand:SI 0 "register_operand" "")
7908 (div:SI (match_operand:SI 1 "register_operand" "")
7909 (match_operand:SI 2 "nonimmediate_operand" "")))
7910 (set (match_operand:SI 3 "register_operand" "")
7911 (mod:SI (match_dup 1) (match_dup 2)))
7912 (clobber (reg:CC 17))]
7914 [(parallel [(set (match_dup 3)
7915 (ashiftrt:SI (match_dup 4) (const_int 31)))
7916 (clobber (reg:CC 17))])
7917 (parallel [(set (match_dup 0)
7918 (div:SI (reg:SI 0) (match_dup 2)))
7920 (mod:SI (reg:SI 0) (match_dup 2)))
7922 (clobber (reg:CC 17))])]
7924 /* Avoid use of cltd in favor of a mov+shift. */
7925 if (!TARGET_USE_CLTD && !optimize_size)
7927 if (true_regnum (operands[1]))
7928 emit_move_insn (operands[0], operands[1]);
7930 emit_move_insn (operands[3], operands[1]);
7931 operands[4] = operands[3];
7935 if (true_regnum (operands[1]))
7937 operands[4] = operands[1];
7941 (define_insn "divmodhi4"
7942 [(set (match_operand:HI 0 "register_operand" "=a")
7943 (div:HI (match_operand:HI 1 "register_operand" "0")
7944 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7945 (set (match_operand:HI 3 "register_operand" "=&d")
7946 (mod:HI (match_dup 1) (match_dup 2)))
7947 (clobber (reg:CC 17))]
7948 "TARGET_HIMODE_MATH"
7950 [(set_attr "type" "multi")
7951 (set_attr "length_immediate" "0")
7952 (set_attr "mode" "SI")])
7954 (define_insn "udivmoddi4"
7955 [(set (match_operand:DI 0 "register_operand" "=a")
7956 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7957 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7958 (set (match_operand:DI 3 "register_operand" "=&d")
7959 (umod:DI (match_dup 1) (match_dup 2)))
7960 (clobber (reg:CC 17))]
7962 "xor{q}\t%3, %3\;div{q}\t%2"
7963 [(set_attr "type" "multi")
7964 (set_attr "length_immediate" "0")
7965 (set_attr "mode" "DI")])
7967 (define_insn "*udivmoddi4_noext"
7968 [(set (match_operand:DI 0 "register_operand" "=a")
7969 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7970 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7971 (set (match_operand:DI 3 "register_operand" "=d")
7972 (umod:DI (match_dup 1) (match_dup 2)))
7974 (clobber (reg:CC 17))]
7977 [(set_attr "type" "idiv")
7978 (set_attr "ppro_uops" "few")
7979 (set_attr "mode" "DI")])
7982 [(set (match_operand:DI 0 "register_operand" "")
7983 (udiv:DI (match_operand:DI 1 "register_operand" "")
7984 (match_operand:DI 2 "nonimmediate_operand" "")))
7985 (set (match_operand:DI 3 "register_operand" "")
7986 (umod:DI (match_dup 1) (match_dup 2)))
7987 (clobber (reg:CC 17))]
7988 "TARGET_64BIT && reload_completed"
7989 [(set (match_dup 3) (const_int 0))
7990 (parallel [(set (match_dup 0)
7991 (udiv:DI (match_dup 1) (match_dup 2)))
7993 (umod:DI (match_dup 1) (match_dup 2)))
7995 (clobber (reg:CC 17))])]
7998 (define_insn "udivmodsi4"
7999 [(set (match_operand:SI 0 "register_operand" "=a")
8000 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8001 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8002 (set (match_operand:SI 3 "register_operand" "=&d")
8003 (umod:SI (match_dup 1) (match_dup 2)))
8004 (clobber (reg:CC 17))]
8006 "xor{l}\t%3, %3\;div{l}\t%2"
8007 [(set_attr "type" "multi")
8008 (set_attr "length_immediate" "0")
8009 (set_attr "mode" "SI")])
8011 (define_insn "*udivmodsi4_noext"
8012 [(set (match_operand:SI 0 "register_operand" "=a")
8013 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8014 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8015 (set (match_operand:SI 3 "register_operand" "=d")
8016 (umod:SI (match_dup 1) (match_dup 2)))
8018 (clobber (reg:CC 17))]
8021 [(set_attr "type" "idiv")
8022 (set_attr "ppro_uops" "few")
8023 (set_attr "mode" "SI")])
8026 [(set (match_operand:SI 0 "register_operand" "")
8027 (udiv:SI (match_operand:SI 1 "register_operand" "")
8028 (match_operand:SI 2 "nonimmediate_operand" "")))
8029 (set (match_operand:SI 3 "register_operand" "")
8030 (umod:SI (match_dup 1) (match_dup 2)))
8031 (clobber (reg:CC 17))]
8033 [(set (match_dup 3) (const_int 0))
8034 (parallel [(set (match_dup 0)
8035 (udiv:SI (match_dup 1) (match_dup 2)))
8037 (umod:SI (match_dup 1) (match_dup 2)))
8039 (clobber (reg:CC 17))])]
8042 (define_expand "udivmodhi4"
8043 [(set (match_dup 4) (const_int 0))
8044 (parallel [(set (match_operand:HI 0 "register_operand" "")
8045 (udiv:HI (match_operand:HI 1 "register_operand" "")
8046 (match_operand:HI 2 "nonimmediate_operand" "")))
8047 (set (match_operand:HI 3 "register_operand" "")
8048 (umod:HI (match_dup 1) (match_dup 2)))
8050 (clobber (reg:CC 17))])]
8051 "TARGET_HIMODE_MATH"
8052 "operands[4] = gen_reg_rtx (HImode);")
8054 (define_insn "*udivmodhi_noext"
8055 [(set (match_operand:HI 0 "register_operand" "=a")
8056 (udiv:HI (match_operand:HI 1 "register_operand" "0")
8057 (match_operand:HI 2 "nonimmediate_operand" "rm")))
8058 (set (match_operand:HI 3 "register_operand" "=d")
8059 (umod:HI (match_dup 1) (match_dup 2)))
8060 (use (match_operand:HI 4 "register_operand" "3"))
8061 (clobber (reg:CC 17))]
8064 [(set_attr "type" "idiv")
8065 (set_attr "mode" "HI")
8066 (set_attr "ppro_uops" "few")])
8068 ;; We can not use div/idiv for double division, because it causes
8069 ;; "division by zero" on the overflow and that's not what we expect
8070 ;; from truncate. Because true (non truncating) double division is
8071 ;; never generated, we can't create this insn anyway.
8074 ; [(set (match_operand:SI 0 "register_operand" "=a")
8076 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
8078 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
8079 ; (set (match_operand:SI 3 "register_operand" "=d")
8081 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
8082 ; (clobber (reg:CC 17))]
8084 ; "div{l}\t{%2, %0|%0, %2}"
8085 ; [(set_attr "type" "idiv")
8086 ; (set_attr "ppro_uops" "few")])
8088 ;;- Logical AND instructions
8090 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
8091 ;; Note that this excludes ah.
8093 (define_insn "*testdi_1_rex64"
8096 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
8097 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
8099 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8100 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8102 test{l}\t{%k1, %k0|%k0, %k1}
8103 test{l}\t{%k1, %k0|%k0, %k1}
8104 test{q}\t{%1, %0|%0, %1}
8105 test{q}\t{%1, %0|%0, %1}
8106 test{q}\t{%1, %0|%0, %1}"
8107 [(set_attr "type" "test")
8108 (set_attr "modrm" "0,1,0,1,1")
8109 (set_attr "mode" "SI,SI,DI,DI,DI")
8110 (set_attr "pent_pair" "uv,np,uv,np,uv")])
8112 (define_insn "testsi_1"
8115 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
8116 (match_operand:SI 1 "general_operand" "in,in,rin"))
8118 "ix86_match_ccmode (insn, CCNOmode)
8119 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8120 "test{l}\t{%1, %0|%0, %1}"
8121 [(set_attr "type" "test")
8122 (set_attr "modrm" "0,1,1")
8123 (set_attr "mode" "SI")
8124 (set_attr "pent_pair" "uv,np,uv")])
8126 (define_expand "testsi_ccno_1"
8129 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
8130 (match_operand:SI 1 "nonmemory_operand" ""))
8135 (define_insn "*testhi_1"
8137 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
8138 (match_operand:HI 1 "general_operand" "n,n,rn"))
8140 "ix86_match_ccmode (insn, CCNOmode)
8141 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8142 "test{w}\t{%1, %0|%0, %1}"
8143 [(set_attr "type" "test")
8144 (set_attr "modrm" "0,1,1")
8145 (set_attr "mode" "HI")
8146 (set_attr "pent_pair" "uv,np,uv")])
8148 (define_expand "testqi_ccz_1"
8150 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
8151 (match_operand:QI 1 "nonmemory_operand" ""))
8156 (define_insn "*testqi_1"
8158 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
8159 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
8161 "ix86_match_ccmode (insn, CCNOmode)
8162 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8164 if (which_alternative == 3)
8166 if (GET_CODE (operands[1]) == CONST_INT
8167 && (INTVAL (operands[1]) & 0xffffff00))
8168 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
8169 return "test{l}\t{%1, %k0|%k0, %1}";
8171 return "test{b}\t{%1, %0|%0, %1}";
8173 [(set_attr "type" "test")
8174 (set_attr "modrm" "0,1,1,1")
8175 (set_attr "mode" "QI,QI,QI,SI")
8176 (set_attr "pent_pair" "uv,np,uv,np")])
8178 (define_expand "testqi_ext_ccno_0"
8183 (match_operand 0 "ext_register_operand" "")
8186 (match_operand 1 "const_int_operand" ""))
8191 (define_insn "*testqi_ext_0"
8196 (match_operand 0 "ext_register_operand" "Q")
8199 (match_operand 1 "const_int_operand" "n"))
8201 "ix86_match_ccmode (insn, CCNOmode)"
8202 "test{b}\t{%1, %h0|%h0, %1}"
8203 [(set_attr "type" "test")
8204 (set_attr "mode" "QI")
8205 (set_attr "length_immediate" "1")
8206 (set_attr "pent_pair" "np")])
8208 (define_insn "*testqi_ext_1"
8213 (match_operand 0 "ext_register_operand" "Q")
8217 (match_operand:QI 1 "general_operand" "Qm")))
8219 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8220 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8221 "test{b}\t{%1, %h0|%h0, %1}"
8222 [(set_attr "type" "test")
8223 (set_attr "mode" "QI")])
8225 (define_insn "*testqi_ext_1_rex64"
8230 (match_operand 0 "ext_register_operand" "Q")
8234 (match_operand:QI 1 "register_operand" "Q")))
8236 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8237 "test{b}\t{%1, %h0|%h0, %1}"
8238 [(set_attr "type" "test")
8239 (set_attr "mode" "QI")])
8241 (define_insn "*testqi_ext_2"
8246 (match_operand 0 "ext_register_operand" "Q")
8250 (match_operand 1 "ext_register_operand" "Q")
8254 "ix86_match_ccmode (insn, CCNOmode)"
8255 "test{b}\t{%h1, %h0|%h0, %h1}"
8256 [(set_attr "type" "test")
8257 (set_attr "mode" "QI")])
8259 ;; Combine likes to form bit extractions for some tests. Humor it.
8260 (define_insn "*testqi_ext_3"
8262 (compare (zero_extract:SI
8263 (match_operand 0 "nonimmediate_operand" "rm")
8264 (match_operand:SI 1 "const_int_operand" "")
8265 (match_operand:SI 2 "const_int_operand" ""))
8267 "ix86_match_ccmode (insn, CCNOmode)
8268 && (GET_MODE (operands[0]) == SImode
8269 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8270 || GET_MODE (operands[0]) == HImode
8271 || GET_MODE (operands[0]) == QImode)"
8274 (define_insn "*testqi_ext_3_rex64"
8276 (compare (zero_extract:DI
8277 (match_operand 0 "nonimmediate_operand" "rm")
8278 (match_operand:DI 1 "const_int_operand" "")
8279 (match_operand:DI 2 "const_int_operand" ""))
8282 && ix86_match_ccmode (insn, CCNOmode)
8283 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8284 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8285 /* Ensure that resulting mask is zero or sign extended operand. */
8286 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8287 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8288 && INTVAL (operands[1]) > 32))
8289 && (GET_MODE (operands[0]) == SImode
8290 || GET_MODE (operands[0]) == DImode
8291 || GET_MODE (operands[0]) == HImode
8292 || GET_MODE (operands[0]) == QImode)"
8297 (compare (zero_extract
8298 (match_operand 0 "nonimmediate_operand" "")
8299 (match_operand 1 "const_int_operand" "")
8300 (match_operand 2 "const_int_operand" ""))
8302 "ix86_match_ccmode (insn, CCNOmode)"
8303 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8305 HOST_WIDE_INT len = INTVAL (operands[1]);
8306 HOST_WIDE_INT pos = INTVAL (operands[2]);
8308 enum machine_mode mode, submode;
8310 mode = GET_MODE (operands[0]);
8311 if (GET_CODE (operands[0]) == MEM)
8313 /* ??? Combine likes to put non-volatile mem extractions in QImode
8314 no matter the size of the test. So find a mode that works. */
8315 if (! MEM_VOLATILE_P (operands[0]))
8317 mode = smallest_mode_for_size (pos + len, MODE_INT);
8318 operands[0] = adjust_address (operands[0], mode, 0);
8321 else if (GET_CODE (operands[0]) == SUBREG
8322 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8323 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8324 && pos + len <= GET_MODE_BITSIZE (submode))
8326 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8328 operands[0] = SUBREG_REG (operands[0]);
8330 else if (mode == HImode && pos + len <= 8)
8332 /* Small HImode tests can be converted to QImode. */
8334 operands[0] = gen_lowpart (QImode, operands[0]);
8337 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8338 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8340 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8343 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8344 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8345 ;; this is relatively important trick.
8346 ;; Do the conversion only post-reload to avoid limiting of the register class
8351 (and (match_operand 0 "register_operand" "")
8352 (match_operand 1 "const_int_operand" ""))
8355 && QI_REG_P (operands[0])
8356 && ((ix86_match_ccmode (insn, CCZmode)
8357 && !(INTVAL (operands[1]) & ~(255 << 8)))
8358 || (ix86_match_ccmode (insn, CCNOmode)
8359 && !(INTVAL (operands[1]) & ~(127 << 8))))
8360 && GET_MODE (operands[0]) != QImode"
8363 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8366 "operands[0] = gen_lowpart (SImode, operands[0]);
8367 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8372 (and (match_operand 0 "nonimmediate_operand" "")
8373 (match_operand 1 "const_int_operand" ""))
8376 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8377 && ((ix86_match_ccmode (insn, CCZmode)
8378 && !(INTVAL (operands[1]) & ~255))
8379 || (ix86_match_ccmode (insn, CCNOmode)
8380 && !(INTVAL (operands[1]) & ~127)))
8381 && GET_MODE (operands[0]) != QImode"
8384 (and:QI (match_dup 0)
8387 "operands[0] = gen_lowpart (QImode, operands[0]);
8388 operands[1] = gen_lowpart (QImode, operands[1]);")
8391 ;; %%% This used to optimize known byte-wide and operations to memory,
8392 ;; and sometimes to QImode registers. If this is considered useful,
8393 ;; it should be done with splitters.
8395 (define_expand "anddi3"
8396 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8397 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8398 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8399 (clobber (reg:CC 17))]
8401 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8403 (define_insn "*anddi_1_rex64"
8404 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8405 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8406 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8407 (clobber (reg:CC 17))]
8408 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8410 switch (get_attr_type (insn))
8414 enum machine_mode mode;
8416 if (GET_CODE (operands[2]) != CONST_INT)
8418 if (INTVAL (operands[2]) == 0xff)
8420 else if (INTVAL (operands[2]) == 0xffff)
8425 operands[1] = gen_lowpart (mode, operands[1]);
8427 return "movz{bq|x}\t{%1,%0|%0, %1}";
8429 return "movz{wq|x}\t{%1,%0|%0, %1}";
8433 if (! rtx_equal_p (operands[0], operands[1]))
8435 if (get_attr_mode (insn) == MODE_SI)
8436 return "and{l}\t{%k2, %k0|%k0, %k2}";
8438 return "and{q}\t{%2, %0|%0, %2}";
8441 [(set_attr "type" "alu,alu,alu,imovx")
8442 (set_attr "length_immediate" "*,*,*,0")
8443 (set_attr "mode" "SI,DI,DI,DI")])
8445 (define_insn "*anddi_2"
8447 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8448 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8450 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8451 (and:DI (match_dup 1) (match_dup 2)))]
8452 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8453 && ix86_binary_operator_ok (AND, DImode, operands)"
8455 and{l}\t{%k2, %k0|%k0, %k2}
8456 and{q}\t{%2, %0|%0, %2}
8457 and{q}\t{%2, %0|%0, %2}"
8458 [(set_attr "type" "alu")
8459 (set_attr "mode" "SI,DI,DI")])
8461 (define_expand "andsi3"
8462 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8463 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8464 (match_operand:SI 2 "general_operand" "")))
8465 (clobber (reg:CC 17))]
8467 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8469 (define_insn "*andsi_1"
8470 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8471 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8472 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8473 (clobber (reg:CC 17))]
8474 "ix86_binary_operator_ok (AND, SImode, operands)"
8476 switch (get_attr_type (insn))
8480 enum machine_mode mode;
8482 if (GET_CODE (operands[2]) != CONST_INT)
8484 if (INTVAL (operands[2]) == 0xff)
8486 else if (INTVAL (operands[2]) == 0xffff)
8491 operands[1] = gen_lowpart (mode, operands[1]);
8493 return "movz{bl|x}\t{%1,%0|%0, %1}";
8495 return "movz{wl|x}\t{%1,%0|%0, %1}";
8499 if (! rtx_equal_p (operands[0], operands[1]))
8501 return "and{l}\t{%2, %0|%0, %2}";
8504 [(set_attr "type" "alu,alu,imovx")
8505 (set_attr "length_immediate" "*,*,0")
8506 (set_attr "mode" "SI")])
8509 [(set (match_operand 0 "register_operand" "")
8511 (const_int -65536)))
8512 (clobber (reg:CC 17))]
8513 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8514 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8515 "operands[1] = gen_lowpart (HImode, operands[0]);")
8518 [(set (match_operand 0 "ext_register_operand" "")
8521 (clobber (reg:CC 17))]
8522 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8523 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8524 "operands[1] = gen_lowpart (QImode, operands[0]);")
8527 [(set (match_operand 0 "ext_register_operand" "")
8529 (const_int -65281)))
8530 (clobber (reg:CC 17))]
8531 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8532 [(parallel [(set (zero_extract:SI (match_dup 0)
8536 (zero_extract:SI (match_dup 0)
8539 (zero_extract:SI (match_dup 0)
8542 (clobber (reg:CC 17))])]
8543 "operands[0] = gen_lowpart (SImode, operands[0]);")
8545 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8546 (define_insn "*andsi_1_zext"
8547 [(set (match_operand:DI 0 "register_operand" "=r")
8549 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8550 (match_operand:SI 2 "general_operand" "rim"))))
8551 (clobber (reg:CC 17))]
8552 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8553 "and{l}\t{%2, %k0|%k0, %2}"
8554 [(set_attr "type" "alu")
8555 (set_attr "mode" "SI")])
8557 (define_insn "*andsi_2"
8559 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8560 (match_operand:SI 2 "general_operand" "rim,ri"))
8562 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8563 (and:SI (match_dup 1) (match_dup 2)))]
8564 "ix86_match_ccmode (insn, CCNOmode)
8565 && ix86_binary_operator_ok (AND, SImode, operands)"
8566 "and{l}\t{%2, %0|%0, %2}"
8567 [(set_attr "type" "alu")
8568 (set_attr "mode" "SI")])
8570 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8571 (define_insn "*andsi_2_zext"
8573 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8574 (match_operand:SI 2 "general_operand" "rim"))
8576 (set (match_operand:DI 0 "register_operand" "=r")
8577 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8578 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8579 && ix86_binary_operator_ok (AND, SImode, operands)"
8580 "and{l}\t{%2, %k0|%k0, %2}"
8581 [(set_attr "type" "alu")
8582 (set_attr "mode" "SI")])
8584 (define_expand "andhi3"
8585 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8586 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8587 (match_operand:HI 2 "general_operand" "")))
8588 (clobber (reg:CC 17))]
8589 "TARGET_HIMODE_MATH"
8590 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8592 (define_insn "*andhi_1"
8593 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8594 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8595 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8596 (clobber (reg:CC 17))]
8597 "ix86_binary_operator_ok (AND, HImode, operands)"
8599 switch (get_attr_type (insn))
8602 if (GET_CODE (operands[2]) != CONST_INT)
8604 if (INTVAL (operands[2]) == 0xff)
8605 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8609 if (! rtx_equal_p (operands[0], operands[1]))
8612 return "and{w}\t{%2, %0|%0, %2}";
8615 [(set_attr "type" "alu,alu,imovx")
8616 (set_attr "length_immediate" "*,*,0")
8617 (set_attr "mode" "HI,HI,SI")])
8619 (define_insn "*andhi_2"
8621 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8622 (match_operand:HI 2 "general_operand" "rim,ri"))
8624 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8625 (and:HI (match_dup 1) (match_dup 2)))]
8626 "ix86_match_ccmode (insn, CCNOmode)
8627 && ix86_binary_operator_ok (AND, HImode, operands)"
8628 "and{w}\t{%2, %0|%0, %2}"
8629 [(set_attr "type" "alu")
8630 (set_attr "mode" "HI")])
8632 (define_expand "andqi3"
8633 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8634 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8635 (match_operand:QI 2 "general_operand" "")))
8636 (clobber (reg:CC 17))]
8637 "TARGET_QIMODE_MATH"
8638 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8640 ;; %%% Potential partial reg stall on alternative 2. What to do?
8641 (define_insn "*andqi_1"
8642 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8643 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8644 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8645 (clobber (reg:CC 17))]
8646 "ix86_binary_operator_ok (AND, QImode, operands)"
8648 and{b}\t{%2, %0|%0, %2}
8649 and{b}\t{%2, %0|%0, %2}
8650 and{l}\t{%k2, %k0|%k0, %k2}"
8651 [(set_attr "type" "alu")
8652 (set_attr "mode" "QI,QI,SI")])
8654 (define_insn "*andqi_1_slp"
8655 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8656 (and:QI (match_dup 0)
8657 (match_operand:QI 1 "general_operand" "qi,qmi")))
8658 (clobber (reg:CC 17))]
8659 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8660 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8661 "and{b}\t{%1, %0|%0, %1}"
8662 [(set_attr "type" "alu1")
8663 (set_attr "mode" "QI")])
8665 (define_insn "*andqi_2"
8668 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8669 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8671 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8672 (and:QI (match_dup 1) (match_dup 2)))]
8673 "ix86_match_ccmode (insn, CCNOmode)
8674 && ix86_binary_operator_ok (AND, QImode, operands)"
8676 if (which_alternative == 2)
8678 if (GET_CODE (operands[2]) == CONST_INT
8679 && (INTVAL (operands[2]) & 0xffffff00))
8680 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8681 return "and{l}\t{%2, %k0|%k0, %2}";
8683 return "and{b}\t{%2, %0|%0, %2}";
8685 [(set_attr "type" "alu")
8686 (set_attr "mode" "QI,QI,SI")])
8688 (define_insn "*andqi_2_slp"
8691 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8692 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8694 (set (strict_low_part (match_dup 0))
8695 (and:QI (match_dup 0) (match_dup 1)))]
8696 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8697 && ix86_match_ccmode (insn, CCNOmode)
8698 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8699 "and{b}\t{%1, %0|%0, %1}"
8700 [(set_attr "type" "alu1")
8701 (set_attr "mode" "QI")])
8703 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8704 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8705 ;; for a QImode operand, which of course failed.
8707 (define_insn "andqi_ext_0"
8708 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8713 (match_operand 1 "ext_register_operand" "0")
8716 (match_operand 2 "const_int_operand" "n")))
8717 (clobber (reg:CC 17))]
8719 "and{b}\t{%2, %h0|%h0, %2}"
8720 [(set_attr "type" "alu")
8721 (set_attr "length_immediate" "1")
8722 (set_attr "mode" "QI")])
8724 ;; Generated by peephole translating test to and. This shows up
8725 ;; often in fp comparisons.
8727 (define_insn "*andqi_ext_0_cc"
8732 (match_operand 1 "ext_register_operand" "0")
8735 (match_operand 2 "const_int_operand" "n"))
8737 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8746 "ix86_match_ccmode (insn, CCNOmode)"
8747 "and{b}\t{%2, %h0|%h0, %2}"
8748 [(set_attr "type" "alu")
8749 (set_attr "length_immediate" "1")
8750 (set_attr "mode" "QI")])
8752 (define_insn "*andqi_ext_1"
8753 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8758 (match_operand 1 "ext_register_operand" "0")
8762 (match_operand:QI 2 "general_operand" "Qm"))))
8763 (clobber (reg:CC 17))]
8765 "and{b}\t{%2, %h0|%h0, %2}"
8766 [(set_attr "type" "alu")
8767 (set_attr "length_immediate" "0")
8768 (set_attr "mode" "QI")])
8770 (define_insn "*andqi_ext_1_rex64"
8771 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8776 (match_operand 1 "ext_register_operand" "0")
8780 (match_operand 2 "ext_register_operand" "Q"))))
8781 (clobber (reg:CC 17))]
8783 "and{b}\t{%2, %h0|%h0, %2}"
8784 [(set_attr "type" "alu")
8785 (set_attr "length_immediate" "0")
8786 (set_attr "mode" "QI")])
8788 (define_insn "*andqi_ext_2"
8789 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8794 (match_operand 1 "ext_register_operand" "%0")
8798 (match_operand 2 "ext_register_operand" "Q")
8801 (clobber (reg:CC 17))]
8803 "and{b}\t{%h2, %h0|%h0, %h2}"
8804 [(set_attr "type" "alu")
8805 (set_attr "length_immediate" "0")
8806 (set_attr "mode" "QI")])
8808 ;; Convert wide AND instructions with immediate operand to shorter QImode
8809 ;; equivalents when possible.
8810 ;; Don't do the splitting with memory operands, since it introduces risk
8811 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8812 ;; for size, but that can (should?) be handled by generic code instead.
8814 [(set (match_operand 0 "register_operand" "")
8815 (and (match_operand 1 "register_operand" "")
8816 (match_operand 2 "const_int_operand" "")))
8817 (clobber (reg:CC 17))]
8819 && QI_REG_P (operands[0])
8820 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8821 && !(~INTVAL (operands[2]) & ~(255 << 8))
8822 && GET_MODE (operands[0]) != QImode"
8823 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8824 (and:SI (zero_extract:SI (match_dup 1)
8825 (const_int 8) (const_int 8))
8827 (clobber (reg:CC 17))])]
8828 "operands[0] = gen_lowpart (SImode, operands[0]);
8829 operands[1] = gen_lowpart (SImode, operands[1]);
8830 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8832 ;; Since AND can be encoded with sign extended immediate, this is only
8833 ;; profitable when 7th bit is not set.
8835 [(set (match_operand 0 "register_operand" "")
8836 (and (match_operand 1 "general_operand" "")
8837 (match_operand 2 "const_int_operand" "")))
8838 (clobber (reg:CC 17))]
8840 && ANY_QI_REG_P (operands[0])
8841 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8842 && !(~INTVAL (operands[2]) & ~255)
8843 && !(INTVAL (operands[2]) & 128)
8844 && GET_MODE (operands[0]) != QImode"
8845 [(parallel [(set (strict_low_part (match_dup 0))
8846 (and:QI (match_dup 1)
8848 (clobber (reg:CC 17))])]
8849 "operands[0] = gen_lowpart (QImode, operands[0]);
8850 operands[1] = gen_lowpart (QImode, operands[1]);
8851 operands[2] = gen_lowpart (QImode, operands[2]);")
8853 ;; Logical inclusive OR instructions
8855 ;; %%% This used to optimize known byte-wide and operations to memory.
8856 ;; If this is considered useful, it should be done with splitters.
8858 (define_expand "iordi3"
8859 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8860 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8861 (match_operand:DI 2 "x86_64_general_operand" "")))
8862 (clobber (reg:CC 17))]
8864 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8866 (define_insn "*iordi_1_rex64"
8867 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8868 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8869 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8870 (clobber (reg:CC 17))]
8872 && ix86_binary_operator_ok (IOR, DImode, operands)"
8873 "or{q}\t{%2, %0|%0, %2}"
8874 [(set_attr "type" "alu")
8875 (set_attr "mode" "DI")])
8877 (define_insn "*iordi_2_rex64"
8879 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8880 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8882 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8883 (ior:DI (match_dup 1) (match_dup 2)))]
8885 && ix86_match_ccmode (insn, CCNOmode)
8886 && ix86_binary_operator_ok (IOR, DImode, operands)"
8887 "or{q}\t{%2, %0|%0, %2}"
8888 [(set_attr "type" "alu")
8889 (set_attr "mode" "DI")])
8891 (define_insn "*iordi_3_rex64"
8893 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8894 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8896 (clobber (match_scratch:DI 0 "=r"))]
8898 && ix86_match_ccmode (insn, CCNOmode)
8899 && ix86_binary_operator_ok (IOR, DImode, operands)"
8900 "or{q}\t{%2, %0|%0, %2}"
8901 [(set_attr "type" "alu")
8902 (set_attr "mode" "DI")])
8905 (define_expand "iorsi3"
8906 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8907 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8908 (match_operand:SI 2 "general_operand" "")))
8909 (clobber (reg:CC 17))]
8911 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8913 (define_insn "*iorsi_1"
8914 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8915 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8916 (match_operand:SI 2 "general_operand" "ri,rmi")))
8917 (clobber (reg:CC 17))]
8918 "ix86_binary_operator_ok (IOR, SImode, operands)"
8919 "or{l}\t{%2, %0|%0, %2}"
8920 [(set_attr "type" "alu")
8921 (set_attr "mode" "SI")])
8923 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8924 (define_insn "*iorsi_1_zext"
8925 [(set (match_operand:DI 0 "register_operand" "=rm")
8927 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8928 (match_operand:SI 2 "general_operand" "rim"))))
8929 (clobber (reg:CC 17))]
8930 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8931 "or{l}\t{%2, %k0|%k0, %2}"
8932 [(set_attr "type" "alu")
8933 (set_attr "mode" "SI")])
8935 (define_insn "*iorsi_1_zext_imm"
8936 [(set (match_operand:DI 0 "register_operand" "=rm")
8937 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8938 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8939 (clobber (reg:CC 17))]
8941 "or{l}\t{%2, %k0|%k0, %2}"
8942 [(set_attr "type" "alu")
8943 (set_attr "mode" "SI")])
8945 (define_insn "*iorsi_2"
8947 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8948 (match_operand:SI 2 "general_operand" "rim,ri"))
8950 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8951 (ior:SI (match_dup 1) (match_dup 2)))]
8952 "ix86_match_ccmode (insn, CCNOmode)
8953 && ix86_binary_operator_ok (IOR, SImode, operands)"
8954 "or{l}\t{%2, %0|%0, %2}"
8955 [(set_attr "type" "alu")
8956 (set_attr "mode" "SI")])
8958 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8959 ;; ??? Special case for immediate operand is missing - it is tricky.
8960 (define_insn "*iorsi_2_zext"
8962 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8963 (match_operand:SI 2 "general_operand" "rim"))
8965 (set (match_operand:DI 0 "register_operand" "=r")
8966 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8967 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8968 && ix86_binary_operator_ok (IOR, SImode, operands)"
8969 "or{l}\t{%2, %k0|%k0, %2}"
8970 [(set_attr "type" "alu")
8971 (set_attr "mode" "SI")])
8973 (define_insn "*iorsi_2_zext_imm"
8975 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8976 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8978 (set (match_operand:DI 0 "register_operand" "=r")
8979 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8980 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8981 && ix86_binary_operator_ok (IOR, SImode, operands)"
8982 "or{l}\t{%2, %k0|%k0, %2}"
8983 [(set_attr "type" "alu")
8984 (set_attr "mode" "SI")])
8986 (define_insn "*iorsi_3"
8988 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8989 (match_operand:SI 2 "general_operand" "rim"))
8991 (clobber (match_scratch:SI 0 "=r"))]
8992 "ix86_match_ccmode (insn, CCNOmode)
8993 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8994 "or{l}\t{%2, %0|%0, %2}"
8995 [(set_attr "type" "alu")
8996 (set_attr "mode" "SI")])
8998 (define_expand "iorhi3"
8999 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9000 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
9001 (match_operand:HI 2 "general_operand" "")))
9002 (clobber (reg:CC 17))]
9003 "TARGET_HIMODE_MATH"
9004 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
9006 (define_insn "*iorhi_1"
9007 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9008 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9009 (match_operand:HI 2 "general_operand" "rmi,ri")))
9010 (clobber (reg:CC 17))]
9011 "ix86_binary_operator_ok (IOR, HImode, operands)"
9012 "or{w}\t{%2, %0|%0, %2}"
9013 [(set_attr "type" "alu")
9014 (set_attr "mode" "HI")])
9016 (define_insn "*iorhi_2"
9018 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9019 (match_operand:HI 2 "general_operand" "rim,ri"))
9021 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9022 (ior:HI (match_dup 1) (match_dup 2)))]
9023 "ix86_match_ccmode (insn, CCNOmode)
9024 && ix86_binary_operator_ok (IOR, HImode, operands)"
9025 "or{w}\t{%2, %0|%0, %2}"
9026 [(set_attr "type" "alu")
9027 (set_attr "mode" "HI")])
9029 (define_insn "*iorhi_3"
9031 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9032 (match_operand:HI 2 "general_operand" "rim"))
9034 (clobber (match_scratch:HI 0 "=r"))]
9035 "ix86_match_ccmode (insn, CCNOmode)
9036 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9037 "or{w}\t{%2, %0|%0, %2}"
9038 [(set_attr "type" "alu")
9039 (set_attr "mode" "HI")])
9041 (define_expand "iorqi3"
9042 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9043 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
9044 (match_operand:QI 2 "general_operand" "")))
9045 (clobber (reg:CC 17))]
9046 "TARGET_QIMODE_MATH"
9047 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
9049 ;; %%% Potential partial reg stall on alternative 2. What to do?
9050 (define_insn "*iorqi_1"
9051 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9052 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9053 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9054 (clobber (reg:CC 17))]
9055 "ix86_binary_operator_ok (IOR, QImode, operands)"
9057 or{b}\t{%2, %0|%0, %2}
9058 or{b}\t{%2, %0|%0, %2}
9059 or{l}\t{%k2, %k0|%k0, %k2}"
9060 [(set_attr "type" "alu")
9061 (set_attr "mode" "QI,QI,SI")])
9063 (define_insn "*iorqi_1_slp"
9064 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
9065 (ior:QI (match_dup 0)
9066 (match_operand:QI 1 "general_operand" "qmi,qi")))
9067 (clobber (reg:CC 17))]
9068 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9069 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9070 "or{b}\t{%1, %0|%0, %1}"
9071 [(set_attr "type" "alu1")
9072 (set_attr "mode" "QI")])
9074 (define_insn "*iorqi_2"
9076 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9077 (match_operand:QI 2 "general_operand" "qim,qi"))
9079 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9080 (ior:QI (match_dup 1) (match_dup 2)))]
9081 "ix86_match_ccmode (insn, CCNOmode)
9082 && ix86_binary_operator_ok (IOR, QImode, operands)"
9083 "or{b}\t{%2, %0|%0, %2}"
9084 [(set_attr "type" "alu")
9085 (set_attr "mode" "QI")])
9087 (define_insn "*iorqi_2_slp"
9089 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9090 (match_operand:QI 1 "general_operand" "qim,qi"))
9092 (set (strict_low_part (match_dup 0))
9093 (ior:QI (match_dup 0) (match_dup 1)))]
9094 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9095 && ix86_match_ccmode (insn, CCNOmode)
9096 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9097 "or{b}\t{%1, %0|%0, %1}"
9098 [(set_attr "type" "alu1")
9099 (set_attr "mode" "QI")])
9101 (define_insn "*iorqi_3"
9103 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9104 (match_operand:QI 2 "general_operand" "qim"))
9106 (clobber (match_scratch:QI 0 "=q"))]
9107 "ix86_match_ccmode (insn, CCNOmode)
9108 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9109 "or{b}\t{%2, %0|%0, %2}"
9110 [(set_attr "type" "alu")
9111 (set_attr "mode" "QI")])
9113 (define_insn "iorqi_ext_0"
9114 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9119 (match_operand 1 "ext_register_operand" "0")
9122 (match_operand 2 "const_int_operand" "n")))
9123 (clobber (reg:CC 17))]
9124 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9125 "or{b}\t{%2, %h0|%h0, %2}"
9126 [(set_attr "type" "alu")
9127 (set_attr "length_immediate" "1")
9128 (set_attr "mode" "QI")])
9130 (define_insn "*iorqi_ext_1"
9131 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9136 (match_operand 1 "ext_register_operand" "0")
9140 (match_operand:QI 2 "general_operand" "Qm"))))
9141 (clobber (reg:CC 17))]
9143 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9144 "or{b}\t{%2, %h0|%h0, %2}"
9145 [(set_attr "type" "alu")
9146 (set_attr "length_immediate" "0")
9147 (set_attr "mode" "QI")])
9149 (define_insn "*iorqi_ext_1_rex64"
9150 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9155 (match_operand 1 "ext_register_operand" "0")
9159 (match_operand 2 "ext_register_operand" "Q"))))
9160 (clobber (reg:CC 17))]
9162 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9163 "or{b}\t{%2, %h0|%h0, %2}"
9164 [(set_attr "type" "alu")
9165 (set_attr "length_immediate" "0")
9166 (set_attr "mode" "QI")])
9168 (define_insn "*iorqi_ext_2"
9169 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9173 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9176 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9179 (clobber (reg:CC 17))]
9180 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9181 "ior{b}\t{%h2, %h0|%h0, %h2}"
9182 [(set_attr "type" "alu")
9183 (set_attr "length_immediate" "0")
9184 (set_attr "mode" "QI")])
9187 [(set (match_operand 0 "register_operand" "")
9188 (ior (match_operand 1 "register_operand" "")
9189 (match_operand 2 "const_int_operand" "")))
9190 (clobber (reg:CC 17))]
9192 && QI_REG_P (operands[0])
9193 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9194 && !(INTVAL (operands[2]) & ~(255 << 8))
9195 && GET_MODE (operands[0]) != QImode"
9196 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9197 (ior:SI (zero_extract:SI (match_dup 1)
9198 (const_int 8) (const_int 8))
9200 (clobber (reg:CC 17))])]
9201 "operands[0] = gen_lowpart (SImode, operands[0]);
9202 operands[1] = gen_lowpart (SImode, operands[1]);
9203 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9205 ;; Since OR can be encoded with sign extended immediate, this is only
9206 ;; profitable when 7th bit is set.
9208 [(set (match_operand 0 "register_operand" "")
9209 (ior (match_operand 1 "general_operand" "")
9210 (match_operand 2 "const_int_operand" "")))
9211 (clobber (reg:CC 17))]
9213 && ANY_QI_REG_P (operands[0])
9214 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9215 && !(INTVAL (operands[2]) & ~255)
9216 && (INTVAL (operands[2]) & 128)
9217 && GET_MODE (operands[0]) != QImode"
9218 [(parallel [(set (strict_low_part (match_dup 0))
9219 (ior:QI (match_dup 1)
9221 (clobber (reg:CC 17))])]
9222 "operands[0] = gen_lowpart (QImode, operands[0]);
9223 operands[1] = gen_lowpart (QImode, operands[1]);
9224 operands[2] = gen_lowpart (QImode, operands[2]);")
9226 ;; Logical XOR instructions
9228 ;; %%% This used to optimize known byte-wide and operations to memory.
9229 ;; If this is considered useful, it should be done with splitters.
9231 (define_expand "xordi3"
9232 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9233 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
9234 (match_operand:DI 2 "x86_64_general_operand" "")))
9235 (clobber (reg:CC 17))]
9237 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
9239 (define_insn "*xordi_1_rex64"
9240 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9241 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9242 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
9243 (clobber (reg:CC 17))]
9245 && ix86_binary_operator_ok (XOR, DImode, operands)"
9247 xor{q}\t{%2, %0|%0, %2}
9248 xor{q}\t{%2, %0|%0, %2}"
9249 [(set_attr "type" "alu")
9250 (set_attr "mode" "DI,DI")])
9252 (define_insn "*xordi_2_rex64"
9254 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9255 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9257 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9258 (xor:DI (match_dup 1) (match_dup 2)))]
9260 && ix86_match_ccmode (insn, CCNOmode)
9261 && ix86_binary_operator_ok (XOR, DImode, operands)"
9263 xor{q}\t{%2, %0|%0, %2}
9264 xor{q}\t{%2, %0|%0, %2}"
9265 [(set_attr "type" "alu")
9266 (set_attr "mode" "DI,DI")])
9268 (define_insn "*xordi_3_rex64"
9270 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9271 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9273 (clobber (match_scratch:DI 0 "=r"))]
9275 && ix86_match_ccmode (insn, CCNOmode)
9276 && ix86_binary_operator_ok (XOR, DImode, operands)"
9277 "xor{q}\t{%2, %0|%0, %2}"
9278 [(set_attr "type" "alu")
9279 (set_attr "mode" "DI")])
9281 (define_expand "xorsi3"
9282 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9283 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9284 (match_operand:SI 2 "general_operand" "")))
9285 (clobber (reg:CC 17))]
9287 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9289 (define_insn "*xorsi_1"
9290 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9291 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9292 (match_operand:SI 2 "general_operand" "ri,rm")))
9293 (clobber (reg:CC 17))]
9294 "ix86_binary_operator_ok (XOR, SImode, operands)"
9295 "xor{l}\t{%2, %0|%0, %2}"
9296 [(set_attr "type" "alu")
9297 (set_attr "mode" "SI")])
9299 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9300 ;; Add speccase for immediates
9301 (define_insn "*xorsi_1_zext"
9302 [(set (match_operand:DI 0 "register_operand" "=r")
9304 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9305 (match_operand:SI 2 "general_operand" "rim"))))
9306 (clobber (reg:CC 17))]
9307 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9308 "xor{l}\t{%2, %k0|%k0, %2}"
9309 [(set_attr "type" "alu")
9310 (set_attr "mode" "SI")])
9312 (define_insn "*xorsi_1_zext_imm"
9313 [(set (match_operand:DI 0 "register_operand" "=r")
9314 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9315 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9316 (clobber (reg:CC 17))]
9317 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9318 "xor{l}\t{%2, %k0|%k0, %2}"
9319 [(set_attr "type" "alu")
9320 (set_attr "mode" "SI")])
9322 (define_insn "*xorsi_2"
9324 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9325 (match_operand:SI 2 "general_operand" "rim,ri"))
9327 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9328 (xor:SI (match_dup 1) (match_dup 2)))]
9329 "ix86_match_ccmode (insn, CCNOmode)
9330 && ix86_binary_operator_ok (XOR, SImode, operands)"
9331 "xor{l}\t{%2, %0|%0, %2}"
9332 [(set_attr "type" "alu")
9333 (set_attr "mode" "SI")])
9335 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9336 ;; ??? Special case for immediate operand is missing - it is tricky.
9337 (define_insn "*xorsi_2_zext"
9339 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9340 (match_operand:SI 2 "general_operand" "rim"))
9342 (set (match_operand:DI 0 "register_operand" "=r")
9343 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9344 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9345 && ix86_binary_operator_ok (XOR, SImode, operands)"
9346 "xor{l}\t{%2, %k0|%k0, %2}"
9347 [(set_attr "type" "alu")
9348 (set_attr "mode" "SI")])
9350 (define_insn "*xorsi_2_zext_imm"
9352 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9353 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9355 (set (match_operand:DI 0 "register_operand" "=r")
9356 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9357 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9358 && ix86_binary_operator_ok (XOR, SImode, operands)"
9359 "xor{l}\t{%2, %k0|%k0, %2}"
9360 [(set_attr "type" "alu")
9361 (set_attr "mode" "SI")])
9363 (define_insn "*xorsi_3"
9365 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9366 (match_operand:SI 2 "general_operand" "rim"))
9368 (clobber (match_scratch:SI 0 "=r"))]
9369 "ix86_match_ccmode (insn, CCNOmode)
9370 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9371 "xor{l}\t{%2, %0|%0, %2}"
9372 [(set_attr "type" "alu")
9373 (set_attr "mode" "SI")])
9375 (define_expand "xorhi3"
9376 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9377 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9378 (match_operand:HI 2 "general_operand" "")))
9379 (clobber (reg:CC 17))]
9380 "TARGET_HIMODE_MATH"
9381 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9383 (define_insn "*xorhi_1"
9384 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9385 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9386 (match_operand:HI 2 "general_operand" "rmi,ri")))
9387 (clobber (reg:CC 17))]
9388 "ix86_binary_operator_ok (XOR, HImode, operands)"
9389 "xor{w}\t{%2, %0|%0, %2}"
9390 [(set_attr "type" "alu")
9391 (set_attr "mode" "HI")])
9393 (define_insn "*xorhi_2"
9395 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9396 (match_operand:HI 2 "general_operand" "rim,ri"))
9398 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9399 (xor:HI (match_dup 1) (match_dup 2)))]
9400 "ix86_match_ccmode (insn, CCNOmode)
9401 && ix86_binary_operator_ok (XOR, HImode, operands)"
9402 "xor{w}\t{%2, %0|%0, %2}"
9403 [(set_attr "type" "alu")
9404 (set_attr "mode" "HI")])
9406 (define_insn "*xorhi_3"
9408 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9409 (match_operand:HI 2 "general_operand" "rim"))
9411 (clobber (match_scratch:HI 0 "=r"))]
9412 "ix86_match_ccmode (insn, CCNOmode)
9413 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9414 "xor{w}\t{%2, %0|%0, %2}"
9415 [(set_attr "type" "alu")
9416 (set_attr "mode" "HI")])
9418 (define_expand "xorqi3"
9419 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9420 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9421 (match_operand:QI 2 "general_operand" "")))
9422 (clobber (reg:CC 17))]
9423 "TARGET_QIMODE_MATH"
9424 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9426 ;; %%% Potential partial reg stall on alternative 2. What to do?
9427 (define_insn "*xorqi_1"
9428 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9429 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9430 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9431 (clobber (reg:CC 17))]
9432 "ix86_binary_operator_ok (XOR, QImode, operands)"
9434 xor{b}\t{%2, %0|%0, %2}
9435 xor{b}\t{%2, %0|%0, %2}
9436 xor{l}\t{%k2, %k0|%k0, %k2}"
9437 [(set_attr "type" "alu")
9438 (set_attr "mode" "QI,QI,SI")])
9440 (define_insn "*xorqi_1_slp"
9441 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9442 (xor:QI (match_dup 0)
9443 (match_operand:QI 1 "general_operand" "qi,qmi")))
9444 (clobber (reg:CC 17))]
9445 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9446 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9447 "xor{b}\t{%1, %0|%0, %1}"
9448 [(set_attr "type" "alu1")
9449 (set_attr "mode" "QI")])
9451 (define_insn "xorqi_ext_0"
9452 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9457 (match_operand 1 "ext_register_operand" "0")
9460 (match_operand 2 "const_int_operand" "n")))
9461 (clobber (reg:CC 17))]
9462 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9463 "xor{b}\t{%2, %h0|%h0, %2}"
9464 [(set_attr "type" "alu")
9465 (set_attr "length_immediate" "1")
9466 (set_attr "mode" "QI")])
9468 (define_insn "*xorqi_ext_1"
9469 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9474 (match_operand 1 "ext_register_operand" "0")
9478 (match_operand:QI 2 "general_operand" "Qm"))))
9479 (clobber (reg:CC 17))]
9481 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9482 "xor{b}\t{%2, %h0|%h0, %2}"
9483 [(set_attr "type" "alu")
9484 (set_attr "length_immediate" "0")
9485 (set_attr "mode" "QI")])
9487 (define_insn "*xorqi_ext_1_rex64"
9488 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9493 (match_operand 1 "ext_register_operand" "0")
9497 (match_operand 2 "ext_register_operand" "Q"))))
9498 (clobber (reg:CC 17))]
9500 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9501 "xor{b}\t{%2, %h0|%h0, %2}"
9502 [(set_attr "type" "alu")
9503 (set_attr "length_immediate" "0")
9504 (set_attr "mode" "QI")])
9506 (define_insn "*xorqi_ext_2"
9507 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9511 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9514 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9517 (clobber (reg:CC 17))]
9518 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9519 "xor{b}\t{%h2, %h0|%h0, %h2}"
9520 [(set_attr "type" "alu")
9521 (set_attr "length_immediate" "0")
9522 (set_attr "mode" "QI")])
9524 (define_insn "*xorqi_cc_1"
9527 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9528 (match_operand:QI 2 "general_operand" "qim,qi"))
9530 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9531 (xor:QI (match_dup 1) (match_dup 2)))]
9532 "ix86_match_ccmode (insn, CCNOmode)
9533 && ix86_binary_operator_ok (XOR, QImode, operands)"
9534 "xor{b}\t{%2, %0|%0, %2}"
9535 [(set_attr "type" "alu")
9536 (set_attr "mode" "QI")])
9538 (define_insn "*xorqi_2_slp"
9540 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9541 (match_operand:QI 1 "general_operand" "qim,qi"))
9543 (set (strict_low_part (match_dup 0))
9544 (xor:QI (match_dup 0) (match_dup 1)))]
9545 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9546 && ix86_match_ccmode (insn, CCNOmode)
9547 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9548 "xor{b}\t{%1, %0|%0, %1}"
9549 [(set_attr "type" "alu1")
9550 (set_attr "mode" "QI")])
9552 (define_insn "*xorqi_cc_2"
9555 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9556 (match_operand:QI 2 "general_operand" "qim"))
9558 (clobber (match_scratch:QI 0 "=q"))]
9559 "ix86_match_ccmode (insn, CCNOmode)
9560 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9561 "xor{b}\t{%2, %0|%0, %2}"
9562 [(set_attr "type" "alu")
9563 (set_attr "mode" "QI")])
9565 (define_insn "*xorqi_cc_ext_1"
9570 (match_operand 1 "ext_register_operand" "0")
9573 (match_operand:QI 2 "general_operand" "qmn"))
9575 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9579 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9581 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9582 "xor{b}\t{%2, %h0|%h0, %2}"
9583 [(set_attr "type" "alu")
9584 (set_attr "mode" "QI")])
9586 (define_insn "*xorqi_cc_ext_1_rex64"
9591 (match_operand 1 "ext_register_operand" "0")
9594 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9596 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9600 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9602 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9603 "xor{b}\t{%2, %h0|%h0, %2}"
9604 [(set_attr "type" "alu")
9605 (set_attr "mode" "QI")])
9607 (define_expand "xorqi_cc_ext_1"
9613 (match_operand 1 "ext_register_operand" "")
9616 (match_operand:QI 2 "general_operand" ""))
9618 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9622 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9628 [(set (match_operand 0 "register_operand" "")
9629 (xor (match_operand 1 "register_operand" "")
9630 (match_operand 2 "const_int_operand" "")))
9631 (clobber (reg:CC 17))]
9633 && QI_REG_P (operands[0])
9634 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9635 && !(INTVAL (operands[2]) & ~(255 << 8))
9636 && GET_MODE (operands[0]) != QImode"
9637 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9638 (xor:SI (zero_extract:SI (match_dup 1)
9639 (const_int 8) (const_int 8))
9641 (clobber (reg:CC 17))])]
9642 "operands[0] = gen_lowpart (SImode, operands[0]);
9643 operands[1] = gen_lowpart (SImode, operands[1]);
9644 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9646 ;; Since XOR can be encoded with sign extended immediate, this is only
9647 ;; profitable when 7th bit is set.
9649 [(set (match_operand 0 "register_operand" "")
9650 (xor (match_operand 1 "general_operand" "")
9651 (match_operand 2 "const_int_operand" "")))
9652 (clobber (reg:CC 17))]
9654 && ANY_QI_REG_P (operands[0])
9655 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9656 && !(INTVAL (operands[2]) & ~255)
9657 && (INTVAL (operands[2]) & 128)
9658 && GET_MODE (operands[0]) != QImode"
9659 [(parallel [(set (strict_low_part (match_dup 0))
9660 (xor:QI (match_dup 1)
9662 (clobber (reg:CC 17))])]
9663 "operands[0] = gen_lowpart (QImode, operands[0]);
9664 operands[1] = gen_lowpart (QImode, operands[1]);
9665 operands[2] = gen_lowpart (QImode, operands[2]);")
9667 ;; Negation instructions
9669 (define_expand "negdi2"
9670 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9671 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9672 (clobber (reg:CC 17))])]
9674 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9676 (define_insn "*negdi2_1"
9677 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9678 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9679 (clobber (reg:CC 17))]
9681 && ix86_unary_operator_ok (NEG, DImode, operands)"
9685 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9686 (neg:DI (match_operand:DI 1 "general_operand" "")))
9687 (clobber (reg:CC 17))]
9688 "!TARGET_64BIT && reload_completed"
9691 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9692 (set (match_dup 0) (neg:SI (match_dup 2)))])
9695 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9698 (clobber (reg:CC 17))])
9701 (neg:SI (match_dup 1)))
9702 (clobber (reg:CC 17))])]
9703 "split_di (operands+1, 1, operands+2, operands+3);
9704 split_di (operands+0, 1, operands+0, operands+1);")
9706 (define_insn "*negdi2_1_rex64"
9707 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9708 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9709 (clobber (reg:CC 17))]
9710 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9712 [(set_attr "type" "negnot")
9713 (set_attr "mode" "DI")])
9715 ;; The problem with neg is that it does not perform (compare x 0),
9716 ;; it really performs (compare 0 x), which leaves us with the zero
9717 ;; flag being the only useful item.
9719 (define_insn "*negdi2_cmpz_rex64"
9721 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9723 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9724 (neg:DI (match_dup 1)))]
9725 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9727 [(set_attr "type" "negnot")
9728 (set_attr "mode" "DI")])
9731 (define_expand "negsi2"
9732 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9733 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9734 (clobber (reg:CC 17))])]
9736 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9738 (define_insn "*negsi2_1"
9739 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9740 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9741 (clobber (reg:CC 17))]
9742 "ix86_unary_operator_ok (NEG, SImode, operands)"
9744 [(set_attr "type" "negnot")
9745 (set_attr "mode" "SI")])
9747 ;; Combine is quite creative about this pattern.
9748 (define_insn "*negsi2_1_zext"
9749 [(set (match_operand:DI 0 "register_operand" "=r")
9750 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9753 (clobber (reg:CC 17))]
9754 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9756 [(set_attr "type" "negnot")
9757 (set_attr "mode" "SI")])
9759 ;; The problem with neg is that it does not perform (compare x 0),
9760 ;; it really performs (compare 0 x), which leaves us with the zero
9761 ;; flag being the only useful item.
9763 (define_insn "*negsi2_cmpz"
9765 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9767 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9768 (neg:SI (match_dup 1)))]
9769 "ix86_unary_operator_ok (NEG, SImode, operands)"
9771 [(set_attr "type" "negnot")
9772 (set_attr "mode" "SI")])
9774 (define_insn "*negsi2_cmpz_zext"
9776 (compare:CCZ (lshiftrt:DI
9778 (match_operand:DI 1 "register_operand" "0")
9782 (set (match_operand:DI 0 "register_operand" "=r")
9783 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9786 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9788 [(set_attr "type" "negnot")
9789 (set_attr "mode" "SI")])
9791 (define_expand "neghi2"
9792 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9793 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9794 (clobber (reg:CC 17))])]
9795 "TARGET_HIMODE_MATH"
9796 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9798 (define_insn "*neghi2_1"
9799 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9800 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9801 (clobber (reg:CC 17))]
9802 "ix86_unary_operator_ok (NEG, HImode, operands)"
9804 [(set_attr "type" "negnot")
9805 (set_attr "mode" "HI")])
9807 (define_insn "*neghi2_cmpz"
9809 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9811 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9812 (neg:HI (match_dup 1)))]
9813 "ix86_unary_operator_ok (NEG, HImode, operands)"
9815 [(set_attr "type" "negnot")
9816 (set_attr "mode" "HI")])
9818 (define_expand "negqi2"
9819 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9820 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9821 (clobber (reg:CC 17))])]
9822 "TARGET_QIMODE_MATH"
9823 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9825 (define_insn "*negqi2_1"
9826 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9827 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9828 (clobber (reg:CC 17))]
9829 "ix86_unary_operator_ok (NEG, QImode, operands)"
9831 [(set_attr "type" "negnot")
9832 (set_attr "mode" "QI")])
9834 (define_insn "*negqi2_cmpz"
9836 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9838 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9839 (neg:QI (match_dup 1)))]
9840 "ix86_unary_operator_ok (NEG, QImode, operands)"
9842 [(set_attr "type" "negnot")
9843 (set_attr "mode" "QI")])
9845 ;; Changing of sign for FP values is doable using integer unit too.
9847 (define_expand "negsf2"
9848 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9849 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9850 (clobber (reg:CC 17))])]
9854 /* In case operand is in memory, we will not use SSE. */
9855 if (memory_operand (operands[0], VOIDmode)
9856 && rtx_equal_p (operands[0], operands[1]))
9857 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9860 /* Using SSE is tricky, since we need bitwise negation of -0
9862 rtx reg = gen_reg_rtx (SFmode);
9863 rtx dest = operands[0];
9864 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9866 operands[1] = force_reg (SFmode, operands[1]);
9867 operands[0] = force_reg (SFmode, operands[0]);
9868 reg = force_reg (V4SFmode,
9869 gen_rtx_CONST_VECTOR (V4SFmode,
9870 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9871 CONST0_RTX (SFmode),
9872 CONST0_RTX (SFmode))));
9873 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9874 if (dest != operands[0])
9875 emit_move_insn (dest, operands[0]);
9879 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9881 (define_insn "negsf2_memory"
9882 [(set (match_operand:SF 0 "memory_operand" "=m")
9883 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9884 (clobber (reg:CC 17))]
9885 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9888 (define_insn "negsf2_ifs"
9889 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9890 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9891 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9892 (clobber (reg:CC 17))]
9894 && (reload_in_progress || reload_completed
9895 || (register_operand (operands[0], VOIDmode)
9896 && register_operand (operands[1], VOIDmode)))"
9900 [(set (match_operand:SF 0 "memory_operand" "")
9901 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9902 (use (match_operand:SF 2 "" ""))
9903 (clobber (reg:CC 17))]
9905 [(parallel [(set (match_dup 0)
9906 (neg:SF (match_dup 1)))
9907 (clobber (reg:CC 17))])])
9910 [(set (match_operand:SF 0 "register_operand" "")
9911 (neg:SF (match_operand:SF 1 "register_operand" "")))
9912 (use (match_operand:V4SF 2 "" ""))
9913 (clobber (reg:CC 17))]
9914 "reload_completed && !SSE_REG_P (operands[0])"
9915 [(parallel [(set (match_dup 0)
9916 (neg:SF (match_dup 1)))
9917 (clobber (reg:CC 17))])])
9920 [(set (match_operand:SF 0 "register_operand" "")
9921 (neg:SF (match_operand:SF 1 "register_operand" "")))
9922 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9923 (clobber (reg:CC 17))]
9924 "reload_completed && SSE_REG_P (operands[0])"
9925 [(set (subreg:TI (match_dup 0) 0)
9926 (xor:TI (match_dup 1)
9929 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9930 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9931 if (operands_match_p (operands[0], operands[2]))
9935 operands[1] = operands[2];
9941 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9942 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9944 (define_insn "*negsf2_if"
9945 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9946 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9947 (clobber (reg:CC 17))]
9948 "TARGET_80387 && !TARGET_SSE
9949 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9953 [(set (match_operand:SF 0 "fp_register_operand" "")
9954 (neg:SF (match_operand:SF 1 "register_operand" "")))
9955 (clobber (reg:CC 17))]
9956 "TARGET_80387 && reload_completed"
9958 (neg:SF (match_dup 1)))]
9962 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9963 (neg:SF (match_operand:SF 1 "register_operand" "")))
9964 (clobber (reg:CC 17))]
9965 "TARGET_80387 && reload_completed"
9966 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9967 (clobber (reg:CC 17))])]
9968 "operands[1] = gen_int_mode (0x80000000, SImode);
9969 operands[0] = gen_lowpart (SImode, operands[0]);")
9972 [(set (match_operand 0 "memory_operand" "")
9973 (neg (match_operand 1 "memory_operand" "")))
9974 (clobber (reg:CC 17))]
9975 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9976 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9977 (clobber (reg:CC 17))])]
9979 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9981 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9984 operands[0] = adjust_address (operands[0], QImode, size - 1);
9985 operands[1] = gen_int_mode (0x80, QImode);
9988 (define_expand "negdf2"
9989 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9990 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9991 (clobber (reg:CC 17))])]
9995 /* In case operand is in memory, we will not use SSE. */
9996 if (memory_operand (operands[0], VOIDmode)
9997 && rtx_equal_p (operands[0], operands[1]))
9998 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
10001 /* Using SSE is tricky, since we need bitwise negation of -0
10004 #if HOST_BITS_PER_WIDE_INT >= 64
10005 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
10007 rtx imm = immed_double_const (0, 0x80000000, DImode);
10009 rtx dest = operands[0];
10011 operands[1] = force_reg (DFmode, operands[1]);
10012 operands[0] = force_reg (DFmode, operands[0]);
10013 imm = gen_lowpart (DFmode, imm);
10014 reg = force_reg (V2DFmode,
10015 gen_rtx_CONST_VECTOR (V2DFmode,
10016 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10017 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
10018 if (dest != operands[0])
10019 emit_move_insn (dest, operands[0]);
10023 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
10025 (define_insn "negdf2_memory"
10026 [(set (match_operand:DF 0 "memory_operand" "=m")
10027 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
10028 (clobber (reg:CC 17))]
10029 "ix86_unary_operator_ok (NEG, DFmode, operands)"
10032 (define_insn "negdf2_ifs"
10033 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
10034 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10035 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10036 (clobber (reg:CC 17))]
10037 "!TARGET_64BIT && TARGET_SSE2
10038 && (reload_in_progress || reload_completed
10039 || (register_operand (operands[0], VOIDmode)
10040 && register_operand (operands[1], VOIDmode)))"
10043 (define_insn "*negdf2_ifs_rex64"
10044 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
10045 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10046 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10047 (clobber (reg:CC 17))]
10048 "TARGET_64BIT && TARGET_SSE2
10049 && (reload_in_progress || reload_completed
10050 || (register_operand (operands[0], VOIDmode)
10051 && register_operand (operands[1], VOIDmode)))"
10055 [(set (match_operand:DF 0 "memory_operand" "")
10056 (neg:DF (match_operand:DF 1 "memory_operand" "")))
10057 (use (match_operand:V2DF 2 "" ""))
10058 (clobber (reg:CC 17))]
10060 [(parallel [(set (match_dup 0)
10061 (neg:DF (match_dup 1)))
10062 (clobber (reg:CC 17))])])
10065 [(set (match_operand:DF 0 "register_operand" "")
10066 (neg:DF (match_operand:DF 1 "register_operand" "")))
10067 (use (match_operand:V2DF 2 "" ""))
10068 (clobber (reg:CC 17))]
10069 "reload_completed && !SSE_REG_P (operands[0])
10070 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
10071 [(parallel [(set (match_dup 0)
10072 (neg:DF (match_dup 1)))
10073 (clobber (reg:CC 17))])])
10076 [(set (match_operand:DF 0 "register_operand" "")
10077 (neg:DF (match_operand:DF 1 "register_operand" "")))
10078 (use (match_operand:V2DF 2 "" ""))
10079 (clobber (reg:CC 17))]
10080 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
10081 [(parallel [(set (match_dup 0)
10082 (xor:DI (match_dup 1) (match_dup 2)))
10083 (clobber (reg:CC 17))])]
10084 "operands[0] = gen_lowpart (DImode, operands[0]);
10085 operands[1] = gen_lowpart (DImode, operands[1]);
10086 operands[2] = gen_lowpart (DImode, operands[2]);")
10089 [(set (match_operand:DF 0 "register_operand" "")
10090 (neg:DF (match_operand:DF 1 "register_operand" "")))
10091 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10092 (clobber (reg:CC 17))]
10093 "reload_completed && SSE_REG_P (operands[0])"
10094 [(set (subreg:TI (match_dup 0) 0)
10095 (xor:TI (match_dup 1)
10098 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10099 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10100 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10101 /* Avoid possible reformatting on the operands. */
10102 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10103 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10104 if (operands_match_p (operands[0], operands[2]))
10108 operands[1] = operands[2];
10113 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10114 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10116 (define_insn "*negdf2_if"
10117 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10118 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10119 (clobber (reg:CC 17))]
10120 "!TARGET_64BIT && TARGET_80387
10121 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10124 ;; FIXME: We should to allow integer registers here. Problem is that
10125 ;; we need another scratch register to get constant from.
10126 ;; Forcing constant to mem if no register available in peep2 should be
10127 ;; safe even for PIC mode, because of RIP relative addressing.
10128 (define_insn "*negdf2_if_rex64"
10129 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10130 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10131 (clobber (reg:CC 17))]
10132 "TARGET_64BIT && TARGET_80387
10133 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10137 [(set (match_operand:DF 0 "fp_register_operand" "")
10138 (neg:DF (match_operand:DF 1 "register_operand" "")))
10139 (clobber (reg:CC 17))]
10140 "TARGET_80387 && reload_completed"
10141 [(set (match_dup 0)
10142 (neg:DF (match_dup 1)))]
10146 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10147 (neg:DF (match_operand:DF 1 "register_operand" "")))
10148 (clobber (reg:CC 17))]
10149 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10150 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
10151 (clobber (reg:CC 17))])]
10152 "operands[4] = gen_int_mode (0x80000000, SImode);
10153 split_di (operands+0, 1, operands+2, operands+3);")
10155 (define_expand "negxf2"
10156 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10157 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10158 (clobber (reg:CC 17))])]
10159 "!TARGET_64BIT && TARGET_80387"
10160 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
10162 (define_expand "negtf2"
10163 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10164 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10165 (clobber (reg:CC 17))])]
10167 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
10169 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10170 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10172 (define_insn "*negxf2_if"
10173 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10174 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10175 (clobber (reg:CC 17))]
10176 "!TARGET_64BIT && TARGET_80387
10177 && ix86_unary_operator_ok (NEG, XFmode, operands)"
10181 [(set (match_operand:XF 0 "fp_register_operand" "")
10182 (neg:XF (match_operand:XF 1 "register_operand" "")))
10183 (clobber (reg:CC 17))]
10184 "TARGET_80387 && reload_completed"
10185 [(set (match_dup 0)
10186 (neg:XF (match_dup 1)))]
10190 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10191 (neg:XF (match_operand:XF 1 "register_operand" "")))
10192 (clobber (reg:CC 17))]
10193 "TARGET_80387 && reload_completed"
10194 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10195 (clobber (reg:CC 17))])]
10196 "operands[1] = GEN_INT (0x8000);
10197 operands[0] = gen_rtx_REG (SImode,
10198 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10200 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10201 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10203 (define_insn "*negtf2_if"
10204 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10205 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10206 (clobber (reg:CC 17))]
10207 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
10211 [(set (match_operand:TF 0 "fp_register_operand" "")
10212 (neg:TF (match_operand:TF 1 "register_operand" "")))
10213 (clobber (reg:CC 17))]
10214 "TARGET_80387 && reload_completed"
10215 [(set (match_dup 0)
10216 (neg:TF (match_dup 1)))]
10220 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
10221 (neg:TF (match_operand:TF 1 "register_operand" "")))
10222 (clobber (reg:CC 17))]
10223 "TARGET_80387 && reload_completed"
10224 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10225 (clobber (reg:CC 17))])]
10226 "operands[1] = GEN_INT (0x8000);
10227 operands[0] = gen_rtx_REG (SImode,
10228 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10230 ;; Conditionalize these after reload. If they matches before reload, we
10231 ;; lose the clobber and ability to use integer instructions.
10233 (define_insn "*negsf2_1"
10234 [(set (match_operand:SF 0 "register_operand" "=f")
10235 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
10236 "TARGET_80387 && reload_completed"
10238 [(set_attr "type" "fsgn")
10239 (set_attr "mode" "SF")
10240 (set_attr "ppro_uops" "few")])
10242 (define_insn "*negdf2_1"
10243 [(set (match_operand:DF 0 "register_operand" "=f")
10244 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
10245 "TARGET_80387 && reload_completed"
10247 [(set_attr "type" "fsgn")
10248 (set_attr "mode" "DF")
10249 (set_attr "ppro_uops" "few")])
10251 (define_insn "*negextendsfdf2"
10252 [(set (match_operand:DF 0 "register_operand" "=f")
10253 (neg:DF (float_extend:DF
10254 (match_operand:SF 1 "register_operand" "0"))))]
10257 [(set_attr "type" "fsgn")
10258 (set_attr "mode" "DF")
10259 (set_attr "ppro_uops" "few")])
10261 (define_insn "*negxf2_1"
10262 [(set (match_operand:XF 0 "register_operand" "=f")
10263 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
10264 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10266 [(set_attr "type" "fsgn")
10267 (set_attr "mode" "XF")
10268 (set_attr "ppro_uops" "few")])
10270 (define_insn "*negextenddfxf2"
10271 [(set (match_operand:XF 0 "register_operand" "=f")
10272 (neg:XF (float_extend:XF
10273 (match_operand:DF 1 "register_operand" "0"))))]
10274 "!TARGET_64BIT && TARGET_80387"
10276 [(set_attr "type" "fsgn")
10277 (set_attr "mode" "XF")
10278 (set_attr "ppro_uops" "few")])
10280 (define_insn "*negextendsfxf2"
10281 [(set (match_operand:XF 0 "register_operand" "=f")
10282 (neg:XF (float_extend:XF
10283 (match_operand:SF 1 "register_operand" "0"))))]
10284 "!TARGET_64BIT && TARGET_80387"
10286 [(set_attr "type" "fsgn")
10287 (set_attr "mode" "XF")
10288 (set_attr "ppro_uops" "few")])
10290 (define_insn "*negtf2_1"
10291 [(set (match_operand:TF 0 "register_operand" "=f")
10292 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
10293 "TARGET_80387 && reload_completed"
10295 [(set_attr "type" "fsgn")
10296 (set_attr "mode" "XF")
10297 (set_attr "ppro_uops" "few")])
10299 (define_insn "*negextenddftf2"
10300 [(set (match_operand:TF 0 "register_operand" "=f")
10301 (neg:TF (float_extend:TF
10302 (match_operand:DF 1 "register_operand" "0"))))]
10305 [(set_attr "type" "fsgn")
10306 (set_attr "mode" "XF")
10307 (set_attr "ppro_uops" "few")])
10309 (define_insn "*negextendsftf2"
10310 [(set (match_operand:TF 0 "register_operand" "=f")
10311 (neg:TF (float_extend:TF
10312 (match_operand:SF 1 "register_operand" "0"))))]
10315 [(set_attr "type" "fsgn")
10316 (set_attr "mode" "XF")
10317 (set_attr "ppro_uops" "few")])
10319 ;; Absolute value instructions
10321 (define_expand "abssf2"
10322 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
10323 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
10324 (clobber (reg:CC 17))])]
10328 /* In case operand is in memory, we will not use SSE. */
10329 if (memory_operand (operands[0], VOIDmode)
10330 && rtx_equal_p (operands[0], operands[1]))
10331 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10334 /* Using SSE is tricky, since we need bitwise negation of -0
10336 rtx reg = gen_reg_rtx (V4SFmode);
10337 rtx dest = operands[0];
10340 operands[1] = force_reg (SFmode, operands[1]);
10341 operands[0] = force_reg (SFmode, operands[0]);
10342 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10343 reg = force_reg (V4SFmode,
10344 gen_rtx_CONST_VECTOR (V4SFmode,
10345 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10346 CONST0_RTX (SFmode),
10347 CONST0_RTX (SFmode))));
10348 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10349 if (dest != operands[0])
10350 emit_move_insn (dest, operands[0]);
10354 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10356 (define_insn "abssf2_memory"
10357 [(set (match_operand:SF 0 "memory_operand" "=m")
10358 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10359 (clobber (reg:CC 17))]
10360 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10363 (define_insn "abssf2_ifs"
10364 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10365 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10366 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10367 (clobber (reg:CC 17))]
10369 && (reload_in_progress || reload_completed
10370 || (register_operand (operands[0], VOIDmode)
10371 && register_operand (operands[1], VOIDmode)))"
10375 [(set (match_operand:SF 0 "memory_operand" "")
10376 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10377 (use (match_operand:V4SF 2 "" ""))
10378 (clobber (reg:CC 17))]
10380 [(parallel [(set (match_dup 0)
10381 (abs:SF (match_dup 1)))
10382 (clobber (reg:CC 17))])])
10385 [(set (match_operand:SF 0 "register_operand" "")
10386 (abs:SF (match_operand:SF 1 "register_operand" "")))
10387 (use (match_operand:V4SF 2 "" ""))
10388 (clobber (reg:CC 17))]
10389 "reload_completed && !SSE_REG_P (operands[0])"
10390 [(parallel [(set (match_dup 0)
10391 (abs:SF (match_dup 1)))
10392 (clobber (reg:CC 17))])])
10395 [(set (match_operand:SF 0 "register_operand" "")
10396 (abs:SF (match_operand:SF 1 "register_operand" "")))
10397 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10398 (clobber (reg:CC 17))]
10399 "reload_completed && SSE_REG_P (operands[0])"
10400 [(set (subreg:TI (match_dup 0) 0)
10401 (and:TI (match_dup 1)
10404 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10405 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10406 if (operands_match_p (operands[0], operands[2]))
10410 operands[1] = operands[2];
10415 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10416 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10418 (define_insn "*abssf2_if"
10419 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10420 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10421 (clobber (reg:CC 17))]
10422 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10426 [(set (match_operand:SF 0 "fp_register_operand" "")
10427 (abs:SF (match_operand:SF 1 "register_operand" "")))
10428 (clobber (reg:CC 17))]
10429 "TARGET_80387 && reload_completed"
10430 [(set (match_dup 0)
10431 (abs:SF (match_dup 1)))]
10435 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10436 (abs:SF (match_operand:SF 1 "register_operand" "")))
10437 (clobber (reg:CC 17))]
10438 "TARGET_80387 && reload_completed"
10439 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10440 (clobber (reg:CC 17))])]
10441 "operands[1] = gen_int_mode (~0x80000000, SImode);
10442 operands[0] = gen_lowpart (SImode, operands[0]);")
10445 [(set (match_operand 0 "memory_operand" "")
10446 (abs (match_operand 1 "memory_operand" "")))
10447 (clobber (reg:CC 17))]
10448 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10449 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10450 (clobber (reg:CC 17))])]
10452 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10454 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
10457 operands[0] = adjust_address (operands[0], QImode, size - 1);
10458 operands[1] = gen_int_mode (~0x80, QImode);
10461 (define_expand "absdf2"
10462 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10463 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10464 (clobber (reg:CC 17))])]
10468 /* In case operand is in memory, we will not use SSE. */
10469 if (memory_operand (operands[0], VOIDmode)
10470 && rtx_equal_p (operands[0], operands[1]))
10471 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10474 /* Using SSE is tricky, since we need bitwise negation of -0
10476 rtx reg = gen_reg_rtx (V2DFmode);
10477 #if HOST_BITS_PER_WIDE_INT >= 64
10478 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10480 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10482 rtx dest = operands[0];
10484 operands[1] = force_reg (DFmode, operands[1]);
10485 operands[0] = force_reg (DFmode, operands[0]);
10487 /* Produce LONG_DOUBLE with the proper immediate argument. */
10488 imm = gen_lowpart (DFmode, imm);
10489 reg = force_reg (V2DFmode,
10490 gen_rtx_CONST_VECTOR (V2DFmode,
10491 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10492 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10493 if (dest != operands[0])
10494 emit_move_insn (dest, operands[0]);
10498 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10500 (define_insn "absdf2_memory"
10501 [(set (match_operand:DF 0 "memory_operand" "=m")
10502 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10503 (clobber (reg:CC 17))]
10504 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10507 (define_insn "absdf2_ifs"
10508 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10509 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10510 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10511 (clobber (reg:CC 17))]
10512 "!TARGET_64BIT && TARGET_SSE2
10513 && (reload_in_progress || reload_completed
10514 || (register_operand (operands[0], VOIDmode)
10515 && register_operand (operands[1], VOIDmode)))"
10518 (define_insn "*absdf2_ifs_rex64"
10519 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10520 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10521 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10522 (clobber (reg:CC 17))]
10523 "TARGET_64BIT && TARGET_SSE2
10524 && (reload_in_progress || reload_completed
10525 || (register_operand (operands[0], VOIDmode)
10526 && register_operand (operands[1], VOIDmode)))"
10530 [(set (match_operand:DF 0 "memory_operand" "")
10531 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10532 (use (match_operand:V2DF 2 "" ""))
10533 (clobber (reg:CC 17))]
10535 [(parallel [(set (match_dup 0)
10536 (abs:DF (match_dup 1)))
10537 (clobber (reg:CC 17))])])
10540 [(set (match_operand:DF 0 "register_operand" "")
10541 (abs:DF (match_operand:DF 1 "register_operand" "")))
10542 (use (match_operand:V2DF 2 "" ""))
10543 (clobber (reg:CC 17))]
10544 "reload_completed && !SSE_REG_P (operands[0])"
10545 [(parallel [(set (match_dup 0)
10546 (abs:DF (match_dup 1)))
10547 (clobber (reg:CC 17))])])
10550 [(set (match_operand:DF 0 "register_operand" "")
10551 (abs:DF (match_operand:DF 1 "register_operand" "")))
10552 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10553 (clobber (reg:CC 17))]
10554 "reload_completed && SSE_REG_P (operands[0])"
10555 [(set (subreg:TI (match_dup 0) 0)
10556 (and:TI (match_dup 1)
10559 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10560 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10561 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10562 /* Avoid possible reformatting on the operands. */
10563 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10564 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10565 if (operands_match_p (operands[0], operands[2]))
10569 operands[1] = operands[2];
10575 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10576 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10578 (define_insn "*absdf2_if"
10579 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10580 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10581 (clobber (reg:CC 17))]
10582 "!TARGET_64BIT && TARGET_80387
10583 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10586 ;; FIXME: We should to allow integer registers here. Problem is that
10587 ;; we need another scratch register to get constant from.
10588 ;; Forcing constant to mem if no register available in peep2 should be
10589 ;; safe even for PIC mode, because of RIP relative addressing.
10590 (define_insn "*absdf2_if_rex64"
10591 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10592 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10593 (clobber (reg:CC 17))]
10594 "TARGET_64BIT && TARGET_80387
10595 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10599 [(set (match_operand:DF 0 "fp_register_operand" "")
10600 (abs:DF (match_operand:DF 1 "register_operand" "")))
10601 (clobber (reg:CC 17))]
10602 "TARGET_80387 && reload_completed"
10603 [(set (match_dup 0)
10604 (abs:DF (match_dup 1)))]
10608 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10609 (abs:DF (match_operand:DF 1 "register_operand" "")))
10610 (clobber (reg:CC 17))]
10611 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10612 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10613 (clobber (reg:CC 17))])]
10614 "operands[4] = gen_int_mode (~0x80000000, SImode);
10615 split_di (operands+0, 1, operands+2, operands+3);")
10617 (define_expand "absxf2"
10618 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10619 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10620 (clobber (reg:CC 17))])]
10621 "!TARGET_64BIT && TARGET_80387"
10622 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10624 (define_expand "abstf2"
10625 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10626 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10627 (clobber (reg:CC 17))])]
10629 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10631 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10632 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10634 (define_insn "*absxf2_if"
10635 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10636 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10637 (clobber (reg:CC 17))]
10638 "!TARGET_64BIT && TARGET_80387
10639 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10643 [(set (match_operand:XF 0 "fp_register_operand" "")
10644 (abs:XF (match_operand:XF 1 "register_operand" "")))
10645 (clobber (reg:CC 17))]
10646 "TARGET_80387 && reload_completed"
10647 [(set (match_dup 0)
10648 (abs:XF (match_dup 1)))]
10652 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10653 (abs:XF (match_operand:XF 1 "register_operand" "")))
10654 (clobber (reg:CC 17))]
10655 "TARGET_80387 && reload_completed"
10656 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10657 (clobber (reg:CC 17))])]
10658 "operands[1] = GEN_INT (~0x8000);
10659 operands[0] = gen_rtx_REG (SImode,
10660 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10662 (define_insn "*abstf2_if"
10663 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10664 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10665 (clobber (reg:CC 17))]
10666 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10670 [(set (match_operand:TF 0 "fp_register_operand" "")
10671 (abs:TF (match_operand:TF 1 "register_operand" "")))
10672 (clobber (reg:CC 17))]
10673 "TARGET_80387 && reload_completed"
10674 [(set (match_dup 0)
10675 (abs:TF (match_dup 1)))]
10679 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10680 (abs:TF (match_operand:TF 1 "register_operand" "")))
10681 (clobber (reg:CC 17))]
10682 "TARGET_80387 && reload_completed"
10683 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10684 (clobber (reg:CC 17))])]
10685 "operands[1] = GEN_INT (~0x8000);
10686 operands[0] = gen_rtx_REG (SImode,
10687 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10689 (define_insn "*abssf2_1"
10690 [(set (match_operand:SF 0 "register_operand" "=f")
10691 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10692 "TARGET_80387 && reload_completed"
10694 [(set_attr "type" "fsgn")
10695 (set_attr "mode" "SF")])
10697 (define_insn "*absdf2_1"
10698 [(set (match_operand:DF 0 "register_operand" "=f")
10699 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10700 "TARGET_80387 && reload_completed"
10702 [(set_attr "type" "fsgn")
10703 (set_attr "mode" "DF")])
10705 (define_insn "*absextendsfdf2"
10706 [(set (match_operand:DF 0 "register_operand" "=f")
10707 (abs:DF (float_extend:DF
10708 (match_operand:SF 1 "register_operand" "0"))))]
10711 [(set_attr "type" "fsgn")
10712 (set_attr "mode" "DF")])
10714 (define_insn "*absxf2_1"
10715 [(set (match_operand:XF 0 "register_operand" "=f")
10716 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10717 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10719 [(set_attr "type" "fsgn")
10720 (set_attr "mode" "DF")])
10722 (define_insn "*absextenddfxf2"
10723 [(set (match_operand:XF 0 "register_operand" "=f")
10724 (abs:XF (float_extend:XF
10725 (match_operand:DF 1 "register_operand" "0"))))]
10726 "!TARGET_64BIT && TARGET_80387"
10728 [(set_attr "type" "fsgn")
10729 (set_attr "mode" "XF")])
10731 (define_insn "*absextendsfxf2"
10732 [(set (match_operand:XF 0 "register_operand" "=f")
10733 (abs:XF (float_extend:XF
10734 (match_operand:SF 1 "register_operand" "0"))))]
10735 "!TARGET_64BIT && TARGET_80387"
10737 [(set_attr "type" "fsgn")
10738 (set_attr "mode" "XF")])
10740 (define_insn "*abstf2_1"
10741 [(set (match_operand:TF 0 "register_operand" "=f")
10742 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10743 "TARGET_80387 && reload_completed"
10745 [(set_attr "type" "fsgn")
10746 (set_attr "mode" "DF")])
10748 (define_insn "*absextenddftf2"
10749 [(set (match_operand:TF 0 "register_operand" "=f")
10750 (abs:TF (float_extend:TF
10751 (match_operand:DF 1 "register_operand" "0"))))]
10754 [(set_attr "type" "fsgn")
10755 (set_attr "mode" "XF")])
10757 (define_insn "*absextendsftf2"
10758 [(set (match_operand:TF 0 "register_operand" "=f")
10759 (abs:TF (float_extend:TF
10760 (match_operand:SF 1 "register_operand" "0"))))]
10763 [(set_attr "type" "fsgn")
10764 (set_attr "mode" "XF")])
10766 ;; One complement instructions
10768 (define_expand "one_cmpldi2"
10769 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10770 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10772 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10774 (define_insn "*one_cmpldi2_1_rex64"
10775 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10776 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10777 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10779 [(set_attr "type" "negnot")
10780 (set_attr "mode" "DI")])
10782 (define_insn "*one_cmpldi2_2_rex64"
10784 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10786 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10787 (not:DI (match_dup 1)))]
10788 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10789 && ix86_unary_operator_ok (NOT, DImode, operands)"
10791 [(set_attr "type" "alu1")
10792 (set_attr "mode" "DI")])
10796 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10798 (set (match_operand:DI 0 "nonimmediate_operand" "")
10799 (not:DI (match_dup 1)))]
10800 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10801 [(parallel [(set (reg:CCNO 17)
10802 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10805 (xor:DI (match_dup 1) (const_int -1)))])]
10808 (define_expand "one_cmplsi2"
10809 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10810 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10812 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10814 (define_insn "*one_cmplsi2_1"
10815 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10816 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10817 "ix86_unary_operator_ok (NOT, SImode, operands)"
10819 [(set_attr "type" "negnot")
10820 (set_attr "mode" "SI")])
10822 ;; ??? Currently never generated - xor is used instead.
10823 (define_insn "*one_cmplsi2_1_zext"
10824 [(set (match_operand:DI 0 "register_operand" "=r")
10825 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10826 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10828 [(set_attr "type" "negnot")
10829 (set_attr "mode" "SI")])
10831 (define_insn "*one_cmplsi2_2"
10833 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10835 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10836 (not:SI (match_dup 1)))]
10837 "ix86_match_ccmode (insn, CCNOmode)
10838 && ix86_unary_operator_ok (NOT, SImode, operands)"
10840 [(set_attr "type" "alu1")
10841 (set_attr "mode" "SI")])
10845 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10847 (set (match_operand:SI 0 "nonimmediate_operand" "")
10848 (not:SI (match_dup 1)))]
10849 "ix86_match_ccmode (insn, CCNOmode)"
10850 [(parallel [(set (reg:CCNO 17)
10851 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10854 (xor:SI (match_dup 1) (const_int -1)))])]
10857 ;; ??? Currently never generated - xor is used instead.
10858 (define_insn "*one_cmplsi2_2_zext"
10860 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10862 (set (match_operand:DI 0 "register_operand" "=r")
10863 (zero_extend:DI (not:SI (match_dup 1))))]
10864 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10865 && ix86_unary_operator_ok (NOT, SImode, operands)"
10867 [(set_attr "type" "alu1")
10868 (set_attr "mode" "SI")])
10872 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10874 (set (match_operand:DI 0 "register_operand" "")
10875 (zero_extend:DI (not:SI (match_dup 1))))]
10876 "ix86_match_ccmode (insn, CCNOmode)"
10877 [(parallel [(set (reg:CCNO 17)
10878 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10881 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10884 (define_expand "one_cmplhi2"
10885 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10886 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10887 "TARGET_HIMODE_MATH"
10888 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10890 (define_insn "*one_cmplhi2_1"
10891 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10892 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10893 "ix86_unary_operator_ok (NOT, HImode, operands)"
10895 [(set_attr "type" "negnot")
10896 (set_attr "mode" "HI")])
10898 (define_insn "*one_cmplhi2_2"
10900 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10902 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10903 (not:HI (match_dup 1)))]
10904 "ix86_match_ccmode (insn, CCNOmode)
10905 && ix86_unary_operator_ok (NEG, HImode, operands)"
10907 [(set_attr "type" "alu1")
10908 (set_attr "mode" "HI")])
10912 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10914 (set (match_operand:HI 0 "nonimmediate_operand" "")
10915 (not:HI (match_dup 1)))]
10916 "ix86_match_ccmode (insn, CCNOmode)"
10917 [(parallel [(set (reg:CCNO 17)
10918 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10921 (xor:HI (match_dup 1) (const_int -1)))])]
10924 ;; %%% Potential partial reg stall on alternative 1. What to do?
10925 (define_expand "one_cmplqi2"
10926 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10927 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10928 "TARGET_QIMODE_MATH"
10929 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10931 (define_insn "*one_cmplqi2_1"
10932 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10933 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10934 "ix86_unary_operator_ok (NOT, QImode, operands)"
10938 [(set_attr "type" "negnot")
10939 (set_attr "mode" "QI,SI")])
10941 (define_insn "*one_cmplqi2_2"
10943 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10945 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10946 (not:QI (match_dup 1)))]
10947 "ix86_match_ccmode (insn, CCNOmode)
10948 && ix86_unary_operator_ok (NOT, QImode, operands)"
10950 [(set_attr "type" "alu1")
10951 (set_attr "mode" "QI")])
10955 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10957 (set (match_operand:QI 0 "nonimmediate_operand" "")
10958 (not:QI (match_dup 1)))]
10959 "ix86_match_ccmode (insn, CCNOmode)"
10960 [(parallel [(set (reg:CCNO 17)
10961 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10964 (xor:QI (match_dup 1) (const_int -1)))])]
10967 ;; Arithmetic shift instructions
10969 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10970 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10971 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10972 ;; from the assembler input.
10974 ;; This instruction shifts the target reg/mem as usual, but instead of
10975 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10976 ;; is a left shift double, bits are taken from the high order bits of
10977 ;; reg, else if the insn is a shift right double, bits are taken from the
10978 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10979 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10981 ;; Since sh[lr]d does not change the `reg' operand, that is done
10982 ;; separately, making all shifts emit pairs of shift double and normal
10983 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10984 ;; support a 63 bit shift, each shift where the count is in a reg expands
10985 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10987 ;; If the shift count is a constant, we need never emit more than one
10988 ;; shift pair, instead using moves and sign extension for counts greater
10991 (define_expand "ashldi3"
10992 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10993 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10994 (match_operand:QI 2 "nonmemory_operand" "")))
10995 (clobber (reg:CC 17))])]
10998 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11000 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
11003 ix86_expand_binary_operator (ASHIFT, DImode, operands);
11007 (define_insn "*ashldi3_1_rex64"
11008 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
11009 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
11010 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
11011 (clobber (reg:CC 17))]
11012 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11014 switch (get_attr_type (insn))
11017 if (operands[2] != const1_rtx)
11019 if (!rtx_equal_p (operands[0], operands[1]))
11021 return "add{q}\t{%0, %0|%0, %0}";
11024 if (GET_CODE (operands[2]) != CONST_INT
11025 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
11027 operands[1] = gen_rtx_MULT (DImode, operands[1],
11028 GEN_INT (1 << INTVAL (operands[2])));
11029 return "lea{q}\t{%a1, %0|%0, %a1}";
11032 if (REG_P (operands[2]))
11033 return "sal{q}\t{%b2, %0|%0, %b2}";
11034 else if (GET_CODE (operands[2]) == CONST_INT
11035 && INTVAL (operands[2]) == 1
11036 && (TARGET_SHIFT1 || optimize_size))
11037 return "sal{q}\t%0";
11039 return "sal{q}\t{%2, %0|%0, %2}";
11042 [(set (attr "type")
11043 (cond [(eq_attr "alternative" "1")
11044 (const_string "lea")
11045 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11047 (match_operand 0 "register_operand" ""))
11048 (match_operand 2 "const1_operand" ""))
11049 (const_string "alu")
11051 (const_string "ishift")))
11052 (set_attr "mode" "DI")])
11054 ;; Convert lea to the lea pattern to avoid flags dependency.
11056 [(set (match_operand:DI 0 "register_operand" "")
11057 (ashift:DI (match_operand:DI 1 "register_operand" "")
11058 (match_operand:QI 2 "immediate_operand" "")))
11059 (clobber (reg:CC 17))]
11060 "TARGET_64BIT && reload_completed
11061 && true_regnum (operands[0]) != true_regnum (operands[1])"
11062 [(set (match_dup 0)
11063 (mult:DI (match_dup 1)
11065 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
11067 ;; This pattern can't accept a variable shift count, since shifts by
11068 ;; zero don't affect the flags. We assume that shifts by constant
11069 ;; zero are optimized away.
11070 (define_insn "*ashldi3_cmp_rex64"
11073 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11074 (match_operand:QI 2 "immediate_operand" "e"))
11076 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11077 (ashift:DI (match_dup 1) (match_dup 2)))]
11078 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11079 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11081 switch (get_attr_type (insn))
11084 if (operands[2] != const1_rtx)
11086 return "add{q}\t{%0, %0|%0, %0}";
11089 if (REG_P (operands[2]))
11090 return "sal{q}\t{%b2, %0|%0, %b2}";
11091 else if (GET_CODE (operands[2]) == CONST_INT
11092 && INTVAL (operands[2]) == 1
11093 && (TARGET_SHIFT1 || optimize_size))
11094 return "sal{q}\t%0";
11096 return "sal{q}\t{%2, %0|%0, %2}";
11099 [(set (attr "type")
11100 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11102 (match_operand 0 "register_operand" ""))
11103 (match_operand 2 "const1_operand" ""))
11104 (const_string "alu")
11106 (const_string "ishift")))
11107 (set_attr "mode" "DI")])
11109 (define_insn "ashldi3_1"
11110 [(set (match_operand:DI 0 "register_operand" "=r")
11111 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11112 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11113 (clobber (match_scratch:SI 3 "=&r"))
11114 (clobber (reg:CC 17))]
11115 "!TARGET_64BIT && TARGET_CMOVE"
11117 [(set_attr "type" "multi")])
11119 (define_insn "*ashldi3_2"
11120 [(set (match_operand:DI 0 "register_operand" "=r")
11121 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11122 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11123 (clobber (reg:CC 17))]
11126 [(set_attr "type" "multi")])
11129 [(set (match_operand:DI 0 "register_operand" "")
11130 (ashift:DI (match_operand:DI 1 "register_operand" "")
11131 (match_operand:QI 2 "nonmemory_operand" "")))
11132 (clobber (match_scratch:SI 3 ""))
11133 (clobber (reg:CC 17))]
11134 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11136 "ix86_split_ashldi (operands, operands[3]); DONE;")
11139 [(set (match_operand:DI 0 "register_operand" "")
11140 (ashift:DI (match_operand:DI 1 "register_operand" "")
11141 (match_operand:QI 2 "nonmemory_operand" "")))
11142 (clobber (reg:CC 17))]
11143 "!TARGET_64BIT && reload_completed"
11145 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
11147 (define_insn "x86_shld_1"
11148 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11149 (ior:SI (ashift:SI (match_dup 0)
11150 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11151 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
11152 (minus:QI (const_int 32) (match_dup 2)))))
11153 (clobber (reg:CC 17))]
11156 shld{l}\t{%2, %1, %0|%0, %1, %2}
11157 shld{l}\t{%s2%1, %0|%0, %1, %2}"
11158 [(set_attr "type" "ishift")
11159 (set_attr "prefix_0f" "1")
11160 (set_attr "mode" "SI")
11161 (set_attr "pent_pair" "np")
11162 (set_attr "athlon_decode" "vector")
11163 (set_attr "ppro_uops" "few")])
11165 (define_expand "x86_shift_adj_1"
11167 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
11170 (set (match_operand:SI 0 "register_operand" "")
11171 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11172 (match_operand:SI 1 "register_operand" "")
11175 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11176 (match_operand:SI 3 "register_operand" "r")
11181 (define_expand "x86_shift_adj_2"
11182 [(use (match_operand:SI 0 "register_operand" ""))
11183 (use (match_operand:SI 1 "register_operand" ""))
11184 (use (match_operand:QI 2 "register_operand" ""))]
11187 rtx label = gen_label_rtx ();
11190 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11192 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11193 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11194 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11195 gen_rtx_LABEL_REF (VOIDmode, label),
11197 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11198 JUMP_LABEL (tmp) = label;
11200 emit_move_insn (operands[0], operands[1]);
11201 emit_move_insn (operands[1], const0_rtx);
11203 emit_label (label);
11204 LABEL_NUSES (label) = 1;
11209 (define_expand "ashlsi3"
11210 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11211 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
11212 (match_operand:QI 2 "nonmemory_operand" "")))
11213 (clobber (reg:CC 17))]
11215 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
11217 (define_insn "*ashlsi3_1"
11218 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
11219 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
11220 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11221 (clobber (reg:CC 17))]
11222 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11224 switch (get_attr_type (insn))
11227 if (operands[2] != const1_rtx)
11229 if (!rtx_equal_p (operands[0], operands[1]))
11231 return "add{l}\t{%0, %0|%0, %0}";
11237 if (REG_P (operands[2]))
11238 return "sal{l}\t{%b2, %0|%0, %b2}";
11239 else if (GET_CODE (operands[2]) == CONST_INT
11240 && INTVAL (operands[2]) == 1
11241 && (TARGET_SHIFT1 || optimize_size))
11242 return "sal{l}\t%0";
11244 return "sal{l}\t{%2, %0|%0, %2}";
11247 [(set (attr "type")
11248 (cond [(eq_attr "alternative" "1")
11249 (const_string "lea")
11250 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11252 (match_operand 0 "register_operand" ""))
11253 (match_operand 2 "const1_operand" ""))
11254 (const_string "alu")
11256 (const_string "ishift")))
11257 (set_attr "mode" "SI")])
11259 ;; Convert lea to the lea pattern to avoid flags dependency.
11261 [(set (match_operand 0 "register_operand" "")
11262 (ashift (match_operand 1 "index_register_operand" "")
11263 (match_operand:QI 2 "const_int_operand" "")))
11264 (clobber (reg:CC 17))]
11266 && true_regnum (operands[0]) != true_regnum (operands[1])"
11270 operands[0] = gen_lowpart (SImode, operands[0]);
11271 operands[1] = gen_lowpart (Pmode, operands[1]);
11272 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11273 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
11274 if (Pmode != SImode)
11275 pat = gen_rtx_SUBREG (SImode, pat, 0);
11276 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11280 ;; Rare case of shifting RSP is handled by generating move and shift
11282 [(set (match_operand 0 "register_operand" "")
11283 (ashift (match_operand 1 "register_operand" "")
11284 (match_operand:QI 2 "const_int_operand" "")))
11285 (clobber (reg:CC 17))]
11287 && true_regnum (operands[0]) != true_regnum (operands[1])"
11291 emit_move_insn (operands[1], operands[0]);
11292 pat = gen_rtx_SET (VOIDmode, operands[0],
11293 gen_rtx_ASHIFT (GET_MODE (operands[0]),
11294 operands[0], operands[2]));
11295 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11296 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
11300 (define_insn "*ashlsi3_1_zext"
11301 [(set (match_operand:DI 0 "register_operand" "=r,r")
11302 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
11303 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
11304 (clobber (reg:CC 17))]
11305 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11307 switch (get_attr_type (insn))
11310 if (operands[2] != const1_rtx)
11312 return "add{l}\t{%k0, %k0|%k0, %k0}";
11318 if (REG_P (operands[2]))
11319 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11320 else if (GET_CODE (operands[2]) == CONST_INT
11321 && INTVAL (operands[2]) == 1
11322 && (TARGET_SHIFT1 || optimize_size))
11323 return "sal{l}\t%k0";
11325 return "sal{l}\t{%2, %k0|%k0, %2}";
11328 [(set (attr "type")
11329 (cond [(eq_attr "alternative" "1")
11330 (const_string "lea")
11331 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11333 (match_operand 2 "const1_operand" ""))
11334 (const_string "alu")
11336 (const_string "ishift")))
11337 (set_attr "mode" "SI")])
11339 ;; Convert lea to the lea pattern to avoid flags dependency.
11341 [(set (match_operand:DI 0 "register_operand" "")
11342 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
11343 (match_operand:QI 2 "const_int_operand" ""))))
11344 (clobber (reg:CC 17))]
11345 "TARGET_64BIT && reload_completed
11346 && true_regnum (operands[0]) != true_regnum (operands[1])"
11347 [(set (match_dup 0) (zero_extend:DI
11348 (subreg:SI (mult:SI (match_dup 1)
11349 (match_dup 2)) 0)))]
11351 operands[1] = gen_lowpart (Pmode, operands[1]);
11352 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11355 ;; This pattern can't accept a variable shift count, since shifts by
11356 ;; zero don't affect the flags. We assume that shifts by constant
11357 ;; zero are optimized away.
11358 (define_insn "*ashlsi3_cmp"
11361 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11362 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11364 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11365 (ashift:SI (match_dup 1) (match_dup 2)))]
11366 "ix86_match_ccmode (insn, CCGOCmode)
11367 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11369 switch (get_attr_type (insn))
11372 if (operands[2] != const1_rtx)
11374 return "add{l}\t{%0, %0|%0, %0}";
11377 if (REG_P (operands[2]))
11378 return "sal{l}\t{%b2, %0|%0, %b2}";
11379 else if (GET_CODE (operands[2]) == CONST_INT
11380 && INTVAL (operands[2]) == 1
11381 && (TARGET_SHIFT1 || optimize_size))
11382 return "sal{l}\t%0";
11384 return "sal{l}\t{%2, %0|%0, %2}";
11387 [(set (attr "type")
11388 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11390 (match_operand 0 "register_operand" ""))
11391 (match_operand 2 "const1_operand" ""))
11392 (const_string "alu")
11394 (const_string "ishift")))
11395 (set_attr "mode" "SI")])
11397 (define_insn "*ashlsi3_cmp_zext"
11400 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11401 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11403 (set (match_operand:DI 0 "register_operand" "=r")
11404 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11405 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11406 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11408 switch (get_attr_type (insn))
11411 if (operands[2] != const1_rtx)
11413 return "add{l}\t{%k0, %k0|%k0, %k0}";
11416 if (REG_P (operands[2]))
11417 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11418 else if (GET_CODE (operands[2]) == CONST_INT
11419 && INTVAL (operands[2]) == 1
11420 && (TARGET_SHIFT1 || optimize_size))
11421 return "sal{l}\t%k0";
11423 return "sal{l}\t{%2, %k0|%k0, %2}";
11426 [(set (attr "type")
11427 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11429 (match_operand 2 "const1_operand" ""))
11430 (const_string "alu")
11432 (const_string "ishift")))
11433 (set_attr "mode" "SI")])
11435 (define_expand "ashlhi3"
11436 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11437 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11438 (match_operand:QI 2 "nonmemory_operand" "")))
11439 (clobber (reg:CC 17))]
11440 "TARGET_HIMODE_MATH"
11441 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11443 (define_insn "*ashlhi3_1_lea"
11444 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11445 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11446 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11447 (clobber (reg:CC 17))]
11448 "!TARGET_PARTIAL_REG_STALL
11449 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11451 switch (get_attr_type (insn))
11456 if (operands[2] != const1_rtx)
11458 return "add{w}\t{%0, %0|%0, %0}";
11461 if (REG_P (operands[2]))
11462 return "sal{w}\t{%b2, %0|%0, %b2}";
11463 else if (GET_CODE (operands[2]) == CONST_INT
11464 && INTVAL (operands[2]) == 1
11465 && (TARGET_SHIFT1 || optimize_size))
11466 return "sal{w}\t%0";
11468 return "sal{w}\t{%2, %0|%0, %2}";
11471 [(set (attr "type")
11472 (cond [(eq_attr "alternative" "1")
11473 (const_string "lea")
11474 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11476 (match_operand 0 "register_operand" ""))
11477 (match_operand 2 "const1_operand" ""))
11478 (const_string "alu")
11480 (const_string "ishift")))
11481 (set_attr "mode" "HI,SI")])
11483 (define_insn "*ashlhi3_1"
11484 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11485 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11486 (match_operand:QI 2 "nonmemory_operand" "cI")))
11487 (clobber (reg:CC 17))]
11488 "TARGET_PARTIAL_REG_STALL
11489 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11491 switch (get_attr_type (insn))
11494 if (operands[2] != const1_rtx)
11496 return "add{w}\t{%0, %0|%0, %0}";
11499 if (REG_P (operands[2]))
11500 return "sal{w}\t{%b2, %0|%0, %b2}";
11501 else if (GET_CODE (operands[2]) == CONST_INT
11502 && INTVAL (operands[2]) == 1
11503 && (TARGET_SHIFT1 || optimize_size))
11504 return "sal{w}\t%0";
11506 return "sal{w}\t{%2, %0|%0, %2}";
11509 [(set (attr "type")
11510 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11512 (match_operand 0 "register_operand" ""))
11513 (match_operand 2 "const1_operand" ""))
11514 (const_string "alu")
11516 (const_string "ishift")))
11517 (set_attr "mode" "HI")])
11519 ;; This pattern can't accept a variable shift count, since shifts by
11520 ;; zero don't affect the flags. We assume that shifts by constant
11521 ;; zero are optimized away.
11522 (define_insn "*ashlhi3_cmp"
11525 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11526 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11528 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11529 (ashift:HI (match_dup 1) (match_dup 2)))]
11530 "ix86_match_ccmode (insn, CCGOCmode)
11531 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11533 switch (get_attr_type (insn))
11536 if (operands[2] != const1_rtx)
11538 return "add{w}\t{%0, %0|%0, %0}";
11541 if (REG_P (operands[2]))
11542 return "sal{w}\t{%b2, %0|%0, %b2}";
11543 else if (GET_CODE (operands[2]) == CONST_INT
11544 && INTVAL (operands[2]) == 1
11545 && (TARGET_SHIFT1 || optimize_size))
11546 return "sal{w}\t%0";
11548 return "sal{w}\t{%2, %0|%0, %2}";
11551 [(set (attr "type")
11552 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11554 (match_operand 0 "register_operand" ""))
11555 (match_operand 2 "const1_operand" ""))
11556 (const_string "alu")
11558 (const_string "ishift")))
11559 (set_attr "mode" "HI")])
11561 (define_expand "ashlqi3"
11562 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11563 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11564 (match_operand:QI 2 "nonmemory_operand" "")))
11565 (clobber (reg:CC 17))]
11566 "TARGET_QIMODE_MATH"
11567 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11569 ;; %%% Potential partial reg stall on alternative 2. What to do?
11571 (define_insn "*ashlqi3_1_lea"
11572 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11573 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11574 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11575 (clobber (reg:CC 17))]
11576 "!TARGET_PARTIAL_REG_STALL
11577 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11579 switch (get_attr_type (insn))
11584 if (operands[2] != const1_rtx)
11586 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11587 return "add{l}\t{%k0, %k0|%k0, %k0}";
11589 return "add{b}\t{%0, %0|%0, %0}";
11592 if (REG_P (operands[2]))
11594 if (get_attr_mode (insn) == MODE_SI)
11595 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11597 return "sal{b}\t{%b2, %0|%0, %b2}";
11599 else if (GET_CODE (operands[2]) == CONST_INT
11600 && INTVAL (operands[2]) == 1
11601 && (TARGET_SHIFT1 || optimize_size))
11603 if (get_attr_mode (insn) == MODE_SI)
11604 return "sal{l}\t%0";
11606 return "sal{b}\t%0";
11610 if (get_attr_mode (insn) == MODE_SI)
11611 return "sal{l}\t{%2, %k0|%k0, %2}";
11613 return "sal{b}\t{%2, %0|%0, %2}";
11617 [(set (attr "type")
11618 (cond [(eq_attr "alternative" "2")
11619 (const_string "lea")
11620 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11622 (match_operand 0 "register_operand" ""))
11623 (match_operand 2 "const1_operand" ""))
11624 (const_string "alu")
11626 (const_string "ishift")))
11627 (set_attr "mode" "QI,SI,SI")])
11629 (define_insn "*ashlqi3_1"
11630 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11631 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11632 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11633 (clobber (reg:CC 17))]
11634 "TARGET_PARTIAL_REG_STALL
11635 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11637 switch (get_attr_type (insn))
11640 if (operands[2] != const1_rtx)
11642 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11643 return "add{l}\t{%k0, %k0|%k0, %k0}";
11645 return "add{b}\t{%0, %0|%0, %0}";
11648 if (REG_P (operands[2]))
11650 if (get_attr_mode (insn) == MODE_SI)
11651 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11653 return "sal{b}\t{%b2, %0|%0, %b2}";
11655 else if (GET_CODE (operands[2]) == CONST_INT
11656 && INTVAL (operands[2]) == 1
11657 && (TARGET_SHIFT1 || optimize_size))
11659 if (get_attr_mode (insn) == MODE_SI)
11660 return "sal{l}\t%0";
11662 return "sal{b}\t%0";
11666 if (get_attr_mode (insn) == MODE_SI)
11667 return "sal{l}\t{%2, %k0|%k0, %2}";
11669 return "sal{b}\t{%2, %0|%0, %2}";
11673 [(set (attr "type")
11674 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11676 (match_operand 0 "register_operand" ""))
11677 (match_operand 2 "const1_operand" ""))
11678 (const_string "alu")
11680 (const_string "ishift")))
11681 (set_attr "mode" "QI,SI")])
11683 ;; This pattern can't accept a variable shift count, since shifts by
11684 ;; zero don't affect the flags. We assume that shifts by constant
11685 ;; zero are optimized away.
11686 (define_insn "*ashlqi3_cmp"
11689 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11690 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11692 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11693 (ashift:QI (match_dup 1) (match_dup 2)))]
11694 "ix86_match_ccmode (insn, CCGOCmode)
11695 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11697 switch (get_attr_type (insn))
11700 if (operands[2] != const1_rtx)
11702 return "add{b}\t{%0, %0|%0, %0}";
11705 if (REG_P (operands[2]))
11706 return "sal{b}\t{%b2, %0|%0, %b2}";
11707 else if (GET_CODE (operands[2]) == CONST_INT
11708 && INTVAL (operands[2]) == 1
11709 && (TARGET_SHIFT1 || optimize_size))
11710 return "sal{b}\t%0";
11712 return "sal{b}\t{%2, %0|%0, %2}";
11715 [(set (attr "type")
11716 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11718 (match_operand 0 "register_operand" ""))
11719 (match_operand 2 "const1_operand" ""))
11720 (const_string "alu")
11722 (const_string "ishift")))
11723 (set_attr "mode" "QI")])
11725 ;; See comment above `ashldi3' about how this works.
11727 (define_expand "ashrdi3"
11728 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11729 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11730 (match_operand:QI 2 "nonmemory_operand" "")))
11731 (clobber (reg:CC 17))])]
11734 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11736 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11739 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11743 (define_insn "ashrdi3_63_rex64"
11744 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11745 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11746 (match_operand:DI 2 "const_int_operand" "i,i")))
11747 (clobber (reg:CC 17))]
11748 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11749 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11752 sar{q}\t{%2, %0|%0, %2}"
11753 [(set_attr "type" "imovx,ishift")
11754 (set_attr "prefix_0f" "0,*")
11755 (set_attr "length_immediate" "0,*")
11756 (set_attr "modrm" "0,1")
11757 (set_attr "mode" "DI")])
11759 (define_insn "*ashrdi3_1_one_bit_rex64"
11760 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11761 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11762 (match_operand:QI 2 "const_int_1_operand" "")))
11763 (clobber (reg:CC 17))]
11764 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11765 && (TARGET_SHIFT1 || optimize_size)"
11767 [(set_attr "type" "ishift")
11768 (set (attr "length")
11769 (if_then_else (match_operand:DI 0 "register_operand" "")
11771 (const_string "*")))])
11773 (define_insn "*ashrdi3_1_rex64"
11774 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11775 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11776 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11777 (clobber (reg:CC 17))]
11778 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11780 sar{q}\t{%2, %0|%0, %2}
11781 sar{q}\t{%b2, %0|%0, %b2}"
11782 [(set_attr "type" "ishift")
11783 (set_attr "mode" "DI")])
11785 ;; This pattern can't accept a variable shift count, since shifts by
11786 ;; zero don't affect the flags. We assume that shifts by constant
11787 ;; zero are optimized away.
11788 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11791 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11792 (match_operand:QI 2 "const_int_1_operand" ""))
11794 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11795 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11796 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11797 && (TARGET_SHIFT1 || optimize_size)
11798 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11800 [(set_attr "type" "ishift")
11801 (set (attr "length")
11802 (if_then_else (match_operand:DI 0 "register_operand" "")
11804 (const_string "*")))])
11806 ;; This pattern can't accept a variable shift count, since shifts by
11807 ;; zero don't affect the flags. We assume that shifts by constant
11808 ;; zero are optimized away.
11809 (define_insn "*ashrdi3_cmp_rex64"
11812 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11813 (match_operand:QI 2 "const_int_operand" "n"))
11815 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11816 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11817 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11818 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11819 "sar{q}\t{%2, %0|%0, %2}"
11820 [(set_attr "type" "ishift")
11821 (set_attr "mode" "DI")])
11824 (define_insn "ashrdi3_1"
11825 [(set (match_operand:DI 0 "register_operand" "=r")
11826 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11827 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11828 (clobber (match_scratch:SI 3 "=&r"))
11829 (clobber (reg:CC 17))]
11830 "!TARGET_64BIT && TARGET_CMOVE"
11832 [(set_attr "type" "multi")])
11834 (define_insn "*ashrdi3_2"
11835 [(set (match_operand:DI 0 "register_operand" "=r")
11836 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11837 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11838 (clobber (reg:CC 17))]
11841 [(set_attr "type" "multi")])
11844 [(set (match_operand:DI 0 "register_operand" "")
11845 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11846 (match_operand:QI 2 "nonmemory_operand" "")))
11847 (clobber (match_scratch:SI 3 ""))
11848 (clobber (reg:CC 17))]
11849 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11851 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11854 [(set (match_operand:DI 0 "register_operand" "")
11855 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11856 (match_operand:QI 2 "nonmemory_operand" "")))
11857 (clobber (reg:CC 17))]
11858 "!TARGET_64BIT && reload_completed"
11860 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11862 (define_insn "x86_shrd_1"
11863 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11864 (ior:SI (ashiftrt:SI (match_dup 0)
11865 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11866 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11867 (minus:QI (const_int 32) (match_dup 2)))))
11868 (clobber (reg:CC 17))]
11871 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11872 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11873 [(set_attr "type" "ishift")
11874 (set_attr "prefix_0f" "1")
11875 (set_attr "pent_pair" "np")
11876 (set_attr "ppro_uops" "few")
11877 (set_attr "mode" "SI")])
11879 (define_expand "x86_shift_adj_3"
11880 [(use (match_operand:SI 0 "register_operand" ""))
11881 (use (match_operand:SI 1 "register_operand" ""))
11882 (use (match_operand:QI 2 "register_operand" ""))]
11885 rtx label = gen_label_rtx ();
11888 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11890 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11891 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11892 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11893 gen_rtx_LABEL_REF (VOIDmode, label),
11895 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11896 JUMP_LABEL (tmp) = label;
11898 emit_move_insn (operands[0], operands[1]);
11899 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11901 emit_label (label);
11902 LABEL_NUSES (label) = 1;
11907 (define_insn "ashrsi3_31"
11908 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11909 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11910 (match_operand:SI 2 "const_int_operand" "i,i")))
11911 (clobber (reg:CC 17))]
11912 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11913 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11916 sar{l}\t{%2, %0|%0, %2}"
11917 [(set_attr "type" "imovx,ishift")
11918 (set_attr "prefix_0f" "0,*")
11919 (set_attr "length_immediate" "0,*")
11920 (set_attr "modrm" "0,1")
11921 (set_attr "mode" "SI")])
11923 (define_insn "*ashrsi3_31_zext"
11924 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11925 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11926 (match_operand:SI 2 "const_int_operand" "i,i"))))
11927 (clobber (reg:CC 17))]
11928 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11929 && INTVAL (operands[2]) == 31
11930 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11933 sar{l}\t{%2, %k0|%k0, %2}"
11934 [(set_attr "type" "imovx,ishift")
11935 (set_attr "prefix_0f" "0,*")
11936 (set_attr "length_immediate" "0,*")
11937 (set_attr "modrm" "0,1")
11938 (set_attr "mode" "SI")])
11940 (define_expand "ashrsi3"
11941 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11942 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11943 (match_operand:QI 2 "nonmemory_operand" "")))
11944 (clobber (reg:CC 17))]
11946 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11948 (define_insn "*ashrsi3_1_one_bit"
11949 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11950 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11951 (match_operand:QI 2 "const_int_1_operand" "")))
11952 (clobber (reg:CC 17))]
11953 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11954 && (TARGET_SHIFT1 || optimize_size)"
11956 [(set_attr "type" "ishift")
11957 (set (attr "length")
11958 (if_then_else (match_operand:SI 0 "register_operand" "")
11960 (const_string "*")))])
11962 (define_insn "*ashrsi3_1_one_bit_zext"
11963 [(set (match_operand:DI 0 "register_operand" "=r")
11964 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11965 (match_operand:QI 2 "const_int_1_operand" ""))))
11966 (clobber (reg:CC 17))]
11967 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11968 && (TARGET_SHIFT1 || optimize_size)"
11970 [(set_attr "type" "ishift")
11971 (set_attr "length" "2")])
11973 (define_insn "*ashrsi3_1"
11974 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11975 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11976 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11977 (clobber (reg:CC 17))]
11978 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11980 sar{l}\t{%2, %0|%0, %2}
11981 sar{l}\t{%b2, %0|%0, %b2}"
11982 [(set_attr "type" "ishift")
11983 (set_attr "mode" "SI")])
11985 (define_insn "*ashrsi3_1_zext"
11986 [(set (match_operand:DI 0 "register_operand" "=r,r")
11987 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11988 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11989 (clobber (reg:CC 17))]
11990 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11992 sar{l}\t{%2, %k0|%k0, %2}
11993 sar{l}\t{%b2, %k0|%k0, %b2}"
11994 [(set_attr "type" "ishift")
11995 (set_attr "mode" "SI")])
11997 ;; This pattern can't accept a variable shift count, since shifts by
11998 ;; zero don't affect the flags. We assume that shifts by constant
11999 ;; zero are optimized away.
12000 (define_insn "*ashrsi3_one_bit_cmp"
12003 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12004 (match_operand:QI 2 "const_int_1_operand" ""))
12006 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12007 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12008 "ix86_match_ccmode (insn, CCGOCmode)
12009 && (TARGET_SHIFT1 || optimize_size)
12010 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12012 [(set_attr "type" "ishift")
12013 (set (attr "length")
12014 (if_then_else (match_operand:SI 0 "register_operand" "")
12016 (const_string "*")))])
12018 (define_insn "*ashrsi3_one_bit_cmp_zext"
12021 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12022 (match_operand:QI 2 "const_int_1_operand" ""))
12024 (set (match_operand:DI 0 "register_operand" "=r")
12025 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12026 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
12027 && (TARGET_SHIFT1 || optimize_size)
12028 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12030 [(set_attr "type" "ishift")
12031 (set_attr "length" "2")])
12033 ;; This pattern can't accept a variable shift count, since shifts by
12034 ;; zero don't affect the flags. We assume that shifts by constant
12035 ;; zero are optimized away.
12036 (define_insn "*ashrsi3_cmp"
12039 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12040 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12042 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12043 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12044 "ix86_match_ccmode (insn, CCGOCmode)
12045 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12046 "sar{l}\t{%2, %0|%0, %2}"
12047 [(set_attr "type" "ishift")
12048 (set_attr "mode" "SI")])
12050 (define_insn "*ashrsi3_cmp_zext"
12053 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12054 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12056 (set (match_operand:DI 0 "register_operand" "=r")
12057 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12058 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12059 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12060 "sar{l}\t{%2, %k0|%k0, %2}"
12061 [(set_attr "type" "ishift")
12062 (set_attr "mode" "SI")])
12064 (define_expand "ashrhi3"
12065 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12066 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12067 (match_operand:QI 2 "nonmemory_operand" "")))
12068 (clobber (reg:CC 17))]
12069 "TARGET_HIMODE_MATH"
12070 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
12072 (define_insn "*ashrhi3_1_one_bit"
12073 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12074 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12075 (match_operand:QI 2 "const_int_1_operand" "")))
12076 (clobber (reg:CC 17))]
12077 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
12078 && (TARGET_SHIFT1 || optimize_size)"
12080 [(set_attr "type" "ishift")
12081 (set (attr "length")
12082 (if_then_else (match_operand 0 "register_operand" "")
12084 (const_string "*")))])
12086 (define_insn "*ashrhi3_1"
12087 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12088 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12089 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12090 (clobber (reg:CC 17))]
12091 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12093 sar{w}\t{%2, %0|%0, %2}
12094 sar{w}\t{%b2, %0|%0, %b2}"
12095 [(set_attr "type" "ishift")
12096 (set_attr "mode" "HI")])
12098 ;; This pattern can't accept a variable shift count, since shifts by
12099 ;; zero don't affect the flags. We assume that shifts by constant
12100 ;; zero are optimized away.
12101 (define_insn "*ashrhi3_one_bit_cmp"
12104 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12105 (match_operand:QI 2 "const_int_1_operand" ""))
12107 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12108 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12109 "ix86_match_ccmode (insn, CCGOCmode)
12110 && (TARGET_SHIFT1 || optimize_size)
12111 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12113 [(set_attr "type" "ishift")
12114 (set (attr "length")
12115 (if_then_else (match_operand 0 "register_operand" "")
12117 (const_string "*")))])
12119 ;; This pattern can't accept a variable shift count, since shifts by
12120 ;; zero don't affect the flags. We assume that shifts by constant
12121 ;; zero are optimized away.
12122 (define_insn "*ashrhi3_cmp"
12125 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12126 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12128 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12129 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12130 "ix86_match_ccmode (insn, CCGOCmode)
12131 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12132 "sar{w}\t{%2, %0|%0, %2}"
12133 [(set_attr "type" "ishift")
12134 (set_attr "mode" "HI")])
12136 (define_expand "ashrqi3"
12137 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12138 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12139 (match_operand:QI 2 "nonmemory_operand" "")))
12140 (clobber (reg:CC 17))]
12141 "TARGET_QIMODE_MATH"
12142 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
12144 (define_insn "*ashrqi3_1_one_bit"
12145 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12146 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12147 (match_operand:QI 2 "const_int_1_operand" "")))
12148 (clobber (reg:CC 17))]
12149 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12150 && (TARGET_SHIFT1 || optimize_size)"
12152 [(set_attr "type" "ishift")
12153 (set (attr "length")
12154 (if_then_else (match_operand 0 "register_operand" "")
12156 (const_string "*")))])
12158 (define_insn "*ashrqi3_1_one_bit_slp"
12159 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12160 (ashiftrt:QI (match_dup 0)
12161 (match_operand:QI 1 "const_int_1_operand" "")))
12162 (clobber (reg:CC 17))]
12163 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12164 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
12165 && (TARGET_SHIFT1 || optimize_size)"
12167 [(set_attr "type" "ishift1")
12168 (set (attr "length")
12169 (if_then_else (match_operand 0 "register_operand" "")
12171 (const_string "*")))])
12173 (define_insn "*ashrqi3_1"
12174 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12175 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12176 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12177 (clobber (reg:CC 17))]
12178 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12180 sar{b}\t{%2, %0|%0, %2}
12181 sar{b}\t{%b2, %0|%0, %b2}"
12182 [(set_attr "type" "ishift")
12183 (set_attr "mode" "QI")])
12185 (define_insn "*ashrqi3_1_slp"
12186 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12187 (ashiftrt:QI (match_dup 0)
12188 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12189 (clobber (reg:CC 17))]
12190 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12191 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12193 sar{b}\t{%1, %0|%0, %1}
12194 sar{b}\t{%b1, %0|%0, %b1}"
12195 [(set_attr "type" "ishift1")
12196 (set_attr "mode" "QI")])
12198 ;; This pattern can't accept a variable shift count, since shifts by
12199 ;; zero don't affect the flags. We assume that shifts by constant
12200 ;; zero are optimized away.
12201 (define_insn "*ashrqi3_one_bit_cmp"
12204 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12205 (match_operand:QI 2 "const_int_1_operand" "I"))
12207 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12208 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12209 "ix86_match_ccmode (insn, CCGOCmode)
12210 && (TARGET_SHIFT1 || optimize_size)
12211 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12213 [(set_attr "type" "ishift")
12214 (set (attr "length")
12215 (if_then_else (match_operand 0 "register_operand" "")
12217 (const_string "*")))])
12219 ;; This pattern can't accept a variable shift count, since shifts by
12220 ;; zero don't affect the flags. We assume that shifts by constant
12221 ;; zero are optimized away.
12222 (define_insn "*ashrqi3_cmp"
12225 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12226 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12228 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12229 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12230 "ix86_match_ccmode (insn, CCGOCmode)
12231 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12232 "sar{b}\t{%2, %0|%0, %2}"
12233 [(set_attr "type" "ishift")
12234 (set_attr "mode" "QI")])
12236 ;; Logical shift instructions
12238 ;; See comment above `ashldi3' about how this works.
12240 (define_expand "lshrdi3"
12241 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
12242 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
12243 (match_operand:QI 2 "nonmemory_operand" "")))
12244 (clobber (reg:CC 17))])]
12247 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
12249 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
12252 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
12256 (define_insn "*lshrdi3_1_one_bit_rex64"
12257 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12258 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12259 (match_operand:QI 2 "const_int_1_operand" "")))
12260 (clobber (reg:CC 17))]
12261 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12262 && (TARGET_SHIFT1 || optimize_size)"
12264 [(set_attr "type" "ishift")
12265 (set (attr "length")
12266 (if_then_else (match_operand:DI 0 "register_operand" "")
12268 (const_string "*")))])
12270 (define_insn "*lshrdi3_1_rex64"
12271 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12272 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12273 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12274 (clobber (reg:CC 17))]
12275 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12277 shr{q}\t{%2, %0|%0, %2}
12278 shr{q}\t{%b2, %0|%0, %b2}"
12279 [(set_attr "type" "ishift")
12280 (set_attr "mode" "DI")])
12282 ;; This pattern can't accept a variable shift count, since shifts by
12283 ;; zero don't affect the flags. We assume that shifts by constant
12284 ;; zero are optimized away.
12285 (define_insn "*lshrdi3_cmp_one_bit_rex64"
12288 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12289 (match_operand:QI 2 "const_int_1_operand" ""))
12291 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12292 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12293 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12294 && (TARGET_SHIFT1 || optimize_size)
12295 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12297 [(set_attr "type" "ishift")
12298 (set (attr "length")
12299 (if_then_else (match_operand:DI 0 "register_operand" "")
12301 (const_string "*")))])
12303 ;; This pattern can't accept a variable shift count, since shifts by
12304 ;; zero don't affect the flags. We assume that shifts by constant
12305 ;; zero are optimized away.
12306 (define_insn "*lshrdi3_cmp_rex64"
12309 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12310 (match_operand:QI 2 "const_int_operand" "e"))
12312 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12313 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12314 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12315 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12316 "shr{q}\t{%2, %0|%0, %2}"
12317 [(set_attr "type" "ishift")
12318 (set_attr "mode" "DI")])
12320 (define_insn "lshrdi3_1"
12321 [(set (match_operand:DI 0 "register_operand" "=r")
12322 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12323 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12324 (clobber (match_scratch:SI 3 "=&r"))
12325 (clobber (reg:CC 17))]
12326 "!TARGET_64BIT && TARGET_CMOVE"
12328 [(set_attr "type" "multi")])
12330 (define_insn "*lshrdi3_2"
12331 [(set (match_operand:DI 0 "register_operand" "=r")
12332 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12333 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12334 (clobber (reg:CC 17))]
12337 [(set_attr "type" "multi")])
12340 [(set (match_operand:DI 0 "register_operand" "")
12341 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12342 (match_operand:QI 2 "nonmemory_operand" "")))
12343 (clobber (match_scratch:SI 3 ""))
12344 (clobber (reg:CC 17))]
12345 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
12347 "ix86_split_lshrdi (operands, operands[3]); DONE;")
12350 [(set (match_operand:DI 0 "register_operand" "")
12351 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12352 (match_operand:QI 2 "nonmemory_operand" "")))
12353 (clobber (reg:CC 17))]
12354 "!TARGET_64BIT && reload_completed"
12356 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
12358 (define_expand "lshrsi3"
12359 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12360 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12361 (match_operand:QI 2 "nonmemory_operand" "")))
12362 (clobber (reg:CC 17))]
12364 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
12366 (define_insn "*lshrsi3_1_one_bit"
12367 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12368 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12369 (match_operand:QI 2 "const_int_1_operand" "")))
12370 (clobber (reg:CC 17))]
12371 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12372 && (TARGET_SHIFT1 || optimize_size)"
12374 [(set_attr "type" "ishift")
12375 (set (attr "length")
12376 (if_then_else (match_operand:SI 0 "register_operand" "")
12378 (const_string "*")))])
12380 (define_insn "*lshrsi3_1_one_bit_zext"
12381 [(set (match_operand:DI 0 "register_operand" "=r")
12382 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12383 (match_operand:QI 2 "const_int_1_operand" "")))
12384 (clobber (reg:CC 17))]
12385 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12386 && (TARGET_SHIFT1 || optimize_size)"
12388 [(set_attr "type" "ishift")
12389 (set_attr "length" "2")])
12391 (define_insn "*lshrsi3_1"
12392 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12393 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12394 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12395 (clobber (reg:CC 17))]
12396 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12398 shr{l}\t{%2, %0|%0, %2}
12399 shr{l}\t{%b2, %0|%0, %b2}"
12400 [(set_attr "type" "ishift")
12401 (set_attr "mode" "SI")])
12403 (define_insn "*lshrsi3_1_zext"
12404 [(set (match_operand:DI 0 "register_operand" "=r,r")
12406 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12407 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12408 (clobber (reg:CC 17))]
12409 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12411 shr{l}\t{%2, %k0|%k0, %2}
12412 shr{l}\t{%b2, %k0|%k0, %b2}"
12413 [(set_attr "type" "ishift")
12414 (set_attr "mode" "SI")])
12416 ;; This pattern can't accept a variable shift count, since shifts by
12417 ;; zero don't affect the flags. We assume that shifts by constant
12418 ;; zero are optimized away.
12419 (define_insn "*lshrsi3_one_bit_cmp"
12422 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12423 (match_operand:QI 2 "const_int_1_operand" ""))
12425 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12426 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12427 "ix86_match_ccmode (insn, CCGOCmode)
12428 && (TARGET_SHIFT1 || optimize_size)
12429 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12431 [(set_attr "type" "ishift")
12432 (set (attr "length")
12433 (if_then_else (match_operand:SI 0 "register_operand" "")
12435 (const_string "*")))])
12437 (define_insn "*lshrsi3_cmp_one_bit_zext"
12440 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12441 (match_operand:QI 2 "const_int_1_operand" ""))
12443 (set (match_operand:DI 0 "register_operand" "=r")
12444 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12445 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12446 && (TARGET_SHIFT1 || optimize_size)
12447 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12449 [(set_attr "type" "ishift")
12450 (set_attr "length" "2")])
12452 ;; This pattern can't accept a variable shift count, since shifts by
12453 ;; zero don't affect the flags. We assume that shifts by constant
12454 ;; zero are optimized away.
12455 (define_insn "*lshrsi3_cmp"
12458 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12459 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12461 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12462 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12463 "ix86_match_ccmode (insn, CCGOCmode)
12464 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12465 "shr{l}\t{%2, %0|%0, %2}"
12466 [(set_attr "type" "ishift")
12467 (set_attr "mode" "SI")])
12469 (define_insn "*lshrsi3_cmp_zext"
12472 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12473 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12475 (set (match_operand:DI 0 "register_operand" "=r")
12476 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12477 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12478 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12479 "shr{l}\t{%2, %k0|%k0, %2}"
12480 [(set_attr "type" "ishift")
12481 (set_attr "mode" "SI")])
12483 (define_expand "lshrhi3"
12484 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12485 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12486 (match_operand:QI 2 "nonmemory_operand" "")))
12487 (clobber (reg:CC 17))]
12488 "TARGET_HIMODE_MATH"
12489 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12491 (define_insn "*lshrhi3_1_one_bit"
12492 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12493 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12494 (match_operand:QI 2 "const_int_1_operand" "")))
12495 (clobber (reg:CC 17))]
12496 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12497 && (TARGET_SHIFT1 || optimize_size)"
12499 [(set_attr "type" "ishift")
12500 (set (attr "length")
12501 (if_then_else (match_operand 0 "register_operand" "")
12503 (const_string "*")))])
12505 (define_insn "*lshrhi3_1"
12506 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12507 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12508 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12509 (clobber (reg:CC 17))]
12510 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12512 shr{w}\t{%2, %0|%0, %2}
12513 shr{w}\t{%b2, %0|%0, %b2}"
12514 [(set_attr "type" "ishift")
12515 (set_attr "mode" "HI")])
12517 ;; This pattern can't accept a variable shift count, since shifts by
12518 ;; zero don't affect the flags. We assume that shifts by constant
12519 ;; zero are optimized away.
12520 (define_insn "*lshrhi3_one_bit_cmp"
12523 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12524 (match_operand:QI 2 "const_int_1_operand" ""))
12526 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12527 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12528 "ix86_match_ccmode (insn, CCGOCmode)
12529 && (TARGET_SHIFT1 || optimize_size)
12530 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12532 [(set_attr "type" "ishift")
12533 (set (attr "length")
12534 (if_then_else (match_operand:SI 0 "register_operand" "")
12536 (const_string "*")))])
12538 ;; This pattern can't accept a variable shift count, since shifts by
12539 ;; zero don't affect the flags. We assume that shifts by constant
12540 ;; zero are optimized away.
12541 (define_insn "*lshrhi3_cmp"
12544 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12545 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12547 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12548 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12549 "ix86_match_ccmode (insn, CCGOCmode)
12550 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12551 "shr{w}\t{%2, %0|%0, %2}"
12552 [(set_attr "type" "ishift")
12553 (set_attr "mode" "HI")])
12555 (define_expand "lshrqi3"
12556 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12557 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12558 (match_operand:QI 2 "nonmemory_operand" "")))
12559 (clobber (reg:CC 17))]
12560 "TARGET_QIMODE_MATH"
12561 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12563 (define_insn "*lshrqi3_1_one_bit"
12564 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12565 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12566 (match_operand:QI 2 "const_int_1_operand" "")))
12567 (clobber (reg:CC 17))]
12568 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12569 && (TARGET_SHIFT1 || optimize_size)"
12571 [(set_attr "type" "ishift")
12572 (set (attr "length")
12573 (if_then_else (match_operand 0 "register_operand" "")
12575 (const_string "*")))])
12577 (define_insn "*lshrqi3_1_one_bit_slp"
12578 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12579 (lshiftrt:QI (match_dup 0)
12580 (match_operand:QI 1 "const_int_1_operand" "")))
12581 (clobber (reg:CC 17))]
12582 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12583 && (TARGET_SHIFT1 || optimize_size)"
12585 [(set_attr "type" "ishift1")
12586 (set (attr "length")
12587 (if_then_else (match_operand 0 "register_operand" "")
12589 (const_string "*")))])
12591 (define_insn "*lshrqi3_1"
12592 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12593 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12594 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12595 (clobber (reg:CC 17))]
12596 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12598 shr{b}\t{%2, %0|%0, %2}
12599 shr{b}\t{%b2, %0|%0, %b2}"
12600 [(set_attr "type" "ishift")
12601 (set_attr "mode" "QI")])
12603 (define_insn "*lshrqi3_1_slp"
12604 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12605 (lshiftrt:QI (match_dup 0)
12606 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12607 (clobber (reg:CC 17))]
12608 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12609 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12611 shr{b}\t{%1, %0|%0, %1}
12612 shr{b}\t{%b1, %0|%0, %b1}"
12613 [(set_attr "type" "ishift1")
12614 (set_attr "mode" "QI")])
12616 ;; This pattern can't accept a variable shift count, since shifts by
12617 ;; zero don't affect the flags. We assume that shifts by constant
12618 ;; zero are optimized away.
12619 (define_insn "*lshrqi2_one_bit_cmp"
12622 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12623 (match_operand:QI 2 "const_int_1_operand" ""))
12625 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12626 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12627 "ix86_match_ccmode (insn, CCGOCmode)
12628 && (TARGET_SHIFT1 || optimize_size)
12629 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12631 [(set_attr "type" "ishift")
12632 (set (attr "length")
12633 (if_then_else (match_operand:SI 0 "register_operand" "")
12635 (const_string "*")))])
12637 ;; This pattern can't accept a variable shift count, since shifts by
12638 ;; zero don't affect the flags. We assume that shifts by constant
12639 ;; zero are optimized away.
12640 (define_insn "*lshrqi2_cmp"
12643 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12644 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12646 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12647 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12648 "ix86_match_ccmode (insn, CCGOCmode)
12649 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12650 "shr{b}\t{%2, %0|%0, %2}"
12651 [(set_attr "type" "ishift")
12652 (set_attr "mode" "QI")])
12654 ;; Rotate instructions
12656 (define_expand "rotldi3"
12657 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12658 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12659 (match_operand:QI 2 "nonmemory_operand" "")))
12660 (clobber (reg:CC 17))]
12662 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12664 (define_insn "*rotlsi3_1_one_bit_rex64"
12665 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12666 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12667 (match_operand:QI 2 "const_int_1_operand" "")))
12668 (clobber (reg:CC 17))]
12669 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12670 && (TARGET_SHIFT1 || optimize_size)"
12672 [(set_attr "type" "rotate")
12673 (set (attr "length")
12674 (if_then_else (match_operand:DI 0 "register_operand" "")
12676 (const_string "*")))])
12678 (define_insn "*rotldi3_1_rex64"
12679 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12680 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12681 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12682 (clobber (reg:CC 17))]
12683 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12685 rol{q}\t{%2, %0|%0, %2}
12686 rol{q}\t{%b2, %0|%0, %b2}"
12687 [(set_attr "type" "rotate")
12688 (set_attr "mode" "DI")])
12690 (define_expand "rotlsi3"
12691 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12692 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12693 (match_operand:QI 2 "nonmemory_operand" "")))
12694 (clobber (reg:CC 17))]
12696 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12698 (define_insn "*rotlsi3_1_one_bit"
12699 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12700 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12701 (match_operand:QI 2 "const_int_1_operand" "")))
12702 (clobber (reg:CC 17))]
12703 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12704 && (TARGET_SHIFT1 || optimize_size)"
12706 [(set_attr "type" "rotate")
12707 (set (attr "length")
12708 (if_then_else (match_operand:SI 0 "register_operand" "")
12710 (const_string "*")))])
12712 (define_insn "*rotlsi3_1_one_bit_zext"
12713 [(set (match_operand:DI 0 "register_operand" "=r")
12715 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12716 (match_operand:QI 2 "const_int_1_operand" ""))))
12717 (clobber (reg:CC 17))]
12718 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12719 && (TARGET_SHIFT1 || optimize_size)"
12721 [(set_attr "type" "rotate")
12722 (set_attr "length" "2")])
12724 (define_insn "*rotlsi3_1"
12725 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12726 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12727 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12728 (clobber (reg:CC 17))]
12729 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12731 rol{l}\t{%2, %0|%0, %2}
12732 rol{l}\t{%b2, %0|%0, %b2}"
12733 [(set_attr "type" "rotate")
12734 (set_attr "mode" "SI")])
12736 (define_insn "*rotlsi3_1_zext"
12737 [(set (match_operand:DI 0 "register_operand" "=r,r")
12739 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12740 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12741 (clobber (reg:CC 17))]
12742 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12744 rol{l}\t{%2, %k0|%k0, %2}
12745 rol{l}\t{%b2, %k0|%k0, %b2}"
12746 [(set_attr "type" "rotate")
12747 (set_attr "mode" "SI")])
12749 (define_expand "rotlhi3"
12750 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12751 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12752 (match_operand:QI 2 "nonmemory_operand" "")))
12753 (clobber (reg:CC 17))]
12754 "TARGET_HIMODE_MATH"
12755 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12757 (define_insn "*rotlhi3_1_one_bit"
12758 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12759 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12760 (match_operand:QI 2 "const_int_1_operand" "")))
12761 (clobber (reg:CC 17))]
12762 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12763 && (TARGET_SHIFT1 || optimize_size)"
12765 [(set_attr "type" "rotate")
12766 (set (attr "length")
12767 (if_then_else (match_operand 0 "register_operand" "")
12769 (const_string "*")))])
12771 (define_insn "*rotlhi3_1"
12772 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12773 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12774 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12775 (clobber (reg:CC 17))]
12776 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12778 rol{w}\t{%2, %0|%0, %2}
12779 rol{w}\t{%b2, %0|%0, %b2}"
12780 [(set_attr "type" "rotate")
12781 (set_attr "mode" "HI")])
12783 (define_expand "rotlqi3"
12784 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12785 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12786 (match_operand:QI 2 "nonmemory_operand" "")))
12787 (clobber (reg:CC 17))]
12788 "TARGET_QIMODE_MATH"
12789 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12791 (define_insn "*rotlqi3_1_one_bit_slp"
12792 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12793 (rotate:QI (match_dup 0)
12794 (match_operand:QI 1 "const_int_1_operand" "")))
12795 (clobber (reg:CC 17))]
12796 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12797 && (TARGET_SHIFT1 || optimize_size)"
12799 [(set_attr "type" "rotate1")
12800 (set (attr "length")
12801 (if_then_else (match_operand 0 "register_operand" "")
12803 (const_string "*")))])
12805 (define_insn "*rotlqi3_1_one_bit"
12806 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12807 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12808 (match_operand:QI 2 "const_int_1_operand" "")))
12809 (clobber (reg:CC 17))]
12810 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12811 && (TARGET_SHIFT1 || optimize_size)"
12813 [(set_attr "type" "rotate")
12814 (set (attr "length")
12815 (if_then_else (match_operand 0 "register_operand" "")
12817 (const_string "*")))])
12819 (define_insn "*rotlqi3_1_slp"
12820 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12821 (rotate:QI (match_dup 0)
12822 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12823 (clobber (reg:CC 17))]
12824 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12825 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12827 rol{b}\t{%1, %0|%0, %1}
12828 rol{b}\t{%b1, %0|%0, %b1}"
12829 [(set_attr "type" "rotate1")
12830 (set_attr "mode" "QI")])
12832 (define_insn "*rotlqi3_1"
12833 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12834 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12835 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12836 (clobber (reg:CC 17))]
12837 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12839 rol{b}\t{%2, %0|%0, %2}
12840 rol{b}\t{%b2, %0|%0, %b2}"
12841 [(set_attr "type" "rotate")
12842 (set_attr "mode" "QI")])
12844 (define_expand "rotrdi3"
12845 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12846 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12847 (match_operand:QI 2 "nonmemory_operand" "")))
12848 (clobber (reg:CC 17))]
12850 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12852 (define_insn "*rotrdi3_1_one_bit_rex64"
12853 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12854 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12855 (match_operand:QI 2 "const_int_1_operand" "")))
12856 (clobber (reg:CC 17))]
12857 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12858 && (TARGET_SHIFT1 || optimize_size)"
12860 [(set_attr "type" "rotate")
12861 (set (attr "length")
12862 (if_then_else (match_operand:DI 0 "register_operand" "")
12864 (const_string "*")))])
12866 (define_insn "*rotrdi3_1_rex64"
12867 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12868 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12869 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12870 (clobber (reg:CC 17))]
12871 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12873 ror{q}\t{%2, %0|%0, %2}
12874 ror{q}\t{%b2, %0|%0, %b2}"
12875 [(set_attr "type" "rotate")
12876 (set_attr "mode" "DI")])
12878 (define_expand "rotrsi3"
12879 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12880 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12881 (match_operand:QI 2 "nonmemory_operand" "")))
12882 (clobber (reg:CC 17))]
12884 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12886 (define_insn "*rotrsi3_1_one_bit"
12887 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12888 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12889 (match_operand:QI 2 "const_int_1_operand" "")))
12890 (clobber (reg:CC 17))]
12891 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12892 && (TARGET_SHIFT1 || optimize_size)"
12894 [(set_attr "type" "rotate")
12895 (set (attr "length")
12896 (if_then_else (match_operand:SI 0 "register_operand" "")
12898 (const_string "*")))])
12900 (define_insn "*rotrsi3_1_one_bit_zext"
12901 [(set (match_operand:DI 0 "register_operand" "=r")
12903 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12904 (match_operand:QI 2 "const_int_1_operand" ""))))
12905 (clobber (reg:CC 17))]
12906 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12907 && (TARGET_SHIFT1 || optimize_size)"
12909 [(set_attr "type" "rotate")
12910 (set (attr "length")
12911 (if_then_else (match_operand:SI 0 "register_operand" "")
12913 (const_string "*")))])
12915 (define_insn "*rotrsi3_1"
12916 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12917 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12918 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12919 (clobber (reg:CC 17))]
12920 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12922 ror{l}\t{%2, %0|%0, %2}
12923 ror{l}\t{%b2, %0|%0, %b2}"
12924 [(set_attr "type" "rotate")
12925 (set_attr "mode" "SI")])
12927 (define_insn "*rotrsi3_1_zext"
12928 [(set (match_operand:DI 0 "register_operand" "=r,r")
12930 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12931 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12932 (clobber (reg:CC 17))]
12933 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12935 ror{l}\t{%2, %k0|%k0, %2}
12936 ror{l}\t{%b2, %k0|%k0, %b2}"
12937 [(set_attr "type" "rotate")
12938 (set_attr "mode" "SI")])
12940 (define_expand "rotrhi3"
12941 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12942 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12943 (match_operand:QI 2 "nonmemory_operand" "")))
12944 (clobber (reg:CC 17))]
12945 "TARGET_HIMODE_MATH"
12946 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12948 (define_insn "*rotrhi3_one_bit"
12949 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12950 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12951 (match_operand:QI 2 "const_int_1_operand" "")))
12952 (clobber (reg:CC 17))]
12953 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12954 && (TARGET_SHIFT1 || optimize_size)"
12956 [(set_attr "type" "rotate")
12957 (set (attr "length")
12958 (if_then_else (match_operand 0 "register_operand" "")
12960 (const_string "*")))])
12962 (define_insn "*rotrhi3"
12963 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12964 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12965 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12966 (clobber (reg:CC 17))]
12967 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12969 ror{w}\t{%2, %0|%0, %2}
12970 ror{w}\t{%b2, %0|%0, %b2}"
12971 [(set_attr "type" "rotate")
12972 (set_attr "mode" "HI")])
12974 (define_expand "rotrqi3"
12975 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12976 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12977 (match_operand:QI 2 "nonmemory_operand" "")))
12978 (clobber (reg:CC 17))]
12979 "TARGET_QIMODE_MATH"
12980 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12982 (define_insn "*rotrqi3_1_one_bit"
12983 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12984 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12985 (match_operand:QI 2 "const_int_1_operand" "")))
12986 (clobber (reg:CC 17))]
12987 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12988 && (TARGET_SHIFT1 || optimize_size)"
12990 [(set_attr "type" "rotate")
12991 (set (attr "length")
12992 (if_then_else (match_operand 0 "register_operand" "")
12994 (const_string "*")))])
12996 (define_insn "*rotrqi3_1_one_bit_slp"
12997 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12998 (rotatert:QI (match_dup 0)
12999 (match_operand:QI 1 "const_int_1_operand" "")))
13000 (clobber (reg:CC 17))]
13001 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13002 && (TARGET_SHIFT1 || optimize_size)"
13004 [(set_attr "type" "rotate1")
13005 (set (attr "length")
13006 (if_then_else (match_operand 0 "register_operand" "")
13008 (const_string "*")))])
13010 (define_insn "*rotrqi3_1"
13011 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13012 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13013 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13014 (clobber (reg:CC 17))]
13015 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
13017 ror{b}\t{%2, %0|%0, %2}
13018 ror{b}\t{%b2, %0|%0, %b2}"
13019 [(set_attr "type" "rotate")
13020 (set_attr "mode" "QI")])
13022 (define_insn "*rotrqi3_1_slp"
13023 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13024 (rotatert:QI (match_dup 0)
13025 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13026 (clobber (reg:CC 17))]
13027 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13028 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
13030 ror{b}\t{%1, %0|%0, %1}
13031 ror{b}\t{%b1, %0|%0, %b1}"
13032 [(set_attr "type" "rotate1")
13033 (set_attr "mode" "QI")])
13035 ;; Bit set / bit test instructions
13037 (define_expand "extv"
13038 [(set (match_operand:SI 0 "register_operand" "")
13039 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
13040 (match_operand:SI 2 "immediate_operand" "")
13041 (match_operand:SI 3 "immediate_operand" "")))]
13044 /* Handle extractions from %ah et al. */
13045 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13048 /* From mips.md: extract_bit_field doesn't verify that our source
13049 matches the predicate, so check it again here. */
13050 if (! register_operand (operands[1], VOIDmode))
13054 (define_expand "extzv"
13055 [(set (match_operand:SI 0 "register_operand" "")
13056 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
13057 (match_operand:SI 2 "immediate_operand" "")
13058 (match_operand:SI 3 "immediate_operand" "")))]
13061 /* Handle extractions from %ah et al. */
13062 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13065 /* From mips.md: extract_bit_field doesn't verify that our source
13066 matches the predicate, so check it again here. */
13067 if (! register_operand (operands[1], VOIDmode))
13071 (define_expand "insv"
13072 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
13073 (match_operand:SI 1 "immediate_operand" "")
13074 (match_operand:SI 2 "immediate_operand" ""))
13075 (match_operand:SI 3 "register_operand" ""))]
13078 /* Handle extractions from %ah et al. */
13079 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
13082 /* From mips.md: insert_bit_field doesn't verify that our source
13083 matches the predicate, so check it again here. */
13084 if (! register_operand (operands[0], VOIDmode))
13088 ;; %%% bts, btr, btc, bt.
13090 ;; Store-flag instructions.
13092 ;; For all sCOND expanders, also expand the compare or test insn that
13093 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
13095 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
13096 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
13097 ;; way, which can later delete the movzx if only QImode is needed.
13099 (define_expand "seq"
13100 [(set (match_operand:QI 0 "register_operand" "")
13101 (eq:QI (reg:CC 17) (const_int 0)))]
13103 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
13105 (define_expand "sne"
13106 [(set (match_operand:QI 0 "register_operand" "")
13107 (ne:QI (reg:CC 17) (const_int 0)))]
13109 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
13111 (define_expand "sgt"
13112 [(set (match_operand:QI 0 "register_operand" "")
13113 (gt:QI (reg:CC 17) (const_int 0)))]
13115 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
13117 (define_expand "sgtu"
13118 [(set (match_operand:QI 0 "register_operand" "")
13119 (gtu:QI (reg:CC 17) (const_int 0)))]
13121 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
13123 (define_expand "slt"
13124 [(set (match_operand:QI 0 "register_operand" "")
13125 (lt:QI (reg:CC 17) (const_int 0)))]
13127 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
13129 (define_expand "sltu"
13130 [(set (match_operand:QI 0 "register_operand" "")
13131 (ltu:QI (reg:CC 17) (const_int 0)))]
13133 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
13135 (define_expand "sge"
13136 [(set (match_operand:QI 0 "register_operand" "")
13137 (ge:QI (reg:CC 17) (const_int 0)))]
13139 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
13141 (define_expand "sgeu"
13142 [(set (match_operand:QI 0 "register_operand" "")
13143 (geu:QI (reg:CC 17) (const_int 0)))]
13145 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
13147 (define_expand "sle"
13148 [(set (match_operand:QI 0 "register_operand" "")
13149 (le:QI (reg:CC 17) (const_int 0)))]
13151 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
13153 (define_expand "sleu"
13154 [(set (match_operand:QI 0 "register_operand" "")
13155 (leu:QI (reg:CC 17) (const_int 0)))]
13157 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
13159 (define_expand "sunordered"
13160 [(set (match_operand:QI 0 "register_operand" "")
13161 (unordered:QI (reg:CC 17) (const_int 0)))]
13162 "TARGET_80387 || TARGET_SSE"
13163 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
13165 (define_expand "sordered"
13166 [(set (match_operand:QI 0 "register_operand" "")
13167 (ordered:QI (reg:CC 17) (const_int 0)))]
13169 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
13171 (define_expand "suneq"
13172 [(set (match_operand:QI 0 "register_operand" "")
13173 (uneq:QI (reg:CC 17) (const_int 0)))]
13174 "TARGET_80387 || TARGET_SSE"
13175 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
13177 (define_expand "sunge"
13178 [(set (match_operand:QI 0 "register_operand" "")
13179 (unge:QI (reg:CC 17) (const_int 0)))]
13180 "TARGET_80387 || TARGET_SSE"
13181 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
13183 (define_expand "sungt"
13184 [(set (match_operand:QI 0 "register_operand" "")
13185 (ungt:QI (reg:CC 17) (const_int 0)))]
13186 "TARGET_80387 || TARGET_SSE"
13187 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
13189 (define_expand "sunle"
13190 [(set (match_operand:QI 0 "register_operand" "")
13191 (unle:QI (reg:CC 17) (const_int 0)))]
13192 "TARGET_80387 || TARGET_SSE"
13193 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
13195 (define_expand "sunlt"
13196 [(set (match_operand:QI 0 "register_operand" "")
13197 (unlt:QI (reg:CC 17) (const_int 0)))]
13198 "TARGET_80387 || TARGET_SSE"
13199 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
13201 (define_expand "sltgt"
13202 [(set (match_operand:QI 0 "register_operand" "")
13203 (ltgt:QI (reg:CC 17) (const_int 0)))]
13204 "TARGET_80387 || TARGET_SSE"
13205 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
13207 (define_insn "*setcc_1"
13208 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13209 (match_operator:QI 1 "ix86_comparison_operator"
13210 [(reg 17) (const_int 0)]))]
13213 [(set_attr "type" "setcc")
13214 (set_attr "mode" "QI")])
13216 (define_insn "setcc_2"
13217 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13218 (match_operator:QI 1 "ix86_comparison_operator"
13219 [(reg 17) (const_int 0)]))]
13222 [(set_attr "type" "setcc")
13223 (set_attr "mode" "QI")])
13225 ;; In general it is not safe to assume too much about CCmode registers,
13226 ;; so simplify-rtx stops when it sees a second one. Under certain
13227 ;; conditions this is safe on x86, so help combine not create
13234 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13235 (ne:QI (match_operator 1 "ix86_comparison_operator"
13236 [(reg 17) (const_int 0)])
13239 [(set (match_dup 0) (match_dup 1))]
13241 PUT_MODE (operands[1], QImode);
13245 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13246 (ne:QI (match_operator 1 "ix86_comparison_operator"
13247 [(reg 17) (const_int 0)])
13250 [(set (match_dup 0) (match_dup 1))]
13252 PUT_MODE (operands[1], QImode);
13256 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13257 (eq:QI (match_operator 1 "ix86_comparison_operator"
13258 [(reg 17) (const_int 0)])
13261 [(set (match_dup 0) (match_dup 1))]
13263 rtx new_op1 = copy_rtx (operands[1]);
13264 operands[1] = new_op1;
13265 PUT_MODE (new_op1, QImode);
13266 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13267 GET_MODE (XEXP (new_op1, 0))));
13269 /* Make sure that (a) the CCmode we have for the flags is strong
13270 enough for the reversed compare or (b) we have a valid FP compare. */
13271 if (! ix86_comparison_operator (new_op1, VOIDmode))
13276 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13277 (eq:QI (match_operator 1 "ix86_comparison_operator"
13278 [(reg 17) (const_int 0)])
13281 [(set (match_dup 0) (match_dup 1))]
13283 rtx new_op1 = copy_rtx (operands[1]);
13284 operands[1] = new_op1;
13285 PUT_MODE (new_op1, QImode);
13286 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13287 GET_MODE (XEXP (new_op1, 0))));
13289 /* Make sure that (a) the CCmode we have for the flags is strong
13290 enough for the reversed compare or (b) we have a valid FP compare. */
13291 if (! ix86_comparison_operator (new_op1, VOIDmode))
13295 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
13296 ;; subsequent logical operations are used to imitate conditional moves.
13297 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
13298 ;; it directly. Further holding this value in pseudo register might bring
13299 ;; problem in implicit normalization in spill code.
13300 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
13301 ;; instructions after reload by splitting the conditional move patterns.
13303 (define_insn "*sse_setccsf"
13304 [(set (match_operand:SF 0 "register_operand" "=x")
13305 (match_operator:SF 1 "sse_comparison_operator"
13306 [(match_operand:SF 2 "register_operand" "0")
13307 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
13308 "TARGET_SSE && reload_completed"
13309 "cmp%D1ss\t{%3, %0|%0, %3}"
13310 [(set_attr "type" "ssecmp")
13311 (set_attr "mode" "SF")])
13313 (define_insn "*sse_setccdf"
13314 [(set (match_operand:DF 0 "register_operand" "=Y")
13315 (match_operator:DF 1 "sse_comparison_operator"
13316 [(match_operand:DF 2 "register_operand" "0")
13317 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
13318 "TARGET_SSE2 && reload_completed"
13319 "cmp%D1sd\t{%3, %0|%0, %3}"
13320 [(set_attr "type" "ssecmp")
13321 (set_attr "mode" "DF")])
13323 ;; Basic conditional jump instructions.
13324 ;; We ignore the overflow flag for signed branch instructions.
13326 ;; For all bCOND expanders, also expand the compare or test insn that
13327 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
13329 (define_expand "beq"
13331 (if_then_else (match_dup 1)
13332 (label_ref (match_operand 0 "" ""))
13335 "ix86_expand_branch (EQ, operands[0]); DONE;")
13337 (define_expand "bne"
13339 (if_then_else (match_dup 1)
13340 (label_ref (match_operand 0 "" ""))
13343 "ix86_expand_branch (NE, operands[0]); DONE;")
13345 (define_expand "bgt"
13347 (if_then_else (match_dup 1)
13348 (label_ref (match_operand 0 "" ""))
13351 "ix86_expand_branch (GT, operands[0]); DONE;")
13353 (define_expand "bgtu"
13355 (if_then_else (match_dup 1)
13356 (label_ref (match_operand 0 "" ""))
13359 "ix86_expand_branch (GTU, operands[0]); DONE;")
13361 (define_expand "blt"
13363 (if_then_else (match_dup 1)
13364 (label_ref (match_operand 0 "" ""))
13367 "ix86_expand_branch (LT, operands[0]); DONE;")
13369 (define_expand "bltu"
13371 (if_then_else (match_dup 1)
13372 (label_ref (match_operand 0 "" ""))
13375 "ix86_expand_branch (LTU, operands[0]); DONE;")
13377 (define_expand "bge"
13379 (if_then_else (match_dup 1)
13380 (label_ref (match_operand 0 "" ""))
13383 "ix86_expand_branch (GE, operands[0]); DONE;")
13385 (define_expand "bgeu"
13387 (if_then_else (match_dup 1)
13388 (label_ref (match_operand 0 "" ""))
13391 "ix86_expand_branch (GEU, operands[0]); DONE;")
13393 (define_expand "ble"
13395 (if_then_else (match_dup 1)
13396 (label_ref (match_operand 0 "" ""))
13399 "ix86_expand_branch (LE, operands[0]); DONE;")
13401 (define_expand "bleu"
13403 (if_then_else (match_dup 1)
13404 (label_ref (match_operand 0 "" ""))
13407 "ix86_expand_branch (LEU, operands[0]); DONE;")
13409 (define_expand "bunordered"
13411 (if_then_else (match_dup 1)
13412 (label_ref (match_operand 0 "" ""))
13414 "TARGET_80387 || TARGET_SSE"
13415 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13417 (define_expand "bordered"
13419 (if_then_else (match_dup 1)
13420 (label_ref (match_operand 0 "" ""))
13422 "TARGET_80387 || TARGET_SSE"
13423 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13425 (define_expand "buneq"
13427 (if_then_else (match_dup 1)
13428 (label_ref (match_operand 0 "" ""))
13430 "TARGET_80387 || TARGET_SSE"
13431 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13433 (define_expand "bunge"
13435 (if_then_else (match_dup 1)
13436 (label_ref (match_operand 0 "" ""))
13438 "TARGET_80387 || TARGET_SSE"
13439 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13441 (define_expand "bungt"
13443 (if_then_else (match_dup 1)
13444 (label_ref (match_operand 0 "" ""))
13446 "TARGET_80387 || TARGET_SSE"
13447 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13449 (define_expand "bunle"
13451 (if_then_else (match_dup 1)
13452 (label_ref (match_operand 0 "" ""))
13454 "TARGET_80387 || TARGET_SSE"
13455 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13457 (define_expand "bunlt"
13459 (if_then_else (match_dup 1)
13460 (label_ref (match_operand 0 "" ""))
13462 "TARGET_80387 || TARGET_SSE"
13463 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13465 (define_expand "bltgt"
13467 (if_then_else (match_dup 1)
13468 (label_ref (match_operand 0 "" ""))
13470 "TARGET_80387 || TARGET_SSE"
13471 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13473 (define_insn "*jcc_1"
13475 (if_then_else (match_operator 1 "ix86_comparison_operator"
13476 [(reg 17) (const_int 0)])
13477 (label_ref (match_operand 0 "" ""))
13481 [(set_attr "type" "ibr")
13482 (set_attr "modrm" "0")
13483 (set (attr "length")
13484 (if_then_else (and (ge (minus (match_dup 0) (pc))
13486 (lt (minus (match_dup 0) (pc))
13491 (define_insn "*jcc_2"
13493 (if_then_else (match_operator 1 "ix86_comparison_operator"
13494 [(reg 17) (const_int 0)])
13496 (label_ref (match_operand 0 "" ""))))]
13499 [(set_attr "type" "ibr")
13500 (set_attr "modrm" "0")
13501 (set (attr "length")
13502 (if_then_else (and (ge (minus (match_dup 0) (pc))
13504 (lt (minus (match_dup 0) (pc))
13509 ;; In general it is not safe to assume too much about CCmode registers,
13510 ;; so simplify-rtx stops when it sees a second one. Under certain
13511 ;; conditions this is safe on x86, so help combine not create
13519 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13520 [(reg 17) (const_int 0)])
13522 (label_ref (match_operand 1 "" ""))
13526 (if_then_else (match_dup 0)
13527 (label_ref (match_dup 1))
13530 PUT_MODE (operands[0], VOIDmode);
13535 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13536 [(reg 17) (const_int 0)])
13538 (label_ref (match_operand 1 "" ""))
13542 (if_then_else (match_dup 0)
13543 (label_ref (match_dup 1))
13546 rtx new_op0 = copy_rtx (operands[0]);
13547 operands[0] = new_op0;
13548 PUT_MODE (new_op0, VOIDmode);
13549 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13550 GET_MODE (XEXP (new_op0, 0))));
13552 /* Make sure that (a) the CCmode we have for the flags is strong
13553 enough for the reversed compare or (b) we have a valid FP compare. */
13554 if (! ix86_comparison_operator (new_op0, VOIDmode))
13558 ;; Define combination compare-and-branch fp compare instructions to use
13559 ;; during early optimization. Splitting the operation apart early makes
13560 ;; for bad code when we want to reverse the operation.
13562 (define_insn "*fp_jcc_1"
13564 (if_then_else (match_operator 0 "comparison_operator"
13565 [(match_operand 1 "register_operand" "f")
13566 (match_operand 2 "register_operand" "f")])
13567 (label_ref (match_operand 3 "" ""))
13569 (clobber (reg:CCFP 18))
13570 (clobber (reg:CCFP 17))]
13571 "TARGET_CMOVE && TARGET_80387
13572 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13573 && FLOAT_MODE_P (GET_MODE (operands[1]))
13574 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13575 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13578 (define_insn "*fp_jcc_1_sse"
13580 (if_then_else (match_operator 0 "comparison_operator"
13581 [(match_operand 1 "register_operand" "f#x,x#f")
13582 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13583 (label_ref (match_operand 3 "" ""))
13585 (clobber (reg:CCFP 18))
13586 (clobber (reg:CCFP 17))]
13588 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13589 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13590 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13593 (define_insn "*fp_jcc_1_sse_only"
13595 (if_then_else (match_operator 0 "comparison_operator"
13596 [(match_operand 1 "register_operand" "x")
13597 (match_operand 2 "nonimmediate_operand" "xm")])
13598 (label_ref (match_operand 3 "" ""))
13600 (clobber (reg:CCFP 18))
13601 (clobber (reg:CCFP 17))]
13602 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13603 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13604 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13607 (define_insn "*fp_jcc_2"
13609 (if_then_else (match_operator 0 "comparison_operator"
13610 [(match_operand 1 "register_operand" "f")
13611 (match_operand 2 "register_operand" "f")])
13613 (label_ref (match_operand 3 "" ""))))
13614 (clobber (reg:CCFP 18))
13615 (clobber (reg:CCFP 17))]
13616 "TARGET_CMOVE && TARGET_80387
13617 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13618 && FLOAT_MODE_P (GET_MODE (operands[1]))
13619 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13620 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13623 (define_insn "*fp_jcc_2_sse"
13625 (if_then_else (match_operator 0 "comparison_operator"
13626 [(match_operand 1 "register_operand" "f#x,x#f")
13627 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13629 (label_ref (match_operand 3 "" ""))))
13630 (clobber (reg:CCFP 18))
13631 (clobber (reg:CCFP 17))]
13633 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13634 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13635 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13638 (define_insn "*fp_jcc_2_sse_only"
13640 (if_then_else (match_operator 0 "comparison_operator"
13641 [(match_operand 1 "register_operand" "x")
13642 (match_operand 2 "nonimmediate_operand" "xm")])
13644 (label_ref (match_operand 3 "" ""))))
13645 (clobber (reg:CCFP 18))
13646 (clobber (reg:CCFP 17))]
13647 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13648 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13649 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13652 (define_insn "*fp_jcc_3"
13654 (if_then_else (match_operator 0 "comparison_operator"
13655 [(match_operand 1 "register_operand" "f")
13656 (match_operand 2 "nonimmediate_operand" "fm")])
13657 (label_ref (match_operand 3 "" ""))
13659 (clobber (reg:CCFP 18))
13660 (clobber (reg:CCFP 17))
13661 (clobber (match_scratch:HI 4 "=a"))]
13663 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13664 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13665 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13666 && SELECT_CC_MODE (GET_CODE (operands[0]),
13667 operands[1], operands[2]) == CCFPmode
13668 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13671 (define_insn "*fp_jcc_4"
13673 (if_then_else (match_operator 0 "comparison_operator"
13674 [(match_operand 1 "register_operand" "f")
13675 (match_operand 2 "nonimmediate_operand" "fm")])
13677 (label_ref (match_operand 3 "" ""))))
13678 (clobber (reg:CCFP 18))
13679 (clobber (reg:CCFP 17))
13680 (clobber (match_scratch:HI 4 "=a"))]
13682 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13683 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13684 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13685 && SELECT_CC_MODE (GET_CODE (operands[0]),
13686 operands[1], operands[2]) == CCFPmode
13687 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13690 (define_insn "*fp_jcc_5"
13692 (if_then_else (match_operator 0 "comparison_operator"
13693 [(match_operand 1 "register_operand" "f")
13694 (match_operand 2 "register_operand" "f")])
13695 (label_ref (match_operand 3 "" ""))
13697 (clobber (reg:CCFP 18))
13698 (clobber (reg:CCFP 17))
13699 (clobber (match_scratch:HI 4 "=a"))]
13701 && FLOAT_MODE_P (GET_MODE (operands[1]))
13702 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13703 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13706 (define_insn "*fp_jcc_6"
13708 (if_then_else (match_operator 0 "comparison_operator"
13709 [(match_operand 1 "register_operand" "f")
13710 (match_operand 2 "register_operand" "f")])
13712 (label_ref (match_operand 3 "" ""))))
13713 (clobber (reg:CCFP 18))
13714 (clobber (reg:CCFP 17))
13715 (clobber (match_scratch:HI 4 "=a"))]
13717 && FLOAT_MODE_P (GET_MODE (operands[1]))
13718 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13719 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13724 (if_then_else (match_operator 0 "comparison_operator"
13725 [(match_operand 1 "register_operand" "")
13726 (match_operand 2 "nonimmediate_operand" "")])
13727 (match_operand 3 "" "")
13728 (match_operand 4 "" "")))
13729 (clobber (reg:CCFP 18))
13730 (clobber (reg:CCFP 17))]
13734 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13735 operands[3], operands[4], NULL_RTX);
13741 (if_then_else (match_operator 0 "comparison_operator"
13742 [(match_operand 1 "register_operand" "")
13743 (match_operand 2 "nonimmediate_operand" "")])
13744 (match_operand 3 "" "")
13745 (match_operand 4 "" "")))
13746 (clobber (reg:CCFP 18))
13747 (clobber (reg:CCFP 17))
13748 (clobber (match_scratch:HI 5 "=a"))]
13751 (if_then_else (match_dup 6)
13755 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13756 operands[3], operands[4], operands[5]);
13760 ;; Unconditional and other jump instructions
13762 (define_insn "jump"
13764 (label_ref (match_operand 0 "" "")))]
13767 [(set_attr "type" "ibr")
13768 (set (attr "length")
13769 (if_then_else (and (ge (minus (match_dup 0) (pc))
13771 (lt (minus (match_dup 0) (pc))
13775 (set_attr "modrm" "0")])
13777 (define_expand "indirect_jump"
13778 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13782 (define_insn "*indirect_jump"
13783 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13786 [(set_attr "type" "ibr")
13787 (set_attr "length_immediate" "0")])
13789 (define_insn "*indirect_jump_rtx64"
13790 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13793 [(set_attr "type" "ibr")
13794 (set_attr "length_immediate" "0")])
13796 (define_expand "tablejump"
13797 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13798 (use (label_ref (match_operand 1 "" "")))])]
13801 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13802 relative. Convert the relative address to an absolute address. */
13806 enum rtx_code code;
13812 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13814 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13818 op1 = pic_offset_table_rtx;
13823 op0 = pic_offset_table_rtx;
13827 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13832 (define_insn "*tablejump_1"
13833 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13834 (use (label_ref (match_operand 1 "" "")))]
13837 [(set_attr "type" "ibr")
13838 (set_attr "length_immediate" "0")])
13840 (define_insn "*tablejump_1_rtx64"
13841 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13842 (use (label_ref (match_operand 1 "" "")))]
13845 [(set_attr "type" "ibr")
13846 (set_attr "length_immediate" "0")])
13848 ;; Loop instruction
13850 ;; This is all complicated by the fact that since this is a jump insn
13851 ;; we must handle our own reloads.
13853 (define_expand "doloop_end"
13854 [(use (match_operand 0 "" "")) ; loop pseudo
13855 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13856 (use (match_operand 2 "" "")) ; max iterations
13857 (use (match_operand 3 "" "")) ; loop level
13858 (use (match_operand 4 "" ""))] ; label
13859 "!TARGET_64BIT && TARGET_USE_LOOP"
13862 /* Only use cloop on innermost loops. */
13863 if (INTVAL (operands[3]) > 1)
13865 if (GET_MODE (operands[0]) != SImode)
13867 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13872 (define_insn "doloop_end_internal"
13874 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13876 (label_ref (match_operand 0 "" ""))
13878 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13879 (plus:SI (match_dup 1)
13881 (clobber (match_scratch:SI 3 "=X,X,r"))
13882 (clobber (reg:CC 17))]
13883 "!TARGET_64BIT && TARGET_USE_LOOP"
13885 if (which_alternative != 0)
13887 if (get_attr_length (insn) == 2)
13888 return "%+loop\t%l0";
13890 return "dec{l}\t%1\;%+jne\t%l0";
13892 [(set_attr "ppro_uops" "many")
13893 (set (attr "length")
13894 (if_then_else (and (eq_attr "alternative" "0")
13895 (and (ge (minus (match_dup 0) (pc))
13897 (lt (minus (match_dup 0) (pc))
13901 ;; We don't know the type before shorten branches. Optimistically expect
13902 ;; the loop instruction to match.
13903 (set (attr "type") (const_string "ibr"))])
13907 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13909 (match_operand 0 "" "")
13912 (plus:SI (match_dup 1)
13914 (clobber (match_scratch:SI 2 ""))
13915 (clobber (reg:CC 17))]
13916 "!TARGET_64BIT && TARGET_USE_LOOP
13917 && reload_completed
13918 && REGNO (operands[1]) != 2"
13919 [(parallel [(set (reg:CCZ 17)
13920 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13922 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13923 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13930 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13932 (match_operand 0 "" "")
13934 (set (match_operand:SI 2 "nonimmediate_operand" "")
13935 (plus:SI (match_dup 1)
13937 (clobber (match_scratch:SI 3 ""))
13938 (clobber (reg:CC 17))]
13939 "!TARGET_64BIT && TARGET_USE_LOOP
13940 && reload_completed
13941 && (! REG_P (operands[2])
13942 || ! rtx_equal_p (operands[1], operands[2]))"
13943 [(set (match_dup 3) (match_dup 1))
13944 (parallel [(set (reg:CCZ 17)
13945 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13947 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13948 (set (match_dup 2) (match_dup 3))
13949 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13954 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13957 [(set (reg 17) (match_operand 0 "" ""))
13958 (set (match_operand:QI 1 "register_operand" "")
13959 (match_operator:QI 2 "ix86_comparison_operator"
13960 [(reg 17) (const_int 0)]))
13961 (set (match_operand 3 "q_regs_operand" "")
13962 (zero_extend (match_dup 1)))]
13963 "(peep2_reg_dead_p (3, operands[1])
13964 || operands_match_p (operands[1], operands[3]))
13965 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13966 [(set (match_dup 4) (match_dup 0))
13967 (set (strict_low_part (match_dup 5))
13970 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13971 operands[5] = gen_lowpart (QImode, operands[3]);
13972 ix86_expand_clear (operands[3]);
13975 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13978 [(set (reg 17) (match_operand 0 "" ""))
13979 (set (match_operand:QI 1 "register_operand" "")
13980 (match_operator:QI 2 "ix86_comparison_operator"
13981 [(reg 17) (const_int 0)]))
13982 (parallel [(set (match_operand 3 "q_regs_operand" "")
13983 (zero_extend (match_dup 1)))
13984 (clobber (reg:CC 17))])]
13985 "(peep2_reg_dead_p (3, operands[1])
13986 || operands_match_p (operands[1], operands[3]))
13987 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13988 [(set (match_dup 4) (match_dup 0))
13989 (set (strict_low_part (match_dup 5))
13992 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13993 operands[5] = gen_lowpart (QImode, operands[3]);
13994 ix86_expand_clear (operands[3]);
13997 ;; Call instructions.
13999 ;; The predicates normally associated with named expanders are not properly
14000 ;; checked for calls. This is a bug in the generic code, but it isn't that
14001 ;; easy to fix. Ignore it for now and be prepared to fix things up.
14003 ;; Call subroutine returning no value.
14005 (define_expand "call_pop"
14006 [(parallel [(call (match_operand:QI 0 "" "")
14007 (match_operand:SI 1 "" ""))
14009 (plus:SI (reg:SI 7)
14010 (match_operand:SI 3 "" "")))])]
14013 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
14017 (define_insn "*call_pop_0"
14018 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
14019 (match_operand:SI 1 "" ""))
14020 (set (reg:SI 7) (plus:SI (reg:SI 7)
14021 (match_operand:SI 2 "immediate_operand" "")))]
14024 if (SIBLING_CALL_P (insn))
14027 return "call\t%P0";
14029 [(set_attr "type" "call")])
14031 (define_insn "*call_pop_1"
14032 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14033 (match_operand:SI 1 "" ""))
14034 (set (reg:SI 7) (plus:SI (reg:SI 7)
14035 (match_operand:SI 2 "immediate_operand" "i")))]
14038 if (constant_call_address_operand (operands[0], Pmode))
14040 if (SIBLING_CALL_P (insn))
14043 return "call\t%P0";
14045 if (SIBLING_CALL_P (insn))
14048 return "call\t%A0";
14050 [(set_attr "type" "call")])
14052 (define_expand "call"
14053 [(call (match_operand:QI 0 "" "")
14054 (match_operand 1 "" ""))
14055 (use (match_operand 2 "" ""))]
14058 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
14062 (define_expand "sibcall"
14063 [(call (match_operand:QI 0 "" "")
14064 (match_operand 1 "" ""))
14065 (use (match_operand 2 "" ""))]
14068 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
14072 (define_insn "*call_0"
14073 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
14074 (match_operand 1 "" ""))]
14077 if (SIBLING_CALL_P (insn))
14080 return "call\t%P0";
14082 [(set_attr "type" "call")])
14084 (define_insn "*call_1"
14085 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14086 (match_operand 1 "" ""))]
14087 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
14089 if (constant_call_address_operand (operands[0], QImode))
14090 return "call\t%P0";
14091 return "call\t%A0";
14093 [(set_attr "type" "call")])
14095 (define_insn "*sibcall_1"
14096 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
14097 (match_operand 1 "" ""))]
14098 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
14100 if (constant_call_address_operand (operands[0], QImode))
14104 [(set_attr "type" "call")])
14106 (define_insn "*call_1_rex64"
14107 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
14108 (match_operand 1 "" ""))]
14109 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
14111 if (constant_call_address_operand (operands[0], QImode))
14112 return "call\t%P0";
14113 return "call\t%A0";
14115 [(set_attr "type" "call")])
14117 (define_insn "*sibcall_1_rex64"
14118 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
14119 (match_operand 1 "" ""))]
14120 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14122 [(set_attr "type" "call")])
14124 (define_insn "*sibcall_1_rex64_v"
14125 [(call (mem:QI (reg:DI 40))
14126 (match_operand 0 "" ""))]
14127 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14129 [(set_attr "type" "call")])
14132 ;; Call subroutine, returning value in operand 0
14134 (define_expand "call_value_pop"
14135 [(parallel [(set (match_operand 0 "" "")
14136 (call (match_operand:QI 1 "" "")
14137 (match_operand:SI 2 "" "")))
14139 (plus:SI (reg:SI 7)
14140 (match_operand:SI 4 "" "")))])]
14143 ix86_expand_call (operands[0], operands[1], operands[2],
14144 operands[3], operands[4], 0);
14148 (define_expand "call_value"
14149 [(set (match_operand 0 "" "")
14150 (call (match_operand:QI 1 "" "")
14151 (match_operand:SI 2 "" "")))
14152 (use (match_operand:SI 3 "" ""))]
14153 ;; Operand 2 not used on the i386.
14156 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
14160 (define_expand "sibcall_value"
14161 [(set (match_operand 0 "" "")
14162 (call (match_operand:QI 1 "" "")
14163 (match_operand:SI 2 "" "")))
14164 (use (match_operand:SI 3 "" ""))]
14165 ;; Operand 2 not used on the i386.
14168 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
14172 ;; Call subroutine returning any type.
14174 (define_expand "untyped_call"
14175 [(parallel [(call (match_operand 0 "" "")
14177 (match_operand 1 "" "")
14178 (match_operand 2 "" "")])]
14183 /* In order to give reg-stack an easier job in validating two
14184 coprocessor registers as containing a possible return value,
14185 simply pretend the untyped call returns a complex long double
14188 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
14189 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
14190 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
14193 for (i = 0; i < XVECLEN (operands[2], 0); i++)
14195 rtx set = XVECEXP (operands[2], 0, i);
14196 emit_move_insn (SET_DEST (set), SET_SRC (set));
14199 /* The optimizer does not know that the call sets the function value
14200 registers we stored in the result block. We avoid problems by
14201 claiming that all hard registers are used and clobbered at this
14203 emit_insn (gen_blockage (const0_rtx));
14208 ;; Prologue and epilogue instructions
14210 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
14211 ;; all of memory. This blocks insns from being moved across this point.
14213 (define_insn "blockage"
14214 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
14217 [(set_attr "length" "0")])
14219 ;; Insn emitted into the body of a function to return from a function.
14220 ;; This is only done if the function's epilogue is known to be simple.
14221 ;; See comments for ix86_can_use_return_insn_p in i386.c.
14223 (define_expand "return"
14225 "ix86_can_use_return_insn_p ()"
14227 if (current_function_pops_args)
14229 rtx popc = GEN_INT (current_function_pops_args);
14230 emit_jump_insn (gen_return_pop_internal (popc));
14235 (define_insn "return_internal"
14239 [(set_attr "length" "1")
14240 (set_attr "length_immediate" "0")
14241 (set_attr "modrm" "0")])
14243 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
14244 ;; instruction Athlon and K8 have.
14246 (define_insn "return_internal_long"
14248 (unspec [(const_int 0)] UNSPEC_REP)]
14251 [(set_attr "length" "1")
14252 (set_attr "length_immediate" "0")
14253 (set_attr "prefix_rep" "1")
14254 (set_attr "modrm" "0")])
14256 (define_insn "return_pop_internal"
14258 (use (match_operand:SI 0 "const_int_operand" ""))]
14261 [(set_attr "length" "3")
14262 (set_attr "length_immediate" "2")
14263 (set_attr "modrm" "0")])
14265 (define_insn "return_indirect_internal"
14267 (use (match_operand:SI 0 "register_operand" "r"))]
14270 [(set_attr "type" "ibr")
14271 (set_attr "length_immediate" "0")])
14277 [(set_attr "length" "1")
14278 (set_attr "length_immediate" "0")
14279 (set_attr "modrm" "0")
14280 (set_attr "ppro_uops" "one")])
14282 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
14283 ;; branch prediction penalty for the third jump in a 16-byte
14286 (define_insn "align"
14287 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
14290 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
14291 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, INTVAL (operands[0]));
14293 ASM_OUTPUT_ALIGN (asm_out_file, 4);
14297 [(set_attr "length" "16")])
14299 (define_expand "prologue"
14302 "ix86_expand_prologue (); DONE;")
14304 (define_insn "set_got"
14305 [(set (match_operand:SI 0 "register_operand" "=r")
14306 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
14307 (clobber (reg:CC 17))]
14309 { return output_set_got (operands[0]); }
14310 [(set_attr "type" "multi")
14311 (set_attr "length" "12")])
14313 (define_expand "epilogue"
14316 "ix86_expand_epilogue (1); DONE;")
14318 (define_expand "sibcall_epilogue"
14321 "ix86_expand_epilogue (0); DONE;")
14323 (define_expand "eh_return"
14324 [(use (match_operand 0 "register_operand" ""))]
14327 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
14329 /* Tricky bit: we write the address of the handler to which we will
14330 be returning into someone else's stack frame, one word below the
14331 stack address we wish to restore. */
14332 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
14333 tmp = plus_constant (tmp, -UNITS_PER_WORD);
14334 tmp = gen_rtx_MEM (Pmode, tmp);
14335 emit_move_insn (tmp, ra);
14337 if (Pmode == SImode)
14338 emit_insn (gen_eh_return_si (sa));
14340 emit_insn (gen_eh_return_di (sa));
14345 (define_insn_and_split "eh_return_si"
14346 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
14347 UNSPECV_EH_RETURN)]
14352 "ix86_expand_epilogue (2); DONE;")
14354 (define_insn_and_split "eh_return_di"
14355 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
14356 UNSPECV_EH_RETURN)]
14361 "ix86_expand_epilogue (2); DONE;")
14363 (define_insn "leave"
14364 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
14365 (set (reg:SI 6) (mem:SI (reg:SI 6)))
14366 (clobber (mem:BLK (scratch)))]
14369 [(set_attr "type" "leave")])
14371 (define_insn "leave_rex64"
14372 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
14373 (set (reg:DI 6) (mem:DI (reg:DI 6)))
14374 (clobber (mem:BLK (scratch)))]
14377 [(set_attr "type" "leave")])
14379 (define_expand "ffssi2"
14381 [(set (match_operand:SI 0 "register_operand" "")
14382 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
14383 (clobber (match_scratch:SI 2 ""))
14384 (clobber (reg:CC 17))])]
14388 (define_insn_and_split "*ffs_cmove"
14389 [(set (match_operand:SI 0 "register_operand" "=r")
14390 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14391 (clobber (match_scratch:SI 2 "=&r"))
14392 (clobber (reg:CC 17))]
14395 "&& reload_completed"
14396 [(set (match_dup 2) (const_int -1))
14397 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14398 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14399 (set (match_dup 0) (if_then_else:SI
14400 (eq (reg:CCZ 17) (const_int 0))
14403 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14404 (clobber (reg:CC 17))])]
14407 (define_insn_and_split "*ffs_no_cmove"
14408 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14409 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14410 (clobber (match_scratch:SI 2 "=&r"))
14411 (clobber (reg:CC 17))]
14415 [(parallel [(set (match_dup 2) (const_int 0))
14416 (clobber (reg:CC 17))])
14417 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14418 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14419 (set (strict_low_part (match_dup 3))
14420 (eq:QI (reg:CCZ 17) (const_int 0)))
14421 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14422 (clobber (reg:CC 17))])
14423 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14424 (clobber (reg:CC 17))])
14425 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14426 (clobber (reg:CC 17))])]
14428 operands[3] = gen_lowpart (QImode, operands[2]);
14431 (define_insn "*ffssi_1"
14433 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14435 (set (match_operand:SI 0 "register_operand" "=r")
14436 (ctz:SI (match_dup 1)))]
14438 "bsf{l}\t{%1, %0|%0, %1}"
14439 [(set_attr "prefix_0f" "1")
14440 (set_attr "ppro_uops" "few")])
14442 (define_insn "ctzsi2"
14443 [(set (match_operand:SI 0 "register_operand" "=r")
14444 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14445 (clobber (reg:CC 17))]
14447 "bsf{l}\t{%1, %0|%0, %1}"
14448 [(set_attr "prefix_0f" "1")
14449 (set_attr "ppro_uops" "few")])
14451 (define_expand "clzsi2"
14453 [(set (match_operand:SI 0 "register_operand" "")
14454 (minus:SI (const_int 31)
14455 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14456 (clobber (reg:CC 17))])
14458 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14459 (clobber (reg:CC 17))])]
14463 (define_insn "*bsr"
14464 [(set (match_operand:SI 0 "register_operand" "=r")
14465 (minus:SI (const_int 31)
14466 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14467 (clobber (reg:CC 17))]
14469 "bsr{l}\t{%1, %0|%0, %1}"
14470 [(set_attr "prefix_0f" "1")
14471 (set_attr "ppro_uops" "few")])
14473 ;; Thread-local storage patterns for ELF.
14475 ;; Note that these code sequences must appear exactly as shown
14476 ;; in order to allow linker relaxation.
14478 (define_insn "*tls_global_dynamic_32_gnu"
14479 [(set (match_operand:SI 0 "register_operand" "=a")
14480 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14481 (match_operand:SI 2 "tls_symbolic_operand" "")
14482 (match_operand:SI 3 "call_insn_operand" "")]
14484 (clobber (match_scratch:SI 4 "=d"))
14485 (clobber (match_scratch:SI 5 "=c"))
14486 (clobber (reg:CC 17))]
14487 "!TARGET_64BIT && TARGET_GNU_TLS"
14488 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14489 [(set_attr "type" "multi")
14490 (set_attr "length" "12")])
14492 (define_insn "*tls_global_dynamic_32_sun"
14493 [(set (match_operand:SI 0 "register_operand" "=a")
14494 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14495 (match_operand:SI 2 "tls_symbolic_operand" "")
14496 (match_operand:SI 3 "call_insn_operand" "")]
14498 (clobber (match_scratch:SI 4 "=d"))
14499 (clobber (match_scratch:SI 5 "=c"))
14500 (clobber (reg:CC 17))]
14501 "!TARGET_64BIT && TARGET_SUN_TLS"
14502 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14503 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14504 [(set_attr "type" "multi")
14505 (set_attr "length" "14")])
14507 (define_expand "tls_global_dynamic_32"
14508 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14511 (match_operand:SI 1 "tls_symbolic_operand" "")
14514 (clobber (match_scratch:SI 4 ""))
14515 (clobber (match_scratch:SI 5 ""))
14516 (clobber (reg:CC 17))])]
14520 operands[2] = pic_offset_table_rtx;
14523 operands[2] = gen_reg_rtx (Pmode);
14524 emit_insn (gen_set_got (operands[2]));
14526 operands[3] = ix86_tls_get_addr ();
14529 (define_insn "*tls_global_dynamic_64"
14530 [(set (match_operand:DI 0 "register_operand" "=a")
14531 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14532 (match_operand:DI 3 "" "")))
14533 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14536 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14537 [(set_attr "type" "multi")
14538 (set_attr "length" "16")])
14540 (define_expand "tls_global_dynamic_64"
14541 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14542 (call (mem:QI (match_dup 2)) (const_int 0)))
14543 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14547 operands[2] = ix86_tls_get_addr ();
14550 (define_insn "*tls_local_dynamic_base_32_gnu"
14551 [(set (match_operand:SI 0 "register_operand" "=a")
14552 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14553 (match_operand:SI 2 "call_insn_operand" "")]
14554 UNSPEC_TLS_LD_BASE))
14555 (clobber (match_scratch:SI 3 "=d"))
14556 (clobber (match_scratch:SI 4 "=c"))
14557 (clobber (reg:CC 17))]
14558 "!TARGET_64BIT && TARGET_GNU_TLS"
14559 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14560 [(set_attr "type" "multi")
14561 (set_attr "length" "11")])
14563 (define_insn "*tls_local_dynamic_base_32_sun"
14564 [(set (match_operand:SI 0 "register_operand" "=a")
14565 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14566 (match_operand:SI 2 "call_insn_operand" "")]
14567 UNSPEC_TLS_LD_BASE))
14568 (clobber (match_scratch:SI 3 "=d"))
14569 (clobber (match_scratch:SI 4 "=c"))
14570 (clobber (reg:CC 17))]
14571 "!TARGET_64BIT && TARGET_SUN_TLS"
14572 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14573 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14574 [(set_attr "type" "multi")
14575 (set_attr "length" "13")])
14577 (define_expand "tls_local_dynamic_base_32"
14578 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14579 (unspec:SI [(match_dup 1) (match_dup 2)]
14580 UNSPEC_TLS_LD_BASE))
14581 (clobber (match_scratch:SI 3 ""))
14582 (clobber (match_scratch:SI 4 ""))
14583 (clobber (reg:CC 17))])]
14587 operands[1] = pic_offset_table_rtx;
14590 operands[1] = gen_reg_rtx (Pmode);
14591 emit_insn (gen_set_got (operands[1]));
14593 operands[2] = ix86_tls_get_addr ();
14596 (define_insn "*tls_local_dynamic_base_64"
14597 [(set (match_operand:DI 0 "register_operand" "=a")
14598 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14599 (match_operand:DI 2 "" "")))
14600 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14602 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14603 [(set_attr "type" "multi")
14604 (set_attr "length" "12")])
14606 (define_expand "tls_local_dynamic_base_64"
14607 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14608 (call (mem:QI (match_dup 1)) (const_int 0)))
14609 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14612 operands[1] = ix86_tls_get_addr ();
14615 ;; Local dynamic of a single variable is a lose. Show combine how
14616 ;; to convert that back to global dynamic.
14618 (define_insn_and_split "*tls_local_dynamic_32_once"
14619 [(set (match_operand:SI 0 "register_operand" "=a")
14620 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14621 (match_operand:SI 2 "call_insn_operand" "")]
14622 UNSPEC_TLS_LD_BASE)
14623 (const:SI (unspec:SI
14624 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14626 (clobber (match_scratch:SI 4 "=d"))
14627 (clobber (match_scratch:SI 5 "=c"))
14628 (clobber (reg:CC 17))]
14632 [(parallel [(set (match_dup 0)
14633 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14635 (clobber (match_dup 4))
14636 (clobber (match_dup 5))
14637 (clobber (reg:CC 17))])]
14640 ;; These patterns match the binary 387 instructions for addM3, subM3,
14641 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14642 ;; SFmode. The first is the normal insn, the second the same insn but
14643 ;; with one operand a conversion, and the third the same insn but with
14644 ;; the other operand a conversion. The conversion may be SFmode or
14645 ;; SImode if the target mode DFmode, but only SImode if the target mode
14648 ;; Gcc is slightly more smart about handling normal two address instructions
14649 ;; so use special patterns for add and mull.
14650 (define_insn "*fop_sf_comm_nosse"
14651 [(set (match_operand:SF 0 "register_operand" "=f")
14652 (match_operator:SF 3 "binary_fp_operator"
14653 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14654 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14655 "TARGET_80387 && !TARGET_SSE_MATH
14656 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14657 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14658 "* return output_387_binary_op (insn, operands);"
14659 [(set (attr "type")
14660 (if_then_else (match_operand:SF 3 "mult_operator" "")
14661 (const_string "fmul")
14662 (const_string "fop")))
14663 (set_attr "mode" "SF")])
14665 (define_insn "*fop_sf_comm"
14666 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14667 (match_operator:SF 3 "binary_fp_operator"
14668 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14669 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14670 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14671 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14672 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14673 "* return output_387_binary_op (insn, operands);"
14674 [(set (attr "type")
14675 (if_then_else (eq_attr "alternative" "1")
14676 (if_then_else (match_operand:SF 3 "mult_operator" "")
14677 (const_string "ssemul")
14678 (const_string "sseadd"))
14679 (if_then_else (match_operand:SF 3 "mult_operator" "")
14680 (const_string "fmul")
14681 (const_string "fop"))))
14682 (set_attr "mode" "SF")])
14684 (define_insn "*fop_sf_comm_sse"
14685 [(set (match_operand:SF 0 "register_operand" "=x")
14686 (match_operator:SF 3 "binary_fp_operator"
14687 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14688 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14689 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14690 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14691 "* return output_387_binary_op (insn, operands);"
14692 [(set (attr "type")
14693 (if_then_else (match_operand:SF 3 "mult_operator" "")
14694 (const_string "ssemul")
14695 (const_string "sseadd")))
14696 (set_attr "mode" "SF")])
14698 (define_insn "*fop_df_comm_nosse"
14699 [(set (match_operand:DF 0 "register_operand" "=f")
14700 (match_operator:DF 3 "binary_fp_operator"
14701 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14702 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14703 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14704 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14705 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14706 "* return output_387_binary_op (insn, operands);"
14707 [(set (attr "type")
14708 (if_then_else (match_operand:SF 3 "mult_operator" "")
14709 (const_string "fmul")
14710 (const_string "fop")))
14711 (set_attr "mode" "DF")])
14713 (define_insn "*fop_df_comm"
14714 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14715 (match_operator:DF 3 "binary_fp_operator"
14716 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14717 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14718 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14719 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14720 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14721 "* return output_387_binary_op (insn, operands);"
14722 [(set (attr "type")
14723 (if_then_else (eq_attr "alternative" "1")
14724 (if_then_else (match_operand:SF 3 "mult_operator" "")
14725 (const_string "ssemul")
14726 (const_string "sseadd"))
14727 (if_then_else (match_operand:SF 3 "mult_operator" "")
14728 (const_string "fmul")
14729 (const_string "fop"))))
14730 (set_attr "mode" "DF")])
14732 (define_insn "*fop_df_comm_sse"
14733 [(set (match_operand:DF 0 "register_operand" "=Y")
14734 (match_operator:DF 3 "binary_fp_operator"
14735 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14736 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14737 "TARGET_SSE2 && TARGET_SSE_MATH
14738 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14739 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14740 "* return output_387_binary_op (insn, operands);"
14741 [(set (attr "type")
14742 (if_then_else (match_operand:SF 3 "mult_operator" "")
14743 (const_string "ssemul")
14744 (const_string "sseadd")))
14745 (set_attr "mode" "DF")])
14747 (define_insn "*fop_xf_comm"
14748 [(set (match_operand:XF 0 "register_operand" "=f")
14749 (match_operator:XF 3 "binary_fp_operator"
14750 [(match_operand:XF 1 "register_operand" "%0")
14751 (match_operand:XF 2 "register_operand" "f")]))]
14752 "!TARGET_64BIT && TARGET_80387
14753 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14754 "* return output_387_binary_op (insn, operands);"
14755 [(set (attr "type")
14756 (if_then_else (match_operand:XF 3 "mult_operator" "")
14757 (const_string "fmul")
14758 (const_string "fop")))
14759 (set_attr "mode" "XF")])
14761 (define_insn "*fop_tf_comm"
14762 [(set (match_operand:TF 0 "register_operand" "=f")
14763 (match_operator:TF 3 "binary_fp_operator"
14764 [(match_operand:TF 1 "register_operand" "%0")
14765 (match_operand:TF 2 "register_operand" "f")]))]
14766 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14767 "* return output_387_binary_op (insn, operands);"
14768 [(set (attr "type")
14769 (if_then_else (match_operand:TF 3 "mult_operator" "")
14770 (const_string "fmul")
14771 (const_string "fop")))
14772 (set_attr "mode" "XF")])
14774 (define_insn "*fop_sf_1_nosse"
14775 [(set (match_operand:SF 0 "register_operand" "=f,f")
14776 (match_operator:SF 3 "binary_fp_operator"
14777 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14778 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14779 "TARGET_80387 && !TARGET_SSE_MATH
14780 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14781 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14782 "* return output_387_binary_op (insn, operands);"
14783 [(set (attr "type")
14784 (cond [(match_operand:SF 3 "mult_operator" "")
14785 (const_string "fmul")
14786 (match_operand:SF 3 "div_operator" "")
14787 (const_string "fdiv")
14789 (const_string "fop")))
14790 (set_attr "mode" "SF")])
14792 (define_insn "*fop_sf_1"
14793 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14794 (match_operator:SF 3 "binary_fp_operator"
14795 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14796 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14797 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14798 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14799 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14800 "* return output_387_binary_op (insn, operands);"
14801 [(set (attr "type")
14802 (cond [(and (eq_attr "alternative" "2")
14803 (match_operand:SF 3 "mult_operator" ""))
14804 (const_string "ssemul")
14805 (and (eq_attr "alternative" "2")
14806 (match_operand:SF 3 "div_operator" ""))
14807 (const_string "ssediv")
14808 (eq_attr "alternative" "2")
14809 (const_string "sseadd")
14810 (match_operand:SF 3 "mult_operator" "")
14811 (const_string "fmul")
14812 (match_operand:SF 3 "div_operator" "")
14813 (const_string "fdiv")
14815 (const_string "fop")))
14816 (set_attr "mode" "SF")])
14818 (define_insn "*fop_sf_1_sse"
14819 [(set (match_operand:SF 0 "register_operand" "=x")
14820 (match_operator:SF 3 "binary_fp_operator"
14821 [(match_operand:SF 1 "register_operand" "0")
14822 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14824 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14825 "* return output_387_binary_op (insn, operands);"
14826 [(set (attr "type")
14827 (cond [(match_operand:SF 3 "mult_operator" "")
14828 (const_string "ssemul")
14829 (match_operand:SF 3 "div_operator" "")
14830 (const_string "ssediv")
14832 (const_string "sseadd")))
14833 (set_attr "mode" "SF")])
14835 ;; ??? Add SSE splitters for these!
14836 (define_insn "*fop_sf_2"
14837 [(set (match_operand:SF 0 "register_operand" "=f,f")
14838 (match_operator:SF 3 "binary_fp_operator"
14839 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14840 (match_operand:SF 2 "register_operand" "0,0")]))]
14841 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14842 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14843 [(set (attr "type")
14844 (cond [(match_operand:SF 3 "mult_operator" "")
14845 (const_string "fmul")
14846 (match_operand:SF 3 "div_operator" "")
14847 (const_string "fdiv")
14849 (const_string "fop")))
14850 (set_attr "fp_int_src" "true")
14851 (set_attr "ppro_uops" "many")
14852 (set_attr "mode" "SI")])
14854 (define_insn "*fop_sf_3"
14855 [(set (match_operand:SF 0 "register_operand" "=f,f")
14856 (match_operator:SF 3 "binary_fp_operator"
14857 [(match_operand:SF 1 "register_operand" "0,0")
14858 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14859 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14860 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14861 [(set (attr "type")
14862 (cond [(match_operand:SF 3 "mult_operator" "")
14863 (const_string "fmul")
14864 (match_operand:SF 3 "div_operator" "")
14865 (const_string "fdiv")
14867 (const_string "fop")))
14868 (set_attr "fp_int_src" "true")
14869 (set_attr "ppro_uops" "many")
14870 (set_attr "mode" "SI")])
14872 (define_insn "*fop_df_1_nosse"
14873 [(set (match_operand:DF 0 "register_operand" "=f,f")
14874 (match_operator:DF 3 "binary_fp_operator"
14875 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14876 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14877 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14878 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14879 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14880 "* return output_387_binary_op (insn, operands);"
14881 [(set (attr "type")
14882 (cond [(match_operand:DF 3 "mult_operator" "")
14883 (const_string "fmul")
14884 (match_operand:DF 3 "div_operator" "")
14885 (const_string "fdiv")
14887 (const_string "fop")))
14888 (set_attr "mode" "DF")])
14891 (define_insn "*fop_df_1"
14892 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14893 (match_operator:DF 3 "binary_fp_operator"
14894 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14895 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14896 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14897 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14898 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14899 "* return output_387_binary_op (insn, operands);"
14900 [(set (attr "type")
14901 (cond [(and (eq_attr "alternative" "2")
14902 (match_operand:SF 3 "mult_operator" ""))
14903 (const_string "ssemul")
14904 (and (eq_attr "alternative" "2")
14905 (match_operand:SF 3 "div_operator" ""))
14906 (const_string "ssediv")
14907 (eq_attr "alternative" "2")
14908 (const_string "sseadd")
14909 (match_operand:DF 3 "mult_operator" "")
14910 (const_string "fmul")
14911 (match_operand:DF 3 "div_operator" "")
14912 (const_string "fdiv")
14914 (const_string "fop")))
14915 (set_attr "mode" "DF")])
14917 (define_insn "*fop_df_1_sse"
14918 [(set (match_operand:DF 0 "register_operand" "=Y")
14919 (match_operator:DF 3 "binary_fp_operator"
14920 [(match_operand:DF 1 "register_operand" "0")
14921 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14922 "TARGET_SSE2 && TARGET_SSE_MATH
14923 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14924 "* return output_387_binary_op (insn, operands);"
14925 [(set_attr "mode" "DF")
14927 (cond [(match_operand:SF 3 "mult_operator" "")
14928 (const_string "ssemul")
14929 (match_operand:SF 3 "div_operator" "")
14930 (const_string "ssediv")
14932 (const_string "sseadd")))])
14934 ;; ??? Add SSE splitters for these!
14935 (define_insn "*fop_df_2"
14936 [(set (match_operand:DF 0 "register_operand" "=f,f")
14937 (match_operator:DF 3 "binary_fp_operator"
14938 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14939 (match_operand:DF 2 "register_operand" "0,0")]))]
14940 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14941 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14942 [(set (attr "type")
14943 (cond [(match_operand:DF 3 "mult_operator" "")
14944 (const_string "fmul")
14945 (match_operand:DF 3 "div_operator" "")
14946 (const_string "fdiv")
14948 (const_string "fop")))
14949 (set_attr "fp_int_src" "true")
14950 (set_attr "ppro_uops" "many")
14951 (set_attr "mode" "SI")])
14953 (define_insn "*fop_df_3"
14954 [(set (match_operand:DF 0 "register_operand" "=f,f")
14955 (match_operator:DF 3 "binary_fp_operator"
14956 [(match_operand:DF 1 "register_operand" "0,0")
14957 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14958 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14959 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14960 [(set (attr "type")
14961 (cond [(match_operand:DF 3 "mult_operator" "")
14962 (const_string "fmul")
14963 (match_operand:DF 3 "div_operator" "")
14964 (const_string "fdiv")
14966 (const_string "fop")))
14967 (set_attr "fp_int_src" "true")
14968 (set_attr "ppro_uops" "many")
14969 (set_attr "mode" "SI")])
14971 (define_insn "*fop_df_4"
14972 [(set (match_operand:DF 0 "register_operand" "=f,f")
14973 (match_operator:DF 3 "binary_fp_operator"
14974 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14975 (match_operand:DF 2 "register_operand" "0,f")]))]
14976 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14977 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14978 "* return output_387_binary_op (insn, operands);"
14979 [(set (attr "type")
14980 (cond [(match_operand:DF 3 "mult_operator" "")
14981 (const_string "fmul")
14982 (match_operand:DF 3 "div_operator" "")
14983 (const_string "fdiv")
14985 (const_string "fop")))
14986 (set_attr "mode" "SF")])
14988 (define_insn "*fop_df_5"
14989 [(set (match_operand:DF 0 "register_operand" "=f,f")
14990 (match_operator:DF 3 "binary_fp_operator"
14991 [(match_operand:DF 1 "register_operand" "0,f")
14993 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14994 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14995 "* return output_387_binary_op (insn, operands);"
14996 [(set (attr "type")
14997 (cond [(match_operand:DF 3 "mult_operator" "")
14998 (const_string "fmul")
14999 (match_operand:DF 3 "div_operator" "")
15000 (const_string "fdiv")
15002 (const_string "fop")))
15003 (set_attr "mode" "SF")])
15005 (define_insn "*fop_df_6"
15006 [(set (match_operand:DF 0 "register_operand" "=f,f")
15007 (match_operator:DF 3 "binary_fp_operator"
15009 (match_operand:SF 1 "register_operand" "0,f"))
15011 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
15012 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15013 "* return output_387_binary_op (insn, operands);"
15014 [(set (attr "type")
15015 (cond [(match_operand:DF 3 "mult_operator" "")
15016 (const_string "fmul")
15017 (match_operand:DF 3 "div_operator" "")
15018 (const_string "fdiv")
15020 (const_string "fop")))
15021 (set_attr "mode" "SF")])
15023 (define_insn "*fop_xf_1"
15024 [(set (match_operand:XF 0 "register_operand" "=f,f")
15025 (match_operator:XF 3 "binary_fp_operator"
15026 [(match_operand:XF 1 "register_operand" "0,f")
15027 (match_operand:XF 2 "register_operand" "f,0")]))]
15028 "!TARGET_64BIT && TARGET_80387
15029 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
15030 "* return output_387_binary_op (insn, operands);"
15031 [(set (attr "type")
15032 (cond [(match_operand:XF 3 "mult_operator" "")
15033 (const_string "fmul")
15034 (match_operand:XF 3 "div_operator" "")
15035 (const_string "fdiv")
15037 (const_string "fop")))
15038 (set_attr "mode" "XF")])
15040 (define_insn "*fop_tf_1"
15041 [(set (match_operand:TF 0 "register_operand" "=f,f")
15042 (match_operator:TF 3 "binary_fp_operator"
15043 [(match_operand:TF 1 "register_operand" "0,f")
15044 (match_operand:TF 2 "register_operand" "f,0")]))]
15046 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
15047 "* return output_387_binary_op (insn, operands);"
15048 [(set (attr "type")
15049 (cond [(match_operand:TF 3 "mult_operator" "")
15050 (const_string "fmul")
15051 (match_operand:TF 3 "div_operator" "")
15052 (const_string "fdiv")
15054 (const_string "fop")))
15055 (set_attr "mode" "XF")])
15057 (define_insn "*fop_xf_2"
15058 [(set (match_operand:XF 0 "register_operand" "=f,f")
15059 (match_operator:XF 3 "binary_fp_operator"
15060 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15061 (match_operand:XF 2 "register_operand" "0,0")]))]
15062 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
15063 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15064 [(set (attr "type")
15065 (cond [(match_operand:XF 3 "mult_operator" "")
15066 (const_string "fmul")
15067 (match_operand:XF 3 "div_operator" "")
15068 (const_string "fdiv")
15070 (const_string "fop")))
15071 (set_attr "fp_int_src" "true")
15072 (set_attr "mode" "SI")
15073 (set_attr "ppro_uops" "many")])
15075 (define_insn "*fop_tf_2"
15076 [(set (match_operand:TF 0 "register_operand" "=f,f")
15077 (match_operator:TF 3 "binary_fp_operator"
15078 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15079 (match_operand:TF 2 "register_operand" "0,0")]))]
15080 "TARGET_80387 && TARGET_USE_FIOP"
15081 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15082 [(set (attr "type")
15083 (cond [(match_operand:TF 3 "mult_operator" "")
15084 (const_string "fmul")
15085 (match_operand:TF 3 "div_operator" "")
15086 (const_string "fdiv")
15088 (const_string "fop")))
15089 (set_attr "fp_int_src" "true")
15090 (set_attr "mode" "SI")
15091 (set_attr "ppro_uops" "many")])
15093 (define_insn "*fop_xf_3"
15094 [(set (match_operand:XF 0 "register_operand" "=f,f")
15095 (match_operator:XF 3 "binary_fp_operator"
15096 [(match_operand:XF 1 "register_operand" "0,0")
15097 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15098 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
15099 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15100 [(set (attr "type")
15101 (cond [(match_operand:XF 3 "mult_operator" "")
15102 (const_string "fmul")
15103 (match_operand:XF 3 "div_operator" "")
15104 (const_string "fdiv")
15106 (const_string "fop")))
15107 (set_attr "fp_int_src" "true")
15108 (set_attr "mode" "SI")
15109 (set_attr "ppro_uops" "many")])
15111 (define_insn "*fop_tf_3"
15112 [(set (match_operand:TF 0 "register_operand" "=f,f")
15113 (match_operator:TF 3 "binary_fp_operator"
15114 [(match_operand:TF 1 "register_operand" "0,0")
15115 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15116 "TARGET_80387 && TARGET_USE_FIOP"
15117 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15118 [(set (attr "type")
15119 (cond [(match_operand:TF 3 "mult_operator" "")
15120 (const_string "fmul")
15121 (match_operand:TF 3 "div_operator" "")
15122 (const_string "fdiv")
15124 (const_string "fop")))
15125 (set_attr "fp_int_src" "true")
15126 (set_attr "mode" "SI")
15127 (set_attr "ppro_uops" "many")])
15129 (define_insn "*fop_xf_4"
15130 [(set (match_operand:XF 0 "register_operand" "=f,f")
15131 (match_operator:XF 3 "binary_fp_operator"
15132 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
15133 (match_operand:XF 2 "register_operand" "0,f")]))]
15134 "!TARGET_64BIT && TARGET_80387"
15135 "* return output_387_binary_op (insn, operands);"
15136 [(set (attr "type")
15137 (cond [(match_operand:XF 3 "mult_operator" "")
15138 (const_string "fmul")
15139 (match_operand:XF 3 "div_operator" "")
15140 (const_string "fdiv")
15142 (const_string "fop")))
15143 (set_attr "mode" "SF")])
15145 (define_insn "*fop_tf_4"
15146 [(set (match_operand:TF 0 "register_operand" "=f,f")
15147 (match_operator:TF 3 "binary_fp_operator"
15148 [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
15149 (match_operand:TF 2 "register_operand" "0,f")]))]
15151 "* return output_387_binary_op (insn, operands);"
15152 [(set (attr "type")
15153 (cond [(match_operand:TF 3 "mult_operator" "")
15154 (const_string "fmul")
15155 (match_operand:TF 3 "div_operator" "")
15156 (const_string "fdiv")
15158 (const_string "fop")))
15159 (set_attr "mode" "SF")])
15161 (define_insn "*fop_xf_5"
15162 [(set (match_operand:XF 0 "register_operand" "=f,f")
15163 (match_operator:XF 3 "binary_fp_operator"
15164 [(match_operand:XF 1 "register_operand" "0,f")
15166 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15167 "!TARGET_64BIT && TARGET_80387"
15168 "* return output_387_binary_op (insn, operands);"
15169 [(set (attr "type")
15170 (cond [(match_operand:XF 3 "mult_operator" "")
15171 (const_string "fmul")
15172 (match_operand:XF 3 "div_operator" "")
15173 (const_string "fdiv")
15175 (const_string "fop")))
15176 (set_attr "mode" "SF")])
15178 (define_insn "*fop_tf_5"
15179 [(set (match_operand:TF 0 "register_operand" "=f,f")
15180 (match_operator:TF 3 "binary_fp_operator"
15181 [(match_operand:TF 1 "register_operand" "0,f")
15183 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15185 "* return output_387_binary_op (insn, operands);"
15186 [(set (attr "type")
15187 (cond [(match_operand:TF 3 "mult_operator" "")
15188 (const_string "fmul")
15189 (match_operand:TF 3 "div_operator" "")
15190 (const_string "fdiv")
15192 (const_string "fop")))
15193 (set_attr "mode" "SF")])
15195 (define_insn "*fop_xf_6"
15196 [(set (match_operand:XF 0 "register_operand" "=f,f")
15197 (match_operator:XF 3 "binary_fp_operator"
15199 (match_operand 1 "register_operand" "0,f"))
15201 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15202 "!TARGET_64BIT && TARGET_80387"
15203 "* return output_387_binary_op (insn, operands);"
15204 [(set (attr "type")
15205 (cond [(match_operand:XF 3 "mult_operator" "")
15206 (const_string "fmul")
15207 (match_operand:XF 3 "div_operator" "")
15208 (const_string "fdiv")
15210 (const_string "fop")))
15211 (set_attr "mode" "SF")])
15213 (define_insn "*fop_tf_6"
15214 [(set (match_operand:TF 0 "register_operand" "=f,f")
15215 (match_operator:TF 3 "binary_fp_operator"
15217 (match_operand 1 "register_operand" "0,f"))
15219 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15221 "* return output_387_binary_op (insn, operands);"
15222 [(set (attr "type")
15223 (cond [(match_operand:TF 3 "mult_operator" "")
15224 (const_string "fmul")
15225 (match_operand:TF 3 "div_operator" "")
15226 (const_string "fdiv")
15228 (const_string "fop")))
15229 (set_attr "mode" "SF")])
15232 [(set (match_operand 0 "register_operand" "")
15233 (match_operator 3 "binary_fp_operator"
15234 [(float (match_operand:SI 1 "register_operand" ""))
15235 (match_operand 2 "register_operand" "")]))]
15236 "TARGET_80387 && reload_completed
15237 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15240 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
15241 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15242 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15243 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15244 GET_MODE (operands[3]),
15247 ix86_free_from_memory (GET_MODE (operands[1]));
15252 [(set (match_operand 0 "register_operand" "")
15253 (match_operator 3 "binary_fp_operator"
15254 [(match_operand 1 "register_operand" "")
15255 (float (match_operand:SI 2 "register_operand" ""))]))]
15256 "TARGET_80387 && reload_completed
15257 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15260 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
15261 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15262 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15263 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15264 GET_MODE (operands[3]),
15267 ix86_free_from_memory (GET_MODE (operands[2]));
15271 ;; FPU special functions.
15273 (define_expand "sqrtsf2"
15274 [(set (match_operand:SF 0 "register_operand" "")
15275 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
15276 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
15278 if (!TARGET_SSE_MATH)
15279 operands[1] = force_reg (SFmode, operands[1]);
15282 (define_insn "sqrtsf2_1"
15283 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
15284 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
15285 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15286 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15289 sqrtss\t{%1, %0|%0, %1}"
15290 [(set_attr "type" "fpspc,sse")
15291 (set_attr "mode" "SF,SF")
15292 (set_attr "athlon_decode" "direct,*")])
15294 (define_insn "sqrtsf2_1_sse_only"
15295 [(set (match_operand:SF 0 "register_operand" "=x")
15296 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
15297 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15298 "sqrtss\t{%1, %0|%0, %1}"
15299 [(set_attr "type" "sse")
15300 (set_attr "mode" "SF")
15301 (set_attr "athlon_decode" "*")])
15303 (define_insn "sqrtsf2_i387"
15304 [(set (match_operand:SF 0 "register_operand" "=f")
15305 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
15306 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15307 && !TARGET_SSE_MATH"
15309 [(set_attr "type" "fpspc")
15310 (set_attr "mode" "SF")
15311 (set_attr "athlon_decode" "direct")])
15313 (define_expand "sqrtdf2"
15314 [(set (match_operand:DF 0 "register_operand" "")
15315 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
15316 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
15317 || (TARGET_SSE2 && TARGET_SSE_MATH)"
15319 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
15320 operands[1] = force_reg (DFmode, operands[1]);
15323 (define_insn "sqrtdf2_1"
15324 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
15325 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
15326 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15327 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15330 sqrtsd\t{%1, %0|%0, %1}"
15331 [(set_attr "type" "fpspc,sse")
15332 (set_attr "mode" "DF,DF")
15333 (set_attr "athlon_decode" "direct,*")])
15335 (define_insn "sqrtdf2_1_sse_only"
15336 [(set (match_operand:DF 0 "register_operand" "=Y")
15337 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
15338 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15339 "sqrtsd\t{%1, %0|%0, %1}"
15340 [(set_attr "type" "sse")
15341 (set_attr "mode" "DF")
15342 (set_attr "athlon_decode" "*")])
15344 (define_insn "sqrtdf2_i387"
15345 [(set (match_operand:DF 0 "register_operand" "=f")
15346 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
15347 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15348 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
15350 [(set_attr "type" "fpspc")
15351 (set_attr "mode" "DF")
15352 (set_attr "athlon_decode" "direct")])
15354 (define_insn "*sqrtextendsfdf2"
15355 [(set (match_operand:DF 0 "register_operand" "=f")
15356 (sqrt:DF (float_extend:DF
15357 (match_operand:SF 1 "register_operand" "0"))))]
15358 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15359 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15361 [(set_attr "type" "fpspc")
15362 (set_attr "mode" "DF")
15363 (set_attr "athlon_decode" "direct")])
15365 (define_insn "sqrtxf2"
15366 [(set (match_operand:XF 0 "register_operand" "=f")
15367 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
15368 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15369 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15371 [(set_attr "type" "fpspc")
15372 (set_attr "mode" "XF")
15373 (set_attr "athlon_decode" "direct")])
15375 (define_insn "sqrttf2"
15376 [(set (match_operand:TF 0 "register_operand" "=f")
15377 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
15378 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15379 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15381 [(set_attr "type" "fpspc")
15382 (set_attr "mode" "XF")
15383 (set_attr "athlon_decode" "direct")])
15385 (define_insn "*sqrtextenddfxf2"
15386 [(set (match_operand:XF 0 "register_operand" "=f")
15387 (sqrt:XF (float_extend:XF
15388 (match_operand:DF 1 "register_operand" "0"))))]
15389 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15391 [(set_attr "type" "fpspc")
15392 (set_attr "mode" "XF")
15393 (set_attr "athlon_decode" "direct")])
15395 (define_insn "*sqrtextenddftf2"
15396 [(set (match_operand:TF 0 "register_operand" "=f")
15397 (sqrt:TF (float_extend:TF
15398 (match_operand:DF 1 "register_operand" "0"))))]
15399 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15401 [(set_attr "type" "fpspc")
15402 (set_attr "mode" "XF")
15403 (set_attr "athlon_decode" "direct")])
15405 (define_insn "*sqrtextendsfxf2"
15406 [(set (match_operand:XF 0 "register_operand" "=f")
15407 (sqrt:XF (float_extend:XF
15408 (match_operand:SF 1 "register_operand" "0"))))]
15409 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15411 [(set_attr "type" "fpspc")
15412 (set_attr "mode" "XF")
15413 (set_attr "athlon_decode" "direct")])
15415 (define_insn "*sqrtextendsftf2"
15416 [(set (match_operand:TF 0 "register_operand" "=f")
15417 (sqrt:TF (float_extend:TF
15418 (match_operand:SF 1 "register_operand" "0"))))]
15419 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15421 [(set_attr "type" "fpspc")
15422 (set_attr "mode" "XF")
15423 (set_attr "athlon_decode" "direct")])
15425 (define_insn "sindf2"
15426 [(set (match_operand:DF 0 "register_operand" "=f")
15427 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15428 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15429 && flag_unsafe_math_optimizations"
15431 [(set_attr "type" "fpspc")
15432 (set_attr "mode" "DF")])
15434 (define_insn "sinsf2"
15435 [(set (match_operand:SF 0 "register_operand" "=f")
15436 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15437 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15438 && flag_unsafe_math_optimizations"
15440 [(set_attr "type" "fpspc")
15441 (set_attr "mode" "SF")])
15443 (define_insn "*sinextendsfdf2"
15444 [(set (match_operand:DF 0 "register_operand" "=f")
15445 (unspec:DF [(float_extend:DF
15446 (match_operand:SF 1 "register_operand" "0"))]
15448 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15449 && flag_unsafe_math_optimizations"
15451 [(set_attr "type" "fpspc")
15452 (set_attr "mode" "DF")])
15454 (define_insn "sinxf2"
15455 [(set (match_operand:XF 0 "register_operand" "=f")
15456 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15457 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15458 && flag_unsafe_math_optimizations"
15460 [(set_attr "type" "fpspc")
15461 (set_attr "mode" "XF")])
15463 (define_insn "sintf2"
15464 [(set (match_operand:TF 0 "register_operand" "=f")
15465 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
15466 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15467 && flag_unsafe_math_optimizations"
15469 [(set_attr "type" "fpspc")
15470 (set_attr "mode" "XF")])
15472 (define_insn "cosdf2"
15473 [(set (match_operand:DF 0 "register_operand" "=f")
15474 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15475 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15476 && flag_unsafe_math_optimizations"
15478 [(set_attr "type" "fpspc")
15479 (set_attr "mode" "DF")])
15481 (define_insn "cossf2"
15482 [(set (match_operand:SF 0 "register_operand" "=f")
15483 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15484 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15485 && flag_unsafe_math_optimizations"
15487 [(set_attr "type" "fpspc")
15488 (set_attr "mode" "SF")])
15490 (define_insn "*cosextendsfdf2"
15491 [(set (match_operand:DF 0 "register_operand" "=f")
15492 (unspec:DF [(float_extend:DF
15493 (match_operand:SF 1 "register_operand" "0"))]
15495 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15496 && flag_unsafe_math_optimizations"
15498 [(set_attr "type" "fpspc")
15499 (set_attr "mode" "DF")])
15501 (define_insn "cosxf2"
15502 [(set (match_operand:XF 0 "register_operand" "=f")
15503 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15504 "!TARGET_64BIT && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15505 && flag_unsafe_math_optimizations"
15507 [(set_attr "type" "fpspc")
15508 (set_attr "mode" "XF")])
15510 (define_insn "costf2"
15511 [(set (match_operand:TF 0 "register_operand" "=f")
15512 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
15513 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15514 && flag_unsafe_math_optimizations"
15516 [(set_attr "type" "fpspc")
15517 (set_attr "mode" "XF")])
15519 (define_insn "atan2df3"
15520 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15521 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15522 (match_operand:DF 1 "register_operand" "u")]
15524 (clobber (match_dup 1))])]
15525 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15526 && flag_unsafe_math_optimizations"
15528 [(set_attr "type" "fpspc")
15529 (set_attr "mode" "DF")])
15531 (define_insn "atan2sf3"
15532 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15533 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15534 (match_operand:SF 1 "register_operand" "u")]
15536 (clobber (match_dup 1))])]
15537 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15538 && flag_unsafe_math_optimizations"
15540 [(set_attr "type" "fpspc")
15541 (set_attr "mode" "SF")])
15543 (define_insn "atan2xf3"
15544 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15545 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15546 (match_operand:XF 1 "register_operand" "u")]
15548 (clobber (match_dup 1))])]
15549 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15550 && flag_unsafe_math_optimizations"
15552 [(set_attr "type" "fpspc")
15553 (set_attr "mode" "XF")])
15555 (define_insn "atan2tf3"
15556 [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
15557 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15558 (match_operand:TF 1 "register_operand" "u")]
15560 (clobber (match_dup 1))])]
15561 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15562 && flag_unsafe_math_optimizations"
15564 [(set_attr "type" "fpspc")
15565 (set_attr "mode" "XF")])
15567 (define_insn "*fyl2x_sfxf3"
15568 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15569 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15570 (match_operand:XF 1 "register_operand" "u")]
15572 (clobber (match_dup 1))])]
15573 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15574 && flag_unsafe_math_optimizations"
15576 [(set_attr "type" "fpspc")
15577 (set_attr "mode" "SF")])
15579 (define_insn "*fyl2x_dfxf3"
15580 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15581 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15582 (match_operand:XF 1 "register_operand" "u")]
15584 (clobber (match_dup 1))])]
15585 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15586 && flag_unsafe_math_optimizations"
15588 [(set_attr "type" "fpspc")
15589 (set_attr "mode" "DF")])
15591 (define_insn "*fyl2x_xf3"
15592 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15593 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15594 (match_operand:XF 1 "register_operand" "u")]
15596 (clobber (match_dup 1))])]
15597 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15598 && flag_unsafe_math_optimizations"
15600 [(set_attr "type" "fpspc")
15601 (set_attr "mode" "XF")])
15603 (define_insn "*fyl2x_tfxf3"
15604 [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
15605 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15606 (match_operand:XF 1 "register_operand" "u")]
15608 (clobber (match_dup 1))])]
15609 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15610 && flag_unsafe_math_optimizations"
15612 [(set_attr "type" "fpspc")
15613 (set_attr "mode" "XF")])
15615 (define_expand "logsf2"
15616 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15617 (unspec:SF [(match_operand:SF 1 "register_operand" "")
15618 (match_dup 2)] UNSPEC_FYL2X))
15619 (clobber (match_dup 2))])]
15620 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15621 && flag_unsafe_math_optimizations"
15625 operands[2] = gen_reg_rtx (XFmode);
15626 temp = standard_80387_constant_rtx (4); /* fldln2 */
15627 emit_move_insn (operands[2], temp);
15630 (define_expand "logdf2"
15631 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15632 (unspec:DF [(match_operand:DF 1 "register_operand" "")
15633 (match_dup 2)] UNSPEC_FYL2X))
15634 (clobber (match_dup 2))])]
15635 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15636 && flag_unsafe_math_optimizations"
15640 operands[2] = gen_reg_rtx (XFmode);
15641 temp = standard_80387_constant_rtx (4); /* fldln2 */
15642 emit_move_insn (operands[2], temp);
15645 (define_expand "logxf2"
15646 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15647 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15648 (match_dup 2)] UNSPEC_FYL2X))
15649 (clobber (match_dup 2))])]
15650 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15651 && flag_unsafe_math_optimizations"
15655 operands[2] = gen_reg_rtx (XFmode);
15656 temp = standard_80387_constant_rtx (4); /* fldln2 */
15657 emit_move_insn (operands[2], temp);
15660 (define_expand "logtf2"
15661 [(parallel [(set (match_operand:TF 0 "register_operand" "")
15662 (unspec:TF [(match_operand:TF 1 "register_operand" "")
15663 (match_dup 2)] UNSPEC_FYL2X))
15664 (clobber (match_dup 2))])]
15665 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15666 && flag_unsafe_math_optimizations"
15670 operands[2] = gen_reg_rtx (XFmode);
15671 temp = standard_80387_constant_rtx (4); /* fldln2 */
15672 emit_move_insn (operands[2], temp);
15675 ;; Block operation instructions
15678 [(set (reg:SI 19) (const_int 0))]
15681 [(set_attr "type" "cld")])
15683 (define_expand "movstrsi"
15684 [(use (match_operand:BLK 0 "memory_operand" ""))
15685 (use (match_operand:BLK 1 "memory_operand" ""))
15686 (use (match_operand:SI 2 "nonmemory_operand" ""))
15687 (use (match_operand:SI 3 "const_int_operand" ""))]
15690 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15696 (define_expand "movstrdi"
15697 [(use (match_operand:BLK 0 "memory_operand" ""))
15698 (use (match_operand:BLK 1 "memory_operand" ""))
15699 (use (match_operand:DI 2 "nonmemory_operand" ""))
15700 (use (match_operand:DI 3 "const_int_operand" ""))]
15703 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15709 ;; Most CPUs don't like single string operations
15710 ;; Handle this case here to simplify previous expander.
15712 (define_expand "strmovdi_rex64"
15713 [(set (match_dup 2)
15714 (mem:DI (match_operand:DI 1 "register_operand" "")))
15715 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
15717 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15718 (clobber (reg:CC 17))])
15719 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
15720 (clobber (reg:CC 17))])]
15723 if (TARGET_SINGLE_STRINGOP || optimize_size)
15725 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
15730 operands[2] = gen_reg_rtx (DImode);
15734 (define_expand "strmovsi"
15735 [(set (match_dup 2)
15736 (mem:SI (match_operand:SI 1 "register_operand" "")))
15737 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
15739 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15740 (clobber (reg:CC 17))])
15741 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
15742 (clobber (reg:CC 17))])]
15747 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
15750 if (TARGET_SINGLE_STRINGOP || optimize_size)
15752 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
15757 operands[2] = gen_reg_rtx (SImode);
15760 (define_expand "strmovsi_rex64"
15761 [(set (match_dup 2)
15762 (mem:SI (match_operand:DI 1 "register_operand" "")))
15763 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
15765 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15766 (clobber (reg:CC 17))])
15767 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
15768 (clobber (reg:CC 17))])]
15771 if (TARGET_SINGLE_STRINGOP || optimize_size)
15773 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
15778 operands[2] = gen_reg_rtx (SImode);
15781 (define_expand "strmovhi"
15782 [(set (match_dup 2)
15783 (mem:HI (match_operand:SI 1 "register_operand" "")))
15784 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
15786 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15787 (clobber (reg:CC 17))])
15788 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
15789 (clobber (reg:CC 17))])]
15794 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
15797 if (TARGET_SINGLE_STRINGOP || optimize_size)
15799 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
15804 operands[2] = gen_reg_rtx (HImode);
15807 (define_expand "strmovhi_rex64"
15808 [(set (match_dup 2)
15809 (mem:HI (match_operand:DI 1 "register_operand" "")))
15810 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
15812 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15813 (clobber (reg:CC 17))])
15814 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
15815 (clobber (reg:CC 17))])]
15818 if (TARGET_SINGLE_STRINGOP || optimize_size)
15820 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
15825 operands[2] = gen_reg_rtx (HImode);
15828 (define_expand "strmovqi"
15829 [(set (match_dup 2)
15830 (mem:QI (match_operand:SI 1 "register_operand" "")))
15831 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
15833 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15834 (clobber (reg:CC 17))])
15835 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
15836 (clobber (reg:CC 17))])]
15841 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
15844 if (TARGET_SINGLE_STRINGOP || optimize_size)
15846 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
15851 operands[2] = gen_reg_rtx (QImode);
15854 (define_expand "strmovqi_rex64"
15855 [(set (match_dup 2)
15856 (mem:QI (match_operand:DI 1 "register_operand" "")))
15857 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
15859 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15860 (clobber (reg:CC 17))])
15861 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
15862 (clobber (reg:CC 17))])]
15865 if (TARGET_SINGLE_STRINGOP || optimize_size)
15867 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
15872 operands[2] = gen_reg_rtx (QImode);
15875 (define_insn "strmovdi_rex_1"
15876 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15877 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15878 (set (match_operand:DI 0 "register_operand" "=D")
15879 (plus:DI (match_dup 2)
15881 (set (match_operand:DI 1 "register_operand" "=S")
15882 (plus:DI (match_dup 3)
15885 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15887 [(set_attr "type" "str")
15888 (set_attr "mode" "DI")
15889 (set_attr "memory" "both")])
15891 (define_insn "strmovsi_1"
15892 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15893 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15894 (set (match_operand:SI 0 "register_operand" "=D")
15895 (plus:SI (match_dup 2)
15897 (set (match_operand:SI 1 "register_operand" "=S")
15898 (plus:SI (match_dup 3)
15901 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15903 [(set_attr "type" "str")
15904 (set_attr "mode" "SI")
15905 (set_attr "memory" "both")])
15907 (define_insn "strmovsi_rex_1"
15908 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15909 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15910 (set (match_operand:DI 0 "register_operand" "=D")
15911 (plus:DI (match_dup 2)
15913 (set (match_operand:DI 1 "register_operand" "=S")
15914 (plus:DI (match_dup 3)
15917 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15919 [(set_attr "type" "str")
15920 (set_attr "mode" "SI")
15921 (set_attr "memory" "both")])
15923 (define_insn "strmovhi_1"
15924 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15925 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15926 (set (match_operand:SI 0 "register_operand" "=D")
15927 (plus:SI (match_dup 2)
15929 (set (match_operand:SI 1 "register_operand" "=S")
15930 (plus:SI (match_dup 3)
15933 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15935 [(set_attr "type" "str")
15936 (set_attr "memory" "both")
15937 (set_attr "mode" "HI")])
15939 (define_insn "strmovhi_rex_1"
15940 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15941 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15942 (set (match_operand:DI 0 "register_operand" "=D")
15943 (plus:DI (match_dup 2)
15945 (set (match_operand:DI 1 "register_operand" "=S")
15946 (plus:DI (match_dup 3)
15949 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15951 [(set_attr "type" "str")
15952 (set_attr "memory" "both")
15953 (set_attr "mode" "HI")])
15955 (define_insn "strmovqi_1"
15956 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15957 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15958 (set (match_operand:SI 0 "register_operand" "=D")
15959 (plus:SI (match_dup 2)
15961 (set (match_operand:SI 1 "register_operand" "=S")
15962 (plus:SI (match_dup 3)
15965 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15967 [(set_attr "type" "str")
15968 (set_attr "memory" "both")
15969 (set_attr "mode" "QI")])
15971 (define_insn "strmovqi_rex_1"
15972 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15973 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15974 (set (match_operand:DI 0 "register_operand" "=D")
15975 (plus:DI (match_dup 2)
15977 (set (match_operand:DI 1 "register_operand" "=S")
15978 (plus:DI (match_dup 3)
15981 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15983 [(set_attr "type" "str")
15984 (set_attr "memory" "both")
15985 (set_attr "mode" "QI")])
15987 (define_insn "rep_movdi_rex64"
15988 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15989 (set (match_operand:DI 0 "register_operand" "=D")
15990 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15992 (match_operand:DI 3 "register_operand" "0")))
15993 (set (match_operand:DI 1 "register_operand" "=S")
15994 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15995 (match_operand:DI 4 "register_operand" "1")))
15996 (set (mem:BLK (match_dup 3))
15997 (mem:BLK (match_dup 4)))
15998 (use (match_dup 5))
16001 "{rep\;movsq|rep movsq}"
16002 [(set_attr "type" "str")
16003 (set_attr "prefix_rep" "1")
16004 (set_attr "memory" "both")
16005 (set_attr "mode" "DI")])
16007 (define_insn "rep_movsi"
16008 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16009 (set (match_operand:SI 0 "register_operand" "=D")
16010 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16012 (match_operand:SI 3 "register_operand" "0")))
16013 (set (match_operand:SI 1 "register_operand" "=S")
16014 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16015 (match_operand:SI 4 "register_operand" "1")))
16016 (set (mem:BLK (match_dup 3))
16017 (mem:BLK (match_dup 4)))
16018 (use (match_dup 5))
16021 "{rep\;movsl|rep movsd}"
16022 [(set_attr "type" "str")
16023 (set_attr "prefix_rep" "1")
16024 (set_attr "memory" "both")
16025 (set_attr "mode" "SI")])
16027 (define_insn "rep_movsi_rex64"
16028 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16029 (set (match_operand:DI 0 "register_operand" "=D")
16030 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16032 (match_operand:DI 3 "register_operand" "0")))
16033 (set (match_operand:DI 1 "register_operand" "=S")
16034 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16035 (match_operand:DI 4 "register_operand" "1")))
16036 (set (mem:BLK (match_dup 3))
16037 (mem:BLK (match_dup 4)))
16038 (use (match_dup 5))
16041 "{rep\;movsl|rep movsd}"
16042 [(set_attr "type" "str")
16043 (set_attr "prefix_rep" "1")
16044 (set_attr "memory" "both")
16045 (set_attr "mode" "SI")])
16047 (define_insn "rep_movqi"
16048 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16049 (set (match_operand:SI 0 "register_operand" "=D")
16050 (plus:SI (match_operand:SI 3 "register_operand" "0")
16051 (match_operand:SI 5 "register_operand" "2")))
16052 (set (match_operand:SI 1 "register_operand" "=S")
16053 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
16054 (set (mem:BLK (match_dup 3))
16055 (mem:BLK (match_dup 4)))
16056 (use (match_dup 5))
16059 "{rep\;movsb|rep movsb}"
16060 [(set_attr "type" "str")
16061 (set_attr "prefix_rep" "1")
16062 (set_attr "memory" "both")
16063 (set_attr "mode" "SI")])
16065 (define_insn "rep_movqi_rex64"
16066 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16067 (set (match_operand:DI 0 "register_operand" "=D")
16068 (plus:DI (match_operand:DI 3 "register_operand" "0")
16069 (match_operand:DI 5 "register_operand" "2")))
16070 (set (match_operand:DI 1 "register_operand" "=S")
16071 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
16072 (set (mem:BLK (match_dup 3))
16073 (mem:BLK (match_dup 4)))
16074 (use (match_dup 5))
16077 "{rep\;movsb|rep movsb}"
16078 [(set_attr "type" "str")
16079 (set_attr "prefix_rep" "1")
16080 (set_attr "memory" "both")
16081 (set_attr "mode" "SI")])
16083 (define_expand "clrstrsi"
16084 [(use (match_operand:BLK 0 "memory_operand" ""))
16085 (use (match_operand:SI 1 "nonmemory_operand" ""))
16086 (use (match_operand 2 "const_int_operand" ""))]
16089 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
16095 (define_expand "clrstrdi"
16096 [(use (match_operand:BLK 0 "memory_operand" ""))
16097 (use (match_operand:DI 1 "nonmemory_operand" ""))
16098 (use (match_operand 2 "const_int_operand" ""))]
16101 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
16107 ;; Most CPUs don't like single string operations
16108 ;; Handle this case here to simplify previous expander.
16110 (define_expand "strsetdi_rex64"
16111 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
16112 (match_operand:DI 1 "register_operand" ""))
16113 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
16114 (clobber (reg:CC 17))])]
16117 if (TARGET_SINGLE_STRINGOP || optimize_size)
16119 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
16124 (define_expand "strsetsi"
16125 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
16126 (match_operand:SI 1 "register_operand" ""))
16127 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
16128 (clobber (reg:CC 17))])]
16133 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
16136 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16138 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
16143 (define_expand "strsetsi_rex64"
16144 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
16145 (match_operand:SI 1 "register_operand" ""))
16146 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
16147 (clobber (reg:CC 17))])]
16150 if (TARGET_SINGLE_STRINGOP || optimize_size)
16152 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
16157 (define_expand "strsethi"
16158 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
16159 (match_operand:HI 1 "register_operand" ""))
16160 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
16161 (clobber (reg:CC 17))])]
16166 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
16169 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16171 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
16176 (define_expand "strsethi_rex64"
16177 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
16178 (match_operand:HI 1 "register_operand" ""))
16179 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
16180 (clobber (reg:CC 17))])]
16183 if (TARGET_SINGLE_STRINGOP || optimize_size)
16185 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
16190 (define_expand "strsetqi"
16191 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
16192 (match_operand:QI 1 "register_operand" ""))
16193 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
16194 (clobber (reg:CC 17))])]
16199 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
16202 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16204 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
16209 (define_expand "strsetqi_rex64"
16210 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
16211 (match_operand:QI 1 "register_operand" ""))
16212 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
16213 (clobber (reg:CC 17))])]
16216 if (TARGET_SINGLE_STRINGOP || optimize_size)
16218 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
16223 (define_insn "strsetdi_rex_1"
16224 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16225 (match_operand:SI 2 "register_operand" "a"))
16226 (set (match_operand:DI 0 "register_operand" "=D")
16227 (plus:DI (match_dup 1)
16230 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16232 [(set_attr "type" "str")
16233 (set_attr "memory" "store")
16234 (set_attr "mode" "DI")])
16236 (define_insn "strsetsi_1"
16237 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16238 (match_operand:SI 2 "register_operand" "a"))
16239 (set (match_operand:SI 0 "register_operand" "=D")
16240 (plus:SI (match_dup 1)
16243 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16245 [(set_attr "type" "str")
16246 (set_attr "memory" "store")
16247 (set_attr "mode" "SI")])
16249 (define_insn "strsetsi_rex_1"
16250 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16251 (match_operand:SI 2 "register_operand" "a"))
16252 (set (match_operand:DI 0 "register_operand" "=D")
16253 (plus:DI (match_dup 1)
16256 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16258 [(set_attr "type" "str")
16259 (set_attr "memory" "store")
16260 (set_attr "mode" "SI")])
16262 (define_insn "strsethi_1"
16263 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16264 (match_operand:HI 2 "register_operand" "a"))
16265 (set (match_operand:SI 0 "register_operand" "=D")
16266 (plus:SI (match_dup 1)
16269 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16271 [(set_attr "type" "str")
16272 (set_attr "memory" "store")
16273 (set_attr "mode" "HI")])
16275 (define_insn "strsethi_rex_1"
16276 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16277 (match_operand:HI 2 "register_operand" "a"))
16278 (set (match_operand:DI 0 "register_operand" "=D")
16279 (plus:DI (match_dup 1)
16282 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16284 [(set_attr "type" "str")
16285 (set_attr "memory" "store")
16286 (set_attr "mode" "HI")])
16288 (define_insn "strsetqi_1"
16289 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16290 (match_operand:QI 2 "register_operand" "a"))
16291 (set (match_operand:SI 0 "register_operand" "=D")
16292 (plus:SI (match_dup 1)
16295 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16297 [(set_attr "type" "str")
16298 (set_attr "memory" "store")
16299 (set_attr "mode" "QI")])
16301 (define_insn "strsetqi_rex_1"
16302 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16303 (match_operand:QI 2 "register_operand" "a"))
16304 (set (match_operand:DI 0 "register_operand" "=D")
16305 (plus:DI (match_dup 1)
16308 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16310 [(set_attr "type" "str")
16311 (set_attr "memory" "store")
16312 (set_attr "mode" "QI")])
16314 (define_insn "rep_stosdi_rex64"
16315 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16316 (set (match_operand:DI 0 "register_operand" "=D")
16317 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16319 (match_operand:DI 3 "register_operand" "0")))
16320 (set (mem:BLK (match_dup 3))
16322 (use (match_operand:DI 2 "register_operand" "a"))
16323 (use (match_dup 4))
16326 "{rep\;stosq|rep stosq}"
16327 [(set_attr "type" "str")
16328 (set_attr "prefix_rep" "1")
16329 (set_attr "memory" "store")
16330 (set_attr "mode" "DI")])
16332 (define_insn "rep_stossi"
16333 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16334 (set (match_operand:SI 0 "register_operand" "=D")
16335 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16337 (match_operand:SI 3 "register_operand" "0")))
16338 (set (mem:BLK (match_dup 3))
16340 (use (match_operand:SI 2 "register_operand" "a"))
16341 (use (match_dup 4))
16344 "{rep\;stosl|rep stosd}"
16345 [(set_attr "type" "str")
16346 (set_attr "prefix_rep" "1")
16347 (set_attr "memory" "store")
16348 (set_attr "mode" "SI")])
16350 (define_insn "rep_stossi_rex64"
16351 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16352 (set (match_operand:DI 0 "register_operand" "=D")
16353 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16355 (match_operand:DI 3 "register_operand" "0")))
16356 (set (mem:BLK (match_dup 3))
16358 (use (match_operand:SI 2 "register_operand" "a"))
16359 (use (match_dup 4))
16362 "{rep\;stosl|rep stosd}"
16363 [(set_attr "type" "str")
16364 (set_attr "prefix_rep" "1")
16365 (set_attr "memory" "store")
16366 (set_attr "mode" "SI")])
16368 (define_insn "rep_stosqi"
16369 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16370 (set (match_operand:SI 0 "register_operand" "=D")
16371 (plus:SI (match_operand:SI 3 "register_operand" "0")
16372 (match_operand:SI 4 "register_operand" "1")))
16373 (set (mem:BLK (match_dup 3))
16375 (use (match_operand:QI 2 "register_operand" "a"))
16376 (use (match_dup 4))
16379 "{rep\;stosb|rep stosb}"
16380 [(set_attr "type" "str")
16381 (set_attr "prefix_rep" "1")
16382 (set_attr "memory" "store")
16383 (set_attr "mode" "QI")])
16385 (define_insn "rep_stosqi_rex64"
16386 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16387 (set (match_operand:DI 0 "register_operand" "=D")
16388 (plus:DI (match_operand:DI 3 "register_operand" "0")
16389 (match_operand:DI 4 "register_operand" "1")))
16390 (set (mem:BLK (match_dup 3))
16392 (use (match_operand:QI 2 "register_operand" "a"))
16393 (use (match_dup 4))
16396 "{rep\;stosb|rep stosb}"
16397 [(set_attr "type" "str")
16398 (set_attr "prefix_rep" "1")
16399 (set_attr "memory" "store")
16400 (set_attr "mode" "QI")])
16402 (define_expand "cmpstrsi"
16403 [(set (match_operand:SI 0 "register_operand" "")
16404 (compare:SI (match_operand:BLK 1 "general_operand" "")
16405 (match_operand:BLK 2 "general_operand" "")))
16406 (use (match_operand 3 "general_operand" ""))
16407 (use (match_operand 4 "immediate_operand" ""))]
16410 rtx addr1, addr2, out, outlow, count, countreg, align;
16412 /* Can't use this if the user has appropriated esi or edi. */
16413 if (global_regs[4] || global_regs[5])
16417 if (GET_CODE (out) != REG)
16418 out = gen_reg_rtx (SImode);
16420 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
16421 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
16423 count = operands[3];
16424 countreg = ix86_zero_extend_to_Pmode (count);
16426 /* %%% Iff we are testing strict equality, we can use known alignment
16427 to good advantage. This may be possible with combine, particularly
16428 once cc0 is dead. */
16429 align = operands[4];
16431 emit_insn (gen_cld ());
16432 if (GET_CODE (count) == CONST_INT)
16434 if (INTVAL (count) == 0)
16436 emit_move_insn (operands[0], const0_rtx);
16440 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
16441 addr1, addr2, countreg));
16443 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
16444 addr1, addr2, countreg));
16450 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
16451 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
16452 addr1, addr2, countreg));
16456 emit_insn (gen_cmpsi_1 (countreg, countreg));
16457 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
16458 addr1, addr2, countreg));
16462 outlow = gen_lowpart (QImode, out);
16463 emit_insn (gen_cmpintqi (outlow));
16464 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
16466 if (operands[0] != out)
16467 emit_move_insn (operands[0], out);
16472 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
16474 (define_expand "cmpintqi"
16475 [(set (match_dup 1)
16476 (gtu:QI (reg:CC 17) (const_int 0)))
16478 (ltu:QI (reg:CC 17) (const_int 0)))
16479 (parallel [(set (match_operand:QI 0 "register_operand" "")
16480 (minus:QI (match_dup 1)
16482 (clobber (reg:CC 17))])]
16484 "operands[1] = gen_reg_rtx (QImode);
16485 operands[2] = gen_reg_rtx (QImode);")
16487 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
16488 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
16490 (define_insn "cmpstrqi_nz_1"
16492 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16493 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
16494 (use (match_operand:SI 6 "register_operand" "2"))
16495 (use (match_operand:SI 3 "immediate_operand" "i"))
16497 (clobber (match_operand:SI 0 "register_operand" "=S"))
16498 (clobber (match_operand:SI 1 "register_operand" "=D"))
16499 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16502 [(set_attr "type" "str")
16503 (set_attr "mode" "QI")
16504 (set_attr "prefix_rep" "1")])
16506 (define_insn "cmpstrqi_nz_rex_1"
16508 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16509 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
16510 (use (match_operand:DI 6 "register_operand" "2"))
16511 (use (match_operand:SI 3 "immediate_operand" "i"))
16513 (clobber (match_operand:DI 0 "register_operand" "=S"))
16514 (clobber (match_operand:DI 1 "register_operand" "=D"))
16515 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16518 [(set_attr "type" "str")
16519 (set_attr "mode" "QI")
16520 (set_attr "prefix_rep" "1")])
16522 ;; The same, but the count is not known to not be zero.
16524 (define_insn "cmpstrqi_1"
16526 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16528 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16529 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16531 (use (match_operand:SI 3 "immediate_operand" "i"))
16534 (clobber (match_operand:SI 0 "register_operand" "=S"))
16535 (clobber (match_operand:SI 1 "register_operand" "=D"))
16536 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16539 [(set_attr "type" "str")
16540 (set_attr "mode" "QI")
16541 (set_attr "prefix_rep" "1")])
16543 (define_insn "cmpstrqi_rex_1"
16545 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16547 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16548 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16550 (use (match_operand:SI 3 "immediate_operand" "i"))
16553 (clobber (match_operand:DI 0 "register_operand" "=S"))
16554 (clobber (match_operand:DI 1 "register_operand" "=D"))
16555 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16558 [(set_attr "type" "str")
16559 (set_attr "mode" "QI")
16560 (set_attr "prefix_rep" "1")])
16562 (define_expand "strlensi"
16563 [(set (match_operand:SI 0 "register_operand" "")
16564 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16565 (match_operand:QI 2 "immediate_operand" "")
16566 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16569 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16575 (define_expand "strlendi"
16576 [(set (match_operand:DI 0 "register_operand" "")
16577 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16578 (match_operand:QI 2 "immediate_operand" "")
16579 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16582 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16588 (define_insn "strlenqi_1"
16589 [(set (match_operand:SI 0 "register_operand" "=&c")
16590 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16591 (match_operand:QI 2 "register_operand" "a")
16592 (match_operand:SI 3 "immediate_operand" "i")
16593 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16595 (clobber (match_operand:SI 1 "register_operand" "=D"))
16596 (clobber (reg:CC 17))]
16599 [(set_attr "type" "str")
16600 (set_attr "mode" "QI")
16601 (set_attr "prefix_rep" "1")])
16603 (define_insn "strlenqi_rex_1"
16604 [(set (match_operand:DI 0 "register_operand" "=&c")
16605 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16606 (match_operand:QI 2 "register_operand" "a")
16607 (match_operand:DI 3 "immediate_operand" "i")
16608 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16610 (clobber (match_operand:DI 1 "register_operand" "=D"))
16611 (clobber (reg:CC 17))]
16614 [(set_attr "type" "str")
16615 (set_attr "mode" "QI")
16616 (set_attr "prefix_rep" "1")])
16618 ;; Peephole optimizations to clean up after cmpstr*. This should be
16619 ;; handled in combine, but it is not currently up to the task.
16620 ;; When used for their truth value, the cmpstr* expanders generate
16629 ;; The intermediate three instructions are unnecessary.
16631 ;; This one handles cmpstr*_nz_1...
16635 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16636 (mem:BLK (match_operand 5 "register_operand" ""))))
16637 (use (match_operand 6 "register_operand" ""))
16638 (use (match_operand:SI 3 "immediate_operand" ""))
16640 (clobber (match_operand 0 "register_operand" ""))
16641 (clobber (match_operand 1 "register_operand" ""))
16642 (clobber (match_operand 2 "register_operand" ""))])
16643 (set (match_operand:QI 7 "register_operand" "")
16644 (gtu:QI (reg:CC 17) (const_int 0)))
16645 (set (match_operand:QI 8 "register_operand" "")
16646 (ltu:QI (reg:CC 17) (const_int 0)))
16648 (compare (match_dup 7) (match_dup 8)))
16650 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16653 (compare:CC (mem:BLK (match_dup 4))
16654 (mem:BLK (match_dup 5))))
16655 (use (match_dup 6))
16656 (use (match_dup 3))
16658 (clobber (match_dup 0))
16659 (clobber (match_dup 1))
16660 (clobber (match_dup 2))])]
16663 ;; ...and this one handles cmpstr*_1.
16667 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16669 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16670 (mem:BLK (match_operand 5 "register_operand" "")))
16672 (use (match_operand:SI 3 "immediate_operand" ""))
16675 (clobber (match_operand 0 "register_operand" ""))
16676 (clobber (match_operand 1 "register_operand" ""))
16677 (clobber (match_operand 2 "register_operand" ""))])
16678 (set (match_operand:QI 7 "register_operand" "")
16679 (gtu:QI (reg:CC 17) (const_int 0)))
16680 (set (match_operand:QI 8 "register_operand" "")
16681 (ltu:QI (reg:CC 17) (const_int 0)))
16683 (compare (match_dup 7) (match_dup 8)))
16685 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16688 (if_then_else:CC (ne (match_dup 6)
16690 (compare:CC (mem:BLK (match_dup 4))
16691 (mem:BLK (match_dup 5)))
16693 (use (match_dup 3))
16696 (clobber (match_dup 0))
16697 (clobber (match_dup 1))
16698 (clobber (match_dup 2))])]
16703 ;; Conditional move instructions.
16705 (define_expand "movdicc"
16706 [(set (match_operand:DI 0 "register_operand" "")
16707 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16708 (match_operand:DI 2 "general_operand" "")
16709 (match_operand:DI 3 "general_operand" "")))]
16711 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16713 (define_insn "x86_movdicc_0_m1_rex64"
16714 [(set (match_operand:DI 0 "register_operand" "=r")
16715 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16718 (clobber (reg:CC 17))]
16721 ; Since we don't have the proper number of operands for an alu insn,
16722 ; fill in all the blanks.
16723 [(set_attr "type" "alu")
16724 (set_attr "pent_pair" "pu")
16725 (set_attr "memory" "none")
16726 (set_attr "imm_disp" "false")
16727 (set_attr "mode" "DI")
16728 (set_attr "length_immediate" "0")])
16730 (define_insn "movdicc_c_rex64"
16731 [(set (match_operand:DI 0 "register_operand" "=r,r")
16732 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16733 [(reg 17) (const_int 0)])
16734 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16735 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16736 "TARGET_64BIT && TARGET_CMOVE
16737 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16739 cmov%O2%C1\t{%2, %0|%0, %2}
16740 cmov%O2%c1\t{%3, %0|%0, %3}"
16741 [(set_attr "type" "icmov")
16742 (set_attr "mode" "DI")])
16744 (define_expand "movsicc"
16745 [(set (match_operand:SI 0 "register_operand" "")
16746 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16747 (match_operand:SI 2 "general_operand" "")
16748 (match_operand:SI 3 "general_operand" "")))]
16750 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16752 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16753 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16754 ;; So just document what we're doing explicitly.
16756 (define_insn "x86_movsicc_0_m1"
16757 [(set (match_operand:SI 0 "register_operand" "=r")
16758 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16761 (clobber (reg:CC 17))]
16764 ; Since we don't have the proper number of operands for an alu insn,
16765 ; fill in all the blanks.
16766 [(set_attr "type" "alu")
16767 (set_attr "pent_pair" "pu")
16768 (set_attr "memory" "none")
16769 (set_attr "imm_disp" "false")
16770 (set_attr "mode" "SI")
16771 (set_attr "length_immediate" "0")])
16773 (define_insn "*movsicc_noc"
16774 [(set (match_operand:SI 0 "register_operand" "=r,r")
16775 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
16776 [(reg 17) (const_int 0)])
16777 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
16778 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
16780 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16782 cmov%O2%C1\t{%2, %0|%0, %2}
16783 cmov%O2%c1\t{%3, %0|%0, %3}"
16784 [(set_attr "type" "icmov")
16785 (set_attr "mode" "SI")])
16787 (define_expand "movhicc"
16788 [(set (match_operand:HI 0 "register_operand" "")
16789 (if_then_else:HI (match_operand 1 "comparison_operator" "")
16790 (match_operand:HI 2 "general_operand" "")
16791 (match_operand:HI 3 "general_operand" "")))]
16792 "TARGET_HIMODE_MATH"
16793 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16795 (define_insn "*movhicc_noc"
16796 [(set (match_operand:HI 0 "register_operand" "=r,r")
16797 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
16798 [(reg 17) (const_int 0)])
16799 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
16800 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
16802 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16804 cmov%O2%C1\t{%2, %0|%0, %2}
16805 cmov%O2%c1\t{%3, %0|%0, %3}"
16806 [(set_attr "type" "icmov")
16807 (set_attr "mode" "HI")])
16809 (define_expand "movqicc"
16810 [(set (match_operand:QI 0 "register_operand" "")
16811 (if_then_else:QI (match_operand 1 "comparison_operator" "")
16812 (match_operand:QI 2 "general_operand" "")
16813 (match_operand:QI 3 "general_operand" "")))]
16814 "TARGET_QIMODE_MATH"
16815 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16817 (define_insn_and_split "*movqicc_noc"
16818 [(set (match_operand:QI 0 "register_operand" "=r,r")
16819 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16820 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16821 (match_operand:QI 2 "register_operand" "r,0")
16822 (match_operand:QI 3 "register_operand" "0,r")))]
16823 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16825 "&& reload_completed"
16826 [(set (match_dup 0)
16827 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16830 "operands[0] = gen_lowpart (SImode, operands[0]);
16831 operands[2] = gen_lowpart (SImode, operands[2]);
16832 operands[3] = gen_lowpart (SImode, operands[3]);"
16833 [(set_attr "type" "icmov")
16834 (set_attr "mode" "SI")])
16836 (define_expand "movsfcc"
16837 [(set (match_operand:SF 0 "register_operand" "")
16838 (if_then_else:SF (match_operand 1 "comparison_operator" "")
16839 (match_operand:SF 2 "register_operand" "")
16840 (match_operand:SF 3 "register_operand" "")))]
16842 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16844 (define_insn "*movsfcc_1"
16845 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16846 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16847 [(reg 17) (const_int 0)])
16848 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16849 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16851 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16853 fcmov%F1\t{%2, %0|%0, %2}
16854 fcmov%f1\t{%3, %0|%0, %3}
16855 cmov%O2%C1\t{%2, %0|%0, %2}
16856 cmov%O2%c1\t{%3, %0|%0, %3}"
16857 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16858 (set_attr "mode" "SF,SF,SI,SI")])
16860 (define_expand "movdfcc"
16861 [(set (match_operand:DF 0 "register_operand" "")
16862 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16863 (match_operand:DF 2 "register_operand" "")
16864 (match_operand:DF 3 "register_operand" "")))]
16866 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16868 (define_insn "*movdfcc_1"
16869 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
16870 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16871 [(reg 17) (const_int 0)])
16872 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16873 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16874 "!TARGET_64BIT && TARGET_CMOVE
16875 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16877 fcmov%F1\t{%2, %0|%0, %2}
16878 fcmov%f1\t{%3, %0|%0, %3}
16881 [(set_attr "type" "fcmov,fcmov,multi,multi")
16882 (set_attr "mode" "DF")])
16884 (define_insn "*movdfcc_1_rex64"
16885 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16886 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16887 [(reg 17) (const_int 0)])
16888 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
16889 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
16890 "TARGET_64BIT && TARGET_CMOVE
16891 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16893 fcmov%F1\t{%2, %0|%0, %2}
16894 fcmov%f1\t{%3, %0|%0, %3}
16895 cmov%O2%C1\t{%2, %0|%0, %2}
16896 cmov%O2%c1\t{%3, %0|%0, %3}"
16897 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16898 (set_attr "mode" "DF")])
16901 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16902 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16903 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16904 (match_operand:DF 2 "nonimmediate_operand" "")
16905 (match_operand:DF 3 "nonimmediate_operand" "")))]
16906 "!TARGET_64BIT && reload_completed"
16907 [(set (match_dup 2)
16908 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16912 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16915 "split_di (operands+2, 1, operands+5, operands+6);
16916 split_di (operands+3, 1, operands+7, operands+8);
16917 split_di (operands, 1, operands+2, operands+3);")
16919 (define_expand "movxfcc"
16920 [(set (match_operand:XF 0 "register_operand" "")
16921 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16922 (match_operand:XF 2 "register_operand" "")
16923 (match_operand:XF 3 "register_operand" "")))]
16924 "!TARGET_64BIT && TARGET_CMOVE"
16925 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16927 (define_expand "movtfcc"
16928 [(set (match_operand:TF 0 "register_operand" "")
16929 (if_then_else:TF (match_operand 1 "comparison_operator" "")
16930 (match_operand:TF 2 "register_operand" "")
16931 (match_operand:TF 3 "register_operand" "")))]
16933 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16935 (define_insn "*movxfcc_1"
16936 [(set (match_operand:XF 0 "register_operand" "=f,f")
16937 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16938 [(reg 17) (const_int 0)])
16939 (match_operand:XF 2 "register_operand" "f,0")
16940 (match_operand:XF 3 "register_operand" "0,f")))]
16941 "!TARGET_64BIT && TARGET_CMOVE"
16943 fcmov%F1\t{%2, %0|%0, %2}
16944 fcmov%f1\t{%3, %0|%0, %3}"
16945 [(set_attr "type" "fcmov")
16946 (set_attr "mode" "XF")])
16948 (define_insn "*movtfcc_1"
16949 [(set (match_operand:TF 0 "register_operand" "=f,f")
16950 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
16951 [(reg 17) (const_int 0)])
16952 (match_operand:TF 2 "register_operand" "f,0")
16953 (match_operand:TF 3 "register_operand" "0,f")))]
16956 fcmov%F1\t{%2, %0|%0, %2}
16957 fcmov%f1\t{%3, %0|%0, %3}"
16958 [(set_attr "type" "fcmov")
16959 (set_attr "mode" "XF")])
16961 (define_expand "minsf3"
16963 (set (match_operand:SF 0 "register_operand" "")
16964 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16965 (match_operand:SF 2 "nonimmediate_operand" ""))
16968 (clobber (reg:CC 17))])]
16972 (define_insn "*minsf"
16973 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16974 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16975 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16978 (clobber (reg:CC 17))]
16979 "TARGET_SSE && TARGET_IEEE_FP"
16982 (define_insn "*minsf_nonieee"
16983 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16984 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16985 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16988 (clobber (reg:CC 17))]
16989 "TARGET_SSE && !TARGET_IEEE_FP
16990 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16994 [(set (match_operand:SF 0 "register_operand" "")
16995 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16996 (match_operand:SF 2 "nonimmediate_operand" ""))
16997 (match_operand:SF 3 "register_operand" "")
16998 (match_operand:SF 4 "nonimmediate_operand" "")))
16999 (clobber (reg:CC 17))]
17000 "SSE_REG_P (operands[0]) && reload_completed
17001 && ((operands_match_p (operands[1], operands[3])
17002 && operands_match_p (operands[2], operands[4]))
17003 || (operands_match_p (operands[1], operands[4])
17004 && operands_match_p (operands[2], operands[3])))"
17005 [(set (match_dup 0)
17006 (if_then_else:SF (lt (match_dup 1)
17011 ;; Conditional addition patterns
17012 (define_expand "addqicc"
17013 [(match_operand:QI 0 "register_operand" "")
17014 (match_operand 1 "comparison_operator" "")
17015 (match_operand:QI 2 "register_operand" "")
17016 (match_operand:QI 3 "const_int_operand" "")]
17018 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17020 (define_expand "addhicc"
17021 [(match_operand:HI 0 "register_operand" "")
17022 (match_operand 1 "comparison_operator" "")
17023 (match_operand:HI 2 "register_operand" "")
17024 (match_operand:HI 3 "const_int_operand" "")]
17026 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17028 (define_expand "addsicc"
17029 [(match_operand:SI 0 "register_operand" "")
17030 (match_operand 1 "comparison_operator" "")
17031 (match_operand:SI 2 "register_operand" "")
17032 (match_operand:SI 3 "const_int_operand" "")]
17034 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17036 (define_expand "adddicc"
17037 [(match_operand:DI 0 "register_operand" "")
17038 (match_operand 1 "comparison_operator" "")
17039 (match_operand:DI 2 "register_operand" "")
17040 (match_operand:DI 3 "const_int_operand" "")]
17042 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17044 ;; We can't represent the LT test directly. Do this by swapping the operands.
17047 [(set (match_operand:SF 0 "fp_register_operand" "")
17048 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17049 (match_operand:SF 2 "register_operand" ""))
17050 (match_operand:SF 3 "register_operand" "")
17051 (match_operand:SF 4 "register_operand" "")))
17052 (clobber (reg:CC 17))]
17054 && ((operands_match_p (operands[1], operands[3])
17055 && operands_match_p (operands[2], operands[4]))
17056 || (operands_match_p (operands[1], operands[4])
17057 && operands_match_p (operands[2], operands[3])))"
17058 [(set (reg:CCFP 17)
17059 (compare:CCFP (match_dup 2)
17062 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
17066 (define_insn "*minsf_sse"
17067 [(set (match_operand:SF 0 "register_operand" "=x")
17068 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17069 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17072 "TARGET_SSE && reload_completed"
17073 "minss\t{%2, %0|%0, %2}"
17074 [(set_attr "type" "sse")
17075 (set_attr "mode" "SF")])
17077 (define_expand "mindf3"
17079 (set (match_operand:DF 0 "register_operand" "")
17080 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17081 (match_operand:DF 2 "nonimmediate_operand" ""))
17084 (clobber (reg:CC 17))])]
17085 "TARGET_SSE2 && TARGET_SSE_MATH"
17088 (define_insn "*mindf"
17089 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17090 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17091 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17094 (clobber (reg:CC 17))]
17095 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17098 (define_insn "*mindf_nonieee"
17099 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17100 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17101 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17104 (clobber (reg:CC 17))]
17105 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17106 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17110 [(set (match_operand:DF 0 "register_operand" "")
17111 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17112 (match_operand:DF 2 "nonimmediate_operand" ""))
17113 (match_operand:DF 3 "register_operand" "")
17114 (match_operand:DF 4 "nonimmediate_operand" "")))
17115 (clobber (reg:CC 17))]
17116 "SSE_REG_P (operands[0]) && reload_completed
17117 && ((operands_match_p (operands[1], operands[3])
17118 && operands_match_p (operands[2], operands[4]))
17119 || (operands_match_p (operands[1], operands[4])
17120 && operands_match_p (operands[2], operands[3])))"
17121 [(set (match_dup 0)
17122 (if_then_else:DF (lt (match_dup 1)
17127 ;; We can't represent the LT test directly. Do this by swapping the operands.
17129 [(set (match_operand:DF 0 "fp_register_operand" "")
17130 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17131 (match_operand:DF 2 "register_operand" ""))
17132 (match_operand:DF 3 "register_operand" "")
17133 (match_operand:DF 4 "register_operand" "")))
17134 (clobber (reg:CC 17))]
17136 && ((operands_match_p (operands[1], operands[3])
17137 && operands_match_p (operands[2], operands[4]))
17138 || (operands_match_p (operands[1], operands[4])
17139 && operands_match_p (operands[2], operands[3])))"
17140 [(set (reg:CCFP 17)
17141 (compare:CCFP (match_dup 2)
17144 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
17148 (define_insn "*mindf_sse"
17149 [(set (match_operand:DF 0 "register_operand" "=Y")
17150 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17151 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17154 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17155 "minsd\t{%2, %0|%0, %2}"
17156 [(set_attr "type" "sse")
17157 (set_attr "mode" "DF")])
17159 (define_expand "maxsf3"
17161 (set (match_operand:SF 0 "register_operand" "")
17162 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17163 (match_operand:SF 2 "nonimmediate_operand" ""))
17166 (clobber (reg:CC 17))])]
17170 (define_insn "*maxsf"
17171 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17172 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17173 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17176 (clobber (reg:CC 17))]
17177 "TARGET_SSE && TARGET_IEEE_FP"
17180 (define_insn "*maxsf_nonieee"
17181 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17182 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17183 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17186 (clobber (reg:CC 17))]
17187 "TARGET_SSE && !TARGET_IEEE_FP
17188 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17192 [(set (match_operand:SF 0 "register_operand" "")
17193 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17194 (match_operand:SF 2 "nonimmediate_operand" ""))
17195 (match_operand:SF 3 "register_operand" "")
17196 (match_operand:SF 4 "nonimmediate_operand" "")))
17197 (clobber (reg:CC 17))]
17198 "SSE_REG_P (operands[0]) && reload_completed
17199 && ((operands_match_p (operands[1], operands[3])
17200 && operands_match_p (operands[2], operands[4]))
17201 || (operands_match_p (operands[1], operands[4])
17202 && operands_match_p (operands[2], operands[3])))"
17203 [(set (match_dup 0)
17204 (if_then_else:SF (gt (match_dup 1)
17210 [(set (match_operand:SF 0 "fp_register_operand" "")
17211 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17212 (match_operand:SF 2 "register_operand" ""))
17213 (match_operand:SF 3 "register_operand" "")
17214 (match_operand:SF 4 "register_operand" "")))
17215 (clobber (reg:CC 17))]
17217 && ((operands_match_p (operands[1], operands[3])
17218 && operands_match_p (operands[2], operands[4]))
17219 || (operands_match_p (operands[1], operands[4])
17220 && operands_match_p (operands[2], operands[3])))"
17221 [(set (reg:CCFP 17)
17222 (compare:CCFP (match_dup 1)
17225 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
17229 (define_insn "*maxsf_sse"
17230 [(set (match_operand:SF 0 "register_operand" "=x")
17231 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17232 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17235 "TARGET_SSE && reload_completed"
17236 "maxss\t{%2, %0|%0, %2}"
17237 [(set_attr "type" "sse")
17238 (set_attr "mode" "SF")])
17240 (define_expand "maxdf3"
17242 (set (match_operand:DF 0 "register_operand" "")
17243 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17244 (match_operand:DF 2 "nonimmediate_operand" ""))
17247 (clobber (reg:CC 17))])]
17248 "TARGET_SSE2 && TARGET_SSE_MATH"
17251 (define_insn "*maxdf"
17252 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17253 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17254 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17257 (clobber (reg:CC 17))]
17258 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17261 (define_insn "*maxdf_nonieee"
17262 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17263 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17264 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17267 (clobber (reg:CC 17))]
17268 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17269 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17273 [(set (match_operand:DF 0 "register_operand" "")
17274 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17275 (match_operand:DF 2 "nonimmediate_operand" ""))
17276 (match_operand:DF 3 "register_operand" "")
17277 (match_operand:DF 4 "nonimmediate_operand" "")))
17278 (clobber (reg:CC 17))]
17279 "SSE_REG_P (operands[0]) && reload_completed
17280 && ((operands_match_p (operands[1], operands[3])
17281 && operands_match_p (operands[2], operands[4]))
17282 || (operands_match_p (operands[1], operands[4])
17283 && operands_match_p (operands[2], operands[3])))"
17284 [(set (match_dup 0)
17285 (if_then_else:DF (gt (match_dup 1)
17291 [(set (match_operand:DF 0 "fp_register_operand" "")
17292 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17293 (match_operand:DF 2 "register_operand" ""))
17294 (match_operand:DF 3 "register_operand" "")
17295 (match_operand:DF 4 "register_operand" "")))
17296 (clobber (reg:CC 17))]
17298 && ((operands_match_p (operands[1], operands[3])
17299 && operands_match_p (operands[2], operands[4]))
17300 || (operands_match_p (operands[1], operands[4])
17301 && operands_match_p (operands[2], operands[3])))"
17302 [(set (reg:CCFP 17)
17303 (compare:CCFP (match_dup 1)
17306 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
17310 (define_insn "*maxdf_sse"
17311 [(set (match_operand:DF 0 "register_operand" "=Y")
17312 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17313 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17316 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17317 "maxsd\t{%2, %0|%0, %2}"
17318 [(set_attr "type" "sse")
17319 (set_attr "mode" "DF")])
17321 ;; Misc patterns (?)
17323 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17324 ;; Otherwise there will be nothing to keep
17326 ;; [(set (reg ebp) (reg esp))]
17327 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17328 ;; (clobber (eflags)]
17329 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
17331 ;; in proper program order.
17332 (define_expand "pro_epilogue_adjust_stack"
17333 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
17334 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17335 (match_operand:SI 2 "immediate_operand" "i,i")))
17336 (clobber (reg:CC 17))
17337 (clobber (mem:BLK (scratch)))])]
17342 emit_insn (gen_pro_epilogue_adjust_stack_rex64
17343 (operands[0], operands[1], operands[2]));
17348 (define_insn "*pro_epilogue_adjust_stack_1"
17349 [(set (match_operand:SI 0 "register_operand" "=r,r")
17350 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17351 (match_operand:SI 2 "immediate_operand" "i,i")))
17352 (clobber (reg:CC 17))
17353 (clobber (mem:BLK (scratch)))]
17356 switch (get_attr_type (insn))
17359 return "mov{l}\t{%1, %0|%0, %1}";
17362 if (GET_CODE (operands[2]) == CONST_INT
17363 && (INTVAL (operands[2]) == 128
17364 || (INTVAL (operands[2]) < 0
17365 && INTVAL (operands[2]) != -128)))
17367 operands[2] = GEN_INT (-INTVAL (operands[2]));
17368 return "sub{l}\t{%2, %0|%0, %2}";
17370 return "add{l}\t{%2, %0|%0, %2}";
17373 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17374 return "lea{l}\t{%a2, %0|%0, %a2}";
17380 [(set (attr "type")
17381 (cond [(eq_attr "alternative" "0")
17382 (const_string "alu")
17383 (match_operand:SI 2 "const0_operand" "")
17384 (const_string "imov")
17386 (const_string "lea")))
17387 (set_attr "mode" "SI")])
17389 (define_insn "pro_epilogue_adjust_stack_rex64"
17390 [(set (match_operand:DI 0 "register_operand" "=r,r")
17391 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
17392 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
17393 (clobber (reg:CC 17))
17394 (clobber (mem:BLK (scratch)))]
17397 switch (get_attr_type (insn))
17400 return "mov{q}\t{%1, %0|%0, %1}";
17403 if (GET_CODE (operands[2]) == CONST_INT
17404 && (INTVAL (operands[2]) == 128
17405 || (INTVAL (operands[2]) < 0
17406 && INTVAL (operands[2]) != -128)))
17408 operands[2] = GEN_INT (-INTVAL (operands[2]));
17409 return "sub{q}\t{%2, %0|%0, %2}";
17411 return "add{q}\t{%2, %0|%0, %2}";
17414 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17415 return "lea{q}\t{%a2, %0|%0, %a2}";
17421 [(set (attr "type")
17422 (cond [(eq_attr "alternative" "0")
17423 (const_string "alu")
17424 (match_operand:DI 2 "const0_operand" "")
17425 (const_string "imov")
17427 (const_string "lea")))
17428 (set_attr "mode" "DI")])
17431 ;; Placeholder for the conditional moves. This one is split either to SSE
17432 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
17433 ;; fact is that compares supported by the cmp??ss instructions are exactly
17434 ;; swapped of those supported by cmove sequence.
17435 ;; The EQ/NE comparisons also needs bit care, since they are not directly
17436 ;; supported by i387 comparisons and we do need to emit two conditional moves
17439 (define_insn "sse_movsfcc"
17440 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
17441 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17442 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
17443 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
17444 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
17445 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
17446 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17447 (clobber (reg:CC 17))]
17449 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17450 /* Avoid combine from being smart and converting min/max
17451 instruction patterns into conditional moves. */
17452 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17453 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17454 || !rtx_equal_p (operands[4], operands[2])
17455 || !rtx_equal_p (operands[5], operands[3]))
17456 && (!TARGET_IEEE_FP
17457 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17460 (define_insn "sse_movsfcc_eq"
17461 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
17462 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
17463 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
17464 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
17465 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
17466 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
17467 (clobber (reg:CC 17))]
17469 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17472 (define_insn "sse_movdfcc"
17473 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
17474 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17475 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
17476 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
17477 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
17478 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
17479 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17480 (clobber (reg:CC 17))]
17482 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17483 /* Avoid combine from being smart and converting min/max
17484 instruction patterns into conditional moves. */
17485 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17486 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17487 || !rtx_equal_p (operands[4], operands[2])
17488 || !rtx_equal_p (operands[5], operands[3]))
17489 && (!TARGET_IEEE_FP
17490 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17493 (define_insn "sse_movdfcc_eq"
17494 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
17495 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
17496 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
17497 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
17498 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
17499 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
17500 (clobber (reg:CC 17))]
17502 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17505 ;; For non-sse moves just expand the usual cmove sequence.
17507 [(set (match_operand 0 "register_operand" "")
17508 (if_then_else (match_operator 1 "comparison_operator"
17509 [(match_operand 4 "nonimmediate_operand" "")
17510 (match_operand 5 "register_operand" "")])
17511 (match_operand 2 "nonimmediate_operand" "")
17512 (match_operand 3 "nonimmediate_operand" "")))
17513 (clobber (match_operand 6 "" ""))
17514 (clobber (reg:CC 17))]
17515 "!SSE_REG_P (operands[0]) && reload_completed
17516 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17519 ix86_compare_op0 = operands[5];
17520 ix86_compare_op1 = operands[4];
17521 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17522 VOIDmode, operands[5], operands[4]);
17523 ix86_expand_fp_movcc (operands);
17527 ;; Split SSE based conditional move into sequence:
17528 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17529 ;; and op2, op0 - zero op2 if comparison was false
17530 ;; nand op0, op3 - load op3 to op0 if comparison was false
17531 ;; or op2, op0 - get the nonzero one into the result.
17533 [(set (match_operand 0 "register_operand" "")
17534 (if_then_else (match_operator 1 "sse_comparison_operator"
17535 [(match_operand 4 "register_operand" "")
17536 (match_operand 5 "nonimmediate_operand" "")])
17537 (match_operand 2 "register_operand" "")
17538 (match_operand 3 "register_operand" "")))
17539 (clobber (match_operand 6 "" ""))
17540 (clobber (reg:CC 17))]
17541 "SSE_REG_P (operands[0]) && reload_completed"
17542 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17543 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17544 (subreg:TI (match_dup 4) 0)))
17545 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17546 (subreg:TI (match_dup 3) 0)))
17547 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17548 (subreg:TI (match_dup 7) 0)))]
17550 if (GET_MODE (operands[2]) == DFmode
17551 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17553 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17554 emit_insn (gen_sse2_unpcklpd (op, op, op));
17555 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17556 emit_insn (gen_sse2_unpcklpd (op, op, op));
17559 /* If op2 == op3, op3 would be clobbered before it is used. */
17560 if (operands_match_p (operands[2], operands[3]))
17562 emit_move_insn (operands[0], operands[2]);
17566 PUT_MODE (operands[1], GET_MODE (operands[0]));
17567 if (operands_match_p (operands[0], operands[4]))
17568 operands[6] = operands[4], operands[7] = operands[2];
17570 operands[6] = operands[2], operands[7] = operands[4];
17573 ;; Special case of conditional move we can handle effectively.
17574 ;; Do not brother with the integer/floating point case, since these are
17575 ;; bot considerably slower, unlike in the generic case.
17576 (define_insn "*sse_movsfcc_const0_1"
17577 [(set (match_operand:SF 0 "register_operand" "=&x")
17578 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17579 [(match_operand:SF 4 "register_operand" "0")
17580 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17581 (match_operand:SF 2 "register_operand" "x")
17582 (match_operand:SF 3 "const0_operand" "X")))]
17586 (define_insn "*sse_movsfcc_const0_2"
17587 [(set (match_operand:SF 0 "register_operand" "=&x")
17588 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17589 [(match_operand:SF 4 "register_operand" "0")
17590 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17591 (match_operand:SF 2 "const0_operand" "X")
17592 (match_operand:SF 3 "register_operand" "x")))]
17596 (define_insn "*sse_movsfcc_const0_3"
17597 [(set (match_operand:SF 0 "register_operand" "=&x")
17598 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17599 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17600 (match_operand:SF 5 "register_operand" "0")])
17601 (match_operand:SF 2 "register_operand" "x")
17602 (match_operand:SF 3 "const0_operand" "X")))]
17606 (define_insn "*sse_movsfcc_const0_4"
17607 [(set (match_operand:SF 0 "register_operand" "=&x")
17608 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17609 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17610 (match_operand:SF 5 "register_operand" "0")])
17611 (match_operand:SF 2 "const0_operand" "X")
17612 (match_operand:SF 3 "register_operand" "x")))]
17616 (define_insn "*sse_movdfcc_const0_1"
17617 [(set (match_operand:DF 0 "register_operand" "=&Y")
17618 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17619 [(match_operand:DF 4 "register_operand" "0")
17620 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17621 (match_operand:DF 2 "register_operand" "Y")
17622 (match_operand:DF 3 "const0_operand" "X")))]
17626 (define_insn "*sse_movdfcc_const0_2"
17627 [(set (match_operand:DF 0 "register_operand" "=&Y")
17628 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17629 [(match_operand:DF 4 "register_operand" "0")
17630 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17631 (match_operand:DF 2 "const0_operand" "X")
17632 (match_operand:DF 3 "register_operand" "Y")))]
17636 (define_insn "*sse_movdfcc_const0_3"
17637 [(set (match_operand:DF 0 "register_operand" "=&Y")
17638 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17639 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17640 (match_operand:DF 5 "register_operand" "0")])
17641 (match_operand:DF 2 "register_operand" "Y")
17642 (match_operand:DF 3 "const0_operand" "X")))]
17646 (define_insn "*sse_movdfcc_const0_4"
17647 [(set (match_operand:DF 0 "register_operand" "=&Y")
17648 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17649 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17650 (match_operand:DF 5 "register_operand" "0")])
17651 (match_operand:DF 2 "const0_operand" "X")
17652 (match_operand:DF 3 "register_operand" "Y")))]
17657 [(set (match_operand 0 "register_operand" "")
17658 (if_then_else (match_operator 1 "comparison_operator"
17659 [(match_operand 4 "nonimmediate_operand" "")
17660 (match_operand 5 "nonimmediate_operand" "")])
17661 (match_operand 2 "nonmemory_operand" "")
17662 (match_operand 3 "nonmemory_operand" "")))]
17663 "SSE_REG_P (operands[0]) && reload_completed
17664 && (const0_operand (operands[2], GET_MODE (operands[0]))
17665 || const0_operand (operands[3], GET_MODE (operands[0])))"
17666 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17667 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17670 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17671 && GET_MODE (operands[2]) == DFmode)
17673 if (REG_P (operands[2]))
17675 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17676 emit_insn (gen_sse2_unpcklpd (op, op, op));
17678 if (REG_P (operands[3]))
17680 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17681 emit_insn (gen_sse2_unpcklpd (op, op, op));
17684 PUT_MODE (operands[1], GET_MODE (operands[0]));
17685 if (!sse_comparison_operator (operands[1], VOIDmode)
17686 || !rtx_equal_p (operands[0], operands[4]))
17688 rtx tmp = operands[5];
17689 operands[5] = operands[4];
17691 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17693 if (!rtx_equal_p (operands[0], operands[4]))
17695 if (const0_operand (operands[2], GET_MODE (operands[0])))
17697 operands[7] = operands[3];
17698 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17703 operands[7] = operands[2];
17704 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17706 operands[7] = simplify_gen_subreg (TImode, operands[7],
17707 GET_MODE (operands[7]), 0);
17710 (define_expand "allocate_stack_worker"
17711 [(match_operand:SI 0 "register_operand" "")]
17712 "TARGET_STACK_PROBE"
17715 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17717 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17721 (define_insn "allocate_stack_worker_1"
17722 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17723 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17724 (clobber (match_dup 0))
17725 (clobber (reg:CC 17))]
17726 "!TARGET_64BIT && TARGET_STACK_PROBE"
17728 [(set_attr "type" "multi")
17729 (set_attr "length" "5")])
17731 (define_insn "allocate_stack_worker_rex64"
17732 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17733 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17734 (clobber (match_dup 0))
17735 (clobber (reg:CC 17))]
17736 "TARGET_64BIT && TARGET_STACK_PROBE"
17738 [(set_attr "type" "multi")
17739 (set_attr "length" "5")])
17741 (define_expand "allocate_stack"
17742 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17743 (minus:SI (reg:SI 7)
17744 (match_operand:SI 1 "general_operand" "")))
17745 (clobber (reg:CC 17))])
17746 (parallel [(set (reg:SI 7)
17747 (minus:SI (reg:SI 7) (match_dup 1)))
17748 (clobber (reg:CC 17))])]
17749 "TARGET_STACK_PROBE"
17751 #ifdef CHECK_STACK_LIMIT
17752 if (GET_CODE (operands[1]) == CONST_INT
17753 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17754 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17758 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17761 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
17765 (define_expand "builtin_setjmp_receiver"
17766 [(label_ref (match_operand 0 "" ""))]
17767 "!TARGET_64BIT && flag_pic"
17769 emit_insn (gen_set_got (pic_offset_table_rtx));
17773 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
17776 [(set (match_operand 0 "register_operand" "")
17777 (match_operator 3 "promotable_binary_operator"
17778 [(match_operand 1 "register_operand" "")
17779 (match_operand 2 "aligned_operand" "")]))
17780 (clobber (reg:CC 17))]
17781 "! TARGET_PARTIAL_REG_STALL && reload_completed
17782 && ((GET_MODE (operands[0]) == HImode
17783 && ((!optimize_size && !TARGET_FAST_PREFIX)
17784 || GET_CODE (operands[2]) != CONST_INT
17785 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
17786 || (GET_MODE (operands[0]) == QImode
17787 && (TARGET_PROMOTE_QImode || optimize_size)))"
17788 [(parallel [(set (match_dup 0)
17789 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17790 (clobber (reg:CC 17))])]
17791 "operands[0] = gen_lowpart (SImode, operands[0]);
17792 operands[1] = gen_lowpart (SImode, operands[1]);
17793 if (GET_CODE (operands[3]) != ASHIFT)
17794 operands[2] = gen_lowpart (SImode, operands[2]);
17795 PUT_MODE (operands[3], SImode);")
17797 ; Promote the QImode tests, as i386 has encoding of the AND
17798 ; instruction with 32-bit sign-extended immediate and thus the
17799 ; instruction size is unchanged, except in the %eax case for
17800 ; which it is increased by one byte, hence the ! optimize_size.
17803 (compare (and (match_operand 1 "aligned_operand" "")
17804 (match_operand 2 "const_int_operand" ""))
17806 (set (match_operand 0 "register_operand" "")
17807 (and (match_dup 1) (match_dup 2)))]
17808 "! TARGET_PARTIAL_REG_STALL && reload_completed
17809 /* Ensure that the operand will remain sign-extended immediate. */
17810 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
17812 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
17813 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
17814 [(parallel [(set (reg:CCNO 17)
17815 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17818 (and:SI (match_dup 1) (match_dup 2)))])]
17820 = gen_int_mode (INTVAL (operands[2])
17821 & GET_MODE_MASK (GET_MODE (operands[0])),
17823 operands[0] = gen_lowpart (SImode, operands[0]);
17824 operands[1] = gen_lowpart (SImode, operands[1]);")
17826 ; Don't promote the QImode tests, as i386 doesn't have encoding of
17827 ; the TEST instruction with 32-bit sign-extended immediate and thus
17828 ; the instruction size would at least double, which is not what we
17829 ; want even with ! optimize_size.
17832 (compare (and (match_operand:HI 0 "aligned_operand" "")
17833 (match_operand:HI 1 "const_int_operand" ""))
17835 "! TARGET_PARTIAL_REG_STALL && reload_completed
17836 /* Ensure that the operand will remain sign-extended immediate. */
17837 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
17838 && ! TARGET_FAST_PREFIX
17839 && ! optimize_size"
17840 [(set (reg:CCNO 17)
17841 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17844 = gen_int_mode (INTVAL (operands[1])
17845 & GET_MODE_MASK (GET_MODE (operands[0])),
17847 operands[0] = gen_lowpart (SImode, operands[0]);")
17850 [(set (match_operand 0 "register_operand" "")
17851 (neg (match_operand 1 "register_operand" "")))
17852 (clobber (reg:CC 17))]
17853 "! TARGET_PARTIAL_REG_STALL && reload_completed
17854 && (GET_MODE (operands[0]) == HImode
17855 || (GET_MODE (operands[0]) == QImode
17856 && (TARGET_PROMOTE_QImode || optimize_size)))"
17857 [(parallel [(set (match_dup 0)
17858 (neg:SI (match_dup 1)))
17859 (clobber (reg:CC 17))])]
17860 "operands[0] = gen_lowpart (SImode, operands[0]);
17861 operands[1] = gen_lowpart (SImode, operands[1]);")
17864 [(set (match_operand 0 "register_operand" "")
17865 (not (match_operand 1 "register_operand" "")))]
17866 "! TARGET_PARTIAL_REG_STALL && reload_completed
17867 && (GET_MODE (operands[0]) == HImode
17868 || (GET_MODE (operands[0]) == QImode
17869 && (TARGET_PROMOTE_QImode || optimize_size)))"
17870 [(set (match_dup 0)
17871 (not:SI (match_dup 1)))]
17872 "operands[0] = gen_lowpart (SImode, operands[0]);
17873 operands[1] = gen_lowpart (SImode, operands[1]);")
17876 [(set (match_operand 0 "register_operand" "")
17877 (if_then_else (match_operator 1 "comparison_operator"
17878 [(reg 17) (const_int 0)])
17879 (match_operand 2 "register_operand" "")
17880 (match_operand 3 "register_operand" "")))]
17881 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
17882 && (GET_MODE (operands[0]) == HImode
17883 || (GET_MODE (operands[0]) == QImode
17884 && (TARGET_PROMOTE_QImode || optimize_size)))"
17885 [(set (match_dup 0)
17886 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
17887 "operands[0] = gen_lowpart (SImode, operands[0]);
17888 operands[2] = gen_lowpart (SImode, operands[2]);
17889 operands[3] = gen_lowpart (SImode, operands[3]);")
17892 ;; RTL Peephole optimizations, run before sched2. These primarily look to
17893 ;; transform a complex memory operation into two memory to register operations.
17895 ;; Don't push memory operands
17897 [(set (match_operand:SI 0 "push_operand" "")
17898 (match_operand:SI 1 "memory_operand" ""))
17899 (match_scratch:SI 2 "r")]
17900 "! optimize_size && ! TARGET_PUSH_MEMORY"
17901 [(set (match_dup 2) (match_dup 1))
17902 (set (match_dup 0) (match_dup 2))]
17906 [(set (match_operand:DI 0 "push_operand" "")
17907 (match_operand:DI 1 "memory_operand" ""))
17908 (match_scratch:DI 2 "r")]
17909 "! optimize_size && ! TARGET_PUSH_MEMORY"
17910 [(set (match_dup 2) (match_dup 1))
17911 (set (match_dup 0) (match_dup 2))]
17914 ;; We need to handle SFmode only, because DFmode and XFmode is split to
17917 [(set (match_operand:SF 0 "push_operand" "")
17918 (match_operand:SF 1 "memory_operand" ""))
17919 (match_scratch:SF 2 "r")]
17920 "! optimize_size && ! TARGET_PUSH_MEMORY"
17921 [(set (match_dup 2) (match_dup 1))
17922 (set (match_dup 0) (match_dup 2))]
17926 [(set (match_operand:HI 0 "push_operand" "")
17927 (match_operand:HI 1 "memory_operand" ""))
17928 (match_scratch:HI 2 "r")]
17929 "! optimize_size && ! TARGET_PUSH_MEMORY"
17930 [(set (match_dup 2) (match_dup 1))
17931 (set (match_dup 0) (match_dup 2))]
17935 [(set (match_operand:QI 0 "push_operand" "")
17936 (match_operand:QI 1 "memory_operand" ""))
17937 (match_scratch:QI 2 "q")]
17938 "! optimize_size && ! TARGET_PUSH_MEMORY"
17939 [(set (match_dup 2) (match_dup 1))
17940 (set (match_dup 0) (match_dup 2))]
17943 ;; Don't move an immediate directly to memory when the instruction
17946 [(match_scratch:SI 1 "r")
17947 (set (match_operand:SI 0 "memory_operand" "")
17950 && ! TARGET_USE_MOV0
17951 && TARGET_SPLIT_LONG_MOVES
17952 && get_attr_length (insn) >= ix86_cost->large_insn
17953 && peep2_regno_dead_p (0, FLAGS_REG)"
17954 [(parallel [(set (match_dup 1) (const_int 0))
17955 (clobber (reg:CC 17))])
17956 (set (match_dup 0) (match_dup 1))]
17960 [(match_scratch:HI 1 "r")
17961 (set (match_operand:HI 0 "memory_operand" "")
17964 && ! TARGET_USE_MOV0
17965 && TARGET_SPLIT_LONG_MOVES
17966 && get_attr_length (insn) >= ix86_cost->large_insn
17967 && peep2_regno_dead_p (0, FLAGS_REG)"
17968 [(parallel [(set (match_dup 2) (const_int 0))
17969 (clobber (reg:CC 17))])
17970 (set (match_dup 0) (match_dup 1))]
17971 "operands[2] = gen_lowpart (SImode, operands[1]);")
17974 [(match_scratch:QI 1 "q")
17975 (set (match_operand:QI 0 "memory_operand" "")
17978 && ! TARGET_USE_MOV0
17979 && TARGET_SPLIT_LONG_MOVES
17980 && get_attr_length (insn) >= ix86_cost->large_insn
17981 && peep2_regno_dead_p (0, FLAGS_REG)"
17982 [(parallel [(set (match_dup 2) (const_int 0))
17983 (clobber (reg:CC 17))])
17984 (set (match_dup 0) (match_dup 1))]
17985 "operands[2] = gen_lowpart (SImode, operands[1]);")
17988 [(match_scratch:SI 2 "r")
17989 (set (match_operand:SI 0 "memory_operand" "")
17990 (match_operand:SI 1 "immediate_operand" ""))]
17992 && get_attr_length (insn) >= ix86_cost->large_insn
17993 && TARGET_SPLIT_LONG_MOVES"
17994 [(set (match_dup 2) (match_dup 1))
17995 (set (match_dup 0) (match_dup 2))]
17999 [(match_scratch:HI 2 "r")
18000 (set (match_operand:HI 0 "memory_operand" "")
18001 (match_operand:HI 1 "immediate_operand" ""))]
18002 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18003 && TARGET_SPLIT_LONG_MOVES"
18004 [(set (match_dup 2) (match_dup 1))
18005 (set (match_dup 0) (match_dup 2))]
18009 [(match_scratch:QI 2 "q")
18010 (set (match_operand:QI 0 "memory_operand" "")
18011 (match_operand:QI 1 "immediate_operand" ""))]
18012 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18013 && TARGET_SPLIT_LONG_MOVES"
18014 [(set (match_dup 2) (match_dup 1))
18015 (set (match_dup 0) (match_dup 2))]
18018 ;; Don't compare memory with zero, load and use a test instead.
18021 (compare (match_operand:SI 0 "memory_operand" "")
18023 (match_scratch:SI 3 "r")]
18024 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
18025 [(set (match_dup 3) (match_dup 0))
18026 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
18029 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
18030 ;; Don't split NOTs with a displacement operand, because resulting XOR
18031 ;; will not be pairable anyway.
18033 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
18034 ;; represented using a modRM byte. The XOR replacement is long decoded,
18035 ;; so this split helps here as well.
18037 ;; Note: Can't do this as a regular split because we can't get proper
18038 ;; lifetime information then.
18041 [(set (match_operand:SI 0 "nonimmediate_operand" "")
18042 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
18044 && peep2_regno_dead_p (0, FLAGS_REG)
18045 && ((TARGET_PENTIUM
18046 && (GET_CODE (operands[0]) != MEM
18047 || !memory_displacement_operand (operands[0], SImode)))
18048 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
18049 [(parallel [(set (match_dup 0)
18050 (xor:SI (match_dup 1) (const_int -1)))
18051 (clobber (reg:CC 17))])]
18055 [(set (match_operand:HI 0 "nonimmediate_operand" "")
18056 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
18058 && peep2_regno_dead_p (0, FLAGS_REG)
18059 && ((TARGET_PENTIUM
18060 && (GET_CODE (operands[0]) != MEM
18061 || !memory_displacement_operand (operands[0], HImode)))
18062 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
18063 [(parallel [(set (match_dup 0)
18064 (xor:HI (match_dup 1) (const_int -1)))
18065 (clobber (reg:CC 17))])]
18069 [(set (match_operand:QI 0 "nonimmediate_operand" "")
18070 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
18072 && peep2_regno_dead_p (0, FLAGS_REG)
18073 && ((TARGET_PENTIUM
18074 && (GET_CODE (operands[0]) != MEM
18075 || !memory_displacement_operand (operands[0], QImode)))
18076 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
18077 [(parallel [(set (match_dup 0)
18078 (xor:QI (match_dup 1) (const_int -1)))
18079 (clobber (reg:CC 17))])]
18082 ;; Non pairable "test imm, reg" instructions can be translated to
18083 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
18084 ;; byte opcode instead of two, have a short form for byte operands),
18085 ;; so do it for other CPUs as well. Given that the value was dead,
18086 ;; this should not create any new dependencies. Pass on the sub-word
18087 ;; versions if we're concerned about partial register stalls.
18091 (compare (and:SI (match_operand:SI 0 "register_operand" "")
18092 (match_operand:SI 1 "immediate_operand" ""))
18094 "ix86_match_ccmode (insn, CCNOmode)
18095 && (true_regnum (operands[0]) != 0
18096 || (GET_CODE (operands[1]) == CONST_INT
18097 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
18098 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18100 [(set (reg:CCNO 17)
18101 (compare:CCNO (and:SI (match_dup 0)
18105 (and:SI (match_dup 0) (match_dup 1)))])]
18108 ;; We don't need to handle HImode case, because it will be promoted to SImode
18109 ;; on ! TARGET_PARTIAL_REG_STALL
18113 (compare (and:QI (match_operand:QI 0 "register_operand" "")
18114 (match_operand:QI 1 "immediate_operand" ""))
18116 "! TARGET_PARTIAL_REG_STALL
18117 && ix86_match_ccmode (insn, CCNOmode)
18118 && true_regnum (operands[0]) != 0
18119 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18121 [(set (reg:CCNO 17)
18122 (compare:CCNO (and:QI (match_dup 0)
18126 (and:QI (match_dup 0) (match_dup 1)))])]
18134 (match_operand 0 "ext_register_operand" "")
18137 (match_operand 1 "const_int_operand" ""))
18139 "! TARGET_PARTIAL_REG_STALL
18140 && ix86_match_ccmode (insn, CCNOmode)
18141 && true_regnum (operands[0]) != 0
18142 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18143 [(parallel [(set (reg:CCNO 17)
18152 (set (zero_extract:SI (match_dup 0)
18163 ;; Don't do logical operations with memory inputs.
18165 [(match_scratch:SI 2 "r")
18166 (parallel [(set (match_operand:SI 0 "register_operand" "")
18167 (match_operator:SI 3 "arith_or_logical_operator"
18169 (match_operand:SI 1 "memory_operand" "")]))
18170 (clobber (reg:CC 17))])]
18171 "! optimize_size && ! TARGET_READ_MODIFY"
18172 [(set (match_dup 2) (match_dup 1))
18173 (parallel [(set (match_dup 0)
18174 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18175 (clobber (reg:CC 17))])]
18179 [(match_scratch:SI 2 "r")
18180 (parallel [(set (match_operand:SI 0 "register_operand" "")
18181 (match_operator:SI 3 "arith_or_logical_operator"
18182 [(match_operand:SI 1 "memory_operand" "")
18184 (clobber (reg:CC 17))])]
18185 "! optimize_size && ! TARGET_READ_MODIFY"
18186 [(set (match_dup 2) (match_dup 1))
18187 (parallel [(set (match_dup 0)
18188 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18189 (clobber (reg:CC 17))])]
18192 ; Don't do logical operations with memory outputs
18194 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18195 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18196 ; the same decoder scheduling characteristics as the original.
18199 [(match_scratch:SI 2 "r")
18200 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18201 (match_operator:SI 3 "arith_or_logical_operator"
18203 (match_operand:SI 1 "nonmemory_operand" "")]))
18204 (clobber (reg:CC 17))])]
18205 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18206 [(set (match_dup 2) (match_dup 0))
18207 (parallel [(set (match_dup 2)
18208 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
18209 (clobber (reg:CC 17))])
18210 (set (match_dup 0) (match_dup 2))]
18214 [(match_scratch:SI 2 "r")
18215 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18216 (match_operator:SI 3 "arith_or_logical_operator"
18217 [(match_operand:SI 1 "nonmemory_operand" "")
18219 (clobber (reg:CC 17))])]
18220 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18221 [(set (match_dup 2) (match_dup 0))
18222 (parallel [(set (match_dup 2)
18223 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18224 (clobber (reg:CC 17))])
18225 (set (match_dup 0) (match_dup 2))]
18228 ;; Attempt to always use XOR for zeroing registers.
18230 [(set (match_operand 0 "register_operand" "")
18232 "(GET_MODE (operands[0]) == QImode
18233 || GET_MODE (operands[0]) == HImode
18234 || GET_MODE (operands[0]) == SImode
18235 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18236 && (! TARGET_USE_MOV0 || optimize_size)
18237 && peep2_regno_dead_p (0, FLAGS_REG)"
18238 [(parallel [(set (match_dup 0) (const_int 0))
18239 (clobber (reg:CC 17))])]
18240 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18244 [(set (strict_low_part (match_operand 0 "register_operand" ""))
18246 "(GET_MODE (operands[0]) == QImode
18247 || GET_MODE (operands[0]) == HImode)
18248 && (! TARGET_USE_MOV0 || optimize_size)
18249 && peep2_regno_dead_p (0, FLAGS_REG)"
18250 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
18251 (clobber (reg:CC 17))])])
18253 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
18255 [(set (match_operand 0 "register_operand" "")
18257 "(GET_MODE (operands[0]) == HImode
18258 || GET_MODE (operands[0]) == SImode
18259 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18260 && (optimize_size || TARGET_PENTIUM)
18261 && peep2_regno_dead_p (0, FLAGS_REG)"
18262 [(parallel [(set (match_dup 0) (const_int -1))
18263 (clobber (reg:CC 17))])]
18264 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18267 ;; Attempt to convert simple leas to adds. These can be created by
18270 [(set (match_operand:SI 0 "register_operand" "")
18271 (plus:SI (match_dup 0)
18272 (match_operand:SI 1 "nonmemory_operand" "")))]
18273 "peep2_regno_dead_p (0, FLAGS_REG)"
18274 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
18275 (clobber (reg:CC 17))])]
18279 [(set (match_operand:SI 0 "register_operand" "")
18280 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
18281 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
18282 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
18283 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
18284 (clobber (reg:CC 17))])]
18285 "operands[2] = gen_lowpart (SImode, operands[2]);")
18288 [(set (match_operand:DI 0 "register_operand" "")
18289 (plus:DI (match_dup 0)
18290 (match_operand:DI 1 "x86_64_general_operand" "")))]
18291 "peep2_regno_dead_p (0, FLAGS_REG)"
18292 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
18293 (clobber (reg:CC 17))])]
18297 [(set (match_operand:SI 0 "register_operand" "")
18298 (mult:SI (match_dup 0)
18299 (match_operand:SI 1 "const_int_operand" "")))]
18300 "exact_log2 (INTVAL (operands[1])) >= 0
18301 && peep2_regno_dead_p (0, FLAGS_REG)"
18302 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18303 (clobber (reg:CC 17))])]
18304 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18307 [(set (match_operand:DI 0 "register_operand" "")
18308 (mult:DI (match_dup 0)
18309 (match_operand:DI 1 "const_int_operand" "")))]
18310 "exact_log2 (INTVAL (operands[1])) >= 0
18311 && peep2_regno_dead_p (0, FLAGS_REG)"
18312 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
18313 (clobber (reg:CC 17))])]
18314 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18317 [(set (match_operand:SI 0 "register_operand" "")
18318 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
18319 (match_operand:DI 2 "const_int_operand" "")) 0))]
18320 "exact_log2 (INTVAL (operands[2])) >= 0
18321 && REGNO (operands[0]) == REGNO (operands[1])
18322 && peep2_regno_dead_p (0, FLAGS_REG)"
18323 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18324 (clobber (reg:CC 17))])]
18325 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
18327 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
18328 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
18329 ;; many CPUs it is also faster, since special hardware to avoid esp
18330 ;; dependencies is present.
18332 ;; While some of these conversions may be done using splitters, we use peepholes
18333 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
18335 ;; Convert prologue esp subtractions to push.
18336 ;; We need register to push. In order to keep verify_flow_info happy we have
18338 ;; - use scratch and clobber it in order to avoid dependencies
18339 ;; - use already live register
18340 ;; We can't use the second way right now, since there is no reliable way how to
18341 ;; verify that given register is live. First choice will also most likely in
18342 ;; fewer dependencies. On the place of esp adjustments it is very likely that
18343 ;; call clobbered registers are dead. We may want to use base pointer as an
18344 ;; alternative when no register is available later.
18347 [(match_scratch:SI 0 "r")
18348 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18349 (clobber (reg:CC 17))
18350 (clobber (mem:BLK (scratch)))])]
18351 "optimize_size || !TARGET_SUB_ESP_4"
18352 [(clobber (match_dup 0))
18353 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18354 (clobber (mem:BLK (scratch)))])])
18357 [(match_scratch:SI 0 "r")
18358 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18359 (clobber (reg:CC 17))
18360 (clobber (mem:BLK (scratch)))])]
18361 "optimize_size || !TARGET_SUB_ESP_8"
18362 [(clobber (match_dup 0))
18363 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18364 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18365 (clobber (mem:BLK (scratch)))])])
18367 ;; Convert esp subtractions to push.
18369 [(match_scratch:SI 0 "r")
18370 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18371 (clobber (reg:CC 17))])]
18372 "optimize_size || !TARGET_SUB_ESP_4"
18373 [(clobber (match_dup 0))
18374 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18377 [(match_scratch:SI 0 "r")
18378 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18379 (clobber (reg:CC 17))])]
18380 "optimize_size || !TARGET_SUB_ESP_8"
18381 [(clobber (match_dup 0))
18382 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18383 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18385 ;; Convert epilogue deallocator to pop.
18387 [(match_scratch:SI 0 "r")
18388 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18389 (clobber (reg:CC 17))
18390 (clobber (mem:BLK (scratch)))])]
18391 "optimize_size || !TARGET_ADD_ESP_4"
18392 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18393 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18394 (clobber (mem:BLK (scratch)))])]
18397 ;; Two pops case is tricky, since pop causes dependency on destination register.
18398 ;; We use two registers if available.
18400 [(match_scratch:SI 0 "r")
18401 (match_scratch:SI 1 "r")
18402 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18403 (clobber (reg:CC 17))
18404 (clobber (mem:BLK (scratch)))])]
18405 "optimize_size || !TARGET_ADD_ESP_8"
18406 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18407 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18408 (clobber (mem:BLK (scratch)))])
18409 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18410 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18414 [(match_scratch:SI 0 "r")
18415 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18416 (clobber (reg:CC 17))
18417 (clobber (mem:BLK (scratch)))])]
18419 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18420 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18421 (clobber (mem:BLK (scratch)))])
18422 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18423 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18426 ;; Convert esp additions to pop.
18428 [(match_scratch:SI 0 "r")
18429 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18430 (clobber (reg:CC 17))])]
18432 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18433 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18436 ;; Two pops case is tricky, since pop causes dependency on destination register.
18437 ;; We use two registers if available.
18439 [(match_scratch:SI 0 "r")
18440 (match_scratch:SI 1 "r")
18441 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18442 (clobber (reg:CC 17))])]
18444 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18445 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18446 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18447 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18451 [(match_scratch:SI 0 "r")
18452 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18453 (clobber (reg:CC 17))])]
18455 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18456 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18457 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18458 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18461 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
18462 ;; required and register dies.
18465 (compare (match_operand:SI 0 "register_operand" "")
18466 (match_operand:SI 1 "incdec_operand" "")))]
18467 "ix86_match_ccmode (insn, CCGCmode)
18468 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18469 [(parallel [(set (reg:CCGC 17)
18470 (compare:CCGC (match_dup 0)
18472 (clobber (match_dup 0))])]
18477 (compare (match_operand:HI 0 "register_operand" "")
18478 (match_operand:HI 1 "incdec_operand" "")))]
18479 "ix86_match_ccmode (insn, CCGCmode)
18480 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18481 [(parallel [(set (reg:CCGC 17)
18482 (compare:CCGC (match_dup 0)
18484 (clobber (match_dup 0))])]
18489 (compare (match_operand:QI 0 "register_operand" "")
18490 (match_operand:QI 1 "incdec_operand" "")))]
18491 "ix86_match_ccmode (insn, CCGCmode)
18492 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18493 [(parallel [(set (reg:CCGC 17)
18494 (compare:CCGC (match_dup 0)
18496 (clobber (match_dup 0))])]
18499 ;; Convert compares with 128 to shorter add -128
18502 (compare (match_operand:SI 0 "register_operand" "")
18504 "ix86_match_ccmode (insn, CCGCmode)
18505 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18506 [(parallel [(set (reg:CCGC 17)
18507 (compare:CCGC (match_dup 0)
18509 (clobber (match_dup 0))])]
18514 (compare (match_operand:HI 0 "register_operand" "")
18516 "ix86_match_ccmode (insn, CCGCmode)
18517 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18518 [(parallel [(set (reg:CCGC 17)
18519 (compare:CCGC (match_dup 0)
18521 (clobber (match_dup 0))])]
18525 [(match_scratch:DI 0 "r")
18526 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18527 (clobber (reg:CC 17))
18528 (clobber (mem:BLK (scratch)))])]
18529 "optimize_size || !TARGET_SUB_ESP_4"
18530 [(clobber (match_dup 0))
18531 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18532 (clobber (mem:BLK (scratch)))])])
18535 [(match_scratch:DI 0 "r")
18536 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18537 (clobber (reg:CC 17))
18538 (clobber (mem:BLK (scratch)))])]
18539 "optimize_size || !TARGET_SUB_ESP_8"
18540 [(clobber (match_dup 0))
18541 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18542 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18543 (clobber (mem:BLK (scratch)))])])
18545 ;; Convert esp subtractions to push.
18547 [(match_scratch:DI 0 "r")
18548 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18549 (clobber (reg:CC 17))])]
18550 "optimize_size || !TARGET_SUB_ESP_4"
18551 [(clobber (match_dup 0))
18552 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18555 [(match_scratch:DI 0 "r")
18556 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18557 (clobber (reg:CC 17))])]
18558 "optimize_size || !TARGET_SUB_ESP_8"
18559 [(clobber (match_dup 0))
18560 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18561 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18563 ;; Convert epilogue deallocator to pop.
18565 [(match_scratch:DI 0 "r")
18566 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18567 (clobber (reg:CC 17))
18568 (clobber (mem:BLK (scratch)))])]
18569 "optimize_size || !TARGET_ADD_ESP_4"
18570 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18571 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18572 (clobber (mem:BLK (scratch)))])]
18575 ;; Two pops case is tricky, since pop causes dependency on destination register.
18576 ;; We use two registers if available.
18578 [(match_scratch:DI 0 "r")
18579 (match_scratch:DI 1 "r")
18580 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18581 (clobber (reg:CC 17))
18582 (clobber (mem:BLK (scratch)))])]
18583 "optimize_size || !TARGET_ADD_ESP_8"
18584 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18585 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18586 (clobber (mem:BLK (scratch)))])
18587 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18588 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18592 [(match_scratch:DI 0 "r")
18593 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18594 (clobber (reg:CC 17))
18595 (clobber (mem:BLK (scratch)))])]
18597 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18598 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18599 (clobber (mem:BLK (scratch)))])
18600 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18601 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18604 ;; Convert esp additions to pop.
18606 [(match_scratch:DI 0 "r")
18607 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18608 (clobber (reg:CC 17))])]
18610 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18611 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18614 ;; Two pops case is tricky, since pop causes dependency on destination register.
18615 ;; We use two registers if available.
18617 [(match_scratch:DI 0 "r")
18618 (match_scratch:DI 1 "r")
18619 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18620 (clobber (reg:CC 17))])]
18622 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18623 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18624 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18625 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18629 [(match_scratch:DI 0 "r")
18630 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18631 (clobber (reg:CC 17))])]
18633 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18634 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18635 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18636 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18639 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18640 ;; imul $32bit_imm, reg, reg is direct decoded.
18642 [(match_scratch:DI 3 "r")
18643 (parallel [(set (match_operand:DI 0 "register_operand" "")
18644 (mult:DI (match_operand:DI 1 "memory_operand" "")
18645 (match_operand:DI 2 "immediate_operand" "")))
18646 (clobber (reg:CC 17))])]
18647 "TARGET_K8 && !optimize_size
18648 && (GET_CODE (operands[2]) != CONST_INT
18649 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18650 [(set (match_dup 3) (match_dup 1))
18651 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18652 (clobber (reg:CC 17))])]
18656 [(match_scratch:SI 3 "r")
18657 (parallel [(set (match_operand:SI 0 "register_operand" "")
18658 (mult:SI (match_operand:SI 1 "memory_operand" "")
18659 (match_operand:SI 2 "immediate_operand" "")))
18660 (clobber (reg:CC 17))])]
18661 "TARGET_K8 && !optimize_size
18662 && (GET_CODE (operands[2]) != CONST_INT
18663 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18664 [(set (match_dup 3) (match_dup 1))
18665 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18666 (clobber (reg:CC 17))])]
18670 [(match_scratch:SI 3 "r")
18671 (parallel [(set (match_operand:DI 0 "register_operand" "")
18673 (mult:SI (match_operand:SI 1 "memory_operand" "")
18674 (match_operand:SI 2 "immediate_operand" ""))))
18675 (clobber (reg:CC 17))])]
18676 "TARGET_K8 && !optimize_size
18677 && (GET_CODE (operands[2]) != CONST_INT
18678 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18679 [(set (match_dup 3) (match_dup 1))
18680 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18681 (clobber (reg:CC 17))])]
18684 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18685 ;; Convert it into imul reg, reg
18686 ;; It would be better to force assembler to encode instruction using long
18687 ;; immediate, but there is apparently no way to do so.
18689 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18690 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18691 (match_operand:DI 2 "const_int_operand" "")))
18692 (clobber (reg:CC 17))])
18693 (match_scratch:DI 3 "r")]
18694 "TARGET_K8 && !optimize_size
18695 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18696 [(set (match_dup 3) (match_dup 2))
18697 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18698 (clobber (reg:CC 17))])]
18700 if (!rtx_equal_p (operands[0], operands[1]))
18701 emit_move_insn (operands[0], operands[1]);
18705 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18706 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18707 (match_operand:SI 2 "const_int_operand" "")))
18708 (clobber (reg:CC 17))])
18709 (match_scratch:SI 3 "r")]
18710 "TARGET_K8 && !optimize_size
18711 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18712 [(set (match_dup 3) (match_dup 2))
18713 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18714 (clobber (reg:CC 17))])]
18716 if (!rtx_equal_p (operands[0], operands[1]))
18717 emit_move_insn (operands[0], operands[1]);
18721 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18722 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18723 (match_operand:HI 2 "immediate_operand" "")))
18724 (clobber (reg:CC 17))])
18725 (match_scratch:HI 3 "r")]
18726 "TARGET_K8 && !optimize_size"
18727 [(set (match_dup 3) (match_dup 2))
18728 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18729 (clobber (reg:CC 17))])]
18731 if (!rtx_equal_p (operands[0], operands[1]))
18732 emit_move_insn (operands[0], operands[1]);
18735 ;; Call-value patterns last so that the wildcard operand does not
18736 ;; disrupt insn-recog's switch tables.
18738 (define_insn "*call_value_pop_0"
18739 [(set (match_operand 0 "" "")
18740 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18741 (match_operand:SI 2 "" "")))
18742 (set (reg:SI 7) (plus:SI (reg:SI 7)
18743 (match_operand:SI 3 "immediate_operand" "")))]
18746 if (SIBLING_CALL_P (insn))
18749 return "call\t%P1";
18751 [(set_attr "type" "callv")])
18753 (define_insn "*call_value_pop_1"
18754 [(set (match_operand 0 "" "")
18755 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18756 (match_operand:SI 2 "" "")))
18757 (set (reg:SI 7) (plus:SI (reg:SI 7)
18758 (match_operand:SI 3 "immediate_operand" "i")))]
18761 if (constant_call_address_operand (operands[1], QImode))
18763 if (SIBLING_CALL_P (insn))
18766 return "call\t%P1";
18768 if (SIBLING_CALL_P (insn))
18771 return "call\t%A1";
18773 [(set_attr "type" "callv")])
18775 (define_insn "*call_value_0"
18776 [(set (match_operand 0 "" "")
18777 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18778 (match_operand:SI 2 "" "")))]
18781 if (SIBLING_CALL_P (insn))
18784 return "call\t%P1";
18786 [(set_attr "type" "callv")])
18788 (define_insn "*call_value_0_rex64"
18789 [(set (match_operand 0 "" "")
18790 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18791 (match_operand:DI 2 "const_int_operand" "")))]
18794 if (SIBLING_CALL_P (insn))
18797 return "call\t%P1";
18799 [(set_attr "type" "callv")])
18801 (define_insn "*call_value_1"
18802 [(set (match_operand 0 "" "")
18803 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18804 (match_operand:SI 2 "" "")))]
18805 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18807 if (constant_call_address_operand (operands[1], QImode))
18808 return "call\t%P1";
18809 return "call\t%*%1";
18811 [(set_attr "type" "callv")])
18813 (define_insn "*sibcall_value_1"
18814 [(set (match_operand 0 "" "")
18815 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18816 (match_operand:SI 2 "" "")))]
18817 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18819 if (constant_call_address_operand (operands[1], QImode))
18821 return "jmp\t%*%1";
18823 [(set_attr "type" "callv")])
18825 (define_insn "*call_value_1_rex64"
18826 [(set (match_operand 0 "" "")
18827 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18828 (match_operand:DI 2 "" "")))]
18829 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
18831 if (constant_call_address_operand (operands[1], QImode))
18832 return "call\t%P1";
18833 return "call\t%A1";
18835 [(set_attr "type" "callv")])
18837 (define_insn "*sibcall_value_1_rex64"
18838 [(set (match_operand 0 "" "")
18839 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18840 (match_operand:DI 2 "" "")))]
18841 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18843 [(set_attr "type" "callv")])
18845 (define_insn "*sibcall_value_1_rex64_v"
18846 [(set (match_operand 0 "" "")
18847 (call (mem:QI (reg:DI 40))
18848 (match_operand:DI 1 "" "")))]
18849 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18851 [(set_attr "type" "callv")])
18853 (define_insn "trap"
18854 [(trap_if (const_int 1) (const_int 5))]
18858 ;;; ix86 doesn't have conditional trap instructions, but we fake them
18859 ;;; for the sake of bounds checking. By emitting bounds checks as
18860 ;;; conditional traps rather than as conditional jumps around
18861 ;;; unconditional traps we avoid introducing spurious basic-block
18862 ;;; boundaries and facilitate elimination of redundant checks. In
18863 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
18866 ;;; FIXME: Static branch prediction rules for ix86 are such that
18867 ;;; forward conditional branches predict as untaken. As implemented
18868 ;;; below, pseudo conditional traps violate that rule. We should use
18869 ;;; .pushsection/.popsection to place all of the `int 5's in a special
18870 ;;; section loaded at the end of the text segment and branch forward
18871 ;;; there on bounds-failure, and then jump back immediately (in case
18872 ;;; the system chooses to ignore bounds violations, or to report
18873 ;;; violations and continue execution).
18875 (define_expand "conditional_trap"
18876 [(trap_if (match_operator 0 "comparison_operator"
18877 [(match_dup 2) (const_int 0)])
18878 (match_operand 1 "const_int_operand" ""))]
18881 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
18882 ix86_expand_compare (GET_CODE (operands[0]),
18888 (define_insn "*conditional_trap_1"
18889 [(trap_if (match_operator 0 "comparison_operator"
18890 [(reg 17) (const_int 0)])
18891 (match_operand 1 "const_int_operand" ""))]
18894 operands[2] = gen_label_rtx ();
18895 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
18896 (*targetm.asm_out.internal_label) (asm_out_file, "L",
18897 CODE_LABEL_NUMBER (operands[2]));
18901 ;; Pentium III SIMD instructions.
18903 ;; Moves for SSE/MMX regs.
18905 (define_insn "movv4sf_internal"
18906 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18907 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18911 movaps\t{%1, %0|%0, %1}
18912 movaps\t{%1, %0|%0, %1}"
18913 [(set_attr "type" "ssemov")
18914 (set_attr "mode" "V4SF")])
18917 [(set (match_operand:V4SF 0 "register_operand" "")
18918 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18920 [(set (match_dup 0)
18922 (vec_duplicate:V4SF (match_dup 1))
18926 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18927 operands[2] = CONST0_RTX (V4SFmode);
18930 (define_insn "movv4si_internal"
18931 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18932 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18935 switch (which_alternative)
18938 if (get_attr_mode (insn) == MODE_V4SF)
18939 return "xorps\t%0, %0";
18941 return "pxor\t%0, %0";
18944 if (get_attr_mode (insn) == MODE_V4SF)
18945 return "movaps\t{%1, %0|%0, %1}";
18947 return "movdqa\t{%1, %0|%0, %1}";
18952 [(set_attr "type" "ssemov")
18954 (cond [(eq_attr "alternative" "0,1")
18956 (ne (symbol_ref "optimize_size")
18958 (const_string "V4SF")
18959 (const_string "TI"))
18960 (eq_attr "alternative" "2")
18962 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18964 (ne (symbol_ref "optimize_size")
18966 (const_string "V4SF")
18967 (const_string "TI"))]
18968 (const_string "TI")))])
18970 (define_insn "movv2di_internal"
18971 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18972 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18975 switch (which_alternative)
18978 if (get_attr_mode (insn) == MODE_V4SF)
18979 return "xorps\t%0, %0";
18981 return "pxor\t%0, %0";
18984 if (get_attr_mode (insn) == MODE_V4SF)
18985 return "movaps\t{%1, %0|%0, %1}";
18987 return "movdqa\t{%1, %0|%0, %1}";
18992 [(set_attr "type" "ssemov")
18994 (cond [(eq_attr "alternative" "0,1")
18996 (ne (symbol_ref "optimize_size")
18998 (const_string "V4SF")
18999 (const_string "TI"))
19000 (eq_attr "alternative" "2")
19002 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19004 (ne (symbol_ref "optimize_size")
19006 (const_string "V4SF")
19007 (const_string "TI"))]
19008 (const_string "TI")))])
19011 [(set (match_operand:V2DF 0 "register_operand" "")
19012 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
19014 [(set (match_dup 0)
19016 (vec_duplicate:V2DF (match_dup 1))
19020 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
19021 operands[2] = CONST0_RTX (V2DFmode);
19024 (define_insn "movv8qi_internal"
19025 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
19026 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
19028 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19031 movq\t{%1, %0|%0, %1}
19032 movq\t{%1, %0|%0, %1}"
19033 [(set_attr "type" "mmxmov")
19034 (set_attr "mode" "DI")])
19036 (define_insn "movv4hi_internal"
19037 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
19038 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
19040 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19043 movq\t{%1, %0|%0, %1}
19044 movq\t{%1, %0|%0, %1}"
19045 [(set_attr "type" "mmxmov")
19046 (set_attr "mode" "DI")])
19048 (define_insn "movv2si_internal"
19049 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
19050 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
19052 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19055 movq\t{%1, %0|%0, %1}
19056 movq\t{%1, %0|%0, %1}"
19057 [(set_attr "type" "mmxcvt")
19058 (set_attr "mode" "DI")])
19060 (define_insn "movv2sf_internal"
19061 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
19062 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
19064 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19067 movq\t{%1, %0|%0, %1}
19068 movq\t{%1, %0|%0, %1}"
19069 [(set_attr "type" "mmxcvt")
19070 (set_attr "mode" "DI")])
19072 (define_expand "movti"
19073 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19074 (match_operand:TI 1 "nonimmediate_operand" ""))]
19075 "TARGET_SSE || TARGET_64BIT"
19078 ix86_expand_move (TImode, operands);
19080 ix86_expand_vector_move (TImode, operands);
19084 (define_insn "movv2df_internal"
19085 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
19086 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
19088 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19090 switch (which_alternative)
19093 if (get_attr_mode (insn) == MODE_V4SF)
19094 return "xorps\t%0, %0";
19096 return "xorpd\t%0, %0";
19099 if (get_attr_mode (insn) == MODE_V4SF)
19100 return "movaps\t{%1, %0|%0, %1}";
19102 return "movapd\t{%1, %0|%0, %1}";
19107 [(set_attr "type" "ssemov")
19109 (cond [(eq_attr "alternative" "0,1")
19111 (ne (symbol_ref "optimize_size")
19113 (const_string "V4SF")
19114 (const_string "V2DF"))
19115 (eq_attr "alternative" "2")
19117 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19119 (ne (symbol_ref "optimize_size")
19121 (const_string "V4SF")
19122 (const_string "V2DF"))]
19123 (const_string "V2DF")))])
19125 (define_insn "movv8hi_internal"
19126 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
19127 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
19129 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19131 switch (which_alternative)
19134 if (get_attr_mode (insn) == MODE_V4SF)
19135 return "xorps\t%0, %0";
19137 return "pxor\t%0, %0";
19140 if (get_attr_mode (insn) == MODE_V4SF)
19141 return "movaps\t{%1, %0|%0, %1}";
19143 return "movdqa\t{%1, %0|%0, %1}";
19148 [(set_attr "type" "ssemov")
19150 (cond [(eq_attr "alternative" "0,1")
19152 (ne (symbol_ref "optimize_size")
19154 (const_string "V4SF")
19155 (const_string "TI"))
19156 (eq_attr "alternative" "2")
19158 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19160 (ne (symbol_ref "optimize_size")
19162 (const_string "V4SF")
19163 (const_string "TI"))]
19164 (const_string "TI")))])
19166 (define_insn "movv16qi_internal"
19167 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
19168 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
19170 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19172 switch (which_alternative)
19175 if (get_attr_mode (insn) == MODE_V4SF)
19176 return "xorps\t%0, %0";
19178 return "pxor\t%0, %0";
19181 if (get_attr_mode (insn) == MODE_V4SF)
19182 return "movaps\t{%1, %0|%0, %1}";
19184 return "movdqa\t{%1, %0|%0, %1}";
19189 [(set_attr "type" "ssemov")
19191 (cond [(eq_attr "alternative" "0,1")
19193 (ne (symbol_ref "optimize_size")
19195 (const_string "V4SF")
19196 (const_string "TI"))
19197 (eq_attr "alternative" "2")
19199 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19201 (ne (symbol_ref "optimize_size")
19203 (const_string "V4SF")
19204 (const_string "TI"))]
19205 (const_string "TI")))])
19207 (define_expand "movv2df"
19208 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
19209 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
19212 ix86_expand_vector_move (V2DFmode, operands);
19216 (define_expand "movv8hi"
19217 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
19218 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
19221 ix86_expand_vector_move (V8HImode, operands);
19225 (define_expand "movv16qi"
19226 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
19227 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
19230 ix86_expand_vector_move (V16QImode, operands);
19234 (define_expand "movv4sf"
19235 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19236 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
19239 ix86_expand_vector_move (V4SFmode, operands);
19243 (define_expand "movv4si"
19244 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
19245 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
19248 ix86_expand_vector_move (V4SImode, operands);
19252 (define_expand "movv2di"
19253 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
19254 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
19257 ix86_expand_vector_move (V2DImode, operands);
19261 (define_expand "movv2si"
19262 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
19263 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
19266 ix86_expand_vector_move (V2SImode, operands);
19270 (define_expand "movv4hi"
19271 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
19272 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
19275 ix86_expand_vector_move (V4HImode, operands);
19279 (define_expand "movv8qi"
19280 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
19281 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
19284 ix86_expand_vector_move (V8QImode, operands);
19288 (define_expand "movv2sf"
19289 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
19290 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
19293 ix86_expand_vector_move (V2SFmode, operands);
19297 (define_insn "*pushti"
19298 [(set (match_operand:TI 0 "push_operand" "=<")
19299 (match_operand:TI 1 "register_operand" "x"))]
19303 (define_insn "*pushv2df"
19304 [(set (match_operand:V2DF 0 "push_operand" "=<")
19305 (match_operand:V2DF 1 "register_operand" "x"))]
19309 (define_insn "*pushv2di"
19310 [(set (match_operand:V2DI 0 "push_operand" "=<")
19311 (match_operand:V2DI 1 "register_operand" "x"))]
19315 (define_insn "*pushv8hi"
19316 [(set (match_operand:V8HI 0 "push_operand" "=<")
19317 (match_operand:V8HI 1 "register_operand" "x"))]
19321 (define_insn "*pushv16qi"
19322 [(set (match_operand:V16QI 0 "push_operand" "=<")
19323 (match_operand:V16QI 1 "register_operand" "x"))]
19327 (define_insn "*pushv4sf"
19328 [(set (match_operand:V4SF 0 "push_operand" "=<")
19329 (match_operand:V4SF 1 "register_operand" "x"))]
19333 (define_insn "*pushv4si"
19334 [(set (match_operand:V4SI 0 "push_operand" "=<")
19335 (match_operand:V4SI 1 "register_operand" "x"))]
19339 (define_insn "*pushv2si"
19340 [(set (match_operand:V2SI 0 "push_operand" "=<")
19341 (match_operand:V2SI 1 "register_operand" "y"))]
19345 (define_insn "*pushv4hi"
19346 [(set (match_operand:V4HI 0 "push_operand" "=<")
19347 (match_operand:V4HI 1 "register_operand" "y"))]
19351 (define_insn "*pushv8qi"
19352 [(set (match_operand:V8QI 0 "push_operand" "=<")
19353 (match_operand:V8QI 1 "register_operand" "y"))]
19357 (define_insn "*pushv2sf"
19358 [(set (match_operand:V2SF 0 "push_operand" "=<")
19359 (match_operand:V2SF 1 "register_operand" "y"))]
19364 [(set (match_operand 0 "push_operand" "")
19365 (match_operand 1 "register_operand" ""))]
19366 "!TARGET_64BIT && reload_completed
19367 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19368 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
19369 (set (match_dup 2) (match_dup 1))]
19370 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19371 stack_pointer_rtx);
19372 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19375 [(set (match_operand 0 "push_operand" "")
19376 (match_operand 1 "register_operand" ""))]
19377 "TARGET_64BIT && reload_completed
19378 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19379 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
19380 (set (match_dup 2) (match_dup 1))]
19381 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19382 stack_pointer_rtx);
19383 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19386 (define_insn "movti_internal"
19387 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
19388 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
19389 "TARGET_SSE && !TARGET_64BIT
19390 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19392 switch (which_alternative)
19395 if (get_attr_mode (insn) == MODE_V4SF)
19396 return "xorps\t%0, %0";
19398 return "pxor\t%0, %0";
19401 if (get_attr_mode (insn) == MODE_V4SF)
19402 return "movaps\t{%1, %0|%0, %1}";
19404 return "movdqa\t{%1, %0|%0, %1}";
19409 [(set_attr "type" "ssemov,ssemov,ssemov")
19411 (cond [(eq_attr "alternative" "0,1")
19413 (ne (symbol_ref "optimize_size")
19415 (const_string "V4SF")
19416 (const_string "TI"))
19417 (eq_attr "alternative" "2")
19419 (ne (symbol_ref "optimize_size")
19421 (const_string "V4SF")
19422 (const_string "TI"))]
19423 (const_string "TI")))])
19425 (define_insn "*movti_rex64"
19426 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
19427 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
19429 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19431 switch (which_alternative)
19437 if (get_attr_mode (insn) == MODE_V4SF)
19438 return "xorps\t%0, %0";
19440 return "pxor\t%0, %0";
19443 if (get_attr_mode (insn) == MODE_V4SF)
19444 return "movaps\t{%1, %0|%0, %1}";
19446 return "movdqa\t{%1, %0|%0, %1}";
19451 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19453 (cond [(eq_attr "alternative" "2,3")
19455 (ne (symbol_ref "optimize_size")
19457 (const_string "V4SF")
19458 (const_string "TI"))
19459 (eq_attr "alternative" "4")
19461 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19463 (ne (symbol_ref "optimize_size")
19465 (const_string "V4SF")
19466 (const_string "TI"))]
19467 (const_string "DI")))])
19470 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19471 (match_operand:TI 1 "general_operand" ""))]
19472 "reload_completed && !SSE_REG_P (operands[0])
19473 && !SSE_REG_P (operands[1])"
19475 "ix86_split_long_move (operands); DONE;")
19477 ;; These two patterns are useful for specifying exactly whether to use
19478 ;; movaps or movups
19479 (define_insn "sse_movaps"
19480 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19481 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19484 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19485 "movaps\t{%1, %0|%0, %1}"
19486 [(set_attr "type" "ssemov,ssemov")
19487 (set_attr "mode" "V4SF")])
19489 (define_insn "sse_movups"
19490 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19491 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19494 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19495 "movups\t{%1, %0|%0, %1}"
19496 [(set_attr "type" "ssecvt,ssecvt")
19497 (set_attr "mode" "V4SF")])
19500 ;; SSE Strange Moves.
19502 (define_insn "sse_movmskps"
19503 [(set (match_operand:SI 0 "register_operand" "=r")
19504 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19507 "movmskps\t{%1, %0|%0, %1}"
19508 [(set_attr "type" "ssecvt")
19509 (set_attr "mode" "V4SF")])
19511 (define_insn "mmx_pmovmskb"
19512 [(set (match_operand:SI 0 "register_operand" "=r")
19513 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19515 "TARGET_SSE || TARGET_3DNOW_A"
19516 "pmovmskb\t{%1, %0|%0, %1}"
19517 [(set_attr "type" "ssecvt")
19518 (set_attr "mode" "V4SF")])
19521 (define_insn "mmx_maskmovq"
19522 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19523 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19524 (match_operand:V8QI 2 "register_operand" "y")]
19526 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19527 ;; @@@ check ordering of operands in intel/nonintel syntax
19528 "maskmovq\t{%2, %1|%1, %2}"
19529 [(set_attr "type" "mmxcvt")
19530 (set_attr "mode" "DI")])
19532 (define_insn "mmx_maskmovq_rex"
19533 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19534 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19535 (match_operand:V8QI 2 "register_operand" "y")]
19537 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19538 ;; @@@ check ordering of operands in intel/nonintel syntax
19539 "maskmovq\t{%2, %1|%1, %2}"
19540 [(set_attr "type" "mmxcvt")
19541 (set_attr "mode" "DI")])
19543 (define_insn "sse_movntv4sf"
19544 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19545 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19548 "movntps\t{%1, %0|%0, %1}"
19549 [(set_attr "type" "ssemov")
19550 (set_attr "mode" "V4SF")])
19552 (define_insn "sse_movntdi"
19553 [(set (match_operand:DI 0 "memory_operand" "=m")
19554 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19556 "TARGET_SSE || TARGET_3DNOW_A"
19557 "movntq\t{%1, %0|%0, %1}"
19558 [(set_attr "type" "mmxmov")
19559 (set_attr "mode" "DI")])
19561 (define_insn "sse_movhlps"
19562 [(set (match_operand:V4SF 0 "register_operand" "=x")
19564 (match_operand:V4SF 1 "register_operand" "0")
19565 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19566 (parallel [(const_int 2)
19572 "movhlps\t{%2, %0|%0, %2}"
19573 [(set_attr "type" "ssecvt")
19574 (set_attr "mode" "V4SF")])
19576 (define_insn "sse_movlhps"
19577 [(set (match_operand:V4SF 0 "register_operand" "=x")
19579 (match_operand:V4SF 1 "register_operand" "0")
19580 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19581 (parallel [(const_int 2)
19587 "movlhps\t{%2, %0|%0, %2}"
19588 [(set_attr "type" "ssecvt")
19589 (set_attr "mode" "V4SF")])
19591 (define_insn "sse_movhps"
19592 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19594 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19595 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19598 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19599 "movhps\t{%2, %0|%0, %2}"
19600 [(set_attr "type" "ssecvt")
19601 (set_attr "mode" "V4SF")])
19603 (define_insn "sse_movlps"
19604 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19606 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19607 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19610 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19611 "movlps\t{%2, %0|%0, %2}"
19612 [(set_attr "type" "ssecvt")
19613 (set_attr "mode" "V4SF")])
19615 (define_expand "sse_loadss"
19616 [(match_operand:V4SF 0 "register_operand" "")
19617 (match_operand:SF 1 "memory_operand" "")]
19620 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19621 CONST0_RTX (V4SFmode)));
19625 (define_insn "sse_loadss_1"
19626 [(set (match_operand:V4SF 0 "register_operand" "=x")
19628 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19629 (match_operand:V4SF 2 "const0_operand" "X")
19632 "movss\t{%1, %0|%0, %1}"
19633 [(set_attr "type" "ssemov")
19634 (set_attr "mode" "SF")])
19636 (define_insn "sse_movss"
19637 [(set (match_operand:V4SF 0 "register_operand" "=x")
19639 (match_operand:V4SF 1 "register_operand" "0")
19640 (match_operand:V4SF 2 "register_operand" "x")
19643 "movss\t{%2, %0|%0, %2}"
19644 [(set_attr "type" "ssemov")
19645 (set_attr "mode" "SF")])
19647 (define_insn "sse_storess"
19648 [(set (match_operand:SF 0 "memory_operand" "=m")
19650 (match_operand:V4SF 1 "register_operand" "x")
19651 (parallel [(const_int 0)])))]
19653 "movss\t{%1, %0|%0, %1}"
19654 [(set_attr "type" "ssemov")
19655 (set_attr "mode" "SF")])
19657 (define_insn "sse_shufps"
19658 [(set (match_operand:V4SF 0 "register_operand" "=x")
19659 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19660 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19661 (match_operand:SI 3 "immediate_operand" "i")]
19664 ;; @@@ check operand order for intel/nonintel syntax
19665 "shufps\t{%3, %2, %0|%0, %2, %3}"
19666 [(set_attr "type" "ssecvt")
19667 (set_attr "mode" "V4SF")])
19672 (define_insn "addv4sf3"
19673 [(set (match_operand:V4SF 0 "register_operand" "=x")
19674 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19675 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19677 "addps\t{%2, %0|%0, %2}"
19678 [(set_attr "type" "sseadd")
19679 (set_attr "mode" "V4SF")])
19681 (define_insn "vmaddv4sf3"
19682 [(set (match_operand:V4SF 0 "register_operand" "=x")
19684 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19685 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19689 "addss\t{%2, %0|%0, %2}"
19690 [(set_attr "type" "sseadd")
19691 (set_attr "mode" "SF")])
19693 (define_insn "subv4sf3"
19694 [(set (match_operand:V4SF 0 "register_operand" "=x")
19695 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19696 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19698 "subps\t{%2, %0|%0, %2}"
19699 [(set_attr "type" "sseadd")
19700 (set_attr "mode" "V4SF")])
19702 (define_insn "vmsubv4sf3"
19703 [(set (match_operand:V4SF 0 "register_operand" "=x")
19705 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19706 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19710 "subss\t{%2, %0|%0, %2}"
19711 [(set_attr "type" "sseadd")
19712 (set_attr "mode" "SF")])
19714 (define_insn "mulv4sf3"
19715 [(set (match_operand:V4SF 0 "register_operand" "=x")
19716 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19717 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19719 "mulps\t{%2, %0|%0, %2}"
19720 [(set_attr "type" "ssemul")
19721 (set_attr "mode" "V4SF")])
19723 (define_insn "vmmulv4sf3"
19724 [(set (match_operand:V4SF 0 "register_operand" "=x")
19726 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19727 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19731 "mulss\t{%2, %0|%0, %2}"
19732 [(set_attr "type" "ssemul")
19733 (set_attr "mode" "SF")])
19735 (define_insn "divv4sf3"
19736 [(set (match_operand:V4SF 0 "register_operand" "=x")
19737 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19738 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19740 "divps\t{%2, %0|%0, %2}"
19741 [(set_attr "type" "ssediv")
19742 (set_attr "mode" "V4SF")])
19744 (define_insn "vmdivv4sf3"
19745 [(set (match_operand:V4SF 0 "register_operand" "=x")
19747 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19748 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19752 "divss\t{%2, %0|%0, %2}"
19753 [(set_attr "type" "ssediv")
19754 (set_attr "mode" "SF")])
19757 ;; SSE square root/reciprocal
19759 (define_insn "rcpv4sf2"
19760 [(set (match_operand:V4SF 0 "register_operand" "=x")
19762 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
19764 "rcpps\t{%1, %0|%0, %1}"
19765 [(set_attr "type" "sse")
19766 (set_attr "mode" "V4SF")])
19768 (define_insn "vmrcpv4sf2"
19769 [(set (match_operand:V4SF 0 "register_operand" "=x")
19771 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19773 (match_operand:V4SF 2 "register_operand" "0")
19776 "rcpss\t{%1, %0|%0, %1}"
19777 [(set_attr "type" "sse")
19778 (set_attr "mode" "SF")])
19780 (define_insn "rsqrtv4sf2"
19781 [(set (match_operand:V4SF 0 "register_operand" "=x")
19783 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
19785 "rsqrtps\t{%1, %0|%0, %1}"
19786 [(set_attr "type" "sse")
19787 (set_attr "mode" "V4SF")])
19789 (define_insn "vmrsqrtv4sf2"
19790 [(set (match_operand:V4SF 0 "register_operand" "=x")
19792 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19794 (match_operand:V4SF 2 "register_operand" "0")
19797 "rsqrtss\t{%1, %0|%0, %1}"
19798 [(set_attr "type" "sse")
19799 (set_attr "mode" "SF")])
19801 (define_insn "sqrtv4sf2"
19802 [(set (match_operand:V4SF 0 "register_operand" "=x")
19803 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19805 "sqrtps\t{%1, %0|%0, %1}"
19806 [(set_attr "type" "sse")
19807 (set_attr "mode" "V4SF")])
19809 (define_insn "vmsqrtv4sf2"
19810 [(set (match_operand:V4SF 0 "register_operand" "=x")
19812 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19813 (match_operand:V4SF 2 "register_operand" "0")
19816 "sqrtss\t{%1, %0|%0, %1}"
19817 [(set_attr "type" "sse")
19818 (set_attr "mode" "SF")])
19820 ;; SSE logical operations.
19822 ;; SSE defines logical operations on floating point values. This brings
19823 ;; interesting challenge to RTL representation where logicals are only valid
19824 ;; on integral types. We deal with this by representing the floating point
19825 ;; logical as logical on arguments casted to TImode as this is what hardware
19826 ;; really does. Unfortunately hardware requires the type information to be
19827 ;; present and thus we must avoid subregs from being simplified and eliminated
19828 ;; in later compilation phases.
19830 ;; We have following variants from each instruction:
19831 ;; sse_andsf3 - the operation taking V4SF vector operands
19832 ;; and doing TImode cast on them
19833 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
19834 ;; TImode, since backend insist on eliminating casts
19835 ;; on memory operands
19836 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
19837 ;; We can not accept memory operand here as instruction reads
19838 ;; whole scalar. This is generated only post reload by GCC
19839 ;; scalar float operations that expands to logicals (fabs)
19840 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
19841 ;; memory operand. Eventually combine can be able
19842 ;; to synthesize these using splitter.
19843 ;; sse2_anddf3, *sse2_anddf3_memory
19846 ;; These are not called andti3 etc. because we really really don't want
19847 ;; the compiler to widen DImode ands to TImode ands and then try to move
19848 ;; into DImode subregs of SSE registers, and them together, and move out
19849 ;; of DImode subregs again!
19850 ;; SSE1 single precision floating point logical operation
19851 (define_expand "sse_andv4sf3"
19852 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19853 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19854 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19858 (define_insn "*sse_andv4sf3"
19859 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19860 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19861 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19863 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19864 "andps\t{%2, %0|%0, %2}"
19865 [(set_attr "type" "sselog")
19866 (set_attr "mode" "V4SF")])
19868 (define_insn "*sse_andsf3"
19869 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19870 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19871 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19873 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19874 "andps\t{%2, %0|%0, %2}"
19875 [(set_attr "type" "sselog")
19876 (set_attr "mode" "V4SF")])
19878 (define_expand "sse_nandv4sf3"
19879 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19880 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19881 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19885 (define_insn "*sse_nandv4sf3"
19886 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19887 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19888 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19890 "andnps\t{%2, %0|%0, %2}"
19891 [(set_attr "type" "sselog")
19892 (set_attr "mode" "V4SF")])
19894 (define_insn "*sse_nandsf3"
19895 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19896 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19897 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19899 "andnps\t{%2, %0|%0, %2}"
19900 [(set_attr "type" "sselog")
19901 (set_attr "mode" "V4SF")])
19903 (define_expand "sse_iorv4sf3"
19904 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19905 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19906 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19910 (define_insn "*sse_iorv4sf3"
19911 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19912 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19913 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19915 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19916 "orps\t{%2, %0|%0, %2}"
19917 [(set_attr "type" "sselog")
19918 (set_attr "mode" "V4SF")])
19920 (define_insn "*sse_iorsf3"
19921 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19922 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19923 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19925 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19926 "orps\t{%2, %0|%0, %2}"
19927 [(set_attr "type" "sselog")
19928 (set_attr "mode" "V4SF")])
19930 (define_expand "sse_xorv4sf3"
19931 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19932 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19933 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19935 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19938 (define_insn "*sse_xorv4sf3"
19939 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19940 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19941 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19943 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19944 "xorps\t{%2, %0|%0, %2}"
19945 [(set_attr "type" "sselog")
19946 (set_attr "mode" "V4SF")])
19948 (define_insn "*sse_xorsf3"
19949 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19950 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19951 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19953 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19954 "xorps\t{%2, %0|%0, %2}"
19955 [(set_attr "type" "sselog")
19956 (set_attr "mode" "V4SF")])
19958 ;; SSE2 double precision floating point logical operation
19960 (define_expand "sse2_andv2df3"
19961 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19962 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19963 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19967 (define_insn "*sse2_andv2df3"
19968 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19969 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19970 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19972 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19973 "andpd\t{%2, %0|%0, %2}"
19974 [(set_attr "type" "sselog")
19975 (set_attr "mode" "V2DF")])
19977 (define_insn "*sse2_andv2df3"
19978 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19979 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19980 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19982 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19983 "andpd\t{%2, %0|%0, %2}"
19984 [(set_attr "type" "sselog")
19985 (set_attr "mode" "V2DF")])
19987 (define_expand "sse2_nandv2df3"
19988 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19989 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19990 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19994 (define_insn "*sse2_nandv2df3"
19995 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19996 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19997 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19999 "andnpd\t{%2, %0|%0, %2}"
20000 [(set_attr "type" "sselog")
20001 (set_attr "mode" "V2DF")])
20003 (define_insn "*sse_nandti3_df"
20004 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
20005 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20006 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
20008 "andnpd\t{%2, %0|%0, %2}"
20009 [(set_attr "type" "sselog")
20010 (set_attr "mode" "V2DF")])
20012 (define_expand "sse2_iorv2df3"
20013 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20014 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
20015 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20019 (define_insn "*sse2_iorv2df3"
20020 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20021 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20022 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20024 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20025 "orpd\t{%2, %0|%0, %2}"
20026 [(set_attr "type" "sselog")
20027 (set_attr "mode" "V2DF")])
20029 (define_insn "*sse2_iordf3"
20030 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
20031 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20032 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20034 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20035 "orpd\t{%2, %0|%0, %2}"
20036 [(set_attr "type" "sselog")
20037 (set_attr "mode" "V2DF")])
20039 (define_expand "sse2_xorv2df3"
20040 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20041 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
20042 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20046 (define_insn "*sse2_xorv2df3"
20047 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20048 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20049 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20051 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20052 "xorpd\t{%2, %0|%0, %2}"
20053 [(set_attr "type" "sselog")
20054 (set_attr "mode" "V2DF")])
20056 (define_insn "*sse2_xordf3"
20057 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
20058 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20059 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20061 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20062 "xorpd\t{%2, %0|%0, %2}"
20063 [(set_attr "type" "sselog")
20064 (set_attr "mode" "V2DF")])
20066 ;; SSE2 integral logicals. These patterns must always come after floating
20067 ;; point ones since we don't want compiler to use integer opcodes on floating
20068 ;; point SSE values to avoid matching of subregs in the match_operand.
20069 (define_insn "*sse2_andti3"
20070 [(set (match_operand:TI 0 "register_operand" "=x")
20071 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20072 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20074 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20075 "pand\t{%2, %0|%0, %2}"
20076 [(set_attr "type" "sselog")
20077 (set_attr "mode" "TI")])
20079 (define_insn "sse2_andv2di3"
20080 [(set (match_operand:V2DI 0 "register_operand" "=x")
20081 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20082 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20084 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20085 "pand\t{%2, %0|%0, %2}"
20086 [(set_attr "type" "sselog")
20087 (set_attr "mode" "TI")])
20089 (define_insn "*sse2_nandti3"
20090 [(set (match_operand:TI 0 "register_operand" "=x")
20091 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20092 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20094 "pandn\t{%2, %0|%0, %2}"
20095 [(set_attr "type" "sselog")
20096 (set_attr "mode" "TI")])
20098 (define_insn "sse2_nandv2di3"
20099 [(set (match_operand:V2DI 0 "register_operand" "=x")
20100 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "0"))
20101 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20103 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20104 "pandn\t{%2, %0|%0, %2}"
20105 [(set_attr "type" "sselog")
20106 (set_attr "mode" "TI")])
20108 (define_insn "*sse2_iorti3"
20109 [(set (match_operand:TI 0 "register_operand" "=x")
20110 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20111 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20113 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20114 "por\t{%2, %0|%0, %2}"
20115 [(set_attr "type" "sselog")
20116 (set_attr "mode" "TI")])
20118 (define_insn "sse2_iorv2di3"
20119 [(set (match_operand:V2DI 0 "register_operand" "=x")
20120 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20121 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20123 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20124 "por\t{%2, %0|%0, %2}"
20125 [(set_attr "type" "sselog")
20126 (set_attr "mode" "TI")])
20128 (define_insn "*sse2_xorti3"
20129 [(set (match_operand:TI 0 "register_operand" "=x")
20130 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20131 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20133 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20134 "pxor\t{%2, %0|%0, %2}"
20135 [(set_attr "type" "sselog")
20136 (set_attr "mode" "TI")])
20138 (define_insn "sse2_xorv2di3"
20139 [(set (match_operand:V2DI 0 "register_operand" "=x")
20140 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20141 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20143 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20144 "pxor\t{%2, %0|%0, %2}"
20145 [(set_attr "type" "sselog")
20146 (set_attr "mode" "TI")])
20148 ;; Use xor, but don't show input operands so they aren't live before
20150 (define_insn "sse_clrv4sf"
20151 [(set (match_operand:V4SF 0 "register_operand" "=x")
20152 (match_operand:V4SF 1 "const0_operand" "X"))]
20155 if (get_attr_mode (insn) == MODE_TI)
20156 return "pxor\t{%0, %0|%0, %0}";
20158 return "xorps\t{%0, %0|%0, %0}";
20160 [(set_attr "type" "sselog")
20161 (set_attr "memory" "none")
20164 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
20166 (ne (symbol_ref "TARGET_SSE2")
20168 (eq (symbol_ref "optimize_size")
20170 (const_string "TI")
20171 (const_string "V4SF")))])
20173 ;; Use xor, but don't show input operands so they aren't live before
20175 (define_insn "sse_clrv2df"
20176 [(set (match_operand:V2DF 0 "register_operand" "=x")
20177 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
20179 "xorpd\t{%0, %0|%0, %0}"
20180 [(set_attr "type" "sselog")
20181 (set_attr "memory" "none")
20182 (set_attr "mode" "V4SF")])
20184 ;; SSE mask-generating compares
20186 (define_insn "maskcmpv4sf3"
20187 [(set (match_operand:V4SI 0 "register_operand" "=x")
20188 (match_operator:V4SI 3 "sse_comparison_operator"
20189 [(match_operand:V4SF 1 "register_operand" "0")
20190 (match_operand:V4SF 2 "register_operand" "x")]))]
20192 "cmp%D3ps\t{%2, %0|%0, %2}"
20193 [(set_attr "type" "ssecmp")
20194 (set_attr "mode" "V4SF")])
20196 (define_insn "maskncmpv4sf3"
20197 [(set (match_operand:V4SI 0 "register_operand" "=x")
20199 (match_operator:V4SI 3 "sse_comparison_operator"
20200 [(match_operand:V4SF 1 "register_operand" "0")
20201 (match_operand:V4SF 2 "register_operand" "x")])))]
20204 if (GET_CODE (operands[3]) == UNORDERED)
20205 return "cmpordps\t{%2, %0|%0, %2}";
20207 return "cmpn%D3ps\t{%2, %0|%0, %2}";
20209 [(set_attr "type" "ssecmp")
20210 (set_attr "mode" "V4SF")])
20212 (define_insn "vmmaskcmpv4sf3"
20213 [(set (match_operand:V4SI 0 "register_operand" "=x")
20215 (match_operator:V4SI 3 "sse_comparison_operator"
20216 [(match_operand:V4SF 1 "register_operand" "0")
20217 (match_operand:V4SF 2 "register_operand" "x")])
20218 (subreg:V4SI (match_dup 1) 0)
20221 "cmp%D3ss\t{%2, %0|%0, %2}"
20222 [(set_attr "type" "ssecmp")
20223 (set_attr "mode" "SF")])
20225 (define_insn "vmmaskncmpv4sf3"
20226 [(set (match_operand:V4SI 0 "register_operand" "=x")
20229 (match_operator:V4SI 3 "sse_comparison_operator"
20230 [(match_operand:V4SF 1 "register_operand" "0")
20231 (match_operand:V4SF 2 "register_operand" "x")]))
20232 (subreg:V4SI (match_dup 1) 0)
20236 if (GET_CODE (operands[3]) == UNORDERED)
20237 return "cmpordss\t{%2, %0|%0, %2}";
20239 return "cmpn%D3ss\t{%2, %0|%0, %2}";
20241 [(set_attr "type" "ssecmp")
20242 (set_attr "mode" "SF")])
20244 (define_insn "sse_comi"
20245 [(set (reg:CCFP 17)
20246 (compare:CCFP (vec_select:SF
20247 (match_operand:V4SF 0 "register_operand" "x")
20248 (parallel [(const_int 0)]))
20250 (match_operand:V4SF 1 "register_operand" "x")
20251 (parallel [(const_int 0)]))))]
20253 "comiss\t{%1, %0|%0, %1}"
20254 [(set_attr "type" "ssecomi")
20255 (set_attr "mode" "SF")])
20257 (define_insn "sse_ucomi"
20258 [(set (reg:CCFPU 17)
20259 (compare:CCFPU (vec_select:SF
20260 (match_operand:V4SF 0 "register_operand" "x")
20261 (parallel [(const_int 0)]))
20263 (match_operand:V4SF 1 "register_operand" "x")
20264 (parallel [(const_int 0)]))))]
20266 "ucomiss\t{%1, %0|%0, %1}"
20267 [(set_attr "type" "ssecomi")
20268 (set_attr "mode" "SF")])
20273 (define_insn "sse_unpckhps"
20274 [(set (match_operand:V4SF 0 "register_operand" "=x")
20276 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20277 (parallel [(const_int 2)
20281 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20282 (parallel [(const_int 0)
20288 "unpckhps\t{%2, %0|%0, %2}"
20289 [(set_attr "type" "ssecvt")
20290 (set_attr "mode" "V4SF")])
20292 (define_insn "sse_unpcklps"
20293 [(set (match_operand:V4SF 0 "register_operand" "=x")
20295 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20296 (parallel [(const_int 0)
20300 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20301 (parallel [(const_int 2)
20307 "unpcklps\t{%2, %0|%0, %2}"
20308 [(set_attr "type" "ssecvt")
20309 (set_attr "mode" "V4SF")])
20314 (define_insn "smaxv4sf3"
20315 [(set (match_operand:V4SF 0 "register_operand" "=x")
20316 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20317 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20319 "maxps\t{%2, %0|%0, %2}"
20320 [(set_attr "type" "sse")
20321 (set_attr "mode" "V4SF")])
20323 (define_insn "vmsmaxv4sf3"
20324 [(set (match_operand:V4SF 0 "register_operand" "=x")
20326 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20327 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20331 "maxss\t{%2, %0|%0, %2}"
20332 [(set_attr "type" "sse")
20333 (set_attr "mode" "SF")])
20335 (define_insn "sminv4sf3"
20336 [(set (match_operand:V4SF 0 "register_operand" "=x")
20337 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20338 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20340 "minps\t{%2, %0|%0, %2}"
20341 [(set_attr "type" "sse")
20342 (set_attr "mode" "V4SF")])
20344 (define_insn "vmsminv4sf3"
20345 [(set (match_operand:V4SF 0 "register_operand" "=x")
20347 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20348 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20352 "minss\t{%2, %0|%0, %2}"
20353 [(set_attr "type" "sse")
20354 (set_attr "mode" "SF")])
20356 ;; SSE <-> integer/MMX conversions
20358 (define_insn "cvtpi2ps"
20359 [(set (match_operand:V4SF 0 "register_operand" "=x")
20361 (match_operand:V4SF 1 "register_operand" "0")
20362 (vec_duplicate:V4SF
20363 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
20366 "cvtpi2ps\t{%2, %0|%0, %2}"
20367 [(set_attr "type" "ssecvt")
20368 (set_attr "mode" "V4SF")])
20370 (define_insn "cvtps2pi"
20371 [(set (match_operand:V2SI 0 "register_operand" "=y")
20373 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20374 (parallel [(const_int 0) (const_int 1)])))]
20376 "cvtps2pi\t{%1, %0|%0, %1}"
20377 [(set_attr "type" "ssecvt")
20378 (set_attr "mode" "V4SF")])
20380 (define_insn "cvttps2pi"
20381 [(set (match_operand:V2SI 0 "register_operand" "=y")
20383 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20385 (parallel [(const_int 0) (const_int 1)])))]
20387 "cvttps2pi\t{%1, %0|%0, %1}"
20388 [(set_attr "type" "ssecvt")
20389 (set_attr "mode" "SF")])
20391 (define_insn "cvtsi2ss"
20392 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20394 (match_operand:V4SF 1 "register_operand" "0,0")
20395 (vec_duplicate:V4SF
20396 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
20399 "cvtsi2ss\t{%2, %0|%0, %2}"
20400 [(set_attr "type" "sseicvt")
20401 (set_attr "athlon_decode" "vector,double")
20402 (set_attr "mode" "SF")])
20404 (define_insn "cvtsi2ssq"
20405 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20407 (match_operand:V4SF 1 "register_operand" "0,0")
20408 (vec_duplicate:V4SF
20409 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20411 "TARGET_SSE && TARGET_64BIT"
20412 "cvtsi2ssq\t{%2, %0|%0, %2}"
20413 [(set_attr "type" "sseicvt")
20414 (set_attr "athlon_decode" "vector,double")
20415 (set_attr "mode" "SF")])
20417 (define_insn "cvtss2si"
20418 [(set (match_operand:SI 0 "register_operand" "=r,r")
20420 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20421 (parallel [(const_int 0)])))]
20423 "cvtss2si\t{%1, %0|%0, %1}"
20424 [(set_attr "type" "sseicvt")
20425 (set_attr "athlon_decode" "double,vector")
20426 (set_attr "mode" "SI")])
20428 (define_insn "cvtss2siq"
20429 [(set (match_operand:DI 0 "register_operand" "=r,r")
20431 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20432 (parallel [(const_int 0)])))]
20434 "cvtss2siq\t{%1, %0|%0, %1}"
20435 [(set_attr "type" "sseicvt")
20436 (set_attr "athlon_decode" "double,vector")
20437 (set_attr "mode" "DI")])
20439 (define_insn "cvttss2si"
20440 [(set (match_operand:SI 0 "register_operand" "=r,r")
20442 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20444 (parallel [(const_int 0)])))]
20446 "cvttss2si\t{%1, %0|%0, %1}"
20447 [(set_attr "type" "sseicvt")
20448 (set_attr "mode" "SF")
20449 (set_attr "athlon_decode" "double,vector")])
20451 (define_insn "cvttss2siq"
20452 [(set (match_operand:DI 0 "register_operand" "=r,r")
20454 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20456 (parallel [(const_int 0)])))]
20457 "TARGET_SSE && TARGET_64BIT"
20458 "cvttss2siq\t{%1, %0|%0, %1}"
20459 [(set_attr "type" "sseicvt")
20460 (set_attr "mode" "SF")
20461 (set_attr "athlon_decode" "double,vector")])
20468 (define_insn "addv8qi3"
20469 [(set (match_operand:V8QI 0 "register_operand" "=y")
20470 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20471 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20473 "paddb\t{%2, %0|%0, %2}"
20474 [(set_attr "type" "mmxadd")
20475 (set_attr "mode" "DI")])
20477 (define_insn "addv4hi3"
20478 [(set (match_operand:V4HI 0 "register_operand" "=y")
20479 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20480 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20482 "paddw\t{%2, %0|%0, %2}"
20483 [(set_attr "type" "mmxadd")
20484 (set_attr "mode" "DI")])
20486 (define_insn "addv2si3"
20487 [(set (match_operand:V2SI 0 "register_operand" "=y")
20488 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
20489 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20491 "paddd\t{%2, %0|%0, %2}"
20492 [(set_attr "type" "mmxadd")
20493 (set_attr "mode" "DI")])
20495 (define_insn "mmx_adddi3"
20496 [(set (match_operand:DI 0 "register_operand" "=y")
20498 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
20499 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20502 "paddq\t{%2, %0|%0, %2}"
20503 [(set_attr "type" "mmxadd")
20504 (set_attr "mode" "DI")])
20506 (define_insn "ssaddv8qi3"
20507 [(set (match_operand:V8QI 0 "register_operand" "=y")
20508 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20509 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20511 "paddsb\t{%2, %0|%0, %2}"
20512 [(set_attr "type" "mmxadd")
20513 (set_attr "mode" "DI")])
20515 (define_insn "ssaddv4hi3"
20516 [(set (match_operand:V4HI 0 "register_operand" "=y")
20517 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20518 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20520 "paddsw\t{%2, %0|%0, %2}"
20521 [(set_attr "type" "mmxadd")
20522 (set_attr "mode" "DI")])
20524 (define_insn "usaddv8qi3"
20525 [(set (match_operand:V8QI 0 "register_operand" "=y")
20526 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20527 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20529 "paddusb\t{%2, %0|%0, %2}"
20530 [(set_attr "type" "mmxadd")
20531 (set_attr "mode" "DI")])
20533 (define_insn "usaddv4hi3"
20534 [(set (match_operand:V4HI 0 "register_operand" "=y")
20535 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20536 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20538 "paddusw\t{%2, %0|%0, %2}"
20539 [(set_attr "type" "mmxadd")
20540 (set_attr "mode" "DI")])
20542 (define_insn "subv8qi3"
20543 [(set (match_operand:V8QI 0 "register_operand" "=y")
20544 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20545 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20547 "psubb\t{%2, %0|%0, %2}"
20548 [(set_attr "type" "mmxadd")
20549 (set_attr "mode" "DI")])
20551 (define_insn "subv4hi3"
20552 [(set (match_operand:V4HI 0 "register_operand" "=y")
20553 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20554 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20556 "psubw\t{%2, %0|%0, %2}"
20557 [(set_attr "type" "mmxadd")
20558 (set_attr "mode" "DI")])
20560 (define_insn "subv2si3"
20561 [(set (match_operand:V2SI 0 "register_operand" "=y")
20562 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20563 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20565 "psubd\t{%2, %0|%0, %2}"
20566 [(set_attr "type" "mmxadd")
20567 (set_attr "mode" "DI")])
20569 (define_insn "mmx_subdi3"
20570 [(set (match_operand:DI 0 "register_operand" "=y")
20572 [(minus:DI (match_operand:DI 1 "register_operand" "0")
20573 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20576 "psubq\t{%2, %0|%0, %2}"
20577 [(set_attr "type" "mmxadd")
20578 (set_attr "mode" "DI")])
20580 (define_insn "sssubv8qi3"
20581 [(set (match_operand:V8QI 0 "register_operand" "=y")
20582 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20583 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20585 "psubsb\t{%2, %0|%0, %2}"
20586 [(set_attr "type" "mmxadd")
20587 (set_attr "mode" "DI")])
20589 (define_insn "sssubv4hi3"
20590 [(set (match_operand:V4HI 0 "register_operand" "=y")
20591 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20592 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20594 "psubsw\t{%2, %0|%0, %2}"
20595 [(set_attr "type" "mmxadd")
20596 (set_attr "mode" "DI")])
20598 (define_insn "ussubv8qi3"
20599 [(set (match_operand:V8QI 0 "register_operand" "=y")
20600 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20601 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20603 "psubusb\t{%2, %0|%0, %2}"
20604 [(set_attr "type" "mmxadd")
20605 (set_attr "mode" "DI")])
20607 (define_insn "ussubv4hi3"
20608 [(set (match_operand:V4HI 0 "register_operand" "=y")
20609 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20610 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20612 "psubusw\t{%2, %0|%0, %2}"
20613 [(set_attr "type" "mmxadd")
20614 (set_attr "mode" "DI")])
20616 (define_insn "mulv4hi3"
20617 [(set (match_operand:V4HI 0 "register_operand" "=y")
20618 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20619 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20621 "pmullw\t{%2, %0|%0, %2}"
20622 [(set_attr "type" "mmxmul")
20623 (set_attr "mode" "DI")])
20625 (define_insn "smulv4hi3_highpart"
20626 [(set (match_operand:V4HI 0 "register_operand" "=y")
20629 (mult:V4SI (sign_extend:V4SI
20630 (match_operand:V4HI 1 "register_operand" "0"))
20632 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20635 "pmulhw\t{%2, %0|%0, %2}"
20636 [(set_attr "type" "mmxmul")
20637 (set_attr "mode" "DI")])
20639 (define_insn "umulv4hi3_highpart"
20640 [(set (match_operand:V4HI 0 "register_operand" "=y")
20643 (mult:V4SI (zero_extend:V4SI
20644 (match_operand:V4HI 1 "register_operand" "0"))
20646 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20648 "TARGET_SSE || TARGET_3DNOW_A"
20649 "pmulhuw\t{%2, %0|%0, %2}"
20650 [(set_attr "type" "mmxmul")
20651 (set_attr "mode" "DI")])
20653 (define_insn "mmx_pmaddwd"
20654 [(set (match_operand:V2SI 0 "register_operand" "=y")
20658 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20659 (parallel [(const_int 0) (const_int 2)])))
20661 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20662 (parallel [(const_int 0) (const_int 2)]))))
20664 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20665 (parallel [(const_int 1)
20667 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20668 (parallel [(const_int 1)
20669 (const_int 3)]))))))]
20671 "pmaddwd\t{%2, %0|%0, %2}"
20672 [(set_attr "type" "mmxmul")
20673 (set_attr "mode" "DI")])
20676 ;; MMX logical operations
20677 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20678 ;; normal code that also wants to use the FPU from getting broken.
20679 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20680 (define_insn "mmx_iordi3"
20681 [(set (match_operand:DI 0 "register_operand" "=y")
20683 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20684 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20687 "por\t{%2, %0|%0, %2}"
20688 [(set_attr "type" "mmxadd")
20689 (set_attr "mode" "DI")])
20691 (define_insn "mmx_xordi3"
20692 [(set (match_operand:DI 0 "register_operand" "=y")
20694 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20695 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20698 "pxor\t{%2, %0|%0, %2}"
20699 [(set_attr "type" "mmxadd")
20700 (set_attr "mode" "DI")
20701 (set_attr "memory" "none")])
20703 ;; Same as pxor, but don't show input operands so that we don't think
20705 (define_insn "mmx_clrdi"
20706 [(set (match_operand:DI 0 "register_operand" "=y")
20707 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20709 "pxor\t{%0, %0|%0, %0}"
20710 [(set_attr "type" "mmxadd")
20711 (set_attr "mode" "DI")
20712 (set_attr "memory" "none")])
20714 (define_insn "mmx_anddi3"
20715 [(set (match_operand:DI 0 "register_operand" "=y")
20717 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20718 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20721 "pand\t{%2, %0|%0, %2}"
20722 [(set_attr "type" "mmxadd")
20723 (set_attr "mode" "DI")])
20725 (define_insn "mmx_nanddi3"
20726 [(set (match_operand:DI 0 "register_operand" "=y")
20728 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20729 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20732 "pandn\t{%2, %0|%0, %2}"
20733 [(set_attr "type" "mmxadd")
20734 (set_attr "mode" "DI")])
20737 ;; MMX unsigned averages/sum of absolute differences
20739 (define_insn "mmx_uavgv8qi3"
20740 [(set (match_operand:V8QI 0 "register_operand" "=y")
20742 (plus:V8QI (plus:V8QI
20743 (match_operand:V8QI 1 "register_operand" "0")
20744 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20745 (const_vector:V8QI [(const_int 1)
20754 "TARGET_SSE || TARGET_3DNOW_A"
20755 "pavgb\t{%2, %0|%0, %2}"
20756 [(set_attr "type" "mmxshft")
20757 (set_attr "mode" "DI")])
20759 (define_insn "mmx_uavgv4hi3"
20760 [(set (match_operand:V4HI 0 "register_operand" "=y")
20762 (plus:V4HI (plus:V4HI
20763 (match_operand:V4HI 1 "register_operand" "0")
20764 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20765 (const_vector:V4HI [(const_int 1)
20770 "TARGET_SSE || TARGET_3DNOW_A"
20771 "pavgw\t{%2, %0|%0, %2}"
20772 [(set_attr "type" "mmxshft")
20773 (set_attr "mode" "DI")])
20775 (define_insn "mmx_psadbw"
20776 [(set (match_operand:DI 0 "register_operand" "=y")
20777 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20778 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20780 "TARGET_SSE || TARGET_3DNOW_A"
20781 "psadbw\t{%2, %0|%0, %2}"
20782 [(set_attr "type" "mmxshft")
20783 (set_attr "mode" "DI")])
20786 ;; MMX insert/extract/shuffle
20788 (define_insn "mmx_pinsrw"
20789 [(set (match_operand:V4HI 0 "register_operand" "=y")
20790 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
20791 (vec_duplicate:V4HI
20792 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
20793 (match_operand:SI 3 "immediate_operand" "i")))]
20794 "TARGET_SSE || TARGET_3DNOW_A"
20795 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20796 [(set_attr "type" "mmxcvt")
20797 (set_attr "mode" "DI")])
20799 (define_insn "mmx_pextrw"
20800 [(set (match_operand:SI 0 "register_operand" "=r")
20801 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20803 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20804 "TARGET_SSE || TARGET_3DNOW_A"
20805 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20806 [(set_attr "type" "mmxcvt")
20807 (set_attr "mode" "DI")])
20809 (define_insn "mmx_pshufw"
20810 [(set (match_operand:V4HI 0 "register_operand" "=y")
20811 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
20812 (match_operand:SI 2 "immediate_operand" "i")]
20814 "TARGET_SSE || TARGET_3DNOW_A"
20815 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20816 [(set_attr "type" "mmxcvt")
20817 (set_attr "mode" "DI")])
20820 ;; MMX mask-generating comparisons
20822 (define_insn "eqv8qi3"
20823 [(set (match_operand:V8QI 0 "register_operand" "=y")
20824 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20825 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20827 "pcmpeqb\t{%2, %0|%0, %2}"
20828 [(set_attr "type" "mmxcmp")
20829 (set_attr "mode" "DI")])
20831 (define_insn "eqv4hi3"
20832 [(set (match_operand:V4HI 0 "register_operand" "=y")
20833 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20834 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20836 "pcmpeqw\t{%2, %0|%0, %2}"
20837 [(set_attr "type" "mmxcmp")
20838 (set_attr "mode" "DI")])
20840 (define_insn "eqv2si3"
20841 [(set (match_operand:V2SI 0 "register_operand" "=y")
20842 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20843 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20845 "pcmpeqd\t{%2, %0|%0, %2}"
20846 [(set_attr "type" "mmxcmp")
20847 (set_attr "mode" "DI")])
20849 (define_insn "gtv8qi3"
20850 [(set (match_operand:V8QI 0 "register_operand" "=y")
20851 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20852 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20854 "pcmpgtb\t{%2, %0|%0, %2}"
20855 [(set_attr "type" "mmxcmp")
20856 (set_attr "mode" "DI")])
20858 (define_insn "gtv4hi3"
20859 [(set (match_operand:V4HI 0 "register_operand" "=y")
20860 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20861 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20863 "pcmpgtw\t{%2, %0|%0, %2}"
20864 [(set_attr "type" "mmxcmp")
20865 (set_attr "mode" "DI")])
20867 (define_insn "gtv2si3"
20868 [(set (match_operand:V2SI 0 "register_operand" "=y")
20869 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20870 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20872 "pcmpgtd\t{%2, %0|%0, %2}"
20873 [(set_attr "type" "mmxcmp")
20874 (set_attr "mode" "DI")])
20877 ;; MMX max/min insns
20879 (define_insn "umaxv8qi3"
20880 [(set (match_operand:V8QI 0 "register_operand" "=y")
20881 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20882 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20883 "TARGET_SSE || TARGET_3DNOW_A"
20884 "pmaxub\t{%2, %0|%0, %2}"
20885 [(set_attr "type" "mmxadd")
20886 (set_attr "mode" "DI")])
20888 (define_insn "smaxv4hi3"
20889 [(set (match_operand:V4HI 0 "register_operand" "=y")
20890 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20891 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20892 "TARGET_SSE || TARGET_3DNOW_A"
20893 "pmaxsw\t{%2, %0|%0, %2}"
20894 [(set_attr "type" "mmxadd")
20895 (set_attr "mode" "DI")])
20897 (define_insn "uminv8qi3"
20898 [(set (match_operand:V8QI 0 "register_operand" "=y")
20899 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20900 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20901 "TARGET_SSE || TARGET_3DNOW_A"
20902 "pminub\t{%2, %0|%0, %2}"
20903 [(set_attr "type" "mmxadd")
20904 (set_attr "mode" "DI")])
20906 (define_insn "sminv4hi3"
20907 [(set (match_operand:V4HI 0 "register_operand" "=y")
20908 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20909 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20910 "TARGET_SSE || TARGET_3DNOW_A"
20911 "pminsw\t{%2, %0|%0, %2}"
20912 [(set_attr "type" "mmxadd")
20913 (set_attr "mode" "DI")])
20918 (define_insn "ashrv4hi3"
20919 [(set (match_operand:V4HI 0 "register_operand" "=y")
20920 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20921 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20923 "psraw\t{%2, %0|%0, %2}"
20924 [(set_attr "type" "mmxshft")
20925 (set_attr "mode" "DI")])
20927 (define_insn "ashrv2si3"
20928 [(set (match_operand:V2SI 0 "register_operand" "=y")
20929 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20930 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20932 "psrad\t{%2, %0|%0, %2}"
20933 [(set_attr "type" "mmxshft")
20934 (set_attr "mode" "DI")])
20936 (define_insn "lshrv4hi3"
20937 [(set (match_operand:V4HI 0 "register_operand" "=y")
20938 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20939 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20941 "psrlw\t{%2, %0|%0, %2}"
20942 [(set_attr "type" "mmxshft")
20943 (set_attr "mode" "DI")])
20945 (define_insn "lshrv2si3"
20946 [(set (match_operand:V2SI 0 "register_operand" "=y")
20947 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20948 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20950 "psrld\t{%2, %0|%0, %2}"
20951 [(set_attr "type" "mmxshft")
20952 (set_attr "mode" "DI")])
20954 ;; See logical MMX insns.
20955 (define_insn "mmx_lshrdi3"
20956 [(set (match_operand:DI 0 "register_operand" "=y")
20958 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20959 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20962 "psrlq\t{%2, %0|%0, %2}"
20963 [(set_attr "type" "mmxshft")
20964 (set_attr "mode" "DI")])
20966 (define_insn "ashlv4hi3"
20967 [(set (match_operand:V4HI 0 "register_operand" "=y")
20968 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20969 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20971 "psllw\t{%2, %0|%0, %2}"
20972 [(set_attr "type" "mmxshft")
20973 (set_attr "mode" "DI")])
20975 (define_insn "ashlv2si3"
20976 [(set (match_operand:V2SI 0 "register_operand" "=y")
20977 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20978 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20980 "pslld\t{%2, %0|%0, %2}"
20981 [(set_attr "type" "mmxshft")
20982 (set_attr "mode" "DI")])
20984 ;; See logical MMX insns.
20985 (define_insn "mmx_ashldi3"
20986 [(set (match_operand:DI 0 "register_operand" "=y")
20988 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20989 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20992 "psllq\t{%2, %0|%0, %2}"
20993 [(set_attr "type" "mmxshft")
20994 (set_attr "mode" "DI")])
20997 ;; MMX pack/unpack insns.
20999 (define_insn "mmx_packsswb"
21000 [(set (match_operand:V8QI 0 "register_operand" "=y")
21002 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21003 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21005 "packsswb\t{%2, %0|%0, %2}"
21006 [(set_attr "type" "mmxshft")
21007 (set_attr "mode" "DI")])
21009 (define_insn "mmx_packssdw"
21010 [(set (match_operand:V4HI 0 "register_operand" "=y")
21012 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
21013 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
21015 "packssdw\t{%2, %0|%0, %2}"
21016 [(set_attr "type" "mmxshft")
21017 (set_attr "mode" "DI")])
21019 (define_insn "mmx_packuswb"
21020 [(set (match_operand:V8QI 0 "register_operand" "=y")
21022 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21023 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21025 "packuswb\t{%2, %0|%0, %2}"
21026 [(set_attr "type" "mmxshft")
21027 (set_attr "mode" "DI")])
21029 (define_insn "mmx_punpckhbw"
21030 [(set (match_operand:V8QI 0 "register_operand" "=y")
21032 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21033 (parallel [(const_int 4)
21041 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21042 (parallel [(const_int 0)
21052 "punpckhbw\t{%2, %0|%0, %2}"
21053 [(set_attr "type" "mmxcvt")
21054 (set_attr "mode" "DI")])
21056 (define_insn "mmx_punpckhwd"
21057 [(set (match_operand:V4HI 0 "register_operand" "=y")
21059 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21060 (parallel [(const_int 0)
21064 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21065 (parallel [(const_int 2)
21071 "punpckhwd\t{%2, %0|%0, %2}"
21072 [(set_attr "type" "mmxcvt")
21073 (set_attr "mode" "DI")])
21075 (define_insn "mmx_punpckhdq"
21076 [(set (match_operand:V2SI 0 "register_operand" "=y")
21078 (match_operand:V2SI 1 "register_operand" "0")
21079 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
21080 (parallel [(const_int 1)
21084 "punpckhdq\t{%2, %0|%0, %2}"
21085 [(set_attr "type" "mmxcvt")
21086 (set_attr "mode" "DI")])
21088 (define_insn "mmx_punpcklbw"
21089 [(set (match_operand:V8QI 0 "register_operand" "=y")
21091 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21092 (parallel [(const_int 0)
21100 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21101 (parallel [(const_int 4)
21111 "punpcklbw\t{%2, %0|%0, %2}"
21112 [(set_attr "type" "mmxcvt")
21113 (set_attr "mode" "DI")])
21115 (define_insn "mmx_punpcklwd"
21116 [(set (match_operand:V4HI 0 "register_operand" "=y")
21118 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21119 (parallel [(const_int 2)
21123 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21124 (parallel [(const_int 0)
21130 "punpcklwd\t{%2, %0|%0, %2}"
21131 [(set_attr "type" "mmxcvt")
21132 (set_attr "mode" "DI")])
21134 (define_insn "mmx_punpckldq"
21135 [(set (match_operand:V2SI 0 "register_operand" "=y")
21137 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
21138 (parallel [(const_int 1)
21140 (match_operand:V2SI 2 "register_operand" "y")
21143 "punpckldq\t{%2, %0|%0, %2}"
21144 [(set_attr "type" "mmxcvt")
21145 (set_attr "mode" "DI")])
21148 ;; Miscellaneous stuff
21150 (define_insn "emms"
21151 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
21152 (clobber (reg:XF 8))
21153 (clobber (reg:XF 9))
21154 (clobber (reg:XF 10))
21155 (clobber (reg:XF 11))
21156 (clobber (reg:XF 12))
21157 (clobber (reg:XF 13))
21158 (clobber (reg:XF 14))
21159 (clobber (reg:XF 15))
21160 (clobber (reg:DI 29))
21161 (clobber (reg:DI 30))
21162 (clobber (reg:DI 31))
21163 (clobber (reg:DI 32))
21164 (clobber (reg:DI 33))
21165 (clobber (reg:DI 34))
21166 (clobber (reg:DI 35))
21167 (clobber (reg:DI 36))]
21170 [(set_attr "type" "mmx")
21171 (set_attr "memory" "unknown")])
21173 (define_insn "ldmxcsr"
21174 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
21178 [(set_attr "type" "sse")
21179 (set_attr "memory" "load")])
21181 (define_insn "stmxcsr"
21182 [(set (match_operand:SI 0 "memory_operand" "=m")
21183 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
21186 [(set_attr "type" "sse")
21187 (set_attr "memory" "store")])
21189 (define_expand "sfence"
21190 [(set (match_dup 0)
21191 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21192 "TARGET_SSE || TARGET_3DNOW_A"
21194 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21195 MEM_VOLATILE_P (operands[0]) = 1;
21198 (define_insn "*sfence_insn"
21199 [(set (match_operand:BLK 0 "" "")
21200 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21201 "TARGET_SSE || TARGET_3DNOW_A"
21203 [(set_attr "type" "sse")
21204 (set_attr "memory" "unknown")])
21206 (define_expand "sse_prologue_save"
21207 [(parallel [(set (match_operand:BLK 0 "" "")
21208 (unspec:BLK [(reg:DI 21)
21215 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21216 (use (match_operand:DI 1 "register_operand" ""))
21217 (use (match_operand:DI 2 "immediate_operand" ""))
21218 (use (label_ref:DI (match_operand 3 "" "")))])]
21222 (define_insn "*sse_prologue_save_insn"
21223 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
21224 (match_operand:DI 4 "const_int_operand" "n")))
21225 (unspec:BLK [(reg:DI 21)
21232 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21233 (use (match_operand:DI 1 "register_operand" "r"))
21234 (use (match_operand:DI 2 "const_int_operand" "i"))
21235 (use (label_ref:DI (match_operand 3 "" "X")))]
21237 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
21238 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
21242 operands[0] = gen_rtx_MEM (Pmode,
21243 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
21244 output_asm_insn (\"jmp\\t%A1\", operands);
21245 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
21247 operands[4] = adjust_address (operands[0], DImode, i*16);
21248 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
21249 PUT_MODE (operands[4], TImode);
21250 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
21251 output_asm_insn (\"rex\", operands);
21252 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
21254 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
21255 CODE_LABEL_NUMBER (operands[3]));
21259 [(set_attr "type" "other")
21260 (set_attr "length_immediate" "0")
21261 (set_attr "length_address" "0")
21262 (set_attr "length" "135")
21263 (set_attr "memory" "store")
21264 (set_attr "modrm" "0")
21265 (set_attr "mode" "DI")])
21267 ;; 3Dnow! instructions
21269 (define_insn "addv2sf3"
21270 [(set (match_operand:V2SF 0 "register_operand" "=y")
21271 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21272 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21274 "pfadd\\t{%2, %0|%0, %2}"
21275 [(set_attr "type" "mmxadd")
21276 (set_attr "mode" "V2SF")])
21278 (define_insn "subv2sf3"
21279 [(set (match_operand:V2SF 0 "register_operand" "=y")
21280 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21281 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21283 "pfsub\\t{%2, %0|%0, %2}"
21284 [(set_attr "type" "mmxadd")
21285 (set_attr "mode" "V2SF")])
21287 (define_insn "subrv2sf3"
21288 [(set (match_operand:V2SF 0 "register_operand" "=y")
21289 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
21290 (match_operand:V2SF 1 "register_operand" "0")))]
21292 "pfsubr\\t{%2, %0|%0, %2}"
21293 [(set_attr "type" "mmxadd")
21294 (set_attr "mode" "V2SF")])
21296 (define_insn "gtv2sf3"
21297 [(set (match_operand:V2SI 0 "register_operand" "=y")
21298 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
21299 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21301 "pfcmpgt\\t{%2, %0|%0, %2}"
21302 [(set_attr "type" "mmxcmp")
21303 (set_attr "mode" "V2SF")])
21305 (define_insn "gev2sf3"
21306 [(set (match_operand:V2SI 0 "register_operand" "=y")
21307 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
21308 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21310 "pfcmpge\\t{%2, %0|%0, %2}"
21311 [(set_attr "type" "mmxcmp")
21312 (set_attr "mode" "V2SF")])
21314 (define_insn "eqv2sf3"
21315 [(set (match_operand:V2SI 0 "register_operand" "=y")
21316 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
21317 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21319 "pfcmpeq\\t{%2, %0|%0, %2}"
21320 [(set_attr "type" "mmxcmp")
21321 (set_attr "mode" "V2SF")])
21323 (define_insn "pfmaxv2sf3"
21324 [(set (match_operand:V2SF 0 "register_operand" "=y")
21325 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
21326 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21328 "pfmax\\t{%2, %0|%0, %2}"
21329 [(set_attr "type" "mmxadd")
21330 (set_attr "mode" "V2SF")])
21332 (define_insn "pfminv2sf3"
21333 [(set (match_operand:V2SF 0 "register_operand" "=y")
21334 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
21335 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21337 "pfmin\\t{%2, %0|%0, %2}"
21338 [(set_attr "type" "mmxadd")
21339 (set_attr "mode" "V2SF")])
21341 (define_insn "mulv2sf3"
21342 [(set (match_operand:V2SF 0 "register_operand" "=y")
21343 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
21344 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21346 "pfmul\\t{%2, %0|%0, %2}"
21347 [(set_attr "type" "mmxmul")
21348 (set_attr "mode" "V2SF")])
21350 (define_insn "femms"
21351 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
21352 (clobber (reg:XF 8))
21353 (clobber (reg:XF 9))
21354 (clobber (reg:XF 10))
21355 (clobber (reg:XF 11))
21356 (clobber (reg:XF 12))
21357 (clobber (reg:XF 13))
21358 (clobber (reg:XF 14))
21359 (clobber (reg:XF 15))
21360 (clobber (reg:DI 29))
21361 (clobber (reg:DI 30))
21362 (clobber (reg:DI 31))
21363 (clobber (reg:DI 32))
21364 (clobber (reg:DI 33))
21365 (clobber (reg:DI 34))
21366 (clobber (reg:DI 35))
21367 (clobber (reg:DI 36))]
21370 [(set_attr "type" "mmx")
21371 (set_attr "memory" "none")])
21373 (define_insn "pf2id"
21374 [(set (match_operand:V2SI 0 "register_operand" "=y")
21375 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
21377 "pf2id\\t{%1, %0|%0, %1}"
21378 [(set_attr "type" "mmxcvt")
21379 (set_attr "mode" "V2SF")])
21381 (define_insn "pf2iw"
21382 [(set (match_operand:V2SI 0 "register_operand" "=y")
21385 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
21387 "pf2iw\\t{%1, %0|%0, %1}"
21388 [(set_attr "type" "mmxcvt")
21389 (set_attr "mode" "V2SF")])
21391 (define_insn "pfacc"
21392 [(set (match_operand:V2SF 0 "register_operand" "=y")
21395 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21396 (parallel [(const_int 0)]))
21397 (vec_select:SF (match_dup 1)
21398 (parallel [(const_int 1)])))
21400 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21401 (parallel [(const_int 0)]))
21402 (vec_select:SF (match_dup 2)
21403 (parallel [(const_int 1)])))))]
21405 "pfacc\\t{%2, %0|%0, %2}"
21406 [(set_attr "type" "mmxadd")
21407 (set_attr "mode" "V2SF")])
21409 (define_insn "pfnacc"
21410 [(set (match_operand:V2SF 0 "register_operand" "=y")
21413 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21414 (parallel [(const_int 0)]))
21415 (vec_select:SF (match_dup 1)
21416 (parallel [(const_int 1)])))
21418 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21419 (parallel [(const_int 0)]))
21420 (vec_select:SF (match_dup 2)
21421 (parallel [(const_int 1)])))))]
21423 "pfnacc\\t{%2, %0|%0, %2}"
21424 [(set_attr "type" "mmxadd")
21425 (set_attr "mode" "V2SF")])
21427 (define_insn "pfpnacc"
21428 [(set (match_operand:V2SF 0 "register_operand" "=y")
21431 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21432 (parallel [(const_int 0)]))
21433 (vec_select:SF (match_dup 1)
21434 (parallel [(const_int 1)])))
21436 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21437 (parallel [(const_int 0)]))
21438 (vec_select:SF (match_dup 2)
21439 (parallel [(const_int 1)])))))]
21441 "pfpnacc\\t{%2, %0|%0, %2}"
21442 [(set_attr "type" "mmxadd")
21443 (set_attr "mode" "V2SF")])
21445 (define_insn "pi2fw"
21446 [(set (match_operand:V2SF 0 "register_operand" "=y")
21451 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21452 (parallel [(const_int 0)]))))
21455 (vec_select:SI (match_dup 1)
21456 (parallel [(const_int 1)])))))))]
21458 "pi2fw\\t{%1, %0|%0, %1}"
21459 [(set_attr "type" "mmxcvt")
21460 (set_attr "mode" "V2SF")])
21462 (define_insn "floatv2si2"
21463 [(set (match_operand:V2SF 0 "register_operand" "=y")
21464 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21466 "pi2fd\\t{%1, %0|%0, %1}"
21467 [(set_attr "type" "mmxcvt")
21468 (set_attr "mode" "V2SF")])
21470 ;; This insn is identical to pavgb in operation, but the opcode is
21471 ;; different. To avoid accidentally matching pavgb, use an unspec.
21473 (define_insn "pavgusb"
21474 [(set (match_operand:V8QI 0 "register_operand" "=y")
21476 [(match_operand:V8QI 1 "register_operand" "0")
21477 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21480 "pavgusb\\t{%2, %0|%0, %2}"
21481 [(set_attr "type" "mmxshft")
21482 (set_attr "mode" "TI")])
21484 ;; 3DNow reciprocal and sqrt
21486 (define_insn "pfrcpv2sf2"
21487 [(set (match_operand:V2SF 0 "register_operand" "=y")
21488 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21491 "pfrcp\\t{%1, %0|%0, %1}"
21492 [(set_attr "type" "mmx")
21493 (set_attr "mode" "TI")])
21495 (define_insn "pfrcpit1v2sf3"
21496 [(set (match_operand:V2SF 0 "register_operand" "=y")
21497 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21498 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21501 "pfrcpit1\\t{%2, %0|%0, %2}"
21502 [(set_attr "type" "mmx")
21503 (set_attr "mode" "TI")])
21505 (define_insn "pfrcpit2v2sf3"
21506 [(set (match_operand:V2SF 0 "register_operand" "=y")
21507 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21508 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21511 "pfrcpit2\\t{%2, %0|%0, %2}"
21512 [(set_attr "type" "mmx")
21513 (set_attr "mode" "TI")])
21515 (define_insn "pfrsqrtv2sf2"
21516 [(set (match_operand:V2SF 0 "register_operand" "=y")
21517 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21520 "pfrsqrt\\t{%1, %0|%0, %1}"
21521 [(set_attr "type" "mmx")
21522 (set_attr "mode" "TI")])
21524 (define_insn "pfrsqit1v2sf3"
21525 [(set (match_operand:V2SF 0 "register_operand" "=y")
21526 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21527 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21530 "pfrsqit1\\t{%2, %0|%0, %2}"
21531 [(set_attr "type" "mmx")
21532 (set_attr "mode" "TI")])
21534 (define_insn "pmulhrwv4hi3"
21535 [(set (match_operand:V4HI 0 "register_operand" "=y")
21541 (match_operand:V4HI 1 "register_operand" "0"))
21543 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21544 (const_vector:V4SI [(const_int 32768)
21547 (const_int 32768)]))
21550 "pmulhrw\\t{%2, %0|%0, %2}"
21551 [(set_attr "type" "mmxmul")
21552 (set_attr "mode" "TI")])
21554 (define_insn "pswapdv2si2"
21555 [(set (match_operand:V2SI 0 "register_operand" "=y")
21556 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21557 (parallel [(const_int 1) (const_int 0)])))]
21559 "pswapd\\t{%1, %0|%0, %1}"
21560 [(set_attr "type" "mmxcvt")
21561 (set_attr "mode" "TI")])
21563 (define_insn "pswapdv2sf2"
21564 [(set (match_operand:V2SF 0 "register_operand" "=y")
21565 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21566 (parallel [(const_int 1) (const_int 0)])))]
21568 "pswapd\\t{%1, %0|%0, %1}"
21569 [(set_attr "type" "mmxcvt")
21570 (set_attr "mode" "TI")])
21572 (define_expand "prefetch"
21573 [(prefetch (match_operand 0 "address_operand" "")
21574 (match_operand:SI 1 "const_int_operand" "")
21575 (match_operand:SI 2 "const_int_operand" ""))]
21576 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21578 int rw = INTVAL (operands[1]);
21579 int locality = INTVAL (operands[2]);
21581 if (rw != 0 && rw != 1)
21583 if (locality < 0 || locality > 3)
21585 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21588 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21589 suported by SSE counterpart or the SSE prefetch is not available
21590 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21592 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21593 operands[2] = GEN_INT (3);
21595 operands[1] = const0_rtx;
21598 (define_insn "*prefetch_sse"
21599 [(prefetch (match_operand:SI 0 "address_operand" "p")
21601 (match_operand:SI 1 "const_int_operand" ""))]
21602 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21604 static const char * const patterns[4] = {
21605 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21608 int locality = INTVAL (operands[1]);
21609 if (locality < 0 || locality > 3)
21612 return patterns[locality];
21614 [(set_attr "type" "sse")
21615 (set_attr "memory" "none")])
21617 (define_insn "*prefetch_sse_rex"
21618 [(prefetch (match_operand:DI 0 "address_operand" "p")
21620 (match_operand:SI 1 "const_int_operand" ""))]
21621 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21623 static const char * const patterns[4] = {
21624 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21627 int locality = INTVAL (operands[1]);
21628 if (locality < 0 || locality > 3)
21631 return patterns[locality];
21633 [(set_attr "type" "sse")
21634 (set_attr "memory" "none")])
21636 (define_insn "*prefetch_3dnow"
21637 [(prefetch (match_operand:SI 0 "address_operand" "p")
21638 (match_operand:SI 1 "const_int_operand" "n")
21640 "TARGET_3DNOW && !TARGET_64BIT"
21642 if (INTVAL (operands[1]) == 0)
21643 return "prefetch\t%a0";
21645 return "prefetchw\t%a0";
21647 [(set_attr "type" "mmx")
21648 (set_attr "memory" "none")])
21650 (define_insn "*prefetch_3dnow_rex"
21651 [(prefetch (match_operand:DI 0 "address_operand" "p")
21652 (match_operand:SI 1 "const_int_operand" "n")
21654 "TARGET_3DNOW && TARGET_64BIT"
21656 if (INTVAL (operands[1]) == 0)
21657 return "prefetch\t%a0";
21659 return "prefetchw\t%a0";
21661 [(set_attr "type" "mmx")
21662 (set_attr "memory" "none")])
21666 (define_insn "addv2df3"
21667 [(set (match_operand:V2DF 0 "register_operand" "=x")
21668 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21669 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21671 "addpd\t{%2, %0|%0, %2}"
21672 [(set_attr "type" "sseadd")
21673 (set_attr "mode" "V2DF")])
21675 (define_insn "vmaddv2df3"
21676 [(set (match_operand:V2DF 0 "register_operand" "=x")
21677 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21678 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21682 "addsd\t{%2, %0|%0, %2}"
21683 [(set_attr "type" "sseadd")
21684 (set_attr "mode" "DF")])
21686 (define_insn "subv2df3"
21687 [(set (match_operand:V2DF 0 "register_operand" "=x")
21688 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21689 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21691 "subpd\t{%2, %0|%0, %2}"
21692 [(set_attr "type" "sseadd")
21693 (set_attr "mode" "V2DF")])
21695 (define_insn "vmsubv2df3"
21696 [(set (match_operand:V2DF 0 "register_operand" "=x")
21697 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21698 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21702 "subsd\t{%2, %0|%0, %2}"
21703 [(set_attr "type" "sseadd")
21704 (set_attr "mode" "DF")])
21706 (define_insn "mulv2df3"
21707 [(set (match_operand:V2DF 0 "register_operand" "=x")
21708 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21709 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21711 "mulpd\t{%2, %0|%0, %2}"
21712 [(set_attr "type" "ssemul")
21713 (set_attr "mode" "V2DF")])
21715 (define_insn "vmmulv2df3"
21716 [(set (match_operand:V2DF 0 "register_operand" "=x")
21717 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21718 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21722 "mulsd\t{%2, %0|%0, %2}"
21723 [(set_attr "type" "ssemul")
21724 (set_attr "mode" "DF")])
21726 (define_insn "divv2df3"
21727 [(set (match_operand:V2DF 0 "register_operand" "=x")
21728 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21729 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21731 "divpd\t{%2, %0|%0, %2}"
21732 [(set_attr "type" "ssediv")
21733 (set_attr "mode" "V2DF")])
21735 (define_insn "vmdivv2df3"
21736 [(set (match_operand:V2DF 0 "register_operand" "=x")
21737 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21738 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21742 "divsd\t{%2, %0|%0, %2}"
21743 [(set_attr "type" "ssediv")
21744 (set_attr "mode" "DF")])
21748 (define_insn "smaxv2df3"
21749 [(set (match_operand:V2DF 0 "register_operand" "=x")
21750 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21751 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21753 "maxpd\t{%2, %0|%0, %2}"
21754 [(set_attr "type" "sseadd")
21755 (set_attr "mode" "V2DF")])
21757 (define_insn "vmsmaxv2df3"
21758 [(set (match_operand:V2DF 0 "register_operand" "=x")
21759 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21760 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21764 "maxsd\t{%2, %0|%0, %2}"
21765 [(set_attr "type" "sseadd")
21766 (set_attr "mode" "DF")])
21768 (define_insn "sminv2df3"
21769 [(set (match_operand:V2DF 0 "register_operand" "=x")
21770 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21771 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21773 "minpd\t{%2, %0|%0, %2}"
21774 [(set_attr "type" "sseadd")
21775 (set_attr "mode" "V2DF")])
21777 (define_insn "vmsminv2df3"
21778 [(set (match_operand:V2DF 0 "register_operand" "=x")
21779 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21780 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21784 "minsd\t{%2, %0|%0, %2}"
21785 [(set_attr "type" "sseadd")
21786 (set_attr "mode" "DF")])
21787 ;; SSE2 square root. There doesn't appear to be an extension for the
21788 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
21790 (define_insn "sqrtv2df2"
21791 [(set (match_operand:V2DF 0 "register_operand" "=x")
21792 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
21794 "sqrtpd\t{%1, %0|%0, %1}"
21795 [(set_attr "type" "sse")
21796 (set_attr "mode" "V2DF")])
21798 (define_insn "vmsqrtv2df2"
21799 [(set (match_operand:V2DF 0 "register_operand" "=x")
21800 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
21801 (match_operand:V2DF 2 "register_operand" "0")
21804 "sqrtsd\t{%1, %0|%0, %1}"
21805 [(set_attr "type" "sse")
21806 (set_attr "mode" "SF")])
21808 ;; SSE mask-generating compares
21810 (define_insn "maskcmpv2df3"
21811 [(set (match_operand:V2DI 0 "register_operand" "=x")
21812 (match_operator:V2DI 3 "sse_comparison_operator"
21813 [(match_operand:V2DF 1 "register_operand" "0")
21814 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
21816 "cmp%D3pd\t{%2, %0|%0, %2}"
21817 [(set_attr "type" "ssecmp")
21818 (set_attr "mode" "V2DF")])
21820 (define_insn "maskncmpv2df3"
21821 [(set (match_operand:V2DI 0 "register_operand" "=x")
21823 (match_operator:V2DI 3 "sse_comparison_operator"
21824 [(match_operand:V2DF 1 "register_operand" "0")
21825 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
21828 if (GET_CODE (operands[3]) == UNORDERED)
21829 return "cmpordps\t{%2, %0|%0, %2}";
21831 return "cmpn%D3pd\t{%2, %0|%0, %2}";
21833 [(set_attr "type" "ssecmp")
21834 (set_attr "mode" "V2DF")])
21836 (define_insn "vmmaskcmpv2df3"
21837 [(set (match_operand:V2DI 0 "register_operand" "=x")
21839 (match_operator:V2DI 3 "sse_comparison_operator"
21840 [(match_operand:V2DF 1 "register_operand" "0")
21841 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
21842 (subreg:V2DI (match_dup 1) 0)
21845 "cmp%D3sd\t{%2, %0|%0, %2}"
21846 [(set_attr "type" "ssecmp")
21847 (set_attr "mode" "DF")])
21849 (define_insn "vmmaskncmpv2df3"
21850 [(set (match_operand:V2DI 0 "register_operand" "=x")
21853 (match_operator:V2DI 3 "sse_comparison_operator"
21854 [(match_operand:V2DF 1 "register_operand" "0")
21855 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
21856 (subreg:V2DI (match_dup 1) 0)
21860 if (GET_CODE (operands[3]) == UNORDERED)
21861 return "cmpordsd\t{%2, %0|%0, %2}";
21863 return "cmpn%D3sd\t{%2, %0|%0, %2}";
21865 [(set_attr "type" "ssecmp")
21866 (set_attr "mode" "DF")])
21868 (define_insn "sse2_comi"
21869 [(set (reg:CCFP 17)
21870 (compare:CCFP (vec_select:DF
21871 (match_operand:V2DF 0 "register_operand" "x")
21872 (parallel [(const_int 0)]))
21874 (match_operand:V2DF 1 "register_operand" "x")
21875 (parallel [(const_int 0)]))))]
21877 "comisd\t{%1, %0|%0, %1}"
21878 [(set_attr "type" "ssecomi")
21879 (set_attr "mode" "DF")])
21881 (define_insn "sse2_ucomi"
21882 [(set (reg:CCFPU 17)
21883 (compare:CCFPU (vec_select:DF
21884 (match_operand:V2DF 0 "register_operand" "x")
21885 (parallel [(const_int 0)]))
21887 (match_operand:V2DF 1 "register_operand" "x")
21888 (parallel [(const_int 0)]))))]
21890 "ucomisd\t{%1, %0|%0, %1}"
21891 [(set_attr "type" "ssecomi")
21892 (set_attr "mode" "DF")])
21894 ;; SSE Strange Moves.
21896 (define_insn "sse2_movmskpd"
21897 [(set (match_operand:SI 0 "register_operand" "=r")
21898 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
21901 "movmskpd\t{%1, %0|%0, %1}"
21902 [(set_attr "type" "ssecvt")
21903 (set_attr "mode" "V2DF")])
21905 (define_insn "sse2_pmovmskb"
21906 [(set (match_operand:SI 0 "register_operand" "=r")
21907 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
21910 "pmovmskb\t{%1, %0|%0, %1}"
21911 [(set_attr "type" "ssecvt")
21912 (set_attr "mode" "V2DF")])
21914 (define_insn "sse2_maskmovdqu"
21915 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
21916 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21917 (match_operand:V16QI 2 "register_operand" "x")]
21920 ;; @@@ check ordering of operands in intel/nonintel syntax
21921 "maskmovdqu\t{%2, %1|%1, %2}"
21922 [(set_attr "type" "ssecvt")
21923 (set_attr "mode" "TI")])
21925 (define_insn "sse2_maskmovdqu_rex64"
21926 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
21927 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21928 (match_operand:V16QI 2 "register_operand" "x")]
21931 ;; @@@ check ordering of operands in intel/nonintel syntax
21932 "maskmovdqu\t{%2, %1|%1, %2}"
21933 [(set_attr "type" "ssecvt")
21934 (set_attr "mode" "TI")])
21936 (define_insn "sse2_movntv2df"
21937 [(set (match_operand:V2DF 0 "memory_operand" "=m")
21938 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
21941 "movntpd\t{%1, %0|%0, %1}"
21942 [(set_attr "type" "ssecvt")
21943 (set_attr "mode" "V2DF")])
21945 (define_insn "sse2_movntv2di"
21946 [(set (match_operand:V2DI 0 "memory_operand" "=m")
21947 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
21950 "movntdq\t{%1, %0|%0, %1}"
21951 [(set_attr "type" "ssecvt")
21952 (set_attr "mode" "TI")])
21954 (define_insn "sse2_movntsi"
21955 [(set (match_operand:SI 0 "memory_operand" "=m")
21956 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
21959 "movnti\t{%1, %0|%0, %1}"
21960 [(set_attr "type" "ssecvt")
21961 (set_attr "mode" "V2DF")])
21963 ;; SSE <-> integer/MMX conversions
21965 ;; Conversions between SI and SF
21967 (define_insn "cvtdq2ps"
21968 [(set (match_operand:V4SF 0 "register_operand" "=x")
21969 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
21971 "cvtdq2ps\t{%1, %0|%0, %1}"
21972 [(set_attr "type" "ssecvt")
21973 (set_attr "mode" "V2DF")])
21975 (define_insn "cvtps2dq"
21976 [(set (match_operand:V4SI 0 "register_operand" "=x")
21977 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21979 "cvtps2dq\t{%1, %0|%0, %1}"
21980 [(set_attr "type" "ssecvt")
21981 (set_attr "mode" "TI")])
21983 (define_insn "cvttps2dq"
21984 [(set (match_operand:V4SI 0 "register_operand" "=x")
21985 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21988 "cvttps2dq\t{%1, %0|%0, %1}"
21989 [(set_attr "type" "ssecvt")
21990 (set_attr "mode" "TI")])
21992 ;; Conversions between SI and DF
21994 (define_insn "cvtdq2pd"
21995 [(set (match_operand:V2DF 0 "register_operand" "=x")
21996 (float:V2DF (vec_select:V2SI
21997 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
22000 (const_int 1)]))))]
22002 "cvtdq2pd\t{%1, %0|%0, %1}"
22003 [(set_attr "type" "ssecvt")
22004 (set_attr "mode" "V2DF")])
22006 (define_insn "cvtpd2dq"
22007 [(set (match_operand:V4SI 0 "register_operand" "=x")
22009 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
22010 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22012 "cvtpd2dq\t{%1, %0|%0, %1}"
22013 [(set_attr "type" "ssecvt")
22014 (set_attr "mode" "TI")])
22016 (define_insn "cvttpd2dq"
22017 [(set (match_operand:V4SI 0 "register_operand" "=x")
22019 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22021 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22023 "cvttpd2dq\t{%1, %0|%0, %1}"
22024 [(set_attr "type" "ssecvt")
22025 (set_attr "mode" "TI")])
22027 (define_insn "cvtpd2pi"
22028 [(set (match_operand:V2SI 0 "register_operand" "=y")
22029 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
22031 "cvtpd2pi\t{%1, %0|%0, %1}"
22032 [(set_attr "type" "ssecvt")
22033 (set_attr "mode" "TI")])
22035 (define_insn "cvttpd2pi"
22036 [(set (match_operand:V2SI 0 "register_operand" "=y")
22037 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22040 "cvttpd2pi\t{%1, %0|%0, %1}"
22041 [(set_attr "type" "ssecvt")
22042 (set_attr "mode" "TI")])
22044 (define_insn "cvtpi2pd"
22045 [(set (match_operand:V2DF 0 "register_operand" "=x")
22046 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22048 "cvtpi2pd\t{%1, %0|%0, %1}"
22049 [(set_attr "type" "ssecvt")
22050 (set_attr "mode" "TI")])
22052 ;; Conversions between SI and DF
22054 (define_insn "cvtsd2si"
22055 [(set (match_operand:SI 0 "register_operand" "=r,r")
22056 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22057 (parallel [(const_int 0)]))))]
22059 "cvtsd2si\t{%1, %0|%0, %1}"
22060 [(set_attr "type" "sseicvt")
22061 (set_attr "athlon_decode" "double,vector")
22062 (set_attr "mode" "SI")])
22064 (define_insn "cvtsd2siq"
22065 [(set (match_operand:DI 0 "register_operand" "=r,r")
22066 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22067 (parallel [(const_int 0)]))))]
22068 "TARGET_SSE2 && TARGET_64BIT"
22069 "cvtsd2siq\t{%1, %0|%0, %1}"
22070 [(set_attr "type" "sseicvt")
22071 (set_attr "athlon_decode" "double,vector")
22072 (set_attr "mode" "DI")])
22074 (define_insn "cvttsd2si"
22075 [(set (match_operand:SI 0 "register_operand" "=r,r")
22076 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22077 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22079 "cvttsd2si\t{%1, %0|%0, %1}"
22080 [(set_attr "type" "sseicvt")
22081 (set_attr "mode" "SI")
22082 (set_attr "athlon_decode" "double,vector")])
22084 (define_insn "cvttsd2siq"
22085 [(set (match_operand:DI 0 "register_operand" "=r,r")
22086 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22087 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22088 "TARGET_SSE2 && TARGET_64BIT"
22089 "cvttsd2siq\t{%1, %0|%0, %1}"
22090 [(set_attr "type" "sseicvt")
22091 (set_attr "mode" "DI")
22092 (set_attr "athlon_decode" "double,vector")])
22094 (define_insn "cvtsi2sd"
22095 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22096 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22097 (vec_duplicate:V2DF
22099 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
22102 "cvtsi2sd\t{%2, %0|%0, %2}"
22103 [(set_attr "type" "sseicvt")
22104 (set_attr "mode" "DF")
22105 (set_attr "athlon_decode" "double,direct")])
22107 (define_insn "cvtsi2sdq"
22108 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22109 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22110 (vec_duplicate:V2DF
22112 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
22114 "TARGET_SSE2 && TARGET_64BIT"
22115 "cvtsi2sdq\t{%2, %0|%0, %2}"
22116 [(set_attr "type" "sseicvt")
22117 (set_attr "mode" "DF")
22118 (set_attr "athlon_decode" "double,direct")])
22120 ;; Conversions between SF and DF
22122 (define_insn "cvtsd2ss"
22123 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
22124 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
22125 (vec_duplicate:V4SF
22126 (float_truncate:V2SF
22127 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
22130 "cvtsd2ss\t{%2, %0|%0, %2}"
22131 [(set_attr "type" "ssecvt")
22132 (set_attr "athlon_decode" "vector,double")
22133 (set_attr "mode" "SF")])
22135 (define_insn "cvtss2sd"
22136 [(set (match_operand:V2DF 0 "register_operand" "=x")
22137 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
22140 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
22141 (parallel [(const_int 0)
22145 "cvtss2sd\t{%2, %0|%0, %2}"
22146 [(set_attr "type" "ssecvt")
22147 (set_attr "mode" "DF")])
22149 (define_insn "cvtpd2ps"
22150 [(set (match_operand:V4SF 0 "register_operand" "=x")
22153 (subreg:V2SI (float_truncate:V2SF
22154 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
22155 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
22157 "cvtpd2ps\t{%1, %0|%0, %1}"
22158 [(set_attr "type" "ssecvt")
22159 (set_attr "mode" "V4SF")])
22161 (define_insn "cvtps2pd"
22162 [(set (match_operand:V2DF 0 "register_operand" "=x")
22164 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
22165 (parallel [(const_int 0)
22166 (const_int 1)]))))]
22168 "cvtps2pd\t{%1, %0|%0, %1}"
22169 [(set_attr "type" "ssecvt")
22170 (set_attr "mode" "V2DF")])
22172 ;; SSE2 variants of MMX insns
22176 (define_insn "addv16qi3"
22177 [(set (match_operand:V16QI 0 "register_operand" "=x")
22178 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22179 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22181 "paddb\t{%2, %0|%0, %2}"
22182 [(set_attr "type" "sseiadd")
22183 (set_attr "mode" "TI")])
22185 (define_insn "addv8hi3"
22186 [(set (match_operand:V8HI 0 "register_operand" "=x")
22187 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22188 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22190 "paddw\t{%2, %0|%0, %2}"
22191 [(set_attr "type" "sseiadd")
22192 (set_attr "mode" "TI")])
22194 (define_insn "addv4si3"
22195 [(set (match_operand:V4SI 0 "register_operand" "=x")
22196 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
22197 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22199 "paddd\t{%2, %0|%0, %2}"
22200 [(set_attr "type" "sseiadd")
22201 (set_attr "mode" "TI")])
22203 (define_insn "addv2di3"
22204 [(set (match_operand:V2DI 0 "register_operand" "=x")
22205 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
22206 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22208 "paddq\t{%2, %0|%0, %2}"
22209 [(set_attr "type" "sseiadd")
22210 (set_attr "mode" "TI")])
22212 (define_insn "ssaddv16qi3"
22213 [(set (match_operand:V16QI 0 "register_operand" "=x")
22214 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22215 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22217 "paddsb\t{%2, %0|%0, %2}"
22218 [(set_attr "type" "sseiadd")
22219 (set_attr "mode" "TI")])
22221 (define_insn "ssaddv8hi3"
22222 [(set (match_operand:V8HI 0 "register_operand" "=x")
22223 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22224 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22226 "paddsw\t{%2, %0|%0, %2}"
22227 [(set_attr "type" "sseiadd")
22228 (set_attr "mode" "TI")])
22230 (define_insn "usaddv16qi3"
22231 [(set (match_operand:V16QI 0 "register_operand" "=x")
22232 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22233 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22235 "paddusb\t{%2, %0|%0, %2}"
22236 [(set_attr "type" "sseiadd")
22237 (set_attr "mode" "TI")])
22239 (define_insn "usaddv8hi3"
22240 [(set (match_operand:V8HI 0 "register_operand" "=x")
22241 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22242 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22244 "paddusw\t{%2, %0|%0, %2}"
22245 [(set_attr "type" "sseiadd")
22246 (set_attr "mode" "TI")])
22248 (define_insn "subv16qi3"
22249 [(set (match_operand:V16QI 0 "register_operand" "=x")
22250 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22251 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22253 "psubb\t{%2, %0|%0, %2}"
22254 [(set_attr "type" "sseiadd")
22255 (set_attr "mode" "TI")])
22257 (define_insn "subv8hi3"
22258 [(set (match_operand:V8HI 0 "register_operand" "=x")
22259 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22260 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22262 "psubw\t{%2, %0|%0, %2}"
22263 [(set_attr "type" "sseiadd")
22264 (set_attr "mode" "TI")])
22266 (define_insn "subv4si3"
22267 [(set (match_operand:V4SI 0 "register_operand" "=x")
22268 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
22269 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22271 "psubd\t{%2, %0|%0, %2}"
22272 [(set_attr "type" "sseiadd")
22273 (set_attr "mode" "TI")])
22275 (define_insn "subv2di3"
22276 [(set (match_operand:V2DI 0 "register_operand" "=x")
22277 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
22278 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22280 "psubq\t{%2, %0|%0, %2}"
22281 [(set_attr "type" "sseiadd")
22282 (set_attr "mode" "TI")])
22284 (define_insn "sssubv16qi3"
22285 [(set (match_operand:V16QI 0 "register_operand" "=x")
22286 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22287 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22289 "psubsb\t{%2, %0|%0, %2}"
22290 [(set_attr "type" "sseiadd")
22291 (set_attr "mode" "TI")])
22293 (define_insn "sssubv8hi3"
22294 [(set (match_operand:V8HI 0 "register_operand" "=x")
22295 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22296 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22298 "psubsw\t{%2, %0|%0, %2}"
22299 [(set_attr "type" "sseiadd")
22300 (set_attr "mode" "TI")])
22302 (define_insn "ussubv16qi3"
22303 [(set (match_operand:V16QI 0 "register_operand" "=x")
22304 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22305 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22307 "psubusb\t{%2, %0|%0, %2}"
22308 [(set_attr "type" "sseiadd")
22309 (set_attr "mode" "TI")])
22311 (define_insn "ussubv8hi3"
22312 [(set (match_operand:V8HI 0 "register_operand" "=x")
22313 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22314 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22316 "psubusw\t{%2, %0|%0, %2}"
22317 [(set_attr "type" "sseiadd")
22318 (set_attr "mode" "TI")])
22320 (define_insn "mulv8hi3"
22321 [(set (match_operand:V8HI 0 "register_operand" "=x")
22322 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
22323 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22325 "pmullw\t{%2, %0|%0, %2}"
22326 [(set_attr "type" "sseimul")
22327 (set_attr "mode" "TI")])
22329 (define_insn "smulv8hi3_highpart"
22330 [(set (match_operand:V8HI 0 "register_operand" "=x")
22333 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22334 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22337 "pmulhw\t{%2, %0|%0, %2}"
22338 [(set_attr "type" "sseimul")
22339 (set_attr "mode" "TI")])
22341 (define_insn "umulv8hi3_highpart"
22342 [(set (match_operand:V8HI 0 "register_operand" "=x")
22345 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22346 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22349 "pmulhuw\t{%2, %0|%0, %2}"
22350 [(set_attr "type" "sseimul")
22351 (set_attr "mode" "TI")])
22353 (define_insn "sse2_umulsidi3"
22354 [(set (match_operand:DI 0 "register_operand" "=y")
22355 (mult:DI (zero_extend:DI (vec_select:SI
22356 (match_operand:V2SI 1 "register_operand" "0")
22357 (parallel [(const_int 0)])))
22358 (zero_extend:DI (vec_select:SI
22359 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
22360 (parallel [(const_int 0)])))))]
22362 "pmuludq\t{%2, %0|%0, %2}"
22363 [(set_attr "type" "sseimul")
22364 (set_attr "mode" "TI")])
22366 (define_insn "sse2_umulv2siv2di3"
22367 [(set (match_operand:V2DI 0 "register_operand" "=x")
22368 (mult:V2DI (zero_extend:V2DI
22370 (match_operand:V4SI 1 "register_operand" "0")
22371 (parallel [(const_int 0) (const_int 2)])))
22374 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
22375 (parallel [(const_int 0) (const_int 2)])))))]
22377 "pmuludq\t{%2, %0|%0, %2}"
22378 [(set_attr "type" "sseimul")
22379 (set_attr "mode" "TI")])
22381 (define_insn "sse2_pmaddwd"
22382 [(set (match_operand:V4SI 0 "register_operand" "=x")
22385 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
22386 (parallel [(const_int 0)
22390 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
22391 (parallel [(const_int 0)
22396 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
22397 (parallel [(const_int 1)
22401 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
22402 (parallel [(const_int 1)
22405 (const_int 7)]))))))]
22407 "pmaddwd\t{%2, %0|%0, %2}"
22408 [(set_attr "type" "sseiadd")
22409 (set_attr "mode" "TI")])
22411 ;; Same as pxor, but don't show input operands so that we don't think
22413 (define_insn "sse2_clrti"
22414 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
22417 if (get_attr_mode (insn) == MODE_TI)
22418 return "pxor\t%0, %0";
22420 return "xorps\t%0, %0";
22422 [(set_attr "type" "ssemov")
22423 (set_attr "memory" "none")
22426 (ne (symbol_ref "optimize_size")
22428 (const_string "V4SF")
22429 (const_string "TI")))])
22431 ;; MMX unsigned averages/sum of absolute differences
22433 (define_insn "sse2_uavgv16qi3"
22434 [(set (match_operand:V16QI 0 "register_operand" "=x")
22436 (plus:V16QI (plus:V16QI
22437 (match_operand:V16QI 1 "register_operand" "0")
22438 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
22439 (const_vector:V16QI [(const_int 1) (const_int 1)
22440 (const_int 1) (const_int 1)
22441 (const_int 1) (const_int 1)
22442 (const_int 1) (const_int 1)
22443 (const_int 1) (const_int 1)
22444 (const_int 1) (const_int 1)
22445 (const_int 1) (const_int 1)
22446 (const_int 1) (const_int 1)]))
22449 "pavgb\t{%2, %0|%0, %2}"
22450 [(set_attr "type" "sseiadd")
22451 (set_attr "mode" "TI")])
22453 (define_insn "sse2_uavgv8hi3"
22454 [(set (match_operand:V8HI 0 "register_operand" "=x")
22456 (plus:V8HI (plus:V8HI
22457 (match_operand:V8HI 1 "register_operand" "0")
22458 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
22459 (const_vector:V8HI [(const_int 1) (const_int 1)
22460 (const_int 1) (const_int 1)
22461 (const_int 1) (const_int 1)
22462 (const_int 1) (const_int 1)]))
22465 "pavgw\t{%2, %0|%0, %2}"
22466 [(set_attr "type" "sseiadd")
22467 (set_attr "mode" "TI")])
22469 ;; @@@ this isn't the right representation.
22470 (define_insn "sse2_psadbw"
22471 [(set (match_operand:V2DI 0 "register_operand" "=x")
22472 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
22473 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
22476 "psadbw\t{%2, %0|%0, %2}"
22477 [(set_attr "type" "sseiadd")
22478 (set_attr "mode" "TI")])
22481 ;; MMX insert/extract/shuffle
22483 (define_insn "sse2_pinsrw"
22484 [(set (match_operand:V8HI 0 "register_operand" "=x")
22485 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
22486 (vec_duplicate:V8HI
22488 (match_operand:SI 2 "nonimmediate_operand" "rm")))
22489 (match_operand:SI 3 "immediate_operand" "i")))]
22491 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
22492 [(set_attr "type" "ssecvt")
22493 (set_attr "mode" "TI")])
22495 (define_insn "sse2_pextrw"
22496 [(set (match_operand:SI 0 "register_operand" "=r")
22498 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
22500 [(match_operand:SI 2 "immediate_operand" "i")]))))]
22502 "pextrw\t{%2, %1, %0|%0, %1, %2}"
22503 [(set_attr "type" "ssecvt")
22504 (set_attr "mode" "TI")])
22506 (define_insn "sse2_pshufd"
22507 [(set (match_operand:V4SI 0 "register_operand" "=x")
22508 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
22509 (match_operand:SI 2 "immediate_operand" "i")]
22512 "pshufd\t{%2, %1, %0|%0, %1, %2}"
22513 [(set_attr "type" "ssecvt")
22514 (set_attr "mode" "TI")])
22516 (define_insn "sse2_pshuflw"
22517 [(set (match_operand:V8HI 0 "register_operand" "=x")
22518 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22519 (match_operand:SI 2 "immediate_operand" "i")]
22522 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
22523 [(set_attr "type" "ssecvt")
22524 (set_attr "mode" "TI")])
22526 (define_insn "sse2_pshufhw"
22527 [(set (match_operand:V8HI 0 "register_operand" "=x")
22528 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22529 (match_operand:SI 2 "immediate_operand" "i")]
22532 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
22533 [(set_attr "type" "ssecvt")
22534 (set_attr "mode" "TI")])
22536 ;; MMX mask-generating comparisons
22538 (define_insn "eqv16qi3"
22539 [(set (match_operand:V16QI 0 "register_operand" "=x")
22540 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
22541 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22543 "pcmpeqb\t{%2, %0|%0, %2}"
22544 [(set_attr "type" "ssecmp")
22545 (set_attr "mode" "TI")])
22547 (define_insn "eqv8hi3"
22548 [(set (match_operand:V8HI 0 "register_operand" "=x")
22549 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
22550 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22552 "pcmpeqw\t{%2, %0|%0, %2}"
22553 [(set_attr "type" "ssecmp")
22554 (set_attr "mode" "TI")])
22556 (define_insn "eqv4si3"
22557 [(set (match_operand:V4SI 0 "register_operand" "=x")
22558 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
22559 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22561 "pcmpeqd\t{%2, %0|%0, %2}"
22562 [(set_attr "type" "ssecmp")
22563 (set_attr "mode" "TI")])
22565 (define_insn "gtv16qi3"
22566 [(set (match_operand:V16QI 0 "register_operand" "=x")
22567 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
22568 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22570 "pcmpgtb\t{%2, %0|%0, %2}"
22571 [(set_attr "type" "ssecmp")
22572 (set_attr "mode" "TI")])
22574 (define_insn "gtv8hi3"
22575 [(set (match_operand:V8HI 0 "register_operand" "=x")
22576 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22577 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22579 "pcmpgtw\t{%2, %0|%0, %2}"
22580 [(set_attr "type" "ssecmp")
22581 (set_attr "mode" "TI")])
22583 (define_insn "gtv4si3"
22584 [(set (match_operand:V4SI 0 "register_operand" "=x")
22585 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22586 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22588 "pcmpgtd\t{%2, %0|%0, %2}"
22589 [(set_attr "type" "ssecmp")
22590 (set_attr "mode" "TI")])
22593 ;; MMX max/min insns
22595 (define_insn "umaxv16qi3"
22596 [(set (match_operand:V16QI 0 "register_operand" "=x")
22597 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22598 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22600 "pmaxub\t{%2, %0|%0, %2}"
22601 [(set_attr "type" "sseiadd")
22602 (set_attr "mode" "TI")])
22604 (define_insn "smaxv8hi3"
22605 [(set (match_operand:V8HI 0 "register_operand" "=x")
22606 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22607 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22609 "pmaxsw\t{%2, %0|%0, %2}"
22610 [(set_attr "type" "sseiadd")
22611 (set_attr "mode" "TI")])
22613 (define_insn "uminv16qi3"
22614 [(set (match_operand:V16QI 0 "register_operand" "=x")
22615 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22616 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22618 "pminub\t{%2, %0|%0, %2}"
22619 [(set_attr "type" "sseiadd")
22620 (set_attr "mode" "TI")])
22622 (define_insn "sminv8hi3"
22623 [(set (match_operand:V8HI 0 "register_operand" "=x")
22624 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22625 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22627 "pminsw\t{%2, %0|%0, %2}"
22628 [(set_attr "type" "sseiadd")
22629 (set_attr "mode" "TI")])
22634 (define_insn "ashrv8hi3"
22635 [(set (match_operand:V8HI 0 "register_operand" "=x")
22636 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22637 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22639 "psraw\t{%2, %0|%0, %2}"
22640 [(set_attr "type" "sseishft")
22641 (set_attr "mode" "TI")])
22643 (define_insn "ashrv4si3"
22644 [(set (match_operand:V4SI 0 "register_operand" "=x")
22645 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22646 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22648 "psrad\t{%2, %0|%0, %2}"
22649 [(set_attr "type" "sseishft")
22650 (set_attr "mode" "TI")])
22652 (define_insn "lshrv8hi3"
22653 [(set (match_operand:V8HI 0 "register_operand" "=x")
22654 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22655 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22657 "psrlw\t{%2, %0|%0, %2}"
22658 [(set_attr "type" "sseishft")
22659 (set_attr "mode" "TI")])
22661 (define_insn "lshrv4si3"
22662 [(set (match_operand:V4SI 0 "register_operand" "=x")
22663 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22664 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22666 "psrld\t{%2, %0|%0, %2}"
22667 [(set_attr "type" "sseishft")
22668 (set_attr "mode" "TI")])
22670 (define_insn "lshrv2di3"
22671 [(set (match_operand:V2DI 0 "register_operand" "=x")
22672 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22673 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22675 "psrlq\t{%2, %0|%0, %2}"
22676 [(set_attr "type" "sseishft")
22677 (set_attr "mode" "TI")])
22679 (define_insn "ashlv8hi3"
22680 [(set (match_operand:V8HI 0 "register_operand" "=x")
22681 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22682 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22684 "psllw\t{%2, %0|%0, %2}"
22685 [(set_attr "type" "sseishft")
22686 (set_attr "mode" "TI")])
22688 (define_insn "ashlv4si3"
22689 [(set (match_operand:V4SI 0 "register_operand" "=x")
22690 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22691 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22693 "pslld\t{%2, %0|%0, %2}"
22694 [(set_attr "type" "sseishft")
22695 (set_attr "mode" "TI")])
22697 (define_insn "ashlv2di3"
22698 [(set (match_operand:V2DI 0 "register_operand" "=x")
22699 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22700 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22702 "psllq\t{%2, %0|%0, %2}"
22703 [(set_attr "type" "sseishft")
22704 (set_attr "mode" "TI")])
22706 (define_insn "ashrv8hi3_ti"
22707 [(set (match_operand:V8HI 0 "register_operand" "=x")
22708 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22709 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22711 "psraw\t{%2, %0|%0, %2}"
22712 [(set_attr "type" "sseishft")
22713 (set_attr "mode" "TI")])
22715 (define_insn "ashrv4si3_ti"
22716 [(set (match_operand:V4SI 0 "register_operand" "=x")
22717 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22718 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22720 "psrad\t{%2, %0|%0, %2}"
22721 [(set_attr "type" "sseishft")
22722 (set_attr "mode" "TI")])
22724 (define_insn "lshrv8hi3_ti"
22725 [(set (match_operand:V8HI 0 "register_operand" "=x")
22726 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22727 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22729 "psrlw\t{%2, %0|%0, %2}"
22730 [(set_attr "type" "sseishft")
22731 (set_attr "mode" "TI")])
22733 (define_insn "lshrv4si3_ti"
22734 [(set (match_operand:V4SI 0 "register_operand" "=x")
22735 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22736 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22738 "psrld\t{%2, %0|%0, %2}"
22739 [(set_attr "type" "sseishft")
22740 (set_attr "mode" "TI")])
22742 (define_insn "lshrv2di3_ti"
22743 [(set (match_operand:V2DI 0 "register_operand" "=x")
22744 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22745 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22747 "psrlq\t{%2, %0|%0, %2}"
22748 [(set_attr "type" "sseishft")
22749 (set_attr "mode" "TI")])
22751 (define_insn "ashlv8hi3_ti"
22752 [(set (match_operand:V8HI 0 "register_operand" "=x")
22753 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22754 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22756 "psllw\t{%2, %0|%0, %2}"
22757 [(set_attr "type" "sseishft")
22758 (set_attr "mode" "TI")])
22760 (define_insn "ashlv4si3_ti"
22761 [(set (match_operand:V4SI 0 "register_operand" "=x")
22762 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22763 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22765 "pslld\t{%2, %0|%0, %2}"
22766 [(set_attr "type" "sseishft")
22767 (set_attr "mode" "TI")])
22769 (define_insn "ashlv2di3_ti"
22770 [(set (match_operand:V2DI 0 "register_operand" "=x")
22771 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22772 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22774 "psllq\t{%2, %0|%0, %2}"
22775 [(set_attr "type" "sseishft")
22776 (set_attr "mode" "TI")])
22778 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
22779 ;; we wouldn't need here it since we never generate TImode arithmetic.
22781 ;; There has to be some kind of prize for the weirdest new instruction...
22782 (define_insn "sse2_ashlti3"
22783 [(set (match_operand:TI 0 "register_operand" "=x")
22785 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
22786 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22787 (const_int 8)))] UNSPEC_NOP))]
22789 "pslldq\t{%2, %0|%0, %2}"
22790 [(set_attr "type" "sseishft")
22791 (set_attr "mode" "TI")])
22793 (define_insn "sse2_lshrti3"
22794 [(set (match_operand:TI 0 "register_operand" "=x")
22796 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
22797 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22798 (const_int 8)))] UNSPEC_NOP))]
22800 "psrldq\t{%2, %0|%0, %2}"
22801 [(set_attr "type" "sseishft")
22802 (set_attr "mode" "TI")])
22806 (define_insn "sse2_unpckhpd"
22807 [(set (match_operand:V2DF 0 "register_operand" "=x")
22809 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22810 (parallel [(const_int 1)]))
22811 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22812 (parallel [(const_int 0)]))))]
22814 "unpckhpd\t{%2, %0|%0, %2}"
22815 [(set_attr "type" "ssecvt")
22816 (set_attr "mode" "TI")])
22818 (define_insn "sse2_unpcklpd"
22819 [(set (match_operand:V2DF 0 "register_operand" "=x")
22821 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22822 (parallel [(const_int 0)]))
22823 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22824 (parallel [(const_int 1)]))))]
22826 "unpcklpd\t{%2, %0|%0, %2}"
22827 [(set_attr "type" "ssecvt")
22828 (set_attr "mode" "TI")])
22830 ;; MMX pack/unpack insns.
22832 (define_insn "sse2_packsswb"
22833 [(set (match_operand:V16QI 0 "register_operand" "=x")
22835 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22836 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22838 "packsswb\t{%2, %0|%0, %2}"
22839 [(set_attr "type" "ssecvt")
22840 (set_attr "mode" "TI")])
22842 (define_insn "sse2_packssdw"
22843 [(set (match_operand:V8HI 0 "register_operand" "=x")
22845 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
22846 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
22848 "packssdw\t{%2, %0|%0, %2}"
22849 [(set_attr "type" "ssecvt")
22850 (set_attr "mode" "TI")])
22852 (define_insn "sse2_packuswb"
22853 [(set (match_operand:V16QI 0 "register_operand" "=x")
22855 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22856 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22858 "packuswb\t{%2, %0|%0, %2}"
22859 [(set_attr "type" "ssecvt")
22860 (set_attr "mode" "TI")])
22862 (define_insn "sse2_punpckhbw"
22863 [(set (match_operand:V16QI 0 "register_operand" "=x")
22865 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22866 (parallel [(const_int 8) (const_int 0)
22867 (const_int 9) (const_int 1)
22868 (const_int 10) (const_int 2)
22869 (const_int 11) (const_int 3)
22870 (const_int 12) (const_int 4)
22871 (const_int 13) (const_int 5)
22872 (const_int 14) (const_int 6)
22873 (const_int 15) (const_int 7)]))
22874 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22875 (parallel [(const_int 0) (const_int 8)
22876 (const_int 1) (const_int 9)
22877 (const_int 2) (const_int 10)
22878 (const_int 3) (const_int 11)
22879 (const_int 4) (const_int 12)
22880 (const_int 5) (const_int 13)
22881 (const_int 6) (const_int 14)
22882 (const_int 7) (const_int 15)]))
22883 (const_int 21845)))]
22885 "punpckhbw\t{%2, %0|%0, %2}"
22886 [(set_attr "type" "ssecvt")
22887 (set_attr "mode" "TI")])
22889 (define_insn "sse2_punpckhwd"
22890 [(set (match_operand:V8HI 0 "register_operand" "=x")
22892 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22893 (parallel [(const_int 4) (const_int 0)
22894 (const_int 5) (const_int 1)
22895 (const_int 6) (const_int 2)
22896 (const_int 7) (const_int 3)]))
22897 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22898 (parallel [(const_int 0) (const_int 4)
22899 (const_int 1) (const_int 5)
22900 (const_int 2) (const_int 6)
22901 (const_int 3) (const_int 7)]))
22904 "punpckhwd\t{%2, %0|%0, %2}"
22905 [(set_attr "type" "ssecvt")
22906 (set_attr "mode" "TI")])
22908 (define_insn "sse2_punpckhdq"
22909 [(set (match_operand:V4SI 0 "register_operand" "=x")
22911 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22912 (parallel [(const_int 2) (const_int 0)
22913 (const_int 3) (const_int 1)]))
22914 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22915 (parallel [(const_int 0) (const_int 2)
22916 (const_int 1) (const_int 3)]))
22919 "punpckhdq\t{%2, %0|%0, %2}"
22920 [(set_attr "type" "ssecvt")
22921 (set_attr "mode" "TI")])
22923 (define_insn "sse2_punpcklbw"
22924 [(set (match_operand:V16QI 0 "register_operand" "=x")
22926 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22927 (parallel [(const_int 0) (const_int 8)
22928 (const_int 1) (const_int 9)
22929 (const_int 2) (const_int 10)
22930 (const_int 3) (const_int 11)
22931 (const_int 4) (const_int 12)
22932 (const_int 5) (const_int 13)
22933 (const_int 6) (const_int 14)
22934 (const_int 7) (const_int 15)]))
22935 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22936 (parallel [(const_int 8) (const_int 0)
22937 (const_int 9) (const_int 1)
22938 (const_int 10) (const_int 2)
22939 (const_int 11) (const_int 3)
22940 (const_int 12) (const_int 4)
22941 (const_int 13) (const_int 5)
22942 (const_int 14) (const_int 6)
22943 (const_int 15) (const_int 7)]))
22944 (const_int 21845)))]
22946 "punpcklbw\t{%2, %0|%0, %2}"
22947 [(set_attr "type" "ssecvt")
22948 (set_attr "mode" "TI")])
22950 (define_insn "sse2_punpcklwd"
22951 [(set (match_operand:V8HI 0 "register_operand" "=x")
22953 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22954 (parallel [(const_int 0) (const_int 4)
22955 (const_int 1) (const_int 5)
22956 (const_int 2) (const_int 6)
22957 (const_int 3) (const_int 7)]))
22958 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22959 (parallel [(const_int 4) (const_int 0)
22960 (const_int 5) (const_int 1)
22961 (const_int 6) (const_int 2)
22962 (const_int 7) (const_int 3)]))
22965 "punpcklwd\t{%2, %0|%0, %2}"
22966 [(set_attr "type" "ssecvt")
22967 (set_attr "mode" "TI")])
22969 (define_insn "sse2_punpckldq"
22970 [(set (match_operand:V4SI 0 "register_operand" "=x")
22972 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22973 (parallel [(const_int 0) (const_int 2)
22974 (const_int 1) (const_int 3)]))
22975 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22976 (parallel [(const_int 2) (const_int 0)
22977 (const_int 3) (const_int 1)]))
22980 "punpckldq\t{%2, %0|%0, %2}"
22981 [(set_attr "type" "ssecvt")
22982 (set_attr "mode" "TI")])
22984 (define_insn "sse2_punpcklqdq"
22985 [(set (match_operand:V2DI 0 "register_operand" "=x")
22987 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22988 (parallel [(const_int 1)
22990 (match_operand:V2DI 1 "register_operand" "0")
22993 "punpcklqdq\t{%2, %0|%0, %2}"
22994 [(set_attr "type" "ssecvt")
22995 (set_attr "mode" "TI")])
22997 (define_insn "sse2_punpckhqdq"
22998 [(set (match_operand:V2DI 0 "register_operand" "=x")
23000 (match_operand:V2DI 1 "register_operand" "0")
23001 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23002 (parallel [(const_int 1)
23006 "punpckhqdq\t{%2, %0|%0, %2}"
23007 [(set_attr "type" "ssecvt")
23008 (set_attr "mode" "TI")])
23012 (define_insn "sse2_movapd"
23013 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23014 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23017 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23018 "movapd\t{%1, %0|%0, %1}"
23019 [(set_attr "type" "ssemov")
23020 (set_attr "mode" "V2DF")])
23022 (define_insn "sse2_movupd"
23023 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23024 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23027 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23028 "movupd\t{%1, %0|%0, %1}"
23029 [(set_attr "type" "ssecvt")
23030 (set_attr "mode" "V2DF")])
23032 (define_insn "sse2_movdqa"
23033 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23034 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23037 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23038 "movdqa\t{%1, %0|%0, %1}"
23039 [(set_attr "type" "ssemov")
23040 (set_attr "mode" "TI")])
23042 (define_insn "sse2_movdqu"
23043 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23044 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23047 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23048 "movdqu\t{%1, %0|%0, %1}"
23049 [(set_attr "type" "ssecvt")
23050 (set_attr "mode" "TI")])
23052 (define_insn "sse2_movdq2q"
23053 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
23054 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
23055 (parallel [(const_int 0)])))]
23056 "TARGET_SSE2 && !TARGET_64BIT"
23058 movq\t{%1, %0|%0, %1}
23059 movdq2q\t{%1, %0|%0, %1}"
23060 [(set_attr "type" "ssecvt")
23061 (set_attr "mode" "TI")])
23063 (define_insn "sse2_movdq2q_rex64"
23064 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
23065 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
23066 (parallel [(const_int 0)])))]
23067 "TARGET_SSE2 && TARGET_64BIT"
23069 movq\t{%1, %0|%0, %1}
23070 movdq2q\t{%1, %0|%0, %1}
23071 movd\t{%1, %0|%0, %1}"
23072 [(set_attr "type" "ssecvt")
23073 (set_attr "mode" "TI")])
23075 (define_insn "sse2_movq2dq"
23076 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
23077 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
23079 "TARGET_SSE2 && !TARGET_64BIT"
23081 movq\t{%1, %0|%0, %1}
23082 movq2dq\t{%1, %0|%0, %1}"
23083 [(set_attr "type" "ssecvt,ssemov")
23084 (set_attr "mode" "TI")])
23086 (define_insn "sse2_movq2dq_rex64"
23087 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
23088 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
23090 "TARGET_SSE2 && TARGET_64BIT"
23092 movq\t{%1, %0|%0, %1}
23093 movq2dq\t{%1, %0|%0, %1}
23094 movd\t{%1, %0|%0, %1}"
23095 [(set_attr "type" "ssecvt,ssemov,ssecvt")
23096 (set_attr "mode" "TI")])
23098 (define_insn "sse2_movq"
23099 [(set (match_operand:V2DI 0 "register_operand" "=x")
23100 (vec_concat:V2DI (vec_select:DI
23101 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
23102 (parallel [(const_int 0)]))
23105 "movq\t{%1, %0|%0, %1}"
23106 [(set_attr "type" "ssemov")
23107 (set_attr "mode" "TI")])
23109 (define_insn "sse2_loadd"
23110 [(set (match_operand:V4SI 0 "register_operand" "=x")
23112 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
23113 (const_vector:V4SI [(const_int 0)
23119 "movd\t{%1, %0|%0, %1}"
23120 [(set_attr "type" "ssemov")
23121 (set_attr "mode" "TI")])
23123 (define_insn "sse2_stored"
23124 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
23126 (match_operand:V4SI 1 "register_operand" "x")
23127 (parallel [(const_int 0)])))]
23129 "movd\t{%1, %0|%0, %1}"
23130 [(set_attr "type" "ssemov")
23131 (set_attr "mode" "TI")])
23133 (define_insn "sse2_movhpd"
23134 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23136 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23137 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23139 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23140 "movhpd\t{%2, %0|%0, %2}"
23141 [(set_attr "type" "ssecvt")
23142 (set_attr "mode" "V2DF")])
23144 (define_insn "sse2_movlpd"
23145 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23147 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23148 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23150 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23151 "movlpd\t{%2, %0|%0, %2}"
23152 [(set_attr "type" "ssecvt")
23153 (set_attr "mode" "V2DF")])
23155 (define_expand "sse2_loadsd"
23156 [(match_operand:V2DF 0 "register_operand" "")
23157 (match_operand:DF 1 "memory_operand" "")]
23160 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
23161 CONST0_RTX (V2DFmode)));
23165 (define_insn "sse2_loadsd_1"
23166 [(set (match_operand:V2DF 0 "register_operand" "=x")
23168 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
23169 (match_operand:V2DF 2 "const0_operand" "X")
23172 "movsd\t{%1, %0|%0, %1}"
23173 [(set_attr "type" "ssecvt")
23174 (set_attr "mode" "DF")])
23176 (define_insn "sse2_movsd"
23177 [(set (match_operand:V2DF 0 "register_operand" "=x")
23179 (match_operand:V2DF 1 "register_operand" "0")
23180 (match_operand:V2DF 2 "register_operand" "x")
23183 "movsd\t{%2, %0|%0, %2}"
23184 [(set_attr "type" "ssecvt")
23185 (set_attr "mode" "DF")])
23187 (define_insn "sse2_storesd"
23188 [(set (match_operand:DF 0 "memory_operand" "=m")
23190 (match_operand:V2DF 1 "register_operand" "x")
23191 (parallel [(const_int 0)])))]
23193 "movsd\t{%1, %0|%0, %1}"
23194 [(set_attr "type" "ssecvt")
23195 (set_attr "mode" "DF")])
23197 (define_insn "sse2_shufpd"
23198 [(set (match_operand:V2DF 0 "register_operand" "=x")
23199 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23200 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
23201 (match_operand:SI 3 "immediate_operand" "i")]
23204 ;; @@@ check operand order for intel/nonintel syntax
23205 "shufpd\t{%3, %2, %0|%0, %2, %3}"
23206 [(set_attr "type" "ssecvt")
23207 (set_attr "mode" "V2DF")])
23209 (define_insn "sse2_clflush"
23210 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
23214 [(set_attr "type" "sse")
23215 (set_attr "memory" "unknown")])
23217 (define_expand "sse2_mfence"
23218 [(set (match_dup 0)
23219 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23222 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23223 MEM_VOLATILE_P (operands[0]) = 1;
23226 (define_insn "*mfence_insn"
23227 [(set (match_operand:BLK 0 "" "")
23228 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23231 [(set_attr "type" "sse")
23232 (set_attr "memory" "unknown")])
23234 (define_expand "sse2_lfence"
23235 [(set (match_dup 0)
23236 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23239 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23240 MEM_VOLATILE_P (operands[0]) = 1;
23243 (define_insn "*lfence_insn"
23244 [(set (match_operand:BLK 0 "" "")
23245 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23248 [(set_attr "type" "sse")
23249 (set_attr "memory" "unknown")])