gcc/config/i386/i386.opt

   1 ; Options for the IA-32 and AMD64 ports of the compiler.
   2
   3 ; Copyright (C) 2005-2020 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 ; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 ; for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/i386/i386-opts.h
  23
  24 ; Bit flags that specify the ISA we are compiling for.
  25 Variable
  26 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
  27
  28 Variable
  29 HOST_WIDE_INT ix86_isa_flags2 = 0
  30
  31 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
  32 ; on the command line.
  33 Variable
  34 HOST_WIDE_INT ix86_isa_flags_explicit
  35
  36 Variable
  37 HOST_WIDE_INT ix86_isa_flags2_explicit
  38
  39 ; Additional target flags
  40 Variable
  41 int ix86_target_flags
  42
  43 TargetVariable
  44 int recip_mask = RECIP_MASK_DEFAULT
  45
  46 Variable
  47 int recip_mask_explicit
  48
  49 TargetSave
  50 int x_recip_mask_explicit
  51
  52 ;; Definitions to add to the cl_target_option structure
  53 ;; -march= processor
  54 TargetSave
  55 unsigned char arch
  56
  57 ;; -mtune= processor
  58 TargetSave
  59 unsigned char tune
  60
  61 ;; -march= processor-string
  62 TargetSave
  63 const char *x_ix86_arch_string
  64
  65 ;; -mtune= processor-string
  66 TargetSave
  67 const char *x_ix86_tune_string
  68
  69 ;; CPU schedule model
  70 TargetSave
  71 unsigned char schedule
  72
  73 ;; True if processor has SSE prefetch instruction.
  74 TargetSave
  75 unsigned char prefetch_sse
  76
  77 ;; branch cost
  78 TargetSave
  79 unsigned char branch_cost
  80
  81 ;; which flags were passed by the user
  82 TargetSave
  83 HOST_WIDE_INT x_ix86_isa_flags2_explicit
  84
  85 ;; which flags were passed by the user
  86 TargetSave
  87 HOST_WIDE_INT x_ix86_isa_flags_explicit
  88
  89 ;; whether -mtune was not specified
  90 TargetSave
  91 unsigned char tune_defaulted
  92
  93 ;; whether -march was specified
  94 TargetSave
  95 unsigned char arch_specified
  96
  97 ;; -mcmodel= model
  98 TargetSave
  99 enum cmodel x_ix86_cmodel
 100
 101 ;; -mabi=
 102 TargetSave
 103 enum calling_abi x_ix86_abi
 104
 105 ;; -masm=
 106 TargetSave
 107 enum asm_dialect x_ix86_asm_dialect
 108
 109 ;; -mbranch-cost=
 110 TargetSave
 111 int x_ix86_branch_cost
 112
 113 ;; -mdump-tune-features=
 114 TargetSave
 115 int x_ix86_dump_tunes
 116
 117 ;; -mstackrealign=
 118 TargetSave
 119 int x_ix86_force_align_arg_pointer
 120
 121 ;; -mforce-drap=
 122 TargetSave
 123 int x_ix86_force_drap
 124
 125 ;; -mincoming-stack-boundary=
 126 TargetSave
 127 int x_ix86_incoming_stack_boundary_arg
 128
 129 ;; -maddress-mode=
 130 TargetSave
 131 enum pmode x_ix86_pmode
 132
 133 ;; -mpreferred-stack-boundary=
 134 TargetSave
 135 int x_ix86_preferred_stack_boundary_arg
 136
 137 ;; -mrecip=
 138 TargetSave
 139 const char *x_ix86_recip_name
 140
 141 ;; -mregparm=
 142 TargetSave
 143 int x_ix86_regparm
 144
 145 ;; -mlarge-data-threshold=
 146 TargetSave
 147 int x_ix86_section_threshold
 148
 149 ;; -msse2avx=
 150 TargetSave
 151 int x_ix86_sse2avx
 152
 153 ;; -mstack-protector-guard=
 154 TargetSave
 155 enum stack_protector_guard x_ix86_stack_protector_guard
 156
 157 ;; -mstringop-strategy=
 158 TargetSave
 159 enum stringop_alg x_ix86_stringop_alg
 160
 161 ;; -mtls-dialect=
 162 TargetSave
 163 enum tls_dialect x_ix86_tls_dialect
 164
 165 ;; -mtune-ctrl=
 166 TargetSave
 167 const char *x_ix86_tune_ctrl_string
 168
 169 ;; -mmemcpy-strategy=
 170 TargetSave
 171 const char *x_ix86_tune_memcpy_strategy
 172
 173 ;; -mmemset-strategy=
 174 TargetSave
 175 const char *x_ix86_tune_memset_strategy
 176
 177 ;; -mno-default=
 178 TargetSave
 179 int x_ix86_tune_no_default
 180
 181 ;; -mveclibabi=
 182 TargetSave
 183 enum ix86_veclibabi x_ix86_veclibabi_type
 184
 185 ;; x86 options
 186 m128bit-long-double
 187 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
 188 sizeof(long double) is 16.
 189
 190 m80387
 191 Target Report Mask(80387) Save
 192 Use hardware fp.
 193
 194 m96bit-long-double
 195 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
 196 sizeof(long double) is 12.
 197
 198 mlong-double-80
 199 Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
 200 Use 80-bit long double.
 201
 202 mlong-double-64
 203 Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
 204 Use 64-bit long double.
 205
 206 mlong-double-128
 207 Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
 208 Use 128-bit long double.
 209
 210 maccumulate-outgoing-args
 211 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
 212 Reserve space for outgoing arguments in the function prologue.
 213
 214 malign-double
 215 Target Report Mask(ALIGN_DOUBLE) Save
 216 Align some doubles on dword boundary.
 217
 218 malign-functions=
 219 Target RejectNegative Joined UInteger
 220 Function starts are aligned to this power of 2.
 221
 222 malign-jumps=
 223 Target RejectNegative Joined UInteger
 224 Jump targets are aligned to this power of 2.
 225
 226 malign-loops=
 227 Target RejectNegative Joined UInteger
 228 Loop code aligned to this power of 2.
 229
 230 malign-stringops
 231 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
 232 Align destination of the string operations.
 233
 234 malign-data=
 235 Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat)
 236 Use the given data alignment.
 237
 238 Enum
 239 Name(ix86_align_data) Type(enum ix86_align_data)
 240 Known data alignment choices (for use with the -malign-data= option):
 241
 242 EnumValue
 243 Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat)
 244
 245 EnumValue
 246 Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi)
 247
 248 EnumValue
 249 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
 250
 251 march=
 252 Target RejectNegative Negative(march=) Joined Var(ix86_arch_string)
 253 Generate code for given CPU.
 254
 255 masm=
 256 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
 257 Use given assembler dialect.
 258
 259 Enum
 260 Name(asm_dialect) Type(enum asm_dialect)
 261 Known assembler dialects (for use with the -masm= option):
 262
 263 EnumValue
 264 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
 265
 266 EnumValue
 267 Enum(asm_dialect) String(att) Value(ASM_ATT)
 268
 269 mbranch-cost=
 270 Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5)
 271 Branches are this expensive (arbitrary units).
 272
 273 mlarge-data-threshold=
 274 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD)
 275 -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model.
 276
 277 mcmodel=
 278 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
 279 Use given x86-64 code model.
 280
 281 Enum
 282 Name(cmodel) Type(enum cmodel)
 283 Known code models (for use with the -mcmodel= option):
 284
 285 EnumValue
 286 Enum(cmodel) String(small) Value(CM_SMALL)
 287
 288 EnumValue
 289 Enum(cmodel) String(medium) Value(CM_MEDIUM)
 290
 291 EnumValue
 292 Enum(cmodel) String(large) Value(CM_LARGE)
 293
 294 EnumValue
 295 Enum(cmodel) String(32) Value(CM_32)
 296
 297 EnumValue
 298 Enum(cmodel) String(kernel) Value(CM_KERNEL)
 299
 300 maddress-mode=
 301 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
 302 Use given address mode.
 303
 304 Enum
 305 Name(pmode) Type(enum pmode)
 306 Known address mode (for use with the -maddress-mode= option):
 307
 308 EnumValue
 309 Enum(pmode) String(short) Value(PMODE_SI)
 310
 311 EnumValue
 312 Enum(pmode) String(long) Value(PMODE_DI)
 313
 314 mcpu=
 315 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
 316
 317 mfancy-math-387
 318 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
 319 Generate sin, cos, sqrt for FPU.
 320
 321 mforce-drap
 322 Target Report Var(ix86_force_drap)
 323 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack.
 324
 325 mfp-ret-in-387
 326 Target Report Mask(FLOAT_RETURNS) Save
 327 Return values of functions in FPU registers.
 328
 329 mfpmath=
 330 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
 331 Generate floating point mathematics using given instruction set.
 332
 333 Enum
 334 Name(fpmath_unit) Type(enum fpmath_unit)
 335 Valid arguments to -mfpmath=:
 336
 337 EnumValue
 338 Enum(fpmath_unit) String(387) Value(FPMATH_387)
 339
 340 EnumValue
 341 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
 342
 343 EnumValue
 344 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 345
 346 EnumValue
 347 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 348
 349 EnumValue
 350 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 351
 352 EnumValue
 353 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 354
 355 EnumValue
 356 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 357
 358 mhard-float
 359 Target RejectNegative Mask(80387) Save
 360 Use hardware fp.
 361
 362 mieee-fp
 363 Target Report Mask(IEEE_FP) Save
 364 Use IEEE math for fp comparisons.
 365
 366 minline-all-stringops
 367 Target Report Mask(INLINE_ALL_STRINGOPS) Save
 368 Inline all known string operations.
 369
 370 minline-stringops-dynamically
 371 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
 372 Inline memset/memcpy string operations, but perform inline version only for small blocks.
 373
 374 mintel-syntax
 375 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
 376
 377 mms-bitfields
 378 Target Report Mask(MS_BITFIELD_LAYOUT) Save
 379 Use native (MS) bitfield layout.
 380
 381 mno-align-stringops
 382 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
 383
 384 mno-fancy-math-387
 385 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
 386
 387 mno-push-args
 388 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
 389
 390 mno-red-zone
 391 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
 392
 393 momit-leaf-frame-pointer
 394 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
 395 Omit the frame pointer in leaf functions.
 396
 397 mpc32
 398 Target RejectNegative Report
 399 Set 80387 floating-point precision to 32-bit.
 400
 401 mpc64
 402 Target RejectNegative Report
 403 Set 80387 floating-point precision to 64-bit.
 404
 405 mpc80
 406 Target RejectNegative Report
 407 Set 80387 floating-point precision to 80-bit.
 408
 409 mpreferred-stack-boundary=
 410 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
 411 Attempt to keep stack aligned to this power of 2.
 412
 413 mincoming-stack-boundary=
 414 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
 415 Assume incoming stack aligned to this power of 2.
 416
 417 mpush-args
 418 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
 419 Use push instructions to save outgoing arguments.
 420
 421 mred-zone
 422 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
 423 Use red-zone in the x86-64 code.
 424
 425 mregparm=
 426 Target RejectNegative Joined UInteger Var(ix86_regparm)
 427 Number of registers used to pass integer arguments.
 428
 429 mrtd
 430 Target Report Mask(RTD) Save
 431 Alternate calling convention.
 432
 433 msoft-float
 434 Target InverseMask(80387) Save
 435 Do not use hardware fp.
 436
 437 msseregparm
 438 Target RejectNegative Mask(SSEREGPARM) Save
 439 Use SSE register passing conventions for SF and DF mode.
 440
 441 mstackrealign
 442 Target Report Var(ix86_force_align_arg_pointer)
 443 Realign stack in prologue.
 444
 445 mstack-arg-probe
 446 Target Report Mask(STACK_PROBE) Save
 447 Enable stack probing.
 448
 449 mmemcpy-strategy=
 450 Target RejectNegative Joined Var(ix86_tune_memcpy_strategy)
 451 Specify memcpy expansion strategy when expected size is known.
 452
 453 mmemset-strategy=
 454 Target RejectNegative Joined Var(ix86_tune_memset_strategy)
 455 Specify memset expansion strategy when expected size is known.
 456
 457 mstringop-strategy=
 458 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
 459 Chose strategy to generate stringop using.
 460
 461 Enum
 462 Name(stringop_alg) Type(enum stringop_alg)
 463 Valid arguments to -mstringop-strategy=:
 464
 465 EnumValue
 466 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
 467
 468 EnumValue
 469 Enum(stringop_alg) String(libcall) Value(libcall)
 470
 471 EnumValue
 472 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
 473
 474 EnumValue
 475 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
 476
 477 EnumValue
 478 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
 479
 480 EnumValue
 481 Enum(stringop_alg) String(loop) Value(loop)
 482
 483 EnumValue
 484 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
 485
 486 EnumValue
 487 Enum(stringop_alg) String(vector_loop) Value(vector_loop)
 488
 489 mtls-dialect=
 490 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
 491 Use given thread-local storage dialect.
 492
 493 Enum
 494 Name(tls_dialect) Type(enum tls_dialect)
 495 Known TLS dialects (for use with the -mtls-dialect= option):
 496
 497 EnumValue
 498 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
 499
 500 EnumValue
 501 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
 502
 503 mtls-direct-seg-refs
 504 Target Report Mask(TLS_DIRECT_SEG_REFS)
 505 Use direct references against %gs when accessing tls data.
 506
 507 mtune=
 508 Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string)
 509 Schedule code for given CPU.
 510
 511 mtune-ctrl=
 512 Target RejectNegative Joined Var(ix86_tune_ctrl_string)
 513 Fine grain control of tune features.
 514
 515 mno-default
 516 Target RejectNegative Var(ix86_tune_no_default)
 517 Clear all tune features.
 518
 519 mdump-tune-features
 520 Target RejectNegative Var(ix86_dump_tunes)
 521
 522 miamcu
 523 Target Report Mask(IAMCU)
 524 Generate code that conforms to Intel MCU psABI.
 525
 526 mabi=
 527 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
 528 Generate code that conforms to the given ABI.
 529
 530 Enum
 531 Name(calling_abi) Type(enum calling_abi)
 532 Known ABIs (for use with the -mabi= option):
 533
 534 EnumValue
 535 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
 536
 537 EnumValue
 538 Enum(calling_abi) String(ms) Value(MS_ABI)
 539
 540 mcall-ms2sysv-xlogues
 541 Target Report Mask(CALL_MS2SYSV_XLOGUES) Save
 542 Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls.
 543
 544 mveclibabi=
 545 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
 546 Vector library ABI to use.
 547
 548 Enum
 549 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
 550 Known vectorization library ABIs (for use with the -mveclibabi= option):
 551
 552 EnumValue
 553 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
 554
 555 EnumValue
 556 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
 557
 558 mvect8-ret-in-mem
 559 Target Report Mask(VECT8_RETURNS) Save
 560 Return 8-byte vectors in memory.
 561
 562 mrecip
 563 Target Report Mask(RECIP) Save
 564 Generate reciprocals instead of divss and sqrtss.
 565
 566 mrecip=
 567 Target Report RejectNegative Joined Var(ix86_recip_name)
 568 Control generation of reciprocal estimates.
 569
 570 mcld
 571 Target Report Mask(CLD) Save
 572 Generate cld instruction in the function prologue.
 573
 574 mvzeroupper
 575 Target Report Mask(VZEROUPPER) Save
 576 Generate vzeroupper instruction before a transfer of control flow out of
 577 the function.
 578
 579 mstv
 580 Target Report Mask(STV) Save
 581 Disable Scalar to Vector optimization pass transforming 64-bit integer
 582 computations into a vector ones.
 583
 584 mdispatch-scheduler
 585 Target RejectNegative Var(flag_dispatch_scheduler)
 586 Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
 587 or znver1 and Haifa scheduling is selected.
 588
 589 mprefer-avx128
 590 Target Alias(mprefer-vector-width=, 128, 256)
 591 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
 592
 593 mprefer-vector-width=
 594 Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save
 595 Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
 596
 597 Enum
 598 Name(prefer_vector_width) Type(enum prefer_vector_width)
 599 Known preferred register vector length (to use with the -mprefer-vector-width= option):
 600
 601 EnumValue
 602 Enum(prefer_vector_width) String(none) Value(PVW_NONE)
 603
 604 EnumValue
 605 Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
 606
 607 EnumValue
 608 Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
 609
 610 EnumValue
 611 Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
 612
 613 ;; ISA support
 614
 615 m32
 616 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
 617 Generate 32bit i386 code.
 618
 619 m64
 620 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
 621 Generate 64bit x86-64 code.
 622
 623 mx32
 624 Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
 625 Generate 32bit x86-64 code.
 626
 627 m16
 628 Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
 629 Generate 16bit i386 code.
 630
 631 mmmx
 632 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
 633 Support MMX built-in functions.
 634
 635 m3dnow
 636 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
 637 Support 3DNow! built-in functions.
 638
 639 m3dnowa
 640 Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
 641 Support Athlon 3Dnow! built-in functions.
 642
 643 msse
 644 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
 645 Support MMX and SSE built-in functions and code generation.
 646
 647 msse2
 648 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
 649 Support MMX, SSE and SSE2 built-in functions and code generation.
 650
 651 msse3
 652 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
 653 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
 654
 655 mssse3
 656 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
 657 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
 658
 659 msse4.1
 660 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 661 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
 662
 663 msse4.2
 664 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 665 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
 666
 667 msse4
 668 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 669 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
 670
 671 mno-sse4
 672 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 673 Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
 674
 675 msse5
 676 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
 677 ;; Deprecated
 678
 679 mavx
 680 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
 681 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
 682
 683 mavx2
 684 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
 685 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation.
 686
 687 mavx512f
 688 Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
 689 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation.
 690
 691 mavx512pf
 692 Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
 693 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation.
 694
 695 mavx512er
 696 Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
 697 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation.
 698
 699 mavx512cd
 700 Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
 701 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation.
 702
 703 mavx512dq
 704 Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
 705 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation.
 706
 707 mavx512bw
 708 Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
 709 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation.
 710
 711 mavx512vl
 712 Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
 713 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation.
 714
 715 mavx512ifma
 716 Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
 717 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation.
 718
 719 mavx512vbmi
 720 Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
 721 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation.
 722
 723 mavx5124fmaps
 724 Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save
 725 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation.
 726
 727 mavx5124vnniw
 728 Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save
 729 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation.
 730
 731 mavx512vpopcntdq
 732 Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save
 733 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation.
 734
 735 mavx512vbmi2
 736 Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save
 737 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation.
 738
 739 mavx512vnni
 740 Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save
 741 Support AVX512VNNI built-in functions and code generation.
 742
 743 mavx512bitalg
 744 Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save
 745 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation.
 746
 747 mavx512vp2intersect
 748 Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save
 749 Support AVX512VP2INTERSECT built-in functions and code generation.
 750
 751 mfma
 752 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
 753 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.
 754
 755 msse4a
 756 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
 757 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation.
 758
 759 mfma4
 760 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
 761 Support FMA4 built-in functions and code generation.
 762
 763 mxop
 764 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
 765 Support XOP built-in functions and code generation.
 766
 767 mlwp
 768 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
 769 Support LWP built-in functions and code generation.
 770
 771 mabm
 772 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
 773 Support code generation of Advanced Bit Manipulation (ABM) instructions.
 774
 775 mpopcnt
 776 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
 777 Support code generation of popcnt instruction.
 778
 779 mpconfig
 780 Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save
 781 Support PCONFIG built-in functions and code generation.
 782
 783 mwbnoinvd
 784 Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save
 785 Support WBNOINVD built-in functions and code generation.
 786
 787 mptwrite
 788 Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save
 789 Support PTWRITE built-in functions and code generation.
 790
 791 msgx
 792 Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
 793 Support SGX built-in functions and code generation.
 794
 795 mrdpid
 796 Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save
 797 Support RDPID built-in functions and code generation.
 798
 799 mgfni
 800 Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save
 801 Support GFNI built-in functions and code generation.
 802
 803 mvaes
 804 Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save
 805 Support VAES built-in functions and code generation.
 806
 807 mvpclmulqdq
 808 Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save
 809 Support VPCLMULQDQ built-in functions and code generation.
 810
 811 mbmi
 812 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
 813 Support BMI built-in functions and code generation.
 814
 815 mbmi2
 816 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
 817 Support BMI2 built-in functions and code generation.
 818
 819 mlzcnt
 820 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
 821 Support LZCNT built-in function and code generation.
 822
 823 mhle
 824 Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save
 825 Support Hardware Lock Elision prefixes.
 826
 827 mrdseed
 828 Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
 829 Support RDSEED instruction.
 830
 831 mprfchw
 832 Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
 833 Support PREFETCHW instruction.
 834
 835 madx
 836 Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
 837 Support flag-preserving add-carry instructions.
 838
 839 mclflushopt
 840 Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
 841 Support CLFLUSHOPT instructions.
 842
 843 mclwb
 844 Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
 845 Support CLWB instruction.
 846
 847 mpcommit
 848 Target WarnRemoved
 849
 850 mfxsr
 851 Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
 852 Support FXSAVE and FXRSTOR instructions.
 853
 854 mxsave
 855 Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
 856 Support XSAVE and XRSTOR instructions.
 857
 858 mxsaveopt
 859 Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
 860 Support XSAVEOPT instruction.
 861
 862 mxsavec
 863 Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
 864 Support XSAVEC instructions.
 865
 866 mxsaves
 867 Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
 868 Support XSAVES and XRSTORS instructions.
 869
 870 mtbm
 871 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
 872 Support TBM built-in functions and code generation.
 873
 874 mcx16
 875 Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save
 876 Support code generation of cmpxchg16b instruction.
 877
 878 msahf
 879 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
 880 Support code generation of sahf instruction in 64bit x86-64 code.
 881
 882 mmovbe
 883 Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save
 884 Support code generation of movbe instruction.
 885
 886 mcrc32
 887 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
 888 Support code generation of crc32 instruction.
 889
 890 maes
 891 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
 892 Support AES built-in functions and code generation.
 893
 894 msha
 895 Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save
 896 Support SHA1 and SHA256 built-in functions and code generation.
 897
 898 mpclmul
 899 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
 900 Support PCLMUL built-in functions and code generation.
 901
 902 msse2avx
 903 Target Report Var(ix86_sse2avx)
 904 Encode SSE instructions with VEX prefix.
 905
 906 mfsgsbase
 907 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
 908 Support FSGSBASE built-in functions and code generation.
 909
 910 mrdrnd
 911 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
 912 Support RDRND built-in functions and code generation.
 913
 914 mf16c
 915 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
 916 Support F16C built-in functions and code generation.
 917
 918 mprefetchwt1
 919 Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
 920 Support PREFETCHWT1 built-in functions and code generation.
 921
 922 mfentry
 923 Target Report Var(flag_fentry)
 924 Emit profiling counter call at function entry before prologue.
 925
 926 mrecord-mcount
 927 Target Report Var(flag_record_mcount)
 928 Generate __mcount_loc section with all mcount or __fentry__ calls.
 929
 930 mnop-mcount
 931 Target Report Var(flag_nop_mcount)
 932 Generate mcount/__fentry__ calls as nops. To activate they need to be
 933 patched in.
 934
 935 mfentry-name=
 936 Target RejectNegative Joined Var(fentry_name)
 937 Set name of __fentry__ symbol called at function entry.
 938
 939 mfentry-section=
 940 Target RejectNegative Joined Var(fentry_section)
 941 Set name of section to record mrecord-mcount calls.
 942
 943 mskip-rax-setup
 944 Target Report Var(flag_skip_rax_setup)
 945 Skip setting up RAX register when passing variable arguments.
 946
 947 m8bit-idiv
 948 Target Report Mask(USE_8BIT_IDIV) Save
 949 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check.
 950
 951 mavx256-split-unaligned-load
 952 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
 953 Split 32-byte AVX unaligned load.
 954
 955 mavx256-split-unaligned-store
 956 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
 957 Split 32-byte AVX unaligned store.
 958
 959 mrtm
 960 Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
 961 Support RTM built-in functions and code generation.
 962
 963 mmpx
 964 Target WarnRemoved
 965 Removed in GCC 9.  This switch has no effect.
 966
 967 mmwaitx
 968 Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save
 969 Support MWAITX and MONITORX built-in functions and code generation.
 970
 971 mclzero
 972 Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save
 973 Support CLZERO built-in functions and code generation.
 974
 975 mpku
 976 Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save
 977 Support PKU built-in functions and code generation.
 978
 979 mstack-protector-guard=
 980 Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
 981 Use given stack-protector guard.
 982
 983 Enum
 984 Name(stack_protector_guard) Type(enum stack_protector_guard)
 985 Known stack protector guard (for use with the -mstack-protector-guard= option):
 986
 987 EnumValue
 988 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
 989
 990 EnumValue
 991 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
 992
 993 mstack-protector-guard-reg=
 994 Target RejectNegative Joined Var(ix86_stack_protector_guard_reg_str)
 995 Use the given base register for addressing the stack-protector guard.
 996
 997 TargetVariable
 998 addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC
 999
1000 mstack-protector-guard-offset=
1001 Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str)
1002 Use the given offset for addressing the stack-protector guard.
1003
1004 TargetVariable
1005 HOST_WIDE_INT ix86_stack_protector_guard_offset = 0
1006
1007 mstack-protector-guard-symbol=
1008 Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str)
1009 Use the given symbol for addressing the stack-protector guard.
1010
1011 mmitigate-rop
1012 Target WarnRemoved
1013
1014 mgeneral-regs-only
1015 Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
1016 Generate code which uses only the general registers.
1017
1018 mshstk
1019 Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save
1020 Enable shadow stack built-in functions from Control-flow Enforcement
1021 Technology (CET).
1022
1023 mcet-switch
1024 Target Report Undocumented Var(flag_cet_switch) Init(0)
1025 Turn on CET instrumentation for switch statements that use a jump table and
1026 an indirect jump.
1027
1028 mmanual-endbr
1029 Target Report Var(flag_manual_endbr) Init(0)
1030 Insert ENDBR instruction at function entry only via cf_check attribute
1031 for CET instrumentation.
1032
1033 mforce-indirect-call
1034 Target Report Var(flag_force_indirect_call) Init(0)
1035 Make all function calls indirect.
1036
1037 mindirect-branch=
1038 Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
1039 Convert indirect call and jump to call and return thunks.
1040
1041 mfunction-return=
1042 Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
1043 Convert function return to call and return thunk.
1044
1045 Enum
1046 Name(indirect_branch) Type(enum indirect_branch)
1047 Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options):
1048
1049 EnumValue
1050 Enum(indirect_branch) String(keep) Value(indirect_branch_keep)
1051
1052 EnumValue
1053 Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk)
1054
1055 EnumValue
1056 Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline)
1057
1058 EnumValue
1059 Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
1060
1061 mindirect-branch-register
1062 Target Report Var(ix86_indirect_branch_register) Init(0)
1063 Force indirect call and jump via register.
1064
1065 mmovdiri
1066 Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save
1067 Support MOVDIRI built-in functions and code generation.
1068
1069 mmovdir64b
1070 Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save
1071 Support MOVDIR64B built-in functions and code generation.
1072
1073 mwaitpkg
1074 Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save
1075 Support WAITPKG built-in functions and code generation.
1076
1077 mcldemote
1078 Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save
1079 Support CLDEMOTE built-in functions and code generation.
1080
1081 minstrument-return=
1082 Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none)
1083 Instrument function exit in instrumented functions with __fentry__.
1084
1085 Enum
1086 Name(instrument_return) Type(enum instrument_return)
1087 Known choices for return instrumentation with -minstrument-return=:
1088
1089 EnumValue
1090 Enum(instrument_return) String(none) Value(instrument_return_none)
1091
1092 EnumValue
1093 Enum(instrument_return) String(call) Value(instrument_return_call)
1094
1095 EnumValue
1096 Enum(instrument_return) String(nop5) Value(instrument_return_nop5)
1097
1098 mrecord-return
1099 Target Report Var(ix86_flag_record_return) Init(0)
1100 Generate a __return_loc section pointing to all return instrumentation code.
1101
1102 mavx512bf16
1103 Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save
1104 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
1105 AVX512BF16 built-in functions and code generation.
1106
1107 menqcmd
1108 Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
1109 Support ENQCMD built-in functions and code generation.