gcc/config/i386/i386.opt

   1 ; Options for the IA-32 and AMD64 ports of the compiler.
   2
   3 ; Copyright (C) 2005-2017 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 ; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 ; for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/i386/i386-opts.h
  23
  24 ; Bit flags that specify the ISA we are compiling for.
  25 Variable
  26 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
  27
  28 Variable
  29 HOST_WIDE_INT ix86_isa_flags2 = 0
  30
  31 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
  32 ; on the command line.
  33 Variable
  34 HOST_WIDE_INT ix86_isa_flags_explicit
  35
  36 Variable
  37 HOST_WIDE_INT ix86_isa_flags2_explicit
  38
  39 ; Additional target flags
  40 Variable
  41 int ix86_target_flags
  42
  43 TargetVariable
  44 int recip_mask = RECIP_MASK_DEFAULT
  45
  46 Variable
  47 int recip_mask_explicit
  48
  49 TargetSave
  50 int x_recip_mask_explicit
  51
  52 ;; Definitions to add to the cl_target_option structure
  53 ;; -march= processor
  54 TargetSave
  55 unsigned char arch
  56
  57 ;; -mtune= processor
  58 TargetSave
  59 unsigned char tune
  60
  61 ;; -march= processor-string
  62 TargetSave
  63 const char *x_ix86_arch_string
  64
  65 ;; -mtune= processor-string
  66 TargetSave
  67 const char *x_ix86_tune_string
  68
  69 ;; CPU schedule model
  70 TargetSave
  71 unsigned char schedule
  72
  73 ;; True if processor has SSE prefetch instruction.
  74 TargetSave
  75 unsigned char prefetch_sse
  76
  77 ;; branch cost
  78 TargetSave
  79 unsigned char branch_cost
  80
  81 ;; which flags were passed by the user
  82 TargetSave
  83 HOST_WIDE_INT x_ix86_isa_flags2_explicit
  84
  85 ;; which flags were passed by the user
  86 TargetSave
  87 HOST_WIDE_INT x_ix86_isa_flags_explicit
  88
  89 ;; whether -mtune was not specified
  90 TargetSave
  91 unsigned char tune_defaulted
  92
  93 ;; whether -march was specified
  94 TargetSave
  95 unsigned char arch_specified
  96
  97 ;; -mcmodel= model
  98 TargetSave
  99 enum cmodel x_ix86_cmodel
 100
 101 ;; -mabi=
 102 TargetSave
 103 enum calling_abi x_ix86_abi
 104
 105 ;; -masm=
 106 TargetSave
 107 enum asm_dialect x_ix86_asm_dialect
 108
 109 ;; -mbranch-cost=
 110 TargetSave
 111 int x_ix86_branch_cost
 112
 113 ;; -mdump-tune-features=
 114 TargetSave
 115 int x_ix86_dump_tunes
 116
 117 ;; -mstackrealign=
 118 TargetSave
 119 int x_ix86_force_align_arg_pointer
 120
 121 ;; -mforce-drap=
 122 TargetSave
 123 int x_ix86_force_drap
 124
 125 ;; -mincoming-stack-boundary=
 126 TargetSave
 127 int x_ix86_incoming_stack_boundary_arg
 128
 129 ;; -maddress-mode=
 130 TargetSave
 131 enum pmode x_ix86_pmode
 132
 133 ;; -mpreferred-stack-boundary=
 134 TargetSave
 135 int x_ix86_preferred_stack_boundary_arg
 136
 137 ;; -mrecip=
 138 TargetSave
 139 const char *x_ix86_recip_name
 140
 141 ;; -mregparm=
 142 TargetSave
 143 int x_ix86_regparm
 144
 145 ;; -mlarge-data-threshold=
 146 TargetSave
 147 int x_ix86_section_threshold
 148
 149 ;; -msse2avx=
 150 TargetSave
 151 int x_ix86_sse2avx
 152
 153 ;; -mstack-protector-guard=
 154 TargetSave
 155 enum stack_protector_guard x_ix86_stack_protector_guard
 156
 157 ;; -mstringop-strategy=
 158 TargetSave
 159 enum stringop_alg x_ix86_stringop_alg
 160
 161 ;; -mtls-dialect=
 162 TargetSave
 163 enum tls_dialect x_ix86_tls_dialect
 164
 165 ;; -mtune-ctrl=
 166 TargetSave
 167 const char *x_ix86_tune_ctrl_string
 168
 169 ;; -mmemcpy-strategy=
 170 TargetSave
 171 const char *x_ix86_tune_memcpy_strategy
 172
 173 ;; -mmemset-strategy=
 174 TargetSave
 175 const char *x_ix86_tune_memset_strategy
 176
 177 ;; -mno-default=
 178 TargetSave
 179 int x_ix86_tune_no_default
 180
 181 ;; -mveclibabi=
 182 TargetSave
 183 enum ix86_veclibabi x_ix86_veclibabi_type
 184
 185 ;; x86 options
 186 m128bit-long-double
 187 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
 188 sizeof(long double) is 16.
 189
 190 m80387
 191 Target Report Mask(80387) Save
 192 Use hardware fp.
 193
 194 m96bit-long-double
 195 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
 196 sizeof(long double) is 12.
 197
 198 mlong-double-80
 199 Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
 200 Use 80-bit long double.
 201
 202 mlong-double-64
 203 Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
 204 Use 64-bit long double.
 205
 206 mlong-double-128
 207 Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
 208 Use 128-bit long double.
 209
 210 maccumulate-outgoing-args
 211 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
 212 Reserve space for outgoing arguments in the function prologue.
 213
 214 malign-double
 215 Target Report Mask(ALIGN_DOUBLE) Save
 216 Align some doubles on dword boundary.
 217
 218 malign-functions=
 219 Target RejectNegative Joined UInteger
 220 Function starts are aligned to this power of 2.
 221
 222 malign-jumps=
 223 Target RejectNegative Joined UInteger
 224 Jump targets are aligned to this power of 2.
 225
 226 malign-loops=
 227 Target RejectNegative Joined UInteger
 228 Loop code aligned to this power of 2.
 229
 230 malign-stringops
 231 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
 232 Align destination of the string operations.
 233
 234 malign-data=
 235 Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat)
 236 Use the given data alignment.
 237
 238 Enum
 239 Name(ix86_align_data) Type(enum ix86_align_data)
 240 Known data alignment choices (for use with the -malign-data= option):
 241
 242 EnumValue
 243 Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat)
 244
 245 EnumValue
 246 Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi)
 247
 248 EnumValue
 249 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
 250
 251 march=
 252 Target RejectNegative Joined Var(ix86_arch_string)
 253 Generate code for given CPU.
 254
 255 masm=
 256 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
 257 Use given assembler dialect.
 258
 259 Enum
 260 Name(asm_dialect) Type(enum asm_dialect)
 261 Known assembler dialects (for use with the -masm-dialect= option):
 262
 263 EnumValue
 264 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
 265
 266 EnumValue
 267 Enum(asm_dialect) String(att) Value(ASM_ATT)
 268
 269 mbranch-cost=
 270 Target RejectNegative Joined UInteger Var(ix86_branch_cost)
 271 Branches are this expensive (1-5, arbitrary units).
 272
 273 mlarge-data-threshold=
 274 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD)
 275 Data greater than given threshold will go into .ldata section in x86-64 medium model.
 276
 277 mcmodel=
 278 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
 279 Use given x86-64 code model.
 280
 281 Enum
 282 Name(cmodel) Type(enum cmodel)
 283 Known code models (for use with the -mcmodel= option):
 284
 285 EnumValue
 286 Enum(cmodel) String(small) Value(CM_SMALL)
 287
 288 EnumValue
 289 Enum(cmodel) String(medium) Value(CM_MEDIUM)
 290
 291 EnumValue
 292 Enum(cmodel) String(large) Value(CM_LARGE)
 293
 294 EnumValue
 295 Enum(cmodel) String(32) Value(CM_32)
 296
 297 EnumValue
 298 Enum(cmodel) String(kernel) Value(CM_KERNEL)
 299
 300 maddress-mode=
 301 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
 302 Use given address mode.
 303
 304 Enum
 305 Name(pmode) Type(enum pmode)
 306 Known address mode (for use with the -maddress-mode= option):
 307
 308 EnumValue
 309 Enum(pmode) String(short) Value(PMODE_SI)
 310
 311 EnumValue
 312 Enum(pmode) String(long) Value(PMODE_DI)
 313
 314 mcpu=
 315 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
 316
 317 mfancy-math-387
 318 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
 319 Generate sin, cos, sqrt for FPU.
 320
 321 mforce-drap
 322 Target Report Var(ix86_force_drap)
 323 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack.
 324
 325 mfp-ret-in-387
 326 Target Report Mask(FLOAT_RETURNS) Save
 327 Return values of functions in FPU registers.
 328
 329 mfpmath=
 330 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
 331 Generate floating point mathematics using given instruction set.
 332
 333 Enum
 334 Name(fpmath_unit) Type(enum fpmath_unit)
 335 Valid arguments to -mfpmath=:
 336
 337 EnumValue
 338 Enum(fpmath_unit) String(387) Value(FPMATH_387)
 339
 340 EnumValue
 341 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
 342
 343 EnumValue
 344 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 345
 346 EnumValue
 347 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 348
 349 EnumValue
 350 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 351
 352 EnumValue
 353 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 354
 355 EnumValue
 356 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 357
 358 mhard-float
 359 Target RejectNegative Mask(80387) Save
 360 Use hardware fp.
 361
 362 mieee-fp
 363 Target Report Mask(IEEE_FP) Save
 364 Use IEEE math for fp comparisons.
 365
 366 minline-all-stringops
 367 Target Report Mask(INLINE_ALL_STRINGOPS) Save
 368 Inline all known string operations.
 369
 370 minline-stringops-dynamically
 371 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
 372 Inline memset/memcpy string operations, but perform inline version only for small blocks.
 373
 374 mintel-syntax
 375 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
 376 ;; Deprecated
 377
 378 mms-bitfields
 379 Target Report Mask(MS_BITFIELD_LAYOUT) Save
 380 Use native (MS) bitfield layout.
 381
 382 mno-align-stringops
 383 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
 384
 385 mno-fancy-math-387
 386 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
 387
 388 mno-push-args
 389 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
 390
 391 mno-red-zone
 392 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
 393
 394 momit-leaf-frame-pointer
 395 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
 396 Omit the frame pointer in leaf functions.
 397
 398 mpc32
 399 Target RejectNegative Report
 400 Set 80387 floating-point precision to 32-bit.
 401
 402 mpc64
 403 Target RejectNegative Report
 404 Set 80387 floating-point precision to 64-bit.
 405
 406 mpc80
 407 Target RejectNegative Report
 408 Set 80387 floating-point precision to 80-bit.
 409
 410 mpreferred-stack-boundary=
 411 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
 412 Attempt to keep stack aligned to this power of 2.
 413
 414 mincoming-stack-boundary=
 415 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
 416 Assume incoming stack aligned to this power of 2.
 417
 418 mpush-args
 419 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
 420 Use push instructions to save outgoing arguments.
 421
 422 mred-zone
 423 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
 424 Use red-zone in the x86-64 code.
 425
 426 mregparm=
 427 Target RejectNegative Joined UInteger Var(ix86_regparm)
 428 Number of registers used to pass integer arguments.
 429
 430 mrtd
 431 Target Report Mask(RTD) Save
 432 Alternate calling convention.
 433
 434 msoft-float
 435 Target InverseMask(80387) Save
 436 Do not use hardware fp.
 437
 438 msseregparm
 439 Target RejectNegative Mask(SSEREGPARM) Save
 440 Use SSE register passing conventions for SF and DF mode.
 441
 442 mstackrealign
 443 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
 444 Realign stack in prologue.
 445
 446 mstack-arg-probe
 447 Target Report Mask(STACK_PROBE) Save
 448 Enable stack probing.
 449
 450 mmemcpy-strategy=
 451 Target RejectNegative Joined Var(ix86_tune_memcpy_strategy)
 452 Specify memcpy expansion strategy when expected size is known.
 453
 454 mmemset-strategy=
 455 Target RejectNegative Joined Var(ix86_tune_memset_strategy)
 456 Specify memset expansion strategy when expected size is known.
 457
 458 mstringop-strategy=
 459 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
 460 Chose strategy to generate stringop using.
 461
 462 Enum
 463 Name(stringop_alg) Type(enum stringop_alg)
 464 Valid arguments to -mstringop-strategy=:
 465
 466 EnumValue
 467 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
 468
 469 EnumValue
 470 Enum(stringop_alg) String(libcall) Value(libcall)
 471
 472 EnumValue
 473 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
 474
 475 EnumValue
 476 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
 477
 478 EnumValue
 479 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
 480
 481 EnumValue
 482 Enum(stringop_alg) String(loop) Value(loop)
 483
 484 EnumValue
 485 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
 486
 487 EnumValue
 488 Enum(stringop_alg) String(vector_loop) Value(vector_loop)
 489
 490 mtls-dialect=
 491 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
 492 Use given thread-local storage dialect.
 493
 494 Enum
 495 Name(tls_dialect) Type(enum tls_dialect)
 496 Known TLS dialects (for use with the -mtls-dialect= option):
 497
 498 EnumValue
 499 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
 500
 501 EnumValue
 502 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
 503
 504 mtls-direct-seg-refs
 505 Target Report Mask(TLS_DIRECT_SEG_REFS)
 506 Use direct references against %gs when accessing tls data.
 507
 508 mtune=
 509 Target RejectNegative Joined Var(ix86_tune_string)
 510 Schedule code for given CPU.
 511
 512 mtune-ctrl=
 513 Target RejectNegative Joined Var(ix86_tune_ctrl_string)
 514 Fine grain control of tune features.
 515
 516 mno-default
 517 Target RejectNegative Var(ix86_tune_no_default) Init(0)
 518 Clear all tune features.
 519
 520 mdump-tune-features
 521 Target RejectNegative Var(ix86_dump_tunes) Init(0)
 522
 523 miamcu
 524 Target Report Mask(IAMCU)
 525 Generate code that conforms to Intel MCU psABI.
 526
 527 mabi=
 528 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
 529 Generate code that conforms to the given ABI.
 530
 531 Enum
 532 Name(calling_abi) Type(enum calling_abi)
 533 Known ABIs (for use with the -mabi= option):
 534
 535 EnumValue
 536 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
 537
 538 EnumValue
 539 Enum(calling_abi) String(ms) Value(MS_ABI)
 540
 541 mveclibabi=
 542 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
 543 Vector library ABI to use.
 544
 545 Enum
 546 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
 547 Known vectorization library ABIs (for use with the -mveclibabi= option):
 548
 549 EnumValue
 550 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
 551
 552 EnumValue
 553 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
 554
 555 mvect8-ret-in-mem
 556 Target Report Mask(VECT8_RETURNS) Save
 557 Return 8-byte vectors in memory.
 558
 559 mrecip
 560 Target Report Mask(RECIP) Save
 561 Generate reciprocals instead of divss and sqrtss.
 562
 563 mrecip=
 564 Target Report RejectNegative Joined Var(ix86_recip_name)
 565 Control generation of reciprocal estimates.
 566
 567 mcld
 568 Target Report Mask(CLD) Save
 569 Generate cld instruction in the function prologue.
 570
 571 mvzeroupper
 572 Target Report Mask(VZEROUPPER) Save
 573 Generate vzeroupper instruction before a transfer of control flow out of
 574 the function.
 575
 576 mstv
 577 Target Report Mask(STV) Save
 578 Disable Scalar to Vector optimization pass transforming 64-bit integer
 579 computations into a vector ones.
 580
 581 mdispatch-scheduler
 582 Target RejectNegative Var(flag_dispatch_scheduler)
 583 Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
 584 or znver1 and Haifa scheduling is selected.
 585
 586 mprefer-avx128
 587 Target Report Mask(PREFER_AVX128) SAVE
 588 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
 589
 590 ;; ISA support
 591
 592 m32
 593 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
 594 Generate 32bit i386 code.
 595
 596 m64
 597 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
 598 Generate 64bit x86-64 code.
 599
 600 mx32
 601 Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
 602 Generate 32bit x86-64 code.
 603
 604 m16
 605 Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
 606 Generate 16bit i386 code.
 607
 608 mmmx
 609 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
 610 Support MMX built-in functions.
 611
 612 m3dnow
 613 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
 614 Support 3DNow! built-in functions.
 615
 616 m3dnowa
 617 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
 618 Support Athlon 3Dnow! built-in functions.
 619
 620 msse
 621 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
 622 Support MMX and SSE built-in functions and code generation.
 623
 624 msse2
 625 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
 626 Support MMX, SSE and SSE2 built-in functions and code generation.
 627
 628 msse3
 629 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
 630 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
 631
 632 mssse3
 633 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
 634 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
 635
 636 msse4.1
 637 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 638 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
 639
 640 msse4.2
 641 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 642 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
 643
 644 msse4
 645 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 646 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
 647
 648 mno-sse4
 649 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 650 Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
 651
 652 msse5
 653 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
 654 ;; Deprecated
 655
 656 mavx
 657 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
 658 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
 659
 660 mavx2
 661 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
 662 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation.
 663
 664 mavx512f
 665 Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
 666 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation.
 667
 668 mavx512pf
 669 Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
 670 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation.
 671
 672 mavx512er
 673 Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
 674 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation.
 675
 676 mavx512cd
 677 Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
 678 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation.
 679
 680 mavx512dq
 681 Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
 682 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation.
 683
 684 mavx512bw
 685 Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
 686 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation.
 687
 688 mavx512vl
 689 Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
 690 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation.
 691
 692 mavx512ifma
 693 Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
 694 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation.
 695
 696 mavx512vbmi
 697 Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
 698 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation.
 699
 700 mavx5124fmaps
 701 Target Report Mask(ISA_AVX5124FMAPS) Var(ix86_isa_flags2) Save
 702 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation.
 703
 704 mavx5124vnniw
 705 Target Report Mask(ISA_AVX5124VNNIW) Var(ix86_isa_flags2) Save
 706 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation.
 707
 708 mfma
 709 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
 710 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.
 711
 712 msse4a
 713 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
 714 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation.
 715
 716 mfma4
 717 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
 718 Support FMA4 built-in functions and code generation.
 719
 720 mxop
 721 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
 722 Support XOP built-in functions and code generation.
 723
 724 mlwp
 725 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
 726 Support LWP built-in functions and code generation.
 727
 728 mabm
 729 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
 730 Support code generation of Advanced Bit Manipulation (ABM) instructions.
 731
 732 mpopcnt
 733 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
 734 Support code generation of popcnt instruction.
 735
 736 mbmi
 737 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
 738 Support BMI built-in functions and code generation.
 739
 740 mbmi2
 741 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
 742 Support BMI2 built-in functions and code generation.
 743
 744 mlzcnt
 745 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
 746 Support LZCNT built-in function and code generation.
 747
 748 mhle
 749 Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
 750 Support Hardware Lock Elision prefixes.
 751
 752 mrdseed
 753 Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
 754 Support RDSEED instruction.
 755
 756 mprfchw
 757 Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
 758 Support PREFETCHW instruction.
 759
 760 madx
 761 Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
 762 Support flag-preserving add-carry instructions.
 763
 764 mclflushopt
 765 Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
 766 Support CLFLUSHOPT instructions.
 767
 768 mclwb
 769 Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
 770 Support CLWB instruction.
 771
 772 mpcommit
 773 Target Undocumented Warn(%<-mpcommit%> was deprecated)
 774 ;; Deprecated
 775
 776 mfxsr
 777 Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
 778 Support FXSAVE and FXRSTOR instructions.
 779
 780 mxsave
 781 Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
 782 Support XSAVE and XRSTOR instructions.
 783
 784 mxsaveopt
 785 Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
 786 Support XSAVEOPT instruction.
 787
 788 mxsavec
 789 Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
 790 Support XSAVEC instructions.
 791
 792 mxsaves
 793 Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
 794 Support XSAVES and XRSTORS instructions.
 795
 796 mtbm
 797 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
 798 Support TBM built-in functions and code generation.
 799
 800 mcx16
 801 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
 802 Support code generation of cmpxchg16b instruction.
 803
 804 msahf
 805 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
 806 Support code generation of sahf instruction in 64bit x86-64 code.
 807
 808 mmovbe
 809 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
 810 Support code generation of movbe instruction.
 811
 812 mcrc32
 813 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
 814 Support code generation of crc32 instruction.
 815
 816 maes
 817 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
 818 Support AES built-in functions and code generation.
 819
 820 msha
 821 Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save
 822 Support SHA1 and SHA256 built-in functions and code generation.
 823
 824 mpclmul
 825 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
 826 Support PCLMUL built-in functions and code generation.
 827
 828 msse2avx
 829 Target Report Var(ix86_sse2avx)
 830 Encode SSE instructions with VEX prefix.
 831
 832 mfsgsbase
 833 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
 834 Support FSGSBASE built-in functions and code generation.
 835
 836 mrdrnd
 837 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
 838 Support RDRND built-in functions and code generation.
 839
 840 mf16c
 841 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
 842 Support F16C built-in functions and code generation.
 843
 844 mprefetchwt1
 845 Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
 846 Support PREFETCHWT1 built-in functions and code generation.
 847
 848 mfentry
 849 Target Report Var(flag_fentry) Init(-1)
 850 Emit profiling counter call at function entry before prologue.
 851
 852 mrecord-mcount
 853 Target Report Var(flag_record_mcount) Init(0)
 854 Generate __mcount_loc section with all mcount or __fentry__ calls.
 855
 856 mnop-mcount
 857 Target Report Var(flag_nop_mcount) Init(0)
 858 Generate mcount/__fentry__ calls as nops. To activate they need to be
 859 patched in.
 860
 861 mskip-rax-setup
 862 Target Report Var(flag_skip_rax_setup) Init(0)
 863 Skip setting up RAX register when passing variable arguments.
 864
 865 m8bit-idiv
 866 Target Report Mask(USE_8BIT_IDIV) Save
 867 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check.
 868
 869 mavx256-split-unaligned-load
 870 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
 871 Split 32-byte AVX unaligned load.
 872
 873 mavx256-split-unaligned-store
 874 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
 875 Split 32-byte AVX unaligned store.
 876
 877 mrtm
 878 Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
 879 Support RTM built-in functions and code generation.
 880
 881 mmpx
 882 Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save
 883 Support MPX code generation.
 884
 885 mmwaitx
 886 Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save
 887 Support MWAITX and MONITORX built-in functions and code generation.
 888
 889 mclzero
 890 Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save
 891 Support CLZERO built-in functions and code generation.
 892
 893 mpku
 894 Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save
 895 Support PKU built-in functions and code generation.
 896
 897 mstack-protector-guard=
 898 Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
 899 Use given stack-protector guard.
 900
 901 Enum
 902 Name(stack_protector_guard) Type(enum stack_protector_guard)
 903 Known stack protector guard (for use with the -mstack-protector-guard= option):
 904
 905 EnumValue
 906 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
 907
 908 EnumValue
 909 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
 910
 911 mmitigate-rop
 912 Target Var(flag_mitigate_rop) Init(0)
 913 Attempt to avoid generating instruction sequences containing ret bytes.
 914
 915 mgeneral-regs-only
 916 Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
 917 Generate code which uses only the general registers.