gcc/config/i386/i386.opt

   1 ; Options for the IA-32 and AMD64 ports of the compiler.
   2
   3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009,
   4 ; 2010, 2011 Free Software Foundation, Inc.
   5 ;
   6 ; This file is part of GCC.
   7 ;
   8 ; GCC is free software; you can redistribute it and/or modify it under
   9 ; the terms of the GNU General Public License as published by the Free
  10 ; Software Foundation; either version 3, or (at your option) any later
  11 ; version.
  12 ;
  13 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 ; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 ; for more details.
  17 ;
  18 ; You should have received a copy of the GNU General Public License
  19 ; along with GCC; see the file COPYING3.  If not see
  20 ; <http://www.gnu.org/licenses/>.
  21
  22 HeaderInclude
  23 config/i386/i386-opts.h
  24
  25 ; Bit flags that specify the ISA we are compiling for.
  26 Variable
  27 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
  28
  29 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
  30 ; on the command line.
  31 Variable
  32 HOST_WIDE_INT ix86_isa_flags_explicit
  33
  34 TargetVariable
  35 int recip_mask = RECIP_MASK_DEFAULT
  36
  37 Variable
  38 int recip_mask_explicit
  39
  40 TargetSave
  41 int x_recip_mask_explicit
  42
  43 ;; Definitions to add to the cl_target_option structure
  44 ;; -march= processor
  45 TargetSave
  46 unsigned char arch
  47
  48 ;; -mtune= processor
  49 TargetSave
  50 unsigned char tune
  51
  52 ;; CPU schedule model
  53 TargetSave
  54 unsigned char schedule
  55
  56 ;; branch cost
  57 TargetSave
  58 unsigned char branch_cost
  59
  60 ;; which flags were passed by the user
  61 TargetSave
  62 HOST_WIDE_INT x_ix86_isa_flags_explicit
  63
  64 ;; which flags were passed by the user
  65 TargetSave
  66 int ix86_target_flags_explicit
  67
  68 ;; whether -mtune was not specified
  69 TargetSave
  70 unsigned char tune_defaulted
  71
  72 ;; whether -march was specified
  73 TargetSave
  74 unsigned char arch_specified
  75
  76 ;; x86 options
  77 m128bit-long-double
  78 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
  79 sizeof(long double) is 16
  80
  81 m80387
  82 Target Report Mask(80387) Save
  83 Use hardware fp
  84
  85 m96bit-long-double
  86 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
  87 sizeof(long double) is 12
  88
  89 maccumulate-outgoing-args
  90 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
  91 Reserve space for outgoing arguments in the function prologue
  92
  93 malign-double
  94 Target Report Mask(ALIGN_DOUBLE) Save
  95 Align some doubles on dword boundary
  96
  97 malign-functions=
  98 Target RejectNegative Joined UInteger
  99 Function starts are aligned to this power of 2
 100
 101 malign-jumps=
 102 Target RejectNegative Joined UInteger
 103 Jump targets are aligned to this power of 2
 104
 105 malign-loops=
 106 Target RejectNegative Joined UInteger
 107 Loop code aligned to this power of 2
 108
 109 malign-stringops
 110 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
 111 Align destination of the string operations
 112
 113 march=
 114 Target RejectNegative Joined Var(ix86_arch_string)
 115 Generate code for given CPU
 116
 117 masm=
 118 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
 119 Use given assembler dialect
 120
 121 Enum
 122 Name(asm_dialect) Type(enum asm_dialect)
 123 Known assembler dialects (for use with the -masm-dialect= option):
 124
 125 EnumValue
 126 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
 127
 128 EnumValue
 129 Enum(asm_dialect) String(att) Value(ASM_ATT)
 130
 131 mbranch-cost=
 132 Target RejectNegative Joined UInteger Var(ix86_branch_cost)
 133 Branches are this expensive (1-5, arbitrary units)
 134
 135 mlarge-data-threshold=
 136 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(65536)
 137 Data greater than given threshold will go into .ldata section in x86-64 medium model
 138
 139 mcmodel=
 140 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
 141 Use given x86-64 code model
 142
 143 Enum
 144 Name(cmodel) Type(enum cmodel)
 145 Known code models (for use with the -mcmodel= option):
 146
 147 EnumValue
 148 Enum(cmodel) String(small) Value(CM_SMALL)
 149
 150 EnumValue
 151 Enum(cmodel) String(medium) Value(CM_MEDIUM)
 152
 153 EnumValue
 154 Enum(cmodel) String(large) Value(CM_LARGE)
 155
 156 EnumValue
 157 Enum(cmodel) String(32) Value(CM_32)
 158
 159 EnumValue
 160 Enum(cmodel) String(kernel) Value(CM_KERNEL)
 161
 162 maddress-mode=
 163 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
 164 Use given address mode
 165
 166 Enum
 167 Name(pmode) Type(enum pmode)
 168 Known address mode (for use with the -maddress-mode= option):
 169
 170 EnumValue
 171 Enum(pmode) String(short) Value(PMODE_SI)
 172
 173 EnumValue
 174 Enum(pmode) String(long) Value(PMODE_DI)
 175
 176 mcpu=
 177 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
 178
 179 mfancy-math-387
 180 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
 181 Generate sin, cos, sqrt for FPU
 182
 183 mforce-drap
 184 Target Report Var(ix86_force_drap)
 185 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
 186
 187 mfp-ret-in-387
 188 Target Report Mask(FLOAT_RETURNS) Save
 189 Return values of functions in FPU registers
 190
 191 mfpmath=
 192 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
 193 Generate floating point mathematics using given instruction set
 194
 195 Enum
 196 Name(fpmath_unit) Type(enum fpmath_unit)
 197 Valid arguments to -mfpmath=:
 198
 199 EnumValue
 200 Enum(fpmath_unit) String(387) Value(FPMATH_387)
 201
 202 EnumValue
 203 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
 204
 205 EnumValue
 206 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 207
 208 EnumValue
 209 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 210
 211 EnumValue
 212 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 213
 214 EnumValue
 215 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 216
 217 EnumValue
 218 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 219
 220 mhard-float
 221 Target RejectNegative Mask(80387) Save
 222 Use hardware fp
 223
 224 mieee-fp
 225 Target Report Mask(IEEE_FP) Save
 226 Use IEEE math for fp comparisons
 227
 228 minline-all-stringops
 229 Target Report Mask(INLINE_ALL_STRINGOPS) Save
 230 Inline all known string operations
 231
 232 minline-stringops-dynamically
 233 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
 234 Inline memset/memcpy string operations, but perform inline version only for small blocks
 235
 236 mintel-syntax
 237 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
 238 ;; Deprecated
 239
 240 mms-bitfields
 241 Target Report Mask(MS_BITFIELD_LAYOUT) Save
 242 Use native (MS) bitfield layout
 243
 244 mno-align-stringops
 245 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
 246
 247 mno-fancy-math-387
 248 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
 249
 250 mno-push-args
 251 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
 252
 253 mno-red-zone
 254 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
 255
 256 momit-leaf-frame-pointer
 257 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
 258 Omit the frame pointer in leaf functions
 259
 260 mpc32
 261 Target RejectNegative Report
 262 Set 80387 floating-point precision to 32-bit
 263
 264 mpc64
 265 Target RejectNegative Report
 266 Set 80387 floating-point precision to 64-bit
 267
 268 mpc80
 269 Target RejectNegative Report
 270 Set 80387 floating-point precision to 80-bit
 271
 272 mpreferred-stack-boundary=
 273 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
 274 Attempt to keep stack aligned to this power of 2
 275
 276 mincoming-stack-boundary=
 277 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
 278 Assume incoming stack aligned to this power of 2
 279
 280 mpush-args
 281 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
 282 Use push instructions to save outgoing arguments
 283
 284 mred-zone
 285 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
 286 Use red-zone in the x86-64 code
 287
 288 mregparm=
 289 Target RejectNegative Joined UInteger Var(ix86_regparm)
 290 Number of registers used to pass integer arguments
 291
 292 mrtd
 293 Target Report Mask(RTD) Save
 294 Alternate calling convention
 295
 296 msoft-float
 297 Target InverseMask(80387) Save
 298 Do not use hardware fp
 299
 300 msseregparm
 301 Target RejectNegative Mask(SSEREGPARM) Save
 302 Use SSE register passing conventions for SF and DF mode
 303
 304 mstackrealign
 305 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
 306 Realign stack in prologue
 307
 308 mstack-arg-probe
 309 Target Report Mask(STACK_PROBE) Save
 310 Enable stack probing
 311
 312 mstringop-strategy=
 313 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
 314 Chose strategy to generate stringop using
 315
 316 Enum
 317 Name(stringop_alg) Type(enum stringop_alg)
 318 Valid arguments to -mstringop-strategy=:
 319
 320 EnumValue
 321 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
 322
 323 EnumValue
 324 Enum(stringop_alg) String(libcall) Value(libcall)
 325
 326 EnumValue
 327 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
 328
 329 EnumValue
 330 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
 331
 332 EnumValue
 333 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
 334
 335 EnumValue
 336 Enum(stringop_alg) String(loop) Value(loop)
 337
 338 EnumValue
 339 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
 340
 341 mtls-dialect=
 342 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
 343 Use given thread-local storage dialect
 344
 345 Enum
 346 Name(tls_dialect) Type(enum tls_dialect)
 347 Known TLS dialects (for use with the -mtls-dialect= option):
 348
 349 EnumValue
 350 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
 351
 352 EnumValue
 353 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
 354
 355 mtls-direct-seg-refs
 356 Target Report Mask(TLS_DIRECT_SEG_REFS)
 357 Use direct references against %gs when accessing tls data
 358
 359 mtune=
 360 Target RejectNegative Joined Var(ix86_tune_string)
 361 Schedule code for given CPU
 362
 363 mabi=
 364 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
 365 Generate code that conforms to the given ABI
 366
 367 Enum
 368 Name(calling_abi) Type(enum calling_abi)
 369 Known ABIs (for use with the -mabi= option):
 370
 371 EnumValue
 372 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
 373
 374 EnumValue
 375 Enum(calling_abi) String(ms) Value(MS_ABI)
 376
 377 mveclibabi=
 378 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
 379 Vector library ABI to use
 380
 381 Enum
 382 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
 383 Known vectorization library ABIs (for use with the -mveclibabi= option):
 384
 385 EnumValue
 386 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
 387
 388 EnumValue
 389 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
 390
 391 mvect8-ret-in-mem
 392 Target Report Mask(VECT8_RETURNS) Save
 393 Return 8-byte vectors in memory
 394
 395 mrecip
 396 Target Report Mask(RECIP) Save
 397 Generate reciprocals instead of divss and sqrtss.
 398
 399 mrecip=
 400 Target Report RejectNegative Joined Var(ix86_recip_name)
 401 Control generation of reciprocal estimates.
 402
 403 mcld
 404 Target Report Mask(CLD) Save
 405 Generate cld instruction in the function prologue.
 406
 407 mvzeroupper
 408 Target Report Mask(VZEROUPPER) Save
 409 Generate vzeroupper instruction before a transfer of control flow out of
 410 the function.
 411
 412 mdispatch-scheduler
 413 Target RejectNegative Var(flag_dispatch_scheduler)
 414 Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling
 415 is selected.
 416
 417 mprefer-avx128
 418 Target Report Mask(PREFER_AVX128) SAVE
 419 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
 420
 421 ;; ISA support
 422
 423 m32
 424 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
 425 Generate 32bit i386 code
 426
 427 m64
 428 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
 429 Generate 64bit x86-64 code
 430
 431 mx32
 432 Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
 433 Generate 32bit x86-64 code
 434
 435 mmmx
 436 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
 437 Support MMX built-in functions
 438
 439 m3dnow
 440 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
 441 Support 3DNow! built-in functions
 442
 443 m3dnowa
 444 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
 445 Support Athlon 3Dnow! built-in functions
 446
 447 msse
 448 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
 449 Support MMX and SSE built-in functions and code generation
 450
 451 msse2
 452 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
 453 Support MMX, SSE and SSE2 built-in functions and code generation
 454
 455 msse3
 456 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
 457 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
 458
 459 mssse3
 460 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
 461 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
 462
 463 msse4.1
 464 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 465 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
 466
 467 msse4.2
 468 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 469 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
 470
 471 msse4
 472 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 473 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
 474
 475 mno-sse4
 476 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 477 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
 478
 479 msse5
 480 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
 481 ;; Deprecated
 482
 483 mavx
 484 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
 485 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
 486
 487 mavx2
 488 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
 489 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
 490
 491 mfma
 492 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
 493 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
 494
 495 msse4a
 496 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
 497 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
 498
 499 mfma4
 500 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
 501 Support FMA4 built-in functions and code generation
 502
 503 mxop
 504 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
 505 Support XOP built-in functions and code generation
 506
 507 mlwp
 508 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
 509 Support LWP built-in functions and code generation
 510
 511 mabm
 512 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
 513 Support code generation of Advanced Bit Manipulation (ABM) instructions.
 514
 515 mpopcnt
 516 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
 517 Support code generation of popcnt instruction.
 518
 519 mbmi
 520 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
 521 Support BMI built-in functions and code generation
 522
 523 mbmi2
 524 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
 525 Support BMI2 built-in functions and code generation
 526
 527 mlzcnt
 528 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
 529 Support LZCNT built-in function and code generation
 530
 531 mtbm
 532 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
 533 Support TBM built-in functions and code generation
 534
 535 mcx16
 536 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
 537 Support code generation of cmpxchg16b instruction.
 538
 539 msahf
 540 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
 541 Support code generation of sahf instruction in 64bit x86-64 code.
 542
 543 mmovbe
 544 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
 545 Support code generation of movbe instruction.
 546
 547 mcrc32
 548 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
 549 Support code generation of crc32 instruction.
 550
 551 maes
 552 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
 553 Support AES built-in functions and code generation
 554
 555 mpclmul
 556 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
 557 Support PCLMUL built-in functions and code generation
 558
 559 msse2avx
 560 Target Report Var(ix86_sse2avx)
 561 Encode SSE instructions with VEX prefix
 562
 563 mfsgsbase
 564 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
 565 Support FSGSBASE built-in functions and code generation
 566
 567 mrdrnd
 568 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
 569 Support RDRND built-in functions and code generation
 570
 571 mf16c
 572 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
 573 Support F16C built-in functions and code generation
 574
 575 mfentry
 576 Target Report Var(flag_fentry) Init(-1)
 577 Emit profiling counter call at function entry before prologue.
 578
 579 m8bit-idiv
 580 Target Report Mask(USE_8BIT_IDIV) Save
 581 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
 582
 583 mavx256-split-unaligned-load
 584 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
 585 Split 32-byte AVX unaligned load
 586
 587 mavx256-split-unaligned-store
 588 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
 589 Split 32-byte AVX unaligned store
 590
 591 mrtm
 592 Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
 593 Support RTM built-in functions and code generation