1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return true if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return true if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "STACK_REGNO_P (REGNO (op))")))
31 ;; Return true if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return true if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "STACK_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is an SSE register.
47 (define_predicate "sse_reg_operand"
48 (and (match_code "reg")
49 (match_test "SSE_REGNO_P (REGNO (op))")))
51 ;; True if the operand is a Q_REGS class register.
52 (define_predicate "q_regs_operand"
53 (match_operand 0 "register_operand")
55 if (GET_CODE (op) == SUBREG)
57 return ANY_QI_REG_P (op);
60 ;; Match an SI or HImode register for a zero_extract.
61 (define_special_predicate "ext_register_operand"
62 (match_operand 0 "register_operand")
64 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
65 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
67 if (GET_CODE (op) == SUBREG)
70 /* Be careful to accept only registers having upper parts. */
72 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
75 ;; Return true if op is the AX register.
76 (define_predicate "ax_reg_operand"
77 (and (match_code "reg")
78 (match_test "REGNO (op) == AX_REG")))
80 ;; Return true if op is the flags register.
81 (define_predicate "flags_reg_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) == FLAGS_REG")))
85 ;; Return true if op is one of QImode registers: %[abcd][hl].
86 (define_predicate "QIreg_operand"
87 (match_test "QI_REG_P (op)"))
89 ;; Return true if op is a QImode register operand other than
91 (define_predicate "ext_QIreg_operand"
92 (and (match_code "reg")
93 (match_test "TARGET_64BIT")
94 (match_test "REGNO (op) > BX_REG")))
96 ;; Return true if op is not xmm0 register.
97 (define_predicate "reg_not_xmm0_operand"
98 (match_operand 0 "register_operand")
100 if (GET_CODE (op) == SUBREG)
101 op = SUBREG_REG (op);
103 return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
106 ;; As above, but also allow memory operands.
107 (define_predicate "nonimm_not_xmm0_operand"
108 (ior (match_operand 0 "memory_operand")
109 (match_operand 0 "reg_not_xmm0_operand")))
111 ;; Return true if op is not xmm0 register, but only for non-AVX targets.
112 (define_predicate "reg_not_xmm0_operand_maybe_avx"
113 (if_then_else (match_test "TARGET_AVX")
114 (match_operand 0 "register_operand")
115 (match_operand 0 "reg_not_xmm0_operand")))
117 ;; As above, but also allow memory operands.
118 (define_predicate "nonimm_not_xmm0_operand_maybe_avx"
119 (if_then_else (match_test "TARGET_AVX")
120 (match_operand 0 "nonimmediate_operand")
121 (match_operand 0 "nonimm_not_xmm0_operand")))
123 ;; Return true if VALUE can be stored in a sign extended immediate field.
124 (define_predicate "x86_64_immediate_operand"
125 (match_code "const_int,symbol_ref,label_ref,const")
128 return immediate_operand (op, mode);
130 switch (GET_CODE (op))
133 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
134 to be at least 32 and this all acceptable constants are
135 represented as CONST_INT. */
136 if (HOST_BITS_PER_WIDE_INT == 32)
140 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
141 return trunc_int_for_mode (val, SImode) == val;
146 /* For certain code models, the symbolic references are known to fit.
147 in CM_SMALL_PIC model we know it fits if it is local to the shared
148 library. Don't count TLS SYMBOL_REFs here, since they should fit
149 only if inside of UNSPEC handled below. */
150 /* TLS symbols are not constant. */
151 if (SYMBOL_REF_TLS_MODEL (op))
153 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
154 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
157 /* For certain code models, the code is near as well. */
158 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
159 || ix86_cmodel == CM_KERNEL);
162 /* We also may accept the offsetted memory references in certain
164 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
165 switch (XINT (XEXP (op, 0), 1))
167 case UNSPEC_GOTPCREL:
169 case UNSPEC_GOTNTPOFF:
176 if (GET_CODE (XEXP (op, 0)) == PLUS)
178 rtx op1 = XEXP (XEXP (op, 0), 0);
179 rtx op2 = XEXP (XEXP (op, 0), 1);
180 HOST_WIDE_INT offset;
182 if (ix86_cmodel == CM_LARGE)
184 if (!CONST_INT_P (op2))
186 offset = trunc_int_for_mode (INTVAL (op2), DImode);
187 switch (GET_CODE (op1))
190 /* TLS symbols are not constant. */
191 if (SYMBOL_REF_TLS_MODEL (op1))
193 /* For CM_SMALL assume that latest object is 16MB before
194 end of 31bits boundary. We may also accept pretty
195 large negative constants knowing that all objects are
196 in the positive half of address space. */
197 if ((ix86_cmodel == CM_SMALL
198 || (ix86_cmodel == CM_MEDIUM
199 && !SYMBOL_REF_FAR_ADDR_P (op1)))
200 && offset < 16*1024*1024
201 && trunc_int_for_mode (offset, SImode) == offset)
203 /* For CM_KERNEL we know that all object resist in the
204 negative half of 32bits address space. We may not
205 accept negative offsets, since they may be just off
206 and we may accept pretty large positive ones. */
207 if (ix86_cmodel == CM_KERNEL
209 && trunc_int_for_mode (offset, SImode) == offset)
214 /* These conditions are similar to SYMBOL_REF ones, just the
215 constraints for code models differ. */
216 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
217 && offset < 16*1024*1024
218 && trunc_int_for_mode (offset, SImode) == offset)
220 if (ix86_cmodel == CM_KERNEL
222 && trunc_int_for_mode (offset, SImode) == offset)
227 switch (XINT (op1, 1))
232 && trunc_int_for_mode (offset, SImode) == offset)
250 ;; Return true if VALUE can be stored in the zero extended immediate field.
251 (define_predicate "x86_64_zext_immediate_operand"
252 (match_code "const_double,const_int,symbol_ref,label_ref,const")
254 switch (GET_CODE (op))
257 if (HOST_BITS_PER_WIDE_INT == 32)
258 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
263 if (HOST_BITS_PER_WIDE_INT == 32)
264 return INTVAL (op) >= 0;
266 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
269 /* For certain code models, the symbolic references are known to fit. */
270 /* TLS symbols are not constant. */
271 if (SYMBOL_REF_TLS_MODEL (op))
273 return (ix86_cmodel == CM_SMALL
274 || (ix86_cmodel == CM_MEDIUM
275 && !SYMBOL_REF_FAR_ADDR_P (op)));
278 /* For certain code models, the code is near as well. */
279 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
282 /* We also may accept the offsetted memory references in certain
284 if (GET_CODE (XEXP (op, 0)) == PLUS)
286 rtx op1 = XEXP (XEXP (op, 0), 0);
287 rtx op2 = XEXP (XEXP (op, 0), 1);
289 if (ix86_cmodel == CM_LARGE)
291 switch (GET_CODE (op1))
294 /* TLS symbols are not constant. */
295 if (SYMBOL_REF_TLS_MODEL (op1))
297 /* For small code model we may accept pretty large positive
298 offsets, since one bit is available for free. Negative
299 offsets are limited by the size of NULL pointer area
300 specified by the ABI. */
301 if ((ix86_cmodel == CM_SMALL
302 || (ix86_cmodel == CM_MEDIUM
303 && !SYMBOL_REF_FAR_ADDR_P (op1)))
305 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
306 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
308 /* ??? For the kernel, we may accept adjustment of
309 -0x10000000, since we know that it will just convert
310 negative address space to positive, but perhaps this
311 is not worthwhile. */
315 /* These conditions are similar to SYMBOL_REF ones, just the
316 constraints for code models differ. */
317 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
319 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
320 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
336 ;; Return true if OP is general operand representable on x86_64.
337 (define_predicate "x86_64_general_operand"
338 (if_then_else (match_test "TARGET_64BIT")
339 (ior (match_operand 0 "nonimmediate_operand")
340 (match_operand 0 "x86_64_immediate_operand"))
341 (match_operand 0 "general_operand")))
343 ;; Return true if OP is general operand representable on x86_64
344 ;; as zero extended constant. This predicate is used in zero-extending
345 ;; conversion operations that require non-VOIDmode immediate operands.
346 (define_predicate "x86_64_zext_general_operand"
347 (if_then_else (match_test "TARGET_64BIT")
348 (ior (match_operand 0 "nonimmediate_operand")
349 (and (match_operand 0 "x86_64_zext_immediate_operand")
350 (match_test "GET_MODE (op) != VOIDmode")))
351 (match_operand 0 "general_operand")))
353 ;; Return true if OP is general operand representable on x86_64
354 ;; as either sign extended or zero extended constant.
355 (define_predicate "x86_64_szext_general_operand"
356 (if_then_else (match_test "TARGET_64BIT")
357 (ior (match_operand 0 "nonimmediate_operand")
358 (match_operand 0 "x86_64_immediate_operand")
359 (match_operand 0 "x86_64_zext_immediate_operand"))
360 (match_operand 0 "general_operand")))
362 ;; Return true if OP is nonmemory operand representable on x86_64.
363 (define_predicate "x86_64_nonmemory_operand"
364 (if_then_else (match_test "TARGET_64BIT")
365 (ior (match_operand 0 "register_operand")
366 (match_operand 0 "x86_64_immediate_operand"))
367 (match_operand 0 "nonmemory_operand")))
369 ;; Return true if OP is nonmemory operand representable on x86_64.
370 (define_predicate "x86_64_szext_nonmemory_operand"
371 (if_then_else (match_test "TARGET_64BIT")
372 (ior (match_operand 0 "register_operand")
373 (match_operand 0 "x86_64_immediate_operand")
374 (match_operand 0 "x86_64_zext_immediate_operand"))
375 (match_operand 0 "nonmemory_operand")))
377 ;; Return true when operand is PIC expression that can be computed by lea
379 (define_predicate "pic_32bit_operand"
380 (match_code "const,symbol_ref,label_ref")
385 /* Rule out relocations that translate into 64bit constants. */
386 if (TARGET_64BIT && GET_CODE (op) == CONST)
389 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
391 if (GET_CODE (op) == UNSPEC
392 && (XINT (op, 1) == UNSPEC_GOTOFF
393 || XINT (op, 1) == UNSPEC_GOT))
397 return symbolic_operand (op, mode);
400 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
401 (define_predicate "x86_64_movabs_operand"
402 (and (match_operand 0 "nonmemory_operand")
403 (not (match_operand 0 "pic_32bit_operand"))))
405 ;; Return true if OP is either a symbol reference or a sum of a symbol
406 ;; reference and a constant.
407 (define_predicate "symbolic_operand"
408 (match_code "symbol_ref,label_ref,const")
410 switch (GET_CODE (op))
418 if (GET_CODE (op) == SYMBOL_REF
419 || GET_CODE (op) == LABEL_REF
420 || (GET_CODE (op) == UNSPEC
421 && (XINT (op, 1) == UNSPEC_GOT
422 || XINT (op, 1) == UNSPEC_GOTOFF
423 || XINT (op, 1) == UNSPEC_PCREL
424 || XINT (op, 1) == UNSPEC_GOTPCREL)))
426 if (GET_CODE (op) != PLUS
427 || !CONST_INT_P (XEXP (op, 1)))
431 if (GET_CODE (op) == SYMBOL_REF
432 || GET_CODE (op) == LABEL_REF)
434 /* Only @GOTOFF gets offsets. */
435 if (GET_CODE (op) != UNSPEC
436 || XINT (op, 1) != UNSPEC_GOTOFF)
439 op = XVECEXP (op, 0, 0);
440 if (GET_CODE (op) == SYMBOL_REF
441 || GET_CODE (op) == LABEL_REF)
450 ;; Return true if OP is a symbolic operand that resolves locally.
451 (define_predicate "local_symbolic_operand"
452 (match_code "const,label_ref,symbol_ref")
454 if (GET_CODE (op) == CONST
455 && GET_CODE (XEXP (op, 0)) == PLUS
456 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
457 op = XEXP (XEXP (op, 0), 0);
459 if (GET_CODE (op) == LABEL_REF)
462 if (GET_CODE (op) != SYMBOL_REF)
465 if (SYMBOL_REF_TLS_MODEL (op))
468 if (SYMBOL_REF_LOCAL_P (op))
471 /* There is, however, a not insubstantial body of code in the rest of
472 the compiler that assumes it can just stick the results of
473 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
474 /* ??? This is a hack. Should update the body of the compiler to
475 always create a DECL an invoke targetm.encode_section_info. */
476 if (strncmp (XSTR (op, 0), internal_label_prefix,
477 internal_label_prefix_len) == 0)
483 ;; Test for a legitimate @GOTOFF operand.
485 ;; VxWorks does not impose a fixed gap between segments; the run-time
486 ;; gap can be different from the object-file gap. We therefore can't
487 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
488 ;; same segment as the GOT. Unfortunately, the flexibility of linker
489 ;; scripts means that we can't be sure of that in general, so assume
490 ;; that @GOTOFF is never valid on VxWorks.
491 (define_predicate "gotoff_operand"
492 (and (not (match_test "TARGET_VXWORKS_RTP"))
493 (match_operand 0 "local_symbolic_operand")))
495 ;; Test for various thread-local symbols.
496 (define_special_predicate "tls_symbolic_operand"
497 (and (match_code "symbol_ref")
498 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
500 (define_special_predicate "tls_modbase_operand"
501 (and (match_code "symbol_ref")
502 (match_test "op == ix86_tls_module_base ()")))
504 ;; Test for a pc-relative call operand
505 (define_predicate "constant_call_address_operand"
506 (match_code "symbol_ref")
508 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
510 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
515 ;; P6 processors will jump to the address after the decrement when %esp
516 ;; is used as a call operand, so they will execute return address as a code.
517 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
519 (define_predicate "call_register_no_elim_operand"
520 (match_operand 0 "register_operand")
522 if (GET_CODE (op) == SUBREG)
523 op = SUBREG_REG (op);
525 if (!TARGET_64BIT && op == stack_pointer_rtx)
528 return register_no_elim_operand (op, mode);
531 ;; True for any non-virtual or eliminable register. Used in places where
532 ;; instantiation of such a register may cause the pattern to not be recognized.
533 (define_predicate "register_no_elim_operand"
534 (match_operand 0 "register_operand")
536 if (GET_CODE (op) == SUBREG)
537 op = SUBREG_REG (op);
538 return !(op == arg_pointer_rtx
539 || op == frame_pointer_rtx
540 || IN_RANGE (REGNO (op),
541 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
544 ;; Similarly, but include the stack pointer. This is used to prevent esp
545 ;; from being used as an index reg.
546 (define_predicate "index_register_operand"
547 (match_operand 0 "register_operand")
549 if (GET_CODE (op) == SUBREG)
550 op = SUBREG_REG (op);
551 if (reload_in_progress || reload_completed)
552 return REG_OK_FOR_INDEX_STRICT_P (op);
554 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
557 ;; Return false if this is any eliminable register. Otherwise general_operand.
558 (define_predicate "general_no_elim_operand"
559 (if_then_else (match_code "reg,subreg")
560 (match_operand 0 "register_no_elim_operand")
561 (match_operand 0 "general_operand")))
563 ;; Return false if this is any eliminable register. Otherwise
564 ;; register_operand or a constant.
565 (define_predicate "nonmemory_no_elim_operand"
566 (ior (match_operand 0 "register_no_elim_operand")
567 (match_operand 0 "immediate_operand")))
569 ;; Test for a valid operand for indirect branch.
570 (define_predicate "indirect_branch_operand"
571 (ior (match_operand 0 "register_operand")
572 (and (not (match_test "TARGET_X32"))
573 (match_operand 0 "memory_operand"))))
575 ;; Test for a valid operand for a call instruction.
576 ;; Allow constant call address operands in Pmode only.
577 (define_special_predicate "call_insn_operand"
578 (ior (match_test "constant_call_address_operand
579 (op, mode == VOIDmode ? mode : Pmode)")
580 (match_operand 0 "call_register_no_elim_operand")
581 (and (not (match_test "TARGET_X32"))
582 (match_operand 0 "memory_operand"))))
584 ;; Similarly, but for tail calls, in which we cannot allow memory references.
585 (define_special_predicate "sibcall_insn_operand"
586 (ior (match_test "constant_call_address_operand
587 (op, mode == VOIDmode ? mode : Pmode)")
588 (match_operand 0 "register_no_elim_operand")))
590 ;; Match exactly zero.
591 (define_predicate "const0_operand"
592 (match_code "const_int,const_double,const_vector")
594 if (mode == VOIDmode)
595 mode = GET_MODE (op);
596 return op == CONST0_RTX (mode);
599 ;; Match exactly one.
600 (define_predicate "const1_operand"
601 (and (match_code "const_int")
602 (match_test "op == const1_rtx")))
604 ;; Match exactly eight.
605 (define_predicate "const8_operand"
606 (and (match_code "const_int")
607 (match_test "INTVAL (op) == 8")))
609 ;; Match exactly 128.
610 (define_predicate "const128_operand"
611 (and (match_code "const_int")
612 (match_test "INTVAL (op) == 128")))
614 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
615 (define_predicate "const_32bit_mask"
616 (and (match_code "const_int")
617 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
618 == (HOST_WIDE_INT) 0xffffffff")))
620 ;; Match 2, 4, or 8. Used for leal multiplicands.
621 (define_predicate "const248_operand"
622 (match_code "const_int")
624 HOST_WIDE_INT i = INTVAL (op);
625 return i == 2 || i == 4 || i == 8;
628 ;; Match 1, 2, 4, or 8
629 (define_predicate "const1248_operand"
630 (match_code "const_int")
632 HOST_WIDE_INT i = INTVAL (op);
633 return i == 1 || i == 2 || i == 4 || i == 8;
636 ;; Match 3, 5, or 9. Used for leal multiplicands.
637 (define_predicate "const359_operand"
638 (match_code "const_int")
640 HOST_WIDE_INT i = INTVAL (op);
641 return i == 3 || i == 5 || i == 9;
645 (define_predicate "const_0_to_1_operand"
646 (and (match_code "const_int")
647 (ior (match_test "op == const0_rtx")
648 (match_test "op == const1_rtx"))))
651 (define_predicate "const_0_to_3_operand"
652 (and (match_code "const_int")
653 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
656 (define_predicate "const_0_to_7_operand"
657 (and (match_code "const_int")
658 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
661 (define_predicate "const_0_to_15_operand"
662 (and (match_code "const_int")
663 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
666 (define_predicate "const_0_to_31_operand"
667 (and (match_code "const_int")
668 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
671 (define_predicate "const_0_to_63_operand"
672 (and (match_code "const_int")
673 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
676 (define_predicate "const_0_to_255_operand"
677 (and (match_code "const_int")
678 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
680 ;; Match (0 to 255) * 8
681 (define_predicate "const_0_to_255_mul_8_operand"
682 (match_code "const_int")
684 unsigned HOST_WIDE_INT val = INTVAL (op);
685 return val <= 255*8 && val % 8 == 0;
688 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
689 ;; for shift & compare patterns, as shifting by 0 does not change flags).
690 (define_predicate "const_1_to_31_operand"
691 (and (match_code "const_int")
692 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
694 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
695 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
696 (define_predicate "const_1_to_63_operand"
697 (and (match_code "const_int")
698 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
701 (define_predicate "const_2_to_3_operand"
702 (and (match_code "const_int")
703 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
706 (define_predicate "const_4_to_5_operand"
707 (and (match_code "const_int")
708 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
711 (define_predicate "const_4_to_7_operand"
712 (and (match_code "const_int")
713 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
716 (define_predicate "const_6_to_7_operand"
717 (and (match_code "const_int")
718 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
721 (define_predicate "const_8_to_11_operand"
722 (and (match_code "const_int")
723 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
726 (define_predicate "const_12_to_15_operand"
727 (and (match_code "const_int")
728 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
730 ;; True if this is a constant appropriate for an increment or decrement.
731 (define_predicate "incdec_operand"
732 (match_code "const_int")
734 /* On Pentium4, the inc and dec operations causes extra dependency on flag
735 registers, since carry flag is not set. */
736 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
738 return op == const1_rtx || op == constm1_rtx;
741 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
742 (define_predicate "reg_or_pm1_operand"
743 (ior (match_operand 0 "register_operand")
744 (and (match_code "const_int")
745 (ior (match_test "op == const1_rtx")
746 (match_test "op == constm1_rtx")))))
748 ;; True if OP is acceptable as operand of DImode shift expander.
749 (define_predicate "shiftdi_operand"
750 (if_then_else (match_test "TARGET_64BIT")
751 (match_operand 0 "nonimmediate_operand")
752 (match_operand 0 "register_operand")))
754 (define_predicate "ashldi_input_operand"
755 (if_then_else (match_test "TARGET_64BIT")
756 (match_operand 0 "nonimmediate_operand")
757 (match_operand 0 "reg_or_pm1_operand")))
759 ;; Return true if OP is a vector load from the constant pool with just
760 ;; the first element nonzero.
761 (define_predicate "zero_extended_scalar_load_operand"
765 op = maybe_get_pool_constant (op);
767 if (!(op && GET_CODE (op) == CONST_VECTOR))
770 n_elts = CONST_VECTOR_NUNITS (op);
772 for (n_elts--; n_elts > 0; n_elts--)
774 rtx elt = CONST_VECTOR_ELT (op, n_elts);
775 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
781 /* Return true if operand is a vector constant that is all ones. */
782 (define_predicate "vector_all_ones_operand"
783 (match_code "const_vector")
785 int nunits = GET_MODE_NUNITS (mode);
787 if (GET_CODE (op) == CONST_VECTOR
788 && CONST_VECTOR_NUNITS (op) == nunits)
791 for (i = 0; i < nunits; ++i)
793 rtx x = CONST_VECTOR_ELT (op, i);
794 if (x != constm1_rtx)
803 ; Return true when OP is operand acceptable for standard SSE move.
804 (define_predicate "vector_move_operand"
805 (ior (match_operand 0 "nonimmediate_operand")
806 (match_operand 0 "const0_operand")))
808 ;; Return true when OP is nonimmediate or standard SSE constant.
809 (define_predicate "nonimmediate_or_sse_const_operand"
810 (match_operand 0 "general_operand")
812 if (nonimmediate_operand (op, mode))
814 if (standard_sse_constant_p (op) > 0)
819 ;; Return true if OP is a register or a zero.
820 (define_predicate "reg_or_0_operand"
821 (ior (match_operand 0 "register_operand")
822 (match_operand 0 "const0_operand")))
824 ;; Return true if op if a valid address for LEA, and does not contain
825 ;; a segment override. Defined as a special predicate to allow
826 ;; mode-less const_int operands pass to address_operand.
827 (define_special_predicate "lea_address_operand"
828 (match_operand 0 "address_operand")
830 struct ix86_address parts;
833 ok = ix86_decompose_address (op, &parts);
835 return parts.seg == SEG_DEFAULT;
838 ;; Return true if op if a valid base register, displacement or
839 ;; sum of base register and displacement for VSIB addressing.
840 (define_predicate "vsib_address_operand"
841 (match_operand 0 "address_operand")
843 struct ix86_address parts;
847 ok = ix86_decompose_address (op, &parts);
849 if (parts.index || parts.seg != SEG_DEFAULT)
852 /* VSIB addressing doesn't support (%rip). */
853 if (parts.disp && GET_CODE (parts.disp) == CONST)
855 disp = XEXP (parts.disp, 0);
856 if (GET_CODE (disp) == PLUS)
857 disp = XEXP (disp, 0);
858 if (GET_CODE (disp) == UNSPEC)
859 switch (XINT (disp, 1))
861 case UNSPEC_GOTPCREL:
863 case UNSPEC_GOTNTPOFF:
871 (define_predicate "vsib_mem_operator"
874 ;; Return true if the rtx is known to be at least 32 bits aligned.
875 (define_predicate "aligned_operand"
876 (match_operand 0 "general_operand")
878 struct ix86_address parts;
881 /* Registers and immediate operands are always "aligned". */
885 /* All patterns using aligned_operand on memory operands ends up
886 in promoting memory operand to 64bit and thus causing memory mismatch. */
887 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
890 /* Don't even try to do any aligned optimizations with volatiles. */
891 if (MEM_VOLATILE_P (op))
894 if (MEM_ALIGN (op) >= 32)
899 /* Pushes and pops are only valid on the stack pointer. */
900 if (GET_CODE (op) == PRE_DEC
901 || GET_CODE (op) == POST_INC)
904 /* Decode the address. */
905 ok = ix86_decompose_address (op, &parts);
908 if (parts.base && GET_CODE (parts.base) == SUBREG)
909 parts.base = SUBREG_REG (parts.base);
910 if (parts.index && GET_CODE (parts.index) == SUBREG)
911 parts.index = SUBREG_REG (parts.index);
913 /* Look for some component that isn't known to be aligned. */
916 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
921 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
926 if (!CONST_INT_P (parts.disp)
927 || (INTVAL (parts.disp) & 3))
931 /* Didn't find one -- this must be an aligned address. */
935 ;; Return true if OP is memory operand with a displacement.
936 (define_predicate "memory_displacement_operand"
937 (match_operand 0 "memory_operand")
939 struct ix86_address parts;
942 ok = ix86_decompose_address (XEXP (op, 0), &parts);
944 return parts.disp != NULL_RTX;
947 ;; Return true if OP is memory operand with a displacement only.
948 (define_predicate "memory_displacement_only_operand"
949 (match_operand 0 "memory_operand")
951 struct ix86_address parts;
957 ok = ix86_decompose_address (XEXP (op, 0), &parts);
960 if (parts.base || parts.index)
963 return parts.disp != NULL_RTX;
966 ;; Return true if OP is memory operand which will need zero or
967 ;; one register at most, not counting stack pointer or frame pointer.
968 (define_predicate "cmpxchg8b_pic_memory_operand"
969 (match_operand 0 "memory_operand")
971 struct ix86_address parts;
974 ok = ix86_decompose_address (XEXP (op, 0), &parts);
977 if (parts.base && GET_CODE (parts.base) == SUBREG)
978 parts.base = SUBREG_REG (parts.base);
979 if (parts.index && GET_CODE (parts.index) == SUBREG)
980 parts.index = SUBREG_REG (parts.index);
982 if (parts.base == NULL_RTX
983 || parts.base == arg_pointer_rtx
984 || parts.base == frame_pointer_rtx
985 || parts.base == hard_frame_pointer_rtx
986 || parts.base == stack_pointer_rtx)
989 if (parts.index == NULL_RTX
990 || parts.index == arg_pointer_rtx
991 || parts.index == frame_pointer_rtx
992 || parts.index == hard_frame_pointer_rtx
993 || parts.index == stack_pointer_rtx)
1000 ;; Return true if OP is memory operand that cannot be represented
1001 ;; by the modRM array.
1002 (define_predicate "long_memory_operand"
1003 (and (match_operand 0 "memory_operand")
1004 (match_test "memory_address_length (op)")))
1006 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1007 (define_predicate "fcmov_comparison_operator"
1008 (match_operand 0 "comparison_operator")
1010 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1011 enum rtx_code code = GET_CODE (op);
1013 if (inmode == CCFPmode || inmode == CCFPUmode)
1015 if (!ix86_trivial_fp_comparison_operator (op, mode))
1017 code = ix86_fp_compare_code_to_integer (code);
1019 /* i387 supports just limited amount of conditional codes. */
1022 case LTU: case GTU: case LEU: case GEU:
1023 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1024 || inmode == CCCmode)
1027 case ORDERED: case UNORDERED:
1035 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1036 ;; The first set are supported directly; the second set can't be done with
1037 ;; full IEEE support, i.e. NaNs.
1039 (define_predicate "sse_comparison_operator"
1040 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1041 (and (match_test "TARGET_AVX")
1042 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1044 (define_predicate "ix86_comparison_int_operator"
1045 (match_code "ne,eq,ge,gt,le,lt"))
1047 (define_predicate "ix86_comparison_uns_operator"
1048 (match_code "ne,eq,geu,gtu,leu,ltu"))
1050 (define_predicate "bt_comparison_operator"
1051 (match_code "ne,eq"))
1053 ;; Return true if OP is a valid comparison operator in valid mode.
1054 (define_predicate "ix86_comparison_operator"
1055 (match_operand 0 "comparison_operator")
1057 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1058 enum rtx_code code = GET_CODE (op);
1060 if (inmode == CCFPmode || inmode == CCFPUmode)
1061 return ix86_trivial_fp_comparison_operator (op, mode);
1068 if (inmode == CCmode || inmode == CCGCmode
1069 || inmode == CCGOCmode || inmode == CCNOmode)
1072 case LTU: case GTU: case LEU: case GEU:
1073 if (inmode == CCmode || inmode == CCCmode)
1076 case ORDERED: case UNORDERED:
1077 if (inmode == CCmode)
1081 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1089 ;; Return true if OP is a valid comparison operator
1090 ;; testing carry flag to be set.
1091 (define_predicate "ix86_carry_flag_operator"
1092 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1094 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1095 enum rtx_code code = GET_CODE (op);
1097 if (inmode == CCFPmode || inmode == CCFPUmode)
1099 if (!ix86_trivial_fp_comparison_operator (op, mode))
1101 code = ix86_fp_compare_code_to_integer (code);
1103 else if (inmode == CCCmode)
1104 return code == LTU || code == GTU;
1105 else if (inmode != CCmode)
1111 ;; Return true if this comparison only requires testing one flag bit.
1112 (define_predicate "ix86_trivial_fp_comparison_operator"
1113 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1115 ;; Return true if we know how to do this comparison. Others require
1116 ;; testing more than one flag bit, and we let the generic middle-end
1118 (define_predicate "ix86_fp_comparison_operator"
1119 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1120 == IX86_FPCMP_ARITH")
1121 (match_operand 0 "comparison_operator")
1122 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1124 ;; Same as above, but for swapped comparison used in fp_jcc_4_387.
1125 (define_predicate "ix86_swapped_fp_comparison_operator"
1126 (match_operand 0 "comparison_operator")
1128 enum rtx_code code = GET_CODE (op);
1131 PUT_CODE (op, swap_condition (code));
1132 ret = ix86_fp_comparison_operator (op, mode);
1133 PUT_CODE (op, code);
1137 ;; Nearly general operand, but accept any const_double, since we wish
1138 ;; to be able to drop them into memory rather than have them get pulled
1140 (define_predicate "cmp_fp_expander_operand"
1141 (ior (match_code "const_double")
1142 (match_operand 0 "general_operand")))
1144 ;; Return true if this is a valid binary floating-point operation.
1145 (define_predicate "binary_fp_operator"
1146 (match_code "plus,minus,mult,div"))
1148 ;; Return true if this is a multiply operation.
1149 (define_predicate "mult_operator"
1150 (match_code "mult"))
1152 ;; Return true if this is a division operation.
1153 (define_predicate "div_operator"
1156 ;; Return true if this is a plus, minus, and, ior or xor operation.
1157 (define_predicate "plusminuslogic_operator"
1158 (match_code "plus,minus,and,ior,xor"))
1160 ;; Return true if this is a float extend operation.
1161 (define_predicate "float_operator"
1162 (match_code "float"))
1164 ;; Return true for ARITHMETIC_P.
1165 (define_predicate "arith_or_logical_operator"
1166 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1167 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1169 ;; Return true for COMMUTATIVE_P.
1170 (define_predicate "commutative_operator"
1171 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1173 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1174 (define_predicate "promotable_binary_operator"
1175 (ior (match_code "plus,minus,and,ior,xor,ashift")
1176 (and (match_code "mult")
1177 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1179 (define_predicate "compare_operator"
1180 (match_code "compare"))
1182 (define_predicate "absneg_operator"
1183 (match_code "abs,neg"))
1185 ;; Return true if OP is misaligned memory operand
1186 (define_predicate "misaligned_operand"
1187 (and (match_code "mem")
1188 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1190 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1191 (define_predicate "emms_operation"
1192 (match_code "parallel")
1196 if (XVECLEN (op, 0) != 17)
1199 for (i = 0; i < 8; i++)
1201 rtx elt = XVECEXP (op, 0, i+1);
1203 if (GET_CODE (elt) != CLOBBER
1204 || GET_CODE (SET_DEST (elt)) != REG
1205 || GET_MODE (SET_DEST (elt)) != XFmode
1206 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1209 elt = XVECEXP (op, 0, i+9);
1211 if (GET_CODE (elt) != CLOBBER
1212 || GET_CODE (SET_DEST (elt)) != REG
1213 || GET_MODE (SET_DEST (elt)) != DImode
1214 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1220 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1221 (define_predicate "vzeroall_operation"
1222 (match_code "parallel")
1224 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1226 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1229 for (i = 0; i < nregs; i++)
1231 rtx elt = XVECEXP (op, 0, i+1);
1233 if (GET_CODE (elt) != SET
1234 || GET_CODE (SET_DEST (elt)) != REG
1235 || GET_MODE (SET_DEST (elt)) != V8SImode
1236 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1237 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1243 ;; Return true if OP is a parallel for a vbroadcast permute.
1245 (define_predicate "avx_vbroadcast_operand"
1246 (and (match_code "parallel")
1247 (match_code "const_int" "a"))
1249 rtx elt = XVECEXP (op, 0, 0);
1250 int i, nelt = XVECLEN (op, 0);
1252 /* Don't bother checking there are the right number of operands,
1253 merely that they're all identical. */
1254 for (i = 1; i < nelt; ++i)
1255 if (XVECEXP (op, 0, i) != elt)
1260 ;; Return true if OP is a proper third operand to vpblendw256.
1261 (define_predicate "avx2_pblendw_operand"
1262 (match_code "const_int")
1264 HOST_WIDE_INT val = INTVAL (op);
1265 HOST_WIDE_INT low = val & 0xff;
1266 return val == ((low << 8) | low);