4271f03ab38d1fce1e4a9f048fa5f36bbe2dfa67
1 /* Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
3 This file is part of GCC.
5 GCC is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GCC is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with GCC; see the file COPYING. If not, write to
17 the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
20 /* As a special exception, if you include this header file into source
21 files compiled by GCC, this header file does not by itself cause
22 the resulting executable to be covered by the GNU General Public
23 License. This exception does not however invalidate any other
24 reasons why the executable file might be covered by the GNU General
27 /* Implemented from the specification included in the Intel C++ Compiler
28 User Guide and Reference, version 8.0. */
30 #ifndef _XMMINTRIN_H_INCLUDED
31 #define _XMMINTRIN_H_INCLUDED
34 # error "SSE instruction set not enabled"
37 /* We need type definitions from the MMX header file. */
40 /* The data type intended for user use. */
41 typedef float __m128
__attribute__ ((vector_size (16)));
43 /* Internal data types for implementing the intrinsics. */
44 typedef float __v4sf
__attribute__ ((vector_size (16)));
46 /* Create a selector for use with the SHUFPS instruction. */
47 #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \
48 (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | (fp0))
50 /* Constants for use with _mm_prefetch. */
59 /* Bits in the MXCSR. */
60 #define _MM_EXCEPT_MASK 0x003f
61 #define _MM_EXCEPT_INVALID 0x0001
62 #define _MM_EXCEPT_DENORM 0x0002
63 #define _MM_EXCEPT_DIV_ZERO 0x0004
64 #define _MM_EXCEPT_OVERFLOW 0x0008
65 #define _MM_EXCEPT_UNDERFLOW 0x0010
66 #define _MM_EXCEPT_INEXACT 0x0020
68 #define _MM_MASK_MASK 0x1f80
69 #define _MM_MASK_INVALID 0x0080
70 #define _MM_MASK_DENORM 0x0100
71 #define _MM_MASK_DIV_ZERO 0x0200
72 #define _MM_MASK_OVERFLOW 0x0400
73 #define _MM_MASK_UNDERFLOW 0x0800
74 #define _MM_MASK_INEXACT 0x1000
76 #define _MM_ROUND_MASK 0x6000
77 #define _MM_ROUND_NEAREST 0x0000
78 #define _MM_ROUND_DOWN 0x2000
79 #define _MM_ROUND_UP 0x4000
80 #define _MM_ROUND_TOWARD_ZERO 0x6000
82 #define _MM_FLUSH_ZERO_MASK 0x8000
83 #define _MM_FLUSH_ZERO_ON 0x8000
84 #define _MM_FLUSH_ZERO_OFF 0x0000
86 /* Perform the respective operation on the lower SPFP (single-precision
87 floating-point) values of A and B; the upper three SPFP values are
88 passed through from A. */
90 static __inline __m128
91 _mm_add_ss (__m128 __A
, __m128 __B
)
93 return (__m128
) __builtin_ia32_addss ((__v4sf
)__A
, (__v4sf
)__B
);
96 static __inline __m128
97 _mm_sub_ss (__m128 __A
, __m128 __B
)
99 return (__m128
) __builtin_ia32_subss ((__v4sf
)__A
, (__v4sf
)__B
);
102 static __inline __m128
103 _mm_mul_ss (__m128 __A
, __m128 __B
)
105 return (__m128
) __builtin_ia32_mulss ((__v4sf
)__A
, (__v4sf
)__B
);
108 static __inline __m128
109 _mm_div_ss (__m128 __A
, __m128 __B
)
111 return (__m128
) __builtin_ia32_divss ((__v4sf
)__A
, (__v4sf
)__B
);
114 static __inline __m128
115 _mm_sqrt_ss (__m128 __A
)
117 return (__m128
) __builtin_ia32_sqrtss ((__v4sf
)__A
);
120 static __inline __m128
121 _mm_rcp_ss (__m128 __A
)
123 return (__m128
) __builtin_ia32_rcpss ((__v4sf
)__A
);
126 static __inline __m128
127 _mm_rsqrt_ss (__m128 __A
)
129 return (__m128
) __builtin_ia32_rsqrtss ((__v4sf
)__A
);
132 static __inline __m128
133 _mm_min_ss (__m128 __A
, __m128 __B
)
135 return (__m128
) __builtin_ia32_minss ((__v4sf
)__A
, (__v4sf
)__B
);
138 static __inline __m128
139 _mm_max_ss (__m128 __A
, __m128 __B
)
141 return (__m128
) __builtin_ia32_maxss ((__v4sf
)__A
, (__v4sf
)__B
);
144 /* Perform the respective operation on the four SPFP values in A and B. */
146 static __inline __m128
147 _mm_add_ps (__m128 __A
, __m128 __B
)
149 return (__m128
) __builtin_ia32_addps ((__v4sf
)__A
, (__v4sf
)__B
);
152 static __inline __m128
153 _mm_sub_ps (__m128 __A
, __m128 __B
)
155 return (__m128
) __builtin_ia32_subps ((__v4sf
)__A
, (__v4sf
)__B
);
158 static __inline __m128
159 _mm_mul_ps (__m128 __A
, __m128 __B
)
161 return (__m128
) __builtin_ia32_mulps ((__v4sf
)__A
, (__v4sf
)__B
);
164 static __inline __m128
165 _mm_div_ps (__m128 __A
, __m128 __B
)
167 return (__m128
) __builtin_ia32_divps ((__v4sf
)__A
, (__v4sf
)__B
);
170 static __inline __m128
171 _mm_sqrt_ps (__m128 __A
)
173 return (__m128
) __builtin_ia32_sqrtps ((__v4sf
)__A
);
176 static __inline __m128
177 _mm_rcp_ps (__m128 __A
)
179 return (__m128
) __builtin_ia32_rcpps ((__v4sf
)__A
);
182 static __inline __m128
183 _mm_rsqrt_ps (__m128 __A
)
185 return (__m128
) __builtin_ia32_rsqrtps ((__v4sf
)__A
);
188 static __inline __m128
189 _mm_min_ps (__m128 __A
, __m128 __B
)
191 return (__m128
) __builtin_ia32_minps ((__v4sf
)__A
, (__v4sf
)__B
);
194 static __inline __m128
195 _mm_max_ps (__m128 __A
, __m128 __B
)
197 return (__m128
) __builtin_ia32_maxps ((__v4sf
)__A
, (__v4sf
)__B
);
200 /* Perform logical bit-wise operations on 128-bit values. */
202 static __inline __m128
203 _mm_and_ps (__m128 __A
, __m128 __B
)
205 return __builtin_ia32_andps (__A
, __B
);
208 static __inline __m128
209 _mm_andnot_ps (__m128 __A
, __m128 __B
)
211 return __builtin_ia32_andnps (__A
, __B
);
214 static __inline __m128
215 _mm_or_ps (__m128 __A
, __m128 __B
)
217 return __builtin_ia32_orps (__A
, __B
);
220 static __inline __m128
221 _mm_xor_ps (__m128 __A
, __m128 __B
)
223 return __builtin_ia32_xorps (__A
, __B
);
226 /* Perform a comparison on the lower SPFP values of A and B. If the
227 comparison is true, place a mask of all ones in the result, otherwise a
228 mask of zeros. The upper three SPFP values are passed through from A. */
230 static __inline __m128
231 _mm_cmpeq_ss (__m128 __A
, __m128 __B
)
233 return (__m128
) __builtin_ia32_cmpeqss ((__v4sf
)__A
, (__v4sf
)__B
);
236 static __inline __m128
237 _mm_cmplt_ss (__m128 __A
, __m128 __B
)
239 return (__m128
) __builtin_ia32_cmpltss ((__v4sf
)__A
, (__v4sf
)__B
);
242 static __inline __m128
243 _mm_cmple_ss (__m128 __A
, __m128 __B
)
245 return (__m128
) __builtin_ia32_cmpless ((__v4sf
)__A
, (__v4sf
)__B
);
248 static __inline __m128
249 _mm_cmpgt_ss (__m128 __A
, __m128 __B
)
251 return (__m128
) __builtin_ia32_movss ((__v4sf
) __A
,
253 __builtin_ia32_cmpltss ((__v4sf
) __B
,
258 static __inline __m128
259 _mm_cmpge_ss (__m128 __A
, __m128 __B
)
261 return (__m128
) __builtin_ia32_movss ((__v4sf
) __A
,
263 __builtin_ia32_cmpless ((__v4sf
) __B
,
268 static __inline __m128
269 _mm_cmpneq_ss (__m128 __A
, __m128 __B
)
271 return (__m128
) __builtin_ia32_cmpneqss ((__v4sf
)__A
, (__v4sf
)__B
);
274 static __inline __m128
275 _mm_cmpnlt_ss (__m128 __A
, __m128 __B
)
277 return (__m128
) __builtin_ia32_cmpnltss ((__v4sf
)__A
, (__v4sf
)__B
);
280 static __inline __m128
281 _mm_cmpnle_ss (__m128 __A
, __m128 __B
)
283 return (__m128
) __builtin_ia32_cmpnless ((__v4sf
)__A
, (__v4sf
)__B
);
286 static __inline __m128
287 _mm_cmpngt_ss (__m128 __A
, __m128 __B
)
289 return (__m128
) __builtin_ia32_movss ((__v4sf
) __A
,
291 __builtin_ia32_cmpnltss ((__v4sf
) __B
,
296 static __inline __m128
297 _mm_cmpnge_ss (__m128 __A
, __m128 __B
)
299 return (__m128
) __builtin_ia32_movss ((__v4sf
) __A
,
301 __builtin_ia32_cmpnless ((__v4sf
) __B
,
306 static __inline __m128
307 _mm_cmpord_ss (__m128 __A
, __m128 __B
)
309 return (__m128
) __builtin_ia32_cmpordss ((__v4sf
)__A
, (__v4sf
)__B
);
312 static __inline __m128
313 _mm_cmpunord_ss (__m128 __A
, __m128 __B
)
315 return (__m128
) __builtin_ia32_cmpunordss ((__v4sf
)__A
, (__v4sf
)__B
);
318 /* Perform a comparison on the four SPFP values of A and B. For each
319 element, if the comparison is true, place a mask of all ones in the
320 result, otherwise a mask of zeros. */
322 static __inline __m128
323 _mm_cmpeq_ps (__m128 __A
, __m128 __B
)
325 return (__m128
) __builtin_ia32_cmpeqps ((__v4sf
)__A
, (__v4sf
)__B
);
328 static __inline __m128
329 _mm_cmplt_ps (__m128 __A
, __m128 __B
)
331 return (__m128
) __builtin_ia32_cmpltps ((__v4sf
)__A
, (__v4sf
)__B
);
334 static __inline __m128
335 _mm_cmple_ps (__m128 __A
, __m128 __B
)
337 return (__m128
) __builtin_ia32_cmpleps ((__v4sf
)__A
, (__v4sf
)__B
);
340 static __inline __m128
341 _mm_cmpgt_ps (__m128 __A
, __m128 __B
)
343 return (__m128
) __builtin_ia32_cmpgtps ((__v4sf
)__A
, (__v4sf
)__B
);
346 static __inline __m128
347 _mm_cmpge_ps (__m128 __A
, __m128 __B
)
349 return (__m128
) __builtin_ia32_cmpgeps ((__v4sf
)__A
, (__v4sf
)__B
);
352 static __inline __m128
353 _mm_cmpneq_ps (__m128 __A
, __m128 __B
)
355 return (__m128
) __builtin_ia32_cmpneqps ((__v4sf
)__A
, (__v4sf
)__B
);
358 static __inline __m128
359 _mm_cmpnlt_ps (__m128 __A
, __m128 __B
)
361 return (__m128
) __builtin_ia32_cmpnltps ((__v4sf
)__A
, (__v4sf
)__B
);
364 static __inline __m128
365 _mm_cmpnle_ps (__m128 __A
, __m128 __B
)
367 return (__m128
) __builtin_ia32_cmpnleps ((__v4sf
)__A
, (__v4sf
)__B
);
370 static __inline __m128
371 _mm_cmpngt_ps (__m128 __A
, __m128 __B
)
373 return (__m128
) __builtin_ia32_cmpngtps ((__v4sf
)__A
, (__v4sf
)__B
);
376 static __inline __m128
377 _mm_cmpnge_ps (__m128 __A
, __m128 __B
)
379 return (__m128
) __builtin_ia32_cmpngeps ((__v4sf
)__A
, (__v4sf
)__B
);
382 static __inline __m128
383 _mm_cmpord_ps (__m128 __A
, __m128 __B
)
385 return (__m128
) __builtin_ia32_cmpordps ((__v4sf
)__A
, (__v4sf
)__B
);
388 static __inline __m128
389 _mm_cmpunord_ps (__m128 __A
, __m128 __B
)
391 return (__m128
) __builtin_ia32_cmpunordps ((__v4sf
)__A
, (__v4sf
)__B
);
394 /* Compare the lower SPFP values of A and B and return 1 if true
398 _mm_comieq_ss (__m128 __A
, __m128 __B
)
400 return __builtin_ia32_comieq ((__v4sf
)__A
, (__v4sf
)__B
);
404 _mm_comilt_ss (__m128 __A
, __m128 __B
)
406 return __builtin_ia32_comilt ((__v4sf
)__A
, (__v4sf
)__B
);
410 _mm_comile_ss (__m128 __A
, __m128 __B
)
412 return __builtin_ia32_comile ((__v4sf
)__A
, (__v4sf
)__B
);
416 _mm_comigt_ss (__m128 __A
, __m128 __B
)
418 return __builtin_ia32_comigt ((__v4sf
)__A
, (__v4sf
)__B
);
422 _mm_comige_ss (__m128 __A
, __m128 __B
)
424 return __builtin_ia32_comige ((__v4sf
)__A
, (__v4sf
)__B
);
428 _mm_comineq_ss (__m128 __A
, __m128 __B
)
430 return __builtin_ia32_comineq ((__v4sf
)__A
, (__v4sf
)__B
);
434 _mm_ucomieq_ss (__m128 __A
, __m128 __B
)
436 return __builtin_ia32_ucomieq ((__v4sf
)__A
, (__v4sf
)__B
);
440 _mm_ucomilt_ss (__m128 __A
, __m128 __B
)
442 return __builtin_ia32_ucomilt ((__v4sf
)__A
, (__v4sf
)__B
);
446 _mm_ucomile_ss (__m128 __A
, __m128 __B
)
448 return __builtin_ia32_ucomile ((__v4sf
)__A
, (__v4sf
)__B
);
452 _mm_ucomigt_ss (__m128 __A
, __m128 __B
)
454 return __builtin_ia32_ucomigt ((__v4sf
)__A
, (__v4sf
)__B
);
458 _mm_ucomige_ss (__m128 __A
, __m128 __B
)
460 return __builtin_ia32_ucomige ((__v4sf
)__A
, (__v4sf
)__B
);
464 _mm_ucomineq_ss (__m128 __A
, __m128 __B
)
466 return __builtin_ia32_ucomineq ((__v4sf
)__A
, (__v4sf
)__B
);
469 /* Convert the lower SPFP value to a 32-bit integer according to the current
472 _mm_cvtss_si32 (__m128 __A
)
474 return __builtin_ia32_cvtss2si ((__v4sf
) __A
);
478 _mm_cvt_ss2si (__m128 __A
)
480 return _mm_cvtss_si32 (__A
);
484 /* Convert the lower SPFP value to a 32-bit integer according to the current
486 static __inline
long long
487 _mm_cvtss_si64x (__m128 __A
)
489 return __builtin_ia32_cvtss2si64 ((__v4sf
) __A
);
493 /* Convert the two lower SPFP values to 32-bit integers according to the
494 current rounding mode. Return the integers in packed form. */
495 static __inline __m64
496 _mm_cvtps_pi32 (__m128 __A
)
498 return (__m64
) __builtin_ia32_cvtps2pi ((__v4sf
) __A
);
501 static __inline __m64
502 _mm_cvt_ps2pi (__m128 __A
)
504 return _mm_cvtps_pi32 (__A
);
507 /* Truncate the lower SPFP value to a 32-bit integer. */
509 _mm_cvttss_si32 (__m128 __A
)
511 return __builtin_ia32_cvttss2si ((__v4sf
) __A
);
515 _mm_cvtt_ss2si (__m128 __A
)
517 return _mm_cvttss_si32 (__A
);
521 /* Truncate the lower SPFP value to a 32-bit integer. */
522 static __inline
long long
523 _mm_cvttss_si64x (__m128 __A
)
525 return __builtin_ia32_cvttss2si64 ((__v4sf
) __A
);
529 /* Truncate the two lower SPFP values to 32-bit integers. Return the
530 integers in packed form. */
531 static __inline __m64
532 _mm_cvttps_pi32 (__m128 __A
)
534 return (__m64
) __builtin_ia32_cvttps2pi ((__v4sf
) __A
);
537 static __inline __m64
538 _mm_cvtt_ps2pi (__m128 __A
)
540 return _mm_cvttps_pi32 (__A
);
543 /* Convert B to a SPFP value and insert it as element zero in A. */
544 static __inline __m128
545 _mm_cvtsi32_ss (__m128 __A
, int __B
)
547 return (__m128
) __builtin_ia32_cvtsi2ss ((__v4sf
) __A
, __B
);
550 static __inline __m128
551 _mm_cvt_si2ss (__m128 __A
, int __B
)
553 return _mm_cvtsi32_ss (__A
, __B
);
557 /* Convert B to a SPFP value and insert it as element zero in A. */
558 static __inline __m128
559 _mm_cvtsi64x_ss (__m128 __A
, long long __B
)
561 return (__m128
) __builtin_ia32_cvtsi642ss ((__v4sf
) __A
, __B
);
565 /* Convert the two 32-bit values in B to SPFP form and insert them
566 as the two lower elements in A. */
567 static __inline __m128
568 _mm_cvtpi32_ps (__m128 __A
, __m64 __B
)
570 return (__m128
) __builtin_ia32_cvtpi2ps ((__v4sf
) __A
, (__v2si
)__B
);
573 static __inline __m128
574 _mm_cvt_pi2ps (__m128 __A
, __m64 __B
)
576 return _mm_cvtpi32_ps (__A
, __B
);
579 /* Convert the four signed 16-bit values in A to SPFP form. */
580 static __inline __m128
581 _mm_cvtpi16_ps (__m64 __A
)
584 __v2si __hisi
, __losi
;
587 /* This comparison against zero gives us a mask that can be used to
588 fill in the missing sign bits in the unpack operations below, so
589 that we get signed values after unpacking. */
590 __sign
= (__v4hi
) __builtin_ia32_mmx_zero ();
591 __sign
= __builtin_ia32_pcmpgtw (__sign
, (__v4hi
)__A
);
593 /* Convert the four words to doublewords. */
594 __hisi
= (__v2si
) __builtin_ia32_punpckhwd ((__v4hi
)__A
, __sign
);
595 __losi
= (__v2si
) __builtin_ia32_punpcklwd ((__v4hi
)__A
, __sign
);
597 /* Convert the doublewords to floating point two at a time. */
598 __r
= (__v4sf
) __builtin_ia32_setzerops ();
599 __r
= __builtin_ia32_cvtpi2ps (__r
, __hisi
);
600 __r
= __builtin_ia32_movlhps (__r
, __r
);
601 __r
= __builtin_ia32_cvtpi2ps (__r
, __losi
);
606 /* Convert the four unsigned 16-bit values in A to SPFP form. */
607 static __inline __m128
608 _mm_cvtpu16_ps (__m64 __A
)
610 __v4hi __zero
= (__v4hi
) __builtin_ia32_mmx_zero ();
611 __v2si __hisi
, __losi
;
614 /* Convert the four words to doublewords. */
615 __hisi
= (__v2si
) __builtin_ia32_punpckhwd ((__v4hi
)__A
, __zero
);
616 __losi
= (__v2si
) __builtin_ia32_punpcklwd ((__v4hi
)__A
, __zero
);
618 /* Convert the doublewords to floating point two at a time. */
619 __r
= (__v4sf
) __builtin_ia32_setzerops ();
620 __r
= __builtin_ia32_cvtpi2ps (__r
, __hisi
);
621 __r
= __builtin_ia32_movlhps (__r
, __r
);
622 __r
= __builtin_ia32_cvtpi2ps (__r
, __losi
);
627 /* Convert the low four signed 8-bit values in A to SPFP form. */
628 static __inline __m128
629 _mm_cvtpi8_ps (__m64 __A
)
633 /* This comparison against zero gives us a mask that can be used to
634 fill in the missing sign bits in the unpack operations below, so
635 that we get signed values after unpacking. */
636 __sign
= (__v8qi
) __builtin_ia32_mmx_zero ();
637 __sign
= __builtin_ia32_pcmpgtb (__sign
, (__v8qi
)__A
);
639 /* Convert the four low bytes to words. */
640 __A
= (__m64
) __builtin_ia32_punpcklbw ((__v8qi
)__A
, __sign
);
642 return _mm_cvtpi16_ps(__A
);
645 /* Convert the low four unsigned 8-bit values in A to SPFP form. */
646 static __inline __m128
647 _mm_cvtpu8_ps(__m64 __A
)
649 __v8qi __zero
= (__v8qi
) __builtin_ia32_mmx_zero ();
650 __A
= (__m64
) __builtin_ia32_punpcklbw ((__v8qi
)__A
, __zero
);
651 return _mm_cvtpu16_ps(__A
);
654 /* Convert the four signed 32-bit values in A and B to SPFP form. */
655 static __inline __m128
656 _mm_cvtpi32x2_ps(__m64 __A
, __m64 __B
)
658 __v4sf __zero
= (__v4sf
) __builtin_ia32_setzerops ();
659 __v4sf __sfa
= __builtin_ia32_cvtpi2ps (__zero
, (__v2si
)__A
);
660 __v4sf __sfb
= __builtin_ia32_cvtpi2ps (__zero
, (__v2si
)__B
);
661 return (__m128
) __builtin_ia32_movlhps (__sfa
, __sfb
);
664 /* Convert the four SPFP values in A to four signed 16-bit integers. */
665 static __inline __m64
666 _mm_cvtps_pi16(__m128 __A
)
668 __v4sf __hisf
= (__v4sf
)__A
;
669 __v4sf __losf
= __builtin_ia32_movhlps (__hisf
, __hisf
);
670 __v2si __hisi
= __builtin_ia32_cvtps2pi (__hisf
);
671 __v2si __losi
= __builtin_ia32_cvtps2pi (__losf
);
672 return (__m64
) __builtin_ia32_packssdw (__hisi
, __losi
);
675 /* Convert the four SPFP values in A to four signed 8-bit integers. */
676 static __inline __m64
677 _mm_cvtps_pi8(__m128 __A
)
679 __v4hi __tmp
= (__v4hi
) _mm_cvtps_pi16 (__A
);
680 __v4hi __zero
= (__v4hi
) __builtin_ia32_mmx_zero ();
681 return (__m64
) __builtin_ia32_packsswb (__tmp
, __zero
);
684 /* Selects four specific SPFP values from A and B based on MASK. */
686 static __inline __m128
687 _mm_shuffle_ps (__m128 __A
, __m128 __B
, int __mask
)
689 return (__m128
) __builtin_ia32_shufps ((__v4sf
)__A
, (__v4sf
)__B
, __mask
);
692 #define _mm_shuffle_ps(A, B, MASK) \
693 ((__m128) __builtin_ia32_shufps ((__v4sf)(A), (__v4sf)(B), (MASK)))
697 /* Selects and interleaves the upper two SPFP values from A and B. */
698 static __inline __m128
699 _mm_unpackhi_ps (__m128 __A
, __m128 __B
)
701 return (__m128
) __builtin_ia32_unpckhps ((__v4sf
)__A
, (__v4sf
)__B
);
704 /* Selects and interleaves the lower two SPFP values from A and B. */
705 static __inline __m128
706 _mm_unpacklo_ps (__m128 __A
, __m128 __B
)
708 return (__m128
) __builtin_ia32_unpcklps ((__v4sf
)__A
, (__v4sf
)__B
);
711 /* Sets the upper two SPFP values with 64-bits of data loaded from P;
712 the lower two values are passed through from A. */
713 static __inline __m128
714 _mm_loadh_pi (__m128 __A
, __m64
const *__P
)
716 return (__m128
) __builtin_ia32_loadhps ((__v4sf
)__A
, (__v2si
*)__P
);
719 /* Stores the upper two SPFP values of A into P. */
721 _mm_storeh_pi (__m64
*__P
, __m128 __A
)
723 __builtin_ia32_storehps ((__v2si
*)__P
, (__v4sf
)__A
);
726 /* Moves the upper two values of B into the lower two values of A. */
727 static __inline __m128
728 _mm_movehl_ps (__m128 __A
, __m128 __B
)
730 return (__m128
) __builtin_ia32_movhlps ((__v4sf
)__A
, (__v4sf
)__B
);
733 /* Moves the lower two values of B into the upper two values of A. */
734 static __inline __m128
735 _mm_movelh_ps (__m128 __A
, __m128 __B
)
737 return (__m128
) __builtin_ia32_movlhps ((__v4sf
)__A
, (__v4sf
)__B
);
740 /* Sets the lower two SPFP values with 64-bits of data loaded from P;
741 the upper two values are passed through from A. */
742 static __inline __m128
743 _mm_loadl_pi (__m128 __A
, __m64
const *__P
)
745 return (__m128
) __builtin_ia32_loadlps ((__v4sf
)__A
, (__v2si
*)__P
);
748 /* Stores the lower two SPFP values of A into P. */
750 _mm_storel_pi (__m64
*__P
, __m128 __A
)
752 __builtin_ia32_storelps ((__v2si
*)__P
, (__v4sf
)__A
);
755 /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
757 _mm_movemask_ps (__m128 __A
)
759 return __builtin_ia32_movmskps ((__v4sf
)__A
);
762 /* Return the contents of the control register. */
763 static __inline
unsigned int
766 return __builtin_ia32_stmxcsr ();
769 /* Read exception bits from the control register. */
770 static __inline
unsigned int
771 _MM_GET_EXCEPTION_STATE (void)
773 return _mm_getcsr() & _MM_EXCEPT_MASK
;
776 static __inline
unsigned int
777 _MM_GET_EXCEPTION_MASK (void)
779 return _mm_getcsr() & _MM_MASK_MASK
;
782 static __inline
unsigned int
783 _MM_GET_ROUNDING_MODE (void)
785 return _mm_getcsr() & _MM_ROUND_MASK
;
788 static __inline
unsigned int
789 _MM_GET_FLUSH_ZERO_MODE (void)
791 return _mm_getcsr() & _MM_FLUSH_ZERO_MASK
;
794 /* Set the control register to I. */
796 _mm_setcsr (unsigned int __I
)
798 __builtin_ia32_ldmxcsr (__I
);
801 /* Set exception bits in the control register. */
803 _MM_SET_EXCEPTION_STATE(unsigned int __mask
)
805 _mm_setcsr((_mm_getcsr() & ~_MM_EXCEPT_MASK
) | __mask
);
809 _MM_SET_EXCEPTION_MASK (unsigned int __mask
)
811 _mm_setcsr((_mm_getcsr() & ~_MM_MASK_MASK
) | __mask
);
815 _MM_SET_ROUNDING_MODE (unsigned int __mode
)
817 _mm_setcsr((_mm_getcsr() & ~_MM_ROUND_MASK
) | __mode
);
821 _MM_SET_FLUSH_ZERO_MODE (unsigned int __mode
)
823 _mm_setcsr((_mm_getcsr() & ~_MM_FLUSH_ZERO_MASK
) | __mode
);
826 /* Create a vector with element 0 as *P and the rest zero. */
827 static __inline __m128
828 _mm_load_ss (float const *__P
)
830 return (__m128
) __builtin_ia32_loadss (__P
);
833 /* Create a vector with all four elements equal to *P. */
834 static __inline __m128
835 _mm_load1_ps (float const *__P
)
837 __v4sf __tmp
= __builtin_ia32_loadss (__P
);
838 return (__m128
) __builtin_ia32_shufps (__tmp
, __tmp
, _MM_SHUFFLE (0,0,0,0));
841 static __inline __m128
842 _mm_load_ps1 (float const *__P
)
844 return _mm_load1_ps (__P
);
847 /* Load four SPFP values from P. The address must be 16-byte aligned. */
848 static __inline __m128
849 _mm_load_ps (float const *__P
)
851 return (__m128
) __builtin_ia32_loadaps (__P
);
854 /* Load four SPFP values from P. The address need not be 16-byte aligned. */
855 static __inline __m128
856 _mm_loadu_ps (float const *__P
)
858 return (__m128
) __builtin_ia32_loadups (__P
);
861 /* Load four SPFP values in reverse order. The address must be aligned. */
862 static __inline __m128
863 _mm_loadr_ps (float const *__P
)
865 __v4sf __tmp
= __builtin_ia32_loadaps (__P
);
866 return (__m128
) __builtin_ia32_shufps (__tmp
, __tmp
, _MM_SHUFFLE (0,1,2,3));
869 /* Create a vector with element 0 as F and the rest zero. */
870 static __inline __m128
871 _mm_set_ss (float __F
)
873 return (__m128
) __builtin_ia32_loadss (&__F
);
876 /* Create a vector with all four elements equal to F. */
877 static __inline __m128
878 _mm_set1_ps (float __F
)
880 __v4sf __tmp
= __builtin_ia32_loadss (&__F
);
881 return (__m128
) __builtin_ia32_shufps (__tmp
, __tmp
, _MM_SHUFFLE (0,0,0,0));
884 static __inline __m128
885 _mm_set_ps1 (float __F
)
887 return _mm_set1_ps (__F
);
890 /* Create the vector [Z Y X W]. */
891 static __inline __m128
892 _mm_set_ps (const float __Z
, const float __Y
, const float __X
, const float __W
)
894 return (__v4sf
) {__W
, __X
, __Y
, __Z
};
897 /* Create the vector [W X Y Z]. */
898 static __inline __m128
899 _mm_setr_ps (float __Z
, float __Y
, float __X
, float __W
)
901 return _mm_set_ps (__W
, __X
, __Y
, __Z
);
904 /* Create a vector of zeros. */
905 static __inline __m128
906 _mm_setzero_ps (void)
908 return (__m128
) __builtin_ia32_setzerops ();
911 /* Stores the lower SPFP value. */
913 _mm_store_ss (float *__P
, __m128 __A
)
915 __builtin_ia32_storess (__P
, (__v4sf
)__A
);
918 /* Store the lower SPFP value across four words. */
920 _mm_store1_ps (float *__P
, __m128 __A
)
922 __v4sf __va
= (__v4sf
)__A
;
923 __v4sf __tmp
= __builtin_ia32_shufps (__va
, __va
, _MM_SHUFFLE (0,0,0,0));
924 __builtin_ia32_storeaps (__P
, __tmp
);
928 _mm_store_ps1 (float *__P
, __m128 __A
)
930 _mm_store1_ps (__P
, __A
);
933 /* Store four SPFP values. The address must be 16-byte aligned. */
935 _mm_store_ps (float *__P
, __m128 __A
)
937 __builtin_ia32_storeaps (__P
, (__v4sf
)__A
);
940 /* Store four SPFP values. The address need not be 16-byte aligned. */
942 _mm_storeu_ps (float *__P
, __m128 __A
)
944 __builtin_ia32_storeups (__P
, (__v4sf
)__A
);
947 /* Store four SPFP values in reverse order. The address must be aligned. */
949 _mm_storer_ps (float *__P
, __m128 __A
)
951 __v4sf __va
= (__v4sf
)__A
;
952 __v4sf __tmp
= __builtin_ia32_shufps (__va
, __va
, _MM_SHUFFLE (0,1,2,3));
953 __builtin_ia32_storeaps (__P
, __tmp
);
956 /* Sets the low SPFP value of A from the low value of B. */
957 static __inline __m128
958 _mm_move_ss (__m128 __A
, __m128 __B
)
960 return (__m128
) __builtin_ia32_movss ((__v4sf
)__A
, (__v4sf
)__B
);
963 /* Extracts one of the four words of A. The selector N must be immediate. */
966 _mm_extract_pi16 (__m64 __A
, int __N
)
968 return __builtin_ia32_pextrw ((__v4hi
)__A
, __N
);
972 _m_pextrw (__m64 __A
, int __N
)
974 return _mm_extract_pi16 (__A
, __N
);
977 #define _mm_extract_pi16(A, N) \
978 __builtin_ia32_pextrw ((__v4hi)(A), (N))
979 #define _m_pextrw(A, N) _mm_extract_pi16((A), (N))
982 /* Inserts word D into one of four words of A. The selector N must be
985 static __inline __m64
986 _mm_insert_pi16 (__m64 __A
, int __D
, int __N
)
988 return (__m64
)__builtin_ia32_pinsrw ((__v4hi
)__A
, __D
, __N
);
991 static __inline __m64
992 _m_pinsrw (__m64 __A
, int __D
, int __N
)
994 return _mm_insert_pi16 (__A
, __D
, __N
);
997 #define _mm_insert_pi16(A, D, N) \
998 ((__m64) __builtin_ia32_pinsrw ((__v4hi)(A), (D), (N)))
999 #define _m_pinsrw(A, D, N) _mm_insert_pi16((A), (D), (N))
1002 /* Compute the element-wise maximum of signed 16-bit values. */
1003 static __inline __m64
1004 _mm_max_pi16 (__m64 __A
, __m64 __B
)
1006 return (__m64
) __builtin_ia32_pmaxsw ((__v4hi
)__A
, (__v4hi
)__B
);
1009 static __inline __m64
1010 _m_pmaxsw (__m64 __A
, __m64 __B
)
1012 return _mm_max_pi16 (__A
, __B
);
1015 /* Compute the element-wise maximum of unsigned 8-bit values. */
1016 static __inline __m64
1017 _mm_max_pu8 (__m64 __A
, __m64 __B
)
1019 return (__m64
) __builtin_ia32_pmaxub ((__v8qi
)__A
, (__v8qi
)__B
);
1022 static __inline __m64
1023 _m_pmaxub (__m64 __A
, __m64 __B
)
1025 return _mm_max_pu8 (__A
, __B
);
1028 /* Compute the element-wise minimum of signed 16-bit values. */
1029 static __inline __m64
1030 _mm_min_pi16 (__m64 __A
, __m64 __B
)
1032 return (__m64
) __builtin_ia32_pminsw ((__v4hi
)__A
, (__v4hi
)__B
);
1035 static __inline __m64
1036 _m_pminsw (__m64 __A
, __m64 __B
)
1038 return _mm_min_pi16 (__A
, __B
);
1041 /* Compute the element-wise minimum of unsigned 8-bit values. */
1042 static __inline __m64
1043 _mm_min_pu8 (__m64 __A
, __m64 __B
)
1045 return (__m64
) __builtin_ia32_pminub ((__v8qi
)__A
, (__v8qi
)__B
);
1048 static __inline __m64
1049 _m_pminub (__m64 __A
, __m64 __B
)
1051 return _mm_min_pu8 (__A
, __B
);
1054 /* Create an 8-bit mask of the signs of 8-bit values. */
1056 _mm_movemask_pi8 (__m64 __A
)
1058 return __builtin_ia32_pmovmskb ((__v8qi
)__A
);
1062 _m_pmovmskb (__m64 __A
)
1064 return _mm_movemask_pi8 (__A
);
1067 /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
1068 in B and produce the high 16 bits of the 32-bit results. */
1069 static __inline __m64
1070 _mm_mulhi_pu16 (__m64 __A
, __m64 __B
)
1072 return (__m64
) __builtin_ia32_pmulhuw ((__v4hi
)__A
, (__v4hi
)__B
);
1075 static __inline __m64
1076 _m_pmulhuw (__m64 __A
, __m64 __B
)
1078 return _mm_mulhi_pu16 (__A
, __B
);
1081 /* Return a combination of the four 16-bit values in A. The selector
1082 must be an immediate. */
1084 static __inline __m64
1085 _mm_shuffle_pi16 (__m64 __A
, int __N
)
1087 return (__m64
) __builtin_ia32_pshufw ((__v4hi
)__A
, __N
);
1090 static __inline __m64
1091 _m_pshufw (__m64 __A
, int __N
)
1093 return _mm_shuffle_pi16 (__A
, __N
);
1096 #define _mm_shuffle_pi16(A, N) \
1097 ((__m64) __builtin_ia32_pshufw ((__v4hi)(A), (N)))
1098 #define _m_pshufw(A, N) _mm_shuffle_pi16 ((A), (N))
1101 /* Conditionally store byte elements of A into P. The high bit of each
1102 byte in the selector N determines whether the corresponding byte from
1104 static __inline
void
1105 _mm_maskmove_si64 (__m64 __A
, __m64 __N
, char *__P
)
1107 __builtin_ia32_maskmovq ((__v8qi
)__A
, (__v8qi
)__N
, __P
);
1110 static __inline
void
1111 _m_maskmovq (__m64 __A
, __m64 __N
, char *__P
)
1113 _mm_maskmove_si64 (__A
, __N
, __P
);
1116 /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
1117 static __inline __m64
1118 _mm_avg_pu8 (__m64 __A
, __m64 __B
)
1120 return (__m64
) __builtin_ia32_pavgb ((__v8qi
)__A
, (__v8qi
)__B
);
1123 static __inline __m64
1124 _m_pavgb (__m64 __A
, __m64 __B
)
1126 return _mm_avg_pu8 (__A
, __B
);
1129 /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
1130 static __inline __m64
1131 _mm_avg_pu16 (__m64 __A
, __m64 __B
)
1133 return (__m64
) __builtin_ia32_pavgw ((__v4hi
)__A
, (__v4hi
)__B
);
1136 static __inline __m64
1137 _m_pavgw (__m64 __A
, __m64 __B
)
1139 return _mm_avg_pu16 (__A
, __B
);
1142 /* Compute the sum of the absolute differences of the unsigned 8-bit
1143 values in A and B. Return the value in the lower 16-bit word; the
1144 upper words are cleared. */
1145 static __inline __m64
1146 _mm_sad_pu8 (__m64 __A
, __m64 __B
)
1148 return (__m64
) __builtin_ia32_psadbw ((__v8qi
)__A
, (__v8qi
)__B
);
1151 static __inline __m64
1152 _m_psadbw (__m64 __A
, __m64 __B
)
1154 return _mm_sad_pu8 (__A
, __B
);
1157 /* Loads one cache line from address P to a location "closer" to the
1158 processor. The selector I specifies the type of prefetch operation. */
1160 static __inline
void
1161 _mm_prefetch (void *__P
, enum _mm_hint __I
)
1163 __builtin_prefetch (__P
, 0, __I
);
1166 #define _mm_prefetch(P, I) \
1167 __builtin_prefetch ((P), 0, (I))
1170 /* Stores the data in A to the address P without polluting the caches. */
1171 static __inline
void
1172 _mm_stream_pi (__m64
*__P
, __m64 __A
)
1174 __builtin_ia32_movntq ((unsigned long long *)__P
, (unsigned long long)__A
);
1177 /* Likewise. The address must be 16-byte aligned. */
1178 static __inline
void
1179 _mm_stream_ps (float *__P
, __m128 __A
)
1181 __builtin_ia32_movntps (__P
, (__v4sf
)__A
);
1184 /* Guarantees that every preceding store is globally visible before
1185 any subsequent store. */
1186 static __inline
void
1189 __builtin_ia32_sfence ();
1192 /* The execution of the next instruction is delayed by an implementation
1193 specific amount of time. The instruction does not modify the
1194 architectural state. */
1195 static __inline
void
1198 __asm__
__volatile__ ("rep; nop" : : );
1201 /* Transpose the 4x4 matrix composed of row[0-3]. */
1202 #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
1204 __v4sf __r0 = (row0), __r1 = (row1), __r2 = (row2), __r3 = (row3); \
1205 __v4sf __t0 = __builtin_ia32_shufps (__r0, __r1, 0x44); \
1206 __v4sf __t2 = __builtin_ia32_shufps (__r0, __r1, 0xEE); \
1207 __v4sf __t1 = __builtin_ia32_shufps (__r2, __r3, 0x44); \
1208 __v4sf __t3 = __builtin_ia32_shufps (__r2, __r3, 0xEE); \
1209 (row0) = __builtin_ia32_shufps (__t0, __t1, 0x88); \
1210 (row1) = __builtin_ia32_shufps (__t0, __t1, 0xDD); \
1211 (row2) = __builtin_ia32_shufps (__t2, __t3, 0x88); \
1212 (row3) = __builtin_ia32_shufps (__t2, __t3, 0xDD); \
1215 /* For backward source compatibility. */
1216 #include <emmintrin.h>
1218 #endif /* __SSE__ */
1219 #endif /* _XMMINTRIN_H_INCLUDED */
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