gcc/config/i386/znver1.md

   1 ;; Copyright (C) 2012-2020 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19
  20
  21 (define_attr "znver1_decode" "direct,vector,double"
  22   (const_string "direct"))
  23
  24 ;; AMD znver1 and znver2 Scheduling
  25 ;; Modeling automatons for zen decoders, integer execution pipes,
  26 ;; AGU pipes and floating point execution units.
  27 (define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu")
  28
  29 ;; Decoders unit has 4 decoders and all of them can decode fast path
  30 ;; and vector type instructions.
  31 (define_cpu_unit "znver1-decode0" "znver1")
  32 (define_cpu_unit "znver1-decode1" "znver1")
  33 (define_cpu_unit "znver1-decode2" "znver1")
  34 (define_cpu_unit "znver1-decode3" "znver1")
  35
  36 ;; Currently blocking all decoders for vector path instructions as
  37 ;; they are dispatched separetely as microcode sequence.
  38 ;; Fix me: Need to revisit this.
  39 (define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3")
  40
  41 ;; Direct instructions can be issued to any of the four decoders.
  42 (define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3")
  43
  44 ;; Fix me: Need to revisit this later to simulate fast path double behavior.
  45 (define_reservation "znver1-double" "znver1-direct")
  46
  47
  48 ;; Integer unit 4 ALU pipes.
  49 (define_cpu_unit "znver1-ieu0" "znver1_ieu")
  50 (define_cpu_unit "znver1-ieu1" "znver1_ieu")
  51 (define_cpu_unit "znver1-ieu2" "znver1_ieu")
  52 (define_cpu_unit "znver1-ieu3" "znver1_ieu")
  53 (define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3")
  54
  55 ;; 2 AGU pipes in znver1 and 3 AGU pipes in znver2
  56 ;; According to CPU diagram last AGU unit is used only for stores.
  57 (define_cpu_unit "znver1-agu0" "znver1_agu")
  58 (define_cpu_unit "znver1-agu1" "znver1_agu")
  59 (define_cpu_unit "znver2-agu2" "znver1_agu")
  60 (define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1")
  61 (define_reservation "znver2-store-agu-reserve" "znver1-agu0|znver1-agu1|znver2-agu2")
  62
  63 ;; Load is 4 cycles. We do not model reservation of load unit.
  64 ;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing")
  65 (define_reservation "znver1-load" "znver1-agu-reserve")
  66 ;; Store operations differs between znver1 and znver2 because extra AGU
  67 ;; was added.
  68 (define_reservation "znver1-store" "znver1-agu-reserve")
  69 (define_reservation "znver2-store" "znver2-store-agu-reserve")
  70
  71 ;; vectorpath (microcoded) instructions are single issue instructions.
  72 ;; So, they occupy all the integer units.
  73 (define_reservation "znver1-ivector" "znver1-ieu0+znver1-ieu1
  74                                       +znver1-ieu2+znver1-ieu3
  75                                       +znver1-agu0+znver1-agu1")
  76
  77 (define_reservation "znver2-ivector" "znver1-ieu0+znver1-ieu1
  78                                       +znver1-ieu2+znver1-ieu3
  79                                       +znver1-agu0+znver1-agu1+znver2-agu2")
  80 ;; Floating point unit 4 FP pipes.
  81 (define_cpu_unit "znver1-fp0" "znver1_fp")
  82 (define_cpu_unit "znver1-fp1" "znver1_fp")
  83 (define_cpu_unit "znver1-fp2" "znver1_fp")
  84 (define_cpu_unit "znver1-fp3" "znver1_fp")
  85
  86 (define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3")
  87
  88 (define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1
  89                                       +znver1-fp2+znver1-fp3
  90                                       +znver1-agu0+znver1-agu1")
  91 (define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1
  92                                       +znver1-fp2+znver1-fp3
  93                                       +znver1-agu0+znver1-agu1+znver2-agu2")
  94
  95 ;; Call instruction
  96 (define_insn_reservation "znver1_call" 1
  97                          (and (eq_attr "cpu" "znver1")
  98                               (eq_attr "type" "call,callv"))
  99                          "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3")
 100
 101 (define_insn_reservation "znver2_call" 1
 102                          (and (eq_attr "cpu" "znver2")
 103                               (eq_attr "type" "call,callv"))
 104                          "znver1-double,znver2-store,znver1-ieu0|znver1-ieu3")
 105
 106 ;; General instructions
 107 (define_insn_reservation "znver1_push" 1
 108                          (and (eq_attr "cpu" "znver1")
 109                               (and (eq_attr "type" "push")
 110                                    (eq_attr "memory" "store")))
 111                          "znver1-direct,znver1-store")
 112 (define_insn_reservation "znver2_push" 1
 113                          (and (eq_attr "cpu" "znver2")
 114                               (and (eq_attr "type" "push")
 115                                    (eq_attr "memory" "store")))
 116                          "znver1-direct,znver1-store")
 117
 118 (define_insn_reservation "znver1_push_load" 4
 119                          (and (eq_attr "cpu" "znver1")
 120                               (and (eq_attr "type" "push")
 121                                    (eq_attr "memory" "both")))
 122                          "znver1-direct,znver1-load,znver1-store")
 123 (define_insn_reservation "znver2_push_load" 4
 124                          (and (eq_attr "cpu" "znver2")
 125                               (and (eq_attr "type" "push")
 126                                    (eq_attr "memory" "both")))
 127                          "znver1-direct,znver1-load,znver2-store")
 128
 129 (define_insn_reservation "znver1_pop" 4
 130                          (and (eq_attr "cpu" "znver1,znver2")
 131                               (and (eq_attr "type" "pop")
 132                                    (eq_attr "memory" "load")))
 133                          "znver1-direct,znver1-load")
 134
 135 (define_insn_reservation "znver1_pop_mem" 4
 136                          (and (eq_attr "cpu" "znver1")
 137                               (and (eq_attr "type" "pop")
 138                                    (eq_attr "memory" "both")))
 139                          "znver1-direct,znver1-load,znver1-store")
 140 (define_insn_reservation "znver2_pop_mem" 4
 141                          (and (eq_attr "cpu" "znver2")
 142                               (and (eq_attr "type" "pop")
 143                                    (eq_attr "memory" "both")))
 144                          "znver1-direct,znver1-load,znver2-store")
 145
 146 ;; Leave
 147 (define_insn_reservation "znver1_leave" 1
 148                          (and (eq_attr "cpu" "znver1")
 149                               (eq_attr "type" "leave"))
 150                          "znver1-double,znver1-ieu, znver1-store")
 151 (define_insn_reservation "znver2_leave" 1
 152                          (and (eq_attr "cpu" "znver2")
 153                               (eq_attr "type" "leave"))
 154                          "znver1-double,znver1-ieu, znver2-store")
 155
 156 ;; Integer Instructions or General instructions
 157 ;; Multiplications
 158 ;; Reg operands
 159 (define_insn_reservation "znver1_imul" 3
 160                          (and (eq_attr "cpu" "znver1,znver2")
 161                               (and (eq_attr "type" "imul")
 162                                    (eq_attr "memory" "none")))
 163                          "znver1-direct,znver1-ieu1")
 164
 165 (define_insn_reservation "znver1_imul_mem" 7
 166                          (and (eq_attr "cpu" "znver1,znver2")
 167                               (and (eq_attr "type" "imul")
 168                                    (eq_attr "memory" "!none")))
 169                          "znver1-direct,znver1-load, znver1-ieu1")
 170
 171 ;; Divisions
 172 ;; Reg operands
 173 (define_insn_reservation "znver1_idiv_DI" 41
 174                          (and (eq_attr "cpu" "znver1,znver2")
 175                               (and (eq_attr "type" "idiv")
 176                                    (and (eq_attr "mode" "DI")
 177                                         (eq_attr "memory" "none"))))
 178                          "znver1-double,znver1-ieu2*41")
 179
 180 (define_insn_reservation "znver1_idiv_SI" 25
 181                          (and (eq_attr "cpu" "znver1,znver2")
 182                               (and (eq_attr "type" "idiv")
 183                                    (and (eq_attr "mode" "SI")
 184                                         (eq_attr "memory" "none"))))
 185                          "znver1-double,znver1-ieu2*25")
 186
 187 (define_insn_reservation "znver1_idiv_HI" 17
 188                          (and (eq_attr "cpu" "znver1,znver2")
 189                               (and (eq_attr "type" "idiv")
 190                                    (and (eq_attr "mode" "HI")
 191                                         (eq_attr "memory" "none"))))
 192                          "znver1-double,znver1-ieu2*17")
 193
 194 (define_insn_reservation "znver1_idiv_QI" 12
 195                          (and (eq_attr "cpu" "znver1,znver2")
 196                               (and (eq_attr "type" "idiv")
 197                                    (and (eq_attr "mode" "QI")
 198                                         (eq_attr "memory" "none"))))
 199                          "znver1-direct,znver1-ieu2*12")
 200
 201 ;; Mem operands
 202 (define_insn_reservation "znver1_idiv_mem_DI" 45
 203                          (and (eq_attr "cpu" "znver1,znver2")
 204                               (and (eq_attr "type" "idiv")
 205                                    (and (eq_attr "mode" "DI")
 206                                         (eq_attr "memory" "none"))))
 207                          "znver1-double,znver1-load,znver1-ieu2*41")
 208
 209 (define_insn_reservation "znver1_idiv_mem_SI" 29
 210                          (and (eq_attr "cpu" "znver1,znver2")
 211                               (and (eq_attr "type" "idiv")
 212                                    (and (eq_attr "mode" "SI")
 213                                         (eq_attr "memory" "none"))))
 214                          "znver1-double,znver1-load,znver1-ieu2*25")
 215
 216 (define_insn_reservation "znver1_idiv_mem_HI" 21
 217                          (and (eq_attr "cpu" "znver1,znver2")
 218                               (and (eq_attr "type" "idiv")
 219                                    (and (eq_attr "mode" "HI")
 220                                         (eq_attr "memory" "none"))))
 221                          "znver1-double,znver1-load,znver1-ieu2*17")
 222
 223 (define_insn_reservation "znver1_idiv_mem_QI" 16
 224                          (and (eq_attr "cpu" "znver1,znver2")
 225                               (and (eq_attr "type" "idiv")
 226                                    (and (eq_attr "mode" "QI")
 227                                         (eq_attr "memory" "none"))))
 228                          "znver1-direct,znver1-load,znver1-ieu2*12")
 229
 230 ;; STR ISHIFT which are micro coded.
 231 ;; Fix me: Latency need to be rechecked.
 232 (define_insn_reservation "znver1_str_ishift" 6
 233                          (and (eq_attr "cpu" "znver1")
 234                               (and (eq_attr "type" "str,ishift")
 235                                    (eq_attr "memory" "both,store")))
 236                          "znver1-vector,znver1-ivector")
 237
 238 (define_insn_reservation "znver2_str_ishift" 3
 239                          (and (eq_attr "cpu" "znver2")
 240                               (and (eq_attr "type" "ishift")
 241                                    (eq_attr "memory" "both,store")))
 242                          "znver1-vector,znver1-ivector")
 243 (define_insn_reservation "znver2_str_istr" 19
 244                          (and (eq_attr "cpu" "znver2")
 245                               (and (eq_attr "type" "str")
 246                                    (eq_attr "memory" "both,store")))
 247                          "znver1-vector,znver1-ivector")
 248 ;; MOV - integer moves
 249 (define_insn_reservation "znver1_load_imov_double" 2
 250                          (and (eq_attr "cpu" "znver1")
 251                               (and (eq_attr "znver1_decode" "double")
 252                                    (and (eq_attr "type" "imovx")
 253                                         (eq_attr "memory" "none"))))
 254                          "znver1-double,znver1-ieu|znver1-ieu")
 255
 256 (define_insn_reservation "znver2_load_imov_double" 1
 257                          (and (eq_attr "cpu" "znver2")
 258                               (and (eq_attr "znver1_decode" "double")
 259                                    (and (eq_attr "type" "imovx")
 260                                         (eq_attr "memory" "none"))))
 261                          "znver1-double,znver1-ieu|znver1-ieu")
 262
 263 (define_insn_reservation "znver1_load_imov_direct" 1
 264                          (and (eq_attr "cpu" "znver1,znver2")
 265                               (and (eq_attr "type" "imov,imovx")
 266                                    (eq_attr "memory" "none")))
 267                          "znver1-direct,znver1-ieu")
 268
 269 (define_insn_reservation "znver1_load_imov_double_store" 2
 270                          (and (eq_attr "cpu" "znver1")
 271                               (and (eq_attr "znver1_decode" "double")
 272                                    (and (eq_attr "type" "imovx")
 273                                         (eq_attr "memory" "store"))))
 274                          "znver1-double,znver1-ieu|znver1-ieu,znver1-store")
 275
 276 (define_insn_reservation "znver2_load_imov_double_store" 1
 277                          (and (eq_attr "cpu" "znver2")
 278                               (and (eq_attr "znver1_decode" "double")
 279                                    (and (eq_attr "type" "imovx")
 280                                         (eq_attr "memory" "store"))))
 281                          "znver1-double,znver1-ieu|znver1-ieu,znver2-store")
 282
 283 (define_insn_reservation "znver1_load_imov_direct_store" 1
 284                          (and (eq_attr "cpu" "znver1")
 285                               (and (eq_attr "type" "imov,imovx")
 286                                    (eq_attr "memory" "store")))
 287                                    "znver1-direct,znver1-ieu,znver1-store")
 288
 289 (define_insn_reservation "znver2_load_imov_direct_store" 1
 290                          (and (eq_attr "cpu" "znver2")
 291                               (and (eq_attr "type" "imov,imovx")
 292                                    (eq_attr "memory" "store")))
 293                                    "znver1-direct,znver1-ieu,znver2-store")
 294
 295 (define_insn_reservation "znver1_load_imov_double_load" 5
 296                          (and (eq_attr "cpu" "znver1,znver2")
 297                               (and (eq_attr "znver1_decode" "double")
 298                                    (and (eq_attr "type" "imovx")
 299                                         (eq_attr "memory" "load"))))
 300                          "znver1-double,znver1-load,znver1-ieu|znver1-ieu")
 301
 302 (define_insn_reservation "znver2_load_imov_double_load" 4
 303                          (and (eq_attr "cpu" "znver1,znver2")
 304                               (and (eq_attr "znver1_decode" "double")
 305                                    (and (eq_attr "type" "imovx")
 306                                         (eq_attr "memory" "load"))))
 307                          "znver1-double,znver1-load,znver1-ieu|znver1-ieu")
 308
 309 (define_insn_reservation "znver1_load_imov_direct_load" 4
 310                          (and (eq_attr "cpu" "znver1,znver2")
 311                               (and (eq_attr "type" "imov,imovx")
 312                                    (eq_attr "memory" "load")))
 313                          "znver1-direct,znver1-load")
 314
 315 ;; INTEGER/GENERAL instructions
 316 ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
 317 (define_insn_reservation "znver1_insn" 1
 318                          (and (eq_attr "cpu" "znver1,znver2")
 319                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
 320                                    (eq_attr "memory" "none,unknown")))
 321                          "znver1-direct,znver1-ieu")
 322
 323 (define_insn_reservation "znver1_insn_load" 5
 324                          (and (eq_attr "cpu" "znver1,znver2")
 325                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
 326                                    (eq_attr "memory" "load")))
 327                          "znver1-direct,znver1-load,znver1-ieu")
 328
 329 (define_insn_reservation "znver1_insn_store" 1
 330                          (and (eq_attr "cpu" "znver1")
 331                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
 332                                    (eq_attr "memory" "store")))
 333                          "znver1-direct,znver1-ieu,znver1-store")
 334
 335 (define_insn_reservation "znver2_insn_store" 1
 336                          (and (eq_attr "cpu" "znver2")
 337                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
 338                                    (eq_attr "memory" "store")))
 339                          "znver1-direct,znver1-ieu,znver2-store")
 340
 341 (define_insn_reservation "znver1_insn_both" 5
 342                          (and (eq_attr "cpu" "znver1")
 343                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
 344                                    (eq_attr "memory" "both")))
 345                          "znver1-direct,znver1-load,znver1-ieu,znver1-store")
 346
 347 (define_insn_reservation "znver2_insn_both" 5
 348                          (and (eq_attr "cpu" "znver2")
 349                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
 350                                    (eq_attr "memory" "both")))
 351                          "znver1-direct,znver1-load,znver1-ieu,znver2-store")
 352
 353 ;; Fix me: Other vector type insns keeping latency 6 as of now.
 354 (define_insn_reservation "znver1_ieu_vector" 6
 355                          (and (eq_attr "cpu" "znver1")
 356                               (eq_attr "type" "other,str,multi"))
 357                          "znver1-vector,znver1-ivector")
 358
 359 (define_insn_reservation "znver2_ieu_vector" 5
 360                          (and (eq_attr "cpu" "znver2")
 361                               (eq_attr "type" "other,str,multi"))
 362                          "znver1-vector,znver2-ivector")
 363
 364 ;; ALU1 register operands.
 365 (define_insn_reservation "znver1_alu1_vector" 3
 366                          (and (eq_attr "cpu" "znver1")
 367                               (and (eq_attr "znver1_decode" "vector")
 368                                    (and (eq_attr "type" "alu1")
 369                                         (eq_attr "memory" "none,unknown"))))
 370                          "znver1-vector,znver1-ivector")
 371
 372 (define_insn_reservation "znver2_alu1_vector" 3
 373                          (and (eq_attr "cpu" "znver2")
 374                               (and (eq_attr "znver1_decode" "vector")
 375                                    (and (eq_attr "type" "alu1")
 376                                         (eq_attr "memory" "none,unknown"))))
 377                          "znver1-vector,znver2-ivector")
 378
 379 (define_insn_reservation "znver1_alu1_double" 2
 380                          (and (eq_attr "cpu" "znver1,znver2")
 381                               (and (eq_attr "znver1_decode" "double")
 382                                    (and (eq_attr "type" "alu1")
 383                                         (eq_attr "memory" "none,unknown"))))
 384                          "znver1-double,znver1-ieu")
 385
 386 (define_insn_reservation "znver1_alu1_direct" 1
 387                          (and (eq_attr "cpu" "znver1,znver2")
 388                               (and (eq_attr "znver1_decode" "direct")
 389                                    (and (eq_attr "type" "alu1")
 390                                         (eq_attr "memory" "none,unknown"))))
 391                          "znver1-direct,znver1-ieu")
 392
 393 ;; Branches : Fix me need to model conditional branches.
 394 (define_insn_reservation "znver1_branch" 1
 395                          (and (eq_attr "cpu" "znver1,znver2")
 396                               (and (eq_attr "type" "ibr")
 397                                    (eq_attr "memory" "none")))
 398                           "znver1-direct")
 399
 400 ;; Indirect branches check latencies.
 401 (define_insn_reservation "znver1_indirect_branch_mem" 6
 402                          (and (eq_attr "cpu" "znver1")
 403                               (and (eq_attr "type" "ibr")
 404                                    (eq_attr "memory" "load")))
 405                          "znver1-vector,znver1-ivector")
 406
 407 (define_insn_reservation "znver2_indirect_branch_mem" 6
 408                          (and (eq_attr "cpu" "znver2")
 409                               (and (eq_attr "type" "ibr")
 410                                    (eq_attr "memory" "load")))
 411                          "znver1-vector,znver2-ivector")
 412
 413 ;; LEA executes in ALU units with 1 cycle latency.
 414 (define_insn_reservation "znver1_lea" 1
 415                          (and (eq_attr "cpu" "znver1,znver2")
 416                               (eq_attr "type" "lea"))
 417                          "znver1-direct,znver1-ieu")
 418
 419 ;; Other integer instrucions
 420 (define_insn_reservation "znver1_idirect" 1
 421                          (and (eq_attr "cpu" "znver1,znver2")
 422                               (and (eq_attr "unit" "integer,unknown")
 423                                    (eq_attr "memory" "none,unknown")))
 424                          "znver1-direct,znver1-ieu")
 425
 426 ;;  Floating point
 427 (define_insn_reservation "znver1_fp_cmov" 6
 428                          (and (eq_attr "cpu" "znver1,znver2")
 429                               (eq_attr "type" "fcmov"))
 430                          "znver1-vector,znver1-fvector")
 431
 432 (define_insn_reservation "znver1_fp_mov_direct_load" 8
 433                          (and (eq_attr "cpu" "znver1,znver2")
 434                               (and (eq_attr "znver1_decode" "direct")
 435                                    (and (eq_attr "type" "fmov")
 436                                         (eq_attr "memory" "load"))))
 437                          "znver1-direct,znver1-load,znver1-fp3|znver1-fp1")
 438
 439 (define_insn_reservation "znver1_fp_mov_direct_store" 5
 440                          (and (eq_attr "cpu" "znver1")
 441                               (and (eq_attr "znver1_decode" "direct")
 442                                    (and (eq_attr "type" "fmov")
 443                                         (eq_attr "memory" "store"))))
 444                          "znver1-direct,znver1-fp2|znver1-fp3,znver1-store")
 445 (define_insn_reservation "znver2_fp_mov_direct_store" 5
 446                          (and (eq_attr "cpu" "znver2")
 447                               (and (eq_attr "znver1_decode" "direct")
 448                                    (and (eq_attr "type" "fmov")
 449                                         (eq_attr "memory" "store"))))
 450                          "znver1-direct,znver1-fp2|znver1-fp3,znver2-store")
 451
 452 (define_insn_reservation "znver1_fp_mov_double" 4
 453                          (and (eq_attr "cpu" "znver1,znver2")
 454                               (and (eq_attr "znver1_decode" "double")
 455                                    (and (eq_attr "type" "fmov")
 456                                         (eq_attr "memory" "none"))))
 457                          "znver1-double,znver1-fp3")
 458
 459 (define_insn_reservation "znver1_fp_mov_double_load" 12
 460                          (and (eq_attr "cpu" "znver1")
 461                               (and (eq_attr "znver1_decode" "double")
 462                                    (and (eq_attr "type" "fmov")
 463                                         (eq_attr "memory" "load"))))
 464                          "znver1-double,znver1-load,znver1-fp3")
 465
 466 (define_insn_reservation "znver2_fp_mov_double_load" 12
 467                          (and (eq_attr "cpu" "znver2")
 468                               (and (eq_attr "znver1_decode" "double")
 469                                    (and (eq_attr "type" "fmov")
 470                                         (eq_attr "memory" "load"))))
 471                          "znver1-double,znver1-load,znver1-fp3")
 472
 473 (define_insn_reservation "znver1_fp_mov_direct" 1
 474                          (and (eq_attr "cpu" "znver1,znver2")
 475                               (eq_attr "type" "fmov"))
 476                          "znver1-direct,znver1-fp3")
 477
 478 ;; TODO: AGU?
 479 (define_insn_reservation "znver1_fp_spc_direct" 5
 480                          (and (eq_attr "cpu" "znver1,znver2")
 481                               (and (eq_attr "type" "fpspc")
 482                                    (eq_attr "memory" "store")))
 483                          "znver1-direct,znver1-fp3,znver1-fp2")
 484
 485 (define_insn_reservation "znver1_fp_insn_vector" 6
 486                          (and (eq_attr "cpu" "znver1")
 487                               (and (eq_attr "znver1_decode" "vector")
 488                                    (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
 489                          "znver1-vector,znver1-fvector")
 490 (define_insn_reservation "znver2_fp_insn_vector" 6
 491                          (and (eq_attr "cpu" "znver2")
 492                               (and (eq_attr "znver1_decode" "vector")
 493                                    (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
 494                          "znver1-vector,znver2-fvector")
 495
 496 ;; FABS
 497 (define_insn_reservation "znver1_fp_fsgn" 1
 498                          (and (eq_attr "cpu" "znver1,znver2")
 499                               (eq_attr "type" "fsgn"))
 500                          "znver1-direct,znver1-fp3")
 501
 502 (define_insn_reservation "znver1_fp_fcmp" 2
 503                          (and (eq_attr "cpu" "znver1,znver2")
 504                               (and (eq_attr "memory" "none")
 505                                    (and (eq_attr "znver1_decode" "double")
 506                                         (eq_attr "type" "fcmp"))))
 507                          "znver1-double,znver1-fp0,znver1-fp2")
 508
 509 (define_insn_reservation "znver1_fp_fcmp_load" 9
 510                          (and (eq_attr "cpu" "znver1,znver2")
 511                               (and (eq_attr "memory" "none")
 512                                    (and (eq_attr "znver1_decode" "double")
 513                                         (eq_attr "type" "fcmp"))))
 514                          "znver1-double,znver1-load, znver1-fp0,znver1-fp2")
 515
 516 ;;FADD FSUB FMUL
 517 (define_insn_reservation "znver1_fp_op_mul" 5
 518                          (and (eq_attr "cpu" "znver1,znver2")
 519                               (and (eq_attr "type" "fop,fmul")
 520                                    (eq_attr "memory" "none")))
 521                          "znver1-direct,znver1-fp0*5")
 522
 523 (define_insn_reservation "znver1_fp_op_mul_load" 12
 524                          (and (eq_attr "cpu" "znver1,znver2")
 525                               (and (eq_attr "type" "fop,fmul")
 526                                    (eq_attr "memory" "load")))
 527                          "znver1-direct,znver1-load,znver1-fp0*5")
 528
 529 (define_insn_reservation "znver1_fp_op_imul_load" 16
 530                          (and (eq_attr "cpu" "znver1,znver2")
 531                               (and (eq_attr "type" "fop,fmul")
 532                                    (and (eq_attr "fp_int_src" "true")
 533                                         (eq_attr "memory" "load"))))
 534                         "znver1-double,znver1-load,znver1-fp3,znver1-fp0")
 535
 536 (define_insn_reservation "znver1_fp_op_div" 15
 537                          (and (eq_attr "cpu" "znver1,znver2")
 538                               (and (eq_attr "type" "fdiv")
 539                                    (eq_attr "memory" "none")))
 540                          "znver1-direct,znver1-fp3*15")
 541
 542 (define_insn_reservation "znver1_fp_op_div_load" 22
 543                          (and (eq_attr "cpu" "znver1,znver2")
 544                               (and (eq_attr "type" "fdiv")
 545                                    (eq_attr "memory" "load")))
 546                          "znver1-direct,znver1-load,znver1-fp3*15")
 547
 548 (define_insn_reservation "znver1_fp_op_idiv_load" 27
 549                          (and (eq_attr "cpu" "znver1")
 550                               (and (eq_attr "type" "fdiv")
 551                                    (and (eq_attr "fp_int_src" "true")
 552                                         (eq_attr "memory" "load"))))
 553                          "znver1-double,znver1-load,znver1-fp3*19")
 554
 555 (define_insn_reservation "znver2_fp_op_idiv_load" 26
 556                          (and (eq_attr "cpu" "znver2")
 557                               (and (eq_attr "type" "fdiv")
 558                                    (and (eq_attr "fp_int_src" "true")
 559                                         (eq_attr "memory" "load"))))
 560                          "znver1-double,znver1-load,znver1-fp3*19")
 561
 562 ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
 563 (define_insn_reservation "znver1_fp_insn" 1
 564                          (and (eq_attr "cpu" "znver1,znver2")
 565                               (eq_attr "type" "mmx"))
 566                          "znver1-direct,znver1-fpu")
 567
 568 (define_insn_reservation "znver1_mmx_add" 1
 569                          (and (eq_attr "cpu" "znver1,znver2")
 570                               (and (eq_attr "type" "mmxadd")
 571                                    (eq_attr "memory" "none")))
 572                          "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
 573
 574 (define_insn_reservation "znver1_mmx_add_load" 8
 575                          (and (eq_attr "cpu" "znver1,znver2")
 576                               (and (eq_attr "type" "mmxadd")
 577                                    (eq_attr "memory" "load")))
 578                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
 579
 580 (define_insn_reservation "znver1_mmx_cmp" 1
 581                          (and (eq_attr "cpu" "znver1,znver2")
 582                               (and (eq_attr "type" "mmxcmp")
 583                                    (eq_attr "memory" "none")))
 584                          "znver1-direct,znver1-fp0|znver1-fp3")
 585
 586 (define_insn_reservation "znver1_mmx_cmp_load" 8
 587                          (and (eq_attr "cpu" "znver1,znver2")
 588                               (and (eq_attr "type" "mmxcmp")
 589                                    (eq_attr "memory" "load")))
 590                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
 591
 592 (define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1
 593                          (and (eq_attr "cpu" "znver1,znver2")
 594                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
 595                                    (eq_attr "memory" "none")))
 596                          "znver1-direct,znver1-fp1|znver1-fp2")
 597
 598 (define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8
 599                          (and (eq_attr "cpu" "znver1,znver2")
 600                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
 601                                    (eq_attr "memory" "load")))
 602                          "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
 603
 604 (define_insn_reservation "znver1_mmx_shift_move" 1
 605                          (and (eq_attr "cpu" "znver1,znver2")
 606                               (and (eq_attr "type" "mmxshft,mmxmov")
 607                                    (eq_attr "memory" "none")))
 608                          "znver1-direct,znver1-fp2")
 609
 610 (define_insn_reservation "znver1_mmx_shift_move_load" 8
 611                          (and (eq_attr "cpu" "znver1,znver2")
 612                               (and (eq_attr "type" "mmxshft,mmxmov")
 613                                    (eq_attr "memory" "load")))
 614                          "znver1-direct,znver1-load,znver1-fp2")
 615
 616 (define_insn_reservation "znver1_mmx_move_store" 1
 617                          (and (eq_attr "cpu" "znver1")
 618                               (and (eq_attr "type" "mmxshft,mmxmov")
 619                                    (eq_attr "memory" "store,both")))
 620                           "znver1-direct,znver1-fp2,znver1-store")
 621 (define_insn_reservation "znver2_mmx_move_store" 1
 622                          (and (eq_attr "cpu" "znver1")
 623                               (and (eq_attr "type" "mmxshft,mmxmov")
 624                                    (eq_attr "memory" "store,both")))
 625                           "znver1-direct,znver1-fp2,znver2-store")
 626
 627 (define_insn_reservation "znver1_mmx_mul" 3
 628                          (and (eq_attr "cpu" "znver1,znver2")
 629                               (and (eq_attr "type" "mmxmul")
 630                                    (eq_attr "memory" "none")))
 631                           "znver1-direct,znver1-fp0*3")
 632
 633 (define_insn_reservation "znver1_mmx_load" 10
 634                          (and (eq_attr "cpu" "znver1,znver2")
 635                               (and (eq_attr "type" "mmxmul")
 636                                    (eq_attr "memory" "load")))
 637                          "znver1-direct,znver1-load,znver1-fp0*3")
 638
 639 ;; TODO
 640 (define_insn_reservation "znver1_avx256_log" 1
 641                          (and (eq_attr "cpu" "znver1")
 642                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 643                                    (and (eq_attr "type" "sselog")
 644                                         (eq_attr "memory" "none"))))
 645                          "znver1-double,znver1-fpu")
 646
 647 (define_insn_reservation "znver1_avx256_log_load" 8
 648                          (and (eq_attr "cpu" "znver1")
 649                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 650                                    (and (eq_attr "type" "sselog")
 651                                         (eq_attr "memory" "load"))))
 652                          "znver1-double,znver1-load,znver1-fpu")
 653
 654 (define_insn_reservation "znver1_sse_log" 1
 655                          (and (eq_attr "cpu" "znver1,znver2")
 656                               (and (eq_attr "type" "sselog")
 657                                    (eq_attr "memory" "none")))
 658                          "znver1-direct,znver1-fpu")
 659
 660 (define_insn_reservation "znver1_sse_log_load" 8
 661                          (and (eq_attr "cpu" "znver1,znver2")
 662                               (and (eq_attr "type" "sselog")
 663                                    (eq_attr "memory" "load")))
 664                          "znver1-direct,znver1-load,znver1-fpu")
 665
 666 (define_insn_reservation "znver1_avx256_log1" 1
 667                          (and (eq_attr "cpu" "znver1")
 668                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 669                                    (and (eq_attr "type" "sselog1")
 670                                         (eq_attr "memory" "none"))))
 671                          "znver1-double,znver1-fp1|znver1-fp2")
 672
 673 (define_insn_reservation "znver1_avx256_log1_load" 8
 674                          (and (eq_attr "cpu" "znver1")
 675                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 676                                    (and (eq_attr "type" "sselog1")
 677                                         (eq_attr "memory" "!none"))))
 678                          "znver1-double,znver1-load,znver1-fp1|znver1-fp2")
 679
 680 (define_insn_reservation "znver1_sse_log1" 1
 681                          (and (eq_attr "cpu" "znver1,znver2")
 682                               (and (eq_attr "type" "sselog1")
 683                                    (eq_attr "memory" "none")))
 684                          "znver1-direct,znver1-fp1|znver1-fp2")
 685
 686 (define_insn_reservation "znver1_sse_log1_load" 8
 687                          (and (eq_attr "cpu" "znver1,znver2")
 688                               (and (eq_attr "type" "sselog1")
 689                                    (eq_attr "memory" "!none")))
 690                          "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
 691
 692 (define_insn_reservation "znver1_sse_comi" 1
 693                          (and (eq_attr "cpu" "znver1")
 694                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 695                                    (and (eq_attr "prefix" "!vex")
 696                                         (and (eq_attr "prefix_extra" "0")
 697                                              (and (eq_attr "type" "ssecomi")
 698                                                   (eq_attr "memory" "none"))))))
 699                          "znver1-direct,znver1-fp0|znver1-fp1")
 700
 701 (define_insn_reservation "znver1_sse_comi_load" 8
 702                          (and (ior (and (eq_attr "cpu" "znver1")
 703                                         (eq_attr "mode" "SF,DF,V4SF,V2DF"))
 704                                    (eq_attr "cpu" "znver2"))
 705                               (and (eq_attr "prefix_extra" "0")
 706                                    (and (eq_attr "type" "ssecomi")
 707                                         (eq_attr "memory" "load"))))
 708                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
 709
 710 (define_insn_reservation "znver1_sse_comi_double" 2
 711                          (and (ior (and (eq_attr "cpu" "znver1")
 712                                         (eq_attr "mode" "V4SF,V2DF,TI"))
 713                                    (eq_attr "cpu" "znver2"))
 714                               (and (eq_attr "prefix" "vex")
 715                                    (and (eq_attr "prefix_extra" "0")
 716                                         (and (eq_attr "type" "ssecomi")
 717                                              (eq_attr "memory" "none")))))
 718                          "znver1-double,znver1-fp0|znver1-fp1")
 719
 720 (define_insn_reservation "znver1_sse_comi_double_load" 10
 721                          (and (ior (and (eq_attr "cpu" "znver1")
 722                                         (eq_attr "mode" "V4SF,V2DF,TI"))
 723                                    (eq_attr "cpu" "znver2"))
 724                               (and (eq_attr "prefix" "vex")
 725                                    (and (eq_attr "prefix_extra" "0")
 726                                         (and (eq_attr "type" "ssecomi")
 727                                              (eq_attr "memory" "load")))))
 728                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
 729
 730 (define_insn_reservation "znver1_sse_test" 1
 731                          (and (ior (and (eq_attr "cpu" "znver1")
 732                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
 733                                    (eq_attr "cpu" "znver2"))
 734                               (and (eq_attr "prefix_extra" "1")
 735                                    (and (eq_attr "type" "ssecomi")
 736                                         (eq_attr "memory" "none"))))
 737                          "znver1-direct,znver1-fp1|znver1-fp2")
 738
 739 (define_insn_reservation "znver1_sse_test_load" 8
 740                          (and (ior (and (eq_attr "cpu" "znver1")
 741                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
 742                                    (eq_attr "cpu" "znver2"))
 743                               (and (eq_attr "prefix_extra" "1")
 744                                    (and (eq_attr "type" "ssecomi")
 745                                         (eq_attr "memory" "load"))))
 746                          "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
 747
 748 ;; SSE moves
 749 ;; Fix me:  Need to revist this again some of the moves may be restricted
 750 ;; to some fpu pipes.
 751 (define_insn_reservation "znver1_sse_mov" 2
 752                          (and (eq_attr "cpu" "znver1")
 753                               (and (eq_attr "mode" "SI")
 754                                    (and (eq_attr "isa" "avx")
 755                                         (and (eq_attr "type" "ssemov")
 756                                              (eq_attr "memory" "none")))))
 757                          "znver1-direct,znver1-ieu0")
 758
 759 (define_insn_reservation "znver2_sse_mov" 1
 760                          (and (eq_attr "cpu" "znver2")
 761                               (and (eq_attr "mode" "SI")
 762                                    (and (eq_attr "isa" "avx")
 763                                         (and (eq_attr "type" "ssemov")
 764                                              (eq_attr "memory" "none")))))
 765                          "znver1-direct,znver1-ieu0")
 766
 767 (define_insn_reservation "znver1_avx_mov" 2
 768                          (and (eq_attr "cpu" "znver1")
 769                               (and (eq_attr "mode" "TI")
 770                                    (and (eq_attr "isa" "avx")
 771                                         (and (eq_attr "type" "ssemov")
 772                                              (and (match_operand:SI 1 "register_operand")
 773                                                   (eq_attr "memory" "none"))))))
 774                          "znver1-direct,znver1-ieu2")
 775
 776 (define_insn_reservation "znver2_avx_mov" 1
 777                          (and (eq_attr "cpu" "znver2")
 778                               (and (eq_attr "mode" "TI")
 779                                    (and (eq_attr "isa" "avx")
 780                                         (and (eq_attr "type" "ssemov")
 781                                              (and (match_operand:SI 1 "register_operand")
 782                                                   (eq_attr "memory" "none"))))))
 783                          "znver1-direct,znver1-ieu2")
 784
 785 (define_insn_reservation "znver1_sseavx_mov" 1
 786                          (and (ior (and (eq_attr "cpu" "znver1")
 787                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
 788                                    (eq_attr "cpu" "znver2"))
 789                               (and (eq_attr "type" "ssemov")
 790                                    (eq_attr "memory" "none")))
 791                          "znver1-direct,znver1-fpu")
 792
 793 (define_insn_reservation "znver1_sseavx_mov_store" 1
 794                          (and (eq_attr "cpu" "znver1")
 795                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 796                                    (and (eq_attr "type" "ssemov")
 797                                         (eq_attr "memory" "store"))))
 798                         "znver1-direct,znver1-fpu,znver1-store")
 799 (define_insn_reservation "znver2_sseavx_mov_store" 1
 800                          (and (eq_attr "cpu" "znver2")
 801                               (and (eq_attr "type" "ssemov")
 802                                    (eq_attr "memory" "store")))
 803                         "znver1-direct,znver1-fpu,znver2-store")
 804
 805 (define_insn_reservation "znver1_sseavx_mov_load" 8
 806                          (and (ior (and (eq_attr "cpu" "znver1")
 807                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
 808                                    (eq_attr "cpu" "znver2"))
 809                                (and (eq_attr "type" "ssemov")
 810                                     (eq_attr "memory" "load")))
 811                          "znver1-direct,znver1-load,znver1-fpu")
 812
 813 (define_insn_reservation "znver1_avx256_mov" 1
 814                          (and (eq_attr "cpu" "znver1")
 815                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 816                                    (and (eq_attr "type" "ssemov")
 817                                         (eq_attr "memory" "none"))))
 818                          "znver1-double,znver1-fpu")
 819
 820 (define_insn_reservation "znver1_avx256_mov_store" 1
 821                          (and (eq_attr "cpu" "znver1")
 822                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 823                                    (and (eq_attr "type" "ssemov")
 824                                         (eq_attr "memory" "store"))))
 825                          "znver1-double,znver1-fpu,znver1-store")
 826
 827 (define_insn_reservation "znver1_avx256_mov_load" 8
 828                          (and (eq_attr "cpu" "znver1")
 829                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 830                                    (and (eq_attr "type" "ssemov")
 831                                         (eq_attr "memory" "load"))))
 832                          "znver1-double,znver1-load,znver1-fpu")
 833
 834 ;; SSE add
 835 (define_insn_reservation "znver1_sseavx_add" 3
 836                          (and (ior (and (eq_attr "cpu" "znver1")
 837                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
 838                                    (eq_attr "cpu" "znver2"))
 839                               (and (eq_attr "type" "sseadd")
 840                                    (eq_attr "memory" "none")))
 841                          "znver1-direct,znver1-fp2|znver1-fp3")
 842
 843 (define_insn_reservation "znver1_sseavx_add_load" 10
 844                          (and (ior (and (eq_attr "cpu" "znver1")
 845                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
 846                                    (eq_attr "cpu" "znver2"))
 847                               (and (eq_attr "type" "sseadd")
 848                                    (eq_attr "memory" "load")))
 849                          "znver1-direct,znver1-load,znver1-fp2|znver1-fp3")
 850
 851 (define_insn_reservation "znver1_avx256_add" 3
 852                          (and (eq_attr "cpu" "znver1")
 853                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 854                                    (and (eq_attr "type" "sseadd")
 855                                         (eq_attr "memory" "none"))))
 856                          "znver1-double,znver1-fp2|znver1-fp3")
 857
 858 (define_insn_reservation "znver1_avx256_add_load" 10
 859                          (and (eq_attr "cpu" "znver1")
 860                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 861                                    (and (eq_attr "type" "sseadd")
 862                                         (eq_attr "memory" "load"))))
 863                          "znver1-double,znver1-load,znver1-fp2|znver1-fp3")
 864
 865 (define_insn_reservation "znver1_sseavx_fma" 5
 866                          (and (ior (and (eq_attr "cpu" "znver1")
 867                                         (eq_attr "mode" "SF,DF,V4SF,V2DF"))
 868                                    (eq_attr "cpu" "znver2"))
 869                               (and (eq_attr "type" "ssemuladd")
 870                                    (eq_attr "memory" "none")))
 871                          "znver1-direct,znver1-fp0|znver1-fp1")
 872
 873 (define_insn_reservation "znver1_sseavx_fma_load" 12
 874                          (and (ior (and (eq_attr "cpu" "znver1")
 875                                         (eq_attr "mode" "SF,DF,V4SF,V2DF"))
 876                                    (eq_attr "cpu" "znver2"))
 877                               (and (eq_attr "type" "ssemuladd")
 878                                    (eq_attr "memory" "load")))
 879                         "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
 880
 881 (define_insn_reservation "znver1_avx256_fma" 5
 882                          (and (eq_attr "cpu" "znver1")
 883                               (and (eq_attr "mode" "V8SF,V4DF")
 884                                    (and (eq_attr "type" "ssemuladd")
 885                                         (eq_attr "memory" "none"))))
 886                          "znver1-double,znver1-fp0|znver1-fp1")
 887
 888 (define_insn_reservation "znver1_avx256_fma_load" 12
 889                          (and (eq_attr "cpu" "znver1")
 890                               (and (eq_attr "mode" "V8SF,V4DF")
 891                                    (and (eq_attr "type" "ssemuladd")
 892                                         (eq_attr "memory" "load"))))
 893                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
 894
 895 (define_insn_reservation "znver1_sseavx_iadd" 1
 896                          (and (ior (and (eq_attr "cpu" "znver1")
 897                                         (eq_attr "mode" "DI,TI"))
 898                                    (eq_attr "cpu" "znver2"))
 899                               (and (eq_attr "type" "sseiadd")
 900                                    (eq_attr "memory" "none")))
 901                          "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
 902
 903 (define_insn_reservation "znver1_sseavx_iadd_load" 8
 904                          (and (ior (and (eq_attr "cpu" "znver1")
 905                                         (eq_attr "mode" "DI,TI"))
 906                                    (eq_attr "cpu" "znver2"))
 907                               (and (eq_attr "type" "sseiadd")
 908                                    (eq_attr "memory" "load")))
 909                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
 910
 911 (define_insn_reservation "znver1_avx256_iadd" 1
 912                          (and (eq_attr "cpu" "znver1")
 913                               (and (eq_attr "mode" "OI")
 914                                    (and (eq_attr "type" "sseiadd")
 915                                         (eq_attr "memory" "none"))))
 916                          "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3")
 917
 918 (define_insn_reservation "znver1_avx256_iadd_load" 8
 919                          (and (eq_attr "cpu" "znver1")
 920                               (and (eq_attr "mode" "OI")
 921                                    (and (eq_attr "type" "sseiadd")
 922                                         (eq_attr "memory" "load"))))
 923                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
 924
 925 ;; SSE conversions.
 926 (define_insn_reservation "znver1_ssecvtsf_si_load" 12
 927                          (and (eq_attr "cpu" "znver1,znver2")
 928                               (and (eq_attr "mode" "SI")
 929                                    (and (eq_attr "type" "sseicvt")
 930                                         (and (match_operand:SF 1 "memory_operand")
 931                                              (eq_attr "memory" "load")))))
 932                          "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
 933
 934 (define_insn_reservation "znver1_ssecvtdf_si" 5
 935                          (and (eq_attr "cpu" "znver1")
 936                               (and (eq_attr "mode" "SI")
 937                                    (and (match_operand:DF 1 "register_operand")
 938                                         (and (eq_attr "type" "sseicvt")
 939                                              (eq_attr "memory" "none")))))
 940                          "znver1-double,znver1-fp3,znver1-ieu0")
 941 (define_insn_reservation "znver2_ssecvtdf_si" 4
 942                          (and (eq_attr "cpu" "znver2")
 943                               (and (eq_attr "mode" "SI")
 944                                    (and (match_operand:DF 1 "register_operand")
 945                                         (and (eq_attr "type" "sseicvt")
 946                                              (eq_attr "memory" "none")))))
 947                          "znver1-double,znver1-fp3,znver1-ieu0")
 948
 949 (define_insn_reservation "znver1_ssecvtdf_si_load" 12
 950                          (and (eq_attr "cpu" "znver1")
 951                               (and (eq_attr "mode" "SI")
 952                                    (and (eq_attr "type" "sseicvt")
 953                                         (and (match_operand:DF 1 "memory_operand")
 954                                              (eq_attr "memory" "load")))))
 955                          "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
 956
 957 (define_insn_reservation "znver2_ssecvtdf_si_load" 11
 958                          (and (eq_attr "cpu" "znver2")
 959                               (and (eq_attr "mode" "SI")
 960                                    (and (eq_attr "type" "sseicvt")
 961                                         (and (match_operand:DF 1 "memory_operand")
 962                                              (eq_attr "memory" "load")))))
 963                          "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
 964
 965 ;; All other used ssecvt fp3 pipes
 966 ;; Check: Need to revisit this again.
 967 ;; Some SSE converts may use different pipe combinations.
 968 (define_insn_reservation "znver1_ssecvt" 4
 969                          (and (eq_attr "cpu" "znver1")
 970                               (and (eq_attr "type" "ssecvt")
 971                                    (eq_attr "memory" "none")))
 972                          "znver1-direct,znver1-fp3")
 973
 974 (define_insn_reservation "znver2_ssecvt" 3
 975                          (and (eq_attr "cpu" "znver2")
 976                               (and (eq_attr "type" "ssecvt")
 977                                    (eq_attr "memory" "none")))
 978                          "znver1-direct,znver1-fp3")
 979
 980 (define_insn_reservation "znver1_ssecvt_load" 11
 981                          (and (eq_attr "cpu" "znver1")
 982                               (and (eq_attr "type" "ssecvt")
 983                                    (eq_attr "memory" "load")))
 984                          "znver1-direct,znver1-load,znver1-fp3")
 985
 986 (define_insn_reservation "znver2_ssecvt_load" 11
 987                          (and (eq_attr "cpu" "znver2")
 988                               (and (eq_attr "type" "ssecvt")
 989                                    (eq_attr "memory" "load")))
 990                          "znver1-direct,znver1-load,znver1-fp3")
 991
 992 ;; SSE div
 993 (define_insn_reservation "znver1_ssediv_ss_ps" 10
 994                          (and (ior (and (eq_attr "cpu" "znver1")
 995                                         (eq_attr "mode" "V4SF,SF"))
 996                                    (and (eq_attr "cpu" "znver2")
 997                                         (eq_attr "mode" "V8SF,V4SF,SF")))
 998                               (and (eq_attr "type" "ssediv")
 999                                    (eq_attr "memory" "none")))
1000                          "znver1-direct,znver1-fp3*10")
1001
1002 (define_insn_reservation "znver1_ssediv_ss_ps_load" 17
1003                          (and (ior (and (eq_attr "cpu" "znver1")
1004                                         (eq_attr "mode" "V4SF,SF"))
1005                                    (and (eq_attr "cpu" "znver2")
1006                                         (eq_attr "mode" "V8SF,V4SF,SF")))
1007                               (and (eq_attr "type" "ssediv")
1008                                    (eq_attr "memory" "load")))
1009                          "znver1-direct,znver1-load,znver1-fp3*10")
1010
1011 (define_insn_reservation "znver1_ssediv_sd_pd" 13
1012                          (and (ior (and (eq_attr "cpu" "znver1")
1013                                         (eq_attr "mode" "V2DF,DF"))
1014                                    (and (eq_attr "cpu" "znver2")
1015                                         (eq_attr "mode" "V4DF,V2DF,DF")))
1016                               (and (eq_attr "type" "ssediv")
1017                                    (eq_attr "memory" "none")))
1018                          "znver1-direct,znver1-fp3*13")
1019
1020 (define_insn_reservation "znver1_ssediv_sd_pd_load" 20
1021                          (and (ior (and (eq_attr "cpu" "znver1")
1022                                         (eq_attr "mode" "V2DF,DF"))
1023                                    (and (eq_attr "cpu" "znver2")
1024                                         (eq_attr "mode" "V4DF,V2DF,DF")))
1025                               (and (eq_attr "type" "ssediv")
1026                                    (eq_attr "memory" "load")))
1027                          "znver1-direct,znver1-load,znver1-fp3*13")
1028
1029 (define_insn_reservation "znver1_ssediv_avx256_ps" 12
1030                          (and (eq_attr "cpu" "znver1")
1031                               (and (eq_attr "mode" "V8SF")
1032                                    (and (eq_attr "memory" "none")
1033                                         (eq_attr "type" "ssediv"))))
1034                          "znver1-double,znver1-fp3*12")
1035
1036 (define_insn_reservation "znver1_ssediv_avx256_ps_load" 19
1037                          (and (eq_attr "cpu" "znver1")
1038                               (and (eq_attr "mode" "V8SF")
1039                                    (and (eq_attr "type" "ssediv")
1040                                         (eq_attr "memory" "load"))))
1041                          "znver1-double,znver1-load,znver1-fp3*12")
1042
1043 (define_insn_reservation "znver1_ssediv_avx256_pd" 15
1044                          (and (eq_attr "cpu" "znver1")
1045                               (and (eq_attr "mode" "V4DF")
1046                                    (and (eq_attr "type" "ssediv")
1047                                         (eq_attr "memory" "none"))))
1048                          "znver1-double,znver1-fp3*15")
1049
1050 (define_insn_reservation "znver1_ssediv_avx256_pd_load" 22
1051                          (and (eq_attr "cpu" "znver1")
1052                               (and (eq_attr "mode" "V4DF")
1053                                    (and (eq_attr "type" "ssediv")
1054                                         (eq_attr "memory" "load"))))
1055                          "znver1-double,znver1-load,znver1-fp3*15")
1056 ;; SSE MUL
1057 (define_insn_reservation "znver1_ssemul_ss_ps" 3
1058                          (and (ior (and (eq_attr "cpu" "znver1")
1059                                         (eq_attr "mode" "V4SF,SF"))
1060                                    (and (eq_attr "cpu" "znver2")
1061                                         (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF")))
1062                               (and (eq_attr "type" "ssemul")
1063                                    (eq_attr "memory" "none")))
1064                          "znver1-direct,(znver1-fp0|znver1-fp1)*3")
1065
1066 (define_insn_reservation "znver1_ssemul_ss_ps_load" 10
1067                          (and (ior (and (eq_attr "cpu" "znver1")
1068                                         (eq_attr "mode" "V4SF,SF"))
1069                                    (and (eq_attr "cpu" "znver2")
1070                                         (eq_attr "mode" "V8SF,V4SF,SF")))
1071                               (and (eq_attr "type" "ssemul")
1072                                    (eq_attr "memory" "load")))
1073                          "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
1074
1075 (define_insn_reservation "znver1_ssemul_avx256_ps" 3
1076                          (and (eq_attr "cpu" "znver1")
1077                               (and (eq_attr "mode" "V8SF")
1078                                    (and (eq_attr "type" "ssemul")
1079                                         (eq_attr "memory" "none"))))
1080                          "znver1-double,(znver1-fp0|znver1-fp1)*3")
1081
1082 (define_insn_reservation "znver1_ssemul_avx256_ps_load" 10
1083                          (and (eq_attr "cpu" "znver1")
1084                               (and (eq_attr "mode" "V8SF")
1085                                    (and (eq_attr "type" "ssemul")
1086                                         (eq_attr "memory" "load"))))
1087                          "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3")
1088
1089 (define_insn_reservation "znver1_ssemul_sd_pd" 4
1090                          (and (eq_attr "cpu" "znver1")
1091                               (and (eq_attr "mode" "V2DF,DF")
1092                                    (and (eq_attr "type" "ssemul")
1093                                         (eq_attr "memory" "none"))))
1094                          "znver1-direct,(znver1-fp0|znver1-fp1)*4")
1095
1096 (define_insn_reservation "znver1_ssemul_sd_pd_load" 11
1097                          (and (eq_attr "cpu" "znver1")
1098                               (and (eq_attr "mode" "V2DF,DF")
1099                                    (and (eq_attr "type" "ssemul")
1100                                         (eq_attr "memory" "load"))))
1101                          "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4")
1102
1103 (define_insn_reservation "znver2_ssemul_sd_pd" 3
1104                          (and (eq_attr "cpu" "znver2")
1105                               (and (eq_attr "type" "ssemul")
1106                                    (eq_attr "memory" "none")))
1107                          "znver1-direct,(znver1-fp0|znver1-fp1)*3")
1108
1109 (define_insn_reservation "znver2_ssemul_sd_pd_load" 10
1110                          (and (eq_attr "cpu" "znver2")
1111                               (and (eq_attr "type" "ssemul")
1112                                    (eq_attr "memory" "load")))
1113                          "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
1114
1115 (define_insn_reservation "znver1_ssemul_avx256_pd" 5
1116                          (and (eq_attr "cpu" "znver1")
1117                               (and (eq_attr "mode" "V4DF")
1118                                    (and (eq_attr "type" "ssemul")
1119                                         (eq_attr "memory" "none"))))
1120                          "znver1-double,(znver1-fp0|znver1-fp1)*4")
1121
1122 (define_insn_reservation "znver1_ssemul_avx256_pd_load" 12
1123                          (and (eq_attr "cpu" "znver1")
1124                               (and (eq_attr "mode" "V4DF")
1125                                    (and (eq_attr "type" "ssemul")
1126                                         (eq_attr "memory" "load"))))
1127                          "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4")
1128
1129 ;;SSE imul
1130 (define_insn_reservation "znver1_sseimul" 3
1131                          (and (ior (and (eq_attr "cpu" "znver1")
1132                                         (eq_attr "mode" "TI"))
1133                                    (and (eq_attr "cpu" "znver2")
1134                                         (eq_attr "mode" "TI,OI")))
1135                               (and (eq_attr "type" "sseimul")
1136                                    (eq_attr "memory" "none")))
1137                          "znver1-direct,znver1-fp0*3")
1138
1139 (define_insn_reservation "znver1_sseimul_avx256" 4
1140                          (and (eq_attr "cpu" "znver1,znver2")
1141                               (and (eq_attr "mode" "OI")
1142                                    (and (eq_attr "type" "sseimul")
1143                                         (eq_attr "memory" "none"))))
1144                          "znver1-double,znver1-fp0*4")
1145
1146 (define_insn_reservation "znver1_sseimul_load" 10
1147                          (and (ior (and (eq_attr "cpu" "znver1")
1148                                         (eq_attr "mode" "TI"))
1149                                    (and (eq_attr "cpu" "znver2")
1150                                         (eq_attr "mode" "TI,OI")))
1151                               (and (eq_attr "type" "sseimul")
1152                                    (eq_attr "memory" "load")))
1153                          "znver1-direct,znver1-load,znver1-fp0*3")
1154
1155 (define_insn_reservation "znver1_sseimul_avx256_load" 11
1156                          (and (eq_attr "cpu" "znver1,znver2")
1157                               (and (eq_attr "mode" "OI")
1158                                    (and (eq_attr "type" "sseimul")
1159                                         (eq_attr "memory" "load"))))
1160                          "znver1-double,znver1-load,znver1-fp0*4")
1161
1162 (define_insn_reservation "znver1_sseimul_di" 3
1163                          (and (eq_attr "cpu" "znver1,znver2")
1164                               (and (eq_attr "mode" "DI")
1165                                    (and (eq_attr "memory" "none")
1166                                         (eq_attr "type" "sseimul"))))
1167                          "znver1-direct,znver1-fp0*3")
1168
1169 (define_insn_reservation "znver1_sseimul_load_di" 10
1170                          (and (eq_attr "cpu" "znver1,znver2")
1171                               (and (eq_attr "mode" "DI")
1172                                    (and (eq_attr "type" "sseimul")
1173                                         (eq_attr "memory" "load"))))
1174                          "znver1-direct,znver1-load,znver1-fp0*3")
1175
1176 ;; SSE compares
1177 (define_insn_reservation "znver1_sse_cmp" 1
1178                          (and (ior (and (eq_attr "cpu" "znver1")
1179                                         (eq_attr "mode" "SF,DF,V4SF,V2DF"))
1180                                    (and (eq_attr "cpu" "znver2")
1181                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF")))
1182                                (and (eq_attr "type" "ssecmp")
1183                                     (eq_attr "memory" "none")))
1184                          "znver1-direct,znver1-fp0|znver1-fp1")
1185
1186 (define_insn_reservation "znver1_sse_cmp_load" 8
1187                          (and (ior (and (eq_attr "cpu" "znver1")
1188                                         (eq_attr "mode" "SF,DF,V4SF,V2DF"))
1189                                    (and (eq_attr "cpu" "znver2")
1190                                         (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF")))
1191                               (and (eq_attr "type" "ssecmp")
1192                                    (eq_attr "memory" "load")))
1193                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
1194
1195 (define_insn_reservation "znver1_sse_cmp_avx256" 1
1196                          (and (eq_attr "cpu" "znver1")
1197                               (and (eq_attr "mode" "V8SF,V4DF")
1198                                    (and (eq_attr "type" "ssecmp")
1199                                         (eq_attr "memory" "none"))))
1200                         "znver1-double,znver1-fp0|znver1-fp1")
1201
1202 (define_insn_reservation "znver1_sse_cmp_avx256_load" 8
1203                          (and (eq_attr "cpu" "znver1")
1204                               (and (eq_attr "mode" "V8SF,V4DF")
1205                                    (and (eq_attr "type" "ssecmp")
1206                                         (eq_attr "memory" "load"))))
1207                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
1208
1209 (define_insn_reservation "znver1_sse_icmp" 1
1210                          (and (ior (and (eq_attr "cpu" "znver1")
1211                                         (eq_attr "mode" "QI,HI,SI,DI,TI"))
1212                                    (and (eq_attr "cpu" "znver2")
1213                                         (eq_attr "mode" "QI,HI,SI,DI,TI,OI")))
1214                               (and (eq_attr "type" "ssecmp")
1215                                    (eq_attr "memory" "none")))
1216                          "znver1-direct,znver1-fp0|znver1-fp3")
1217
1218 (define_insn_reservation "znver1_sse_icmp_load" 8
1219                          (and (ior (and (eq_attr "cpu" "znver1")
1220                                         (eq_attr "mode" "QI,HI,SI,DI,TI"))
1221                                    (and (eq_attr "cpu" "znver2")
1222                                         (eq_attr "mode" "QI,HI,SI,DI,TI,OI")))
1223                               (and (eq_attr "type" "ssecmp")
1224                                    (eq_attr "memory" "load")))
1225                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
1226
1227 (define_insn_reservation "znver1_sse_icmp_avx256" 1
1228                          (and (eq_attr "cpu" "znver1")
1229                               (and (eq_attr "mode" "OI")
1230                                    (and (eq_attr "type" "ssecmp")
1231                                         (eq_attr "memory" "none"))))
1232                          "znver1-double,znver1-fp0|znver1-fp3")
1233
1234 (define_insn_reservation "znver1_sse_icmp_avx256_load" 8
1235                          (and (eq_attr "cpu" "znver1")
1236                               (and (eq_attr "mode" "OI")
1237                                    (and (eq_attr "type" "ssecmp")
1238                                         (eq_attr "memory" "load"))))
1239                          "znver1-double,znver1-load,znver1-fp0|znver1-fp3")