1 /* Subroutines for insn-output.c for Intel 860
2 Copyright (C) 1989, 1991 Free Software Foundation, Inc.
5 Written by Richard Stallman (rms@ai.mit.edu).
7 Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater
8 to the whims of the System V Release 4 assembler.
10 This file is part of GNU CC.
12 GNU CC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GNU CC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GNU CC; see the file COPYING. If not, write to
24 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
38 #include "insn-attr.h"
42 static rtx
find_addr_reg ();
44 #ifndef I860_REG_PREFIX
45 #define I860_REG_PREFIX ""
48 char *i860_reg_prefix
= I860_REG_PREFIX
;
50 /* Save information from a "cmpxx" operation until the branch is emitted. */
52 rtx i860_compare_op0
, i860_compare_op1
;
54 /* Return non-zero if this pattern, can be evaluated safely, even if it
57 safe_insn_src_p (op
, mode
)
59 enum machine_mode mode
;
61 /* Just experimenting. */
63 /* No floating point src is safe if it contains an arithmetic
64 operation, since that operation may trap. */
65 switch (GET_CODE (op
))
77 return CONSTANT_ADDRESS_P (XEXP (op
, 0));
79 /* We never need to negate or complement constants. */
81 return (mode
!= SFmode
&& mode
!= DFmode
);
98 return (mode
!= SFmode
&& mode
!= DFmode
);
106 if ((GET_CODE (XEXP (op
, 0)) == CONST_INT
&& ! SMALL_INT (XEXP (op
, 0)))
107 || (GET_CODE (XEXP (op
, 1)) == CONST_INT
&& ! SMALL_INT (XEXP (op
, 1))))
116 /* Return 1 if REG is clobbered in IN.
117 Return 2 if REG is used in IN.
118 Return 3 if REG is both used and clobbered in IN.
119 Return 0 if neither. */
122 reg_clobbered_p (reg
, in
)
126 register enum rtx_code code
;
131 code
= GET_CODE (in
);
133 if (code
== SET
|| code
== CLOBBER
)
135 rtx dest
= SET_DEST (in
);
139 while (GET_CODE (dest
) == STRICT_LOW_PART
140 || GET_CODE (dest
) == SUBREG
141 || GET_CODE (dest
) == SIGN_EXTRACT
142 || GET_CODE (dest
) == ZERO_EXTRACT
)
143 dest
= XEXP (dest
, 0);
147 else if (GET_CODE (dest
) == REG
148 && refers_to_regno_p (REGNO (reg
),
149 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
153 /* Anything that sets just part of the register
154 is considered using as well as setting it.
155 But note that a straight SUBREG of a single-word value
156 clobbers the entire value. */
157 if (dest
!= SET_DEST (in
)
158 && ! (GET_CODE (SET_DEST (in
)) == SUBREG
159 || UNITS_PER_WORD
>= GET_MODE_SIZE (GET_MODE (dest
))))
166 used
= refers_to_regno_p (REGNO (reg
),
167 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
170 used
= refers_to_regno_p (REGNO (reg
),
171 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
175 return set
+ used
* 2;
178 if (refers_to_regno_p (REGNO (reg
),
179 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
185 /* Return non-zero if OP can be written to without screwing up
186 GCC's model of what's going on. It is assumed that this operand
187 appears in the dest position of a SET insn in a conditional
188 branch's delay slot. AFTER is the label to start looking from. */
190 operand_clobbered_before_used_after (op
, after
)
194 /* Just experimenting. */
195 if (GET_CODE (op
) == CC0
)
197 if (GET_CODE (op
) == REG
)
201 if (op
== stack_pointer_rtx
)
204 /* Scan forward from the label, to see if the value of OP
205 is clobbered before the first use. */
207 for (insn
= NEXT_INSN (after
); insn
; insn
= NEXT_INSN (insn
))
209 if (GET_CODE (insn
) == NOTE
)
211 if (GET_CODE (insn
) == INSN
212 || GET_CODE (insn
) == JUMP_INSN
213 || GET_CODE (insn
) == CALL_INSN
)
215 switch (reg_clobbered_p (op
, PATTERN (insn
)))
225 /* If we reach another label without clobbering OP,
226 then we cannot safely write it here. */
227 else if (GET_CODE (insn
) == CODE_LABEL
)
229 if (GET_CODE (insn
) == JUMP_INSN
)
231 if (condjump_p (insn
))
233 /* This is a jump insn which has already
234 been mangled. We can't tell what it does. */
235 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
237 if (! JUMP_LABEL (insn
))
239 /* Keep following jumps. */
240 insn
= JUMP_LABEL (insn
);
246 /* In both of these cases, the first insn executed
247 for this op will be a orh whatever%h,%?r0,%?r31,
248 which is tolerable. */
249 if (GET_CODE (op
) == MEM
)
250 return (CONSTANT_ADDRESS_P (XEXP (op
, 0)));
255 /* Return non-zero if this pattern, as a source to a "SET",
256 is known to yield an instruction of unit size. */
258 single_insn_src_p (op
, mode
)
260 enum machine_mode mode
;
262 switch (GET_CODE (op
))
265 /* This is not always a single insn src, technically,
266 but output_delayed_branch knows how to deal with it. */
271 /* This is not a single insn src, technically,
272 but output_delayed_branch knows how to deal with it. */
281 /* We never need to negate or complement constants. */
283 return (mode
!= DFmode
);
290 /* Detect cases that require multiple instructions. */
291 if (CONSTANT_P (XEXP (op
, 1))
292 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
293 && SMALL_INT (XEXP (op
, 1))))
305 /* Not doing floating point, since they probably
306 take longer than the branch slot they might fill. */
307 return (mode
!= SFmode
&& mode
!= DFmode
);
310 if (GET_CODE (XEXP (op
, 1)) == NOT
)
312 rtx arg
= XEXP (XEXP (op
, 1), 0);
314 && !(GET_CODE (arg
) == CONST_INT
316 || INTVAL (arg
) & 0xffff == 0)))
321 /* Both small and round numbers take one instruction;
323 if (CONSTANT_P (XEXP (op
, 1))
324 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
325 && (SMALL_INT (XEXP (op
, 1))
326 || INTVAL (XEXP (op
, 1)) & 0xffff == 0)))
336 if (SUBREG_WORD (op
) != 0)
338 return single_insn_src_p (SUBREG_REG (op
), mode
);
340 /* Not doing floating point, since they probably
341 take longer than the branch slot they might fill. */
355 /* Nonzero only if this *really* is a single insn operand. */
357 strict_single_insn_op_p (op
, mode
)
359 enum machine_mode mode
;
361 if (mode
== VOIDmode
)
362 mode
= GET_MODE (op
);
364 switch (GET_CODE (op
))
372 /* We can put this set insn into delay slot, because this is one
374 if ((INTVAL (op
) & 0xffff) == 0)
383 /* This loses when moving an freg to a general reg. */
384 return HARD_REGNO_NREGS (REGNO (op
), mode
) == 1;
386 return (mode
!= DFmode
&& mode
!= DImode
);
389 if (! CONSTANT_ADDRESS_P (XEXP (op
, 0)))
390 return (mode
!= DFmode
&& mode
!= DImode
);
393 /* We never need to negate or complement constants. */
395 return (mode
!= DFmode
);
402 /* Detect cases that require multiple instructions. */
403 if (CONSTANT_P (XEXP (op
, 1))
404 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
405 && SMALL_INT (XEXP (op
, 1))))
420 if (GET_CODE (XEXP (op
, 1)) == NOT
)
422 rtx arg
= XEXP (XEXP (op
, 1), 0);
424 && !(GET_CODE (arg
) == CONST_INT
426 || INTVAL (arg
) & 0xffff == 0)))
431 /* Both small and round numbers take one instruction;
433 if (CONSTANT_P (XEXP (op
, 1))
434 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
435 && (SMALL_INT (XEXP (op
, 1))
436 || INTVAL (XEXP (op
, 1)) & 0xffff == 0)))
446 if (SUBREG_WORD (op
) != 0)
448 return strict_single_insn_op_p (SUBREG_REG (op
), mode
);
451 if (GET_CODE (XEXP (op
, 0)) == MEM
452 && ! CONSTANT_ADDRESS_P (XEXP (XEXP (op
, 0), 0)))
456 /* Not doing floating point, since they probably
457 take longer than the branch slot they might fill. */
471 /* Return truth value of whether OP is a relational operator. */
475 enum machine_mode mode
;
477 switch (GET_CODE (op
))
494 /* Return non-zero only if OP is a register of mode MODE,
497 reg_or_0_operand (op
, mode
)
499 enum machine_mode mode
;
501 return (op
== const0_rtx
|| register_operand (op
, mode
)
502 || op
== CONST0_RTX (mode
));
505 /* Return truth value of whether OP can be used as an operands in a three
506 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
509 arith_operand (op
, mode
)
511 enum machine_mode mode
;
513 return (register_operand (op
, mode
)
514 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
517 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
520 logic_operand (op
, mode
)
522 enum machine_mode mode
;
524 return (register_operand (op
, mode
)
525 || (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
)));
528 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
531 shift_operand (op
, mode
)
533 enum machine_mode mode
;
535 return (register_operand (op
, mode
)
536 || (GET_CODE (op
) == CONST_INT
));
539 /* Return 1 if OP is a valid first operand for either a logical insn
540 or an add insn of mode MODE. */
543 compare_operand (op
, mode
)
545 enum machine_mode mode
;
547 return (register_operand (op
, mode
)
548 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
) && LOGIC_INT (op
)));
551 /* Return truth value of whether OP can be used as the 5-bit immediate
552 operand of a bte or btne insn. */
555 bte_operand (op
, mode
)
557 enum machine_mode mode
;
559 return (register_operand (op
, mode
)
560 || (GET_CODE (op
) == CONST_INT
561 && (unsigned) INTVAL (op
) < 0x20));
564 /* Return 1 if OP is an indexed memory reference of mode MODE. */
567 indexed_operand (op
, mode
)
569 enum machine_mode mode
;
571 return (GET_CODE (op
) == MEM
&& GET_MODE (op
) == mode
572 && GET_CODE (XEXP (op
, 0)) == PLUS
573 && GET_MODE (XEXP (op
, 0)) == SImode
574 && register_operand (XEXP (XEXP (op
, 0), 0), SImode
)
575 && register_operand (XEXP (XEXP (op
, 0), 1), SImode
));
578 /* Return 1 if OP is a suitable source operand for a load insn
582 load_operand (op
, mode
)
584 enum machine_mode mode
;
586 return (memory_operand (op
, mode
) || indexed_operand (op
, mode
));
589 /* Return truth value of whether OP is a integer which fits the
590 range constraining immediate operands in add/subtract insns. */
595 enum machine_mode mode
;
597 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
600 /* Return truth value of whether OP is a integer which fits the
601 range constraining immediate operands in logic insns. */
606 enum machine_mode mode
;
608 return (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
));
611 /* Return the best assembler insn template
612 for moving operands[1] into operands[0] as a fullword. */
615 singlemove_string (operands
)
618 if (GET_CODE (operands
[0]) == MEM
)
620 if (GET_CODE (operands
[1]) != MEM
)
621 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
623 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
624 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
625 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
628 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
630 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
631 cc_status
.mdep
= XEXP (operands
[0], 0);
632 return "st.l %r1,%L0(%?r31)";
635 return "st.l %r1,%0";
642 cc_status
.flags
&= ~CC_F0_IS_0
;
643 xoperands
[0] = gen_rtx (REG
, SFmode
, 32);
644 xoperands
[1] = operands
[1];
645 output_asm_insn (singlemove_string (xoperands
), xoperands
);
646 xoperands
[1] = xoperands
[0];
647 xoperands
[0] = operands
[0];
648 output_asm_insn (singlemove_string (xoperands
), xoperands
);
653 if (GET_CODE (operands
[1]) == MEM
)
655 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
657 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
658 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
659 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
662 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
664 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
665 cc_status
.mdep
= XEXP (operands
[1], 0);
666 return "ld.l %L1(%?r31),%0";
668 return "ld.l %m1,%0";
670 if (GET_CODE (operands
[1]) == CONST_INT
)
672 if((INTVAL (operands
[1]) & 0xffff0000) == 0)
673 return "or %L1,%?r0,%0";
674 if((INTVAL (operands
[1]) & 0x0000ffff) == 0)
675 return "orh %H1,%?r0,%0";
676 if (operands
[1] == const0_rtx
)
677 return "mov %?r0,%0";
682 /* Output assembler code to perform a doubleword move insn
683 with operands OPERANDS. */
686 output_move_double (operands
)
689 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
691 rtx addreg0
= 0, addreg1
= 0;
693 /* First classify both operands. */
695 if (REG_P (operands
[0]))
697 else if (offsettable_memref_p (operands
[0]))
699 else if (GET_CODE (operands
[0]) == MEM
)
704 if (REG_P (operands
[1]))
706 else if (CONSTANT_P (operands
[1]))
708 else if (offsettable_memref_p (operands
[1]))
710 else if (GET_CODE (operands
[1]) == MEM
)
715 /* Check for the cases that the operand constraints are not
716 supposed to allow to happen. Abort if we get one,
717 because generating code for these cases is painful. */
719 if (optype0
== RNDOP
|| optype1
== RNDOP
)
722 /* If an operand is an unoffsettable memory ref, find a register
723 we can increment temporarily to make it refer to the second word. */
725 if (optype0
== MEMOP
)
726 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
728 if (optype1
== MEMOP
)
729 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
731 /* ??? Perhaps in some cases move double words
732 if there is a spare pair of floating regs. */
734 /* Ok, we can do one word at a time.
735 Normally we do the low-numbered word first,
736 but if either operand is autodecrementing then we
737 do the high-numbered word first.
739 In either case, set up in LATEHALF the operands to use
740 for the high-numbered word and in some cases alter the
741 operands in OPERANDS to be suitable for the low-numbered word. */
743 if (optype0
== REGOP
)
744 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
745 else if (optype0
== OFFSOP
)
746 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
748 latehalf
[0] = operands
[0];
750 if (optype1
== REGOP
)
751 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
752 else if (optype1
== OFFSOP
)
753 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
754 else if (optype1
== CNSTOP
)
756 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
757 split_double (operands
[1], &operands
[1], &latehalf
[1]);
758 else if (CONSTANT_P (operands
[1]))
759 latehalf
[1] = const0_rtx
;
762 latehalf
[1] = operands
[1];
764 /* If the first move would clobber the source of the second one,
765 do them in the other order.
767 RMS says "This happens only for registers;
768 such overlap can't happen in memory unless the user explicitly
769 sets it up, and that is an undefined circumstance."
771 but it happens on the sparc when loading parameter registers,
772 so I am going to define that circumstance, and make it work
775 if (optype0
== REGOP
&& optype1
== REGOP
776 && REGNO (operands
[0]) == REGNO (latehalf
[1]))
778 CC_STATUS_PARTIAL_INIT
;
779 /* Make any unoffsettable addresses point at high-numbered word. */
781 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
783 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
786 output_asm_insn (singlemove_string (latehalf
), latehalf
);
788 /* Undo the adds we just did. */
790 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
792 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
794 /* Do low-numbered word. */
795 return singlemove_string (operands
);
797 else if (optype0
== REGOP
&& optype1
!= REGOP
798 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
800 /* Do the late half first. */
801 output_asm_insn (singlemove_string (latehalf
), latehalf
);
803 return singlemove_string (operands
);
806 /* Normal case: do the two words, low-numbered first. */
808 output_asm_insn (singlemove_string (operands
), operands
);
810 CC_STATUS_PARTIAL_INIT
;
811 /* Make any unoffsettable addresses point at high-numbered word. */
813 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
815 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
818 output_asm_insn (singlemove_string (latehalf
), latehalf
);
820 /* Undo the adds we just did. */
822 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
824 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
830 output_fp_move_double (operands
)
833 /* If the source operand is any sort of zero, use f0 instead. */
835 if (operands
[1] == CONST0_RTX (GET_MODE (operands
[1])))
836 operands
[1] = gen_rtx (REG
, DFmode
, F0_REGNUM
);
838 if (FP_REG_P (operands
[0]))
840 if (FP_REG_P (operands
[1]))
841 return "fmov.dd %1,%0";
842 if (GET_CODE (operands
[1]) == REG
)
844 output_asm_insn ("ixfr %1,%0", operands
);
845 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
846 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
849 if (operands
[1] == CONST0_RTX (DFmode
))
850 return "fmov.dd f0,%0";
851 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
853 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
854 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
855 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
858 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
860 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
861 cc_status
.mdep
= XEXP (operands
[1], 0);
862 return "fld.d %L1(%?r31),%0";
864 return "fld.d %1,%0";
866 else if (FP_REG_P (operands
[1]))
868 if (GET_CODE (operands
[0]) == REG
)
870 output_asm_insn ("fxfr %1,%0", operands
);
871 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
872 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
875 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
877 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
878 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
879 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
882 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
884 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
885 cc_status
.mdep
= XEXP (operands
[0], 0);
886 return "fst.d %1,%L0(%?r31)";
888 return "fst.d %1,%0";
896 /* Return a REG that occurs in ADDR with coefficient 1.
897 ADDR can be effectively incremented by incrementing REG. */
903 while (GET_CODE (addr
) == PLUS
)
905 if (GET_CODE (XEXP (addr
, 0)) == REG
)
906 addr
= XEXP (addr
, 0);
907 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
908 addr
= XEXP (addr
, 1);
909 else if (CONSTANT_P (XEXP (addr
, 0)))
910 addr
= XEXP (addr
, 1);
911 else if (CONSTANT_P (XEXP (addr
, 1)))
912 addr
= XEXP (addr
, 0);
916 if (GET_CODE (addr
) == REG
)
923 /* Return a template for a load instruction with mode MODE and
924 arguments from the string ARGS.
926 This string is in static storage. */
929 load_opcode (mode
, args
, reg
)
930 enum machine_mode mode
;
966 sprintf (buf
, "%s %s", opcode
, args
);
970 /* Return a template for a store instruction with mode MODE and
971 arguments from the string ARGS.
973 This string is in static storage. */
976 store_opcode (mode
, args
, reg
)
977 enum machine_mode mode
;
1003 if (!FP_REG_P (reg
))
1013 sprintf (buf
, "%s %s", opcode
, args
);
1017 /* Output a store-in-memory whose operands are OPERANDS[0,1].
1018 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
1020 This function returns a template for an insn.
1021 This is in static storage.
1023 It may also output some insns directly.
1024 It may alter the values of operands[0] and operands[1]. */
1027 output_store (operands
)
1030 enum machine_mode mode
= GET_MODE (operands
[0]);
1031 rtx address
= XEXP (operands
[0], 0);
1034 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
1035 cc_status
.mdep
= address
;
1037 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1038 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1039 && address
== cc_prev_status
.mdep
))
1042 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
1043 cc_prev_status
.mdep
= address
;
1046 /* Store zero in two parts when appropriate. */
1047 if (mode
== DFmode
&& operands
[1] == CONST0_RTX (DFmode
))
1048 return store_opcode (DFmode
, "%r1,%L0(%?r31)", operands
[1]);
1050 /* Code below isn't smart enough to move a doubleword in two parts,
1051 so use output_move_double to do that in the cases that require it. */
1052 if ((mode
== DImode
|| mode
== DFmode
)
1053 && ! FP_REG_P (operands
[1]))
1054 return output_move_double (operands
);
1056 return store_opcode (mode
, "%r1,%L0(%?r31)", operands
[1]);
1059 /* Output a load-from-memory whose operands are OPERANDS[0,1].
1060 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
1062 This function returns a template for an insn.
1063 This is in static storage.
1065 It may also output some insns directly.
1066 It may alter the values of operands[0] and operands[1]. */
1069 output_load (operands
)
1072 enum machine_mode mode
= GET_MODE (operands
[0]);
1073 rtx address
= XEXP (operands
[1], 0);
1075 /* We don't bother trying to see if we know %hi(address).
1076 This is because we are doing a load, and if we know the
1077 %hi value, we probably also know that value in memory. */
1078 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
1079 cc_status
.mdep
= address
;
1081 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1082 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1083 && address
== cc_prev_status
.mdep
1084 && cc_prev_status
.mdep
== cc_status
.mdep
))
1087 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
1088 cc_prev_status
.mdep
= address
;
1091 /* Code below isn't smart enough to move a doubleword in two parts,
1092 so use output_move_double to do that in the cases that require it. */
1093 if ((mode
== DImode
|| mode
== DFmode
)
1094 && ! FP_REG_P (operands
[0]))
1095 return output_move_double (operands
);
1097 return load_opcode (mode
, "%L1(%?r31),%0", operands
[0]);
1101 /* Load the address specified by OPERANDS[3] into the register
1102 specified by OPERANDS[0].
1104 OPERANDS[3] may be the result of a sum, hence it could either be:
1109 (3) REG + REG + CONST_INT
1110 (4) REG + REG (special case of 3).
1112 Note that (3) is not a legitimate address.
1113 All cases are handled here. */
1116 output_load_address (operands
)
1121 if (CONSTANT_P (operands
[3]))
1123 output_asm_insn ("mov %3,%0", operands
);
1127 if (REG_P (operands
[3]))
1129 if (REGNO (operands
[0]) != REGNO (operands
[3]))
1130 output_asm_insn ("shl %?r0,%3,%0", operands
);
1134 if (GET_CODE (operands
[3]) != PLUS
)
1137 base
= XEXP (operands
[3], 0);
1138 offset
= XEXP (operands
[3], 1);
1140 if (GET_CODE (base
) == CONST_INT
)
1147 if (GET_CODE (offset
) != CONST_INT
)
1149 /* Operand is (PLUS (REG) (REG)). */
1151 offset
= const0_rtx
;
1157 operands
[7] = offset
;
1158 CC_STATUS_PARTIAL_INIT
;
1159 if (SMALL_INT (offset
))
1160 output_asm_insn ("adds %7,%6,%0", operands
);
1162 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands
);
1164 else if (GET_CODE (base
) == PLUS
)
1166 operands
[6] = XEXP (base
, 0);
1167 operands
[7] = XEXP (base
, 1);
1168 operands
[8] = offset
;
1170 CC_STATUS_PARTIAL_INIT
;
1171 if (SMALL_INT (offset
))
1172 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands
);
1174 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands
);
1181 /* Output code to place a size count SIZE in register REG.
1182 Because block moves are pipelined, we don't include the
1183 first element in the transfer of SIZE to REG.
1184 For this, we subtract ALIGN. (Actually, I think it is not
1185 right to subtract on this machine, so right now we don't.) */
1188 output_size_for_block_move (size
, reg
, align
)
1189 rtx size
, reg
, align
;
1194 xoperands
[1] = size
;
1195 xoperands
[2] = align
;
1198 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
1199 output_asm_insn ("mov %1,%0", xoperands
);
1201 if (GET_CODE (size
) == REG
)
1202 output_asm_insn ("sub %2,%1,%0", xoperands
);
1206 = gen_rtx (CONST_INT
, VOIDmode
, INTVAL (size
) - INTVAL (align
));
1207 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
1208 output_asm_insn ("mov %1,%0", xoperands
);
1213 /* Emit code to perform a block move.
1215 OPERANDS[0] is the destination.
1216 OPERANDS[1] is the source.
1217 OPERANDS[2] is the size.
1218 OPERANDS[3] is the known safe alignment.
1219 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1222 output_block_move (operands
)
1225 /* A vector for our computed operands. Note that load_output_address
1226 makes use of (and can clobber) up to the 8th element of this vector. */
1229 static int movstrsi_label
= 0;
1231 rtx temp1
= operands
[4];
1232 rtx alignrtx
= operands
[3];
1233 int align
= INTVAL (alignrtx
);
1236 xoperands
[0] = operands
[0];
1237 xoperands
[1] = operands
[1];
1238 xoperands
[2] = temp1
;
1240 /* We can't move more than four bytes at a time
1241 because we have only one register to move them through. */
1245 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, 4);
1248 /* Recognize special cases of block moves. These occur
1249 when GNU C++ is forced to treat something as BLKmode
1250 to keep it in memory, when its mode could be represented
1251 with something smaller.
1253 We cannot do this for global variables, since we don't know
1254 what pages they don't cross. Sigh. */
1255 if (GET_CODE (operands
[2]) == CONST_INT
1256 && ! CONSTANT_ADDRESS_P (operands
[0])
1257 && ! CONSTANT_ADDRESS_P (operands
[1]))
1259 int size
= INTVAL (operands
[2]);
1260 rtx op0
= xoperands
[0];
1261 rtx op1
= xoperands
[1];
1263 if ((align
& 3) == 0 && (size
& 3) == 0 && (size
>> 2) <= 16)
1265 if (memory_address_p (SImode
, plus_constant (op0
, size
))
1266 && memory_address_p (SImode
, plus_constant (op1
, size
)))
1268 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1269 for (i
= (size
>>2)-1; i
>= 0; i
--)
1271 xoperands
[0] = plus_constant (op0
, i
* 4);
1272 xoperands
[1] = plus_constant (op1
, i
* 4);
1273 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1279 else if ((align
& 1) == 0 && (size
& 1) == 0 && (size
>> 1) <= 16)
1281 if (memory_address_p (HImode
, plus_constant (op0
, size
))
1282 && memory_address_p (HImode
, plus_constant (op1
, size
)))
1284 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1285 for (i
= (size
>>1)-1; i
>= 0; i
--)
1287 xoperands
[0] = plus_constant (op0
, i
* 2);
1288 xoperands
[1] = plus_constant (op1
, i
* 2);
1289 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1295 else if (size
<= 16)
1297 if (memory_address_p (QImode
, plus_constant (op0
, size
))
1298 && memory_address_p (QImode
, plus_constant (op1
, size
)))
1300 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1301 for (i
= size
-1; i
>= 0; i
--)
1303 xoperands
[0] = plus_constant (op0
, i
);
1304 xoperands
[1] = plus_constant (op1
, i
);
1305 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1313 /* Since we clobber untold things, nix the condition codes. */
1316 /* This is the size of the transfer.
1317 Either use the register which already contains the size,
1318 or use a free register (used by no operands). */
1319 output_size_for_block_move (operands
[2], operands
[4], alignrtx
);
1322 /* Also emit code to decrement the size value by ALIGN. */
1323 zoperands
[0] = operands
[0];
1324 zoperands
[3] = plus_constant (operands
[0], align
);
1325 output_load_address (zoperands
);
1328 /* Generate number for unique label. */
1330 xoperands
[3] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
1332 /* Calculate the size of the chunks we will be trying to move first. */
1335 if ((align
& 3) == 0)
1337 else if ((align
& 1) == 0)
1343 /* Copy the increment (negative) to a register for bla insn. */
1345 xoperands
[4] = gen_rtx (CONST_INT
, VOIDmode
, - chunk_size
);
1346 xoperands
[5] = operands
[5];
1347 output_asm_insn ("adds %4,%?r0,%5", xoperands
);
1349 /* Predecrement the loop counter. This happens again also in the `bla'
1350 instruction which precceds the loop, but we need to have it done
1351 two times before we enter the loop because of the bizzare semantics
1352 of the bla instruction. */
1354 output_asm_insn ("adds %5,%2,%2", xoperands
);
1356 /* Check for the case where the original count was less than or equal to
1357 zero. Avoid going through the loop at all if the original count was
1358 indeed less than or equal to zero. Note that we treat the count as
1359 if it were a signed 32-bit quantity here, rather than an unsigned one,
1360 even though we really shouldn't. We have to do this because of the
1361 semantics of the `ble' instruction, which assume that the count is
1362 a signed 32-bit value. Anyway, in practice it won't matter because
1363 nobody is going to try to do a memcpy() of more than half of the
1364 entire address space (i.e. 2 gigabytes) anyway. */
1366 output_asm_insn ("bc .Le%3", xoperands
);
1368 /* Make available a register which is a temporary. */
1370 xoperands
[6] = operands
[6];
1372 /* Now the actual loop.
1373 In xoperands, elements 1 and 0 are the input and output vectors.
1374 Element 2 is the loop index. Element 5 is the increment. */
1376 output_asm_insn ("subs %1,%5,%1", xoperands
);
1377 output_asm_insn ("bla %5,%2,.Lm%3", xoperands
);
1378 output_asm_insn ("adds %0,%2,%6", xoperands
);
1379 output_asm_insn ("\n.Lm%3:", xoperands
); /* Label for bla above. */
1380 output_asm_insn ("\n.Ls%3:", xoperands
); /* Loop start label. */
1381 output_asm_insn ("adds %5,%6,%6", xoperands
);
1383 /* NOTE: The code here which is supposed to handle the cases where the
1384 sources and destinations are known to start on a 4 or 2 byte boundary
1385 are currently broken. They fail to do anything about the overflow
1386 bytes which might still need to be copied even after we have copied
1387 some number of words or halfwords. Thus, for now we use the lowest
1388 common denominator, i.e. the code which just copies some number of
1389 totally unaligned individual bytes. (See the calculation of
1390 chunk_size above. */
1392 if (chunk_size
== 4)
1394 output_asm_insn ("ld.l %2(%1),%?r31", xoperands
);
1395 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1396 output_asm_insn ("st.l %?r31,8(%6)", xoperands
);
1398 else if (chunk_size
== 2)
1400 output_asm_insn ("ld.s %2(%1),%?r31", xoperands
);
1401 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1402 output_asm_insn ("st.s %?r31,4(%6)", xoperands
);
1404 else /* chunk_size == 1 */
1406 output_asm_insn ("ld.b %2(%1),%?r31", xoperands
);
1407 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1408 output_asm_insn ("st.b %?r31,2(%6)", xoperands
);
1410 output_asm_insn ("\n.Le%3:", xoperands
); /* Here if count <= 0. */
1415 /* Output a delayed branch insn with the delay insn in its
1416 branch slot. The delayed branch insn template is in TEMPLATE,
1417 with operands OPERANDS. The insn in its delay slot is INSN.
1419 As a special case, since we know that all memory transfers are via
1420 ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
1421 reference around the branch as
1425 ld/st l%x(%?r31),...
1427 As another special case, we handle loading (SYMBOL_REF ...) and
1428 other large constants around branches as well:
1437 output_delayed_branch (template, operands
, insn
)
1442 rtx src
= XVECEXP (PATTERN (insn
), 0, 1);
1443 rtx dest
= XVECEXP (PATTERN (insn
), 0, 0);
1445 /* See if we are doing some branch together with setting some register
1446 to some 32-bit value which does (or may) have some of the high-order
1447 16 bits set. If so, we need to set the register in two stages. One
1448 stage must be done before the branch, and the other one can be done
1449 in the delay slot. */
1451 if ( (GET_CODE (src
) == CONST_INT
1452 && ((unsigned) INTVAL (src
) & (unsigned) 0xffff0000) != (unsigned) 0)
1453 || (GET_CODE (src
) == SYMBOL_REF
)
1454 || (GET_CODE (src
) == LABEL_REF
)
1455 || (GET_CODE (src
) == CONST
))
1458 xoperands
[0] = dest
;
1461 CC_STATUS_PARTIAL_INIT
;
1462 /* Output the `orh' insn. */
1463 output_asm_insn ("orh %H1,%?r0,%0", xoperands
);
1465 /* Output the branch instruction next. */
1466 output_asm_insn (template, operands
);
1468 /* Now output the `or' insn. */
1469 output_asm_insn ("or %L1,%0,%0", xoperands
);
1471 else if ((GET_CODE (src
) == MEM
1472 && CONSTANT_ADDRESS_P (XEXP (src
, 0)))
1473 || (GET_CODE (dest
) == MEM
1474 && CONSTANT_ADDRESS_P (XEXP (dest
, 0))))
1477 char *split_template
;
1478 xoperands
[0] = dest
;
1481 /* Output the `orh' insn. */
1482 if (GET_CODE (src
) == MEM
)
1484 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1485 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1486 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
1489 output_asm_insn ("orh %h1,%?r0,%?r31", xoperands
);
1491 split_template
= load_opcode (GET_MODE (dest
),
1492 "%L1(%?r31),%0", dest
);
1496 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1497 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1498 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
1501 output_asm_insn ("orh %h0,%?r0,%?r31", xoperands
);
1503 split_template
= store_opcode (GET_MODE (dest
),
1504 "%r1,%L0(%?r31)", src
);
1507 /* Output the branch instruction next. */
1508 output_asm_insn (template, operands
);
1510 /* Now output the load or store.
1511 No need to do a CC_STATUS_INIT, because we are branching anyway. */
1512 output_asm_insn (split_template
, xoperands
);
1516 int insn_code_number
;
1517 rtx pat
= gen_rtx (SET
, VOIDmode
, dest
, src
);
1518 rtx delay_insn
= gen_rtx (INSN
, VOIDmode
, 0, 0, 0, pat
, -1, 0, 0);
1521 /* Output the branch instruction first. */
1522 output_asm_insn (template, operands
);
1524 /* Now recognize the insn which we put in its delay slot.
1525 We must do this after outputing the branch insn,
1526 since operands may just be a pointer to `recog_operand'. */
1527 INSN_CODE (delay_insn
) = insn_code_number
= recog (pat
, delay_insn
);
1528 if (insn_code_number
== -1)
1531 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1533 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1534 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1537 insn_extract (delay_insn
);
1538 if (! constrain_operands (insn_code_number
, 1))
1539 fatal_insn_not_found (delay_insn
);
1541 template = insn_template
[insn_code_number
];
1543 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1544 output_asm_insn (template, recog_operand
);
1550 /* Output a newly constructed insn DELAY_INSN. */
1552 output_delay_insn (delay_insn
)
1556 int insn_code_number
;
1559 /* Now recognize the insn which we put in its delay slot.
1560 We must do this after outputing the branch insn,
1561 since operands may just be a pointer to `recog_operand'. */
1562 insn_code_number
= recog_memoized (delay_insn
);
1563 if (insn_code_number
== -1)
1566 /* Extract the operands of this delay insn. */
1567 INSN_CODE (delay_insn
) = insn_code_number
;
1568 insn_extract (delay_insn
);
1570 /* It is possible that this insn has not been properly scaned by final
1571 yet. If this insn's operands don't appear in the peephole's
1572 actual operands, then they won't be fixed up by final, so we
1573 make sure they get fixed up here. -- This is a kludge. */
1574 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1576 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1577 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1580 #ifdef REGISTER_CONSTRAINTS
1581 if (! constrain_operands (insn_code_number
))
1585 cc_prev_status
= cc_status
;
1587 /* Update `cc_status' for this instruction.
1588 The instruction's output routine may change it further.
1589 If the output routine for a jump insn needs to depend
1590 on the cc status, it should look at cc_prev_status. */
1592 NOTICE_UPDATE_CC (PATTERN (delay_insn
), delay_insn
);
1594 /* Now get the template for what this insn would
1595 have been, without the branch. */
1597 template = insn_template
[insn_code_number
];
1599 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1600 output_asm_insn (template, recog_operand
);
1604 /* Special routine to convert an SFmode value represented as a
1605 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1606 We convert the value from a double precision floating-point
1607 value to single precision first, and thence to a bit-wise
1608 equivalent unsigned long value. This routine is used when
1609 generating an immediate move of an SFmode value directly
1610 into a general register because the svr4 assembler doesn't
1611 grok floating literals in instruction operand contexts. */
1614 sfmode_constant_to_ulong (x
)
1618 union { float f
; unsigned long i
; } u2
;
1620 if (GET_CODE (x
) != CONST_DOUBLE
|| GET_MODE (x
) != SFmode
)
1623 #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1624 # error IEEE emulation needed
1626 REAL_VALUE_FROM_CONST_DOUBLE (u
.d
, x
);
1631 /* This function generates the assembly code for function entry.
1632 The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1634 ASM_FILE is a stdio stream to output the code to.
1635 SIZE is an int: how many units of temporary storage to allocate.
1637 Refer to the array `regs_ever_live' to determine which registers
1638 to save; `regs_ever_live[I]' is nonzero if register number I
1639 is ever used in the function. This macro is responsible for
1640 knowing which registers should not be saved even if used.
1642 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1643 between the new `fp' value and the new `sp' value after the
1644 prologue is done. `frame_upper_bytes' is the count of bytes
1645 that will lie between the new `fp' and the *old* `sp' value
1646 after the new `fp' is setup (in the prologue). The upper
1647 part of each frame always includes at least 2 words (8 bytes)
1648 to hold the saved frame pointer and the saved return address.
1650 The svr4 ABI for the i860 now requires that the values of the
1651 stack pointer and frame pointer registers be kept aligned to
1652 16-byte boundaries at all times. We obey that restriction here.
1654 The svr4 ABI for the i860 is entirely vague when it comes to specifying
1655 exactly where the "preserved" registers should be saved. The native
1656 svr4 C compiler I now have doesn't help to clarify the requirements
1657 very much because it is plainly out-of-date and non-ABI-compliant
1658 (in at least one important way, i.e. how it generates function
1661 The native svr4 C compiler saves the "preserved" registers (i.e.
1662 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1663 offsets from the frame pointer).
1665 Previous versions of GCC also saved the "preserved" registers in the
1666 "nagative" part of the frame, but they saved them using positive
1667 offsets from the (adjusted) stack pointer (after it had been adjusted
1668 to allocate space for the new frame). That's just plain wrong
1669 because if the current function calls alloca(), the stack pointer
1670 will get moved, and it will be impossible to restore the registers
1671 properly again after that.
1673 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1674 by copying their values either into various "preserved" registers or
1675 into stack slots in the lower part of the current frame (as seemed
1676 appropriate, depending upon subsequent usage of these values).
1678 Here we want to save the preserved registers at some offset from the
1679 frame pointer register so as to avoid any possible problems arising
1680 from calls to alloca(). We can either save them at small positive
1681 offsets from the frame pointer, or at small negative offsets from
1682 the frame pointer. If we save them at small negative offsets from
1683 the frame pointer (i.e. in the lower part of the frame) then we
1684 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1685 many bytes of space we plan to use in the lower part of the frame
1686 for this purpose. Since other parts of the compiler reference the
1687 value of STARTING_FRAME_OFFSET long before final() calls this function,
1688 we would have to go ahead and assume the worst-case storage requirements
1689 for saving all of the "preserved" registers (and use that number, i.e.
1690 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1691 the lower part of the frame. That could potentially be very wasteful,
1692 and that wastefulness could really hamper people compiling for embedded
1693 i860 targets with very tight limits on stack space. Thus, we choose
1694 here to save the preserved registers in the upper part of the
1695 frame, so that we can decide at the very last minute how much (or how
1696 little) space we must allocate for this purpose.
1698 To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1699 registers must always be saved so that the saved values of registers
1700 with higher numbers are at higher addresses. We obey that restriction
1703 There are two somewhat different ways that you can generate prologues
1704 here... i.e. pedantically ABI-compliant, and the "other" way. The
1705 "other" way is more consistant with what is currently generated by the
1706 "native" svr4 C compiler for the i860. That's important if you want
1707 to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1708 The SVR4 SDB for the i860 insists on having function prologues be
1711 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1712 in the i860svr4.h file. (By default this is *not* defined).
1714 The differences between the ABI-compliant and non-ABI-compliant prologues
1715 are that (a) the ABI version seems to require the use of *signed*
1716 (rather than unsigned) adds and subtracts, and (b) the ordering of
1717 the various steps (e.g. saving preserved registers, saving the
1718 return address, setting up the new frame pointer value) is different.
1720 For strict ABI compliance, it seems to be the case that the very last
1721 thing that is supposed to happen in the prologue is getting the frame
1722 pointer set to its new value (but only after everything else has
1723 already been properly setup). We do that here, but only if the symbol
1724 I860_STRICT_ABI_PROLOGUES is defined.
1727 #ifndef STACK_ALIGNMENT
1728 #define STACK_ALIGNMENT 16
1731 extern char call_used_regs
[];
1732 extern int leaf_function_p ();
1734 char *current_function_original_name
;
1736 static int must_preserve_r1
;
1737 static unsigned must_preserve_bytes
;
1740 function_prologue (asm_file
, local_bytes
)
1741 register FILE *asm_file
;
1742 register unsigned local_bytes
;
1744 register unsigned frame_lower_bytes
;
1745 register unsigned frame_upper_bytes
;
1746 register unsigned total_fsize
;
1747 register unsigned preserved_reg_bytes
= 0;
1748 register unsigned i
;
1749 register unsigned preserved_so_far
= 0;
1751 must_preserve_r1
= (optimize
< 2 || ! leaf_function_p ());
1752 must_preserve_bytes
= 4 + (must_preserve_r1
? 4 : 0);
1754 /* Count registers that need preserving. Ignore r0. It never needs
1757 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
1759 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1760 preserved_reg_bytes
+= 4;
1763 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1765 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1767 /* The upper part of each frame will contain the saved fp,
1768 the saved r1, and stack slots for all of the other "preserved"
1769 registers that we find we will need to save & restore. */
1771 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
1773 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1776 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1778 total_fsize
= frame_upper_bytes
+ frame_lower_bytes
;
1780 #ifndef I860_STRICT_ABI_PROLOGUES
1782 /* There are two kinds of function prologues.
1783 You use the "small" version if the total frame size is
1784 small enough so that it can fit into an immediate 16-bit
1785 value in one instruction. Otherwise, you use the "large"
1786 version of the function prologue. */
1788 if (total_fsize
> 0x7fff)
1790 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1791 but the native C compiler on svr4 uses `addu'. */
1793 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1794 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1796 /* Save the old frame pointer. */
1798 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1799 i860_reg_prefix
, i860_reg_prefix
);
1801 /* Setup the new frame pointer. The ABI sez to do this after
1802 preserving registers (using adds), but that's not what the
1803 native C compiler on svr4 does. */
1805 fprintf (asm_file
, "\taddu 0,%ssp,%sfp\n",
1806 i860_reg_prefix
, i860_reg_prefix
);
1808 /* Get the value of frame_lower_bytes into r31. */
1810 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1811 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1812 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1813 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1815 /* Now re-adjust the stack pointer using the value in r31.
1816 The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1818 fprintf (asm_file
, "\tsubu %ssp,%sr31,%ssp\n",
1819 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1821 /* Preserve registers. The ABI sez to do this before setting
1822 up the new frame pointer, but that's not what the native
1823 C compiler on svr4 does. */
1825 for (i
= 1; i
< 32; i
++)
1826 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1827 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1828 i860_reg_prefix
, reg_names
[i
],
1829 must_preserve_bytes
+ (4 * preserved_so_far
++),
1832 for (i
= 32; i
< 64; i
++)
1833 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1834 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1835 i860_reg_prefix
, reg_names
[i
],
1836 must_preserve_bytes
+ (4 * preserved_so_far
++),
1839 /* Save the return address. */
1841 if (must_preserve_r1
)
1842 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1843 i860_reg_prefix
, i860_reg_prefix
);
1847 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1848 but the native C compiler on svr4 uses `addu'. */
1850 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1851 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1853 /* Save the old frame pointer. */
1855 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1856 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1858 /* Setup the new frame pointer. The ABI sez to do this after
1859 preserving registers and after saving the return address,
1860 (and its saz to do this using adds), but that's not what the
1861 native C compiler on svr4 does. */
1863 fprintf (asm_file
, "\taddu %d,%ssp,%sfp\n",
1864 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1866 /* Preserve registers. The ABI sez to do this before setting
1867 up the new frame pointer, but that's not what the native
1868 compiler on svr4 does. */
1870 for (i
= 1; i
< 32; i
++)
1871 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1872 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1873 i860_reg_prefix
, reg_names
[i
],
1874 must_preserve_bytes
+ (4 * preserved_so_far
++),
1877 for (i
= 32; i
< 64; i
++)
1878 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1879 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1880 i860_reg_prefix
, reg_names
[i
],
1881 must_preserve_bytes
+ (4 * preserved_so_far
++),
1884 /* Save the return address. The ABI sez to do this earlier,
1885 and also via an offset from %sp, but the native C compiler
1886 on svr4 does it later (i.e. now) and uses an offset from
1889 if (must_preserve_r1
)
1890 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1891 i860_reg_prefix
, i860_reg_prefix
);
1894 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1896 /* There are two kinds of function prologues.
1897 You use the "small" version if the total frame size is
1898 small enough so that it can fit into an immediate 16-bit
1899 value in one instruction. Otherwise, you use the "large"
1900 version of the function prologue. */
1902 if (total_fsize
> 0x7fff)
1904 /* Adjust the stack pointer (thereby allocating a new frame). */
1906 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1907 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1909 /* Save the caller's frame pointer. */
1911 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1912 i860_reg_prefix
, i860_reg_prefix
);
1914 /* Save return address. */
1916 if (must_preserve_r1
)
1917 fprintf (asm_file
, "\tst.l %sr1,4(%ssp)\n",
1918 i860_reg_prefix
, i860_reg_prefix
);
1920 /* Get the value of frame_lower_bytes into r31 for later use. */
1922 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1923 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1924 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1925 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1927 /* Now re-adjust the stack pointer using the value in r31. */
1929 fprintf (asm_file
, "\tsubs %ssp,%sr31,%ssp\n",
1930 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1932 /* Pre-compute value to be used as the new frame pointer. */
1934 fprintf (asm_file
, "\tadds %ssp,%sr31,%sr31\n",
1935 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1937 /* Preserve registers. */
1939 for (i
= 1; i
< 32; i
++)
1940 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1941 fprintf (asm_file
, "\tst.l %s%s,%d(%sr31)\n",
1942 i860_reg_prefix
, reg_names
[i
],
1943 must_preserve_bytes
+ (4 * preserved_so_far
++),
1946 for (i
= 32; i
< 64; i
++)
1947 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1948 fprintf (asm_file
, "\tfst.l %s%s,%d(%sr31)\n",
1949 i860_reg_prefix
, reg_names
[i
],
1950 must_preserve_bytes
+ (4 * preserved_so_far
++),
1953 /* Actually set the new value of the frame pointer. */
1955 fprintf (asm_file
, "\tmov %sr31,%sfp\n",
1956 i860_reg_prefix
, i860_reg_prefix
);
1960 /* Adjust the stack pointer. */
1962 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1963 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1965 /* Save the caller's frame pointer. */
1967 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1968 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1970 /* Save the return address. */
1972 if (must_preserve_r1
)
1973 fprintf (asm_file
, "\tst.l %sr1,%d(%ssp)\n",
1974 i860_reg_prefix
, frame_lower_bytes
+ 4, i860_reg_prefix
);
1976 /* Preserve registers. */
1978 for (i
= 1; i
< 32; i
++)
1979 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1980 fprintf (asm_file
, "\tst.l %s%s,%d(%ssp)\n",
1981 i860_reg_prefix
, reg_names
[i
],
1982 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1985 for (i
= 32; i
< 64; i
++)
1986 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1987 fprintf (asm_file
, "\tfst.l %s%s,%d(%ssp)\n",
1988 i860_reg_prefix
, reg_names
[i
],
1989 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1992 /* Setup the new frame pointer. */
1994 fprintf (asm_file
, "\tadds %d,%ssp,%sfp\n",
1995 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1997 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1999 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
2000 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file
);
2001 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
2004 /* This function generates the assembly code for function exit.
2005 The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
2007 ASM_FILE is a stdio stream to output the code to.
2008 SIZE is an int: how many units of temporary storage to allocate.
2010 The function epilogue should not depend on the current stack pointer!
2011 It should use the frame pointer only. This is mandatory because
2012 of alloca; we also take advantage of it to omit stack adjustments
2015 Note that when we go to restore the preserved register values we must
2016 not try to address their slots by using offsets from the stack pointer.
2017 That's because the stack pointer may have been moved during the function
2018 execution due to a call to alloca(). Rather, we must restore all
2019 preserved registers via offsets from the frame pointer value.
2021 Note also that when the current frame is being "popped" (by adjusting
2022 the value of the stack pointer) on function exit, we must (for the
2023 sake of alloca) set the new value of the stack pointer based upon
2024 the current value of the frame pointer. We can't just add what we
2025 believe to be the (static) frame size to the stack pointer because
2026 if we did that, and alloca() had been called during this function,
2027 we would end up returning *without* having fully deallocated all of
2028 the space grabbed by alloca. If that happened, and a function
2029 containing one or more alloca() calls was called over and over again,
2030 then the stack would grow without limit!
2032 Finally note that the epilogues generated here are completely ABI
2033 compliant. They go out of their way to insure that the value in
2034 the frame pointer register is never less than the value in the stack
2035 pointer register. It's not clear why this relationship needs to be
2036 maintained at all times, but maintaining it only costs one extra
2037 instruction, so what the hell.
2041 function_epilogue (asm_file
, local_bytes
)
2042 register FILE *asm_file
;
2043 register unsigned local_bytes
;
2045 register unsigned frame_upper_bytes
;
2046 register unsigned preserved_reg_bytes
= 0;
2047 register unsigned i
;
2048 register unsigned restored_so_far
= 0;
2050 /* Count the number of registers that were preserved in the prologue.
2051 Ignore r0. It is never preserved. */
2053 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
2055 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2056 preserved_reg_bytes
+= 4;
2059 /* The upper part of each frame will contain only saved fp,
2060 the saved r1, and stack slots for all of the other "preserved"
2061 registers that we find we will need to save & restore. */
2063 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
2065 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
2068 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
2070 /* Restore all of the "preserved" registers that need restoring. */
2072 for (i
= 1; i
< 32; i
++)
2073 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2074 fprintf (asm_file
, "\tld.l %d(%sfp),%s%s\n",
2075 must_preserve_bytes
+ (4 * restored_so_far
++),
2076 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
2078 for (i
= 32; i
< 64; i
++)
2079 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2080 fprintf (asm_file
, "\tfld.l %d(%sfp),%s%s\n",
2081 must_preserve_bytes
+ (4 * restored_so_far
++),
2082 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
2084 /* Get the value we plan to use to restore the stack pointer into r31. */
2086 fprintf (asm_file
, "\tadds %d,%sfp,%sr31\n",
2087 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
2089 /* Restore the return address and the old frame pointer. */
2091 if (must_preserve_r1
)
2092 fprintf (asm_file
, "\tld.l 4(%sfp),%sr1\n",
2093 i860_reg_prefix
, i860_reg_prefix
);
2095 fprintf (asm_file
, "\tld.l 0(%sfp),%sfp\n",
2096 i860_reg_prefix
, i860_reg_prefix
);
2098 /* Return and restore the old stack pointer value. */
2100 fprintf (asm_file
, "\tbri %sr1\n\tmov %sr31,%ssp\n",
2101 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);