1 /* Subroutines for insn-output.c for Intel 860
2 Copyright (C) 1989, 1991 Free Software Foundation, Inc.
5 Written by Richard Stallman (rms@ai.mit.edu).
7 Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater
8 to the whims of the System V Release 4 assembler.
10 This file is part of GNU CC.
12 GNU CC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GNU CC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GNU CC; see the file COPYING. If not, write to
24 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
38 #include "insn-attr.h"
42 static rtx
find_addr_reg ();
44 #ifndef I860_REG_PREFIX
45 #define I860_REG_PREFIX ""
48 char *i860_reg_prefix
= I860_REG_PREFIX
;
50 /* Save information from a "cmpxx" operation until the branch is emitted. */
52 rtx i860_compare_op0
, i860_compare_op1
;
54 /* Return non-zero if this pattern, can be evaluated safely, even if it
57 safe_insn_src_p (op
, mode
)
59 enum machine_mode mode
;
61 /* Just experimenting. */
63 /* No floating point src is safe if it contains an arithmetic
64 operation, since that operation may trap. */
65 switch (GET_CODE (op
))
77 return CONSTANT_ADDRESS_P (XEXP (op
, 0));
79 /* We never need to negate or complement constants. */
81 return (mode
!= SFmode
&& mode
!= DFmode
);
98 return (mode
!= SFmode
&& mode
!= DFmode
);
106 if ((GET_CODE (XEXP (op
, 0)) == CONST_INT
&& ! SMALL_INT (XEXP (op
, 0)))
107 || (GET_CODE (XEXP (op
, 1)) == CONST_INT
&& ! SMALL_INT (XEXP (op
, 1))))
116 /* Return 1 if REG is clobbered in IN.
117 Return 2 if REG is used in IN.
118 Return 3 if REG is both used and clobbered in IN.
119 Return 0 if neither. */
122 reg_clobbered_p (reg
, in
)
126 register enum rtx_code code
;
131 code
= GET_CODE (in
);
133 if (code
== SET
|| code
== CLOBBER
)
135 rtx dest
= SET_DEST (in
);
139 while (GET_CODE (dest
) == STRICT_LOW_PART
140 || GET_CODE (dest
) == SUBREG
141 || GET_CODE (dest
) == SIGN_EXTRACT
142 || GET_CODE (dest
) == ZERO_EXTRACT
)
143 dest
= XEXP (dest
, 0);
147 else if (GET_CODE (dest
) == REG
148 && refers_to_regno_p (REGNO (reg
),
149 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
153 /* Anything that sets just part of the register
154 is considered using as well as setting it.
155 But note that a straight SUBREG of a single-word value
156 clobbers the entire value. */
157 if (dest
!= SET_DEST (in
)
158 && ! (GET_CODE (SET_DEST (in
)) == SUBREG
159 || UNITS_PER_WORD
>= GET_MODE_SIZE (GET_MODE (dest
))))
166 used
= refers_to_regno_p (REGNO (reg
),
167 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
170 used
= refers_to_regno_p (REGNO (reg
),
171 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
175 return set
+ used
* 2;
178 if (refers_to_regno_p (REGNO (reg
),
179 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
185 /* Return non-zero if OP can be written to without screwing up
186 GCC's model of what's going on. It is assumed that this operand
187 appears in the dest position of a SET insn in a conditional
188 branch's delay slot. AFTER is the label to start looking from. */
190 operand_clobbered_before_used_after (op
, after
)
194 /* Just experimenting. */
195 if (GET_CODE (op
) == CC0
)
197 if (GET_CODE (op
) == REG
)
201 if (op
== stack_pointer_rtx
)
204 /* Scan forward from the label, to see if the value of OP
205 is clobbered before the first use. */
207 for (insn
= NEXT_INSN (after
); insn
; insn
= NEXT_INSN (insn
))
209 if (GET_CODE (insn
) == NOTE
)
211 if (GET_CODE (insn
) == INSN
212 || GET_CODE (insn
) == JUMP_INSN
213 || GET_CODE (insn
) == CALL_INSN
)
215 switch (reg_clobbered_p (op
, PATTERN (insn
)))
225 /* If we reach another label without clobbering OP,
226 then we cannot safely write it here. */
227 else if (GET_CODE (insn
) == CODE_LABEL
)
229 if (GET_CODE (insn
) == JUMP_INSN
)
231 if (condjump_p (insn
))
233 /* This is a jump insn which has already
234 been mangled. We can't tell what it does. */
235 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
237 if (! JUMP_LABEL (insn
))
239 /* Keep following jumps. */
240 insn
= JUMP_LABEL (insn
);
246 /* In both of these cases, the first insn executed
247 for this op will be a orh whatever%h,%?r0,%?r31,
248 which is tolerable. */
249 if (GET_CODE (op
) == MEM
)
250 return (CONSTANT_ADDRESS_P (XEXP (op
, 0)));
255 /* Return non-zero if this pattern, as a source to a "SET",
256 is known to yield an instruction of unit size. */
258 single_insn_src_p (op
, mode
)
260 enum machine_mode mode
;
262 switch (GET_CODE (op
))
265 /* This is not always a single insn src, technically,
266 but output_delayed_branch knows how to deal with it. */
271 /* This is not a single insn src, technically,
272 but output_delayed_branch knows how to deal with it. */
281 /* We never need to negate or complement constants. */
283 return (mode
!= DFmode
);
290 /* Detect cases that require multiple instructions. */
291 if (CONSTANT_P (XEXP (op
, 1))
292 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
293 && SMALL_INT (XEXP (op
, 1))))
305 /* Not doing floating point, since they probably
306 take longer than the branch slot they might fill. */
307 return (mode
!= SFmode
&& mode
!= DFmode
);
310 if (GET_CODE (XEXP (op
, 1)) == NOT
)
312 rtx arg
= XEXP (XEXP (op
, 1), 0);
314 && !(GET_CODE (arg
) == CONST_INT
316 || INTVAL (arg
) & 0xffff == 0)))
321 /* Both small and round numbers take one instruction;
323 if (CONSTANT_P (XEXP (op
, 1))
324 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
325 && (SMALL_INT (XEXP (op
, 1))
326 || INTVAL (XEXP (op
, 1)) & 0xffff == 0)))
336 if (SUBREG_WORD (op
) != 0)
338 return single_insn_src_p (SUBREG_REG (op
), mode
);
340 /* Not doing floating point, since they probably
341 take longer than the branch slot they might fill. */
355 /* Return non-zero only if OP is a register of mode MODE,
358 reg_or_0_operand (op
, mode
)
360 enum machine_mode mode
;
362 return (op
== const0_rtx
|| register_operand (op
, mode
)
363 || op
== CONST0_RTX (mode
));
366 /* Return truth value of whether OP can be used as an operands in a three
367 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
370 arith_operand (op
, mode
)
372 enum machine_mode mode
;
374 return (register_operand (op
, mode
)
375 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
378 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
381 logic_operand (op
, mode
)
383 enum machine_mode mode
;
385 return (register_operand (op
, mode
)
386 || (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
)));
389 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
392 shift_operand (op
, mode
)
394 enum machine_mode mode
;
396 return (register_operand (op
, mode
)
397 || (GET_CODE (op
) == CONST_INT
));
400 /* Return 1 if OP is a valid first operand for either a logical insn
401 or an add insn of mode MODE. */
404 compare_operand (op
, mode
)
406 enum machine_mode mode
;
408 return (register_operand (op
, mode
)
409 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
) && LOGIC_INT (op
)));
412 /* Return truth value of whether OP can be used as the 5-bit immediate
413 operand of a bte or btne insn. */
416 bte_operand (op
, mode
)
418 enum machine_mode mode
;
420 return (register_operand (op
, mode
)
421 || (GET_CODE (op
) == CONST_INT
422 && (unsigned) INTVAL (op
) < 0x20));
425 /* Return 1 if OP is an indexed memory reference of mode MODE. */
428 indexed_operand (op
, mode
)
430 enum machine_mode mode
;
432 return (GET_CODE (op
) == MEM
&& GET_MODE (op
) == mode
433 && GET_CODE (XEXP (op
, 0)) == PLUS
434 && GET_MODE (XEXP (op
, 0)) == SImode
435 && register_operand (XEXP (XEXP (op
, 0), 0), SImode
)
436 && register_operand (XEXP (XEXP (op
, 0), 1), SImode
));
439 /* Return 1 if OP is a suitable source operand for a load insn
443 load_operand (op
, mode
)
445 enum machine_mode mode
;
447 return (memory_operand (op
, mode
) || indexed_operand (op
, mode
));
450 /* Return truth value of whether OP is a integer which fits the
451 range constraining immediate operands in add/subtract insns. */
456 enum machine_mode mode
;
458 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
461 /* Return truth value of whether OP is a integer which fits the
462 range constraining immediate operands in logic insns. */
467 enum machine_mode mode
;
469 return (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
));
472 /* Test for a valid operand for a call instruction.
473 Don't allow the arg pointer register or virtual regs
474 since they may change into reg + const, which the patterns
478 call_insn_operand (op
, mode
)
480 enum machine_mode mode
;
482 if (GET_CODE (op
) == MEM
483 && (CONSTANT_ADDRESS_P (XEXP (op
, 0))
484 || (GET_CODE (XEXP (op
, 0)) == REG
485 && XEXP (op
, 0) != arg_pointer_rtx
486 && !(REGNO (XEXP (op
, 0)) >= FIRST_PSEUDO_REGISTER
487 && REGNO (XEXP (op
, 0)) <= LAST_VIRTUAL_REGISTER
))))
492 /* Return the best assembler insn template
493 for moving operands[1] into operands[0] as a fullword. */
496 singlemove_string (operands
)
499 if (GET_CODE (operands
[0]) == MEM
)
501 if (GET_CODE (operands
[1]) != MEM
)
502 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
504 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
505 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
506 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
509 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
511 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
512 cc_status
.mdep
= XEXP (operands
[0], 0);
513 return "st.l %r1,%L0(%?r31)";
516 return "st.l %r1,%0";
523 cc_status
.flags
&= ~CC_F0_IS_0
;
524 xoperands
[0] = gen_rtx (REG
, SFmode
, 32);
525 xoperands
[1] = operands
[1];
526 output_asm_insn (singlemove_string (xoperands
), xoperands
);
527 xoperands
[1] = xoperands
[0];
528 xoperands
[0] = operands
[0];
529 output_asm_insn (singlemove_string (xoperands
), xoperands
);
534 if (GET_CODE (operands
[1]) == MEM
)
536 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
538 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
539 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
540 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
543 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
545 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
546 cc_status
.mdep
= XEXP (operands
[1], 0);
547 return "ld.l %L1(%?r31),%0";
549 return "ld.l %m1,%0";
551 if (GET_CODE (operands
[1]) == CONST_INT
)
553 if (operands
[1] == const0_rtx
)
554 return "mov %?r0,%0";
555 if((INTVAL (operands
[1]) & 0xffff0000) == 0)
556 return "or %L1,%?r0,%0";
557 if((INTVAL (operands
[1]) & 0xffff8000) == 0xffff8000)
558 return "adds %1,%?r0,%0";
559 if((INTVAL (operands
[1]) & 0x0000ffff) == 0)
560 return "orh %H1,%?r0,%0";
565 /* Output assembler code to perform a doubleword move insn
566 with operands OPERANDS. */
569 output_move_double (operands
)
572 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
574 rtx addreg0
= 0, addreg1
= 0;
576 /* First classify both operands. */
578 if (REG_P (operands
[0]))
580 else if (offsettable_memref_p (operands
[0]))
582 else if (GET_CODE (operands
[0]) == MEM
)
587 if (REG_P (operands
[1]))
589 else if (CONSTANT_P (operands
[1]))
591 else if (offsettable_memref_p (operands
[1]))
593 else if (GET_CODE (operands
[1]) == MEM
)
598 /* Check for the cases that the operand constraints are not
599 supposed to allow to happen. Abort if we get one,
600 because generating code for these cases is painful. */
602 if (optype0
== RNDOP
|| optype1
== RNDOP
)
605 /* If an operand is an unoffsettable memory ref, find a register
606 we can increment temporarily to make it refer to the second word. */
608 if (optype0
== MEMOP
)
609 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
611 if (optype1
== MEMOP
)
612 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
614 /* ??? Perhaps in some cases move double words
615 if there is a spare pair of floating regs. */
617 /* Ok, we can do one word at a time.
618 Normally we do the low-numbered word first,
619 but if either operand is autodecrementing then we
620 do the high-numbered word first.
622 In either case, set up in LATEHALF the operands to use
623 for the high-numbered word and in some cases alter the
624 operands in OPERANDS to be suitable for the low-numbered word. */
626 if (optype0
== REGOP
)
627 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
628 else if (optype0
== OFFSOP
)
629 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
631 latehalf
[0] = operands
[0];
633 if (optype1
== REGOP
)
634 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
635 else if (optype1
== OFFSOP
)
636 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
637 else if (optype1
== CNSTOP
)
639 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
640 split_double (operands
[1], &operands
[1], &latehalf
[1]);
641 else if (CONSTANT_P (operands
[1]))
642 latehalf
[1] = const0_rtx
;
645 latehalf
[1] = operands
[1];
647 /* If the first move would clobber the source of the second one,
648 do them in the other order.
650 RMS says "This happens only for registers;
651 such overlap can't happen in memory unless the user explicitly
652 sets it up, and that is an undefined circumstance."
654 but it happens on the sparc when loading parameter registers,
655 so I am going to define that circumstance, and make it work
658 if (optype0
== REGOP
&& optype1
== REGOP
659 && REGNO (operands
[0]) == REGNO (latehalf
[1]))
661 CC_STATUS_PARTIAL_INIT
;
662 /* Make any unoffsettable addresses point at high-numbered word. */
664 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
666 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
669 output_asm_insn (singlemove_string (latehalf
), latehalf
);
671 /* Undo the adds we just did. */
673 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
675 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
677 /* Do low-numbered word. */
678 return singlemove_string (operands
);
680 else if (optype0
== REGOP
&& optype1
!= REGOP
681 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
683 if (reg_mentioned_p (op0
, XEXP (op1
, 0))
684 && reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
686 /* If both halves of dest are used in the src memory address,
687 add the two regs and put them in the low reg (op0).
688 Then it works to load latehalf first. */
690 xops
[0] = latehalf
[0];
692 output_asm_insn ("adds %1,%0,%1", xops
);
693 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
694 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
696 /* Do the late half first. */
697 output_asm_insn (singlemove_string (latehalf
), latehalf
);
699 return singlemove_string (operands
);
702 /* Normal case: do the two words, low-numbered first. */
704 output_asm_insn (singlemove_string (operands
), operands
);
706 CC_STATUS_PARTIAL_INIT
;
707 /* Make any unoffsettable addresses point at high-numbered word. */
709 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
711 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
714 output_asm_insn (singlemove_string (latehalf
), latehalf
);
716 /* Undo the adds we just did. */
718 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
720 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
726 output_fp_move_double (operands
)
729 /* If the source operand is any sort of zero, use f0 instead. */
731 if (operands
[1] == CONST0_RTX (GET_MODE (operands
[1])))
732 operands
[1] = gen_rtx (REG
, DFmode
, F0_REGNUM
);
734 if (FP_REG_P (operands
[0]))
736 if (FP_REG_P (operands
[1]))
737 return "fmov.dd %1,%0";
738 if (GET_CODE (operands
[1]) == REG
)
740 output_asm_insn ("ixfr %1,%0", operands
);
741 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
742 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
745 if (operands
[1] == CONST0_RTX (DFmode
))
746 return "fmov.dd f0,%0";
747 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
749 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
750 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
751 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
754 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
756 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
757 cc_status
.mdep
= XEXP (operands
[1], 0);
758 return "fld.d %L1(%?r31),%0";
760 return "fld.d %1,%0";
762 else if (FP_REG_P (operands
[1]))
764 if (GET_CODE (operands
[0]) == REG
)
766 output_asm_insn ("fxfr %1,%0", operands
);
767 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
768 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
771 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
773 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
774 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
775 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
778 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
780 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
781 cc_status
.mdep
= XEXP (operands
[0], 0);
782 return "fst.d %1,%L0(%?r31)";
784 return "fst.d %1,%0";
792 /* Return a REG that occurs in ADDR with coefficient 1.
793 ADDR can be effectively incremented by incrementing REG. */
799 while (GET_CODE (addr
) == PLUS
)
801 if (GET_CODE (XEXP (addr
, 0)) == REG
)
802 addr
= XEXP (addr
, 0);
803 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
804 addr
= XEXP (addr
, 1);
805 else if (CONSTANT_P (XEXP (addr
, 0)))
806 addr
= XEXP (addr
, 1);
807 else if (CONSTANT_P (XEXP (addr
, 1)))
808 addr
= XEXP (addr
, 0);
812 if (GET_CODE (addr
) == REG
)
819 /* Return a template for a load instruction with mode MODE and
820 arguments from the string ARGS.
822 This string is in static storage. */
825 load_opcode (mode
, args
, reg
)
826 enum machine_mode mode
;
862 sprintf (buf
, "%s %s", opcode
, args
);
866 /* Return a template for a store instruction with mode MODE and
867 arguments from the string ARGS.
869 This string is in static storage. */
872 store_opcode (mode
, args
, reg
)
873 enum machine_mode mode
;
909 sprintf (buf
, "%s %s", opcode
, args
);
913 /* Output a store-in-memory whose operands are OPERANDS[0,1].
914 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
916 This function returns a template for an insn.
917 This is in static storage.
919 It may also output some insns directly.
920 It may alter the values of operands[0] and operands[1]. */
923 output_store (operands
)
926 enum machine_mode mode
= GET_MODE (operands
[0]);
927 rtx address
= XEXP (operands
[0], 0);
930 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
931 cc_status
.mdep
= address
;
933 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
934 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
935 && address
== cc_prev_status
.mdep
))
938 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
939 cc_prev_status
.mdep
= address
;
942 /* Store zero in two parts when appropriate. */
943 if (mode
== DFmode
&& operands
[1] == CONST0_RTX (DFmode
))
944 return store_opcode (DFmode
, "%r1,%L0(%?r31)", operands
[1]);
946 /* Code below isn't smart enough to move a doubleword in two parts,
947 so use output_move_double to do that in the cases that require it. */
948 if ((mode
== DImode
|| mode
== DFmode
)
949 && ! FP_REG_P (operands
[1]))
950 return output_move_double (operands
);
952 return store_opcode (mode
, "%r1,%L0(%?r31)", operands
[1]);
955 /* Output a load-from-memory whose operands are OPERANDS[0,1].
956 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
958 This function returns a template for an insn.
959 This is in static storage.
961 It may also output some insns directly.
962 It may alter the values of operands[0] and operands[1]. */
965 output_load (operands
)
968 enum machine_mode mode
= GET_MODE (operands
[0]);
969 rtx address
= XEXP (operands
[1], 0);
971 /* We don't bother trying to see if we know %hi(address).
972 This is because we are doing a load, and if we know the
973 %hi value, we probably also know that value in memory. */
974 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
975 cc_status
.mdep
= address
;
977 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
978 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
979 && address
== cc_prev_status
.mdep
980 && cc_prev_status
.mdep
== cc_status
.mdep
))
983 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
984 cc_prev_status
.mdep
= address
;
987 /* Code below isn't smart enough to move a doubleword in two parts,
988 so use output_move_double to do that in the cases that require it. */
989 if ((mode
== DImode
|| mode
== DFmode
)
990 && ! FP_REG_P (operands
[0]))
991 return output_move_double (operands
);
993 return load_opcode (mode
, "%L1(%?r31),%0", operands
[0]);
997 /* Load the address specified by OPERANDS[3] into the register
998 specified by OPERANDS[0].
1000 OPERANDS[3] may be the result of a sum, hence it could either be:
1005 (3) REG + REG + CONST_INT
1006 (4) REG + REG (special case of 3).
1008 Note that (3) is not a legitimate address.
1009 All cases are handled here. */
1012 output_load_address (operands
)
1017 if (CONSTANT_P (operands
[3]))
1019 output_asm_insn ("mov %3,%0", operands
);
1023 if (REG_P (operands
[3]))
1025 if (REGNO (operands
[0]) != REGNO (operands
[3]))
1026 output_asm_insn ("shl %?r0,%3,%0", operands
);
1030 if (GET_CODE (operands
[3]) != PLUS
)
1033 base
= XEXP (operands
[3], 0);
1034 offset
= XEXP (operands
[3], 1);
1036 if (GET_CODE (base
) == CONST_INT
)
1043 if (GET_CODE (offset
) != CONST_INT
)
1045 /* Operand is (PLUS (REG) (REG)). */
1047 offset
= const0_rtx
;
1053 operands
[7] = offset
;
1054 CC_STATUS_PARTIAL_INIT
;
1055 if (SMALL_INT (offset
))
1056 output_asm_insn ("adds %7,%6,%0", operands
);
1058 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands
);
1060 else if (GET_CODE (base
) == PLUS
)
1062 operands
[6] = XEXP (base
, 0);
1063 operands
[7] = XEXP (base
, 1);
1064 operands
[8] = offset
;
1066 CC_STATUS_PARTIAL_INIT
;
1067 if (SMALL_INT (offset
))
1068 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands
);
1070 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands
);
1077 /* Output code to place a size count SIZE in register REG.
1078 Because block moves are pipelined, we don't include the
1079 first element in the transfer of SIZE to REG.
1080 For this, we subtract ALIGN. (Actually, I think it is not
1081 right to subtract on this machine, so right now we don't.) */
1084 output_size_for_block_move (size
, reg
, align
)
1085 rtx size
, reg
, align
;
1090 xoperands
[1] = size
;
1091 xoperands
[2] = align
;
1094 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
1095 output_asm_insn (singlemove_string (xoperands
), xoperands
);
1097 if (GET_CODE (size
) == REG
)
1098 output_asm_insn ("sub %2,%1,%0", xoperands
);
1102 = gen_rtx (CONST_INT
, VOIDmode
, INTVAL (size
) - INTVAL (align
));
1103 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
1104 output_asm_insn ("mov %1,%0", xoperands
);
1109 /* Emit code to perform a block move.
1111 OPERANDS[0] is the destination.
1112 OPERANDS[1] is the source.
1113 OPERANDS[2] is the size.
1114 OPERANDS[3] is the known safe alignment.
1115 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1118 output_block_move (operands
)
1121 /* A vector for our computed operands. Note that load_output_address
1122 makes use of (and can clobber) up to the 8th element of this vector. */
1125 static int movstrsi_label
= 0;
1127 rtx temp1
= operands
[4];
1128 rtx alignrtx
= operands
[3];
1129 int align
= INTVAL (alignrtx
);
1132 xoperands
[0] = operands
[0];
1133 xoperands
[1] = operands
[1];
1134 xoperands
[2] = temp1
;
1136 /* We can't move more than four bytes at a time
1137 because we have only one register to move them through. */
1141 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, 4);
1144 /* Recognize special cases of block moves. These occur
1145 when GNU C++ is forced to treat something as BLKmode
1146 to keep it in memory, when its mode could be represented
1147 with something smaller.
1149 We cannot do this for global variables, since we don't know
1150 what pages they don't cross. Sigh. */
1151 if (GET_CODE (operands
[2]) == CONST_INT
1152 && ! CONSTANT_ADDRESS_P (operands
[0])
1153 && ! CONSTANT_ADDRESS_P (operands
[1]))
1155 int size
= INTVAL (operands
[2]);
1156 rtx op0
= xoperands
[0];
1157 rtx op1
= xoperands
[1];
1159 if ((align
& 3) == 0 && (size
& 3) == 0 && (size
>> 2) <= 16)
1161 if (memory_address_p (SImode
, plus_constant (op0
, size
))
1162 && memory_address_p (SImode
, plus_constant (op1
, size
)))
1164 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1165 for (i
= (size
>>2)-1; i
>= 0; i
--)
1167 xoperands
[0] = plus_constant (op0
, i
* 4);
1168 xoperands
[1] = plus_constant (op1
, i
* 4);
1169 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1175 else if ((align
& 1) == 0 && (size
& 1) == 0 && (size
>> 1) <= 16)
1177 if (memory_address_p (HImode
, plus_constant (op0
, size
))
1178 && memory_address_p (HImode
, plus_constant (op1
, size
)))
1180 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1181 for (i
= (size
>>1)-1; i
>= 0; i
--)
1183 xoperands
[0] = plus_constant (op0
, i
* 2);
1184 xoperands
[1] = plus_constant (op1
, i
* 2);
1185 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1191 else if (size
<= 16)
1193 if (memory_address_p (QImode
, plus_constant (op0
, size
))
1194 && memory_address_p (QImode
, plus_constant (op1
, size
)))
1196 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1197 for (i
= size
-1; i
>= 0; i
--)
1199 xoperands
[0] = plus_constant (op0
, i
);
1200 xoperands
[1] = plus_constant (op1
, i
);
1201 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1209 /* Since we clobber untold things, nix the condition codes. */
1212 /* This is the size of the transfer.
1213 Either use the register which already contains the size,
1214 or use a free register (used by no operands). */
1215 output_size_for_block_move (operands
[2], operands
[4], alignrtx
);
1218 /* Also emit code to decrement the size value by ALIGN. */
1219 zoperands
[0] = operands
[0];
1220 zoperands
[3] = plus_constant (operands
[0], align
);
1221 output_load_address (zoperands
);
1224 /* Generate number for unique label. */
1226 xoperands
[3] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
1228 /* Calculate the size of the chunks we will be trying to move first. */
1231 if ((align
& 3) == 0)
1233 else if ((align
& 1) == 0)
1239 /* Copy the increment (negative) to a register for bla insn. */
1241 xoperands
[4] = gen_rtx (CONST_INT
, VOIDmode
, - chunk_size
);
1242 xoperands
[5] = operands
[5];
1243 output_asm_insn ("adds %4,%?r0,%5", xoperands
);
1245 /* Predecrement the loop counter. This happens again also in the `bla'
1246 instruction which precedes the loop, but we need to have it done
1247 two times before we enter the loop because of the bizarre semantics
1248 of the bla instruction. */
1250 output_asm_insn ("adds %5,%2,%2", xoperands
);
1252 /* Check for the case where the original count was less than or equal to
1253 zero. Avoid going through the loop at all if the original count was
1254 indeed less than or equal to zero. Note that we treat the count as
1255 if it were a signed 32-bit quantity here, rather than an unsigned one,
1256 even though we really shouldn't. We have to do this because of the
1257 semantics of the `ble' instruction, which assume that the count is
1258 a signed 32-bit value. Anyway, in practice it won't matter because
1259 nobody is going to try to do a memcpy() of more than half of the
1260 entire address space (i.e. 2 gigabytes) anyway. */
1262 output_asm_insn ("bc .Le%3", xoperands
);
1264 /* Make available a register which is a temporary. */
1266 xoperands
[6] = operands
[6];
1268 /* Now the actual loop.
1269 In xoperands, elements 1 and 0 are the input and output vectors.
1270 Element 2 is the loop index. Element 5 is the increment. */
1272 output_asm_insn ("subs %1,%5,%1", xoperands
);
1273 output_asm_insn ("bla %5,%2,.Lm%3", xoperands
);
1274 output_asm_insn ("adds %0,%2,%6", xoperands
);
1275 output_asm_insn ("\n.Lm%3:", xoperands
); /* Label for bla above. */
1276 output_asm_insn ("\n.Ls%3:", xoperands
); /* Loop start label. */
1277 output_asm_insn ("adds %5,%6,%6", xoperands
);
1279 /* NOTE: The code here which is supposed to handle the cases where the
1280 sources and destinations are known to start on a 4 or 2 byte boundary
1281 are currently broken. They fail to do anything about the overflow
1282 bytes which might still need to be copied even after we have copied
1283 some number of words or halfwords. Thus, for now we use the lowest
1284 common denominator, i.e. the code which just copies some number of
1285 totally unaligned individual bytes. (See the calculation of
1286 chunk_size above. */
1288 if (chunk_size
== 4)
1290 output_asm_insn ("ld.l %2(%1),%?r31", xoperands
);
1291 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1292 output_asm_insn ("st.l %?r31,8(%6)", xoperands
);
1294 else if (chunk_size
== 2)
1296 output_asm_insn ("ld.s %2(%1),%?r31", xoperands
);
1297 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1298 output_asm_insn ("st.s %?r31,4(%6)", xoperands
);
1300 else /* chunk_size == 1 */
1302 output_asm_insn ("ld.b %2(%1),%?r31", xoperands
);
1303 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1304 output_asm_insn ("st.b %?r31,2(%6)", xoperands
);
1306 output_asm_insn ("\n.Le%3:", xoperands
); /* Here if count <= 0. */
1311 /* Output a delayed branch insn with the delay insn in its
1312 branch slot. The delayed branch insn template is in TEMPLATE,
1313 with operands OPERANDS. The insn in its delay slot is INSN.
1315 As a special case, since we know that all memory transfers are via
1316 ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
1317 reference around the branch as
1321 ld/st l%x(%?r31),...
1323 As another special case, we handle loading (SYMBOL_REF ...) and
1324 other large constants around branches as well:
1333 output_delayed_branch (template, operands
, insn
)
1338 rtx src
= XVECEXP (PATTERN (insn
), 0, 1);
1339 rtx dest
= XVECEXP (PATTERN (insn
), 0, 0);
1341 /* See if we are doing some branch together with setting some register
1342 to some 32-bit value which does (or may) have some of the high-order
1343 16 bits set. If so, we need to set the register in two stages. One
1344 stage must be done before the branch, and the other one can be done
1345 in the delay slot. */
1347 if ( (GET_CODE (src
) == CONST_INT
1348 && ((unsigned) INTVAL (src
) & (unsigned) 0xffff0000) != (unsigned) 0)
1349 || (GET_CODE (src
) == SYMBOL_REF
)
1350 || (GET_CODE (src
) == LABEL_REF
)
1351 || (GET_CODE (src
) == CONST
))
1354 xoperands
[0] = dest
;
1357 CC_STATUS_PARTIAL_INIT
;
1358 /* Output the `orh' insn. */
1359 output_asm_insn ("orh %H1,%?r0,%0", xoperands
);
1361 /* Output the branch instruction next. */
1362 output_asm_insn (template, operands
);
1364 /* Now output the `or' insn. */
1365 output_asm_insn ("or %L1,%0,%0", xoperands
);
1367 else if ((GET_CODE (src
) == MEM
1368 && CONSTANT_ADDRESS_P (XEXP (src
, 0)))
1369 || (GET_CODE (dest
) == MEM
1370 && CONSTANT_ADDRESS_P (XEXP (dest
, 0))))
1373 char *split_template
;
1374 xoperands
[0] = dest
;
1377 /* Output the `orh' insn. */
1378 if (GET_CODE (src
) == MEM
)
1380 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1381 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1382 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
1385 output_asm_insn ("orh %h1,%?r0,%?r31", xoperands
);
1387 split_template
= load_opcode (GET_MODE (dest
),
1388 "%L1(%?r31),%0", dest
);
1392 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1393 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1394 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
1397 output_asm_insn ("orh %h0,%?r0,%?r31", xoperands
);
1399 split_template
= store_opcode (GET_MODE (dest
),
1400 "%r1,%L0(%?r31)", src
);
1403 /* Output the branch instruction next. */
1404 output_asm_insn (template, operands
);
1406 /* Now output the load or store.
1407 No need to do a CC_STATUS_INIT, because we are branching anyway. */
1408 output_asm_insn (split_template
, xoperands
);
1412 int insn_code_number
;
1413 rtx pat
= gen_rtx (SET
, VOIDmode
, dest
, src
);
1414 rtx delay_insn
= gen_rtx (INSN
, VOIDmode
, 0, 0, 0, pat
, -1, 0, 0);
1417 /* Output the branch instruction first. */
1418 output_asm_insn (template, operands
);
1420 /* Now recognize the insn which we put in its delay slot.
1421 We must do this after outputting the branch insn,
1422 since operands may just be a pointer to `recog_operand'. */
1423 INSN_CODE (delay_insn
) = insn_code_number
= recog (pat
, delay_insn
);
1424 if (insn_code_number
== -1)
1427 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1429 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1430 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1433 insn_extract (delay_insn
);
1434 if (! constrain_operands (insn_code_number
, 1))
1435 fatal_insn_not_found (delay_insn
);
1437 template = insn_template
[insn_code_number
];
1439 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1440 output_asm_insn (template, recog_operand
);
1446 /* Output a newly constructed insn DELAY_INSN. */
1448 output_delay_insn (delay_insn
)
1452 int insn_code_number
;
1455 /* Now recognize the insn which we put in its delay slot.
1456 We must do this after outputting the branch insn,
1457 since operands may just be a pointer to `recog_operand'. */
1458 insn_code_number
= recog_memoized (delay_insn
);
1459 if (insn_code_number
== -1)
1462 /* Extract the operands of this delay insn. */
1463 INSN_CODE (delay_insn
) = insn_code_number
;
1464 insn_extract (delay_insn
);
1466 /* It is possible that this insn has not been properly scanned by final
1467 yet. If this insn's operands don't appear in the peephole's
1468 actual operands, then they won't be fixed up by final, so we
1469 make sure they get fixed up here. -- This is a kludge. */
1470 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1472 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1473 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1476 #ifdef REGISTER_CONSTRAINTS
1477 if (! constrain_operands (insn_code_number
))
1481 cc_prev_status
= cc_status
;
1483 /* Update `cc_status' for this instruction.
1484 The instruction's output routine may change it further.
1485 If the output routine for a jump insn needs to depend
1486 on the cc status, it should look at cc_prev_status. */
1488 NOTICE_UPDATE_CC (PATTERN (delay_insn
), delay_insn
);
1490 /* Now get the template for what this insn would
1491 have been, without the branch. */
1493 template = insn_template
[insn_code_number
];
1495 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1496 output_asm_insn (template, recog_operand
);
1500 /* Special routine to convert an SFmode value represented as a
1501 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1502 We convert the value from a double precision floating-point
1503 value to single precision first, and thence to a bit-wise
1504 equivalent unsigned long value. This routine is used when
1505 generating an immediate move of an SFmode value directly
1506 into a general register because the svr4 assembler doesn't
1507 grok floating literals in instruction operand contexts. */
1510 sfmode_constant_to_ulong (x
)
1514 union { float f
; unsigned long i
; } u2
;
1516 if (GET_CODE (x
) != CONST_DOUBLE
|| GET_MODE (x
) != SFmode
)
1519 #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1520 error IEEE emulation needed
1522 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1527 /* This function generates the assembly code for function entry.
1528 The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1530 ASM_FILE is a stdio stream to output the code to.
1531 SIZE is an int: how many units of temporary storage to allocate.
1533 Refer to the array `regs_ever_live' to determine which registers
1534 to save; `regs_ever_live[I]' is nonzero if register number I
1535 is ever used in the function. This macro is responsible for
1536 knowing which registers should not be saved even if used.
1538 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1539 between the new `fp' value and the new `sp' value after the
1540 prologue is done. `frame_upper_bytes' is the count of bytes
1541 that will lie between the new `fp' and the *old* `sp' value
1542 after the new `fp' is setup (in the prologue). The upper
1543 part of each frame always includes at least 2 words (8 bytes)
1544 to hold the saved frame pointer and the saved return address.
1546 The svr4 ABI for the i860 now requires that the values of the
1547 stack pointer and frame pointer registers be kept aligned to
1548 16-byte boundaries at all times. We obey that restriction here.
1550 The svr4 ABI for the i860 is entirely vague when it comes to specifying
1551 exactly where the "preserved" registers should be saved. The native
1552 svr4 C compiler I now have doesn't help to clarify the requirements
1553 very much because it is plainly out-of-date and non-ABI-compliant
1554 (in at least one important way, i.e. how it generates function
1557 The native svr4 C compiler saves the "preserved" registers (i.e.
1558 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1559 offsets from the frame pointer).
1561 Previous versions of GCC also saved the "preserved" registers in the
1562 "negative" part of the frame, but they saved them using positive
1563 offsets from the (adjusted) stack pointer (after it had been adjusted
1564 to allocate space for the new frame). That's just plain wrong
1565 because if the current function calls alloca(), the stack pointer
1566 will get moved, and it will be impossible to restore the registers
1567 properly again after that.
1569 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1570 by copying their values either into various "preserved" registers or
1571 into stack slots in the lower part of the current frame (as seemed
1572 appropriate, depending upon subsequent usage of these values).
1574 Here we want to save the preserved registers at some offset from the
1575 frame pointer register so as to avoid any possible problems arising
1576 from calls to alloca(). We can either save them at small positive
1577 offsets from the frame pointer, or at small negative offsets from
1578 the frame pointer. If we save them at small negative offsets from
1579 the frame pointer (i.e. in the lower part of the frame) then we
1580 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1581 many bytes of space we plan to use in the lower part of the frame
1582 for this purpose. Since other parts of the compiler reference the
1583 value of STARTING_FRAME_OFFSET long before final() calls this function,
1584 we would have to go ahead and assume the worst-case storage requirements
1585 for saving all of the "preserved" registers (and use that number, i.e.
1586 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1587 the lower part of the frame. That could potentially be very wasteful,
1588 and that wastefulness could really hamper people compiling for embedded
1589 i860 targets with very tight limits on stack space. Thus, we choose
1590 here to save the preserved registers in the upper part of the
1591 frame, so that we can decide at the very last minute how much (or how
1592 little) space we must allocate for this purpose.
1594 To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1595 registers must always be saved so that the saved values of registers
1596 with higher numbers are at higher addresses. We obey that restriction
1599 There are two somewhat different ways that you can generate prologues
1600 here... i.e. pedantically ABI-compliant, and the "other" way. The
1601 "other" way is more consistent with what is currently generated by the
1602 "native" svr4 C compiler for the i860. That's important if you want
1603 to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1604 The SVR4 SDB for the i860 insists on having function prologues be
1607 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1608 in the i860svr4.h file. (By default this is *not* defined).
1610 The differences between the ABI-compliant and non-ABI-compliant prologues
1611 are that (a) the ABI version seems to require the use of *signed*
1612 (rather than unsigned) adds and subtracts, and (b) the ordering of
1613 the various steps (e.g. saving preserved registers, saving the
1614 return address, setting up the new frame pointer value) is different.
1616 For strict ABI compliance, it seems to be the case that the very last
1617 thing that is supposed to happen in the prologue is getting the frame
1618 pointer set to its new value (but only after everything else has
1619 already been properly setup). We do that here, but only if the symbol
1620 I860_STRICT_ABI_PROLOGUES is defined.
1623 #ifndef STACK_ALIGNMENT
1624 #define STACK_ALIGNMENT 16
1627 extern char call_used_regs
[];
1628 extern int leaf_function_p ();
1630 char *current_function_original_name
;
1632 static int must_preserve_r1
;
1633 static unsigned must_preserve_bytes
;
1636 function_prologue (asm_file
, local_bytes
)
1637 register FILE *asm_file
;
1638 register unsigned local_bytes
;
1640 register unsigned frame_lower_bytes
;
1641 register unsigned frame_upper_bytes
;
1642 register unsigned total_fsize
;
1643 register unsigned preserved_reg_bytes
= 0;
1644 register unsigned i
;
1645 register unsigned preserved_so_far
= 0;
1647 must_preserve_r1
= (optimize
< 2 || ! leaf_function_p ());
1648 must_preserve_bytes
= 4 + (must_preserve_r1
? 4 : 0);
1650 /* Count registers that need preserving. Ignore r0. It never needs
1653 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
1655 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1656 preserved_reg_bytes
+= 4;
1659 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1661 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1663 /* The upper part of each frame will contain the saved fp,
1664 the saved r1, and stack slots for all of the other "preserved"
1665 registers that we find we will need to save & restore. */
1667 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
1669 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1672 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1674 total_fsize
= frame_upper_bytes
+ frame_lower_bytes
;
1676 #ifndef I860_STRICT_ABI_PROLOGUES
1678 /* There are two kinds of function prologues.
1679 You use the "small" version if the total frame size is
1680 small enough so that it can fit into an immediate 16-bit
1681 value in one instruction. Otherwise, you use the "large"
1682 version of the function prologue. */
1684 if (total_fsize
> 0x7fff)
1686 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1687 but the native C compiler on svr4 uses `addu'. */
1689 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1690 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1692 /* Save the old frame pointer. */
1694 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1695 i860_reg_prefix
, i860_reg_prefix
);
1697 /* Setup the new frame pointer. The ABI sez to do this after
1698 preserving registers (using adds), but that's not what the
1699 native C compiler on svr4 does. */
1701 fprintf (asm_file
, "\taddu 0,%ssp,%sfp\n",
1702 i860_reg_prefix
, i860_reg_prefix
);
1704 /* Get the value of frame_lower_bytes into r31. */
1706 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1707 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1708 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1709 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1711 /* Now re-adjust the stack pointer using the value in r31.
1712 The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1714 fprintf (asm_file
, "\tsubu %ssp,%sr31,%ssp\n",
1715 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1717 /* Preserve registers. The ABI sez to do this before setting
1718 up the new frame pointer, but that's not what the native
1719 C compiler on svr4 does. */
1721 for (i
= 1; i
< 32; i
++)
1722 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1723 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1724 i860_reg_prefix
, reg_names
[i
],
1725 must_preserve_bytes
+ (4 * preserved_so_far
++),
1728 for (i
= 32; i
< 64; i
++)
1729 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1730 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1731 i860_reg_prefix
, reg_names
[i
],
1732 must_preserve_bytes
+ (4 * preserved_so_far
++),
1735 /* Save the return address. */
1737 if (must_preserve_r1
)
1738 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1739 i860_reg_prefix
, i860_reg_prefix
);
1743 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1744 but the native C compiler on svr4 uses `addu'. */
1746 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1747 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1749 /* Save the old frame pointer. */
1751 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1752 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1754 /* Setup the new frame pointer. The ABI sez to do this after
1755 preserving registers and after saving the return address,
1756 (and its saz to do this using adds), but that's not what the
1757 native C compiler on svr4 does. */
1759 fprintf (asm_file
, "\taddu %d,%ssp,%sfp\n",
1760 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1762 /* Preserve registers. The ABI sez to do this before setting
1763 up the new frame pointer, but that's not what the native
1764 compiler on svr4 does. */
1766 for (i
= 1; i
< 32; i
++)
1767 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1768 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1769 i860_reg_prefix
, reg_names
[i
],
1770 must_preserve_bytes
+ (4 * preserved_so_far
++),
1773 for (i
= 32; i
< 64; i
++)
1774 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1775 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1776 i860_reg_prefix
, reg_names
[i
],
1777 must_preserve_bytes
+ (4 * preserved_so_far
++),
1780 /* Save the return address. The ABI sez to do this earlier,
1781 and also via an offset from %sp, but the native C compiler
1782 on svr4 does it later (i.e. now) and uses an offset from
1785 if (must_preserve_r1
)
1786 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1787 i860_reg_prefix
, i860_reg_prefix
);
1790 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1792 /* There are two kinds of function prologues.
1793 You use the "small" version if the total frame size is
1794 small enough so that it can fit into an immediate 16-bit
1795 value in one instruction. Otherwise, you use the "large"
1796 version of the function prologue. */
1798 if (total_fsize
> 0x7fff)
1800 /* Adjust the stack pointer (thereby allocating a new frame). */
1802 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1803 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1805 /* Save the caller's frame pointer. */
1807 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1808 i860_reg_prefix
, i860_reg_prefix
);
1810 /* Save return address. */
1812 if (must_preserve_r1
)
1813 fprintf (asm_file
, "\tst.l %sr1,4(%ssp)\n",
1814 i860_reg_prefix
, i860_reg_prefix
);
1816 /* Get the value of frame_lower_bytes into r31 for later use. */
1818 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1819 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1820 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1821 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1823 /* Now re-adjust the stack pointer using the value in r31. */
1825 fprintf (asm_file
, "\tsubs %ssp,%sr31,%ssp\n",
1826 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1828 /* Pre-compute value to be used as the new frame pointer. */
1830 fprintf (asm_file
, "\tadds %ssp,%sr31,%sr31\n",
1831 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1833 /* Preserve registers. */
1835 for (i
= 1; i
< 32; i
++)
1836 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1837 fprintf (asm_file
, "\tst.l %s%s,%d(%sr31)\n",
1838 i860_reg_prefix
, reg_names
[i
],
1839 must_preserve_bytes
+ (4 * preserved_so_far
++),
1842 for (i
= 32; i
< 64; i
++)
1843 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1844 fprintf (asm_file
, "\tfst.l %s%s,%d(%sr31)\n",
1845 i860_reg_prefix
, reg_names
[i
],
1846 must_preserve_bytes
+ (4 * preserved_so_far
++),
1849 /* Actually set the new value of the frame pointer. */
1851 fprintf (asm_file
, "\tmov %sr31,%sfp\n",
1852 i860_reg_prefix
, i860_reg_prefix
);
1856 /* Adjust the stack pointer. */
1858 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1859 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1861 /* Save the caller's frame pointer. */
1863 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1864 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1866 /* Save the return address. */
1868 if (must_preserve_r1
)
1869 fprintf (asm_file
, "\tst.l %sr1,%d(%ssp)\n",
1870 i860_reg_prefix
, frame_lower_bytes
+ 4, i860_reg_prefix
);
1872 /* Preserve registers. */
1874 for (i
= 1; i
< 32; i
++)
1875 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1876 fprintf (asm_file
, "\tst.l %s%s,%d(%ssp)\n",
1877 i860_reg_prefix
, reg_names
[i
],
1878 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1881 for (i
= 32; i
< 64; i
++)
1882 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1883 fprintf (asm_file
, "\tfst.l %s%s,%d(%ssp)\n",
1884 i860_reg_prefix
, reg_names
[i
],
1885 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1888 /* Setup the new frame pointer. */
1890 fprintf (asm_file
, "\tadds %d,%ssp,%sfp\n",
1891 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1893 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1895 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1896 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file
);
1897 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1900 /* This function generates the assembly code for function exit.
1901 The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
1903 ASM_FILE is a stdio stream to output the code to.
1904 SIZE is an int: how many units of temporary storage to allocate.
1906 The function epilogue should not depend on the current stack pointer!
1907 It should use the frame pointer only. This is mandatory because
1908 of alloca; we also take advantage of it to omit stack adjustments
1911 Note that when we go to restore the preserved register values we must
1912 not try to address their slots by using offsets from the stack pointer.
1913 That's because the stack pointer may have been moved during the function
1914 execution due to a call to alloca(). Rather, we must restore all
1915 preserved registers via offsets from the frame pointer value.
1917 Note also that when the current frame is being "popped" (by adjusting
1918 the value of the stack pointer) on function exit, we must (for the
1919 sake of alloca) set the new value of the stack pointer based upon
1920 the current value of the frame pointer. We can't just add what we
1921 believe to be the (static) frame size to the stack pointer because
1922 if we did that, and alloca() had been called during this function,
1923 we would end up returning *without* having fully deallocated all of
1924 the space grabbed by alloca. If that happened, and a function
1925 containing one or more alloca() calls was called over and over again,
1926 then the stack would grow without limit!
1928 Finally note that the epilogues generated here are completely ABI
1929 compliant. They go out of their way to insure that the value in
1930 the frame pointer register is never less than the value in the stack
1931 pointer register. It's not clear why this relationship needs to be
1932 maintained at all times, but maintaining it only costs one extra
1933 instruction, so what the hell.
1936 /* This corresponds to a version 4 TDESC structure. Lower numbered
1937 versions successively omit the last word of the structure. We
1938 don't try to handle version 5 here. */
1940 typedef struct TDESC_flags
{
1943 int callable_block
:1;
1945 int fregs
:6; /* fp regs 2-7 */
1946 int iregs
:16; /* regs 0-15 */
1949 typedef struct TDESC
{
1951 int integer_reg_offset
; /* same as must_preserve_bytes */
1952 int floating_point_reg_offset
;
1953 unsigned int positive_frame_size
; /* same as frame_upper_bytes */
1954 unsigned int negative_frame_size
; /* same as frame_lower_bytes */
1958 function_epilogue (asm_file
, local_bytes
)
1959 register FILE *asm_file
;
1960 register unsigned local_bytes
;
1962 register unsigned frame_upper_bytes
;
1963 register unsigned frame_lower_bytes
;
1964 register unsigned preserved_reg_bytes
= 0;
1965 register unsigned i
;
1966 register unsigned restored_so_far
= 0;
1967 register unsigned int_restored
;
1968 register unsigned mask
;
1969 unsigned intflags
=0;
1970 register TDESC_flags
*flags
= (TDESC_flags
*) &intflags
;
1973 flags
->reg_packing
= 1;
1974 flags
->iregs
= 8; /* old fp always gets saved */
1976 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1978 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1980 /* Count the number of registers that were preserved in the prologue.
1981 Ignore r0. It is never preserved. */
1983 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
1985 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1986 preserved_reg_bytes
+= 4;
1989 /* The upper part of each frame will contain only saved fp,
1990 the saved r1, and stack slots for all of the other "preserved"
1991 registers that we find we will need to save & restore. */
1993 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
1995 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
1998 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
2000 /* Restore all of the "preserved" registers that need restoring. */
2004 for (i
= 1; i
< 32; i
++, mask
<<=1)
2005 if (regs_ever_live
[i
] && ! call_used_regs
[i
]) {
2006 fprintf (asm_file
, "\tld.l %d(%sfp),%s%s\n",
2007 must_preserve_bytes
+ (4 * restored_so_far
++),
2008 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
2009 if (i
> 3 && i
< 16)
2010 flags
->iregs
|= mask
;
2013 int_restored
= restored_so_far
;
2016 for (i
= 32; i
< 64; i
++) {
2017 if (regs_ever_live
[i
] && ! call_used_regs
[i
]) {
2018 fprintf (asm_file
, "\tfld.l %d(%sfp),%s%s\n",
2019 must_preserve_bytes
+ (4 * restored_so_far
++),
2020 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
2021 if (i
> 33 & i
< 40)
2022 flags
->fregs
|= mask
;
2024 if (i
> 33 && i
< 40)
2028 /* Get the value we plan to use to restore the stack pointer into r31. */
2030 fprintf (asm_file
, "\tadds %d,%sfp,%sr31\n",
2031 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
2033 /* Restore the return address and the old frame pointer. */
2035 if (must_preserve_r1
) {
2036 fprintf (asm_file
, "\tld.l 4(%sfp),%sr1\n",
2037 i860_reg_prefix
, i860_reg_prefix
);
2041 fprintf (asm_file
, "\tld.l 0(%sfp),%sfp\n",
2042 i860_reg_prefix
, i860_reg_prefix
);
2044 /* Return and restore the old stack pointer value. */
2046 fprintf (asm_file
, "\tbri %sr1\n\tmov %sr31,%ssp\n",
2047 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
2049 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
2050 if (! frame_lower_bytes
) {
2052 if (! frame_upper_bytes
) {
2054 if (restored_so_far
== int_restored
) /* No FP saves */
2058 assemble_name(asm_file
,current_function_original_name
);
2059 fputs(".TDESC:\n", asm_file
);
2060 fprintf(asm_file
, "%s 0x%0x\n", ASM_LONG
, intflags
);
2061 fprintf(asm_file
, "%s %d\n", ASM_LONG
,
2062 int_restored
? must_preserve_bytes
: 0);
2063 if (flags
->version
> 1) {
2064 fprintf(asm_file
, "%s %d\n", ASM_LONG
,
2065 (restored_so_far
== int_restored
) ? 0 : must_preserve_bytes
+
2066 (4 * int_restored
));
2067 if (flags
->version
> 2) {
2068 fprintf(asm_file
, "%s %d\n", ASM_LONG
, frame_upper_bytes
);
2069 if (flags
->version
> 3)
2070 fprintf(asm_file
, "%s %d\n", ASM_LONG
, frame_lower_bytes
);
2074 fprintf(asm_file
, "%s ", ASM_LONG
);
2075 assemble_name(asm_file
, current_function_original_name
);
2076 fprintf(asm_file
, "\n%s ", ASM_LONG
);
2077 assemble_name(asm_file
, current_function_original_name
);
2078 fputs(".TDESC\n", asm_file
);