1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (finput
, t
)
100 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
103 pname
= IDENTIFIER_POINTER (t
);
105 if (strcmp (pname
, "align") == 0)
113 } while (c
== ' ' || c
== '\t');
117 while (c
>= '0' && c
<= '9')
119 if (s
< buf
+ sizeof buf
- 1)
125 /* We had to read a non-numerical character to get out of the
126 while loop---often a newline. So, we have to put it back to
127 make sure we continue to parse everything properly. */
134 /* Return to last alignment. */
135 align
= i960_last_maxbitalignment
/ 8;
142 i960_last_maxbitalignment
= i960_maxbitalignment
;
143 i960_maxbitalignment
= align
* 8;
147 /* Silently ignore bad values. */
151 /* NOTE: ic960 R3.0 pragma align definition:
153 #pragma align [(size)] | (identifier=size[,...])
154 #pragma noalign [(identifier)[,...]]
156 (all parens are optional)
158 - size is [1,2,4,8,16]
159 - noalign means size==1
160 - applies only to component elements of a struct (and union?)
161 - identifier applies to structure tag (only)
162 - missing identifier means next struct
164 - alignment rules for bitfields need more investigation */
169 /* Should be pragma 'far' or equivalent for callx/balx here. */
174 /* Initialize variables before compiling any files. */
179 if (TARGET_IC_COMPAT2_0
)
181 i960_maxbitalignment
= 8;
182 i960_last_maxbitalignment
= 128;
186 i960_maxbitalignment
= 128;
187 i960_last_maxbitalignment
= 8;
191 /* Return true if OP can be used as the source of an fp move insn. */
194 fpmove_src_operand (op
, mode
)
196 enum machine_mode mode
;
198 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
202 /* Return true if OP is a register or zero. */
205 reg_or_zero_operand (op
, mode
)
207 enum machine_mode mode
;
209 return register_operand (op
, mode
) || op
== const0_rtx
;
213 /* Return truth value of whether OP can be used as an operands in a three
214 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
217 arith_operand (op
, mode
)
219 enum machine_mode mode
;
221 return (register_operand (op
, mode
) || literal (op
, mode
));
224 /* Return truth value of whether OP can be used as an operands in a three
225 address logic insn, possibly complementing OP, of mode MODE. */
228 logic_operand (op
, mode
)
230 enum machine_mode mode
;
232 return (register_operand (op
, mode
)
233 || (GET_CODE (op
) == CONST_INT
234 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
237 /* Return true if OP is a register or a valid floating point literal. */
240 fp_arith_operand (op
, mode
)
242 enum machine_mode mode
;
244 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
247 /* Return true is OP is a register or a valid signed integer literal. */
250 signed_arith_operand (op
, mode
)
252 enum machine_mode mode
;
254 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
257 /* Return truth value of whether OP is a integer which fits the
258 range constraining immediate operands in three-address insns. */
263 enum machine_mode mode
;
265 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
268 /* Return true if OP is a float constant of 1. */
271 fp_literal_one (op
, mode
)
273 enum machine_mode mode
;
275 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
278 /* Return true if OP is a float constant of 0. */
281 fp_literal_zero (op
, mode
)
283 enum machine_mode mode
;
285 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
288 /* Return true if OP is a valid floating point literal. */
293 enum machine_mode mode
;
295 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
298 /* Return true if OP is a valid signed immediate constant. */
301 signed_literal(op
, mode
)
303 enum machine_mode mode
;
305 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
308 /* Return truth value of statement that OP is a symbolic memory
309 operand of mode MODE. */
312 symbolic_memory_operand (op
, mode
)
314 enum machine_mode mode
;
316 if (GET_CODE (op
) == SUBREG
)
317 op
= SUBREG_REG (op
);
318 if (GET_CODE (op
) != MEM
)
321 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
322 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
325 /* Return truth value of whether OP is EQ or NE. */
330 enum machine_mode mode
;
332 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
335 /* OP is an integer register or a constant. */
338 arith32_operand (op
, mode
)
340 enum machine_mode mode
;
342 if (register_operand (op
, mode
))
344 return (CONSTANT_P (op
));
347 /* Return true if OP is an integer constant which is a power of 2. */
350 power2_operand (op
,mode
)
352 enum machine_mode mode
;
354 if (GET_CODE (op
) != CONST_INT
)
357 return exact_log2 (INTVAL (op
)) >= 0;
360 /* Return true if OP is an integer constant which is the complement of a
364 cmplpower2_operand (op
, mode
)
366 enum machine_mode mode
;
368 if (GET_CODE (op
) != CONST_INT
)
371 return exact_log2 (~ INTVAL (op
)) >= 0;
374 /* If VAL has only one bit set, return the index of that bit. Otherwise
383 for (i
= 0; val
!= 0; i
++, val
>>= 1)
395 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
396 The return value indicates how many consecutive non-zero bits exist
397 if this is a mask. This is the same as the next function, except that
398 it does not indicate what the start and stop bit positions are. */
404 register int start
, end
, i
;
407 for (i
= 0; val
!= 0; val
>>= 1, i
++)
417 /* Still looking for the first bit. */
421 /* We've seen the start of a bit sequence, and now a zero. There
422 must be more one bits, otherwise we would have exited the loop.
423 Therefore, it is not a mask. */
428 /* The bit string has ones from START to END bit positions only. */
429 return end
- start
+ 1;
432 /* If VAL is a mask, then return nonzero, with S set to the starting bit
433 position and E set to the ending bit position of the mask. The return
434 value indicates how many consecutive bits exist in the mask. This is
435 the same as the previous function, except that it also indicates the
436 start and end bit positions of the mask. */
443 register int start
, end
, i
;
447 for (i
= 0; val
!= 0; val
>>= 1, i
++)
458 /* Still looking for the first bit. */
462 /* We've seen the start of a bit sequence, and now a zero. There
463 must be more one bits, otherwise we would have exited the loop.
464 Therefor, it is not a mask. */
473 /* The bit string has ones from START to END bit positions only. */
476 return ((start
< 0) ? 0 : end
- start
+ 1);
479 /* Return the machine mode to use for a comparison. */
482 select_cc_mode (op
, x
)
486 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
491 /* X and Y are two things to compare using CODE. Emit the compare insn and
492 return the rtx for register 36 in the proper mode. */
495 gen_compare_reg (code
, x
, y
)
500 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
501 enum machine_mode mode
502 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
506 if (! arith_operand (x
, mode
))
507 x
= force_reg (SImode
, x
);
508 if (! arith_operand (y
, mode
))
509 y
= force_reg (SImode
, y
);
512 cc_reg
= gen_rtx (REG
, ccmode
, 36);
513 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
514 gen_rtx (COMPARE
, ccmode
, x
, y
)));
519 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
520 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
521 are 4. Indexed addresses are cost 6. */
523 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
526 i960_address_cost (x
)
530 /* Handled before calling here. */
531 if (GET_CODE (x
) == REG
)
534 if (GET_CODE (x
) == PLUS
)
536 rtx base
= XEXP (x
, 0);
537 rtx offset
= XEXP (x
, 1);
539 if (GET_CODE (base
) == SUBREG
)
540 base
= SUBREG_REG (base
);
541 if (GET_CODE (offset
) == SUBREG
)
542 offset
= SUBREG_REG (offset
);
544 if (GET_CODE (base
) == REG
)
546 if (GET_CODE (offset
) == REG
)
548 if (GET_CODE (offset
) == CONST_INT
)
550 if ((unsigned)INTVAL (offset
) < 2047)
554 if (CONSTANT_P (offset
))
557 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
560 /* This is an invalid address. The return value doesn't matter, but
561 for convenience we make this more expensive than anything else. */
564 if (GET_CODE (x
) == MULT
)
567 /* Symbol_refs and other unrecognized addresses are cost 4. */
571 /* Emit insns to move operands[1] into operands[0].
573 Return 1 if we have written out everything that needs to be done to
574 do the move. Otherwise, return 0 and the caller will emit the move
578 emit_move_sequence (operands
, mode
)
580 enum machine_mode mode
;
582 /* We can only store registers to memory. */
584 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
585 operands
[1] = force_reg (mode
, operands
[1]);
587 /* Storing multi-word values in unaligned hard registers to memory may
588 require a scratch since we have to store them a register at a time and
589 adding 4 to the memory address may not yield a valid insn. */
590 /* ??? We don't always need the scratch, but that would complicate things.
592 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
593 && GET_CODE (operands
[0]) == MEM
594 && GET_CODE (operands
[1]) == REG
595 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
596 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
598 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
600 gen_rtx (SET
, VOIDmode
,
601 operands
[0], operands
[1]),
602 gen_rtx (CLOBBER
, VOIDmode
,
603 gen_rtx (SCRATCH
, Pmode
)))));
610 /* Output assembler to move a double word value. */
613 i960_output_move_double (dst
, src
)
618 if (GET_CODE (dst
) == REG
619 && GET_CODE (src
) == REG
)
621 if ((REGNO (src
) & 1)
622 || (REGNO (dst
) & 1))
624 /* We normally copy the low-numbered register first. However, if
625 the second source register is the same as the first destination
626 register, we must copy in the opposite order. */
627 if (REGNO (src
) + 1 == REGNO (dst
))
628 return "mov %D1,%D0\n\tmov %1,%0";
630 return "mov %1,%0\n\tmov %D1,%D0";
635 else if (GET_CODE (dst
) == REG
636 && GET_CODE (src
) == CONST_INT
637 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
640 return "mov %1,%0\n\tmov 0,%D0";
644 else if (GET_CODE (dst
) == REG
645 && GET_CODE (src
) == MEM
)
649 /* One can optimize a few cases here, but you have to be
650 careful of clobbering registers used in the address and
654 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
655 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
656 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
657 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
663 else if (GET_CODE (dst
) == MEM
664 && GET_CODE (src
) == REG
)
668 /* This is handled by emit_move_sequence so we shouldn't get here. */
677 /* Output assembler to move a quad word value. */
680 i960_output_move_quad (dst
, src
)
685 if (GET_CODE (dst
) == REG
686 && GET_CODE (src
) == REG
)
688 if ((REGNO (src
) & 3)
689 || (REGNO (dst
) & 3))
691 /* We normally copy starting with the low numbered register.
692 However, if there is an overlap such that the first dest reg
693 is <= the last source reg but not < the first source reg, we
694 must copy in the opposite order. */
695 if (REGNO (dst
) <= REGNO (src
) + 3
696 && REGNO (dst
) >= REGNO (src
))
697 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
699 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
704 else if (GET_CODE (dst
) == REG
705 && GET_CODE (src
) == CONST_INT
706 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
709 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
713 else if (GET_CODE (dst
) == REG
714 && GET_CODE (src
) == MEM
)
718 /* One can optimize a few cases here, but you have to be
719 careful of clobbering registers used in the address and
723 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
724 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
725 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
726 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
727 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
728 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
734 else if (GET_CODE (dst
) == MEM
735 && GET_CODE (src
) == REG
)
739 /* This is handled by emit_move_sequence so we shouldn't get here. */
748 /* Emit insns to load a constant to non-floating point registers.
749 Uses several strategies to try to use as few insns as possible. */
752 i960_output_ldconst (dst
, src
)
753 register rtx dst
, src
;
756 register unsigned rsrc2
;
757 enum machine_mode mode
= GET_MODE (dst
);
760 operands
[0] = operands
[2] = dst
;
761 operands
[1] = operands
[3] = src
;
763 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
764 must be a ldconst insn. */
766 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
768 output_asm_insn ("ldconst %1,%0", operands
);
771 else if (mode
== XFmode
)
777 if (fp_literal_zero (src
, XFmode
))
780 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
781 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
783 output_asm_insn ("# ldconst %1,%0",operands
);
785 for (i
= 0; i
< 3; i
++)
787 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
788 operands
[1] = GEN_INT (value_long
[i
]);
789 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
795 else if (mode
== DFmode
)
799 if (fp_literal_zero (src
, DFmode
))
802 split_double (src
, &first
, &second
);
804 output_asm_insn ("# ldconst %1,%0",operands
);
806 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
808 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
810 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
811 operands
[1] = second
;
812 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
816 else if (mode
== SFmode
)
821 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
822 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
824 output_asm_insn ("# ldconst %1,%0",operands
);
825 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
826 operands
[1] = GEN_INT (value
);
827 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
831 else if (mode
== TImode
)
833 /* ??? This is currently not handled at all. */
836 /* Note: lowest order word goes in lowest numbered reg. */
837 rsrc1
= INTVAL (src
);
838 if (rsrc1
>= 0 && rsrc1
< 32)
841 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
842 /* Go pick up the low-order word. */
844 else if (mode
== DImode
)
846 rtx upperhalf
, lowerhalf
, xoperands
[2];
848 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
849 split_double (src
, &lowerhalf
, &upperhalf
);
854 /* Note: lowest order word goes in lowest numbered reg. */
855 /* Numbers from 0 to 31 can be handled with a single insn. */
856 rsrc1
= INTVAL (lowerhalf
);
857 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
860 /* Output the upper half with a recursive call. */
861 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
862 xoperands
[1] = upperhalf
;
863 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
865 /* The lower word is emitted as normally. */
869 rsrc1
= INTVAL (src
);
875 else if (mode
== HImode
)
884 /* ldconst 0..31,X -> mov 0..31,X */
887 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
892 /* ldconst 32..63,X -> add 31,nn,X */
895 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
897 operands
[1] = GEN_INT (rsrc1
- 31);
898 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
904 /* ldconst -1..-31 -> sub 0,0..31,X */
907 /* return 'sub -(%1),0,%0' */
908 operands
[1] = GEN_INT (- rsrc1
);
909 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
913 /* ldconst -32 -> not 31,X */
916 operands
[1] = GEN_INT (~rsrc1
);
917 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
922 /* If const is a single bit. */
923 if (bitpos (rsrc1
) >= 0)
925 operands
[1] = GEN_INT (bitpos (rsrc1
));
926 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
930 /* If const is a bit string of less than 6 bits (1..31 shifted). */
935 if (bitstr (rsrc1
, &s
, &e
) < 6)
937 rsrc2
= ((unsigned int) rsrc1
) >> s
;
938 operands
[1] = GEN_INT (rsrc2
);
939 operands
[2] = GEN_INT (s
);
940 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
945 /* Unimplemented cases:
946 const is in range 0..31 but rotated around end of word:
947 ror 31,3,g0 -> ldconst 0xe0000003,g0
949 and any 2 instruction cases that might be worthwhile */
951 output_asm_insn ("ldconst %1,%0", operands
);
955 /* Determine if there is an opportunity for a bypass optimization.
956 Bypass succeeds on the 960K* if the destination of the previous
957 instruction is the second operand of the current instruction.
958 Bypass always succeeds on the C*.
960 Return 1 if the pattern should interchange the operands.
962 CMPBR_FLAG is true if this is for a compare-and-branch insn.
963 OP1 and OP2 are the two source operands of a 3 operand insn. */
966 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
967 register rtx insn
, op1
, op2
;
970 register rtx prev_insn
, prev_dest
;
975 /* Can't do this if op1 isn't a register. */
979 /* Can't do this for a compare-and-branch if both ops aren't regs. */
980 if (cmpbr_flag
&& ! REG_P (op2
))
983 prev_insn
= prev_real_insn (insn
);
985 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
986 && GET_CODE (PATTERN (prev_insn
)) == SET
)
988 prev_dest
= SET_DEST (PATTERN (prev_insn
));
989 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
990 || (GET_CODE (prev_dest
) == SUBREG
991 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
992 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
998 /* Output the code which declares the function name. This also handles
999 leaf routines, which have special requirements, and initializes some
1000 global variables. */
1003 i960_function_name_declare (file
, name
, fndecl
)
1012 /* Increment global return label. */
1016 /* Compute whether tail calls and leaf routine optimizations can be performed
1017 for this function. */
1019 if (TARGET_TAILCALL
)
1024 if (TARGET_LEAFPROC
)
1029 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1030 argblock, because argblock uses g14 implicitly. */
1032 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1038 /* See if caller passes in an address to return value. */
1040 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1046 /* Can not use tail calls or make this a leaf routine if there is a non
1049 if (get_frame_size () != 0)
1052 /* I don't understand this condition, and do not think that it is correct.
1053 Apparently this is just checking whether the frame pointer is used, and
1054 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1057 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1058 if (GET_CODE (insn
) == INSN
1059 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1065 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1068 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1069 if (GET_CODE (insn
) == CALL_INSN
)
1075 /* Can not be a leaf routine if any non-call clobbered registers are
1076 used in this function. */
1079 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1080 if (regs_ever_live
[i
]
1081 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1083 /* Global registers. */
1084 if (i
< 16 && i
> 7 && i
!= 13)
1086 /* Local registers. */
1091 /* Now choose a leaf return register, if we can find one, and if it is
1092 OK for this to be a leaf routine. */
1094 i960_leaf_ret_reg
= -1;
1096 if (optimize
&& leaf_proc_ok
)
1098 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1099 if (regs_ever_live
[i
] == 0)
1101 i960_leaf_ret_reg
= i
;
1102 regs_ever_live
[i
] = 1;
1107 /* Do this after choosing the leaf return register, so it will be listed
1108 if one was chosen. */
1110 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1111 fprintf (file
, "\t# Registers used: ");
1113 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1115 if (regs_ever_live
[i
])
1117 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1119 if (i
> 15 && j
== 0)
1121 fprintf (file
,"\n\t#\t\t ");
1127 fprintf (file
, "\n");
1129 if (i960_leaf_ret_reg
>= 0)
1131 /* Make it a leaf procedure. */
1133 if (TREE_PUBLIC (fndecl
))
1134 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1136 fprintf (file
, "\t.leafproc\t");
1137 assemble_name (file
, name
);
1138 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1139 ASM_OUTPUT_LABEL (file
, name
);
1140 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1141 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1142 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1144 if (TARGET_C_SERIES
)
1146 fprintf (file
, "\tlda 0,g14\n");
1147 i960_last_insn_type
= I_TYPE_MEM
;
1151 fprintf (file
, "\tmov 0,g14\n");
1152 i960_last_insn_type
= I_TYPE_REG
;
1157 ASM_OUTPUT_LABEL (file
, name
);
1158 i960_last_insn_type
= I_TYPE_CTRL
;
1162 /* Compute and return the frame size. */
1165 compute_frame_size (size
)
1169 int outgoing_args_size
= current_function_outgoing_args_size
;
1171 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1172 as size is concerned. */
1173 actual_fsize
= (size
+ 15) & -16;
1174 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1176 return actual_fsize
;
1179 /* Output code for the function prologue. */
1182 i960_function_prologue (file
, size
)
1186 register int i
, j
, nr
;
1189 int actual_fsize
, offset
;
1191 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1193 int regs
[FIRST_PSEUDO_REGISTER
];
1195 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1196 if (regs_ever_live
[i
]
1197 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1200 /* Count global registers that need saving. */
1207 epilogue_string
[0] = '\0';
1209 if (profile_flag
|| profile_block_flag
)
1211 /* When profiling, we may use registers 20 to 27 to save arguments, so
1212 they can't be used here for saving globals. J is the number of
1213 argument registers the mcount call will save. */
1214 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1217 for (i
= 20; i
<= j
+ 20; i
++)
1221 /* First look for local registers to save globals in. */
1222 for (i
= 0; i
< 16; i
++)
1227 /* Start at r4, not r3. */
1228 for (j
= 20; j
< 32; j
++)
1235 regs_ever_live
[j
] = 1;
1237 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1238 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1243 regs_ever_live
[j
+1] = 1;
1245 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1246 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1251 regs_ever_live
[j
+2] = 1;
1253 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1258 regs_ever_live
[j
+3] = 1;
1261 fprintf (file
, "\tmov%s %s,%s\n",
1264 (nr
== 2) ? "l" : ""),
1265 reg_names
[i
], reg_names
[j
]);
1266 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1269 (nr
== 2) ? "l" : ""),
1270 reg_names
[j
], reg_names
[i
]);
1271 strcat (epilogue_string
, tmpstr
);
1279 /* N_iregs is now the number of global registers that haven't been saved
1282 rsize
= (n_iregs
* 4);
1283 actual_fsize
= compute_frame_size (size
) + rsize
;
1285 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1286 size up to the nearest multiple of 16. I don't know whether this is
1287 necessary, or even desirable.
1289 The frame pointer must be aligned, but the call instruction takes care of
1290 that. If we leave the stack pointer unaligned, we may save a little on
1291 dynamic stack allocation. And we don't lose, at least according to the
1293 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1296 /* Allocate space for register save and locals. */
1297 if (actual_fsize
> 0)
1299 if (actual_fsize
< 32)
1300 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1302 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1305 /* Take hardware register save area created by the call instruction
1306 into account, but store them before the argument block area. */
1307 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1308 /* Save registers on stack if needed. */
1309 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1316 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1319 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1323 if (nr
== 3 && regs
[i
+3] == -1)
1326 fprintf (file
,"\tst%s %s,%d(fp)\n",
1329 (nr
== 2) ? "l" : ""),
1330 reg_names
[i
], offset
);
1331 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1334 (nr
== 2) ? "l" : ""),
1335 offset
, reg_names
[i
]);
1336 strcat (epilogue_string
, tmpstr
);
1342 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1345 fprintf (file
, "\t#Prologue stats:\n");
1346 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1349 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1351 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1353 fprintf (file
, "\t#End Prologue#\n");
1356 /* Output code for the function profiler. */
1359 output_function_profiler (file
, labelno
)
1363 /* The last used parameter register. */
1365 int i
, j
, increment
;
1366 int varargs_stdarg_function
1367 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1369 /* Figure out the last used parameter register. The proper thing to do
1370 is to walk incoming args of the function. A function might have live
1371 parameter registers even if it has no incoming args. Note that we
1372 don't have to save parameter registers g8 to g11 because they are
1375 /* See also output_function_prologue, which tries to use local registers
1376 for preserved call-saved global registers. */
1378 for (last_parm_reg
= 7;
1379 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1383 /* Save parameter registers in regs r4 (20) to r11 (27). */
1385 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1387 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1389 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1391 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1396 fprintf (file
, "\tmov%s g%d,r%d\n",
1397 (increment
== 4 ? "q" : increment
== 3 ? "t"
1398 : increment
== 2 ? "l": ""), i
, j
);
1401 /* If this function uses the arg pointer, then save it in r3 and then
1404 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1405 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1407 /* Load location address into g0 and call mcount. */
1409 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1411 /* If this function uses the arg pointer, restore it. */
1413 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1414 fprintf (file
, "\tmov r3,g14\n");
1416 /* Restore parameter registers. */
1418 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1420 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1422 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1424 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1429 fprintf (file
, "\tmov%s r%d,g%d\n",
1430 (increment
== 4 ? "q" : increment
== 3 ? "t"
1431 : increment
== 2 ? "l": ""), j
, i
);
1435 /* Output code for the function epilogue. */
1438 i960_function_epilogue (file
, size
)
1442 if (i960_leaf_ret_reg
>= 0)
1444 fprintf (file
, "LR%d: ret\n", ret_label
);
1448 if (*epilogue_string
== 0)
1452 /* Emit a return insn, but only if control can fall through to here. */
1454 tmp
= get_last_insn ();
1457 if (GET_CODE (tmp
) == BARRIER
)
1459 if (GET_CODE (tmp
) == CODE_LABEL
)
1461 if (GET_CODE (tmp
) == JUMP_INSN
)
1463 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1467 if (GET_CODE (tmp
) == NOTE
)
1469 tmp
= PREV_INSN (tmp
);
1474 fprintf (file
, "LR%d: ret\n", ret_label
);
1478 fprintf (file
, "LR%d:\n", ret_label
);
1480 fprintf (file
, "\t#EPILOGUE#\n");
1482 /* Output the string created by the prologue which will restore all
1483 registers saved by the prologue. */
1485 if (epilogue_string
[0] != '\0')
1486 fprintf (file
, "%s", epilogue_string
);
1488 /* Must clear g14 on return if this function set it.
1489 Only varargs/stdarg functions modify g14. */
1491 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1492 fprintf (file
, "\tmov 0,g14\n");
1494 fprintf (file
, "\tret\n");
1495 fprintf (file
, "\t#End Epilogue#\n");
1498 /* Output code for a call insn. */
1501 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1502 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1504 int argsize
= INTVAL (argsize_rtx
);
1505 rtx nexti
= next_real_insn (insn
);
1507 int varargs_stdarg_function
1508 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1510 operands
[0] = target
;
1511 operands
[1] = arg_pointer
;
1513 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1514 output_asm_insn ("mov g14,r3", operands
);
1517 output_asm_insn ("lda %a1,g14", operands
);
1518 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1519 output_asm_insn ("mov 0,g14", operands
);
1521 /* The code used to assume that calls to SYMBOL_REFs could not be more
1522 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1523 feature is now implemented by relaxing in the GNU linker. It can convert
1524 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1526 /* Nexti could be zero if the called routine is volatile. */
1527 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1528 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1530 /* Delete following return insn. */
1531 if (nexti
&& no_labels_between_p (insn
, nexti
))
1532 delete_insn (nexti
);
1533 output_asm_insn ("bx %0", operands
);
1534 return "# notreached";
1537 output_asm_insn ("callx %0", operands
);
1539 /* If the caller sets g14 to the address of the argblock, then the caller
1540 must clear it after the return. */
1542 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1543 output_asm_insn ("mov r3,g14", operands
);
1544 else if (argsize
> 48)
1545 output_asm_insn ("mov 0,g14", operands
);
1550 /* Output code for a return insn. */
1553 i960_output_ret_insn (insn
)
1556 static char lbuf
[20];
1558 if (*epilogue_string
!= 0)
1560 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1563 sprintf (lbuf
, "b LR%d", ret_label
);
1567 /* Must clear g14 on return if this function set it.
1568 Only varargs/stdarg functions modify g14. */
1570 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1571 output_asm_insn ("mov 0,g14", 0);
1573 if (i960_leaf_ret_reg
>= 0)
1575 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1582 /* Return a character string representing the branch prediction
1583 opcode to be tacked on an instruction. This must at least
1584 return a null string. */
1587 i960_br_predict_opcode (lab_ref
, insn
)
1590 if (TARGET_BRANCH_PREDICT
)
1592 unsigned long label_uid
;
1594 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1595 label_uid
= INSN_UID (lab_ref
);
1596 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1597 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1601 /* If not optimizing, then the insn_addresses array will not be
1602 valid. In this case, always return ".t" since most branches
1603 are taken. If optimizing, return .t for backward branches
1604 and .f for forward branches. */
1606 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1615 /* Print the operand represented by rtx X formatted by code CODE. */
1618 i960_print_operand (file
, x
, code
)
1623 enum rtx_code rtxcode
= GET_CODE (x
);
1630 /* Second reg of a double or quad. */
1631 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1635 /* Third reg of a quad. */
1636 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1640 /* Fourth reg of a quad. */
1641 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1645 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1653 else if (rtxcode
== MEM
)
1655 output_address (XEXP (x
, 0));
1658 else if (rtxcode
== CONST_INT
)
1660 HOST_WIDE_INT val
= INTVAL (x
);
1663 if (val
> 9999 || val
< -999)
1664 fprintf (file
, "0x%x", val
);
1666 fprintf (file
, "%d", val
);
1669 else if (rtxcode
== CONST_DOUBLE
)
1674 if (x
== CONST0_RTX (GET_MODE (x
)))
1676 fprintf (file
, "0f0.0");
1679 else if (x
== CONST1_RTX (GET_MODE (x
)))
1681 fprintf (file
, "0f1.0");
1685 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1686 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1687 fprintf (file
, "0f%s", dstr
);
1694 /* Branch or jump, depending on assembler. */
1695 if (TARGET_ASM_COMPAT
)
1702 /* Sign of condition. */
1703 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1704 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1706 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1707 || (rtxcode
== GE
) || (rtxcode
== LE
))
1714 /* Inverted condition. */
1715 rtxcode
= reverse_condition (rtxcode
);
1719 /* Inverted condition w/ reversed operands. */
1720 rtxcode
= reverse_condition (rtxcode
);
1724 /* Reversed operand condition. */
1725 rtxcode
= swap_condition (rtxcode
);
1729 /* Normal condition. */
1731 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1732 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1733 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1734 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1735 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1736 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1737 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1738 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1739 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1740 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1745 output_addr_const (file
, x
);
1755 /* Print a memory address as an operand to reference that memory location.
1757 This is exactly the same as legitimate_address_p, except that it the prints
1758 addresses instead of recognizing them. */
1761 i960_print_operand_addr (file
, addr
)
1773 if (GET_CODE (addr
) == REG
)
1775 else if (CONSTANT_P (addr
))
1777 else if (GET_CODE (addr
) == PLUS
)
1781 op0
= XEXP (addr
, 0);
1782 op1
= XEXP (addr
, 1);
1784 if (GET_CODE (op0
) == REG
)
1787 if (GET_CODE (op1
) == REG
)
1789 else if (CONSTANT_P (op1
))
1794 else if (GET_CODE (op0
) == PLUS
)
1796 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1798 ireg
= XEXP (XEXP (op0
, 0), 0);
1799 scale
= XEXP (XEXP (op0
, 0), 1);
1800 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1802 breg
= XEXP (op0
, 1);
1808 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1810 breg
= XEXP (op0
, 0);
1811 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1813 ireg
= XEXP (op0
, 1);
1822 else if (GET_CODE (op0
) == MULT
)
1824 ireg
= XEXP (op0
, 0);
1825 scale
= XEXP (op0
, 1);
1826 if (GET_CODE (op1
) == REG
)
1828 else if (CONSTANT_P (op1
))
1836 else if (GET_CODE (addr
) == MULT
)
1838 ireg
= XEXP (addr
, 0);
1839 scale
= XEXP (addr
, 1);
1845 output_addr_const (file
, offset
);
1847 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1849 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1852 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1853 that is a valid memory address for an instruction.
1854 The MODE argument is the machine mode for the MEM expression
1855 that wants to use this address.
1857 On 80960, legitimate addresses are:
1859 disp (12 or 32 bit) ld foo,r0
1860 base + index ld (g0)[g1*1],r0
1861 base + displ ld 0xf00(g0),r0
1862 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1863 index*scale + base ld (g0)[g1*4],r0
1864 index*scale + displ ld 0xf00[g1*4],r0
1865 index*scale ld [g1*4],r0
1866 index + base + displ ld 0xf00(g0)[g1*1],r0
1868 In each case, scale can be 1, 2, 4, 8, or 16. */
1870 /* This is exactly the same as i960_print_operand_addr, except that
1871 it recognizes addresses instead of printing them.
1873 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1874 convert common non-canonical forms to canonical form so that they will
1877 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1878 where a register is valid. */
1880 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1881 ((GET_CODE (X) == REG \
1882 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1883 || (GET_CODE (X) == SUBREG \
1884 && GET_CODE (SUBREG_REG (X)) == REG \
1885 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1886 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1888 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1889 ((GET_CODE (X) == REG \
1890 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1891 || (GET_CODE (X) == SUBREG \
1892 && GET_CODE (SUBREG_REG (X)) == REG \
1893 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1894 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1897 legitimate_address_p (mode
, addr
, strict
)
1898 enum machine_mode mode
;
1902 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1904 else if (CONSTANT_P (addr
))
1906 else if (GET_CODE (addr
) == PLUS
)
1910 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1913 op0
= XEXP (addr
, 0);
1914 op1
= XEXP (addr
, 1);
1916 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1918 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1920 else if (CONSTANT_P (op1
))
1925 else if (GET_CODE (op0
) == PLUS
)
1927 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1929 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1930 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1933 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1934 && CONSTANT_P (op1
))
1939 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1941 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1942 && CONSTANT_P (op1
))
1950 else if (GET_CODE (op0
) == MULT
)
1952 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1953 && SCALE_TERM_P (XEXP (op0
, 1))))
1956 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1958 else if (CONSTANT_P (op1
))
1966 else if (GET_CODE (addr
) == MULT
)
1968 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1971 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1972 && SCALE_TERM_P (XEXP (addr
, 1)));
1978 /* Try machine-dependent ways of modifying an illegitimate address
1979 to be legitimate. If we find one, return the new, valid address.
1980 This macro is used in only one place: `memory_address' in explow.c.
1982 This converts some non-canonical addresses to canonical form so they
1983 can be recognized. */
1986 legitimize_address (x
, oldx
, mode
)
1989 enum machine_mode mode
;
1991 if (GET_CODE (x
) == SYMBOL_REF
)
1994 x
= copy_to_reg (x
);
1997 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2000 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2001 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2002 created by virtual register instantiation, register elimination, and
2003 similar optimizations. */
2004 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2005 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2006 x
= gen_rtx (PLUS
, Pmode
,
2007 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2008 XEXP (XEXP (x
, 1), 1));
2010 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2011 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2012 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2013 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2014 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2015 && CONSTANT_P (XEXP (x
, 1)))
2017 rtx constant
, other
;
2019 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2021 constant
= XEXP (x
, 1);
2022 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2024 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2026 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2027 other
= XEXP (x
, 1);
2033 x
= gen_rtx (PLUS
, Pmode
,
2034 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2035 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2036 plus_constant (other
, INTVAL (constant
)));
2043 /* Return the most stringent alignment that we are willing to consider
2044 objects of size SIZE and known alignment ALIGN as having. */
2047 i960_alignment (size
, align
)
2053 if (! TARGET_STRICT_ALIGN
)
2054 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2056 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2065 /* Modes for condition codes. */
2067 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2069 /* Modes for single-word (and smaller) quantities. */
2072 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2073 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2075 /* Modes for double-word (and smaller) quantities. */
2078 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2080 /* Modes for quad-word quantities. */
2081 #define T_MODES (~C_MODES)
2083 /* Modes for single-float quantities. */
2084 #define SF_MODES ((1 << (int) SFmode))
2086 /* Modes for double-float quantities. */
2087 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2089 /* Modes for quad-float quantities. */
2090 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2092 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
2093 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2094 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2095 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2096 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2098 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
2101 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2102 advantage of machine specific facts, such as knowing that the frame pointer
2103 is always 16 byte aligned. */
2106 i960_expr_alignment (x
, size
)
2115 switch (GET_CODE(x
))
2120 if ((align
& 0xf) == 0)
2122 else if ((align
& 0x7) == 0)
2124 else if ((align
& 0x3) == 0)
2126 else if ((align
& 0x1) == 0)
2133 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2134 i960_expr_alignment (XEXP (x
, 1), size
));
2138 /* If this is a valid program, objects are guaranteed to be
2139 correctly aligned for whatever size the reference actually is. */
2140 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2144 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2149 align
= i960_expr_alignment (XEXP (x
, 0));
2151 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2153 align
= align
<< INTVAL (XEXP (x
, 1));
2154 align
= MIN (align
, 16);
2159 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2160 i960_expr_alignment (XEXP (x
, 1), size
));
2162 align
= MIN (align
, 16);
2169 /* Return true if it is possible to reference both BASE and OFFSET, which
2170 have alignment at least as great as 4 byte, as if they had alignment valid
2171 for an object of size SIZE. */
2174 i960_improve_align (base
, offset
, size
)
2181 /* We have at least a word reference to the object, so we know it has to
2182 be aligned at least to 4 bytes. */
2184 i
= MIN (i960_expr_alignment (base
, 4),
2185 i960_expr_alignment (offset
, 4));
2189 /* We know the size of the request. If strict align is not enabled, we
2190 can guess that the alignment is OK for the requested size. */
2192 if (! TARGET_STRICT_ALIGN
)
2193 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2199 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2200 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2203 i960_si_ti (base
, offset
)
2207 return i960_improve_align (base
, offset
, 16);
2210 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2211 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2214 i960_si_di (base
, offset
)
2218 return i960_improve_align (base
, offset
, 8);
2221 /* Return raw values of size and alignment (in words) for the data
2222 type being accessed. These values will be rounded by the caller. */
2225 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2226 enum machine_mode mode
;
2233 /* Use formal alignment requirements of type being passed, except make
2234 it at least a word. If we don't have a type, this is a library call,
2235 and the parm has to be of scalar type. In this case, consider its
2236 formal alignment requirement to be its size in words. */
2238 if (mode
== BLKmode
)
2239 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2240 else if (mode
== VOIDmode
)
2242 /* End of parm list. */
2243 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2248 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2252 /* ??? This is a hack to properly correct the alignment of XFmode
2253 values without affecting anything else. */
2259 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2260 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2268 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2269 Any arg that is bigger than 4 words is placed on the stack and all
2270 subsequent arguments are placed on the stack.
2272 Additionally, parameters with an alignment requirement stronger than
2273 a word must be aligned appropriately. Note that this means that a
2274 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2275 passed in an odd/even register pair. */
2277 /* Update CUM to advance past an argument described by MODE and TYPE. */
2280 i960_function_arg_advance (cum
, mode
, type
, named
)
2281 CUMULATIVE_ARGS
*cum
;
2282 enum machine_mode mode
;
2288 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2290 if (size
> 4 || cum
->ca_nstackparms
!= 0
2291 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2292 || MUST_PASS_IN_STACK (mode
, type
))
2294 /* Indicate that all the registers are in use, even if all are not,
2295 so va_start will compute the right value. */
2296 cum
->ca_nregparms
= NPARM_REGS
;
2297 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2300 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2303 /* Return the register that the argument described by MODE and TYPE is
2304 passed in, or else return 0 if it is passed on the stack. */
2307 i960_function_arg (cum
, mode
, type
, named
)
2308 CUMULATIVE_ARGS
*cum
;
2309 enum machine_mode mode
;
2316 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2318 if (size
> 4 || cum
->ca_nstackparms
!= 0
2319 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2320 || MUST_PASS_IN_STACK (mode
, type
))
2322 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2327 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2328 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2334 /* Floating-point support. */
2337 i960_output_long_double (file
, value
)
2339 REAL_VALUE_TYPE value
;
2344 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2345 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2348 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2349 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2350 fprintf (file
, "\t.word\t0x0\n");
2354 i960_output_double (file
, value
)
2356 REAL_VALUE_TYPE value
;
2361 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2362 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2364 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2365 value_long
[0], dstr
, value_long
[1]);
2369 i960_output_float (file
, value
)
2371 REAL_VALUE_TYPE value
;
2376 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2377 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2379 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2382 /* Return the number of bits that an object of size N bytes is aligned to. */
2385 i960_object_bytes_bitalign (n
)
2389 else if (n
> 4) n
= 64;
2390 else if (n
> 2) n
= 32;
2391 else if (n
> 1) n
= 16;
2397 /* Compute the alignment for an aggregate type TSIZE.
2398 Alignment is MAX (greatest member alignment,
2399 MIN (pragma align, structure size alignment)). */
2402 i960_round_align (align
, tsize
)
2408 if (TREE_CODE (tsize
) != INTEGER_CST
)
2411 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2413 /* Handle #pragma align. */
2414 if (new_align
> i960_maxbitalignment
)
2415 new_align
= i960_maxbitalignment
;
2417 if (align
< new_align
)
2423 /* Do any needed setup for a varargs function. For the i960, we must
2424 create a register parameter block if one doesn't exist, and then copy
2425 all register parameters to memory. */
2428 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2429 CUMULATIVE_ARGS
*cum
;
2430 enum machine_mode mode
;
2435 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2436 int first_reg
= cum
->ca_nregparms
;
2438 /* Copy only unnamed register arguments to memory. If there are
2439 any stack parms, there are no unnamed arguments in registers, and
2440 an argument block was already allocated by the caller.
2441 Remember that any arg bigger than 4 words is passed on the stack as
2442 are all subsequent args.
2444 If there are no stack arguments but there are exactly NPARM_REGS
2445 registers, either there were no extra arguments or the caller
2446 allocated an argument block. */
2448 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2450 rtx label
= gen_label_rtx ();
2453 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2454 and we need to allocate a chunk to save the registers (if any
2455 arguments were passed on the stack the caller would allocate the
2456 48 bytes as well). We must allocate all 48 bytes (12*4) because
2457 va_start assumes it. */
2458 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2459 emit_jump_insn (gen_bne (label
));
2460 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2461 stack_pointer_rtx
));
2462 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2463 memory_address (SImode
,
2464 plus_constant (stack_pointer_rtx
,
2468 /* ??? Note that we unnecessarily store one extra register for stdarg
2469 fns. We could optimize this, but it's kept as for now. */
2470 regblock
= gen_rtx (MEM
, BLKmode
,
2471 plus_constant (arg_pointer_rtx
,
2473 move_block_from_reg (first_reg
, regblock
,
2474 NPARM_REGS
- first_reg
,
2475 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2479 /* Calculate the final size of the reg parm stack space for the current
2480 function, based on how many bytes would be allocated on the stack. */
2483 i960_final_reg_parm_stack_space (const_size
, var_size
)
2487 if (var_size
|| const_size
> 48)
2493 /* Calculate the size of the reg parm stack space. This is a bit complicated
2497 i960_reg_parm_stack_space (fndecl
)
2500 /* In this case, we are called from emit_library_call, and we don't need
2501 to pretend we have more space for parameters than what's apparent. */
2505 /* In this case, we are called from locate_and_pad_parms when we're
2506 not IN_REGS, so we have an arg block. */
2507 if (fndecl
!= current_function_decl
)
2510 /* Otherwise, we have an arg block if the current function has more than
2511 48 bytes of parameters. */
2512 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2518 /* Return the register class of a scratch register needed to copy IN into
2519 or out of a register in CLASS in MODE. If it can be done directly,
2520 NO_REGS is returned. */
2523 secondary_reload_class (class, mode
, in
)
2524 enum reg_class
class;
2525 enum machine_mode mode
;
2530 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2531 regno
= true_regnum (in
);
2533 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2534 LOCAL_OR_GLOBAL_REGS into anything. */
2535 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2536 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2539 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2540 if (class == FP_REGS
2541 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2542 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2545 return LOCAL_OR_GLOBAL_REGS
;
2548 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2549 function unit it executed on. */
2551 /* ??? This would make more sense as an attribute. */
2554 i960_scan_opcode (p
)
2566 /* Ret is not actually of type REG, but it won't matter, because no
2567 insn will ever follow it. */
2570 i960_last_insn_type
= I_TYPE_REG
;
2574 if (p
[1] == 'x' || p
[3] == 'x')
2575 i960_last_insn_type
= I_TYPE_MEM
;
2576 i960_last_insn_type
= I_TYPE_CTRL
;
2581 i960_last_insn_type
= I_TYPE_CTRL
;
2588 i960_last_insn_type
= I_TYPE_MEM
;
2590 i960_last_insn_type
= I_TYPE_CTRL
;
2592 else if (p
[1] == 'm')
2595 i960_last_insn_type
= I_TYPE_REG
;
2596 else if (p
[4] == 'b' || p
[4] == 'j')
2597 i960_last_insn_type
= I_TYPE_CTRL
;
2599 i960_last_insn_type
= I_TYPE_REG
;
2602 i960_last_insn_type
= I_TYPE_REG
;
2606 i960_last_insn_type
= I_TYPE_MEM
;
2611 i960_last_insn_type
= I_TYPE_MEM
;
2613 i960_last_insn_type
= I_TYPE_REG
;