1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
48 rtx i960_compare_op0
, i960_compare_op1
;
50 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
53 static int i960_maxbitalignment
;
54 static int i960_last_maxbitalignment
;
56 /* Used to implement switching between MEM and ALU insn types, for better
57 C series performance. */
59 enum insn_types i960_last_insn_type
;
61 /* The leaf-procedure return register. Set only if this is a leaf routine. */
63 static int i960_leaf_ret_reg
;
65 /* True if replacing tail calls with jumps is OK. */
67 static int tail_call_ok
;
69 /* A string containing a list of insns to emit in the epilogue so as to
70 restore all registers saved by the prologue. Created by the prologue
71 code as it saves registers away. */
73 char epilogue_string
[1000];
75 /* A unique number (per function) for return labels. */
77 static int ret_label
= 0;
79 /* This is true if FNDECL is either a varargs or a stdarg function.
80 This is used to help identify functions that use an argument block. */
82 #define VARARGS_STDARG_FUNCTION(FNDECL) \
83 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
84 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
85 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. */
93 process_pragma (finput
, t
)
101 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
104 pname
= IDENTIFIER_POINTER (t
);
106 if (strcmp (pname
, "align") == 0)
114 } while (c
== ' ' || c
== '\t');
118 while (c
>= '0' && c
<= '9')
120 if (s
< buf
+ sizeof buf
- 1)
130 /* Return to last alignment. */
131 align
= i960_last_maxbitalignment
/ 8;
138 i960_last_maxbitalignment
= i960_maxbitalignment
;
139 i960_maxbitalignment
= align
* 8;
143 /* Silently ignore bad values. */
147 /* NOTE: ic960 R3.0 pragma align definition:
149 #pragma align [(size)] | (identifier=size[,...])
150 #pragma noalign [(identifier)[,...]]
152 (all parens are optional)
154 - size is [1,2,4,8,16]
155 - noalign means size==1
156 - applies only to component elements of a struct (and union?)
157 - identifier applies to structure tag (only)
158 - missing identifier means next struct
160 - alignment rules for bitfields need more investigation */
165 /* Should be pragma 'far' or equivalent for callx/balx here. */
170 /* Initialize variables before compiling any files. */
175 if (TARGET_IC_COMPAT2_0
)
177 i960_maxbitalignment
= 8;
178 i960_last_maxbitalignment
= 128;
182 i960_maxbitalignment
= 128;
183 i960_last_maxbitalignment
= 8;
187 /* Return true if OP can be used as the source of an fp move insn. */
190 fpmove_src_operand (op
, mode
)
192 enum machine_mode mode
;
194 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
198 /* Return true if OP is a register or zero. */
201 reg_or_zero_operand (op
, mode
)
203 enum machine_mode mode
;
205 return register_operand (op
, mode
) || op
== const0_rtx
;
209 /* Return truth value of whether OP can be used as an operands in a three
210 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
213 arith_operand (op
, mode
)
215 enum machine_mode mode
;
217 return (register_operand (op
, mode
) || literal (op
, mode
));
220 /* Return truth value of whether OP can be used as an operands in a three
221 address logic insn, possibly complementing OP, of mode MODE. */
224 logic_operand (op
, mode
)
226 enum machine_mode mode
;
228 return (register_operand (op
, mode
)
229 || (GET_CODE (op
) == CONST_INT
230 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
233 /* Return true if OP is a register or a valid floating point literal. */
236 fp_arith_operand (op
, mode
)
238 enum machine_mode mode
;
240 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
243 /* Return true is OP is a register or a valid signed integer literal. */
246 signed_arith_operand (op
, mode
)
248 enum machine_mode mode
;
250 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
253 /* Return truth value of whether OP is a integer which fits the
254 range constraining immediate operands in three-address insns. */
259 enum machine_mode mode
;
261 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
264 /* Return true if OP is a float constant of 1. */
267 fp_literal_one (op
, mode
)
269 enum machine_mode mode
;
271 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
274 /* Return true if OP is a float constant of 0. */
277 fp_literal_zero (op
, mode
)
279 enum machine_mode mode
;
281 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
284 /* Return true if OP is a valid floating point literal. */
289 enum machine_mode mode
;
291 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
294 /* Return true if OP is a valid signed immediate constant. */
297 signed_literal(op
, mode
)
299 enum machine_mode mode
;
301 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
304 /* Return truth value of statement that OP is a symbolic memory
305 operand of mode MODE. */
308 symbolic_memory_operand (op
, mode
)
310 enum machine_mode mode
;
312 if (GET_CODE (op
) == SUBREG
)
313 op
= SUBREG_REG (op
);
314 if (GET_CODE (op
) != MEM
)
317 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
318 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
321 /* Return truth value of whether OP is EQ or NE. */
326 enum machine_mode mode
;
328 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
331 /* OP is an integer register or a constant. */
334 arith32_operand (op
, mode
)
336 enum machine_mode mode
;
338 if (register_operand (op
, mode
))
340 return (CONSTANT_P (op
));
343 /* Return true if OP is an integer constant which is a power of 2. */
346 power2_operand (op
,mode
)
348 enum machine_mode mode
;
350 if (GET_CODE (op
) != CONST_INT
)
353 return exact_log2 (INTVAL (op
)) >= 0;
356 /* Return true if OP is an integer constant which is the complement of a
360 cmplpower2_operand (op
, mode
)
362 enum machine_mode mode
;
364 if (GET_CODE (op
) != CONST_INT
)
367 return exact_log2 (~ INTVAL (op
)) >= 0;
370 /* If VAL has only one bit set, return the index of that bit. Otherwise
379 for (i
= 0; val
!= 0; i
++, val
>>= 1)
391 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
392 The return value indicates how many consecutive non-zero bits exist
393 if this is a mask. This is the same as the next function, except that
394 it does not indicate what the start and stop bit positions are. */
400 register int start
, end
, i
;
403 for (i
= 0; val
!= 0; val
>>= 1, i
++)
413 /* Still looking for the first bit. */
417 /* We've seen the start of a bit sequence, and now a zero. There
418 must be more one bits, otherwise we would have exited the loop.
419 Therefore, it is not a mask. */
424 /* The bit string has ones from START to END bit positions only. */
425 return end
- start
+ 1;
428 /* If VAL is a mask, then return nonzero, with S set to the starting bit
429 position and E set to the ending bit position of the mask. The return
430 value indicates how many consecutive bits exist in the mask. This is
431 the same as the previous function, except that it also indicates the
432 start and end bit positions of the mask. */
439 register int start
, end
, i
;
443 for (i
= 0; val
!= 0; val
>>= 1, i
++)
454 /* Still looking for the first bit. */
458 /* We've seen the start of a bit sequence, and now a zero. There
459 must be more one bits, otherwise we would have exited the loop.
460 Therefor, it is not a mask. */
469 /* The bit string has ones from START to END bit positions only. */
472 return ((start
< 0) ? 0 : end
- start
+ 1);
475 /* Return the machine mode to use for a comparison. */
478 select_cc_mode (op
, x
)
482 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
487 /* X and Y are two things to compare using CODE. Emit the compare insn and
488 return the rtx for register 36 in the proper mode. */
491 gen_compare_reg (code
, x
, y
)
496 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
497 enum machine_mode mode
498 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
502 if (! arith_operand (x
, mode
))
503 x
= force_reg (SImode
, x
);
504 if (! arith_operand (y
, mode
))
505 y
= force_reg (SImode
, y
);
508 cc_reg
= gen_rtx (REG
, ccmode
, 36);
509 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
510 gen_rtx (COMPARE
, ccmode
, x
, y
)));
515 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
516 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
517 are 4. Indexed addresses are cost 6. */
519 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
522 i960_address_cost (x
)
526 /* Handled before calling here. */
527 if (GET_CODE (x
) == REG
)
530 if (GET_CODE (x
) == PLUS
)
532 rtx base
= XEXP (x
, 0);
533 rtx offset
= XEXP (x
, 1);
535 if (GET_CODE (base
) == SUBREG
)
536 base
= SUBREG_REG (base
);
537 if (GET_CODE (offset
) == SUBREG
)
538 offset
= SUBREG_REG (offset
);
540 if (GET_CODE (base
) == REG
)
542 if (GET_CODE (offset
) == REG
)
544 if (GET_CODE (offset
) == CONST_INT
)
546 if ((unsigned)INTVAL (offset
) < 2047)
550 if (CONSTANT_P (offset
))
553 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
556 /* This is an invalid address. The return value doesn't matter, but
557 for convenience we make this more expensive than anything else. */
560 if (GET_CODE (x
) == MULT
)
563 /* Symbol_refs and other unrecognized addresses are cost 4. */
567 /* Emit insns to move operands[1] into operands[0].
569 Return 1 if we have written out everything that needs to be done to
570 do the move. Otherwise, return 0 and the caller will emit the move
574 emit_move_sequence (operands
, mode
)
576 enum machine_mode mode
;
578 /* We can only store registers to memory. */
580 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
581 operands
[1] = force_reg (mode
, operands
[1]);
583 /* Storing multi-word values in unaligned hard registers to memory may
584 require a scratch since we have to store them a register at a time and
585 adding 4 to the memory address may not yield a valid insn. */
586 /* ??? We don't always need the scratch, but that would complicate things.
588 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
589 && GET_CODE (operands
[0]) == MEM
590 && GET_CODE (operands
[1]) == REG
591 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
592 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
594 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
596 gen_rtx (SET
, VOIDmode
,
597 operands
[0], operands
[1]),
598 gen_rtx (CLOBBER
, VOIDmode
,
599 gen_rtx (SCRATCH
, Pmode
)))));
606 /* Output assembler to move a double word value. */
609 i960_output_move_double (dst
, src
)
614 if (GET_CODE (dst
) == REG
615 && GET_CODE (src
) == REG
)
617 if ((REGNO (src
) & 1)
618 || (REGNO (dst
) & 1))
620 /* We normally copy the low-numbered register first. However, if
621 the second source register is the same as the first destination
622 register, we must copy in the opposite order. */
623 if (REGNO (src
) + 1 == REGNO (dst
))
624 return "mov %D1,%D0\n\tmov %1,%0";
626 return "mov %1,%0\n\tmov %D1,%D0";
631 else if (GET_CODE (dst
) == REG
632 && GET_CODE (src
) == CONST_INT
633 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
636 return "mov %1,%0\n\tmov 0,%D0";
640 else if (GET_CODE (dst
) == REG
641 && GET_CODE (src
) == MEM
)
645 /* One can optimize a few cases here, but you have to be
646 careful of clobbering registers used in the address and
650 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
651 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
652 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
653 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
659 else if (GET_CODE (dst
) == MEM
660 && GET_CODE (src
) == REG
)
664 /* This is handled by emit_move_sequence so we shouldn't get here. */
673 /* Output assembler to move a quad word value. */
676 i960_output_move_quad (dst
, src
)
681 if (GET_CODE (dst
) == REG
682 && GET_CODE (src
) == REG
)
684 if ((REGNO (src
) & 3)
685 || (REGNO (dst
) & 3))
687 /* We normally copy starting with the low numbered register.
688 However, if there is an overlap such that the first dest reg
689 is <= the last source reg but not < the first source reg, we
690 must copy in the opposite order. */
691 if (REGNO (dst
) <= REGNO (src
) + 3
692 && REGNO (dst
) >= REGNO (src
))
693 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
695 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
700 else if (GET_CODE (dst
) == REG
701 && GET_CODE (src
) == CONST_INT
702 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
705 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
709 else if (GET_CODE (dst
) == REG
710 && GET_CODE (src
) == MEM
)
714 /* One can optimize a few cases here, but you have to be
715 careful of clobbering registers used in the address and
719 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
720 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
721 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
722 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
723 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
724 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
730 else if (GET_CODE (dst
) == MEM
731 && GET_CODE (src
) == REG
)
735 /* This is handled by emit_move_sequence so we shouldn't get here. */
744 /* Emit insns to load a constant to non-floating point registers.
745 Uses several strategies to try to use as few insns as possible. */
748 i960_output_ldconst (dst
, src
)
749 register rtx dst
, src
;
752 register unsigned rsrc2
;
753 enum machine_mode mode
= GET_MODE (dst
);
756 operands
[0] = operands
[2] = dst
;
757 operands
[1] = operands
[3] = src
;
759 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
760 must be a ldconst insn. */
762 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
764 output_asm_insn ("ldconst %1,%0", operands
);
767 else if (mode
== XFmode
)
773 if (fp_literal_zero (src
, XFmode
))
776 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
777 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
779 output_asm_insn ("# ldconst %1,%0",operands
);
781 for (i
= 0; i
< 3; i
++)
783 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
784 operands
[1] = GEN_INT (value_long
[i
]);
785 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
791 else if (mode
== DFmode
)
795 if (fp_literal_zero (src
, DFmode
))
798 split_double (src
, &first
, &second
);
800 output_asm_insn ("# ldconst %1,%0",operands
);
802 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
804 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
806 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
807 operands
[1] = second
;
808 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
812 else if (mode
== SFmode
)
817 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
818 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
820 output_asm_insn ("# ldconst %1,%0",operands
);
821 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
822 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
823 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
827 else if (mode
== TImode
)
829 /* ??? This is currently not handled at all. */
832 /* Note: lowest order word goes in lowest numbered reg. */
833 rsrc1
= INTVAL (src
);
834 if (rsrc1
>= 0 && rsrc1
< 32)
837 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
838 /* Go pick up the low-order word. */
840 else if (mode
== DImode
)
842 rtx upperhalf
, lowerhalf
, xoperands
[2];
844 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
845 split_double (src
, &lowerhalf
, &upperhalf
);
850 /* Note: lowest order word goes in lowest numbered reg. */
851 /* Numbers from 0 to 31 can be handled with a single insn. */
852 rsrc1
= INTVAL (lowerhalf
);
853 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
856 /* Output the upper half with a recursive call. */
857 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
858 xoperands
[1] = upperhalf
;
859 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
861 /* The lower word is emitted as normally. */
865 rsrc1
= INTVAL (src
);
871 else if (mode
== HImode
)
880 /* ldconst 0..31,X -> mov 0..31,X */
883 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
888 /* ldconst 32..63,X -> add 31,nn,X */
891 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
893 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
894 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
900 /* ldconst -1..-31 -> sub 0,0..31,X */
903 /* return 'sub -(%1),0,%0' */
904 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
905 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
909 /* ldconst -32 -> not 31,X */
912 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
913 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
918 /* If const is a single bit. */
919 if (bitpos (rsrc1
) >= 0)
921 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
922 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
926 /* If const is a bit string of less than 6 bits (1..31 shifted). */
931 if (bitstr (rsrc1
, &s
, &e
) < 6)
933 rsrc2
= ((unsigned int) rsrc1
) >> s
;
934 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
935 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
936 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
941 /* Unimplemented cases:
942 const is in range 0..31 but rotated around end of word:
943 ror 31,3,g0 -> ldconst 0xe0000003,g0
945 and any 2 instruction cases that might be worthwhile */
947 output_asm_insn ("ldconst %1,%0", operands
);
951 /* Determine if there is an opportunity for a bypass optimization.
952 Bypass succeeds on the 960K* if the destination of the previous
953 instruction is the second operand of the current instruction.
954 Bypass always succeeds on the C*.
956 Return 1 if the pattern should interchange the operands.
958 CMPBR_FLAG is true if this is for a compare-and-branch insn.
959 OP1 and OP2 are the two source operands of a 3 operand insn. */
962 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
963 register rtx insn
, op1
, op2
;
966 register rtx prev_insn
, prev_dest
;
971 /* Can't do this if op1 isn't a register. */
975 /* Can't do this for a compare-and-branch if both ops aren't regs. */
976 if (cmpbr_flag
&& ! REG_P (op2
))
979 prev_insn
= prev_real_insn (insn
);
981 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
982 && GET_CODE (PATTERN (prev_insn
)) == SET
)
984 prev_dest
= SET_DEST (PATTERN (prev_insn
));
985 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
986 || (GET_CODE (prev_dest
) == SUBREG
987 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
988 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
994 /* Output the code which declares the function name. This also handles
995 leaf routines, which have special requirements, and initializes some
999 i960_function_name_declare (file
, name
, fndecl
)
1008 /* Increment global return label. */
1012 /* Compute whether tail calls and leaf routine optimizations can be performed
1013 for this function. */
1015 if (TARGET_TAILCALL
)
1020 if (TARGET_LEAFPROC
)
1025 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1026 argblock, because argblock uses g14 implicitly. */
1028 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1034 /* See if caller passes in an address to return value. */
1036 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1042 /* Can not use tail calls or make this a leaf routine if there is a non
1045 if (get_frame_size () != 0)
1048 /* I don't understand this condition, and do not think that it is correct.
1049 Apparently this is just checking whether the frame pointer is used, and
1050 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1053 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1054 if (GET_CODE (insn
) == INSN
1055 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1061 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1064 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1065 if (GET_CODE (insn
) == CALL_INSN
)
1071 /* Can not be a leaf routine if any non-call clobbered registers are
1072 used in this function. */
1075 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1076 if (regs_ever_live
[i
]
1077 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1079 /* Global registers. */
1080 if (i
< 16 && i
> 7 && i
!= 13)
1082 /* Local registers. */
1087 /* Now choose a leaf return register, if we can find one, and if it is
1088 OK for this to be a leaf routine. */
1090 i960_leaf_ret_reg
= -1;
1092 if (optimize
&& leaf_proc_ok
)
1094 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1095 if (regs_ever_live
[i
] == 0)
1097 i960_leaf_ret_reg
= i
;
1098 regs_ever_live
[i
] = 1;
1103 /* Do this after choosing the leaf return register, so it will be listed
1104 if one was chosen. */
1106 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1107 fprintf (file
, "\t# Registers used: ");
1109 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1111 if (regs_ever_live
[i
])
1113 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1115 if (i
> 15 && j
== 0)
1117 fprintf (file
,"\n\t#\t\t ");
1123 fprintf (file
, "\n");
1125 if (i960_leaf_ret_reg
>= 0)
1127 /* Make it a leaf procedure. */
1129 if (TREE_PUBLIC (fndecl
))
1130 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1132 fprintf (file
, "\t.leafproc\t");
1133 assemble_name (file
, name
);
1134 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1135 ASM_OUTPUT_LABEL (file
, name
);
1136 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1137 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1138 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1140 if (TARGET_C_SERIES
)
1142 fprintf (file
, "\tlda 0,g14\n");
1143 i960_last_insn_type
= I_TYPE_MEM
;
1147 fprintf (file
, "\tmov 0,g14\n");
1148 i960_last_insn_type
= I_TYPE_REG
;
1153 ASM_OUTPUT_LABEL (file
, name
);
1154 i960_last_insn_type
= I_TYPE_CTRL
;
1158 /* Compute and return the frame size. */
1161 compute_frame_size (size
)
1165 int outgoing_args_size
= current_function_outgoing_args_size
;
1167 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1168 as size is concerned. */
1169 actual_fsize
= (size
+ 15) & -16;
1170 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1172 return actual_fsize
;
1175 /* Output code for the function prologue. */
1178 i960_function_prologue (file
, size
)
1182 register int i
, j
, nr
;
1185 int actual_fsize
, offset
;
1187 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1189 int regs
[FIRST_PSEUDO_REGISTER
];
1191 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1192 if (regs_ever_live
[i
]
1193 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1196 /* Count global registers that need saving. */
1203 epilogue_string
[0] = '\0';
1205 if (profile_flag
|| profile_block_flag
)
1207 /* When profiling, we may use registers 20 to 27 to save arguments, so
1208 they can't be used here for saving globals. J is the number of
1209 argument registers the mcount call will save. */
1210 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1213 for (i
= 20; i
<= j
+ 20; i
++)
1217 /* First look for local registers to save globals in. */
1218 for (i
= 0; i
< 16; i
++)
1223 /* Start at r4, not r3. */
1224 for (j
= 20; j
< 32; j
++)
1231 regs_ever_live
[j
] = 1;
1233 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1234 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1239 regs_ever_live
[j
+1] = 1;
1241 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1242 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1247 regs_ever_live
[j
+2] = 1;
1249 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1254 regs_ever_live
[j
+3] = 1;
1257 fprintf (file
, "\tmov%s %s,%s\n",
1260 (nr
== 2) ? "l" : ""),
1261 reg_names
[i
], reg_names
[j
]);
1262 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1265 (nr
== 2) ? "l" : ""),
1266 reg_names
[j
], reg_names
[i
]);
1267 strcat (epilogue_string
, tmpstr
);
1275 /* N_iregs is now the number of global registers that haven't been saved
1278 rsize
= (n_iregs
* 4);
1279 actual_fsize
= compute_frame_size (size
) + rsize
;
1281 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1282 size up to the nearest multiple of 16. I don't know whether this is
1283 necessary, or even desirable.
1285 The frame pointer must be aligned, but the call instruction takes care of
1286 that. If we leave the stack pointer unaligned, we may save a little on
1287 dynamic stack allocation. And we don't lose, at least according to the
1289 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1292 /* Allocate space for register save and locals. */
1293 if (actual_fsize
> 0)
1295 if (actual_fsize
< 32)
1296 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1298 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1301 /* Take hardware register save area created by the call instruction
1302 into account, but store them before the argument block area. */
1303 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1304 /* Save registers on stack if needed. */
1305 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1312 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1315 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1319 if (nr
== 3 && regs
[i
+3] == -1)
1322 fprintf (file
,"\tst%s %s,%d(fp)\n",
1325 (nr
== 2) ? "l" : ""),
1326 reg_names
[i
], offset
);
1327 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1330 (nr
== 2) ? "l" : ""),
1331 offset
, reg_names
[i
]);
1332 strcat (epilogue_string
, tmpstr
);
1338 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1341 fprintf (file
, "\t#Prologue stats:\n");
1342 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1345 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1347 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1349 fprintf (file
, "\t#End Prologue#\n");
1352 /* Output code for the function profiler. */
1355 output_function_profiler (file
, labelno
)
1359 /* The last used parameter register. */
1361 int i
, j
, increment
;
1362 int varargs_stdarg_function
1363 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1365 /* Figure out the last used parameter register. The proper thing to do
1366 is to walk incoming args of the function. A function might have live
1367 parameter registers even if it has no incoming args. Note that we
1368 don't have to save parameter registers g8 to g11 because they are
1371 /* See also output_function_prologue, which tries to use local registers
1372 for preserved call-saved global registers. */
1374 for (last_parm_reg
= 7;
1375 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1379 /* Save parameter registers in regs r4 (20) to r11 (27). */
1381 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1383 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1385 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1387 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1392 fprintf (file
, "\tmov%s g%d,r%d\n",
1393 (increment
== 4 ? "q" : increment
== 3 ? "t"
1394 : increment
== 2 ? "l": ""), i
, j
);
1397 /* If this function uses the arg pointer, then save it in r3 and then
1400 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1401 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1403 /* Load location address into g0 and call mcount. */
1405 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1407 /* If this function uses the arg pointer, restore it. */
1409 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1410 fprintf (file
, "\tmov r3,g14\n");
1412 /* Restore parameter registers. */
1414 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1416 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1418 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1420 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1425 fprintf (file
, "\tmov%s r%d,g%d\n",
1426 (increment
== 4 ? "q" : increment
== 3 ? "t"
1427 : increment
== 2 ? "l": ""), j
, i
);
1431 /* Output code for the function epilogue. */
1434 i960_function_epilogue (file
, size
)
1438 if (i960_leaf_ret_reg
>= 0)
1440 fprintf (file
, "LR%d: ret\n", ret_label
);
1444 if (*epilogue_string
== 0)
1448 /* Emit a return insn, but only if control can fall through to here. */
1450 tmp
= get_last_insn ();
1453 if (GET_CODE (tmp
) == BARRIER
)
1455 if (GET_CODE (tmp
) == CODE_LABEL
)
1457 if (GET_CODE (tmp
) == JUMP_INSN
)
1459 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1463 if (GET_CODE (tmp
) == NOTE
)
1465 tmp
= PREV_INSN (tmp
);
1470 fprintf (file
, "LR%d: ret\n", ret_label
);
1474 fprintf (file
, "LR%d:\n", ret_label
);
1476 fprintf (file
, "\t#EPILOGUE#\n");
1478 /* Output the string created by the prologue which will restore all
1479 registers saved by the prologue. */
1481 if (epilogue_string
[0] != '\0')
1482 fprintf (file
, "%s", epilogue_string
);
1484 /* Must clear g14 on return if this function set it.
1485 Only varargs/stdarg functions modify g14. */
1487 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1488 fprintf (file
, "\tmov 0,g14\n");
1490 fprintf (file
, "\tret\n");
1491 fprintf (file
, "\t#End Epilogue#\n");
1494 /* Output code for a call insn. */
1497 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1498 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1500 int argsize
= INTVAL (argsize_rtx
);
1501 rtx nexti
= next_real_insn (insn
);
1503 int varargs_stdarg_function
1504 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1506 operands
[0] = target
;
1507 operands
[1] = arg_pointer
;
1509 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1510 output_asm_insn ("mov g14,r3", operands
);
1513 output_asm_insn ("lda %a1,g14", operands
);
1514 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1515 output_asm_insn ("mov 0,g14", operands
);
1517 /* The code used to assume that calls to SYMBOL_REFs could not be more
1518 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1519 feature is now implemented by relaxing in the GNU linker. It can convert
1520 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1522 /* Nexti could be zero if the called routine is volatile. */
1523 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1524 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1526 /* Delete following return insn. */
1527 if (nexti
&& no_labels_between_p (insn
, nexti
))
1528 delete_insn (nexti
);
1529 output_asm_insn ("bx %0", operands
);
1530 return "# notreached";
1533 output_asm_insn ("callx %0", operands
);
1535 /* If the caller sets g14 to the address of the argblock, then the caller
1536 must clear it after the return. */
1538 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1539 output_asm_insn ("mov r3,g14", operands
);
1540 else if (argsize
> 48)
1541 output_asm_insn ("mov 0,g14", operands
);
1546 /* Output code for a return insn. */
1549 i960_output_ret_insn (insn
)
1552 static char lbuf
[20];
1554 if (*epilogue_string
!= 0)
1556 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1559 sprintf (lbuf
, "b LR%d", ret_label
);
1563 /* Must clear g14 on return if this function set it.
1564 Only varargs/stdarg functions modify g14. */
1566 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1567 output_asm_insn ("mov 0,g14", 0);
1569 if (i960_leaf_ret_reg
>= 0)
1571 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1578 /* Return a character string representing the branch prediction
1579 opcode to be tacked on an instruction. This must at least
1580 return a null string. */
1583 i960_br_predict_opcode (lab_ref
, insn
)
1586 if (TARGET_BRANCH_PREDICT
)
1588 unsigned long label_uid
;
1590 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1591 label_uid
= INSN_UID (lab_ref
);
1592 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1593 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1597 /* If not optimizing, then the insn_addresses array will not be
1598 valid. In this case, always return ".t" since most branches
1599 are taken. If optimizing, return .t for backward branches
1600 and .f for forward branches. */
1602 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1611 /* Print the operand represented by rtx X formatted by code CODE. */
1614 i960_print_operand (file
, x
, code
)
1619 enum rtx_code rtxcode
= GET_CODE (x
);
1626 /* Second reg of a double or quad. */
1627 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1631 /* Third reg of a quad. */
1632 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1636 /* Fourth reg of a quad. */
1637 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1641 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1649 else if (rtxcode
== MEM
)
1651 output_address (XEXP (x
, 0));
1654 else if (rtxcode
== CONST_INT
)
1656 HOST_WIDE_INT val
= INTVAL (x
);
1659 if (val
> 9999 || val
< -999)
1660 fprintf (file
, "0x%x", val
);
1662 fprintf (file
, "%d", val
);
1665 else if (rtxcode
== CONST_DOUBLE
)
1670 if (x
== CONST0_RTX (GET_MODE (x
)))
1672 fprintf (file
, "0f0.0");
1675 else if (x
== CONST1_RTX (GET_MODE (x
)))
1677 fprintf (file
, "0f1.0");
1681 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1682 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1683 fprintf (file
, "0f%s", dstr
);
1690 /* Branch or jump, depending on assembler. */
1691 if (TARGET_ASM_COMPAT
)
1698 /* Sign of condition. */
1699 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1700 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1702 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1703 || (rtxcode
== GE
) || (rtxcode
== LE
))
1710 /* Inverted condition. */
1711 rtxcode
= reverse_condition (rtxcode
);
1715 /* Inverted condition w/ reversed operands. */
1716 rtxcode
= reverse_condition (rtxcode
);
1720 /* Reversed operand condition. */
1721 rtxcode
= swap_condition (rtxcode
);
1725 /* Normal condition. */
1727 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1728 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1729 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1730 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1731 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1732 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1733 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1734 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1735 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1736 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1741 output_addr_const (file
, x
);
1751 /* Print a memory address as an operand to reference that memory location.
1753 This is exactly the same as legitimate_address_p, except that it the prints
1754 addresses instead of recognizing them. */
1757 i960_print_operand_addr (file
, addr
)
1769 if (GET_CODE (addr
) == REG
)
1771 else if (CONSTANT_P (addr
))
1773 else if (GET_CODE (addr
) == PLUS
)
1777 op0
= XEXP (addr
, 0);
1778 op1
= XEXP (addr
, 1);
1780 if (GET_CODE (op0
) == REG
)
1783 if (GET_CODE (op1
) == REG
)
1785 else if (CONSTANT_P (op1
))
1790 else if (GET_CODE (op0
) == PLUS
)
1792 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1794 ireg
= XEXP (XEXP (op0
, 0), 0);
1795 scale
= XEXP (XEXP (op0
, 0), 1);
1796 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1798 breg
= XEXP (op0
, 1);
1804 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1806 breg
= XEXP (op0
, 0);
1807 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1809 ireg
= XEXP (op0
, 1);
1818 else if (GET_CODE (op0
) == MULT
)
1820 ireg
= XEXP (op0
, 0);
1821 scale
= XEXP (op0
, 1);
1822 if (GET_CODE (op1
) == REG
)
1824 else if (CONSTANT_P (op1
))
1832 else if (GET_CODE (addr
) == MULT
)
1834 ireg
= XEXP (addr
, 0);
1835 scale
= XEXP (addr
, 1);
1841 output_addr_const (file
, offset
);
1843 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1845 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1848 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1849 that is a valid memory address for an instruction.
1850 The MODE argument is the machine mode for the MEM expression
1851 that wants to use this address.
1853 On 80960, legitimate addresses are:
1855 disp (12 or 32 bit) ld foo,r0
1856 base + index ld (g0)[g1*1],r0
1857 base + displ ld 0xf00(g0),r0
1858 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1859 index*scale + base ld (g0)[g1*4],r0
1860 index*scale + displ ld 0xf00[g1*4],r0
1861 index*scale ld [g1*4],r0
1862 index + base + displ ld 0xf00(g0)[g1*1],r0
1864 In each case, scale can be 1, 2, 4, 8, or 16. */
1866 /* This is exactly the same as i960_print_operand_addr, except that
1867 it recognizes addresses instead of printing them.
1869 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1870 convert common non-canonical forms to canonical form so that they will
1873 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1874 where a register is valid. */
1876 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1877 ((GET_CODE (X) == REG \
1878 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1879 || (GET_CODE (X) == SUBREG \
1880 && GET_CODE (SUBREG_REG (X)) == REG \
1881 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1882 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1884 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1885 ((GET_CODE (X) == REG \
1886 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1887 || (GET_CODE (X) == SUBREG \
1888 && GET_CODE (SUBREG_REG (X)) == REG \
1889 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1890 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1893 legitimate_address_p (mode
, addr
, strict
)
1894 enum machine_mode mode
;
1898 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1900 else if (CONSTANT_P (addr
))
1902 else if (GET_CODE (addr
) == PLUS
)
1906 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1909 op0
= XEXP (addr
, 0);
1910 op1
= XEXP (addr
, 1);
1912 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1914 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1916 else if (CONSTANT_P (op1
))
1921 else if (GET_CODE (op0
) == PLUS
)
1923 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1925 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1926 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1929 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1930 && CONSTANT_P (op1
))
1935 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1937 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1938 && CONSTANT_P (op1
))
1946 else if (GET_CODE (op0
) == MULT
)
1948 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1949 && SCALE_TERM_P (XEXP (op0
, 1))))
1952 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1954 else if (CONSTANT_P (op1
))
1962 else if (GET_CODE (addr
) == MULT
)
1964 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1967 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1968 && SCALE_TERM_P (XEXP (addr
, 1)));
1974 /* Try machine-dependent ways of modifying an illegitimate address
1975 to be legitimate. If we find one, return the new, valid address.
1976 This macro is used in only one place: `memory_address' in explow.c.
1978 This converts some non-canonical addresses to canonical form so they
1979 can be recognized. */
1982 legitimize_address (x
, oldx
, mode
)
1985 enum machine_mode mode
;
1987 if (GET_CODE (x
) == SYMBOL_REF
)
1990 x
= copy_to_reg (x
);
1993 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1996 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1997 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1998 created by virtual register instantiation, register elimination, and
1999 similar optimizations. */
2000 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2001 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2002 x
= gen_rtx (PLUS
, Pmode
,
2003 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2004 XEXP (XEXP (x
, 1), 1));
2006 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2007 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2008 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2009 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2010 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2011 && CONSTANT_P (XEXP (x
, 1)))
2013 rtx constant
, other
;
2015 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2017 constant
= XEXP (x
, 1);
2018 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2020 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2022 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2023 other
= XEXP (x
, 1);
2029 x
= gen_rtx (PLUS
, Pmode
,
2030 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2031 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2032 plus_constant (other
, INTVAL (constant
)));
2039 /* Return the most stringent alignment that we are willing to consider
2040 objects of size SIZE and known alignment ALIGN as having. */
2043 i960_alignment (size
, align
)
2049 if (! TARGET_STRICT_ALIGN
)
2050 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2052 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2061 /* Modes for condition codes. */
2063 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2065 /* Modes for single-word (and smaller) quantities. */
2068 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2069 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2071 /* Modes for double-word (and smaller) quantities. */
2074 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2076 /* Modes for quad-word quantities. */
2077 #define T_MODES (~C_MODES)
2079 /* Modes for single-float quantities. */
2080 #define SF_MODES ((1 << (int) SFmode))
2082 /* Modes for double-float quantities. */
2083 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2085 /* Modes for quad-float quantities. */
2086 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2088 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
2089 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2090 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2091 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2092 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2094 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
2097 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2098 advantage of machine specific facts, such as knowing that the frame pointer
2099 is always 16 byte aligned. */
2102 i960_expr_alignment (x
, size
)
2111 switch (GET_CODE(x
))
2116 if ((align
& 0xf) == 0)
2118 else if ((align
& 0x7) == 0)
2120 else if ((align
& 0x3) == 0)
2122 else if ((align
& 0x1) == 0)
2129 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2130 i960_expr_alignment (XEXP (x
, 1), size
));
2134 /* If this is a valid program, objects are guaranteed to be
2135 correctly aligned for whatever size the reference actually is. */
2136 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2140 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2145 align
= i960_expr_alignment (XEXP (x
, 0));
2147 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2149 align
= align
<< INTVAL (XEXP (x
, 1));
2150 align
= MIN (align
, 16);
2155 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2156 i960_expr_alignment (XEXP (x
, 1), size
));
2158 align
= MIN (align
, 16);
2165 /* Return true if it is possible to reference both BASE and OFFSET, which
2166 have alignment at least as great as 4 byte, as if they had alignment valid
2167 for an object of size SIZE. */
2170 i960_improve_align (base
, offset
, size
)
2177 /* We have at least a word reference to the object, so we know it has to
2178 be aligned at least to 4 bytes. */
2180 i
= MIN (i960_expr_alignment (base
, 4),
2181 i960_expr_alignment (offset
, 4));
2185 /* We know the size of the request. If strict align is not enabled, we
2186 can guess that the alignment is OK for the requested size. */
2188 if (! TARGET_STRICT_ALIGN
)
2189 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2195 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2196 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2199 i960_si_ti (base
, offset
)
2203 return i960_improve_align (base
, offset
, 16);
2206 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2207 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2210 i960_si_di (base
, offset
)
2214 return i960_improve_align (base
, offset
, 8);
2217 /* Return raw values of size and alignment (in words) for the data
2218 type being accessed. These values will be rounded by the caller. */
2221 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2222 enum machine_mode mode
;
2229 /* Use formal alignment requirements of type being passed, except make
2230 it at least a word. If we don't have a type, this is a library call,
2231 and the parm has to be of scalar type. In this case, consider its
2232 formal alignment requirement to be its size in words. */
2234 if (mode
== BLKmode
)
2235 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2236 else if (mode
== VOIDmode
)
2238 /* End of parm list. */
2239 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2243 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2247 /* ??? This is a hack to properly correct the alignment of XFmode
2248 values without affecting anything else. */
2254 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2255 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2263 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2264 Any arg that is bigger than 4 words is placed on the stack and all
2265 subsequent arguments are placed on the stack.
2267 Additionally, parameters with an alignment requirement stronger than
2268 a word must be aligned appropriately. Note that this means that a
2269 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2270 passed in an odd/even register pair. */
2272 /* Update CUM to advance past an argument described by MODE and TYPE. */
2275 i960_function_arg_advance (cum
, mode
, type
, named
)
2276 CUMULATIVE_ARGS
*cum
;
2277 enum machine_mode mode
;
2283 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2285 if (size
> 4 || cum
->ca_nstackparms
!= 0
2286 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2287 || MUST_PASS_IN_STACK (mode
, type
))
2289 /* Indicate that all the registers are in use, even if all are not,
2290 so va_start will compute the right value. */
2291 cum
->ca_nregparms
= NPARM_REGS
;
2292 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2295 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2298 /* Return the register that the argument described by MODE and TYPE is
2299 passed in, or else return 0 if it is passed on the stack. */
2302 i960_function_arg (cum
, mode
, type
, named
)
2303 CUMULATIVE_ARGS
*cum
;
2304 enum machine_mode mode
;
2311 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2313 if (size
> 4 || cum
->ca_nstackparms
!= 0
2314 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2315 || MUST_PASS_IN_STACK (mode
, type
))
2317 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2322 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2323 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2329 /* Floating-point support. */
2332 i960_output_long_double (file
, value
)
2334 REAL_VALUE_TYPE value
;
2339 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2340 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2343 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2344 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2345 fprintf (file
, "\t.word\t0x0\n");
2349 i960_output_double (file
, value
)
2351 REAL_VALUE_TYPE value
;
2356 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2357 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2359 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2360 value_long
[0], dstr
, value_long
[1]);
2364 i960_output_float (file
, value
)
2366 REAL_VALUE_TYPE value
;
2371 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2372 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2374 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2377 /* Return the number of bits that an object of size N bytes is aligned to. */
2380 i960_object_bytes_bitalign (n
)
2384 else if (n
> 4) n
= 64;
2385 else if (n
> 2) n
= 32;
2386 else if (n
> 1) n
= 16;
2392 /* Compute the alignment for an aggregate type TSIZE.
2393 Alignment is MAX (greatest member alignment,
2394 MIN (pragma align, structure size alignment)). */
2397 i960_round_align (align
, tsize
)
2403 if (TREE_CODE (tsize
) != INTEGER_CST
)
2406 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2408 /* Handle #pragma align. */
2409 if (new_align
> i960_maxbitalignment
)
2410 new_align
= i960_maxbitalignment
;
2412 if (align
< new_align
)
2418 /* Do any needed setup for a varargs function. For the i960, we must
2419 create a register parameter block if one doesn't exist, and then copy
2420 all register parameters to memory. */
2423 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2424 CUMULATIVE_ARGS
*cum
;
2425 enum machine_mode mode
;
2430 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2431 int first_reg
= cum
->ca_nregparms
;
2433 /* Copy only unnamed register arguments to memory. If there are
2434 any stack parms, there are no unnamed arguments in registers, and
2435 an argument block was already allocated by the caller.
2436 Remember that any arg bigger than 4 words is passed on the stack as
2437 are all subsequent args.
2439 If there are no stack arguments but there are exactly NPARM_REGS
2440 registers, either there were no extra arguments or the caller
2441 allocated an argument block. */
2443 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2445 rtx label
= gen_label_rtx ();
2448 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2449 and we need to allocate a chunk to save the registers (if any
2450 arguments were passed on the stack the caller would allocate the
2451 48 bytes as well). We must allocate all 48 bytes (12*4) because
2452 va_start assumes it. */
2453 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2454 emit_jump_insn (gen_bne (label
));
2455 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2456 stack_pointer_rtx
));
2457 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2458 memory_address (SImode
,
2459 plus_constant (stack_pointer_rtx
,
2463 /* ??? Note that we unnecessarily store one extra register for stdarg
2464 fns. We could optimize this, but it's kept as for now. */
2465 regblock
= gen_rtx (MEM
, BLKmode
,
2466 plus_constant (arg_pointer_rtx
,
2468 move_block_from_reg (first_reg
, regblock
,
2469 NPARM_REGS
- first_reg
,
2470 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2474 /* Calculate the final size of the reg parm stack space for the current
2475 function, based on how many bytes would be allocated on the stack. */
2478 i960_final_reg_parm_stack_space (const_size
, var_size
)
2482 if (var_size
|| const_size
> 48)
2488 /* Calculate the size of the reg parm stack space. This is a bit complicated
2492 i960_reg_parm_stack_space (fndecl
)
2495 /* In this case, we are called from emit_library_call, and we don't need
2496 to pretend we have more space for parameters than what's apparent. */
2500 /* In this case, we are called from locate_and_pad_parms when we're
2501 not IN_REGS, so we have an arg block. */
2502 if (fndecl
!= current_function_decl
)
2505 /* Otherwise, we have an arg block if the current function has more than
2506 48 bytes of parameters. */
2507 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2513 /* Return the register class of a scratch register needed to copy IN into
2514 or out of a register in CLASS in MODE. If it can be done directly,
2515 NO_REGS is returned. */
2518 secondary_reload_class (class, mode
, in
)
2519 enum reg_class
class;
2520 enum machine_mode mode
;
2525 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2526 regno
= true_regnum (in
);
2528 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2529 LOCAL_OR_GLOBAL_REGS into anything. */
2530 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2531 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2534 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2535 if (class == FP_REGS
2536 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2537 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2540 return LOCAL_OR_GLOBAL_REGS
;
2543 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2544 function unit it executed on. */
2546 /* ??? This would make more sense as an attribute. */
2549 i960_scan_opcode (p
)
2561 /* Ret is not actually of type REG, but it won't matter, because no
2562 insn will ever follow it. */
2565 i960_last_insn_type
= I_TYPE_REG
;
2569 if (p
[1] == 'x' || p
[3] == 'x')
2570 i960_last_insn_type
= I_TYPE_MEM
;
2571 i960_last_insn_type
= I_TYPE_CTRL
;
2576 i960_last_insn_type
= I_TYPE_CTRL
;
2583 i960_last_insn_type
= I_TYPE_MEM
;
2585 i960_last_insn_type
= I_TYPE_CTRL
;
2587 else if (p
[1] == 'm')
2590 i960_last_insn_type
= I_TYPE_REG
;
2591 else if (p
[4] == 'b' || p
[4] == 'j')
2592 i960_last_insn_type
= I_TYPE_CTRL
;
2594 i960_last_insn_type
= I_TYPE_REG
;
2597 i960_last_insn_type
= I_TYPE_REG
;
2601 i960_last_insn_type
= I_TYPE_MEM
;
2606 i960_last_insn_type
= I_TYPE_MEM
;
2608 i960_last_insn_type
= I_TYPE_REG
;