1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (finput
, t
)
100 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
103 pname
= IDENTIFIER_POINTER (t
);
105 if (strcmp (pname
, "align") == 0)
113 } while (c
== ' ' || c
== '\t');
117 while (c
>= '0' && c
<= '9')
119 if (s
< buf
+ sizeof buf
- 1)
125 /* We had to read a non-numerical character to get out of the
126 while loop---often a newline. So, we have to put it back to
127 make sure we continue to parse everything properly. */
134 /* Return to last alignment. */
135 align
= i960_last_maxbitalignment
/ 8;
142 i960_last_maxbitalignment
= i960_maxbitalignment
;
143 i960_maxbitalignment
= align
* 8;
147 /* Silently ignore bad values. */
151 /* NOTE: ic960 R3.0 pragma align definition:
153 #pragma align [(size)] | (identifier=size[,...])
154 #pragma noalign [(identifier)[,...]]
156 (all parens are optional)
158 - size is [1,2,4,8,16]
159 - noalign means size==1
160 - applies only to component elements of a struct (and union?)
161 - identifier applies to structure tag (only)
162 - missing identifier means next struct
164 - alignment rules for bitfields need more investigation */
169 /* Should be pragma 'far' or equivalent for callx/balx here. */
174 /* Initialize variables before compiling any files. */
179 if (TARGET_IC_COMPAT2_0
)
181 i960_maxbitalignment
= 8;
182 i960_last_maxbitalignment
= 128;
186 i960_maxbitalignment
= 128;
187 i960_last_maxbitalignment
= 8;
191 /* Return true if OP can be used as the source of an fp move insn. */
194 fpmove_src_operand (op
, mode
)
196 enum machine_mode mode
;
198 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
202 /* Return true if OP is a register or zero. */
205 reg_or_zero_operand (op
, mode
)
207 enum machine_mode mode
;
209 return register_operand (op
, mode
) || op
== const0_rtx
;
213 /* Return truth value of whether OP can be used as an operands in a three
214 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
217 arith_operand (op
, mode
)
219 enum machine_mode mode
;
221 return (register_operand (op
, mode
) || literal (op
, mode
));
224 /* Return truth value of whether OP can be used as an operands in a three
225 address logic insn, possibly complementing OP, of mode MODE. */
228 logic_operand (op
, mode
)
230 enum machine_mode mode
;
232 return (register_operand (op
, mode
)
233 || (GET_CODE (op
) == CONST_INT
234 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
237 /* Return true if OP is a register or a valid floating point literal. */
240 fp_arith_operand (op
, mode
)
242 enum machine_mode mode
;
244 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
247 /* Return true is OP is a register or a valid signed integer literal. */
250 signed_arith_operand (op
, mode
)
252 enum machine_mode mode
;
254 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
257 /* Return truth value of whether OP is a integer which fits the
258 range constraining immediate operands in three-address insns. */
263 enum machine_mode mode
;
265 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
268 /* Return true if OP is a float constant of 1. */
271 fp_literal_one (op
, mode
)
273 enum machine_mode mode
;
275 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
278 /* Return true if OP is a float constant of 0. */
281 fp_literal_zero (op
, mode
)
283 enum machine_mode mode
;
285 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
288 /* Return true if OP is a valid floating point literal. */
293 enum machine_mode mode
;
295 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
298 /* Return true if OP is a valid signed immediate constant. */
301 signed_literal(op
, mode
)
303 enum machine_mode mode
;
305 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
308 /* Return truth value of statement that OP is a symbolic memory
309 operand of mode MODE. */
312 symbolic_memory_operand (op
, mode
)
314 enum machine_mode mode
;
316 if (GET_CODE (op
) == SUBREG
)
317 op
= SUBREG_REG (op
);
318 if (GET_CODE (op
) != MEM
)
321 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
322 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
325 /* Return truth value of whether OP is EQ or NE. */
330 enum machine_mode mode
;
332 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
335 /* OP is an integer register or a constant. */
338 arith32_operand (op
, mode
)
340 enum machine_mode mode
;
342 if (register_operand (op
, mode
))
344 return (CONSTANT_P (op
));
347 /* Return true if OP is an integer constant which is a power of 2. */
350 power2_operand (op
,mode
)
352 enum machine_mode mode
;
354 if (GET_CODE (op
) != CONST_INT
)
357 return exact_log2 (INTVAL (op
)) >= 0;
360 /* Return true if OP is an integer constant which is the complement of a
364 cmplpower2_operand (op
, mode
)
366 enum machine_mode mode
;
368 if (GET_CODE (op
) != CONST_INT
)
371 return exact_log2 (~ INTVAL (op
)) >= 0;
374 /* If VAL has only one bit set, return the index of that bit. Otherwise
383 for (i
= 0; val
!= 0; i
++, val
>>= 1)
395 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
396 The return value indicates how many consecutive non-zero bits exist
397 if this is a mask. This is the same as the next function, except that
398 it does not indicate what the start and stop bit positions are. */
404 register int start
, end
, i
;
407 for (i
= 0; val
!= 0; val
>>= 1, i
++)
417 /* Still looking for the first bit. */
421 /* We've seen the start of a bit sequence, and now a zero. There
422 must be more one bits, otherwise we would have exited the loop.
423 Therefore, it is not a mask. */
428 /* The bit string has ones from START to END bit positions only. */
429 return end
- start
+ 1;
432 /* If VAL is a mask, then return nonzero, with S set to the starting bit
433 position and E set to the ending bit position of the mask. The return
434 value indicates how many consecutive bits exist in the mask. This is
435 the same as the previous function, except that it also indicates the
436 start and end bit positions of the mask. */
443 register int start
, end
, i
;
447 for (i
= 0; val
!= 0; val
>>= 1, i
++)
458 /* Still looking for the first bit. */
462 /* We've seen the start of a bit sequence, and now a zero. There
463 must be more one bits, otherwise we would have exited the loop.
464 Therefor, it is not a mask. */
473 /* The bit string has ones from START to END bit positions only. */
476 return ((start
< 0) ? 0 : end
- start
+ 1);
479 /* Return the machine mode to use for a comparison. */
482 select_cc_mode (op
, x
)
486 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
491 /* X and Y are two things to compare using CODE. Emit the compare insn and
492 return the rtx for register 36 in the proper mode. */
495 gen_compare_reg (code
, x
, y
)
500 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
501 enum machine_mode mode
502 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
506 if (! arith_operand (x
, mode
))
507 x
= force_reg (SImode
, x
);
508 if (! arith_operand (y
, mode
))
509 y
= force_reg (SImode
, y
);
512 cc_reg
= gen_rtx (REG
, ccmode
, 36);
513 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
514 gen_rtx (COMPARE
, ccmode
, x
, y
)));
519 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
520 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
521 are 4. Indexed addresses are cost 6. */
523 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
526 i960_address_cost (x
)
530 /* Handled before calling here. */
531 if (GET_CODE (x
) == REG
)
534 /* This is a MEMA operand -- it's free. */
535 if (GET_CODE (x
) == CONST_INT
537 && INTVAL (x
) < 4096)
540 if (GET_CODE (x
) == PLUS
)
542 rtx base
= XEXP (x
, 0);
543 rtx offset
= XEXP (x
, 1);
545 if (GET_CODE (base
) == SUBREG
)
546 base
= SUBREG_REG (base
);
547 if (GET_CODE (offset
) == SUBREG
)
548 offset
= SUBREG_REG (offset
);
550 if (GET_CODE (base
) == REG
)
552 if (GET_CODE (offset
) == REG
)
554 if (GET_CODE (offset
) == CONST_INT
)
556 if ((unsigned)INTVAL (offset
) < 2047)
560 if (CONSTANT_P (offset
))
563 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
566 /* This is an invalid address. The return value doesn't matter, but
567 for convenience we make this more expensive than anything else. */
570 if (GET_CODE (x
) == MULT
)
573 /* Symbol_refs and other unrecognized addresses are cost 4. */
577 /* Emit insns to move operands[1] into operands[0].
579 Return 1 if we have written out everything that needs to be done to
580 do the move. Otherwise, return 0 and the caller will emit the move
584 emit_move_sequence (operands
, mode
)
586 enum machine_mode mode
;
588 /* We can only store registers to memory. */
590 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
591 operands
[1] = force_reg (mode
, operands
[1]);
593 /* Storing multi-word values in unaligned hard registers to memory may
594 require a scratch since we have to store them a register at a time and
595 adding 4 to the memory address may not yield a valid insn. */
596 /* ??? We don't always need the scratch, but that would complicate things.
598 /* ??? We must also handle stores to pseudos here, because the pseudo may be
599 replaced with a MEM later. This would be cleaner if we didn't have
600 a separate pattern for unaligned DImode/TImode stores. */
601 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
602 && (GET_CODE (operands
[0]) == MEM
603 || (GET_CODE (operands
[0]) == REG
604 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
605 && GET_CODE (operands
[1]) == REG
606 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
607 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
609 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
611 gen_rtx (SET
, VOIDmode
,
612 operands
[0], operands
[1]),
613 gen_rtx (CLOBBER
, VOIDmode
,
614 gen_rtx (SCRATCH
, Pmode
)))));
621 /* Output assembler to move a double word value. */
624 i960_output_move_double (dst
, src
)
629 if (GET_CODE (dst
) == REG
630 && GET_CODE (src
) == REG
)
632 if ((REGNO (src
) & 1)
633 || (REGNO (dst
) & 1))
635 /* We normally copy the low-numbered register first. However, if
636 the second source register is the same as the first destination
637 register, we must copy in the opposite order. */
638 if (REGNO (src
) + 1 == REGNO (dst
))
639 return "mov %D1,%D0\n\tmov %1,%0";
641 return "mov %1,%0\n\tmov %D1,%D0";
646 else if (GET_CODE (dst
) == REG
647 && GET_CODE (src
) == CONST_INT
648 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
651 return "mov %1,%0\n\tmov 0,%D0";
655 else if (GET_CODE (dst
) == REG
656 && GET_CODE (src
) == MEM
)
660 /* One can optimize a few cases here, but you have to be
661 careful of clobbering registers used in the address and
665 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
666 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
667 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
668 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
674 else if (GET_CODE (dst
) == MEM
675 && GET_CODE (src
) == REG
)
679 /* This is handled by emit_move_sequence so we shouldn't get here. */
688 /* Output assembler to move a quad word value. */
691 i960_output_move_quad (dst
, src
)
696 if (GET_CODE (dst
) == REG
697 && GET_CODE (src
) == REG
)
699 if ((REGNO (src
) & 3)
700 || (REGNO (dst
) & 3))
702 /* We normally copy starting with the low numbered register.
703 However, if there is an overlap such that the first dest reg
704 is <= the last source reg but not < the first source reg, we
705 must copy in the opposite order. */
706 if (REGNO (dst
) <= REGNO (src
) + 3
707 && REGNO (dst
) >= REGNO (src
))
708 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
710 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
715 else if (GET_CODE (dst
) == REG
716 && GET_CODE (src
) == CONST_INT
717 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
720 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
724 else if (GET_CODE (dst
) == REG
725 && GET_CODE (src
) == MEM
)
729 /* One can optimize a few cases here, but you have to be
730 careful of clobbering registers used in the address and
734 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
735 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
736 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
737 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
738 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
739 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
745 else if (GET_CODE (dst
) == MEM
746 && GET_CODE (src
) == REG
)
750 /* This is handled by emit_move_sequence so we shouldn't get here. */
759 /* Emit insns to load a constant to non-floating point registers.
760 Uses several strategies to try to use as few insns as possible. */
763 i960_output_ldconst (dst
, src
)
764 register rtx dst
, src
;
767 register unsigned rsrc2
;
768 enum machine_mode mode
= GET_MODE (dst
);
771 operands
[0] = operands
[2] = dst
;
772 operands
[1] = operands
[3] = src
;
774 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
775 must be a ldconst insn. */
777 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
779 output_asm_insn ("ldconst %1,%0", operands
);
782 else if (mode
== XFmode
)
788 if (fp_literal_zero (src
, XFmode
))
791 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
792 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
794 output_asm_insn ("# ldconst %1,%0",operands
);
796 for (i
= 0; i
< 3; i
++)
798 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
799 operands
[1] = GEN_INT (value_long
[i
]);
800 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
806 else if (mode
== DFmode
)
810 if (fp_literal_zero (src
, DFmode
))
813 split_double (src
, &first
, &second
);
815 output_asm_insn ("# ldconst %1,%0",operands
);
817 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
819 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
821 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
822 operands
[1] = second
;
823 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
827 else if (mode
== SFmode
)
832 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
833 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
835 output_asm_insn ("# ldconst %1,%0",operands
);
836 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
837 operands
[1] = GEN_INT (value
);
838 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
842 else if (mode
== TImode
)
844 /* ??? This is currently not handled at all. */
847 /* Note: lowest order word goes in lowest numbered reg. */
848 rsrc1
= INTVAL (src
);
849 if (rsrc1
>= 0 && rsrc1
< 32)
852 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
853 /* Go pick up the low-order word. */
855 else if (mode
== DImode
)
857 rtx upperhalf
, lowerhalf
, xoperands
[2];
859 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
860 split_double (src
, &lowerhalf
, &upperhalf
);
865 /* Note: lowest order word goes in lowest numbered reg. */
866 /* Numbers from 0 to 31 can be handled with a single insn. */
867 rsrc1
= INTVAL (lowerhalf
);
868 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
871 /* Output the upper half with a recursive call. */
872 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
873 xoperands
[1] = upperhalf
;
874 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
876 /* The lower word is emitted as normally. */
880 rsrc1
= INTVAL (src
);
886 else if (mode
== HImode
)
895 /* ldconst 0..31,X -> mov 0..31,X */
898 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
903 /* ldconst 32..63,X -> add 31,nn,X */
906 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
908 operands
[1] = GEN_INT (rsrc1
- 31);
909 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
915 /* ldconst -1..-31 -> sub 0,0..31,X */
918 /* return 'sub -(%1),0,%0' */
919 operands
[1] = GEN_INT (- rsrc1
);
920 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
924 /* ldconst -32 -> not 31,X */
927 operands
[1] = GEN_INT (~rsrc1
);
928 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
933 /* If const is a single bit. */
934 if (bitpos (rsrc1
) >= 0)
936 operands
[1] = GEN_INT (bitpos (rsrc1
));
937 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
941 /* If const is a bit string of less than 6 bits (1..31 shifted). */
946 if (bitstr (rsrc1
, &s
, &e
) < 6)
948 rsrc2
= ((unsigned int) rsrc1
) >> s
;
949 operands
[1] = GEN_INT (rsrc2
);
950 operands
[2] = GEN_INT (s
);
951 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
956 /* Unimplemented cases:
957 const is in range 0..31 but rotated around end of word:
958 ror 31,3,g0 -> ldconst 0xe0000003,g0
960 and any 2 instruction cases that might be worthwhile */
962 output_asm_insn ("ldconst %1,%0", operands
);
966 /* Determine if there is an opportunity for a bypass optimization.
967 Bypass succeeds on the 960K* if the destination of the previous
968 instruction is the second operand of the current instruction.
969 Bypass always succeeds on the C*.
971 Return 1 if the pattern should interchange the operands.
973 CMPBR_FLAG is true if this is for a compare-and-branch insn.
974 OP1 and OP2 are the two source operands of a 3 operand insn. */
977 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
978 register rtx insn
, op1
, op2
;
981 register rtx prev_insn
, prev_dest
;
986 /* Can't do this if op1 isn't a register. */
990 /* Can't do this for a compare-and-branch if both ops aren't regs. */
991 if (cmpbr_flag
&& ! REG_P (op2
))
994 prev_insn
= prev_real_insn (insn
);
996 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
997 && GET_CODE (PATTERN (prev_insn
)) == SET
)
999 prev_dest
= SET_DEST (PATTERN (prev_insn
));
1000 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
1001 || (GET_CODE (prev_dest
) == SUBREG
1002 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
1003 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1009 /* Output the code which declares the function name. This also handles
1010 leaf routines, which have special requirements, and initializes some
1011 global variables. */
1014 i960_function_name_declare (file
, name
, fndecl
)
1023 /* Increment global return label. */
1027 /* Compute whether tail calls and leaf routine optimizations can be performed
1028 for this function. */
1030 if (TARGET_TAILCALL
)
1035 if (TARGET_LEAFPROC
)
1040 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1041 argblock, because argblock uses g14 implicitly. */
1043 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1049 /* See if caller passes in an address to return value. */
1051 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1057 /* Can not use tail calls or make this a leaf routine if there is a non
1060 if (get_frame_size () != 0)
1063 /* I don't understand this condition, and do not think that it is correct.
1064 Apparently this is just checking whether the frame pointer is used, and
1065 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1068 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1069 if (GET_CODE (insn
) == INSN
1070 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1076 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1079 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1080 if (GET_CODE (insn
) == CALL_INSN
)
1086 /* Can not be a leaf routine if any non-call clobbered registers are
1087 used in this function. */
1090 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1091 if (regs_ever_live
[i
]
1092 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1094 /* Global registers. */
1095 if (i
< 16 && i
> 7 && i
!= 13)
1097 /* Local registers. */
1102 /* Now choose a leaf return register, if we can find one, and if it is
1103 OK for this to be a leaf routine. */
1105 i960_leaf_ret_reg
= -1;
1107 if (optimize
&& leaf_proc_ok
)
1109 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1110 if (regs_ever_live
[i
] == 0)
1112 i960_leaf_ret_reg
= i
;
1113 regs_ever_live
[i
] = 1;
1118 /* Do this after choosing the leaf return register, so it will be listed
1119 if one was chosen. */
1121 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1122 fprintf (file
, "\t# Registers used: ");
1124 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1126 if (regs_ever_live
[i
])
1128 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1130 if (i
> 15 && j
== 0)
1132 fprintf (file
,"\n\t#\t\t ");
1138 fprintf (file
, "\n");
1140 if (i960_leaf_ret_reg
>= 0)
1142 /* Make it a leaf procedure. */
1144 if (TREE_PUBLIC (fndecl
))
1145 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1147 fprintf (file
, "\t.leafproc\t");
1148 assemble_name (file
, name
);
1149 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1150 ASM_OUTPUT_LABEL (file
, name
);
1151 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1152 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1153 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1155 if (TARGET_C_SERIES
)
1157 fprintf (file
, "\tlda 0,g14\n");
1158 i960_last_insn_type
= I_TYPE_MEM
;
1162 fprintf (file
, "\tmov 0,g14\n");
1163 i960_last_insn_type
= I_TYPE_REG
;
1168 ASM_OUTPUT_LABEL (file
, name
);
1169 i960_last_insn_type
= I_TYPE_CTRL
;
1173 /* Compute and return the frame size. */
1176 compute_frame_size (size
)
1180 int outgoing_args_size
= current_function_outgoing_args_size
;
1182 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1183 as size is concerned. */
1184 actual_fsize
= (size
+ 15) & -16;
1185 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1187 return actual_fsize
;
1190 /* Output code for the function prologue. */
1193 i960_function_prologue (file
, size
)
1197 register int i
, j
, nr
;
1200 int actual_fsize
, offset
;
1202 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1204 int regs
[FIRST_PSEUDO_REGISTER
];
1206 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1207 if (regs_ever_live
[i
]
1208 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1211 /* Count global registers that need saving. */
1218 epilogue_string
[0] = '\0';
1220 if (profile_flag
|| profile_block_flag
)
1222 /* When profiling, we may use registers 20 to 27 to save arguments, so
1223 they can't be used here for saving globals. J is the number of
1224 argument registers the mcount call will save. */
1225 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1228 for (i
= 20; i
<= j
+ 20; i
++)
1232 /* First look for local registers to save globals in. */
1233 for (i
= 0; i
< 16; i
++)
1238 /* Start at r4, not r3. */
1239 for (j
= 20; j
< 32; j
++)
1246 regs_ever_live
[j
] = 1;
1248 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1249 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1254 regs_ever_live
[j
+1] = 1;
1256 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1257 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1262 regs_ever_live
[j
+2] = 1;
1264 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1269 regs_ever_live
[j
+3] = 1;
1272 fprintf (file
, "\tmov%s %s,%s\n",
1275 (nr
== 2) ? "l" : ""),
1276 reg_names
[i
], reg_names
[j
]);
1277 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1280 (nr
== 2) ? "l" : ""),
1281 reg_names
[j
], reg_names
[i
]);
1282 strcat (epilogue_string
, tmpstr
);
1290 /* N_iregs is now the number of global registers that haven't been saved
1293 rsize
= (n_iregs
* 4);
1294 actual_fsize
= compute_frame_size (size
) + rsize
;
1296 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1297 size up to the nearest multiple of 16. I don't know whether this is
1298 necessary, or even desirable.
1300 The frame pointer must be aligned, but the call instruction takes care of
1301 that. If we leave the stack pointer unaligned, we may save a little on
1302 dynamic stack allocation. And we don't lose, at least according to the
1304 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1307 /* Allocate space for register save and locals. */
1308 if (actual_fsize
> 0)
1310 if (actual_fsize
< 32)
1311 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1313 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1316 /* Take hardware register save area created by the call instruction
1317 into account, but store them before the argument block area. */
1318 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1319 /* Save registers on stack if needed. */
1320 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1327 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1330 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1334 if (nr
== 3 && regs
[i
+3] == -1)
1337 fprintf (file
,"\tst%s %s,%d(fp)\n",
1340 (nr
== 2) ? "l" : ""),
1341 reg_names
[i
], offset
);
1342 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1345 (nr
== 2) ? "l" : ""),
1346 offset
, reg_names
[i
]);
1347 strcat (epilogue_string
, tmpstr
);
1353 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1356 fprintf (file
, "\t#Prologue stats:\n");
1357 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1360 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1362 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1364 fprintf (file
, "\t#End Prologue#\n");
1367 /* Output code for the function profiler. */
1370 output_function_profiler (file
, labelno
)
1374 /* The last used parameter register. */
1376 int i
, j
, increment
;
1377 int varargs_stdarg_function
1378 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1380 /* Figure out the last used parameter register. The proper thing to do
1381 is to walk incoming args of the function. A function might have live
1382 parameter registers even if it has no incoming args. Note that we
1383 don't have to save parameter registers g8 to g11 because they are
1386 /* See also output_function_prologue, which tries to use local registers
1387 for preserved call-saved global registers. */
1389 for (last_parm_reg
= 7;
1390 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1394 /* Save parameter registers in regs r4 (20) to r11 (27). */
1396 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1398 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1400 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1402 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1407 fprintf (file
, "\tmov%s g%d,r%d\n",
1408 (increment
== 4 ? "q" : increment
== 3 ? "t"
1409 : increment
== 2 ? "l": ""), i
, j
);
1412 /* If this function uses the arg pointer, then save it in r3 and then
1415 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1416 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1418 /* Load location address into g0 and call mcount. */
1420 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1422 /* If this function uses the arg pointer, restore it. */
1424 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1425 fprintf (file
, "\tmov r3,g14\n");
1427 /* Restore parameter registers. */
1429 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1431 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1433 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1435 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1440 fprintf (file
, "\tmov%s r%d,g%d\n",
1441 (increment
== 4 ? "q" : increment
== 3 ? "t"
1442 : increment
== 2 ? "l": ""), j
, i
);
1446 /* Output code for the function epilogue. */
1449 i960_function_epilogue (file
, size
)
1453 if (i960_leaf_ret_reg
>= 0)
1455 fprintf (file
, "LR%d: ret\n", ret_label
);
1459 if (*epilogue_string
== 0)
1463 /* Emit a return insn, but only if control can fall through to here. */
1465 tmp
= get_last_insn ();
1468 if (GET_CODE (tmp
) == BARRIER
)
1470 if (GET_CODE (tmp
) == CODE_LABEL
)
1472 if (GET_CODE (tmp
) == JUMP_INSN
)
1474 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1478 if (GET_CODE (tmp
) == NOTE
)
1480 tmp
= PREV_INSN (tmp
);
1485 fprintf (file
, "LR%d: ret\n", ret_label
);
1489 fprintf (file
, "LR%d:\n", ret_label
);
1491 fprintf (file
, "\t#EPILOGUE#\n");
1493 /* Output the string created by the prologue which will restore all
1494 registers saved by the prologue. */
1496 if (epilogue_string
[0] != '\0')
1497 fprintf (file
, "%s", epilogue_string
);
1499 /* Must clear g14 on return if this function set it.
1500 Only varargs/stdarg functions modify g14. */
1502 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1503 fprintf (file
, "\tmov 0,g14\n");
1505 fprintf (file
, "\tret\n");
1506 fprintf (file
, "\t#End Epilogue#\n");
1509 /* Output code for a call insn. */
1512 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1513 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1515 int argsize
= INTVAL (argsize_rtx
);
1516 rtx nexti
= next_real_insn (insn
);
1518 int varargs_stdarg_function
1519 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1521 operands
[0] = target
;
1522 operands
[1] = arg_pointer
;
1524 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1525 output_asm_insn ("mov g14,r3", operands
);
1528 output_asm_insn ("lda %a1,g14", operands
);
1529 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1530 output_asm_insn ("mov 0,g14", operands
);
1532 /* The code used to assume that calls to SYMBOL_REFs could not be more
1533 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1534 feature is now implemented by relaxing in the GNU linker. It can convert
1535 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1537 /* Nexti could be zero if the called routine is volatile. */
1538 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1539 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1541 /* Delete following return insn. */
1542 if (nexti
&& no_labels_between_p (insn
, nexti
))
1543 delete_insn (nexti
);
1544 output_asm_insn ("bx %0", operands
);
1545 return "# notreached";
1548 output_asm_insn ("callx %0", operands
);
1550 /* If the caller sets g14 to the address of the argblock, then the caller
1551 must clear it after the return. */
1553 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1554 output_asm_insn ("mov r3,g14", operands
);
1555 else if (argsize
> 48)
1556 output_asm_insn ("mov 0,g14", operands
);
1561 /* Output code for a return insn. */
1564 i960_output_ret_insn (insn
)
1567 static char lbuf
[20];
1569 if (*epilogue_string
!= 0)
1571 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1574 sprintf (lbuf
, "b LR%d", ret_label
);
1578 /* Must clear g14 on return if this function set it.
1579 Only varargs/stdarg functions modify g14. */
1581 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1582 output_asm_insn ("mov 0,g14", 0);
1584 if (i960_leaf_ret_reg
>= 0)
1586 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1593 /* Return a character string representing the branch prediction
1594 opcode to be tacked on an instruction. This must at least
1595 return a null string. */
1598 i960_br_predict_opcode (lab_ref
, insn
)
1601 if (TARGET_BRANCH_PREDICT
)
1603 unsigned long label_uid
;
1605 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1606 label_uid
= INSN_UID (lab_ref
);
1607 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1608 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1612 /* If not optimizing, then the insn_addresses array will not be
1613 valid. In this case, always return ".t" since most branches
1614 are taken. If optimizing, return .t for backward branches
1615 and .f for forward branches. */
1617 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1626 /* Print the operand represented by rtx X formatted by code CODE. */
1629 i960_print_operand (file
, x
, code
)
1634 enum rtx_code rtxcode
= GET_CODE (x
);
1641 /* Second reg of a double or quad. */
1642 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1646 /* Third reg of a quad. */
1647 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1651 /* Fourth reg of a quad. */
1652 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1656 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1664 else if (rtxcode
== MEM
)
1666 output_address (XEXP (x
, 0));
1669 else if (rtxcode
== CONST_INT
)
1671 HOST_WIDE_INT val
= INTVAL (x
);
1674 if (val
> 9999 || val
< -999)
1675 fprintf (file
, "0x%x", val
);
1677 fprintf (file
, "%d", val
);
1680 else if (rtxcode
== CONST_DOUBLE
)
1685 if (x
== CONST0_RTX (GET_MODE (x
)))
1687 fprintf (file
, "0f0.0");
1690 else if (x
== CONST1_RTX (GET_MODE (x
)))
1692 fprintf (file
, "0f1.0");
1696 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1697 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1698 fprintf (file
, "0f%s", dstr
);
1705 /* Branch or jump, depending on assembler. */
1706 if (TARGET_ASM_COMPAT
)
1713 /* Sign of condition. */
1714 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1715 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1717 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1718 || (rtxcode
== GE
) || (rtxcode
== LE
))
1725 /* Inverted condition. */
1726 rtxcode
= reverse_condition (rtxcode
);
1730 /* Inverted condition w/ reversed operands. */
1731 rtxcode
= reverse_condition (rtxcode
);
1735 /* Reversed operand condition. */
1736 rtxcode
= swap_condition (rtxcode
);
1740 /* Normal condition. */
1742 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1743 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1744 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1745 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1746 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1747 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1748 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1749 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1750 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1751 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1756 output_addr_const (file
, x
);
1766 /* Print a memory address as an operand to reference that memory location.
1768 This is exactly the same as legitimate_address_p, except that it the prints
1769 addresses instead of recognizing them. */
1772 i960_print_operand_addr (file
, addr
)
1784 if (GET_CODE (addr
) == REG
)
1786 else if (CONSTANT_P (addr
))
1788 else if (GET_CODE (addr
) == PLUS
)
1792 op0
= XEXP (addr
, 0);
1793 op1
= XEXP (addr
, 1);
1795 if (GET_CODE (op0
) == REG
)
1798 if (GET_CODE (op1
) == REG
)
1800 else if (CONSTANT_P (op1
))
1805 else if (GET_CODE (op0
) == PLUS
)
1807 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1809 ireg
= XEXP (XEXP (op0
, 0), 0);
1810 scale
= XEXP (XEXP (op0
, 0), 1);
1811 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1813 breg
= XEXP (op0
, 1);
1819 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1821 breg
= XEXP (op0
, 0);
1822 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1824 ireg
= XEXP (op0
, 1);
1833 else if (GET_CODE (op0
) == MULT
)
1835 ireg
= XEXP (op0
, 0);
1836 scale
= XEXP (op0
, 1);
1837 if (GET_CODE (op1
) == REG
)
1839 else if (CONSTANT_P (op1
))
1847 else if (GET_CODE (addr
) == MULT
)
1849 ireg
= XEXP (addr
, 0);
1850 scale
= XEXP (addr
, 1);
1856 output_addr_const (file
, offset
);
1858 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1860 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1863 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1864 that is a valid memory address for an instruction.
1865 The MODE argument is the machine mode for the MEM expression
1866 that wants to use this address.
1868 On 80960, legitimate addresses are:
1870 disp (12 or 32 bit) ld foo,r0
1871 base + index ld (g0)[g1*1],r0
1872 base + displ ld 0xf00(g0),r0
1873 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1874 index*scale + base ld (g0)[g1*4],r0
1875 index*scale + displ ld 0xf00[g1*4],r0
1876 index*scale ld [g1*4],r0
1877 index + base + displ ld 0xf00(g0)[g1*1],r0
1879 In each case, scale can be 1, 2, 4, 8, or 16. */
1881 /* This is exactly the same as i960_print_operand_addr, except that
1882 it recognizes addresses instead of printing them.
1884 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1885 convert common non-canonical forms to canonical form so that they will
1888 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1889 where a register is valid. */
1891 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1892 ((GET_CODE (X) == REG \
1893 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1894 || (GET_CODE (X) == SUBREG \
1895 && GET_CODE (SUBREG_REG (X)) == REG \
1896 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1897 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1899 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1900 ((GET_CODE (X) == REG \
1901 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1902 || (GET_CODE (X) == SUBREG \
1903 && GET_CODE (SUBREG_REG (X)) == REG \
1904 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1905 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1908 legitimate_address_p (mode
, addr
, strict
)
1909 enum machine_mode mode
;
1913 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1915 else if (CONSTANT_P (addr
))
1917 else if (GET_CODE (addr
) == PLUS
)
1921 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1924 op0
= XEXP (addr
, 0);
1925 op1
= XEXP (addr
, 1);
1927 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1929 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1931 else if (CONSTANT_P (op1
))
1936 else if (GET_CODE (op0
) == PLUS
)
1938 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1940 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1941 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1944 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1945 && CONSTANT_P (op1
))
1950 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1952 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1953 && CONSTANT_P (op1
))
1961 else if (GET_CODE (op0
) == MULT
)
1963 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1964 && SCALE_TERM_P (XEXP (op0
, 1))))
1967 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1969 else if (CONSTANT_P (op1
))
1977 else if (GET_CODE (addr
) == MULT
)
1979 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1982 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1983 && SCALE_TERM_P (XEXP (addr
, 1)));
1989 /* Try machine-dependent ways of modifying an illegitimate address
1990 to be legitimate. If we find one, return the new, valid address.
1991 This macro is used in only one place: `memory_address' in explow.c.
1993 This converts some non-canonical addresses to canonical form so they
1994 can be recognized. */
1997 legitimize_address (x
, oldx
, mode
)
2000 enum machine_mode mode
;
2002 if (GET_CODE (x
) == SYMBOL_REF
)
2005 x
= copy_to_reg (x
);
2008 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2011 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2012 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2013 created by virtual register instantiation, register elimination, and
2014 similar optimizations. */
2015 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2016 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2017 x
= gen_rtx (PLUS
, Pmode
,
2018 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2019 XEXP (XEXP (x
, 1), 1));
2021 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2022 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2023 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2024 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2025 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2026 && CONSTANT_P (XEXP (x
, 1)))
2028 rtx constant
, other
;
2030 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2032 constant
= XEXP (x
, 1);
2033 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2035 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2037 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2038 other
= XEXP (x
, 1);
2044 x
= gen_rtx (PLUS
, Pmode
,
2045 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2046 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2047 plus_constant (other
, INTVAL (constant
)));
2054 /* Return the most stringent alignment that we are willing to consider
2055 objects of size SIZE and known alignment ALIGN as having. */
2058 i960_alignment (size
, align
)
2064 if (! TARGET_STRICT_ALIGN
)
2065 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2067 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2078 hard_regno_mode_ok (regno
, mode
)
2080 enum machine_mode mode
;
2086 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2089 case DImode
: case DFmode
:
2090 return (regno
& 1) == 0;
2092 case TImode
: case XFmode
:
2093 return (regno
& 3) == 0;
2099 else if (regno
>= 32 && regno
< 36)
2103 case SFmode
: case DFmode
: case XFmode
:
2104 case SCmode
: case DCmode
:
2111 else if (regno
== 36)
2115 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2122 else if (regno
== 37)
2129 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2130 advantage of machine specific facts, such as knowing that the frame pointer
2131 is always 16 byte aligned. */
2134 i960_expr_alignment (x
, size
)
2143 switch (GET_CODE(x
))
2148 if ((align
& 0xf) == 0)
2150 else if ((align
& 0x7) == 0)
2152 else if ((align
& 0x3) == 0)
2154 else if ((align
& 0x1) == 0)
2161 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2162 i960_expr_alignment (XEXP (x
, 1), size
));
2166 /* If this is a valid program, objects are guaranteed to be
2167 correctly aligned for whatever size the reference actually is. */
2168 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2172 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2177 align
= i960_expr_alignment (XEXP (x
, 0));
2179 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2181 align
= align
<< INTVAL (XEXP (x
, 1));
2182 align
= MIN (align
, 16);
2187 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2188 i960_expr_alignment (XEXP (x
, 1), size
));
2190 align
= MIN (align
, 16);
2197 /* Return true if it is possible to reference both BASE and OFFSET, which
2198 have alignment at least as great as 4 byte, as if they had alignment valid
2199 for an object of size SIZE. */
2202 i960_improve_align (base
, offset
, size
)
2209 /* We have at least a word reference to the object, so we know it has to
2210 be aligned at least to 4 bytes. */
2212 i
= MIN (i960_expr_alignment (base
, 4),
2213 i960_expr_alignment (offset
, 4));
2217 /* We know the size of the request. If strict align is not enabled, we
2218 can guess that the alignment is OK for the requested size. */
2220 if (! TARGET_STRICT_ALIGN
)
2221 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2227 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2228 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2231 i960_si_ti (base
, offset
)
2235 return i960_improve_align (base
, offset
, 16);
2238 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2239 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2242 i960_si_di (base
, offset
)
2246 return i960_improve_align (base
, offset
, 8);
2249 /* Return raw values of size and alignment (in words) for the data
2250 type being accessed. These values will be rounded by the caller. */
2253 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2254 enum machine_mode mode
;
2261 /* Use formal alignment requirements of type being passed, except make
2262 it at least a word. If we don't have a type, this is a library call,
2263 and the parm has to be of scalar type. In this case, consider its
2264 formal alignment requirement to be its size in words. */
2266 if (mode
== BLKmode
)
2267 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2268 else if (mode
== VOIDmode
)
2270 /* End of parm list. */
2271 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2276 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2280 /* ??? This is a hack to properly correct the alignment of XFmode
2281 values without affecting anything else. */
2287 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2288 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2296 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2297 Any arg that is bigger than 4 words is placed on the stack and all
2298 subsequent arguments are placed on the stack.
2300 Additionally, parameters with an alignment requirement stronger than
2301 a word must be aligned appropriately. Note that this means that a
2302 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2303 passed in an odd/even register pair. */
2305 /* Update CUM to advance past an argument described by MODE and TYPE. */
2308 i960_function_arg_advance (cum
, mode
, type
, named
)
2309 CUMULATIVE_ARGS
*cum
;
2310 enum machine_mode mode
;
2316 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2318 if (size
> 4 || cum
->ca_nstackparms
!= 0
2319 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2320 || MUST_PASS_IN_STACK (mode
, type
))
2322 /* Indicate that all the registers are in use, even if all are not,
2323 so va_start will compute the right value. */
2324 cum
->ca_nregparms
= NPARM_REGS
;
2325 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2328 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2331 /* Return the register that the argument described by MODE and TYPE is
2332 passed in, or else return 0 if it is passed on the stack. */
2335 i960_function_arg (cum
, mode
, type
, named
)
2336 CUMULATIVE_ARGS
*cum
;
2337 enum machine_mode mode
;
2344 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2346 if (size
> 4 || cum
->ca_nstackparms
!= 0
2347 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2348 || MUST_PASS_IN_STACK (mode
, type
))
2350 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2355 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2356 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2362 /* Floating-point support. */
2365 i960_output_long_double (file
, value
)
2367 REAL_VALUE_TYPE value
;
2372 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2373 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2376 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2377 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2378 fprintf (file
, "\t.word\t0x0\n");
2382 i960_output_double (file
, value
)
2384 REAL_VALUE_TYPE value
;
2389 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2390 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2392 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2393 value_long
[0], dstr
, value_long
[1]);
2397 i960_output_float (file
, value
)
2399 REAL_VALUE_TYPE value
;
2404 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2405 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2407 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2410 /* Return the number of bits that an object of size N bytes is aligned to. */
2413 i960_object_bytes_bitalign (n
)
2417 else if (n
> 4) n
= 64;
2418 else if (n
> 2) n
= 32;
2419 else if (n
> 1) n
= 16;
2425 /* Compute the alignment for an aggregate type TSIZE.
2426 Alignment is MAX (greatest member alignment,
2427 MIN (pragma align, structure size alignment)). */
2430 i960_round_align (align
, tsize
)
2436 if (TREE_CODE (tsize
) != INTEGER_CST
)
2439 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2441 /* Handle #pragma align. */
2442 if (new_align
> i960_maxbitalignment
)
2443 new_align
= i960_maxbitalignment
;
2445 if (align
< new_align
)
2451 /* Do any needed setup for a varargs function. For the i960, we must
2452 create a register parameter block if one doesn't exist, and then copy
2453 all register parameters to memory. */
2456 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2457 CUMULATIVE_ARGS
*cum
;
2458 enum machine_mode mode
;
2463 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2464 int first_reg
= cum
->ca_nregparms
;
2466 /* Copy only unnamed register arguments to memory. If there are
2467 any stack parms, there are no unnamed arguments in registers, and
2468 an argument block was already allocated by the caller.
2469 Remember that any arg bigger than 4 words is passed on the stack as
2470 are all subsequent args.
2472 If there are no stack arguments but there are exactly NPARM_REGS
2473 registers, either there were no extra arguments or the caller
2474 allocated an argument block. */
2476 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2478 rtx label
= gen_label_rtx ();
2481 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2482 and we need to allocate a chunk to save the registers (if any
2483 arguments were passed on the stack the caller would allocate the
2484 48 bytes as well). We must allocate all 48 bytes (12*4) because
2485 va_start assumes it. */
2486 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2487 emit_jump_insn (gen_bne (label
));
2488 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2489 stack_pointer_rtx
));
2490 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2491 memory_address (SImode
,
2492 plus_constant (stack_pointer_rtx
,
2496 /* ??? Note that we unnecessarily store one extra register for stdarg
2497 fns. We could optimize this, but it's kept as for now. */
2498 regblock
= gen_rtx (MEM
, BLKmode
,
2499 plus_constant (arg_pointer_rtx
,
2501 move_block_from_reg (first_reg
, regblock
,
2502 NPARM_REGS
- first_reg
,
2503 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2507 /* Calculate the final size of the reg parm stack space for the current
2508 function, based on how many bytes would be allocated on the stack. */
2511 i960_final_reg_parm_stack_space (const_size
, var_size
)
2515 if (var_size
|| const_size
> 48)
2521 /* Calculate the size of the reg parm stack space. This is a bit complicated
2525 i960_reg_parm_stack_space (fndecl
)
2528 /* In this case, we are called from emit_library_call, and we don't need
2529 to pretend we have more space for parameters than what's apparent. */
2533 /* In this case, we are called from locate_and_pad_parms when we're
2534 not IN_REGS, so we have an arg block. */
2535 if (fndecl
!= current_function_decl
)
2538 /* Otherwise, we have an arg block if the current function has more than
2539 48 bytes of parameters. */
2540 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2546 /* Return the register class of a scratch register needed to copy IN into
2547 or out of a register in CLASS in MODE. If it can be done directly,
2548 NO_REGS is returned. */
2551 secondary_reload_class (class, mode
, in
)
2552 enum reg_class
class;
2553 enum machine_mode mode
;
2558 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2559 regno
= true_regnum (in
);
2561 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2562 LOCAL_OR_GLOBAL_REGS into anything. */
2563 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2564 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2567 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2568 if (class == FP_REGS
2569 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2570 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2573 return LOCAL_OR_GLOBAL_REGS
;
2576 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2577 function unit it executed on. */
2579 /* ??? This would make more sense as an attribute. */
2582 i960_scan_opcode (p
)
2594 /* Ret is not actually of type REG, but it won't matter, because no
2595 insn will ever follow it. */
2598 i960_last_insn_type
= I_TYPE_REG
;
2602 if (p
[1] == 'x' || p
[3] == 'x')
2603 i960_last_insn_type
= I_TYPE_MEM
;
2604 i960_last_insn_type
= I_TYPE_CTRL
;
2609 i960_last_insn_type
= I_TYPE_CTRL
;
2616 i960_last_insn_type
= I_TYPE_MEM
;
2618 i960_last_insn_type
= I_TYPE_CTRL
;
2620 else if (p
[1] == 'm')
2623 i960_last_insn_type
= I_TYPE_REG
;
2624 else if (p
[4] == 'b' || p
[4] == 'j')
2625 i960_last_insn_type
= I_TYPE_CTRL
;
2627 i960_last_insn_type
= I_TYPE_REG
;
2630 i960_last_insn_type
= I_TYPE_REG
;
2634 i960_last_insn_type
= I_TYPE_MEM
;
2639 i960_last_insn_type
= I_TYPE_MEM
;
2641 i960_last_insn_type
= I_TYPE_REG
;