1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (finput
)
99 while (c
== ' ' || c
== '\t')
103 && getc (finput
) == 'l'
104 && getc (finput
) == 'i'
105 && getc (finput
) == 'g'
106 && getc (finput
) == 'n'
107 && ((c
= getc (finput
)) == ' ' || c
== '\t' || c
== '\n'))
113 while (c
== ' ' || c
== '\t')
117 while (c
>= '0' && c
<= '9')
119 if (s
< buf
+ sizeof buf
- 1)
129 /* Return to last alignment. */
130 align
= i960_last_maxbitalignment
/ 8;
137 i960_last_maxbitalignment
= i960_maxbitalignment
;
138 i960_maxbitalignment
= align
* 8;
142 /* Silently ignore bad values. */
146 /* NOTE: ic960 R3.0 pragma align definition:
148 #pragma align [(size)] | (identifier=size[,...])
149 #pragma noalign [(identifier)[,...]]
151 (all parens are optional)
153 - size is [1,2,4,8,16]
154 - noalign means size==1
155 - applies only to component elements of a struct (and union?)
156 - identifier applies to structure tag (only)
157 - missing identifier means next struct
159 - alignment rules for bitfields need more investigation */
162 /* Should be pragma 'far' or equivalent for callx/balx here. */
167 /* Initialize variables before compiling any files. */
172 if (TARGET_IC_COMPAT2_0
)
174 i960_maxbitalignment
= 8;
175 i960_last_maxbitalignment
= 128;
179 i960_maxbitalignment
= 128;
180 i960_last_maxbitalignment
= 8;
184 /* Return true if OP can be used as the source of an fp move insn. */
187 fpmove_src_operand (op
, mode
)
189 enum machine_mode mode
;
191 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
195 /* Return true if OP is a register or zero. */
198 reg_or_zero_operand (op
, mode
)
200 enum machine_mode mode
;
202 return register_operand (op
, mode
) || op
== const0_rtx
;
206 /* Return truth value of whether OP can be used as an operands in a three
207 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
210 arith_operand (op
, mode
)
212 enum machine_mode mode
;
214 return (register_operand (op
, mode
) || literal (op
, mode
));
217 /* Return true if OP is a register or a valid floating point literal. */
220 fp_arith_operand (op
, mode
)
222 enum machine_mode mode
;
224 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
227 /* Return true is OP is a register or a valid signed integer literal. */
230 signed_arith_operand (op
, mode
)
232 enum machine_mode mode
;
234 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
237 /* Return truth value of whether OP is a integer which fits the
238 range constraining immediate operands in three-address insns. */
243 enum machine_mode mode
;
245 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
248 /* Return true if OP is a float constant of 1. */
251 fp_literal_one (op
, mode
)
253 enum machine_mode mode
;
255 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
258 /* Return true if OP is a float constant of 0. */
261 fp_literal_zero (op
, mode
)
263 enum machine_mode mode
;
265 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
268 /* Return true if OP is a valid floating point literal. */
273 enum machine_mode mode
;
275 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
278 /* Return true if OP is a valid signed immediate constant. */
281 signed_literal(op
, mode
)
283 enum machine_mode mode
;
285 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
288 /* Return truth value of statement that OP is a symbolic memory
289 operand of mode MODE. */
292 symbolic_memory_operand (op
, mode
)
294 enum machine_mode mode
;
296 if (GET_CODE (op
) == SUBREG
)
297 op
= SUBREG_REG (op
);
298 if (GET_CODE (op
) != MEM
)
301 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
302 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
305 /* Return truth value of whether OP is EQ or NE. */
310 enum machine_mode mode
;
312 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
315 /* OP is an integer register or a constant. */
318 arith32_operand (op
, mode
)
320 enum machine_mode mode
;
322 if (register_operand (op
, mode
))
324 return (CONSTANT_P (op
));
327 /* Return true if OP is an integer constant which is a power of 2. */
330 power2_operand (op
,mode
)
332 enum machine_mode mode
;
334 if (GET_CODE (op
) != CONST_INT
)
337 return exact_log2 (INTVAL (op
)) >= 0;
340 /* Return true if OP is an integer constant which is the complement of a
344 cmplpower2_operand (op
, mode
)
346 enum machine_mode mode
;
348 if (GET_CODE (op
) != CONST_INT
)
351 return exact_log2 (~ INTVAL (op
)) >= 0;
354 /* If VAL has only one bit set, return the index of that bit. Otherwise
363 for (i
= 0; val
!= 0; i
++, val
>>= 1)
375 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
376 The return value indicates how many consecutive non-zero bits exist
377 if this is a mask. This is the same as the next function, except that
378 it does not indicate what the start and stop bit positions are. */
384 register int start
, end
, i
;
387 for (i
= 0; val
!= 0; val
>>= 1, i
++)
397 /* Still looking for the first bit. */
401 /* We've seen the start of a bit sequence, and now a zero. There
402 must be more one bits, otherwise we would have exited the loop.
403 Therefore, it is not a mask. */
408 /* The bit string has ones from START to END bit positions only. */
409 return end
- start
+ 1;
412 /* If VAL is a mask, then return nonzero, with S set to the starting bit
413 position and E set to the ending bit position of the mask. The return
414 value indicates how many consecutive bits exist in the mask. This is
415 the same as the previous function, except that it also indicates the
416 start and end bit positions of the mask. */
423 register int start
, end
, i
;
427 for (i
= 0; val
!= 0; val
>>= 1, i
++)
438 /* Still looking for the first bit. */
442 /* We've seen the start of a bit sequence, and now a zero. There
443 must be more one bits, otherwise we would have exited the loop.
444 Therefor, it is not a mask. */
453 /* The bit string has ones from START to END bit positions only. */
456 return ((start
< 0) ? 0 : end
- start
+ 1);
459 /* Return the machine mode to use for a comparison. */
462 select_cc_mode (op
, x
)
466 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
471 /* X and Y are two things to compare using CODE. Emit the compare insn and
472 return the rtx for register 36 in the proper mode. */
475 gen_compare_reg (code
, x
, y
)
480 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
481 enum machine_mode mode
482 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
486 if (! arith_operand (x
, mode
))
487 x
= force_reg (SImode
, x
);
488 if (! arith_operand (y
, mode
))
489 y
= force_reg (SImode
, y
);
492 cc_reg
= gen_rtx (REG
, ccmode
, 36);
493 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
494 gen_rtx (COMPARE
, ccmode
, x
, y
)));
499 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
500 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
501 are 4. Indexed addresses are cost 6. */
503 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
506 i960_address_cost (x
)
510 /* Handled before calling here. */
511 if (GET_CODE (x
) == REG
)
514 if (GET_CODE (x
) == PLUS
)
516 rtx base
= XEXP (x
, 0);
517 rtx offset
= XEXP (x
, 1);
519 if (GET_CODE (base
) == SUBREG
)
520 base
= SUBREG_REG (base
);
521 if (GET_CODE (offset
) == SUBREG
)
522 offset
= SUBREG_REG (offset
);
524 if (GET_CODE (base
) == REG
)
526 if (GET_CODE (offset
) == REG
)
528 if (GET_CODE (offset
) == CONST_INT
)
530 if ((unsigned)INTVAL (offset
) < 2047)
534 if (CONSTANT_P (offset
))
537 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
540 /* This is an invalid address. The return value doesn't matter, but
541 for convenience we make this more expensive than anything else. */
544 if (GET_CODE (x
) == MULT
)
547 /* Symbol_refs and other unrecognized addresses are cost 4. */
551 /* Emit insns to move operands[1] into operands[0].
553 Return 1 if we have written out everything that needs to be done to
554 do the move. Otherwise, return 0 and the caller will emit the move
558 emit_move_sequence (operands
, mode
)
560 enum machine_mode mode
;
562 register rtx operand0
= operands
[0];
563 register rtx operand1
= operands
[1];
565 /* We can only store registers to memory. */
567 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
568 operands
[1] = force_reg (mode
, operand1
);
573 /* Emit insns to load a constant to non-floating point registers.
574 Uses several strategies to try to use as few insns as possible. */
577 i960_output_ldconst (dst
, src
)
578 register rtx dst
, src
;
581 register unsigned rsrc2
;
582 enum machine_mode mode
= GET_MODE (dst
);
585 operands
[0] = operands
[2] = dst
;
586 operands
[1] = operands
[3] = src
;
588 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
589 must be a ldconst insn. */
591 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
593 output_asm_insn ("ldconst %1,%0", operands
);
596 else if (mode
== XFmode
)
602 if (fp_literal_zero (src
, XFmode
))
605 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
606 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
608 output_asm_insn ("# ldconst %1,%0",operands
);
610 for (i
= 0; i
< 3; i
++)
612 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
613 operands
[1] = GEN_INT (value_long
[i
]);
614 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
620 else if (mode
== DFmode
)
624 if (fp_literal_zero (src
, DFmode
))
627 split_double (src
, &first
, &second
);
629 output_asm_insn ("# ldconst %1,%0",operands
);
631 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
633 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
635 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
636 operands
[1] = second
;
637 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
641 else if (mode
== SFmode
)
646 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
647 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
649 output_asm_insn ("# ldconst %1,%0",operands
);
650 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
651 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
652 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
656 else if (mode
== TImode
)
658 /* ??? This is currently not handled at all. */
661 /* Note: lowest order word goes in lowest numbered reg. */
662 rsrc1
= INTVAL (src
);
663 if (rsrc1
>= 0 && rsrc1
< 32)
666 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
667 /* Go pick up the low-order word. */
669 else if (mode
== DImode
)
671 rtx upperhalf
, lowerhalf
, xoperands
[2];
673 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
674 split_double (src
, &lowerhalf
, &upperhalf
);
679 /* Note: lowest order word goes in lowest numbered reg. */
680 /* Numbers from 0 to 31 can be handled with a single insn. */
681 rsrc1
= INTVAL (lowerhalf
);
682 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
685 /* Output the upper half with a recursive call. */
686 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
687 xoperands
[1] = upperhalf
;
688 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
690 /* The lower word is emitted as normally. */
694 rsrc1
= INTVAL (src
);
700 else if (mode
== HImode
)
709 /* ldconst 0..31,X -> mov 0..31,X */
712 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
717 /* ldconst 32..63,X -> add 31,nn,X */
720 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
722 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
723 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
729 /* ldconst -1..-31 -> sub 0,0..31,X */
732 /* return 'sub -(%1),0,%0' */
733 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
734 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
738 /* ldconst -32 -> not 31,X */
741 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
742 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
747 /* If const is a single bit. */
748 if (bitpos (rsrc1
) >= 0)
750 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
751 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
755 /* If const is a bit string of less than 6 bits (1..31 shifted). */
760 if (bitstr (rsrc1
, &s
, &e
) < 6)
762 rsrc2
= ((unsigned int) rsrc1
) >> s
;
763 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
764 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
765 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
770 /* Unimplemented cases:
771 const is in range 0..31 but rotated around end of word:
772 ror 31,3,g0 -> ldconst 0xe0000003,g0
774 and any 2 instruction cases that might be worthwhile */
776 output_asm_insn ("ldconst %1,%0", operands
);
780 /* Determine if there is an opportunity for a bypass optimization.
781 Bypass succeeds on the 960K* if the destination of the previous
782 instruction is the second operand of the current instruction.
783 Bypass always succeeds on the C*.
785 Return 1 if the pattern should interchange the operands.
787 CMPBR_FLAG is true if this is for a compare-and-branch insn.
788 OP1 and OP2 are the two source operands of a 3 operand insn. */
791 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
792 register rtx insn
, op1
, op2
;
795 register rtx prev_insn
, prev_dest
;
800 /* Can't do this if op1 isn't a register. */
804 /* Can't do this for a compare-and-branch if both ops aren't regs. */
805 if (cmpbr_flag
&& ! REG_P (op2
))
808 prev_insn
= prev_real_insn (insn
);
810 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
811 && GET_CODE (PATTERN (prev_insn
)) == SET
)
813 prev_dest
= SET_DEST (PATTERN (prev_insn
));
814 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
815 || (GET_CODE (prev_dest
) == SUBREG
816 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
817 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
823 /* Output the code which declares the function name. This also handles
824 leaf routines, which have special requirements, and initializes some
828 i960_function_name_declare (file
, name
, fndecl
)
837 /* Increment global return label. */
841 /* Compute whether tail calls and leaf routine optimizations can be performed
842 for this function. */
854 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
855 argblock, because argblock uses g14 implicitly. */
857 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
863 /* See if caller passes in an address to return value. */
865 if (aggregate_value_p (DECL_RESULT (fndecl
)))
871 /* Can not use tail calls or make this a leaf routine if there is a non
874 if (get_frame_size () != 0)
877 /* I don't understand this condition, and do not think that it is correct.
878 Apparently this is just checking whether the frame pointer is used, and
879 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
882 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
883 if (GET_CODE (insn
) == INSN
884 && reg_mentioned_p (frame_pointer_rtx
, insn
))
890 /* Check for CALL insns. Can not be a leaf routine if there are any. */
893 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
894 if (GET_CODE (insn
) == CALL_INSN
)
900 /* Can not be a leaf routine if any non-call clobbered registers are
901 used in this function. */
904 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
905 if (regs_ever_live
[i
]
906 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
908 /* Global registers. */
909 if (i
< 16 && i
> 7 && i
!= 13)
911 /* Local registers. */
916 /* Now choose a leaf return register, if we can find one, and if it is
917 OK for this to be a leaf routine. */
919 i960_leaf_ret_reg
= -1;
921 if (optimize
&& leaf_proc_ok
)
923 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
924 if (regs_ever_live
[i
] == 0)
926 i960_leaf_ret_reg
= i
;
927 regs_ever_live
[i
] = 1;
932 /* Do this after choosing the leaf return register, so it will be listed
933 if one was chosen. */
935 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
936 fprintf (file
, "\t# Registers used: ");
938 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
940 if (regs_ever_live
[i
])
942 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
944 if (i
> 15 && j
== 0)
946 fprintf (file
,"\n\t#\t\t ");
952 fprintf (file
, "\n");
954 if (i960_leaf_ret_reg
>= 0)
956 /* Make it a leaf procedure. */
958 if (TREE_PUBLIC (fndecl
))
959 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
961 fprintf (file
, "\t.leafproc\t");
962 assemble_name (file
, name
);
963 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
964 ASM_OUTPUT_LABEL (file
, name
);
965 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
966 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
967 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
971 fprintf (file
, "\tlda 0,g14\n");
972 i960_last_insn_type
= I_TYPE_MEM
;
976 fprintf (file
, "\tmov 0,g14\n");
977 i960_last_insn_type
= I_TYPE_REG
;
982 ASM_OUTPUT_LABEL (file
, name
);
983 i960_last_insn_type
= I_TYPE_CTRL
;
987 /* Compute and return the frame size. */
990 compute_frame_size (size
)
994 int outgoing_args_size
= current_function_outgoing_args_size
;
996 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
997 as size is concerned. */
998 actual_fsize
= (size
+ 15) & -16;
999 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1001 return actual_fsize
;
1004 /* Output code for the function prologue. */
1007 i960_function_prologue (file
, size
)
1011 register int i
, j
, nr
;
1014 int actual_fsize
, offset
;
1016 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1018 int regs
[FIRST_PSEUDO_REGISTER
];
1020 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1021 if (regs_ever_live
[i
]
1022 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1025 /* Count global registers that need saving. */
1032 epilogue_string
[0] = '\0';
1034 if (profile_flag
|| profile_block_flag
)
1036 /* When profiling, we may use registers 20 to 27 to save arguments, so
1037 they can't be used here for saving globals. J is the number of
1038 argument registers the mcount call will save. */
1039 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1042 for (i
= 20; i
<= j
+ 20; i
++)
1046 /* First look for local registers to save globals in. */
1047 for (i
= 0; i
< 16; i
++)
1052 /* Start at r4, not r3. */
1053 for (j
= 20; j
< 32; j
++)
1060 regs_ever_live
[j
] = 1;
1062 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1063 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1068 regs_ever_live
[j
+1] = 1;
1070 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1071 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1076 regs_ever_live
[j
+2] = 1;
1078 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1083 regs_ever_live
[j
+3] = 1;
1086 fprintf (file
, "\tmov%s %s,%s\n",
1089 (nr
== 2) ? "l" : ""),
1090 reg_names
[i
], reg_names
[j
]);
1091 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1094 (nr
== 2) ? "l" : ""),
1095 reg_names
[j
], reg_names
[i
]);
1096 strcat (epilogue_string
, tmpstr
);
1104 /* N_iregs is now the number of global registers that haven't been saved
1107 rsize
= (n_iregs
* 4);
1108 actual_fsize
= compute_frame_size (size
) + rsize
;
1110 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1111 size up to the nearest multiple of 16. I don't know whether this is
1112 necessary, or even desirable.
1114 The frame pointer must be aligned, but the call instruction takes care of
1115 that. If we leave the stack pointer unaligned, we may save a little on
1116 dynamic stack allocation. And we don't lose, at least according to the
1118 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1121 /* Allocate space for register save and locals. */
1122 if (actual_fsize
> 0)
1124 if (actual_fsize
< 32)
1125 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1127 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1130 /* Take hardware register save area created by the call instruction
1131 into account, but store them before the argument block area. */
1132 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1133 /* Save registers on stack if needed. */
1134 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1141 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1144 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1148 if (nr
== 3 && regs
[i
+3] == -1)
1151 fprintf (file
,"\tst%s %s,%d(fp)\n",
1154 (nr
== 2) ? "l" : ""),
1155 reg_names
[i
], offset
);
1156 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1159 (nr
== 2) ? "l" : ""),
1160 offset
, reg_names
[i
]);
1161 strcat (epilogue_string
, tmpstr
);
1167 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1170 fprintf (file
, "\t#Prologue stats:\n");
1171 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1174 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1176 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1178 fprintf (file
, "\t#End Prologue#\n");
1181 /* Output code for the function profiler. */
1184 output_function_profiler (file
, labelno
)
1188 /* The last used parameter register. */
1190 int i
, j
, increment
;
1191 int varargs_stdarg_function
1192 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1194 /* Figure out the last used parameter register. The proper thing to do
1195 is to walk incoming args of the function. A function might have live
1196 parameter registers even if it has no incoming args. Note that we
1197 don't have to save parameter registers g8 to g11 because they are
1200 /* See also output_function_prologue, which tries to use local registers
1201 for preserved call-saved global registers. */
1203 for (last_parm_reg
= 7;
1204 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1208 /* Save parameter registers in regs r4 (20) to r11 (27). */
1210 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1212 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1214 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1216 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1221 fprintf (file
, "\tmov%s g%d,r%d\n",
1222 (increment
== 4 ? "q" : increment
== 3 ? "t"
1223 : increment
== 2 ? "l": ""), i
, j
);
1226 /* If this function uses the arg pointer, then save it in r3 and then
1229 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1230 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1232 /* Load location address into g0 and call mcount. */
1234 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1236 /* If this function uses the arg pointer, restore it. */
1238 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1239 fprintf (file
, "\tmov r3,g14\n");
1241 /* Restore parameter registers. */
1243 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1245 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1247 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1249 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1254 fprintf (file
, "\tmov%s r%d,g%d\n",
1255 (increment
== 4 ? "q" : increment
== 3 ? "t"
1256 : increment
== 2 ? "l": ""), j
, i
);
1260 /* Output code for the function epilogue. */
1263 i960_function_epilogue (file
, size
)
1267 if (i960_leaf_ret_reg
>= 0)
1269 fprintf (file
, "LR%d: ret\n", ret_label
);
1273 if (*epilogue_string
== 0)
1277 /* Emit a return insn, but only if control can fall through to here. */
1279 tmp
= get_last_insn ();
1282 if (GET_CODE (tmp
) == BARRIER
)
1284 if (GET_CODE (tmp
) == CODE_LABEL
)
1286 if (GET_CODE (tmp
) == JUMP_INSN
)
1288 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1292 if (GET_CODE (tmp
) == NOTE
)
1294 tmp
= PREV_INSN (tmp
);
1299 fprintf (file
, "LR%d: ret\n", ret_label
);
1303 fprintf (file
, "LR%d:\n", ret_label
);
1305 fprintf (file
, "\t#EPILOGUE#\n");
1307 /* Output the string created by the prologue which will restore all
1308 registers saved by the prologue. */
1310 if (epilogue_string
[0] != '\0')
1311 fprintf (file
, "%s", epilogue_string
);
1313 /* Must clear g14 on return. */
1315 if (current_function_args_size
!= 0
1316 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1317 fprintf (file
, "\tmov 0,g14\n");
1319 fprintf (file
, "\tret\n");
1320 fprintf (file
, "\t#End Epilogue#\n");
1323 /* Output code for a call insn. */
1326 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1327 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1329 int argsize
= INTVAL (argsize_rtx
);
1330 rtx nexti
= next_real_insn (insn
);
1332 int varargs_stdarg_function
1333 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1335 operands
[0] = target
;
1336 operands
[1] = arg_pointer
;
1338 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1339 output_asm_insn ("mov g14,r3", operands
);
1342 output_asm_insn ("lda %a1,g14", operands
);
1343 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1344 output_asm_insn ("mov 0,g14", operands
);
1346 /* The code used to assume that calls to SYMBOL_REFs could not be more
1347 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1348 feature is now implemented by relaxing in the GNU linker. It can convert
1349 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1351 /* Nexti could be zero if the called routine is volatile. */
1352 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1353 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1355 /* Delete following return insn. */
1356 if (nexti
&& no_labels_between_p (insn
, nexti
))
1357 delete_insn (nexti
);
1358 output_asm_insn ("bx %0", operands
);
1359 return "# notreached";
1362 output_asm_insn ("callx %0", operands
);
1364 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1365 output_asm_insn ("mov r3,g14", operands
);
1370 /* Output code for a return insn. */
1373 i960_output_ret_insn (insn
)
1376 static char lbuf
[20];
1378 if (*epilogue_string
!= 0)
1380 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1383 sprintf (lbuf
, "b LR%d", ret_label
);
1387 if (current_function_args_size
!= 0
1388 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1389 output_asm_insn ("mov 0,g14", 0);
1391 if (i960_leaf_ret_reg
>= 0)
1393 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1400 /* Return a character string representing the branch prediction
1401 opcode to be tacked on an instruction. This must at least
1402 return a null string. */
1405 i960_br_predict_opcode (lab_ref
, insn
)
1408 if (TARGET_BRANCH_PREDICT
)
1410 unsigned long label_uid
;
1412 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1413 label_uid
= INSN_UID (lab_ref
);
1414 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1415 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1419 /* If not optimizing, then the insn_addresses array will not be
1420 valid. In this case, always return ".t" since most branches
1421 are taken. If optimizing, return .t for backward branches
1422 and .f for forward branches. */
1424 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1433 /* Print the operand represented by rtx X formatted by code CODE. */
1436 i960_print_operand (file
, x
, code
)
1441 enum rtx_code rtxcode
= GET_CODE (x
);
1448 /* Second reg of a double. */
1449 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1453 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1461 else if (rtxcode
== MEM
)
1463 output_address (XEXP (x
, 0));
1466 else if (rtxcode
== CONST_INT
)
1468 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1469 fprintf (file
, "0x%x", INTVAL (x
));
1471 fprintf (file
, "%d", INTVAL (x
));
1474 else if (rtxcode
== CONST_DOUBLE
)
1479 if (x
== CONST0_RTX (GET_MODE (x
)))
1481 fprintf (file
, "0f0.0");
1484 else if (x
== CONST1_RTX (GET_MODE (x
)))
1486 fprintf (file
, "0f1.0");
1490 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1491 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1492 fprintf (file
, "0f%s", dstr
);
1499 /* Branch or jump, depending on assembler. */
1500 if (TARGET_ASM_COMPAT
)
1507 /* Sign of condition. */
1508 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1509 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1511 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1512 || (rtxcode
== GE
) || (rtxcode
== LE
))
1519 /* Inverted condition. */
1520 rtxcode
= reverse_condition (rtxcode
);
1524 /* Inverted condition w/ reversed operands. */
1525 rtxcode
= reverse_condition (rtxcode
);
1529 /* Reversed operand condition. */
1530 rtxcode
= swap_condition (rtxcode
);
1534 /* Normal condition. */
1536 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1537 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1538 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1539 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1540 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1541 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1542 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1543 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1544 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1545 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1550 output_addr_const (file
, x
);
1560 /* Print a memory address as an operand to reference that memory location.
1562 This is exactly the same as legitimate_address_p, except that it the prints
1563 addresses instead of recognizing them. */
1566 i960_print_operand_addr (file
, addr
)
1578 if (GET_CODE (addr
) == REG
)
1580 else if (CONSTANT_P (addr
))
1582 else if (GET_CODE (addr
) == PLUS
)
1586 op0
= XEXP (addr
, 0);
1587 op1
= XEXP (addr
, 1);
1589 if (GET_CODE (op0
) == REG
)
1592 if (GET_CODE (op1
) == REG
)
1594 else if (CONSTANT_P (op1
))
1599 else if (GET_CODE (op0
) == PLUS
)
1601 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1603 ireg
= XEXP (XEXP (op0
, 0), 0);
1604 scale
= XEXP (XEXP (op0
, 0), 1);
1605 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1607 breg
= XEXP (op0
, 1);
1613 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1615 breg
= XEXP (op0
, 0);
1616 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1618 ireg
= XEXP (op0
, 1);
1627 else if (GET_CODE (op0
) == MULT
)
1629 ireg
= XEXP (op0
, 0);
1630 scale
= XEXP (op0
, 1);
1631 if (GET_CODE (op1
) == REG
)
1633 else if (CONSTANT_P (op1
))
1641 else if (GET_CODE (addr
) == MULT
)
1643 ireg
= XEXP (addr
, 0);
1644 scale
= XEXP (addr
, 1);
1650 output_addr_const (file
, offset
);
1652 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1654 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1657 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1658 that is a valid memory address for an instruction.
1659 The MODE argument is the machine mode for the MEM expression
1660 that wants to use this address.
1662 On 80960, legitimate addresses are:
1664 disp (12 or 32 bit) ld foo,r0
1665 base + index ld (g0)[g1*1],r0
1666 base + displ ld 0xf00(g0),r0
1667 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1668 index*scale + base ld (g0)[g1*4],r0
1669 index*scale + displ ld 0xf00[g1*4],r0
1670 index*scale ld [g1*4],r0
1671 index + base + displ ld 0xf00(g0)[g1*1],r0
1673 In each case, scale can be 1, 2, 4, 8, or 16. */
1675 /* This is exactly the same as i960_print_operand_addr, except that
1676 it recognizes addresses instead of printing them.
1678 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1679 convert common non-canonical forms to canonical form so that they will
1682 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1683 where a register is valid. */
1685 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1686 ((GET_CODE (X) == REG \
1687 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1688 || (GET_CODE (X) == SUBREG \
1689 && GET_CODE (SUBREG_REG (X)) == REG \
1690 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1691 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1693 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1694 ((GET_CODE (X) == REG \
1695 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1696 || (GET_CODE (X) == SUBREG \
1697 && GET_CODE (SUBREG_REG (X)) == REG \
1698 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1699 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1702 legitimate_address_p (mode
, addr
, strict
)
1703 enum machine_mode mode
;
1707 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1709 else if (CONSTANT_P (addr
))
1711 else if (GET_CODE (addr
) == PLUS
)
1715 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1718 op0
= XEXP (addr
, 0);
1719 op1
= XEXP (addr
, 1);
1721 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1723 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1725 else if (CONSTANT_P (op1
))
1730 else if (GET_CODE (op0
) == PLUS
)
1732 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1734 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1735 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1738 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1739 && CONSTANT_P (op1
))
1744 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1746 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1747 && CONSTANT_P (op1
))
1755 else if (GET_CODE (op0
) == MULT
)
1757 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1758 && SCALE_TERM_P (XEXP (op0
, 1))))
1761 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1763 else if (CONSTANT_P (op1
))
1771 else if (GET_CODE (addr
) == MULT
)
1773 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1776 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1777 && SCALE_TERM_P (XEXP (addr
, 1)));
1783 /* Try machine-dependent ways of modifying an illegitimate address
1784 to be legitimate. If we find one, return the new, valid address.
1785 This macro is used in only one place: `memory_address' in explow.c.
1787 This converts some non-canonical addresses to canonical form so they
1788 can be recognized. */
1791 legitimize_address (x
, oldx
, mode
)
1794 enum machine_mode mode
;
1796 if (GET_CODE (x
) == SYMBOL_REF
)
1799 x
= copy_to_reg (x
);
1802 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1805 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1806 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1807 created by virtual register instantiation, register elimination, and
1808 similar optimizations. */
1809 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1810 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1811 x
= gen_rtx (PLUS
, Pmode
,
1812 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1813 XEXP (XEXP (x
, 1), 1));
1815 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1816 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1817 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1818 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1819 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1820 && CONSTANT_P (XEXP (x
, 1)))
1822 rtx constant
, other
;
1824 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1826 constant
= XEXP (x
, 1);
1827 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1829 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1831 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1832 other
= XEXP (x
, 1);
1838 x
= gen_rtx (PLUS
, Pmode
,
1839 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1840 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1841 plus_constant (other
, INTVAL (constant
)));
1848 /* Return the most stringent alignment that we are willing to consider
1849 objects of size SIZE and known alignment ALIGN as having. */
1852 i960_alignment (size
, align
)
1858 if (! TARGET_STRICT_ALIGN
)
1859 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1861 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1870 /* Modes for condition codes. */
1872 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1874 /* Modes for single-word (and smaller) quantities. */
1877 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1878 | (1 << (int) DFmode) | (1 << (int) XFmode)))
1880 /* Modes for double-word (and smaller) quantities. */
1883 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
1885 /* Modes for quad-word quantities. */
1886 #define T_MODES (~C_MODES)
1888 /* Modes for single-float quantities. */
1889 #define SF_MODES ((1 << (int) SFmode))
1891 /* Modes for double-float quantities. */
1892 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1894 /* Modes for quad-float quantities. */
1895 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
1897 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1898 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1899 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1900 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1901 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1903 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
1906 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1907 advantage of machine specific facts, such as knowing that the frame pointer
1908 is always 16 byte aligned. */
1911 i960_expr_alignment (x
, size
)
1920 switch (GET_CODE(x
))
1925 if ((align
& 0xf) == 0)
1927 else if ((align
& 0x7) == 0)
1929 else if ((align
& 0x3) == 0)
1931 else if ((align
& 0x1) == 0)
1938 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1939 i960_expr_alignment (XEXP (x
, 1), size
));
1943 /* If this is a valid program, objects are guaranteed to be
1944 correctly aligned for whatever size the reference actually is. */
1945 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1949 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1954 align
= i960_expr_alignment (XEXP (x
, 0));
1956 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1958 align
= align
<< INTVAL (XEXP (x
, 1));
1959 align
= MIN (align
, 16);
1964 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1965 i960_expr_alignment (XEXP (x
, 1), size
));
1967 align
= MIN (align
, 16);
1974 /* Return true if it is possible to reference both BASE and OFFSET, which
1975 have alignment at least as great as 4 byte, as if they had alignment valid
1976 for an object of size SIZE. */
1979 i960_improve_align (base
, offset
, size
)
1986 /* We have at least a word reference to the object, so we know it has to
1987 be aligned at least to 4 bytes. */
1989 i
= MIN (i960_expr_alignment (base
, 4),
1990 i960_expr_alignment (offset
, 4));
1994 /* We know the size of the request. If strict align is not enabled, we
1995 can guess that the alignment is OK for the requested size. */
1997 if (! TARGET_STRICT_ALIGN
)
1998 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2004 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2005 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2008 i960_si_ti (base
, offset
)
2012 return i960_improve_align (base
, offset
, 16);
2015 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2016 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2019 i960_si_di (base
, offset
)
2023 return i960_improve_align (base
, offset
, 8);
2026 /* Return raw values of size and alignment (in words) for the data
2027 type being accessed. These values will be rounded by the caller. */
2030 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2031 enum machine_mode mode
;
2038 /* Use formal alignment requirements of type being passed, except make
2039 it at least a word. If we don't have a type, this is a library call,
2040 and the parm has to be of scalar type. In this case, consider its
2041 formal alignment requirement to be its size in words. */
2043 if (mode
== BLKmode
)
2044 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2045 else if (mode
== VOIDmode
)
2047 /* End of parm list. */
2048 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2052 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2056 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2057 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2065 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2066 Any arg that is bigger than 4 words is placed on the stack and all
2067 subsequent arguments are placed on the stack.
2069 Additionally, parameters with an alignment requirement stronger than
2070 a word must be be aligned appropriately. */
2072 /* Update CUM to advance past an argument described by MODE and TYPE. */
2075 i960_function_arg_advance (cum
, mode
, type
, named
)
2076 CUMULATIVE_ARGS
*cum
;
2077 enum machine_mode mode
;
2083 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2085 if (size
> 4 || cum
->ca_nstackparms
!= 0
2086 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2087 || MUST_PASS_IN_STACK (mode
, type
))
2089 /* Indicate that all the registers are in use, even if all are not,
2090 so va_start will compute the right value. */
2091 cum
->ca_nregparms
= NPARM_REGS
;
2092 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2095 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2098 /* Return the register that the argument described by MODE and TYPE is
2099 passed in, or else return 0 if it is passed on the stack. */
2102 i960_function_arg (cum
, mode
, type
, named
)
2103 CUMULATIVE_ARGS
*cum
;
2104 enum machine_mode mode
;
2111 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2113 if (size
> 4 || cum
->ca_nstackparms
!= 0
2114 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2115 || MUST_PASS_IN_STACK (mode
, type
))
2117 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2122 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2123 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2129 /* Floating-point support. */
2132 i960_output_long_double (file
, value
)
2134 REAL_VALUE_TYPE value
;
2139 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2140 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2143 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2144 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2145 fprintf (file
, "\t.word\t0x0\n");
2149 i960_output_double (file
, value
)
2151 REAL_VALUE_TYPE value
;
2156 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2157 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2159 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2160 value_long
[0], dstr
, value_long
[1]);
2164 i960_output_float (file
, value
)
2166 REAL_VALUE_TYPE value
;
2171 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2172 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2174 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2177 /* Return the number of bits that an object of size N bytes is aligned to. */
2180 i960_object_bytes_bitalign (n
)
2184 else if (n
> 4) n
= 64;
2185 else if (n
> 2) n
= 32;
2186 else if (n
> 1) n
= 16;
2192 /* Compute the alignment for an aggregate type TSIZE.
2193 Alignment is MAX (greatest member alignment,
2194 MIN (pragma align, structure size alignment)). */
2197 i960_round_align (align
, tsize
)
2203 if (TREE_CODE (tsize
) != INTEGER_CST
)
2206 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2208 /* Handle #pragma align. */
2209 if (new_align
> i960_maxbitalignment
)
2210 new_align
= i960_maxbitalignment
;
2212 if (align
< new_align
)
2218 /* Do any needed setup for a varargs function. For the i960, we must
2219 create a register parameter block if one doesn't exist, and then copy
2220 all register parameters to memory. */
2223 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2224 CUMULATIVE_ARGS
*cum
;
2225 enum machine_mode mode
;
2230 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2231 int first_reg
= cum
->ca_nregparms
;
2233 /* Copy only unnamed register arguments to memory. If there are
2234 any stack parms, there are no unnamed arguments in registers, and
2235 an argument block was already allocated by the caller.
2236 Remember that any arg bigger than 4 words is passed on the stack as
2237 are all subsequent args.
2239 If there are no stack arguments but there are exactly NPARM_REGS
2240 registers, either there were no extra arguments or the caller
2241 allocated an argument block. */
2243 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2245 rtx label
= gen_label_rtx ();
2248 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2249 and we need to allocate a chunk to save the registers (if any
2250 arguments were passed on the stack the caller would allocate the
2251 48 bytes as well). We must allocate all 48 bytes (12*4) because
2252 va_start assumes it. */
2253 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2254 emit_jump_insn (gen_bne (label
));
2255 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2256 stack_pointer_rtx
));
2257 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2258 memory_address (SImode
,
2259 plus_constant (stack_pointer_rtx
,
2263 /* ??? Note that we unnecessarily store one extra register for stdarg
2264 fns. We could optimize this, but it's kept as for now. */
2265 regblock
= gen_rtx (MEM
, BLKmode
,
2266 plus_constant (arg_pointer_rtx
,
2268 move_block_from_reg (first_reg
, regblock
,
2269 NPARM_REGS
- first_reg
,
2270 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2274 /* Calculate the final size of the reg parm stack space for the current
2275 function, based on how many bytes would be allocated on the stack. */
2278 i960_final_reg_parm_stack_space (const_size
, var_size
)
2282 if (var_size
|| const_size
> 48)
2288 /* Calculate the size of the reg parm stack space. This is a bit complicated
2292 i960_reg_parm_stack_space (fndecl
)
2295 /* In this case, we are called from emit_library_call, and we don't need
2296 to pretend we have more space for parameters than what's apparent. */
2300 /* In this case, we are called from locate_and_pad_parms when we're
2301 not IN_REGS, so we have an arg block. */
2302 if (fndecl
!= current_function_decl
)
2305 /* Otherwise, we have an arg block if the current function has more than
2306 48 bytes of parameters. */
2307 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2313 /* Return the register class of a scratch register needed to copy IN into
2314 or out of a register in CLASS in MODE. If it can be done directly,
2315 NO_REGS is returned. */
2318 secondary_reload_class (class, mode
, in
)
2319 enum reg_class
class;
2320 enum machine_mode mode
;
2325 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2326 regno
= true_regnum (in
);
2328 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2329 LOCAL_OR_GLOBAL_REGS into anything. */
2330 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2331 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2334 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2335 if (class == FP_REGS
2336 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2337 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2340 return LOCAL_OR_GLOBAL_REGS
;
2343 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2344 function unit it executed on. */
2346 /* ??? This would make more sense as an attribute. */
2349 i960_scan_opcode (p
)
2361 /* Ret is not actually of type REG, but it won't matter, because no
2362 insn will ever follow it. */
2365 i960_last_insn_type
= I_TYPE_REG
;
2369 if (p
[1] == 'x' || p
[3] == 'x')
2370 i960_last_insn_type
= I_TYPE_MEM
;
2371 i960_last_insn_type
= I_TYPE_CTRL
;
2376 i960_last_insn_type
= I_TYPE_CTRL
;
2383 i960_last_insn_type
= I_TYPE_MEM
;
2385 i960_last_insn_type
= I_TYPE_CTRL
;
2387 else if (p
[1] == 'm')
2390 i960_last_insn_type
= I_TYPE_REG
;
2391 else if (p
[4] == 'b' || p
[4] == 'j')
2392 i960_last_insn_type
= I_TYPE_CTRL
;
2394 i960_last_insn_type
= I_TYPE_REG
;
2397 i960_last_insn_type
= I_TYPE_REG
;
2401 i960_last_insn_type
= I_TYPE_MEM
;
2406 i960_last_insn_type
= I_TYPE_MEM
;
2408 i960_last_insn_type
= I_TYPE_REG
;