1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. Also, it needs to be rewritten to accept
91 a stream instead of a string for GCC 2. */
100 if ((i
= sscanf (str
, " align %d", &align
)) == 1)
103 case 0: /* Return to last alignment. */
104 align
= i960_last_maxbitalignment
/ 8;
106 case 16: /* Byte alignments. */
111 i960_last_maxbitalignment
= i960_maxbitalignment
;
112 i960_maxbitalignment
= align
* 8;
115 default: /* Unknown, silently ignore. */
119 /* NOTE: ic960 R3.0 pragma align definition:
121 #pragma align [(size)] | (identifier=size[,...])
122 #pragma noalign [(identifier)[,...]]
124 (all parens are optional)
126 - size is [1,2,4,8,16]
127 - noalign means size==1
128 - applies only to component elements of a struct (and union?)
129 - identifier applies to structure tag (only)
130 - missing identifier means next struct
132 - alignment rules for bitfields need more investigation */
134 /* Should be pragma 'far' or equivalent for callx/balx here. */
138 /* Initialize variables before compiling any files. */
143 if (TARGET_IC_COMPAT2_0
)
145 i960_maxbitalignment
= 8;
146 i960_last_maxbitalignment
= 128;
150 i960_maxbitalignment
= 128;
151 i960_last_maxbitalignment
= 8;
155 /* Return true if OP can be used as the source of an fp move insn. */
158 fpmove_src_operand (op
, mode
)
160 enum machine_mode mode
;
162 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
166 /* Return true if OP is a register or zero. */
169 reg_or_zero_operand (op
, mode
)
171 enum machine_mode mode
;
173 return register_operand (op
, mode
) || op
== const0_rtx
;
177 /* Return truth value of whether OP can be used as an operands in a three
178 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
181 arith_operand (op
, mode
)
183 enum machine_mode mode
;
185 return (register_operand (op
, mode
) || literal (op
, mode
));
188 /* Return true if OP is a register or a valid floating point literal. */
191 fp_arith_operand (op
, mode
)
193 enum machine_mode mode
;
195 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
198 /* Return true is OP is a register or a valid signed integer literal. */
201 signed_arith_operand (op
, mode
)
203 enum machine_mode mode
;
205 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
208 /* Return truth value of whether OP is a integer which fits the
209 range constraining immediate operands in three-address insns. */
214 enum machine_mode mode
;
216 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
219 /* Return true if OP is a float constant of 1. */
222 fp_literal_one (op
, mode
)
224 enum machine_mode mode
;
226 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
227 && (op
== CONST1_RTX (mode
)));
230 /* Return true if OP is a float constant of 0. */
233 fp_literal_zero (op
, mode
)
235 enum machine_mode mode
;
237 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
238 && (op
== CONST0_RTX (mode
)));
241 /* Return true if OP is a valid floating point literal. */
246 enum machine_mode mode
;
248 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
251 /* Return true if OP is a valid signed immediate constant. */
254 signed_literal(op
, mode
)
256 enum machine_mode mode
;
258 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
261 /* Return truth value of statement that OP is a symbolic memory
262 operand of mode MODE. */
265 symbolic_memory_operand (op
, mode
)
267 enum machine_mode mode
;
269 if (GET_CODE (op
) == SUBREG
)
270 op
= SUBREG_REG (op
);
271 if (GET_CODE (op
) != MEM
)
274 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
275 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
278 /* Return truth value of whether OP is EQ or NE. */
283 enum machine_mode mode
;
285 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
288 /* OP is an integer register or a constant. */
291 arith32_operand (op
, mode
)
293 enum machine_mode mode
;
295 if (register_operand (op
, mode
))
297 return (CONSTANT_P (op
));
300 /* Return true if OP is an integer constant which is a power of 2. */
303 power2_operand (op
,mode
)
305 enum machine_mode mode
;
307 if (GET_CODE (op
) != CONST_INT
)
310 return exact_log2 (INTVAL (op
)) >= 0;
313 /* Return true if OP is an integer constant which is the complement of a
317 cmplpower2_operand (op
, mode
)
319 enum machine_mode mode
;
321 if (GET_CODE (op
) != CONST_INT
)
324 return exact_log2 (~ INTVAL (op
)) >= 0;
327 /* If VAL has only one bit set, return the index of that bit. Otherwise
336 for (i
= 0; val
!= 0; i
++, val
>>= 1)
348 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
349 The return value indicates how many consecutive non-zero bits exist
350 if this is a mask. This is the same as the next function, except that
351 it does not indicate what the start and stop bit positions are. */
357 register int start
, end
, i
;
360 for (i
= 0; val
!= 0; val
>>= 1, i
++)
370 /* Still looking for the first bit. */
374 /* We've seen the start of a bit sequence, and now a zero. There
375 must be more one bits, otherwise we would have exited the loop.
376 Therefore, it is not a mask. */
381 /* The bit string has ones from START to END bit positions only. */
382 return end
- start
+ 1;
385 /* If VAL is a mask, then return nonzero, with S set to the starting bit
386 position and E set to the ending bit position of the mask. The return
387 value indicates how many consecutive bits exist in the mask. This is
388 the same as the previous function, except that it also indicates the
389 start and end bit positions of the mask. */
396 register int start
, end
, i
;
400 for (i
= 0; val
!= 0; val
>>= 1, i
++)
411 /* Still looking for the first bit. */
415 /* We've seen the start of a bit sequence, and now a zero. There
416 must be more one bits, otherwise we would have exited the loop.
417 Therefor, it is not a mask. */
426 /* The bit string has ones from START to END bit positions only. */
429 return ((start
< 0) ? 0 : end
- start
+ 1);
432 /* Return the machine mode to use for a comparison. */
435 select_cc_mode (op
, x
)
439 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
444 /* X and Y are two things to compare using CODE. Emit the compare insn and
445 return the rtx for register 36 in the proper mode. */
448 gen_compare_reg (code
, x
, y
)
453 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
454 enum machine_mode mode
455 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
459 if (! arith_operand (x
, mode
))
460 x
= force_reg (SImode
, x
);
461 if (! arith_operand (y
, mode
))
462 y
= force_reg (SImode
, y
);
465 cc_reg
= gen_rtx (REG
, ccmode
, 36);
466 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
467 gen_rtx (COMPARE
, ccmode
, x
, y
)));
472 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
473 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
474 are 4. Indexed addresses are cost 6. */
476 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
479 i960_address_cost (x
)
483 /* Handled before calling here. */
484 if (GET_CODE (x
) == REG
)
487 if (GET_CODE (x
) == PLUS
)
489 rtx base
= XEXP (x
, 0);
490 rtx offset
= XEXP (x
, 1);
492 if (GET_CODE (base
) == SUBREG
)
493 base
= SUBREG_REG (base
);
494 if (GET_CODE (offset
) == SUBREG
)
495 offset
= SUBREG_REG (offset
);
497 if (GET_CODE (base
) == REG
)
499 if (GET_CODE (offset
) == REG
)
501 if (GET_CODE (offset
) == CONST_INT
)
503 if ((unsigned)INTVAL (offset
) < 2047)
507 if (CONSTANT_P (offset
))
510 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
513 /* This is an invalid address. The return value doesn't matter, but
514 for convenience we make this more expensive than anything else. */
517 if (GET_CODE (x
) == MULT
)
520 /* Symbol_refs and other unrecognized addresses are cost 4. */
524 /* Emit insns to move operands[1] into operands[0].
526 Return 1 if we have written out everything that needs to be done to
527 do the move. Otherwise, return 0 and the caller will emit the move
531 emit_move_sequence (operands
, mode
)
533 enum machine_mode mode
;
535 register rtx operand0
= operands
[0];
536 register rtx operand1
= operands
[1];
538 /* We can only store registers to memory. */
540 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
541 operands
[1] = force_reg (mode
, operand1
);
546 /* Emit insns to load a constant. Uses several strategies to try to use
547 as few insns as possible. */
550 i960_output_ldconst (dst
, src
)
551 register rtx dst
, src
;
554 register unsigned rsrc2
;
555 enum machine_mode mode
= GET_MODE (dst
);
557 union { long l
[2]; double d
; } x
;
559 operands
[0] = operands
[2] = dst
;
560 operands
[1] = operands
[3] = src
;
562 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
563 must be a ldconst insn. */
565 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
567 output_asm_insn ("ldconst %1,%0", operands
);
570 else if (mode
== DFmode
)
574 if (fp_literal_zero (src
, VOIDmode
))
577 return "movrl %1,%0";
582 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
583 split_double (src
, &first
, &second
);
585 output_asm_insn ("# ldconst %1,%0",operands
);
587 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
589 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
591 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
592 operands
[1] = second
;
593 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
597 if (fp_literal_one (src
, VOIDmode
))
598 return "movrl 0f1.0,%0";
599 fatal ("inline double constants not supported on this host");
602 else if (mode
== TImode
)
604 /* ??? This is currently not handled at all. */
607 /* Note: lowest order word goes in lowest numbered reg. */
608 rsrc1
= INTVAL (src
);
609 if (rsrc1
>= 0 && rsrc1
< 32)
612 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
613 /* Go pick up the low-order word. */
615 else if (mode
== DImode
)
617 rtx upperhalf
, lowerhalf
, xoperands
[2];
620 if (GET_CODE (src
) == CONST_DOUBLE
)
622 upperhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_HIGH (src
));
623 lowerhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_LOW (src
));
625 else if (GET_CODE (src
) == CONST_INT
)
628 upperhalf
= INTVAL (src
) < 0 ? constm1_rtx
: const0_rtx
;
633 /* Note: lowest order word goes in lowest numbered reg. */
634 /* Numbers from 0 to 31 can be handled with a single insn. */
635 rsrc1
= INTVAL (lowerhalf
);
636 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
639 /* Output the upper half with a recursive call. */
640 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
641 xoperands
[1] = upperhalf
;
642 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
644 /* The lower word is emitted as normally. */
646 else if (mode
== SFmode
)
648 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
652 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
653 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
655 output_asm_insn ("# ldconst %1,%0",operands
);
656 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
657 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
658 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
661 if (fp_literal_zero (src
, VOIDmode
))
662 return "movr 0f0.0,%0";
663 if (fp_literal_one (src
, VOIDmode
))
664 return "movr 0f1.0,%0";
665 fatal ("inline float constants not supported on this host");
671 rsrc1
= INTVAL (src
);
677 else if (mode
== HImode
)
686 /* ldconst 0..31,X -> mov 0..31,X */
689 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
694 /* ldconst 32..63,X -> add 31,nn,X */
697 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
699 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
700 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
706 /* ldconst -1..-31 -> sub 0,0..31,X */
709 /* return 'sub -(%1),0,%0' */
710 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
711 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
715 /* ldconst -32 -> not 31,X */
718 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
719 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
724 /* If const is a single bit. */
725 if (bitpos (rsrc1
) >= 0)
727 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
728 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
732 /* If const is a bit string of less than 6 bits (1..31 shifted). */
737 if (bitstr (rsrc1
, &s
, &e
) < 6)
739 rsrc2
= ((unsigned int) rsrc1
) >> s
;
740 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
741 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
742 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
747 /* Unimplemented cases:
748 const is in range 0..31 but rotated around end of word:
749 ror 31,3,g0 -> ldconst 0xe0000003,g0
751 and any 2 instruction cases that might be worthwhile */
753 output_asm_insn ("ldconst %1,%0", operands
);
757 /* Determine if there is an opportunity for a bypass optimization.
758 Bypass succeeds on the 960K* if the destination of the previous
759 instruction is the second operand of the current instruction.
760 Bypass always succeeds on the C*.
762 Return 1 if the pattern should interchange the operands.
764 CMPBR_FLAG is true if this is for a compare-and-branch insn.
765 OP1 and OP2 are the two source operands of a 3 operand insn. */
768 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
769 register rtx insn
, op1
, op2
;
772 register rtx prev_insn
, prev_dest
;
777 /* Can't do this if op1 isn't a register. */
781 /* Can't do this for a compare-and-branch if both ops aren't regs. */
782 if (cmpbr_flag
&& ! REG_P (op2
))
785 prev_insn
= prev_real_insn (insn
);
787 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
788 && GET_CODE (PATTERN (prev_insn
)) == SET
)
790 prev_dest
= SET_DEST (PATTERN (prev_insn
));
791 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
792 || (GET_CODE (prev_dest
) == SUBREG
793 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
794 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
800 /* Output the code which declares the function name. This also handles
801 leaf routines, which have special requirements, and initializes some
805 i960_function_name_declare (file
, name
, fndecl
)
814 /* Increment global return label. */
818 /* Compute whether tail calls and leaf routine optimizations can be performed
819 for this function. */
831 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
832 argblock, because argblock uses g14 implicitly. */
834 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
840 /* See if caller passes in an address to return value. */
842 if (aggregate_value_p (DECL_RESULT (fndecl
)))
848 /* Can not use tail calls or make this a leaf routine if there is a non
851 if (get_frame_size () != 0)
854 /* I don't understand this condition, and do not think that it is correct.
855 Apparently this is just checking whether the frame pointer is used, and
856 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
859 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
860 if (GET_CODE (insn
) == INSN
861 && reg_mentioned_p (frame_pointer_rtx
, insn
))
867 /* Check for CALL insns. Can not be a leaf routine if there are any. */
870 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
871 if (GET_CODE (insn
) == CALL_INSN
)
877 /* Can not be a leaf routine if any non-call clobbered registers are
878 used in this function. */
881 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
882 if (regs_ever_live
[i
]
883 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
885 /* Global registers. */
886 if (i
< 16 && i
> 7 && i
!= 13)
888 /* Local registers. */
893 /* Now choose a leaf return register, if we can find one, and if it is
894 OK for this to be a leaf routine. */
896 i960_leaf_ret_reg
= -1;
898 if (optimize
&& leaf_proc_ok
)
900 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
901 if (regs_ever_live
[i
] == 0)
903 i960_leaf_ret_reg
= i
;
904 regs_ever_live
[i
] = 1;
909 /* Do this after choosing the leaf return register, so it will be listed
910 if one was chosen. */
912 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
913 fprintf (file
, "\t# Registers used: ");
915 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
917 if (regs_ever_live
[i
])
919 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
921 if (i
> 15 && j
== 0)
923 fprintf (file
,"\n\t#\t\t ");
929 fprintf (file
, "\n");
931 if (i960_leaf_ret_reg
>= 0)
933 /* Make it a leaf procedure. */
935 if (TREE_PUBLIC (fndecl
))
936 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
938 fprintf (file
, "\t.leafproc\t");
939 assemble_name (file
, name
);
940 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
941 ASM_OUTPUT_LABEL (file
, name
);
942 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
943 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
944 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
948 fprintf (file
, "\tlda 0,g14\n");
949 i960_last_insn_type
= I_TYPE_MEM
;
953 fprintf (file
, "\tmov 0,g14\n");
954 i960_last_insn_type
= I_TYPE_REG
;
959 ASM_OUTPUT_LABEL (file
, name
);
960 i960_last_insn_type
= I_TYPE_CTRL
;
964 /* Compute and return the frame size. */
967 compute_frame_size (size
)
971 int outgoing_args_size
= current_function_outgoing_args_size
;
973 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
974 as size is concerned. */
975 actual_fsize
= (size
+ 15) & -16;
976 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
981 /* Output code for the function prologue. */
984 i960_function_prologue (file
, size
)
988 register int i
, j
, nr
;
991 int actual_fsize
, offset
;
993 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
995 int regs
[FIRST_PSEUDO_REGISTER
];
997 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
998 if (regs_ever_live
[i
]
999 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1002 /* Count global registers that need saving. */
1009 epilogue_string
[0] = '\0';
1011 if (profile_flag
|| profile_block_flag
)
1013 /* When profiling, we may use registers 20 to 27 to save arguments, so
1014 they can't be used here for saving globals. J is the number of
1015 argument registers the mcount call will save. */
1016 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1019 for (i
= 20; i
<= j
+ 20; i
++)
1023 /* First look for local registers to save globals in. */
1024 for (i
= 0; i
< 16; i
++)
1029 /* Start at r4, not r3. */
1030 for (j
= 20; j
< 32; j
++)
1037 regs_ever_live
[j
] = 1;
1039 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1040 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1045 regs_ever_live
[j
+1] = 1;
1047 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1048 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1053 regs_ever_live
[j
+2] = 1;
1055 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1060 regs_ever_live
[j
+3] = 1;
1063 fprintf (file
, "\tmov%s %s,%s\n",
1066 (nr
== 2) ? "l" : ""),
1067 reg_names
[i
], reg_names
[j
]);
1068 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1071 (nr
== 2) ? "l" : ""),
1072 reg_names
[j
], reg_names
[i
]);
1073 strcat (epilogue_string
, tmpstr
);
1081 /* N_iregs is now the number of global registers that haven't been saved
1084 rsize
= (n_iregs
* 4);
1085 actual_fsize
= compute_frame_size (size
) + rsize
;
1087 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1088 size up to the nearest multiple of 16. I don't know whether this is
1089 necessary, or even desirable.
1091 The frame pointer must be aligned, but the call instruction takes care of
1092 that. If we leave the stack pointer unaligned, we may save a little on
1093 dynamic stack allocation. And we don't lose, at least according to the
1095 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1098 /* Allocate space for register save and locals. */
1099 if (actual_fsize
> 0)
1101 if (actual_fsize
< 32)
1102 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1104 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1107 /* Take hardware register save area created by the call instruction
1108 into account, but store them before the argument block area. */
1109 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1110 /* Save registers on stack if needed. */
1111 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1118 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1121 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1125 if (nr
== 3 && regs
[i
+3] == -1)
1128 fprintf (file
,"\tst%s %s,%d(fp)\n",
1131 (nr
== 2) ? "l" : ""),
1132 reg_names
[i
], offset
);
1133 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1136 (nr
== 2) ? "l" : ""),
1137 offset
, reg_names
[i
]);
1138 strcat (epilogue_string
, tmpstr
);
1144 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1147 fprintf (file
, "\t#Prologue stats:\n");
1148 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1151 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1153 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1155 fprintf (file
, "\t#End Prologue#\n");
1158 /* Output code for the function profiler. */
1161 output_function_profiler (file
, labelno
)
1165 /* The last used parameter register. */
1167 int i
, j
, increment
;
1168 int varargs_stdarg_function
1169 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1171 /* Figure out the last used parameter register. The proper thing to do
1172 is to walk incoming args of the function. A function might have live
1173 parameter registers even if it has no incoming args. Note that we
1174 don't have to save parameter registers g8 to g11 because they are
1177 /* See also output_function_prologue, which tries to use local registers
1178 for preserved call-saved global registers. */
1180 for (last_parm_reg
= 7;
1181 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1185 /* Save parameter registers in regs r4 (20) to r11 (27). */
1187 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1189 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1191 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1193 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1198 fprintf (file
, "\tmov%s g%d,r%d\n",
1199 (increment
== 4 ? "q" : increment
== 3 ? "t"
1200 : increment
== 2 ? "l": ""), i
, j
);
1203 /* If this function uses the arg pointer, then save it in r3 and then
1206 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1207 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1209 /* Load location address into g0 and call mcount. */
1211 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1213 /* If this function uses the arg pointer, restore it. */
1215 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1216 fprintf (file
, "\tmov r3,g14\n");
1218 /* Restore parameter registers. */
1220 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1222 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1224 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1226 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1231 fprintf (file
, "\tmov%s r%d,g%d\n",
1232 (increment
== 4 ? "q" : increment
== 3 ? "t"
1233 : increment
== 2 ? "l": ""), j
, i
);
1237 /* Output code for the function epilogue. */
1240 i960_function_epilogue (file
, size
)
1244 if (i960_leaf_ret_reg
>= 0)
1246 fprintf (file
, "LR%d: ret\n", ret_label
);
1250 if (*epilogue_string
== 0)
1254 /* Emit a return insn, but only if control can fall through to here. */
1256 tmp
= get_last_insn ();
1259 if (GET_CODE (tmp
) == BARRIER
)
1261 if (GET_CODE (tmp
) == CODE_LABEL
)
1263 if (GET_CODE (tmp
) == JUMP_INSN
)
1265 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1269 if (GET_CODE (tmp
) == NOTE
)
1271 tmp
= PREV_INSN (tmp
);
1276 fprintf (file
, "LR%d: ret\n", ret_label
);
1280 fprintf (file
, "LR%d:\n", ret_label
);
1282 fprintf (file
, "\t#EPILOGUE#\n");
1284 /* Output the string created by the prologue which will restore all
1285 registers saved by the prologue. */
1287 if (epilogue_string
[0] != '\0')
1288 fprintf (file
, "%s", epilogue_string
);
1290 /* Must clear g14 on return. */
1292 if (current_function_args_size
!= 0
1293 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1294 fprintf (file
, "\tmov 0,g14\n");
1296 fprintf (file
, "\tret\n");
1297 fprintf (file
, "\t#End Epilogue#\n");
1300 /* Output code for a call insn. */
1303 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1304 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1306 int argsize
= INTVAL (argsize_rtx
);
1307 rtx nexti
= next_real_insn (insn
);
1309 int varargs_stdarg_function
1310 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1312 operands
[0] = target
;
1313 operands
[1] = arg_pointer
;
1315 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1316 output_asm_insn ("mov g14,r3", operands
);
1319 output_asm_insn ("lda %a1,g14", operands
);
1320 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1321 output_asm_insn ("mov 0,g14", operands
);
1323 /* The code used to assume that calls to SYMBOL_REFs could not be more
1324 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1325 feature is now implemented by relaxing in the GNU linker. It can convert
1326 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1328 /* Nexti could be zero if the called routine is volatile. */
1329 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1330 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1332 /* Delete following return insn. */
1333 if (nexti
&& no_labels_between_p (insn
, nexti
))
1334 delete_insn (nexti
);
1335 output_asm_insn ("bx %0", operands
);
1336 return "# notreached";
1339 output_asm_insn ("callx %0", operands
);
1341 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1342 output_asm_insn ("mov r3,g14", operands
);
1347 /* Output code for a return insn. */
1350 i960_output_ret_insn (insn
)
1353 static char lbuf
[20];
1355 if (*epilogue_string
!= 0)
1357 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1360 sprintf (lbuf
, "b LR%d", ret_label
);
1364 if (current_function_args_size
!= 0
1365 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1366 output_asm_insn ("mov 0,g14", 0);
1368 if (i960_leaf_ret_reg
>= 0)
1370 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1377 /* Return a character string representing the branch prediction
1378 opcode to be tacked on an instruction. This must at least
1379 return a null string. */
1382 i960_br_predict_opcode (lab_ref
, insn
)
1385 if (TARGET_BRANCH_PREDICT
)
1387 unsigned long label_uid
;
1389 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1390 label_uid
= INSN_UID (lab_ref
);
1391 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1392 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1396 /* If not optimizing, then the insn_addresses array will not be
1397 valid. In this case, always return ".t" since most branches
1398 are taken. If optimizing, return .t for backward branches
1399 and .f for forward branches. */
1401 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1410 /* Print the operand represented by rtx X formatted by code CODE. */
1413 i960_print_operand (file
, x
, code
)
1418 enum rtx_code rtxcode
= GET_CODE (x
);
1425 /* Second reg of a double. */
1426 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1430 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1438 else if (rtxcode
== MEM
)
1440 output_address (XEXP (x
, 0));
1443 else if (rtxcode
== CONST_INT
)
1445 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1446 fprintf (file
, "0x%x", INTVAL (x
));
1448 fprintf (file
, "%d", INTVAL (x
));
1451 else if (rtxcode
== CONST_DOUBLE
)
1455 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1457 fprintf (file
, "0f0.0");
1460 else if (x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))
1462 fprintf (file
, "0f1.0");
1466 /* This better be a comment. */
1467 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1468 fprintf (file
, "%#g", d
);
1475 /* Branch or jump, depending on assembler. */
1476 if (TARGET_ASM_COMPAT
)
1483 /* Sign of condition. */
1484 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1485 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1487 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1488 || (rtxcode
== GE
) || (rtxcode
== LE
))
1495 /* Inverted condition. */
1496 rtxcode
= reverse_condition (rtxcode
);
1500 /* Inverted condition w/ reversed operands. */
1501 rtxcode
= reverse_condition (rtxcode
);
1505 /* Reversed operand condition. */
1506 rtxcode
= swap_condition (rtxcode
);
1510 /* Normal condition. */
1512 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1513 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1514 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1515 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1516 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1517 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1518 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1519 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1520 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1521 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1526 output_addr_const (file
, x
);
1536 /* Print a memory address as an operand to reference that memory location.
1538 This is exactly the same as legitimate_address_p, except that it the prints
1539 addresses instead of recognizing them. */
1542 i960_print_operand_addr (file
, addr
)
1554 if (GET_CODE (addr
) == REG
)
1556 else if (CONSTANT_P (addr
))
1558 else if (GET_CODE (addr
) == PLUS
)
1562 op0
= XEXP (addr
, 0);
1563 op1
= XEXP (addr
, 1);
1565 if (GET_CODE (op0
) == REG
)
1568 if (GET_CODE (op1
) == REG
)
1570 else if (CONSTANT_P (op1
))
1575 else if (GET_CODE (op0
) == PLUS
)
1577 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1579 ireg
= XEXP (XEXP (op0
, 0), 0);
1580 scale
= XEXP (XEXP (op0
, 0), 1);
1581 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1583 breg
= XEXP (op0
, 1);
1589 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1591 breg
= XEXP (op0
, 0);
1592 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1594 ireg
= XEXP (op0
, 1);
1603 else if (GET_CODE (op0
) == MULT
)
1605 ireg
= XEXP (op0
, 0);
1606 scale
= XEXP (op0
, 1);
1607 if (GET_CODE (op1
) == REG
)
1609 else if (CONSTANT_P (op1
))
1617 else if (GET_CODE (addr
) == MULT
)
1619 ireg
= XEXP (addr
, 0);
1620 scale
= XEXP (addr
, 1);
1626 output_addr_const (file
, offset
);
1628 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1630 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1633 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1634 that is a valid memory address for an instruction.
1635 The MODE argument is the machine mode for the MEM expression
1636 that wants to use this address.
1638 On 80960, legitimate addresses are:
1640 disp (12 or 32 bit) ld foo,r0
1641 base + index ld (g0)[g1*1],r0
1642 base + displ ld 0xf00(g0),r0
1643 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1644 index*scale + base ld (g0)[g1*4],r0
1645 index*scale + displ ld 0xf00[g1*4],r0
1646 index*scale ld [g1*4],r0
1647 index + base + displ ld 0xf00(g0)[g1*1],r0
1649 In each case, scale can be 1, 2, 4, 8, or 16. */
1651 /* This is exactly the same as i960_print_operand_addr, except that
1652 it recognizes addresses instead of printing them.
1654 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1655 convert common non-canonical forms to canonical form so that they will
1658 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1659 where a register is valid. */
1661 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1662 ((GET_CODE (X) == REG \
1663 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1664 || (GET_CODE (X) == SUBREG \
1665 && GET_CODE (SUBREG_REG (X)) == REG \
1666 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1667 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1669 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1670 ((GET_CODE (X) == REG \
1671 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1672 || (GET_CODE (X) == SUBREG \
1673 && GET_CODE (SUBREG_REG (X)) == REG \
1674 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1675 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1678 legitimate_address_p (mode
, addr
, strict
)
1679 enum machine_mode mode
;
1683 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1685 else if (CONSTANT_P (addr
))
1687 else if (GET_CODE (addr
) == PLUS
)
1691 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1694 op0
= XEXP (addr
, 0);
1695 op1
= XEXP (addr
, 1);
1697 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1699 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1701 else if (CONSTANT_P (op1
))
1706 else if (GET_CODE (op0
) == PLUS
)
1708 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1710 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1711 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1714 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1715 && CONSTANT_P (op1
))
1720 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1722 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1723 && CONSTANT_P (op1
))
1731 else if (GET_CODE (op0
) == MULT
)
1733 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1734 && SCALE_TERM_P (XEXP (op0
, 1))))
1737 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1739 else if (CONSTANT_P (op1
))
1747 else if (GET_CODE (addr
) == MULT
)
1749 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1752 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1753 && SCALE_TERM_P (XEXP (addr
, 1)));
1759 /* Try machine-dependent ways of modifying an illegitimate address
1760 to be legitimate. If we find one, return the new, valid address.
1761 This macro is used in only one place: `memory_address' in explow.c.
1763 This converts some non-canonical addresses to canonical form so they
1764 can be recognized. */
1767 legitimize_address (x
, oldx
, mode
)
1770 enum machine_mode mode
;
1772 if (GET_CODE (x
) == SYMBOL_REF
)
1775 x
= copy_to_reg (x
);
1778 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1781 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1782 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1783 created by virtual register instantiation, register elimination, and
1784 similar optimizations. */
1785 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1786 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1787 x
= gen_rtx (PLUS
, Pmode
,
1788 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1789 XEXP (XEXP (x
, 1), 1));
1791 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1792 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1793 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1794 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1795 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1796 && CONSTANT_P (XEXP (x
, 1)))
1798 rtx constant
, other
;
1800 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1802 constant
= XEXP (x
, 1);
1803 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1805 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1807 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1808 other
= XEXP (x
, 1);
1814 x
= gen_rtx (PLUS
, Pmode
,
1815 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1816 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1817 plus_constant (other
, INTVAL (constant
)));
1824 /* Return the most stringent alignment that we are willing to consider
1825 objects of size SIZE and known alignment ALIGN as having. */
1828 i960_alignment (size
, align
)
1834 if (! TARGET_STRICT_ALIGN
)
1835 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1837 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1846 /* Modes for condition codes. */
1848 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1850 /* Modes for single-word (and smaller) quantities. */
1853 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1854 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1856 /* Modes for double-word (and smaller) quantities. */
1859 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1861 /* Modes for quad-word quantities. */
1862 #define T_MODES (~C_MODES)
1864 /* Modes for single-float quantities. */
1865 #define SF_MODES ((1 << (int) SFmode))
1867 /* Modes for double-float quantities. */
1868 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1870 /* Modes for quad-float quantities. */
1871 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1873 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1874 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1875 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1876 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1877 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1879 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1882 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1883 advantage of machine specific facts, such as knowing that the frame pointer
1884 is always 16 byte aligned. */
1887 i960_expr_alignment (x
, size
)
1896 switch (GET_CODE(x
))
1901 if ((align
& 0xf) == 0)
1903 else if ((align
& 0x7) == 0)
1905 else if ((align
& 0x3) == 0)
1907 else if ((align
& 0x1) == 0)
1914 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1915 i960_expr_alignment (XEXP (x
, 1), size
));
1919 /* If this is a valid program, objects are guaranteed to be
1920 correctly aligned for whatever size the reference actually is. */
1921 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1925 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1930 align
= i960_expr_alignment (XEXP (x
, 0));
1932 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1934 align
= align
<< INTVAL (XEXP (x
, 1));
1935 align
= MIN (align
, 16);
1940 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1941 i960_expr_alignment (XEXP (x
, 1), size
));
1943 align
= MIN (align
, 16);
1950 /* Return true if it is possible to reference both BASE and OFFSET, which
1951 have alignment at least as great as 4 byte, as if they had alignment valid
1952 for an object of size SIZE. */
1955 i960_improve_align (base
, offset
, size
)
1962 /* We have at least a word reference to the object, so we know it has to
1963 be aligned at least to 4 bytes. */
1965 i
= MIN (i960_expr_alignment (base
, 4),
1966 i960_expr_alignment (offset
, 4));
1970 /* We know the size of the request. If strict align is not enabled, we
1971 can guess that the alignment is OK for the requested size. */
1973 if (! TARGET_STRICT_ALIGN
)
1974 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1980 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1981 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1984 i960_si_ti (base
, offset
)
1988 return i960_improve_align (base
, offset
, 16);
1991 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1992 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1995 i960_si_di (base
, offset
)
1999 return i960_improve_align (base
, offset
, 8);
2002 /* Return raw values of size and alignment (in words) for the data
2003 type being accessed. These values will be rounded by the caller. */
2006 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2007 enum machine_mode mode
;
2014 /* Use formal alignment requirements of type being passed, except make
2015 it at least a word. If we don't have a type, this is a library call,
2016 and the parm has to be of scalar type. In this case, consider its
2017 formal alignment requirement to be its size in words. */
2019 if (mode
== BLKmode
)
2020 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2021 else if (mode
== VOIDmode
)
2023 /* End of parm list. */
2024 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2028 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2032 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2033 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2041 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2042 Any arg that is bigger than 4 words is placed on the stack and all
2043 subsequent arguments are placed on the stack.
2045 Additionally, parameters with an alignment requirement stronger than
2046 a word must be be aligned appropriately. */
2048 /* Update CUM to advance past an argument described by MODE and TYPE. */
2051 i960_function_arg_advance (cum
, mode
, type
, named
)
2052 CUMULATIVE_ARGS
*cum
;
2053 enum machine_mode mode
;
2059 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2061 if (size
> 4 || cum
->ca_nstackparms
!= 0
2062 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2063 || MUST_PASS_IN_STACK (mode
, type
))
2064 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2066 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2069 /* Return the register that the argument described by MODE and TYPE is
2070 passed in, or else return 0 if it is passed on the stack. */
2073 i960_function_arg (cum
, mode
, type
, named
)
2074 CUMULATIVE_ARGS
*cum
;
2075 enum machine_mode mode
;
2082 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2084 if (size
> 4 || cum
->ca_nstackparms
!= 0
2085 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2086 || MUST_PASS_IN_STACK (mode
, type
))
2088 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2093 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2094 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2100 /* Floating-point support. */
2103 i960_output_double (file
, value
)
2107 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
2109 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2111 fprintf (file
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
2112 value_long
[0], value
, value_long
[1]);
2114 if (REAL_VALUE_ISINF (value
))
2116 fprintf (file
, "\t.word 0\n");
2117 fprintf (file
, "\t.word 0x7ff00000 # Infinity\n");
2120 fprintf (file
, "\t.double 0d%.17e\n", (value
));
2125 i960_output_float (file
, value
)
2129 #ifdef REAL_VALUE_TO_TARGET_SINGLE
2131 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2133 fprintf (file
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
2135 if (REAL_VALUE_ISINF (value
))
2136 fprintf (file
, "\t.word 0x7f800000 # Infinity\n");
2138 fprintf (file
, "\t.float 0f%.12e\n", (value
));
2142 /* Return the number of bits that an object of size N bytes is aligned to. */
2145 i960_object_bytes_bitalign (n
)
2149 else if (n
> 4) n
= 64;
2150 else if (n
> 2) n
= 32;
2151 else if (n
> 1) n
= 16;
2157 /* Compute the size of an aggregate type TSIZE. */
2160 i960_round_size (tsize
)
2163 int size
, byte_size
, align
;
2165 if (TREE_CODE (tsize
) != INTEGER_CST
)
2168 size
= TREE_INT_CST_LOW (tsize
);
2169 byte_size
= (size
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2170 align
= i960_object_bytes_bitalign (byte_size
);
2172 /* Handle #pragma align. */
2173 if (align
> i960_maxbitalignment
)
2174 align
= i960_maxbitalignment
;
2177 size
= ((size
/ align
) + 1) * align
;
2179 return size_int (size
);
2182 /* Compute the alignment for an aggregate type TSIZE. */
2185 i960_round_align (align
, tsize
)
2191 if (TREE_CODE (tsize
) != INTEGER_CST
)
2194 byte_size
= (TREE_INT_CST_LOW (tsize
) + BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2195 align
= i960_object_bytes_bitalign (byte_size
);
2199 /* Do any needed setup for a varargs function. For the i960, we must
2200 create a register parameter block if one doesn't exist, and then copy
2201 all register parameters to memory. */
2204 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2205 CUMULATIVE_ARGS
*cum
;
2206 enum machine_mode mode
;
2211 if (cum
->ca_nregparms
< NPARM_REGS
)
2213 int first_reg_offset
= cum
->ca_nregparms
;
2217 rtx label
= gen_label_rtx ();
2220 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2221 and we need to allocate a chunk to save the registers (if any
2222 arguments were passed on the stack the caller would allocate the
2223 48 bytes as well). We must allocate all 48 bytes (12*4) because
2224 arg_pointer_rtx is saved at the front, the anonymous args are
2225 saved at the end. */
2226 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2227 emit_jump_insn (gen_bne (label
));
2228 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2229 stack_pointer_rtx
));
2230 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2231 memory_address (SImode
,
2232 plus_constant (stack_pointer_rtx
,
2236 /* Any anonymous args passed in regs? */
2237 if (first_reg_offset
+ 1 < NPARM_REGS
)
2240 regblock
= gen_rtx (MEM
, BLKmode
,
2241 plus_constant (arg_pointer_rtx
,
2242 (first_reg_offset
+ 1) * 4));
2243 move_block_from_reg (first_reg_offset
+ 1, regblock
,
2244 NPARM_REGS
- first_reg_offset
- 1,
2245 ((NPARM_REGS
- first_reg_offset
- 1)
2252 /* Calculate the final size of the reg parm stack space for the current
2253 function, based on how many bytes would be allocated on the stack. */
2256 i960_final_reg_parm_stack_space (const_size
, var_size
)
2260 if (var_size
|| const_size
> 48)
2266 /* Calculate the size of the reg parm stack space. This is a bit complicated
2270 i960_reg_parm_stack_space (fndecl
)
2273 /* In this case, we are called from emit_library_call, and we don't need
2274 to pretend we have more space for parameters than what's apparent. */
2278 /* In this case, we are called from locate_and_pad_parms when we're
2279 not IN_REGS, so we have an arg block. */
2280 if (fndecl
!= current_function_decl
)
2283 /* Otherwise, we have an arg block if the current function has more than
2284 48 bytes of parameters. */
2285 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2291 /* Return the register class of a scratch register needed to copy IN into
2292 or out of a register in CLASS in MODE. If it can be done directly,
2293 NO_REGS is returned. */
2296 secondary_reload_class (class, mode
, in
)
2297 enum reg_class
class;
2298 enum machine_mode mode
;
2303 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2304 regno
= true_regnum (in
);
2306 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2307 LOCAL_OR_GLOBAL_REGS into anything. */
2308 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2309 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2312 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2313 if (class == FP_REGS
2314 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2315 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2318 return LOCAL_OR_GLOBAL_REGS
;
2321 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2322 function unit it executed on. */
2324 /* ??? This would make more sense as an attribute. */
2327 i960_scan_opcode (p
)
2339 /* Ret is not actually of type REG, but it won't matter, because no
2340 insn will ever follow it. */
2343 i960_last_insn_type
= I_TYPE_REG
;
2347 if (p
[1] == 'x' || p
[3] == 'x')
2348 i960_last_insn_type
= I_TYPE_MEM
;
2349 i960_last_insn_type
= I_TYPE_CTRL
;
2354 i960_last_insn_type
= I_TYPE_CTRL
;
2361 i960_last_insn_type
= I_TYPE_MEM
;
2363 i960_last_insn_type
= I_TYPE_CTRL
;
2365 else if (p
[1] == 'm')
2368 i960_last_insn_type
= I_TYPE_REG
;
2369 else if (p
[4] == 'b' || p
[4] == 'j')
2370 i960_last_insn_type
= I_TYPE_CTRL
;
2372 i960_last_insn_type
= I_TYPE_REG
;
2375 i960_last_insn_type
= I_TYPE_REG
;
2379 i960_last_insn_type
= I_TYPE_MEM
;
2384 i960_last_insn_type
= I_TYPE_MEM
;
2386 i960_last_insn_type
= I_TYPE_REG
;