1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
48 rtx i960_compare_op0
, i960_compare_op1
;
50 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
53 static int i960_maxbitalignment
;
54 static int i960_last_maxbitalignment
;
56 /* Used to implement switching between MEM and ALU insn types, for better
57 C series performance. */
59 enum insn_types i960_last_insn_type
;
61 /* The leaf-procedure return register. Set only if this is a leaf routine. */
63 static int i960_leaf_ret_reg
;
65 /* True if replacing tail calls with jumps is OK. */
67 static int tail_call_ok
;
69 /* A string containing a list of insns to emit in the epilogue so as to
70 restore all registers saved by the prologue. Created by the prologue
71 code as it saves registers away. */
73 char epilogue_string
[1000];
75 /* A unique number (per function) for return labels. */
77 static int ret_label
= 0;
79 /* This is true if FNDECL is either a varargs or a stdarg function.
80 This is used to help identify functions that use an argument block. */
82 #define VARARGS_STDARG_FUNCTION(FNDECL) \
83 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
84 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
85 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. */
93 process_pragma (finput
)
100 while (c
== ' ' || c
== '\t')
104 && getc (finput
) == 'l'
105 && getc (finput
) == 'i'
106 && getc (finput
) == 'g'
107 && getc (finput
) == 'n'
108 && ((c
= getc (finput
)) == ' ' || c
== '\t' || c
== '\n'))
114 while (c
== ' ' || c
== '\t')
118 while (c
>= '0' && c
<= '9')
120 if (s
< buf
+ sizeof buf
- 1)
130 /* Return to last alignment. */
131 align
= i960_last_maxbitalignment
/ 8;
138 i960_last_maxbitalignment
= i960_maxbitalignment
;
139 i960_maxbitalignment
= align
* 8;
143 /* Silently ignore bad values. */
147 /* NOTE: ic960 R3.0 pragma align definition:
149 #pragma align [(size)] | (identifier=size[,...])
150 #pragma noalign [(identifier)[,...]]
152 (all parens are optional)
154 - size is [1,2,4,8,16]
155 - noalign means size==1
156 - applies only to component elements of a struct (and union?)
157 - identifier applies to structure tag (only)
158 - missing identifier means next struct
160 - alignment rules for bitfields need more investigation */
163 /* Should be pragma 'far' or equivalent for callx/balx here. */
168 /* Initialize variables before compiling any files. */
173 if (TARGET_IC_COMPAT2_0
)
175 i960_maxbitalignment
= 8;
176 i960_last_maxbitalignment
= 128;
180 i960_maxbitalignment
= 128;
181 i960_last_maxbitalignment
= 8;
185 /* Return true if OP can be used as the source of an fp move insn. */
188 fpmove_src_operand (op
, mode
)
190 enum machine_mode mode
;
192 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
196 /* Return true if OP is a register or zero. */
199 reg_or_zero_operand (op
, mode
)
201 enum machine_mode mode
;
203 return register_operand (op
, mode
) || op
== const0_rtx
;
207 /* Return truth value of whether OP can be used as an operands in a three
208 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
211 arith_operand (op
, mode
)
213 enum machine_mode mode
;
215 return (register_operand (op
, mode
) || literal (op
, mode
));
218 /* Return true if OP is a register or a valid floating point literal. */
221 fp_arith_operand (op
, mode
)
223 enum machine_mode mode
;
225 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
228 /* Return true is OP is a register or a valid signed integer literal. */
231 signed_arith_operand (op
, mode
)
233 enum machine_mode mode
;
235 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
238 /* Return truth value of whether OP is a integer which fits the
239 range constraining immediate operands in three-address insns. */
244 enum machine_mode mode
;
246 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
249 /* Return true if OP is a float constant of 1. */
252 fp_literal_one (op
, mode
)
254 enum machine_mode mode
;
256 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
259 /* Return true if OP is a float constant of 0. */
262 fp_literal_zero (op
, mode
)
264 enum machine_mode mode
;
266 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
269 /* Return true if OP is a valid floating point literal. */
274 enum machine_mode mode
;
276 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
279 /* Return true if OP is a valid signed immediate constant. */
282 signed_literal(op
, mode
)
284 enum machine_mode mode
;
286 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
289 /* Return truth value of statement that OP is a symbolic memory
290 operand of mode MODE. */
293 symbolic_memory_operand (op
, mode
)
295 enum machine_mode mode
;
297 if (GET_CODE (op
) == SUBREG
)
298 op
= SUBREG_REG (op
);
299 if (GET_CODE (op
) != MEM
)
302 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
303 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
306 /* Return truth value of whether OP is EQ or NE. */
311 enum machine_mode mode
;
313 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
316 /* OP is an integer register or a constant. */
319 arith32_operand (op
, mode
)
321 enum machine_mode mode
;
323 if (register_operand (op
, mode
))
325 return (CONSTANT_P (op
));
328 /* Return true if OP is an integer constant which is a power of 2. */
331 power2_operand (op
,mode
)
333 enum machine_mode mode
;
335 if (GET_CODE (op
) != CONST_INT
)
338 return exact_log2 (INTVAL (op
)) >= 0;
341 /* Return true if OP is an integer constant which is the complement of a
345 cmplpower2_operand (op
, mode
)
347 enum machine_mode mode
;
349 if (GET_CODE (op
) != CONST_INT
)
352 return exact_log2 (~ INTVAL (op
)) >= 0;
355 /* If VAL has only one bit set, return the index of that bit. Otherwise
364 for (i
= 0; val
!= 0; i
++, val
>>= 1)
376 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
377 The return value indicates how many consecutive non-zero bits exist
378 if this is a mask. This is the same as the next function, except that
379 it does not indicate what the start and stop bit positions are. */
385 register int start
, end
, i
;
388 for (i
= 0; val
!= 0; val
>>= 1, i
++)
398 /* Still looking for the first bit. */
402 /* We've seen the start of a bit sequence, and now a zero. There
403 must be more one bits, otherwise we would have exited the loop.
404 Therefore, it is not a mask. */
409 /* The bit string has ones from START to END bit positions only. */
410 return end
- start
+ 1;
413 /* If VAL is a mask, then return nonzero, with S set to the starting bit
414 position and E set to the ending bit position of the mask. The return
415 value indicates how many consecutive bits exist in the mask. This is
416 the same as the previous function, except that it also indicates the
417 start and end bit positions of the mask. */
424 register int start
, end
, i
;
428 for (i
= 0; val
!= 0; val
>>= 1, i
++)
439 /* Still looking for the first bit. */
443 /* We've seen the start of a bit sequence, and now a zero. There
444 must be more one bits, otherwise we would have exited the loop.
445 Therefor, it is not a mask. */
454 /* The bit string has ones from START to END bit positions only. */
457 return ((start
< 0) ? 0 : end
- start
+ 1);
460 /* Return the machine mode to use for a comparison. */
463 select_cc_mode (op
, x
)
467 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
472 /* X and Y are two things to compare using CODE. Emit the compare insn and
473 return the rtx for register 36 in the proper mode. */
476 gen_compare_reg (code
, x
, y
)
481 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
482 enum machine_mode mode
483 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
487 if (! arith_operand (x
, mode
))
488 x
= force_reg (SImode
, x
);
489 if (! arith_operand (y
, mode
))
490 y
= force_reg (SImode
, y
);
493 cc_reg
= gen_rtx (REG
, ccmode
, 36);
494 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
495 gen_rtx (COMPARE
, ccmode
, x
, y
)));
500 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
501 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
502 are 4. Indexed addresses are cost 6. */
504 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
507 i960_address_cost (x
)
511 /* Handled before calling here. */
512 if (GET_CODE (x
) == REG
)
515 if (GET_CODE (x
) == PLUS
)
517 rtx base
= XEXP (x
, 0);
518 rtx offset
= XEXP (x
, 1);
520 if (GET_CODE (base
) == SUBREG
)
521 base
= SUBREG_REG (base
);
522 if (GET_CODE (offset
) == SUBREG
)
523 offset
= SUBREG_REG (offset
);
525 if (GET_CODE (base
) == REG
)
527 if (GET_CODE (offset
) == REG
)
529 if (GET_CODE (offset
) == CONST_INT
)
531 if ((unsigned)INTVAL (offset
) < 2047)
535 if (CONSTANT_P (offset
))
538 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
541 /* This is an invalid address. The return value doesn't matter, but
542 for convenience we make this more expensive than anything else. */
545 if (GET_CODE (x
) == MULT
)
548 /* Symbol_refs and other unrecognized addresses are cost 4. */
552 /* Emit insns to move operands[1] into operands[0].
554 Return 1 if we have written out everything that needs to be done to
555 do the move. Otherwise, return 0 and the caller will emit the move
559 emit_move_sequence (operands
, mode
)
561 enum machine_mode mode
;
563 register rtx operand0
= operands
[0];
564 register rtx operand1
= operands
[1];
566 /* We can only store registers to memory. */
568 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
569 operands
[1] = force_reg (mode
, operand1
);
574 /* Emit insns to load a constant to non-floating point registers.
575 Uses several strategies to try to use as few insns as possible. */
578 i960_output_ldconst (dst
, src
)
579 register rtx dst
, src
;
582 register unsigned rsrc2
;
583 enum machine_mode mode
= GET_MODE (dst
);
586 operands
[0] = operands
[2] = dst
;
587 operands
[1] = operands
[3] = src
;
589 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
590 must be a ldconst insn. */
592 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
594 output_asm_insn ("ldconst %1,%0", operands
);
597 else if (mode
== XFmode
)
603 if (fp_literal_zero (src
, XFmode
))
606 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
607 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
609 output_asm_insn ("# ldconst %1,%0",operands
);
611 for (i
= 0; i
< 3; i
++)
613 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
614 operands
[1] = GEN_INT (value_long
[i
]);
615 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
621 else if (mode
== DFmode
)
625 if (fp_literal_zero (src
, DFmode
))
628 split_double (src
, &first
, &second
);
630 output_asm_insn ("# ldconst %1,%0",operands
);
632 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
634 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
636 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
637 operands
[1] = second
;
638 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
642 else if (mode
== SFmode
)
647 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
648 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
650 output_asm_insn ("# ldconst %1,%0",operands
);
651 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
652 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
653 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
657 else if (mode
== TImode
)
659 /* ??? This is currently not handled at all. */
662 /* Note: lowest order word goes in lowest numbered reg. */
663 rsrc1
= INTVAL (src
);
664 if (rsrc1
>= 0 && rsrc1
< 32)
667 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
668 /* Go pick up the low-order word. */
670 else if (mode
== DImode
)
672 rtx upperhalf
, lowerhalf
, xoperands
[2];
674 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
675 split_double (src
, &lowerhalf
, &upperhalf
);
680 /* Note: lowest order word goes in lowest numbered reg. */
681 /* Numbers from 0 to 31 can be handled with a single insn. */
682 rsrc1
= INTVAL (lowerhalf
);
683 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
686 /* Output the upper half with a recursive call. */
687 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
688 xoperands
[1] = upperhalf
;
689 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
691 /* The lower word is emitted as normally. */
695 rsrc1
= INTVAL (src
);
701 else if (mode
== HImode
)
710 /* ldconst 0..31,X -> mov 0..31,X */
713 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
718 /* ldconst 32..63,X -> add 31,nn,X */
721 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
723 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
724 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
730 /* ldconst -1..-31 -> sub 0,0..31,X */
733 /* return 'sub -(%1),0,%0' */
734 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
735 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
739 /* ldconst -32 -> not 31,X */
742 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
743 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
748 /* If const is a single bit. */
749 if (bitpos (rsrc1
) >= 0)
751 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
752 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
756 /* If const is a bit string of less than 6 bits (1..31 shifted). */
761 if (bitstr (rsrc1
, &s
, &e
) < 6)
763 rsrc2
= ((unsigned int) rsrc1
) >> s
;
764 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
765 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
766 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
771 /* Unimplemented cases:
772 const is in range 0..31 but rotated around end of word:
773 ror 31,3,g0 -> ldconst 0xe0000003,g0
775 and any 2 instruction cases that might be worthwhile */
777 output_asm_insn ("ldconst %1,%0", operands
);
781 /* Determine if there is an opportunity for a bypass optimization.
782 Bypass succeeds on the 960K* if the destination of the previous
783 instruction is the second operand of the current instruction.
784 Bypass always succeeds on the C*.
786 Return 1 if the pattern should interchange the operands.
788 CMPBR_FLAG is true if this is for a compare-and-branch insn.
789 OP1 and OP2 are the two source operands of a 3 operand insn. */
792 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
793 register rtx insn
, op1
, op2
;
796 register rtx prev_insn
, prev_dest
;
801 /* Can't do this if op1 isn't a register. */
805 /* Can't do this for a compare-and-branch if both ops aren't regs. */
806 if (cmpbr_flag
&& ! REG_P (op2
))
809 prev_insn
= prev_real_insn (insn
);
811 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
812 && GET_CODE (PATTERN (prev_insn
)) == SET
)
814 prev_dest
= SET_DEST (PATTERN (prev_insn
));
815 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
816 || (GET_CODE (prev_dest
) == SUBREG
817 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
818 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
824 /* Output the code which declares the function name. This also handles
825 leaf routines, which have special requirements, and initializes some
829 i960_function_name_declare (file
, name
, fndecl
)
838 /* Increment global return label. */
842 /* Compute whether tail calls and leaf routine optimizations can be performed
843 for this function. */
855 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
856 argblock, because argblock uses g14 implicitly. */
858 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
864 /* See if caller passes in an address to return value. */
866 if (aggregate_value_p (DECL_RESULT (fndecl
)))
872 /* Can not use tail calls or make this a leaf routine if there is a non
875 if (get_frame_size () != 0)
878 /* I don't understand this condition, and do not think that it is correct.
879 Apparently this is just checking whether the frame pointer is used, and
880 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
883 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
884 if (GET_CODE (insn
) == INSN
885 && reg_mentioned_p (frame_pointer_rtx
, insn
))
891 /* Check for CALL insns. Can not be a leaf routine if there are any. */
894 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
895 if (GET_CODE (insn
) == CALL_INSN
)
901 /* Can not be a leaf routine if any non-call clobbered registers are
902 used in this function. */
905 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
906 if (regs_ever_live
[i
]
907 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
909 /* Global registers. */
910 if (i
< 16 && i
> 7 && i
!= 13)
912 /* Local registers. */
917 /* Now choose a leaf return register, if we can find one, and if it is
918 OK for this to be a leaf routine. */
920 i960_leaf_ret_reg
= -1;
922 if (optimize
&& leaf_proc_ok
)
924 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
925 if (regs_ever_live
[i
] == 0)
927 i960_leaf_ret_reg
= i
;
928 regs_ever_live
[i
] = 1;
933 /* Do this after choosing the leaf return register, so it will be listed
934 if one was chosen. */
936 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
937 fprintf (file
, "\t# Registers used: ");
939 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
941 if (regs_ever_live
[i
])
943 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
945 if (i
> 15 && j
== 0)
947 fprintf (file
,"\n\t#\t\t ");
953 fprintf (file
, "\n");
955 if (i960_leaf_ret_reg
>= 0)
957 /* Make it a leaf procedure. */
959 if (TREE_PUBLIC (fndecl
))
960 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
962 fprintf (file
, "\t.leafproc\t");
963 assemble_name (file
, name
);
964 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
965 ASM_OUTPUT_LABEL (file
, name
);
966 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
967 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
968 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
972 fprintf (file
, "\tlda 0,g14\n");
973 i960_last_insn_type
= I_TYPE_MEM
;
977 fprintf (file
, "\tmov 0,g14\n");
978 i960_last_insn_type
= I_TYPE_REG
;
983 ASM_OUTPUT_LABEL (file
, name
);
984 i960_last_insn_type
= I_TYPE_CTRL
;
988 /* Compute and return the frame size. */
991 compute_frame_size (size
)
995 int outgoing_args_size
= current_function_outgoing_args_size
;
997 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
998 as size is concerned. */
999 actual_fsize
= (size
+ 15) & -16;
1000 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1002 return actual_fsize
;
1005 /* Output code for the function prologue. */
1008 i960_function_prologue (file
, size
)
1012 register int i
, j
, nr
;
1015 int actual_fsize
, offset
;
1017 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1019 int regs
[FIRST_PSEUDO_REGISTER
];
1021 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1022 if (regs_ever_live
[i
]
1023 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1026 /* Count global registers that need saving. */
1033 epilogue_string
[0] = '\0';
1035 if (profile_flag
|| profile_block_flag
)
1037 /* When profiling, we may use registers 20 to 27 to save arguments, so
1038 they can't be used here for saving globals. J is the number of
1039 argument registers the mcount call will save. */
1040 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1043 for (i
= 20; i
<= j
+ 20; i
++)
1047 /* First look for local registers to save globals in. */
1048 for (i
= 0; i
< 16; i
++)
1053 /* Start at r4, not r3. */
1054 for (j
= 20; j
< 32; j
++)
1061 regs_ever_live
[j
] = 1;
1063 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1064 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1069 regs_ever_live
[j
+1] = 1;
1071 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1072 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1077 regs_ever_live
[j
+2] = 1;
1079 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1084 regs_ever_live
[j
+3] = 1;
1087 fprintf (file
, "\tmov%s %s,%s\n",
1090 (nr
== 2) ? "l" : ""),
1091 reg_names
[i
], reg_names
[j
]);
1092 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1095 (nr
== 2) ? "l" : ""),
1096 reg_names
[j
], reg_names
[i
]);
1097 strcat (epilogue_string
, tmpstr
);
1105 /* N_iregs is now the number of global registers that haven't been saved
1108 rsize
= (n_iregs
* 4);
1109 actual_fsize
= compute_frame_size (size
) + rsize
;
1111 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1112 size up to the nearest multiple of 16. I don't know whether this is
1113 necessary, or even desirable.
1115 The frame pointer must be aligned, but the call instruction takes care of
1116 that. If we leave the stack pointer unaligned, we may save a little on
1117 dynamic stack allocation. And we don't lose, at least according to the
1119 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1122 /* Allocate space for register save and locals. */
1123 if (actual_fsize
> 0)
1125 if (actual_fsize
< 32)
1126 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1128 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1131 /* Take hardware register save area created by the call instruction
1132 into account, but store them before the argument block area. */
1133 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1134 /* Save registers on stack if needed. */
1135 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1142 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1145 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1149 if (nr
== 3 && regs
[i
+3] == -1)
1152 fprintf (file
,"\tst%s %s,%d(fp)\n",
1155 (nr
== 2) ? "l" : ""),
1156 reg_names
[i
], offset
);
1157 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1160 (nr
== 2) ? "l" : ""),
1161 offset
, reg_names
[i
]);
1162 strcat (epilogue_string
, tmpstr
);
1168 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1171 fprintf (file
, "\t#Prologue stats:\n");
1172 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1175 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1177 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1179 fprintf (file
, "\t#End Prologue#\n");
1182 /* Output code for the function profiler. */
1185 output_function_profiler (file
, labelno
)
1189 /* The last used parameter register. */
1191 int i
, j
, increment
;
1192 int varargs_stdarg_function
1193 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1195 /* Figure out the last used parameter register. The proper thing to do
1196 is to walk incoming args of the function. A function might have live
1197 parameter registers even if it has no incoming args. Note that we
1198 don't have to save parameter registers g8 to g11 because they are
1201 /* See also output_function_prologue, which tries to use local registers
1202 for preserved call-saved global registers. */
1204 for (last_parm_reg
= 7;
1205 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1209 /* Save parameter registers in regs r4 (20) to r11 (27). */
1211 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1213 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1215 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1217 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1222 fprintf (file
, "\tmov%s g%d,r%d\n",
1223 (increment
== 4 ? "q" : increment
== 3 ? "t"
1224 : increment
== 2 ? "l": ""), i
, j
);
1227 /* If this function uses the arg pointer, then save it in r3 and then
1230 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1231 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1233 /* Load location address into g0 and call mcount. */
1235 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1237 /* If this function uses the arg pointer, restore it. */
1239 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1240 fprintf (file
, "\tmov r3,g14\n");
1242 /* Restore parameter registers. */
1244 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1246 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1248 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1250 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1255 fprintf (file
, "\tmov%s r%d,g%d\n",
1256 (increment
== 4 ? "q" : increment
== 3 ? "t"
1257 : increment
== 2 ? "l": ""), j
, i
);
1261 /* Output code for the function epilogue. */
1264 i960_function_epilogue (file
, size
)
1268 if (i960_leaf_ret_reg
>= 0)
1270 fprintf (file
, "LR%d: ret\n", ret_label
);
1274 if (*epilogue_string
== 0)
1278 /* Emit a return insn, but only if control can fall through to here. */
1280 tmp
= get_last_insn ();
1283 if (GET_CODE (tmp
) == BARRIER
)
1285 if (GET_CODE (tmp
) == CODE_LABEL
)
1287 if (GET_CODE (tmp
) == JUMP_INSN
)
1289 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1293 if (GET_CODE (tmp
) == NOTE
)
1295 tmp
= PREV_INSN (tmp
);
1300 fprintf (file
, "LR%d: ret\n", ret_label
);
1304 fprintf (file
, "LR%d:\n", ret_label
);
1306 fprintf (file
, "\t#EPILOGUE#\n");
1308 /* Output the string created by the prologue which will restore all
1309 registers saved by the prologue. */
1311 if (epilogue_string
[0] != '\0')
1312 fprintf (file
, "%s", epilogue_string
);
1314 /* Must clear g14 on return. */
1316 if (current_function_args_size
!= 0
1317 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1318 fprintf (file
, "\tmov 0,g14\n");
1320 fprintf (file
, "\tret\n");
1321 fprintf (file
, "\t#End Epilogue#\n");
1324 /* Output code for a call insn. */
1327 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1328 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1330 int argsize
= INTVAL (argsize_rtx
);
1331 rtx nexti
= next_real_insn (insn
);
1333 int varargs_stdarg_function
1334 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1336 operands
[0] = target
;
1337 operands
[1] = arg_pointer
;
1339 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1340 output_asm_insn ("mov g14,r3", operands
);
1343 output_asm_insn ("lda %a1,g14", operands
);
1344 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1345 output_asm_insn ("mov 0,g14", operands
);
1347 /* The code used to assume that calls to SYMBOL_REFs could not be more
1348 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1349 feature is now implemented by relaxing in the GNU linker. It can convert
1350 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1352 /* Nexti could be zero if the called routine is volatile. */
1353 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1354 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1356 /* Delete following return insn. */
1357 if (nexti
&& no_labels_between_p (insn
, nexti
))
1358 delete_insn (nexti
);
1359 output_asm_insn ("bx %0", operands
);
1360 return "# notreached";
1363 output_asm_insn ("callx %0", operands
);
1365 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1366 output_asm_insn ("mov r3,g14", operands
);
1371 /* Output code for a return insn. */
1374 i960_output_ret_insn (insn
)
1377 static char lbuf
[20];
1379 if (*epilogue_string
!= 0)
1381 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1384 sprintf (lbuf
, "b LR%d", ret_label
);
1388 if (current_function_args_size
!= 0
1389 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1390 output_asm_insn ("mov 0,g14", 0);
1392 if (i960_leaf_ret_reg
>= 0)
1394 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1401 /* Return a character string representing the branch prediction
1402 opcode to be tacked on an instruction. This must at least
1403 return a null string. */
1406 i960_br_predict_opcode (lab_ref
, insn
)
1409 if (TARGET_BRANCH_PREDICT
)
1411 unsigned long label_uid
;
1413 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1414 label_uid
= INSN_UID (lab_ref
);
1415 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1416 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1420 /* If not optimizing, then the insn_addresses array will not be
1421 valid. In this case, always return ".t" since most branches
1422 are taken. If optimizing, return .t for backward branches
1423 and .f for forward branches. */
1425 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1434 /* Print the operand represented by rtx X formatted by code CODE. */
1437 i960_print_operand (file
, x
, code
)
1442 enum rtx_code rtxcode
= GET_CODE (x
);
1449 /* Second reg of a double. */
1450 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1454 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1462 else if (rtxcode
== MEM
)
1464 output_address (XEXP (x
, 0));
1467 else if (rtxcode
== CONST_INT
)
1469 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1470 fprintf (file
, "0x%x", INTVAL (x
));
1472 fprintf (file
, "%d", INTVAL (x
));
1475 else if (rtxcode
== CONST_DOUBLE
)
1480 if (x
== CONST0_RTX (GET_MODE (x
)))
1482 fprintf (file
, "0f0.0");
1485 else if (x
== CONST1_RTX (GET_MODE (x
)))
1487 fprintf (file
, "0f1.0");
1491 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1492 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1493 fprintf (file
, "0f%s", dstr
);
1500 /* Branch or jump, depending on assembler. */
1501 if (TARGET_ASM_COMPAT
)
1508 /* Sign of condition. */
1509 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1510 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1512 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1513 || (rtxcode
== GE
) || (rtxcode
== LE
))
1520 /* Inverted condition. */
1521 rtxcode
= reverse_condition (rtxcode
);
1525 /* Inverted condition w/ reversed operands. */
1526 rtxcode
= reverse_condition (rtxcode
);
1530 /* Reversed operand condition. */
1531 rtxcode
= swap_condition (rtxcode
);
1535 /* Normal condition. */
1537 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1538 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1539 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1540 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1541 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1542 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1543 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1544 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1545 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1546 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1551 output_addr_const (file
, x
);
1561 /* Print a memory address as an operand to reference that memory location.
1563 This is exactly the same as legitimate_address_p, except that it the prints
1564 addresses instead of recognizing them. */
1567 i960_print_operand_addr (file
, addr
)
1579 if (GET_CODE (addr
) == REG
)
1581 else if (CONSTANT_P (addr
))
1583 else if (GET_CODE (addr
) == PLUS
)
1587 op0
= XEXP (addr
, 0);
1588 op1
= XEXP (addr
, 1);
1590 if (GET_CODE (op0
) == REG
)
1593 if (GET_CODE (op1
) == REG
)
1595 else if (CONSTANT_P (op1
))
1600 else if (GET_CODE (op0
) == PLUS
)
1602 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1604 ireg
= XEXP (XEXP (op0
, 0), 0);
1605 scale
= XEXP (XEXP (op0
, 0), 1);
1606 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1608 breg
= XEXP (op0
, 1);
1614 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1616 breg
= XEXP (op0
, 0);
1617 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1619 ireg
= XEXP (op0
, 1);
1628 else if (GET_CODE (op0
) == MULT
)
1630 ireg
= XEXP (op0
, 0);
1631 scale
= XEXP (op0
, 1);
1632 if (GET_CODE (op1
) == REG
)
1634 else if (CONSTANT_P (op1
))
1642 else if (GET_CODE (addr
) == MULT
)
1644 ireg
= XEXP (addr
, 0);
1645 scale
= XEXP (addr
, 1);
1651 output_addr_const (file
, offset
);
1653 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1655 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1658 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1659 that is a valid memory address for an instruction.
1660 The MODE argument is the machine mode for the MEM expression
1661 that wants to use this address.
1663 On 80960, legitimate addresses are:
1665 disp (12 or 32 bit) ld foo,r0
1666 base + index ld (g0)[g1*1],r0
1667 base + displ ld 0xf00(g0),r0
1668 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1669 index*scale + base ld (g0)[g1*4],r0
1670 index*scale + displ ld 0xf00[g1*4],r0
1671 index*scale ld [g1*4],r0
1672 index + base + displ ld 0xf00(g0)[g1*1],r0
1674 In each case, scale can be 1, 2, 4, 8, or 16. */
1676 /* This is exactly the same as i960_print_operand_addr, except that
1677 it recognizes addresses instead of printing them.
1679 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1680 convert common non-canonical forms to canonical form so that they will
1683 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1684 where a register is valid. */
1686 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1687 ((GET_CODE (X) == REG \
1688 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1689 || (GET_CODE (X) == SUBREG \
1690 && GET_CODE (SUBREG_REG (X)) == REG \
1691 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1692 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1694 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1695 ((GET_CODE (X) == REG \
1696 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1697 || (GET_CODE (X) == SUBREG \
1698 && GET_CODE (SUBREG_REG (X)) == REG \
1699 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1700 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1703 legitimate_address_p (mode
, addr
, strict
)
1704 enum machine_mode mode
;
1708 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1710 else if (CONSTANT_P (addr
))
1712 else if (GET_CODE (addr
) == PLUS
)
1716 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1719 op0
= XEXP (addr
, 0);
1720 op1
= XEXP (addr
, 1);
1722 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1724 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1726 else if (CONSTANT_P (op1
))
1731 else if (GET_CODE (op0
) == PLUS
)
1733 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1735 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1736 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1739 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1740 && CONSTANT_P (op1
))
1745 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1747 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1748 && CONSTANT_P (op1
))
1756 else if (GET_CODE (op0
) == MULT
)
1758 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1759 && SCALE_TERM_P (XEXP (op0
, 1))))
1762 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1764 else if (CONSTANT_P (op1
))
1772 else if (GET_CODE (addr
) == MULT
)
1774 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1777 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1778 && SCALE_TERM_P (XEXP (addr
, 1)));
1784 /* Try machine-dependent ways of modifying an illegitimate address
1785 to be legitimate. If we find one, return the new, valid address.
1786 This macro is used in only one place: `memory_address' in explow.c.
1788 This converts some non-canonical addresses to canonical form so they
1789 can be recognized. */
1792 legitimize_address (x
, oldx
, mode
)
1795 enum machine_mode mode
;
1797 if (GET_CODE (x
) == SYMBOL_REF
)
1800 x
= copy_to_reg (x
);
1803 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1806 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1807 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1808 created by virtual register instantiation, register elimination, and
1809 similar optimizations. */
1810 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1811 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1812 x
= gen_rtx (PLUS
, Pmode
,
1813 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1814 XEXP (XEXP (x
, 1), 1));
1816 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1817 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1818 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1819 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1820 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1821 && CONSTANT_P (XEXP (x
, 1)))
1823 rtx constant
, other
;
1825 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1827 constant
= XEXP (x
, 1);
1828 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1830 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1832 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1833 other
= XEXP (x
, 1);
1839 x
= gen_rtx (PLUS
, Pmode
,
1840 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1841 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1842 plus_constant (other
, INTVAL (constant
)));
1849 /* Return the most stringent alignment that we are willing to consider
1850 objects of size SIZE and known alignment ALIGN as having. */
1853 i960_alignment (size
, align
)
1859 if (! TARGET_STRICT_ALIGN
)
1860 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1862 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1871 /* Modes for condition codes. */
1873 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1875 /* Modes for single-word (and smaller) quantities. */
1878 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1879 | (1 << (int) DFmode) | (1 << (int) XFmode)))
1881 /* Modes for double-word (and smaller) quantities. */
1884 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
1886 /* Modes for quad-word quantities. */
1887 #define T_MODES (~C_MODES)
1889 /* Modes for single-float quantities. */
1890 #define SF_MODES ((1 << (int) SFmode))
1892 /* Modes for double-float quantities. */
1893 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1895 /* Modes for quad-float quantities. */
1896 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
1898 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1899 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1900 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1901 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1902 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1904 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
1907 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1908 advantage of machine specific facts, such as knowing that the frame pointer
1909 is always 16 byte aligned. */
1912 i960_expr_alignment (x
, size
)
1921 switch (GET_CODE(x
))
1926 if ((align
& 0xf) == 0)
1928 else if ((align
& 0x7) == 0)
1930 else if ((align
& 0x3) == 0)
1932 else if ((align
& 0x1) == 0)
1939 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1940 i960_expr_alignment (XEXP (x
, 1), size
));
1944 /* If this is a valid program, objects are guaranteed to be
1945 correctly aligned for whatever size the reference actually is. */
1946 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1950 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1955 align
= i960_expr_alignment (XEXP (x
, 0));
1957 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1959 align
= align
<< INTVAL (XEXP (x
, 1));
1960 align
= MIN (align
, 16);
1965 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1966 i960_expr_alignment (XEXP (x
, 1), size
));
1968 align
= MIN (align
, 16);
1975 /* Return true if it is possible to reference both BASE and OFFSET, which
1976 have alignment at least as great as 4 byte, as if they had alignment valid
1977 for an object of size SIZE. */
1980 i960_improve_align (base
, offset
, size
)
1987 /* We have at least a word reference to the object, so we know it has to
1988 be aligned at least to 4 bytes. */
1990 i
= MIN (i960_expr_alignment (base
, 4),
1991 i960_expr_alignment (offset
, 4));
1995 /* We know the size of the request. If strict align is not enabled, we
1996 can guess that the alignment is OK for the requested size. */
1998 if (! TARGET_STRICT_ALIGN
)
1999 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2005 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2006 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2009 i960_si_ti (base
, offset
)
2013 return i960_improve_align (base
, offset
, 16);
2016 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2017 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2020 i960_si_di (base
, offset
)
2024 return i960_improve_align (base
, offset
, 8);
2027 /* Return raw values of size and alignment (in words) for the data
2028 type being accessed. These values will be rounded by the caller. */
2031 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2032 enum machine_mode mode
;
2039 /* Use formal alignment requirements of type being passed, except make
2040 it at least a word. If we don't have a type, this is a library call,
2041 and the parm has to be of scalar type. In this case, consider its
2042 formal alignment requirement to be its size in words. */
2044 if (mode
== BLKmode
)
2045 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2046 else if (mode
== VOIDmode
)
2048 /* End of parm list. */
2049 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2053 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2057 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2058 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2066 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2067 Any arg that is bigger than 4 words is placed on the stack and all
2068 subsequent arguments are placed on the stack.
2070 Additionally, parameters with an alignment requirement stronger than
2071 a word must be be aligned appropriately. */
2073 /* Update CUM to advance past an argument described by MODE and TYPE. */
2076 i960_function_arg_advance (cum
, mode
, type
, named
)
2077 CUMULATIVE_ARGS
*cum
;
2078 enum machine_mode mode
;
2084 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2086 if (size
> 4 || cum
->ca_nstackparms
!= 0
2087 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2088 || MUST_PASS_IN_STACK (mode
, type
))
2090 /* Indicate that all the registers are in use, even if all are not,
2091 so va_start will compute the right value. */
2092 cum
->ca_nregparms
= NPARM_REGS
;
2093 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2096 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2099 /* Return the register that the argument described by MODE and TYPE is
2100 passed in, or else return 0 if it is passed on the stack. */
2103 i960_function_arg (cum
, mode
, type
, named
)
2104 CUMULATIVE_ARGS
*cum
;
2105 enum machine_mode mode
;
2112 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2114 if (size
> 4 || cum
->ca_nstackparms
!= 0
2115 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2116 || MUST_PASS_IN_STACK (mode
, type
))
2118 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2123 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2124 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2130 /* Floating-point support. */
2133 i960_output_long_double (file
, value
)
2135 REAL_VALUE_TYPE value
;
2140 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2141 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2144 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2145 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2146 fprintf (file
, "\t.word\t0x0\n");
2150 i960_output_double (file
, value
)
2152 REAL_VALUE_TYPE value
;
2157 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2158 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2160 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2161 value_long
[0], dstr
, value_long
[1]);
2165 i960_output_float (file
, value
)
2167 REAL_VALUE_TYPE value
;
2172 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2173 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2175 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2178 /* Return the number of bits that an object of size N bytes is aligned to. */
2181 i960_object_bytes_bitalign (n
)
2185 else if (n
> 4) n
= 64;
2186 else if (n
> 2) n
= 32;
2187 else if (n
> 1) n
= 16;
2193 /* Compute the alignment for an aggregate type TSIZE.
2194 Alignment is MAX (greatest member alignment,
2195 MIN (pragma align, structure size alignment)). */
2198 i960_round_align (align
, tsize
)
2204 if (TREE_CODE (tsize
) != INTEGER_CST
)
2207 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2209 /* Handle #pragma align. */
2210 if (new_align
> i960_maxbitalignment
)
2211 new_align
= i960_maxbitalignment
;
2213 if (align
< new_align
)
2219 /* Do any needed setup for a varargs function. For the i960, we must
2220 create a register parameter block if one doesn't exist, and then copy
2221 all register parameters to memory. */
2224 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2225 CUMULATIVE_ARGS
*cum
;
2226 enum machine_mode mode
;
2231 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2232 int first_reg
= cum
->ca_nregparms
;
2234 /* Copy only unnamed register arguments to memory. If there are
2235 any stack parms, there are no unnamed arguments in registers, and
2236 an argument block was already allocated by the caller.
2237 Remember that any arg bigger than 4 words is passed on the stack as
2238 are all subsequent args.
2240 If there are no stack arguments but there are exactly NPARM_REGS
2241 registers, either there were no extra arguments or the caller
2242 allocated an argument block. */
2244 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2246 rtx label
= gen_label_rtx ();
2249 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2250 and we need to allocate a chunk to save the registers (if any
2251 arguments were passed on the stack the caller would allocate the
2252 48 bytes as well). We must allocate all 48 bytes (12*4) because
2253 va_start assumes it. */
2254 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2255 emit_jump_insn (gen_bne (label
));
2256 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2257 stack_pointer_rtx
));
2258 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2259 memory_address (SImode
,
2260 plus_constant (stack_pointer_rtx
,
2264 /* ??? Note that we unnecessarily store one extra register for stdarg
2265 fns. We could optimize this, but it's kept as for now. */
2266 regblock
= gen_rtx (MEM
, BLKmode
,
2267 plus_constant (arg_pointer_rtx
,
2269 move_block_from_reg (first_reg
, regblock
,
2270 NPARM_REGS
- first_reg
,
2271 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2275 /* Calculate the final size of the reg parm stack space for the current
2276 function, based on how many bytes would be allocated on the stack. */
2279 i960_final_reg_parm_stack_space (const_size
, var_size
)
2283 if (var_size
|| const_size
> 48)
2289 /* Calculate the size of the reg parm stack space. This is a bit complicated
2293 i960_reg_parm_stack_space (fndecl
)
2296 /* In this case, we are called from emit_library_call, and we don't need
2297 to pretend we have more space for parameters than what's apparent. */
2301 /* In this case, we are called from locate_and_pad_parms when we're
2302 not IN_REGS, so we have an arg block. */
2303 if (fndecl
!= current_function_decl
)
2306 /* Otherwise, we have an arg block if the current function has more than
2307 48 bytes of parameters. */
2308 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2314 /* Return the register class of a scratch register needed to copy IN into
2315 or out of a register in CLASS in MODE. If it can be done directly,
2316 NO_REGS is returned. */
2319 secondary_reload_class (class, mode
, in
)
2320 enum reg_class
class;
2321 enum machine_mode mode
;
2326 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2327 regno
= true_regnum (in
);
2329 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2330 LOCAL_OR_GLOBAL_REGS into anything. */
2331 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2332 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2335 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2336 if (class == FP_REGS
2337 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2338 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2341 return LOCAL_OR_GLOBAL_REGS
;
2344 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2345 function unit it executed on. */
2347 /* ??? This would make more sense as an attribute. */
2350 i960_scan_opcode (p
)
2362 /* Ret is not actually of type REG, but it won't matter, because no
2363 insn will ever follow it. */
2366 i960_last_insn_type
= I_TYPE_REG
;
2370 if (p
[1] == 'x' || p
[3] == 'x')
2371 i960_last_insn_type
= I_TYPE_MEM
;
2372 i960_last_insn_type
= I_TYPE_CTRL
;
2377 i960_last_insn_type
= I_TYPE_CTRL
;
2384 i960_last_insn_type
= I_TYPE_MEM
;
2386 i960_last_insn_type
= I_TYPE_CTRL
;
2388 else if (p
[1] == 'm')
2391 i960_last_insn_type
= I_TYPE_REG
;
2392 else if (p
[4] == 'b' || p
[4] == 'j')
2393 i960_last_insn_type
= I_TYPE_CTRL
;
2395 i960_last_insn_type
= I_TYPE_REG
;
2398 i960_last_insn_type
= I_TYPE_REG
;
2402 i960_last_insn_type
= I_TYPE_MEM
;
2407 i960_last_insn_type
= I_TYPE_MEM
;
2409 i960_last_insn_type
= I_TYPE_REG
;