1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
49 rtx i960_compare_op0
, i960_compare_op1
;
51 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
54 static int i960_maxbitalignment
;
55 static int i960_last_maxbitalignment
;
57 /* Used to implement switching between MEM and ALU insn types, for better
58 C series performance. */
60 enum insn_types i960_last_insn_type
;
62 /* The leaf-procedure return register. Set only if this is a leaf routine. */
64 static int i960_leaf_ret_reg
;
66 /* True if replacing tail calls with jumps is OK. */
68 static int tail_call_ok
;
70 /* A string containing a list of insns to emit in the epilogue so as to
71 restore all registers saved by the prologue. Created by the prologue
72 code as it saves registers away. */
74 char epilogue_string
[1000];
76 /* A unique number (per function) for return labels. */
78 static int ret_label
= 0;
80 /* This is true if FNDECL is either a varargs or a stdarg function.
81 This is used to help identify functions that use an argument block. */
83 #define VARARGS_STDARG_FUNCTION(FNDECL) \
84 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
85 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
86 || current_function_varargs)
88 /* Handle pragmas for compatibility with Intel's compilers. */
90 /* ??? This is incomplete, since it does not handle all pragmas that the
91 intel compilers understand. */
94 process_pragma (finput
, t
)
100 register char *pname
;
102 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
105 pname
= IDENTIFIER_POINTER (t
);
107 if (strcmp (pname
, "align") == 0)
115 } while (c
== ' ' || c
== '\t');
119 while (c
>= '0' && c
<= '9')
121 if (s
< buf
+ sizeof buf
- 1)
131 /* Return to last alignment. */
132 align
= i960_last_maxbitalignment
/ 8;
139 i960_last_maxbitalignment
= i960_maxbitalignment
;
140 i960_maxbitalignment
= align
* 8;
144 /* Silently ignore bad values. */
148 /* NOTE: ic960 R3.0 pragma align definition:
150 #pragma align [(size)] | (identifier=size[,...])
151 #pragma noalign [(identifier)[,...]]
153 (all parens are optional)
155 - size is [1,2,4,8,16]
156 - noalign means size==1
157 - applies only to component elements of a struct (and union?)
158 - identifier applies to structure tag (only)
159 - missing identifier means next struct
161 - alignment rules for bitfields need more investigation */
166 /* Should be pragma 'far' or equivalent for callx/balx here. */
171 /* Initialize variables before compiling any files. */
176 if (TARGET_IC_COMPAT2_0
)
178 i960_maxbitalignment
= 8;
179 i960_last_maxbitalignment
= 128;
183 i960_maxbitalignment
= 128;
184 i960_last_maxbitalignment
= 8;
188 /* Return true if OP can be used as the source of an fp move insn. */
191 fpmove_src_operand (op
, mode
)
193 enum machine_mode mode
;
195 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
199 /* Return true if OP is a register or zero. */
202 reg_or_zero_operand (op
, mode
)
204 enum machine_mode mode
;
206 return register_operand (op
, mode
) || op
== const0_rtx
;
210 /* Return truth value of whether OP can be used as an operands in a three
211 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
214 arith_operand (op
, mode
)
216 enum machine_mode mode
;
218 return (register_operand (op
, mode
) || literal (op
, mode
));
221 /* Return truth value of whether OP can be used as an operands in a three
222 address logic insn, possibly complementing OP, of mode MODE. */
225 logic_operand (op
, mode
)
227 enum machine_mode mode
;
229 return (register_operand (op
, mode
)
230 || (GET_CODE (op
) == CONST_INT
231 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
234 /* Return true if OP is a register or a valid floating point literal. */
237 fp_arith_operand (op
, mode
)
239 enum machine_mode mode
;
241 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
244 /* Return true is OP is a register or a valid signed integer literal. */
247 signed_arith_operand (op
, mode
)
249 enum machine_mode mode
;
251 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
254 /* Return truth value of whether OP is a integer which fits the
255 range constraining immediate operands in three-address insns. */
260 enum machine_mode mode
;
262 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
265 /* Return true if OP is a float constant of 1. */
268 fp_literal_one (op
, mode
)
270 enum machine_mode mode
;
272 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
275 /* Return true if OP is a float constant of 0. */
278 fp_literal_zero (op
, mode
)
280 enum machine_mode mode
;
282 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
285 /* Return true if OP is a valid floating point literal. */
290 enum machine_mode mode
;
292 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
295 /* Return true if OP is a valid signed immediate constant. */
298 signed_literal(op
, mode
)
300 enum machine_mode mode
;
302 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
305 /* Return truth value of statement that OP is a symbolic memory
306 operand of mode MODE. */
309 symbolic_memory_operand (op
, mode
)
311 enum machine_mode mode
;
313 if (GET_CODE (op
) == SUBREG
)
314 op
= SUBREG_REG (op
);
315 if (GET_CODE (op
) != MEM
)
318 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
319 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
322 /* Return truth value of whether OP is EQ or NE. */
327 enum machine_mode mode
;
329 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
332 /* OP is an integer register or a constant. */
335 arith32_operand (op
, mode
)
337 enum machine_mode mode
;
339 if (register_operand (op
, mode
))
341 return (CONSTANT_P (op
));
344 /* Return true if OP is an integer constant which is a power of 2. */
347 power2_operand (op
,mode
)
349 enum machine_mode mode
;
351 if (GET_CODE (op
) != CONST_INT
)
354 return exact_log2 (INTVAL (op
)) >= 0;
357 /* Return true if OP is an integer constant which is the complement of a
361 cmplpower2_operand (op
, mode
)
363 enum machine_mode mode
;
365 if (GET_CODE (op
) != CONST_INT
)
368 return exact_log2 (~ INTVAL (op
)) >= 0;
371 /* If VAL has only one bit set, return the index of that bit. Otherwise
380 for (i
= 0; val
!= 0; i
++, val
>>= 1)
392 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
393 The return value indicates how many consecutive non-zero bits exist
394 if this is a mask. This is the same as the next function, except that
395 it does not indicate what the start and stop bit positions are. */
401 register int start
, end
, i
;
404 for (i
= 0; val
!= 0; val
>>= 1, i
++)
414 /* Still looking for the first bit. */
418 /* We've seen the start of a bit sequence, and now a zero. There
419 must be more one bits, otherwise we would have exited the loop.
420 Therefore, it is not a mask. */
425 /* The bit string has ones from START to END bit positions only. */
426 return end
- start
+ 1;
429 /* If VAL is a mask, then return nonzero, with S set to the starting bit
430 position and E set to the ending bit position of the mask. The return
431 value indicates how many consecutive bits exist in the mask. This is
432 the same as the previous function, except that it also indicates the
433 start and end bit positions of the mask. */
440 register int start
, end
, i
;
444 for (i
= 0; val
!= 0; val
>>= 1, i
++)
455 /* Still looking for the first bit. */
459 /* We've seen the start of a bit sequence, and now a zero. There
460 must be more one bits, otherwise we would have exited the loop.
461 Therefor, it is not a mask. */
470 /* The bit string has ones from START to END bit positions only. */
473 return ((start
< 0) ? 0 : end
- start
+ 1);
476 /* Return the machine mode to use for a comparison. */
479 select_cc_mode (op
, x
)
483 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
488 /* X and Y are two things to compare using CODE. Emit the compare insn and
489 return the rtx for register 36 in the proper mode. */
492 gen_compare_reg (code
, x
, y
)
497 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
498 enum machine_mode mode
499 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
503 if (! arith_operand (x
, mode
))
504 x
= force_reg (SImode
, x
);
505 if (! arith_operand (y
, mode
))
506 y
= force_reg (SImode
, y
);
509 cc_reg
= gen_rtx (REG
, ccmode
, 36);
510 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
511 gen_rtx (COMPARE
, ccmode
, x
, y
)));
516 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
517 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
518 are 4. Indexed addresses are cost 6. */
520 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
523 i960_address_cost (x
)
527 /* Handled before calling here. */
528 if (GET_CODE (x
) == REG
)
531 if (GET_CODE (x
) == PLUS
)
533 rtx base
= XEXP (x
, 0);
534 rtx offset
= XEXP (x
, 1);
536 if (GET_CODE (base
) == SUBREG
)
537 base
= SUBREG_REG (base
);
538 if (GET_CODE (offset
) == SUBREG
)
539 offset
= SUBREG_REG (offset
);
541 if (GET_CODE (base
) == REG
)
543 if (GET_CODE (offset
) == REG
)
545 if (GET_CODE (offset
) == CONST_INT
)
547 if ((unsigned)INTVAL (offset
) < 2047)
551 if (CONSTANT_P (offset
))
554 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
557 /* This is an invalid address. The return value doesn't matter, but
558 for convenience we make this more expensive than anything else. */
561 if (GET_CODE (x
) == MULT
)
564 /* Symbol_refs and other unrecognized addresses are cost 4. */
568 /* Emit insns to move operands[1] into operands[0].
570 Return 1 if we have written out everything that needs to be done to
571 do the move. Otherwise, return 0 and the caller will emit the move
575 emit_move_sequence (operands
, mode
)
577 enum machine_mode mode
;
579 /* We can only store registers to memory. */
581 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
582 operands
[1] = force_reg (mode
, operands
[1]);
584 /* Storing multi-word values in unaligned hard registers to memory may
585 require a scratch since we have to store them a register at a time and
586 adding 4 to the memory address may not yield a valid insn. */
587 /* ??? We don't always need the scratch, but that would complicate things.
589 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
590 && GET_CODE (operands
[0]) == MEM
591 && GET_CODE (operands
[1]) == REG
592 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
593 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
595 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
597 gen_rtx (SET
, VOIDmode
,
598 operands
[0], operands
[1]),
599 gen_rtx (CLOBBER
, VOIDmode
,
600 gen_rtx (SCRATCH
, Pmode
)))));
607 /* Output assembler to move a double word value. */
610 i960_output_move_double (dst
, src
)
615 if (GET_CODE (dst
) == REG
616 && GET_CODE (src
) == REG
)
618 if ((REGNO (src
) & 1)
619 || (REGNO (dst
) & 1))
621 /* We normally copy the low-numbered register first. However, if
622 the second source register is the same as the first destination
623 register, we must copy in the opposite order. */
624 if (REGNO (src
) + 1 == REGNO (dst
))
625 return "mov %D1,%D0\n\tmov %1,%0";
627 return "mov %1,%0\n\tmov %D1,%D0";
632 else if (GET_CODE (dst
) == REG
633 && GET_CODE (src
) == CONST_INT
634 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
637 return "mov %1,%0\n\tmov 0,%D0";
641 else if (GET_CODE (dst
) == REG
642 && GET_CODE (src
) == MEM
)
646 /* One can optimize a few cases here, but you have to be
647 careful of clobbering registers used in the address and
651 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
652 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
653 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
654 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
660 else if (GET_CODE (dst
) == MEM
661 && GET_CODE (src
) == REG
)
665 /* This is handled by emit_move_sequence so we shouldn't get here. */
674 /* Output assembler to move a quad word value. */
677 i960_output_move_quad (dst
, src
)
682 if (GET_CODE (dst
) == REG
683 && GET_CODE (src
) == REG
)
685 if ((REGNO (src
) & 3)
686 || (REGNO (dst
) & 3))
688 /* We normally copy starting with the low numbered register.
689 However, if there is an overlap such that the first dest reg
690 is <= the last source reg but not < the first source reg, we
691 must copy in the opposite order. */
692 if (REGNO (dst
) <= REGNO (src
) + 3
693 && REGNO (dst
) >= REGNO (src
))
694 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
696 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
701 else if (GET_CODE (dst
) == REG
702 && GET_CODE (src
) == CONST_INT
703 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
706 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
710 else if (GET_CODE (dst
) == REG
711 && GET_CODE (src
) == MEM
)
715 /* One can optimize a few cases here, but you have to be
716 careful of clobbering registers used in the address and
720 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
721 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
722 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
723 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
724 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
725 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
731 else if (GET_CODE (dst
) == MEM
732 && GET_CODE (src
) == REG
)
736 /* This is handled by emit_move_sequence so we shouldn't get here. */
745 /* Emit insns to load a constant to non-floating point registers.
746 Uses several strategies to try to use as few insns as possible. */
749 i960_output_ldconst (dst
, src
)
750 register rtx dst
, src
;
753 register unsigned rsrc2
;
754 enum machine_mode mode
= GET_MODE (dst
);
757 operands
[0] = operands
[2] = dst
;
758 operands
[1] = operands
[3] = src
;
760 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
761 must be a ldconst insn. */
763 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
765 output_asm_insn ("ldconst %1,%0", operands
);
768 else if (mode
== XFmode
)
774 if (fp_literal_zero (src
, XFmode
))
777 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
778 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
780 output_asm_insn ("# ldconst %1,%0",operands
);
782 for (i
= 0; i
< 3; i
++)
784 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
785 operands
[1] = GEN_INT (value_long
[i
]);
786 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
792 else if (mode
== DFmode
)
796 if (fp_literal_zero (src
, DFmode
))
799 split_double (src
, &first
, &second
);
801 output_asm_insn ("# ldconst %1,%0",operands
);
803 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
805 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
807 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
808 operands
[1] = second
;
809 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
813 else if (mode
== SFmode
)
818 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
819 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
821 output_asm_insn ("# ldconst %1,%0",operands
);
822 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
823 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
824 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
828 else if (mode
== TImode
)
830 /* ??? This is currently not handled at all. */
833 /* Note: lowest order word goes in lowest numbered reg. */
834 rsrc1
= INTVAL (src
);
835 if (rsrc1
>= 0 && rsrc1
< 32)
838 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
839 /* Go pick up the low-order word. */
841 else if (mode
== DImode
)
843 rtx upperhalf
, lowerhalf
, xoperands
[2];
845 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
846 split_double (src
, &lowerhalf
, &upperhalf
);
851 /* Note: lowest order word goes in lowest numbered reg. */
852 /* Numbers from 0 to 31 can be handled with a single insn. */
853 rsrc1
= INTVAL (lowerhalf
);
854 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
857 /* Output the upper half with a recursive call. */
858 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
859 xoperands
[1] = upperhalf
;
860 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
862 /* The lower word is emitted as normally. */
866 rsrc1
= INTVAL (src
);
872 else if (mode
== HImode
)
881 /* ldconst 0..31,X -> mov 0..31,X */
884 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
889 /* ldconst 32..63,X -> add 31,nn,X */
892 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
894 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
895 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
901 /* ldconst -1..-31 -> sub 0,0..31,X */
904 /* return 'sub -(%1),0,%0' */
905 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
906 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
910 /* ldconst -32 -> not 31,X */
913 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
914 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
919 /* If const is a single bit. */
920 if (bitpos (rsrc1
) >= 0)
922 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
923 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
927 /* If const is a bit string of less than 6 bits (1..31 shifted). */
932 if (bitstr (rsrc1
, &s
, &e
) < 6)
934 rsrc2
= ((unsigned int) rsrc1
) >> s
;
935 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
936 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
937 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
942 /* Unimplemented cases:
943 const is in range 0..31 but rotated around end of word:
944 ror 31,3,g0 -> ldconst 0xe0000003,g0
946 and any 2 instruction cases that might be worthwhile */
948 output_asm_insn ("ldconst %1,%0", operands
);
952 /* Determine if there is an opportunity for a bypass optimization.
953 Bypass succeeds on the 960K* if the destination of the previous
954 instruction is the second operand of the current instruction.
955 Bypass always succeeds on the C*.
957 Return 1 if the pattern should interchange the operands.
959 CMPBR_FLAG is true if this is for a compare-and-branch insn.
960 OP1 and OP2 are the two source operands of a 3 operand insn. */
963 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
964 register rtx insn
, op1
, op2
;
967 register rtx prev_insn
, prev_dest
;
972 /* Can't do this if op1 isn't a register. */
976 /* Can't do this for a compare-and-branch if both ops aren't regs. */
977 if (cmpbr_flag
&& ! REG_P (op2
))
980 prev_insn
= prev_real_insn (insn
);
982 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
983 && GET_CODE (PATTERN (prev_insn
)) == SET
)
985 prev_dest
= SET_DEST (PATTERN (prev_insn
));
986 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
987 || (GET_CODE (prev_dest
) == SUBREG
988 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
989 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
995 /* Output the code which declares the function name. This also handles
996 leaf routines, which have special requirements, and initializes some
1000 i960_function_name_declare (file
, name
, fndecl
)
1009 /* Increment global return label. */
1013 /* Compute whether tail calls and leaf routine optimizations can be performed
1014 for this function. */
1016 if (TARGET_TAILCALL
)
1021 if (TARGET_LEAFPROC
)
1026 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1027 argblock, because argblock uses g14 implicitly. */
1029 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1035 /* See if caller passes in an address to return value. */
1037 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1043 /* Can not use tail calls or make this a leaf routine if there is a non
1046 if (get_frame_size () != 0)
1049 /* I don't understand this condition, and do not think that it is correct.
1050 Apparently this is just checking whether the frame pointer is used, and
1051 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1054 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1055 if (GET_CODE (insn
) == INSN
1056 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1062 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1065 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1066 if (GET_CODE (insn
) == CALL_INSN
)
1072 /* Can not be a leaf routine if any non-call clobbered registers are
1073 used in this function. */
1076 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1077 if (regs_ever_live
[i
]
1078 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1080 /* Global registers. */
1081 if (i
< 16 && i
> 7 && i
!= 13)
1083 /* Local registers. */
1088 /* Now choose a leaf return register, if we can find one, and if it is
1089 OK for this to be a leaf routine. */
1091 i960_leaf_ret_reg
= -1;
1093 if (optimize
&& leaf_proc_ok
)
1095 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1096 if (regs_ever_live
[i
] == 0)
1098 i960_leaf_ret_reg
= i
;
1099 regs_ever_live
[i
] = 1;
1104 /* Do this after choosing the leaf return register, so it will be listed
1105 if one was chosen. */
1107 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1108 fprintf (file
, "\t# Registers used: ");
1110 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1112 if (regs_ever_live
[i
])
1114 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1116 if (i
> 15 && j
== 0)
1118 fprintf (file
,"\n\t#\t\t ");
1124 fprintf (file
, "\n");
1126 if (i960_leaf_ret_reg
>= 0)
1128 /* Make it a leaf procedure. */
1130 if (TREE_PUBLIC (fndecl
))
1131 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1133 fprintf (file
, "\t.leafproc\t");
1134 assemble_name (file
, name
);
1135 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1136 ASM_OUTPUT_LABEL (file
, name
);
1137 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1138 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1139 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1141 if (TARGET_C_SERIES
)
1143 fprintf (file
, "\tlda 0,g14\n");
1144 i960_last_insn_type
= I_TYPE_MEM
;
1148 fprintf (file
, "\tmov 0,g14\n");
1149 i960_last_insn_type
= I_TYPE_REG
;
1154 ASM_OUTPUT_LABEL (file
, name
);
1155 i960_last_insn_type
= I_TYPE_CTRL
;
1159 /* Compute and return the frame size. */
1162 compute_frame_size (size
)
1166 int outgoing_args_size
= current_function_outgoing_args_size
;
1168 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1169 as size is concerned. */
1170 actual_fsize
= (size
+ 15) & -16;
1171 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1173 return actual_fsize
;
1176 /* Output code for the function prologue. */
1179 i960_function_prologue (file
, size
)
1183 register int i
, j
, nr
;
1186 int actual_fsize
, offset
;
1188 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1190 int regs
[FIRST_PSEUDO_REGISTER
];
1192 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1193 if (regs_ever_live
[i
]
1194 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1197 /* Count global registers that need saving. */
1204 epilogue_string
[0] = '\0';
1206 if (profile_flag
|| profile_block_flag
)
1208 /* When profiling, we may use registers 20 to 27 to save arguments, so
1209 they can't be used here for saving globals. J is the number of
1210 argument registers the mcount call will save. */
1211 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1214 for (i
= 20; i
<= j
+ 20; i
++)
1218 /* First look for local registers to save globals in. */
1219 for (i
= 0; i
< 16; i
++)
1224 /* Start at r4, not r3. */
1225 for (j
= 20; j
< 32; j
++)
1232 regs_ever_live
[j
] = 1;
1234 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1235 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1240 regs_ever_live
[j
+1] = 1;
1242 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1243 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1248 regs_ever_live
[j
+2] = 1;
1250 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1255 regs_ever_live
[j
+3] = 1;
1258 fprintf (file
, "\tmov%s %s,%s\n",
1261 (nr
== 2) ? "l" : ""),
1262 reg_names
[i
], reg_names
[j
]);
1263 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1266 (nr
== 2) ? "l" : ""),
1267 reg_names
[j
], reg_names
[i
]);
1268 strcat (epilogue_string
, tmpstr
);
1276 /* N_iregs is now the number of global registers that haven't been saved
1279 rsize
= (n_iregs
* 4);
1280 actual_fsize
= compute_frame_size (size
) + rsize
;
1282 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1283 size up to the nearest multiple of 16. I don't know whether this is
1284 necessary, or even desirable.
1286 The frame pointer must be aligned, but the call instruction takes care of
1287 that. If we leave the stack pointer unaligned, we may save a little on
1288 dynamic stack allocation. And we don't lose, at least according to the
1290 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1293 /* Allocate space for register save and locals. */
1294 if (actual_fsize
> 0)
1296 if (actual_fsize
< 32)
1297 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1299 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1302 /* Take hardware register save area created by the call instruction
1303 into account, but store them before the argument block area. */
1304 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1305 /* Save registers on stack if needed. */
1306 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1313 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1316 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1320 if (nr
== 3 && regs
[i
+3] == -1)
1323 fprintf (file
,"\tst%s %s,%d(fp)\n",
1326 (nr
== 2) ? "l" : ""),
1327 reg_names
[i
], offset
);
1328 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1331 (nr
== 2) ? "l" : ""),
1332 offset
, reg_names
[i
]);
1333 strcat (epilogue_string
, tmpstr
);
1339 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1342 fprintf (file
, "\t#Prologue stats:\n");
1343 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1346 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1348 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1350 fprintf (file
, "\t#End Prologue#\n");
1353 /* Output code for the function profiler. */
1356 output_function_profiler (file
, labelno
)
1360 /* The last used parameter register. */
1362 int i
, j
, increment
;
1363 int varargs_stdarg_function
1364 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1366 /* Figure out the last used parameter register. The proper thing to do
1367 is to walk incoming args of the function. A function might have live
1368 parameter registers even if it has no incoming args. Note that we
1369 don't have to save parameter registers g8 to g11 because they are
1372 /* See also output_function_prologue, which tries to use local registers
1373 for preserved call-saved global registers. */
1375 for (last_parm_reg
= 7;
1376 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1380 /* Save parameter registers in regs r4 (20) to r11 (27). */
1382 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1384 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1386 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1388 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1393 fprintf (file
, "\tmov%s g%d,r%d\n",
1394 (increment
== 4 ? "q" : increment
== 3 ? "t"
1395 : increment
== 2 ? "l": ""), i
, j
);
1398 /* If this function uses the arg pointer, then save it in r3 and then
1401 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1402 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1404 /* Load location address into g0 and call mcount. */
1406 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1408 /* If this function uses the arg pointer, restore it. */
1410 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1411 fprintf (file
, "\tmov r3,g14\n");
1413 /* Restore parameter registers. */
1415 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1417 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1419 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1421 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1426 fprintf (file
, "\tmov%s r%d,g%d\n",
1427 (increment
== 4 ? "q" : increment
== 3 ? "t"
1428 : increment
== 2 ? "l": ""), j
, i
);
1432 /* Output code for the function epilogue. */
1435 i960_function_epilogue (file
, size
)
1439 if (i960_leaf_ret_reg
>= 0)
1441 fprintf (file
, "LR%d: ret\n", ret_label
);
1445 if (*epilogue_string
== 0)
1449 /* Emit a return insn, but only if control can fall through to here. */
1451 tmp
= get_last_insn ();
1454 if (GET_CODE (tmp
) == BARRIER
)
1456 if (GET_CODE (tmp
) == CODE_LABEL
)
1458 if (GET_CODE (tmp
) == JUMP_INSN
)
1460 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1464 if (GET_CODE (tmp
) == NOTE
)
1466 tmp
= PREV_INSN (tmp
);
1471 fprintf (file
, "LR%d: ret\n", ret_label
);
1475 fprintf (file
, "LR%d:\n", ret_label
);
1477 fprintf (file
, "\t#EPILOGUE#\n");
1479 /* Output the string created by the prologue which will restore all
1480 registers saved by the prologue. */
1482 if (epilogue_string
[0] != '\0')
1483 fprintf (file
, "%s", epilogue_string
);
1485 /* Must clear g14 on return if this function set it.
1486 Only varargs/stdarg functions modify g14. */
1488 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1489 fprintf (file
, "\tmov 0,g14\n");
1491 fprintf (file
, "\tret\n");
1492 fprintf (file
, "\t#End Epilogue#\n");
1495 /* Output code for a call insn. */
1498 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1499 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1501 int argsize
= INTVAL (argsize_rtx
);
1502 rtx nexti
= next_real_insn (insn
);
1504 int varargs_stdarg_function
1505 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1507 operands
[0] = target
;
1508 operands
[1] = arg_pointer
;
1510 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1511 output_asm_insn ("mov g14,r3", operands
);
1514 output_asm_insn ("lda %a1,g14", operands
);
1515 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1516 output_asm_insn ("mov 0,g14", operands
);
1518 /* The code used to assume that calls to SYMBOL_REFs could not be more
1519 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1520 feature is now implemented by relaxing in the GNU linker. It can convert
1521 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1523 /* Nexti could be zero if the called routine is volatile. */
1524 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1525 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1527 /* Delete following return insn. */
1528 if (nexti
&& no_labels_between_p (insn
, nexti
))
1529 delete_insn (nexti
);
1530 output_asm_insn ("bx %0", operands
);
1531 return "# notreached";
1534 output_asm_insn ("callx %0", operands
);
1536 /* If the caller sets g14 to the address of the argblock, then the caller
1537 must clear it after the return. */
1539 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1540 output_asm_insn ("mov r3,g14", operands
);
1541 else if (argsize
> 48)
1542 output_asm_insn ("mov 0,g14", operands
);
1547 /* Output code for a return insn. */
1550 i960_output_ret_insn (insn
)
1553 static char lbuf
[20];
1555 if (*epilogue_string
!= 0)
1557 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1560 sprintf (lbuf
, "b LR%d", ret_label
);
1564 /* Must clear g14 on return if this function set it.
1565 Only varargs/stdarg functions modify g14. */
1567 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1568 output_asm_insn ("mov 0,g14", 0);
1570 if (i960_leaf_ret_reg
>= 0)
1572 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1579 /* Return a character string representing the branch prediction
1580 opcode to be tacked on an instruction. This must at least
1581 return a null string. */
1584 i960_br_predict_opcode (lab_ref
, insn
)
1587 if (TARGET_BRANCH_PREDICT
)
1589 unsigned long label_uid
;
1591 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1592 label_uid
= INSN_UID (lab_ref
);
1593 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1594 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1598 /* If not optimizing, then the insn_addresses array will not be
1599 valid. In this case, always return ".t" since most branches
1600 are taken. If optimizing, return .t for backward branches
1601 and .f for forward branches. */
1603 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1612 /* Print the operand represented by rtx X formatted by code CODE. */
1615 i960_print_operand (file
, x
, code
)
1620 enum rtx_code rtxcode
= GET_CODE (x
);
1627 /* Second reg of a double or quad. */
1628 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1632 /* Third reg of a quad. */
1633 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1637 /* Fourth reg of a quad. */
1638 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1642 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1650 else if (rtxcode
== MEM
)
1652 output_address (XEXP (x
, 0));
1655 else if (rtxcode
== CONST_INT
)
1657 HOST_WIDE_INT val
= INTVAL (x
);
1660 if (val
> 9999 || val
< -999)
1661 fprintf (file
, "0x%x", val
);
1663 fprintf (file
, "%d", val
);
1666 else if (rtxcode
== CONST_DOUBLE
)
1671 if (x
== CONST0_RTX (GET_MODE (x
)))
1673 fprintf (file
, "0f0.0");
1676 else if (x
== CONST1_RTX (GET_MODE (x
)))
1678 fprintf (file
, "0f1.0");
1682 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1683 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1684 fprintf (file
, "0f%s", dstr
);
1691 /* Branch or jump, depending on assembler. */
1692 if (TARGET_ASM_COMPAT
)
1699 /* Sign of condition. */
1700 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1701 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1703 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1704 || (rtxcode
== GE
) || (rtxcode
== LE
))
1711 /* Inverted condition. */
1712 rtxcode
= reverse_condition (rtxcode
);
1716 /* Inverted condition w/ reversed operands. */
1717 rtxcode
= reverse_condition (rtxcode
);
1721 /* Reversed operand condition. */
1722 rtxcode
= swap_condition (rtxcode
);
1726 /* Normal condition. */
1728 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1729 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1730 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1731 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1732 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1733 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1734 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1735 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1736 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1737 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1742 output_addr_const (file
, x
);
1752 /* Print a memory address as an operand to reference that memory location.
1754 This is exactly the same as legitimate_address_p, except that it the prints
1755 addresses instead of recognizing them. */
1758 i960_print_operand_addr (file
, addr
)
1770 if (GET_CODE (addr
) == REG
)
1772 else if (CONSTANT_P (addr
))
1774 else if (GET_CODE (addr
) == PLUS
)
1778 op0
= XEXP (addr
, 0);
1779 op1
= XEXP (addr
, 1);
1781 if (GET_CODE (op0
) == REG
)
1784 if (GET_CODE (op1
) == REG
)
1786 else if (CONSTANT_P (op1
))
1791 else if (GET_CODE (op0
) == PLUS
)
1793 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1795 ireg
= XEXP (XEXP (op0
, 0), 0);
1796 scale
= XEXP (XEXP (op0
, 0), 1);
1797 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1799 breg
= XEXP (op0
, 1);
1805 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1807 breg
= XEXP (op0
, 0);
1808 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1810 ireg
= XEXP (op0
, 1);
1819 else if (GET_CODE (op0
) == MULT
)
1821 ireg
= XEXP (op0
, 0);
1822 scale
= XEXP (op0
, 1);
1823 if (GET_CODE (op1
) == REG
)
1825 else if (CONSTANT_P (op1
))
1833 else if (GET_CODE (addr
) == MULT
)
1835 ireg
= XEXP (addr
, 0);
1836 scale
= XEXP (addr
, 1);
1842 output_addr_const (file
, offset
);
1844 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1846 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1849 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1850 that is a valid memory address for an instruction.
1851 The MODE argument is the machine mode for the MEM expression
1852 that wants to use this address.
1854 On 80960, legitimate addresses are:
1856 disp (12 or 32 bit) ld foo,r0
1857 base + index ld (g0)[g1*1],r0
1858 base + displ ld 0xf00(g0),r0
1859 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1860 index*scale + base ld (g0)[g1*4],r0
1861 index*scale + displ ld 0xf00[g1*4],r0
1862 index*scale ld [g1*4],r0
1863 index + base + displ ld 0xf00(g0)[g1*1],r0
1865 In each case, scale can be 1, 2, 4, 8, or 16. */
1867 /* This is exactly the same as i960_print_operand_addr, except that
1868 it recognizes addresses instead of printing them.
1870 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1871 convert common non-canonical forms to canonical form so that they will
1874 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1875 where a register is valid. */
1877 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1878 ((GET_CODE (X) == REG \
1879 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1880 || (GET_CODE (X) == SUBREG \
1881 && GET_CODE (SUBREG_REG (X)) == REG \
1882 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1883 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1885 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1886 ((GET_CODE (X) == REG \
1887 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1888 || (GET_CODE (X) == SUBREG \
1889 && GET_CODE (SUBREG_REG (X)) == REG \
1890 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1891 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1894 legitimate_address_p (mode
, addr
, strict
)
1895 enum machine_mode mode
;
1899 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1901 else if (CONSTANT_P (addr
))
1903 else if (GET_CODE (addr
) == PLUS
)
1907 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1910 op0
= XEXP (addr
, 0);
1911 op1
= XEXP (addr
, 1);
1913 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1915 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1917 else if (CONSTANT_P (op1
))
1922 else if (GET_CODE (op0
) == PLUS
)
1924 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1926 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1927 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1930 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1931 && CONSTANT_P (op1
))
1936 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1938 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1939 && CONSTANT_P (op1
))
1947 else if (GET_CODE (op0
) == MULT
)
1949 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1950 && SCALE_TERM_P (XEXP (op0
, 1))))
1953 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1955 else if (CONSTANT_P (op1
))
1963 else if (GET_CODE (addr
) == MULT
)
1965 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1968 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1969 && SCALE_TERM_P (XEXP (addr
, 1)));
1975 /* Try machine-dependent ways of modifying an illegitimate address
1976 to be legitimate. If we find one, return the new, valid address.
1977 This macro is used in only one place: `memory_address' in explow.c.
1979 This converts some non-canonical addresses to canonical form so they
1980 can be recognized. */
1983 legitimize_address (x
, oldx
, mode
)
1986 enum machine_mode mode
;
1988 if (GET_CODE (x
) == SYMBOL_REF
)
1991 x
= copy_to_reg (x
);
1994 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1997 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1998 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1999 created by virtual register instantiation, register elimination, and
2000 similar optimizations. */
2001 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2002 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2003 x
= gen_rtx (PLUS
, Pmode
,
2004 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2005 XEXP (XEXP (x
, 1), 1));
2007 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2008 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2009 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2010 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2011 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2012 && CONSTANT_P (XEXP (x
, 1)))
2014 rtx constant
, other
;
2016 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2018 constant
= XEXP (x
, 1);
2019 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2021 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2023 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2024 other
= XEXP (x
, 1);
2030 x
= gen_rtx (PLUS
, Pmode
,
2031 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2032 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2033 plus_constant (other
, INTVAL (constant
)));
2040 /* Return the most stringent alignment that we are willing to consider
2041 objects of size SIZE and known alignment ALIGN as having. */
2044 i960_alignment (size
, align
)
2050 if (! TARGET_STRICT_ALIGN
)
2051 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2053 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2062 /* Modes for condition codes. */
2064 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2066 /* Modes for single-word (and smaller) quantities. */
2069 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2070 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2072 /* Modes for double-word (and smaller) quantities. */
2075 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2077 /* Modes for quad-word quantities. */
2078 #define T_MODES (~C_MODES)
2080 /* Modes for single-float quantities. */
2081 #define SF_MODES ((1 << (int) SFmode))
2083 /* Modes for double-float quantities. */
2084 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2086 /* Modes for quad-float quantities. */
2087 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2089 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
2090 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2091 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2092 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2093 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2095 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
2098 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2099 advantage of machine specific facts, such as knowing that the frame pointer
2100 is always 16 byte aligned. */
2103 i960_expr_alignment (x
, size
)
2112 switch (GET_CODE(x
))
2117 if ((align
& 0xf) == 0)
2119 else if ((align
& 0x7) == 0)
2121 else if ((align
& 0x3) == 0)
2123 else if ((align
& 0x1) == 0)
2130 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2131 i960_expr_alignment (XEXP (x
, 1), size
));
2135 /* If this is a valid program, objects are guaranteed to be
2136 correctly aligned for whatever size the reference actually is. */
2137 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2141 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2146 align
= i960_expr_alignment (XEXP (x
, 0));
2148 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2150 align
= align
<< INTVAL (XEXP (x
, 1));
2151 align
= MIN (align
, 16);
2156 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2157 i960_expr_alignment (XEXP (x
, 1), size
));
2159 align
= MIN (align
, 16);
2166 /* Return true if it is possible to reference both BASE and OFFSET, which
2167 have alignment at least as great as 4 byte, as if they had alignment valid
2168 for an object of size SIZE. */
2171 i960_improve_align (base
, offset
, size
)
2178 /* We have at least a word reference to the object, so we know it has to
2179 be aligned at least to 4 bytes. */
2181 i
= MIN (i960_expr_alignment (base
, 4),
2182 i960_expr_alignment (offset
, 4));
2186 /* We know the size of the request. If strict align is not enabled, we
2187 can guess that the alignment is OK for the requested size. */
2189 if (! TARGET_STRICT_ALIGN
)
2190 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2196 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2197 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2200 i960_si_ti (base
, offset
)
2204 return i960_improve_align (base
, offset
, 16);
2207 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2208 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2211 i960_si_di (base
, offset
)
2215 return i960_improve_align (base
, offset
, 8);
2218 /* Return raw values of size and alignment (in words) for the data
2219 type being accessed. These values will be rounded by the caller. */
2222 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2223 enum machine_mode mode
;
2230 /* Use formal alignment requirements of type being passed, except make
2231 it at least a word. If we don't have a type, this is a library call,
2232 and the parm has to be of scalar type. In this case, consider its
2233 formal alignment requirement to be its size in words. */
2235 if (mode
== BLKmode
)
2236 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2237 else if (mode
== VOIDmode
)
2239 /* End of parm list. */
2240 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2244 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2248 /* ??? This is a hack to properly correct the alignment of XFmode
2249 values without affecting anything else. */
2255 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2256 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2264 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2265 Any arg that is bigger than 4 words is placed on the stack and all
2266 subsequent arguments are placed on the stack.
2268 Additionally, parameters with an alignment requirement stronger than
2269 a word must be aligned appropriately. Note that this means that a
2270 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2271 passed in an odd/even register pair. */
2273 /* Update CUM to advance past an argument described by MODE and TYPE. */
2276 i960_function_arg_advance (cum
, mode
, type
, named
)
2277 CUMULATIVE_ARGS
*cum
;
2278 enum machine_mode mode
;
2284 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2286 if (size
> 4 || cum
->ca_nstackparms
!= 0
2287 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2288 || MUST_PASS_IN_STACK (mode
, type
))
2290 /* Indicate that all the registers are in use, even if all are not,
2291 so va_start will compute the right value. */
2292 cum
->ca_nregparms
= NPARM_REGS
;
2293 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2296 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2299 /* Return the register that the argument described by MODE and TYPE is
2300 passed in, or else return 0 if it is passed on the stack. */
2303 i960_function_arg (cum
, mode
, type
, named
)
2304 CUMULATIVE_ARGS
*cum
;
2305 enum machine_mode mode
;
2312 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2314 if (size
> 4 || cum
->ca_nstackparms
!= 0
2315 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2316 || MUST_PASS_IN_STACK (mode
, type
))
2318 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2323 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2324 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2330 /* Floating-point support. */
2333 i960_output_long_double (file
, value
)
2335 REAL_VALUE_TYPE value
;
2340 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2341 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2344 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2345 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2346 fprintf (file
, "\t.word\t0x0\n");
2350 i960_output_double (file
, value
)
2352 REAL_VALUE_TYPE value
;
2357 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2358 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2360 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2361 value_long
[0], dstr
, value_long
[1]);
2365 i960_output_float (file
, value
)
2367 REAL_VALUE_TYPE value
;
2372 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2373 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2375 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2378 /* Return the number of bits that an object of size N bytes is aligned to. */
2381 i960_object_bytes_bitalign (n
)
2385 else if (n
> 4) n
= 64;
2386 else if (n
> 2) n
= 32;
2387 else if (n
> 1) n
= 16;
2393 /* Compute the alignment for an aggregate type TSIZE.
2394 Alignment is MAX (greatest member alignment,
2395 MIN (pragma align, structure size alignment)). */
2398 i960_round_align (align
, tsize
)
2404 if (TREE_CODE (tsize
) != INTEGER_CST
)
2407 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2409 /* Handle #pragma align. */
2410 if (new_align
> i960_maxbitalignment
)
2411 new_align
= i960_maxbitalignment
;
2413 if (align
< new_align
)
2419 /* Do any needed setup for a varargs function. For the i960, we must
2420 create a register parameter block if one doesn't exist, and then copy
2421 all register parameters to memory. */
2424 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2425 CUMULATIVE_ARGS
*cum
;
2426 enum machine_mode mode
;
2431 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2432 int first_reg
= cum
->ca_nregparms
;
2434 /* Copy only unnamed register arguments to memory. If there are
2435 any stack parms, there are no unnamed arguments in registers, and
2436 an argument block was already allocated by the caller.
2437 Remember that any arg bigger than 4 words is passed on the stack as
2438 are all subsequent args.
2440 If there are no stack arguments but there are exactly NPARM_REGS
2441 registers, either there were no extra arguments or the caller
2442 allocated an argument block. */
2444 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2446 rtx label
= gen_label_rtx ();
2449 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2450 and we need to allocate a chunk to save the registers (if any
2451 arguments were passed on the stack the caller would allocate the
2452 48 bytes as well). We must allocate all 48 bytes (12*4) because
2453 va_start assumes it. */
2454 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2455 emit_jump_insn (gen_bne (label
));
2456 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2457 stack_pointer_rtx
));
2458 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2459 memory_address (SImode
,
2460 plus_constant (stack_pointer_rtx
,
2464 /* ??? Note that we unnecessarily store one extra register for stdarg
2465 fns. We could optimize this, but it's kept as for now. */
2466 regblock
= gen_rtx (MEM
, BLKmode
,
2467 plus_constant (arg_pointer_rtx
,
2469 move_block_from_reg (first_reg
, regblock
,
2470 NPARM_REGS
- first_reg
,
2471 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2475 /* Calculate the final size of the reg parm stack space for the current
2476 function, based on how many bytes would be allocated on the stack. */
2479 i960_final_reg_parm_stack_space (const_size
, var_size
)
2483 if (var_size
|| const_size
> 48)
2489 /* Calculate the size of the reg parm stack space. This is a bit complicated
2493 i960_reg_parm_stack_space (fndecl
)
2496 /* In this case, we are called from emit_library_call, and we don't need
2497 to pretend we have more space for parameters than what's apparent. */
2501 /* In this case, we are called from locate_and_pad_parms when we're
2502 not IN_REGS, so we have an arg block. */
2503 if (fndecl
!= current_function_decl
)
2506 /* Otherwise, we have an arg block if the current function has more than
2507 48 bytes of parameters. */
2508 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2514 /* Return the register class of a scratch register needed to copy IN into
2515 or out of a register in CLASS in MODE. If it can be done directly,
2516 NO_REGS is returned. */
2519 secondary_reload_class (class, mode
, in
)
2520 enum reg_class
class;
2521 enum machine_mode mode
;
2526 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2527 regno
= true_regnum (in
);
2529 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2530 LOCAL_OR_GLOBAL_REGS into anything. */
2531 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2532 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2535 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2536 if (class == FP_REGS
2537 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2538 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2541 return LOCAL_OR_GLOBAL_REGS
;
2544 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2545 function unit it executed on. */
2547 /* ??? This would make more sense as an attribute. */
2550 i960_scan_opcode (p
)
2562 /* Ret is not actually of type REG, but it won't matter, because no
2563 insn will ever follow it. */
2566 i960_last_insn_type
= I_TYPE_REG
;
2570 if (p
[1] == 'x' || p
[3] == 'x')
2571 i960_last_insn_type
= I_TYPE_MEM
;
2572 i960_last_insn_type
= I_TYPE_CTRL
;
2577 i960_last_insn_type
= I_TYPE_CTRL
;
2584 i960_last_insn_type
= I_TYPE_MEM
;
2586 i960_last_insn_type
= I_TYPE_CTRL
;
2588 else if (p
[1] == 'm')
2591 i960_last_insn_type
= I_TYPE_REG
;
2592 else if (p
[4] == 'b' || p
[4] == 'j')
2593 i960_last_insn_type
= I_TYPE_CTRL
;
2595 i960_last_insn_type
= I_TYPE_REG
;
2598 i960_last_insn_type
= I_TYPE_REG
;
2602 i960_last_insn_type
= I_TYPE_MEM
;
2607 i960_last_insn_type
= I_TYPE_MEM
;
2609 i960_last_insn_type
= I_TYPE_REG
;