1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. Also, it needs to be rewritten to accept
91 a stream instead of a string for GCC 2. */
100 if ((i
= sscanf (str
, " align %d", &align
)) == 1)
103 case 0: /* Return to last alignment. */
104 align
= i960_last_maxbitalignment
/ 8;
106 case 16: /* Byte alignments. */
111 i960_last_maxbitalignment
= i960_maxbitalignment
;
112 i960_maxbitalignment
= align
* 8;
115 default: /* Unknown, silently ignore. */
119 /* NOTE: ic960 R3.0 pragma align definition:
121 #pragma align [(size)] | (identifier=size[,...])
122 #pragma noalign [(identifier)[,...]]
124 (all parens are optional)
126 - size is [1,2,4,8,16]
127 - noalign means size==1
128 - applies only to component elements of a struct (and union?)
129 - identifier applies to structure tag (only)
130 - missing identifier means next struct
132 - alignment rules for bitfields need more investigation */
134 /* Should be pragma 'far' or equivalent for callx/balx here. */
138 /* Initialize variables before compiling any files. */
143 if (TARGET_IC_COMPAT2_0
)
145 i960_maxbitalignment
= 8;
146 i960_last_maxbitalignment
= 128;
150 i960_maxbitalignment
= 128;
151 i960_last_maxbitalignment
= 8;
155 /* Return true if OP can be used as the source of an fp move insn. */
158 fpmove_src_operand (op
, mode
)
160 enum machine_mode mode
;
162 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
166 /* Return true if OP is a register or zero. */
169 reg_or_zero_operand (op
, mode
)
171 enum machine_mode mode
;
173 return register_operand (op
, mode
) || op
== const0_rtx
;
177 /* Return truth value of whether OP can be used as an operands in a three
178 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
181 arith_operand (op
, mode
)
183 enum machine_mode mode
;
185 return (register_operand (op
, mode
) || literal (op
, mode
));
188 /* Return true if OP is a register or a valid floating point literal. */
191 fp_arith_operand (op
, mode
)
193 enum machine_mode mode
;
195 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
198 /* Return true is OP is a register or a valid signed integer literal. */
201 signed_arith_operand (op
, mode
)
203 enum machine_mode mode
;
205 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
208 /* Return truth value of whether OP is a integer which fits the
209 range constraining immediate operands in three-address insns. */
214 enum machine_mode mode
;
216 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
219 /* Return true if OP is a float constant of 1. */
222 fp_literal_one (op
, mode
)
224 enum machine_mode mode
;
226 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
229 /* Return true if OP is a float constant of 0. */
232 fp_literal_zero (op
, mode
)
234 enum machine_mode mode
;
236 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
239 /* Return true if OP is a valid floating point literal. */
244 enum machine_mode mode
;
246 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
249 /* Return true if OP is a valid signed immediate constant. */
252 signed_literal(op
, mode
)
254 enum machine_mode mode
;
256 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
259 /* Return truth value of statement that OP is a symbolic memory
260 operand of mode MODE. */
263 symbolic_memory_operand (op
, mode
)
265 enum machine_mode mode
;
267 if (GET_CODE (op
) == SUBREG
)
268 op
= SUBREG_REG (op
);
269 if (GET_CODE (op
) != MEM
)
272 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
273 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
276 /* Return truth value of whether OP is EQ or NE. */
281 enum machine_mode mode
;
283 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
286 /* OP is an integer register or a constant. */
289 arith32_operand (op
, mode
)
291 enum machine_mode mode
;
293 if (register_operand (op
, mode
))
295 return (CONSTANT_P (op
));
298 /* Return true if OP is an integer constant which is a power of 2. */
301 power2_operand (op
,mode
)
303 enum machine_mode mode
;
305 if (GET_CODE (op
) != CONST_INT
)
308 return exact_log2 (INTVAL (op
)) >= 0;
311 /* Return true if OP is an integer constant which is the complement of a
315 cmplpower2_operand (op
, mode
)
317 enum machine_mode mode
;
319 if (GET_CODE (op
) != CONST_INT
)
322 return exact_log2 (~ INTVAL (op
)) >= 0;
325 /* If VAL has only one bit set, return the index of that bit. Otherwise
334 for (i
= 0; val
!= 0; i
++, val
>>= 1)
346 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
347 The return value indicates how many consecutive non-zero bits exist
348 if this is a mask. This is the same as the next function, except that
349 it does not indicate what the start and stop bit positions are. */
355 register int start
, end
, i
;
358 for (i
= 0; val
!= 0; val
>>= 1, i
++)
368 /* Still looking for the first bit. */
372 /* We've seen the start of a bit sequence, and now a zero. There
373 must be more one bits, otherwise we would have exited the loop.
374 Therefore, it is not a mask. */
379 /* The bit string has ones from START to END bit positions only. */
380 return end
- start
+ 1;
383 /* If VAL is a mask, then return nonzero, with S set to the starting bit
384 position and E set to the ending bit position of the mask. The return
385 value indicates how many consecutive bits exist in the mask. This is
386 the same as the previous function, except that it also indicates the
387 start and end bit positions of the mask. */
394 register int start
, end
, i
;
398 for (i
= 0; val
!= 0; val
>>= 1, i
++)
409 /* Still looking for the first bit. */
413 /* We've seen the start of a bit sequence, and now a zero. There
414 must be more one bits, otherwise we would have exited the loop.
415 Therefor, it is not a mask. */
424 /* The bit string has ones from START to END bit positions only. */
427 return ((start
< 0) ? 0 : end
- start
+ 1);
430 /* Return the machine mode to use for a comparison. */
433 select_cc_mode (op
, x
)
437 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
442 /* X and Y are two things to compare using CODE. Emit the compare insn and
443 return the rtx for register 36 in the proper mode. */
446 gen_compare_reg (code
, x
, y
)
451 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
452 enum machine_mode mode
453 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
457 if (! arith_operand (x
, mode
))
458 x
= force_reg (SImode
, x
);
459 if (! arith_operand (y
, mode
))
460 y
= force_reg (SImode
, y
);
463 cc_reg
= gen_rtx (REG
, ccmode
, 36);
464 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
465 gen_rtx (COMPARE
, ccmode
, x
, y
)));
470 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
471 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
472 are 4. Indexed addresses are cost 6. */
474 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
477 i960_address_cost (x
)
481 /* Handled before calling here. */
482 if (GET_CODE (x
) == REG
)
485 if (GET_CODE (x
) == PLUS
)
487 rtx base
= XEXP (x
, 0);
488 rtx offset
= XEXP (x
, 1);
490 if (GET_CODE (base
) == SUBREG
)
491 base
= SUBREG_REG (base
);
492 if (GET_CODE (offset
) == SUBREG
)
493 offset
= SUBREG_REG (offset
);
495 if (GET_CODE (base
) == REG
)
497 if (GET_CODE (offset
) == REG
)
499 if (GET_CODE (offset
) == CONST_INT
)
501 if ((unsigned)INTVAL (offset
) < 2047)
505 if (CONSTANT_P (offset
))
508 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
511 /* This is an invalid address. The return value doesn't matter, but
512 for convenience we make this more expensive than anything else. */
515 if (GET_CODE (x
) == MULT
)
518 /* Symbol_refs and other unrecognized addresses are cost 4. */
522 /* Emit insns to move operands[1] into operands[0].
524 Return 1 if we have written out everything that needs to be done to
525 do the move. Otherwise, return 0 and the caller will emit the move
529 emit_move_sequence (operands
, mode
)
531 enum machine_mode mode
;
533 register rtx operand0
= operands
[0];
534 register rtx operand1
= operands
[1];
536 /* We can only store registers to memory. */
538 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
539 operands
[1] = force_reg (mode
, operand1
);
544 /* Emit insns to load a constant. Uses several strategies to try to use
545 as few insns as possible. */
548 i960_output_ldconst (dst
, src
)
549 register rtx dst
, src
;
552 register unsigned rsrc2
;
553 enum machine_mode mode
= GET_MODE (dst
);
555 union { long l
[2]; double d
; } x
;
557 operands
[0] = operands
[2] = dst
;
558 operands
[1] = operands
[3] = src
;
560 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
561 must be a ldconst insn. */
563 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
565 output_asm_insn ("ldconst %1,%0", operands
);
568 else if (mode
== DFmode
)
572 if (fp_literal_zero (src
, DFmode
))
575 split_double (src
, &first
, &second
);
577 output_asm_insn ("# ldconst %1,%0",operands
);
579 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
581 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
583 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
584 operands
[1] = second
;
585 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
589 else if (mode
== TImode
)
591 /* ??? This is currently not handled at all. */
594 /* Note: lowest order word goes in lowest numbered reg. */
595 rsrc1
= INTVAL (src
);
596 if (rsrc1
>= 0 && rsrc1
< 32)
599 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
600 /* Go pick up the low-order word. */
602 else if (mode
== DImode
)
604 rtx upperhalf
, lowerhalf
, xoperands
[2];
607 if (GET_CODE (src
) == CONST_DOUBLE
)
609 upperhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_HIGH (src
));
610 lowerhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_LOW (src
));
612 else if (GET_CODE (src
) == CONST_INT
)
615 upperhalf
= INTVAL (src
) < 0 ? constm1_rtx
: const0_rtx
;
620 /* Note: lowest order word goes in lowest numbered reg. */
621 /* Numbers from 0 to 31 can be handled with a single insn. */
622 rsrc1
= INTVAL (lowerhalf
);
623 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
626 /* Output the upper half with a recursive call. */
627 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
628 xoperands
[1] = upperhalf
;
629 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
631 /* The lower word is emitted as normally. */
633 else if (mode
== SFmode
)
638 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
639 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
641 output_asm_insn ("# ldconst %1,%0",operands
);
642 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
643 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
644 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
650 rsrc1
= INTVAL (src
);
656 else if (mode
== HImode
)
665 /* ldconst 0..31,X -> mov 0..31,X */
668 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
673 /* ldconst 32..63,X -> add 31,nn,X */
676 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
678 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
679 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
685 /* ldconst -1..-31 -> sub 0,0..31,X */
688 /* return 'sub -(%1),0,%0' */
689 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
690 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
694 /* ldconst -32 -> not 31,X */
697 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
698 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
703 /* If const is a single bit. */
704 if (bitpos (rsrc1
) >= 0)
706 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
707 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
711 /* If const is a bit string of less than 6 bits (1..31 shifted). */
716 if (bitstr (rsrc1
, &s
, &e
) < 6)
718 rsrc2
= ((unsigned int) rsrc1
) >> s
;
719 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
720 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
721 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
726 /* Unimplemented cases:
727 const is in range 0..31 but rotated around end of word:
728 ror 31,3,g0 -> ldconst 0xe0000003,g0
730 and any 2 instruction cases that might be worthwhile */
732 output_asm_insn ("ldconst %1,%0", operands
);
736 /* Determine if there is an opportunity for a bypass optimization.
737 Bypass succeeds on the 960K* if the destination of the previous
738 instruction is the second operand of the current instruction.
739 Bypass always succeeds on the C*.
741 Return 1 if the pattern should interchange the operands.
743 CMPBR_FLAG is true if this is for a compare-and-branch insn.
744 OP1 and OP2 are the two source operands of a 3 operand insn. */
747 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
748 register rtx insn
, op1
, op2
;
751 register rtx prev_insn
, prev_dest
;
756 /* Can't do this if op1 isn't a register. */
760 /* Can't do this for a compare-and-branch if both ops aren't regs. */
761 if (cmpbr_flag
&& ! REG_P (op2
))
764 prev_insn
= prev_real_insn (insn
);
766 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
767 && GET_CODE (PATTERN (prev_insn
)) == SET
)
769 prev_dest
= SET_DEST (PATTERN (prev_insn
));
770 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
771 || (GET_CODE (prev_dest
) == SUBREG
772 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
773 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
779 /* Output the code which declares the function name. This also handles
780 leaf routines, which have special requirements, and initializes some
784 i960_function_name_declare (file
, name
, fndecl
)
793 /* Increment global return label. */
797 /* Compute whether tail calls and leaf routine optimizations can be performed
798 for this function. */
810 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
811 argblock, because argblock uses g14 implicitly. */
813 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
819 /* See if caller passes in an address to return value. */
821 if (aggregate_value_p (DECL_RESULT (fndecl
)))
827 /* Can not use tail calls or make this a leaf routine if there is a non
830 if (get_frame_size () != 0)
833 /* I don't understand this condition, and do not think that it is correct.
834 Apparently this is just checking whether the frame pointer is used, and
835 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
838 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
839 if (GET_CODE (insn
) == INSN
840 && reg_mentioned_p (frame_pointer_rtx
, insn
))
846 /* Check for CALL insns. Can not be a leaf routine if there are any. */
849 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
850 if (GET_CODE (insn
) == CALL_INSN
)
856 /* Can not be a leaf routine if any non-call clobbered registers are
857 used in this function. */
860 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
861 if (regs_ever_live
[i
]
862 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
864 /* Global registers. */
865 if (i
< 16 && i
> 7 && i
!= 13)
867 /* Local registers. */
872 /* Now choose a leaf return register, if we can find one, and if it is
873 OK for this to be a leaf routine. */
875 i960_leaf_ret_reg
= -1;
877 if (optimize
&& leaf_proc_ok
)
879 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
880 if (regs_ever_live
[i
] == 0)
882 i960_leaf_ret_reg
= i
;
883 regs_ever_live
[i
] = 1;
888 /* Do this after choosing the leaf return register, so it will be listed
889 if one was chosen. */
891 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
892 fprintf (file
, "\t# Registers used: ");
894 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
896 if (regs_ever_live
[i
])
898 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
900 if (i
> 15 && j
== 0)
902 fprintf (file
,"\n\t#\t\t ");
908 fprintf (file
, "\n");
910 if (i960_leaf_ret_reg
>= 0)
912 /* Make it a leaf procedure. */
914 if (TREE_PUBLIC (fndecl
))
915 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
917 fprintf (file
, "\t.leafproc\t");
918 assemble_name (file
, name
);
919 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
920 ASM_OUTPUT_LABEL (file
, name
);
921 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
922 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
923 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
927 fprintf (file
, "\tlda 0,g14\n");
928 i960_last_insn_type
= I_TYPE_MEM
;
932 fprintf (file
, "\tmov 0,g14\n");
933 i960_last_insn_type
= I_TYPE_REG
;
938 ASM_OUTPUT_LABEL (file
, name
);
939 i960_last_insn_type
= I_TYPE_CTRL
;
943 /* Compute and return the frame size. */
946 compute_frame_size (size
)
950 int outgoing_args_size
= current_function_outgoing_args_size
;
952 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
953 as size is concerned. */
954 actual_fsize
= (size
+ 15) & -16;
955 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
960 /* Output code for the function prologue. */
963 i960_function_prologue (file
, size
)
967 register int i
, j
, nr
;
970 int actual_fsize
, offset
;
972 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
974 int regs
[FIRST_PSEUDO_REGISTER
];
976 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
977 if (regs_ever_live
[i
]
978 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
981 /* Count global registers that need saving. */
988 epilogue_string
[0] = '\0';
990 if (profile_flag
|| profile_block_flag
)
992 /* When profiling, we may use registers 20 to 27 to save arguments, so
993 they can't be used here for saving globals. J is the number of
994 argument registers the mcount call will save. */
995 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
998 for (i
= 20; i
<= j
+ 20; i
++)
1002 /* First look for local registers to save globals in. */
1003 for (i
= 0; i
< 16; i
++)
1008 /* Start at r4, not r3. */
1009 for (j
= 20; j
< 32; j
++)
1016 regs_ever_live
[j
] = 1;
1018 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1019 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1024 regs_ever_live
[j
+1] = 1;
1026 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1027 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1032 regs_ever_live
[j
+2] = 1;
1034 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1039 regs_ever_live
[j
+3] = 1;
1042 fprintf (file
, "\tmov%s %s,%s\n",
1045 (nr
== 2) ? "l" : ""),
1046 reg_names
[i
], reg_names
[j
]);
1047 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1050 (nr
== 2) ? "l" : ""),
1051 reg_names
[j
], reg_names
[i
]);
1052 strcat (epilogue_string
, tmpstr
);
1060 /* N_iregs is now the number of global registers that haven't been saved
1063 rsize
= (n_iregs
* 4);
1064 actual_fsize
= compute_frame_size (size
) + rsize
;
1066 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1067 size up to the nearest multiple of 16. I don't know whether this is
1068 necessary, or even desirable.
1070 The frame pointer must be aligned, but the call instruction takes care of
1071 that. If we leave the stack pointer unaligned, we may save a little on
1072 dynamic stack allocation. And we don't lose, at least according to the
1074 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1077 /* Allocate space for register save and locals. */
1078 if (actual_fsize
> 0)
1080 if (actual_fsize
< 32)
1081 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1083 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1086 /* Take hardware register save area created by the call instruction
1087 into account, but store them before the argument block area. */
1088 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1089 /* Save registers on stack if needed. */
1090 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1097 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1100 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1104 if (nr
== 3 && regs
[i
+3] == -1)
1107 fprintf (file
,"\tst%s %s,%d(fp)\n",
1110 (nr
== 2) ? "l" : ""),
1111 reg_names
[i
], offset
);
1112 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1115 (nr
== 2) ? "l" : ""),
1116 offset
, reg_names
[i
]);
1117 strcat (epilogue_string
, tmpstr
);
1123 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1126 fprintf (file
, "\t#Prologue stats:\n");
1127 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1130 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1132 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1134 fprintf (file
, "\t#End Prologue#\n");
1137 /* Output code for the function profiler. */
1140 output_function_profiler (file
, labelno
)
1144 /* The last used parameter register. */
1146 int i
, j
, increment
;
1147 int varargs_stdarg_function
1148 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1150 /* Figure out the last used parameter register. The proper thing to do
1151 is to walk incoming args of the function. A function might have live
1152 parameter registers even if it has no incoming args. Note that we
1153 don't have to save parameter registers g8 to g11 because they are
1156 /* See also output_function_prologue, which tries to use local registers
1157 for preserved call-saved global registers. */
1159 for (last_parm_reg
= 7;
1160 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1164 /* Save parameter registers in regs r4 (20) to r11 (27). */
1166 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1168 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1170 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1172 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1177 fprintf (file
, "\tmov%s g%d,r%d\n",
1178 (increment
== 4 ? "q" : increment
== 3 ? "t"
1179 : increment
== 2 ? "l": ""), i
, j
);
1182 /* If this function uses the arg pointer, then save it in r3 and then
1185 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1186 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1188 /* Load location address into g0 and call mcount. */
1190 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1192 /* If this function uses the arg pointer, restore it. */
1194 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1195 fprintf (file
, "\tmov r3,g14\n");
1197 /* Restore parameter registers. */
1199 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1201 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1203 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1205 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1210 fprintf (file
, "\tmov%s r%d,g%d\n",
1211 (increment
== 4 ? "q" : increment
== 3 ? "t"
1212 : increment
== 2 ? "l": ""), j
, i
);
1216 /* Output code for the function epilogue. */
1219 i960_function_epilogue (file
, size
)
1223 if (i960_leaf_ret_reg
>= 0)
1225 fprintf (file
, "LR%d: ret\n", ret_label
);
1229 if (*epilogue_string
== 0)
1233 /* Emit a return insn, but only if control can fall through to here. */
1235 tmp
= get_last_insn ();
1238 if (GET_CODE (tmp
) == BARRIER
)
1240 if (GET_CODE (tmp
) == CODE_LABEL
)
1242 if (GET_CODE (tmp
) == JUMP_INSN
)
1244 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1248 if (GET_CODE (tmp
) == NOTE
)
1250 tmp
= PREV_INSN (tmp
);
1255 fprintf (file
, "LR%d: ret\n", ret_label
);
1259 fprintf (file
, "LR%d:\n", ret_label
);
1261 fprintf (file
, "\t#EPILOGUE#\n");
1263 /* Output the string created by the prologue which will restore all
1264 registers saved by the prologue. */
1266 if (epilogue_string
[0] != '\0')
1267 fprintf (file
, "%s", epilogue_string
);
1269 /* Must clear g14 on return. */
1271 if (current_function_args_size
!= 0
1272 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1273 fprintf (file
, "\tmov 0,g14\n");
1275 fprintf (file
, "\tret\n");
1276 fprintf (file
, "\t#End Epilogue#\n");
1279 /* Output code for a call insn. */
1282 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1283 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1285 int argsize
= INTVAL (argsize_rtx
);
1286 rtx nexti
= next_real_insn (insn
);
1288 int varargs_stdarg_function
1289 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1291 operands
[0] = target
;
1292 operands
[1] = arg_pointer
;
1294 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1295 output_asm_insn ("mov g14,r3", operands
);
1298 output_asm_insn ("lda %a1,g14", operands
);
1299 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1300 output_asm_insn ("mov 0,g14", operands
);
1302 /* The code used to assume that calls to SYMBOL_REFs could not be more
1303 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1304 feature is now implemented by relaxing in the GNU linker. It can convert
1305 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1307 /* Nexti could be zero if the called routine is volatile. */
1308 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1309 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1311 /* Delete following return insn. */
1312 if (nexti
&& no_labels_between_p (insn
, nexti
))
1313 delete_insn (nexti
);
1314 output_asm_insn ("bx %0", operands
);
1315 return "# notreached";
1318 output_asm_insn ("callx %0", operands
);
1320 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1321 output_asm_insn ("mov r3,g14", operands
);
1326 /* Output code for a return insn. */
1329 i960_output_ret_insn (insn
)
1332 static char lbuf
[20];
1334 if (*epilogue_string
!= 0)
1336 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1339 sprintf (lbuf
, "b LR%d", ret_label
);
1343 if (current_function_args_size
!= 0
1344 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1345 output_asm_insn ("mov 0,g14", 0);
1347 if (i960_leaf_ret_reg
>= 0)
1349 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1356 /* Return a character string representing the branch prediction
1357 opcode to be tacked on an instruction. This must at least
1358 return a null string. */
1361 i960_br_predict_opcode (lab_ref
, insn
)
1364 if (TARGET_BRANCH_PREDICT
)
1366 unsigned long label_uid
;
1368 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1369 label_uid
= INSN_UID (lab_ref
);
1370 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1371 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1375 /* If not optimizing, then the insn_addresses array will not be
1376 valid. In this case, always return ".t" since most branches
1377 are taken. If optimizing, return .t for backward branches
1378 and .f for forward branches. */
1380 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1389 /* Print the operand represented by rtx X formatted by code CODE. */
1392 i960_print_operand (file
, x
, code
)
1397 enum rtx_code rtxcode
= GET_CODE (x
);
1404 /* Second reg of a double. */
1405 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1409 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1417 else if (rtxcode
== MEM
)
1419 output_address (XEXP (x
, 0));
1422 else if (rtxcode
== CONST_INT
)
1424 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1425 fprintf (file
, "0x%x", INTVAL (x
));
1427 fprintf (file
, "%d", INTVAL (x
));
1430 else if (rtxcode
== CONST_DOUBLE
)
1434 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1436 fprintf (file
, "0f0.0");
1439 else if (x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))
1441 fprintf (file
, "0f1.0");
1445 /* This better be a comment. */
1446 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1447 fprintf (file
, "%#g", d
);
1454 /* Branch or jump, depending on assembler. */
1455 if (TARGET_ASM_COMPAT
)
1462 /* Sign of condition. */
1463 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1464 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1466 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1467 || (rtxcode
== GE
) || (rtxcode
== LE
))
1474 /* Inverted condition. */
1475 rtxcode
= reverse_condition (rtxcode
);
1479 /* Inverted condition w/ reversed operands. */
1480 rtxcode
= reverse_condition (rtxcode
);
1484 /* Reversed operand condition. */
1485 rtxcode
= swap_condition (rtxcode
);
1489 /* Normal condition. */
1491 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1492 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1493 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1494 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1495 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1496 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1497 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1498 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1499 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1500 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1505 output_addr_const (file
, x
);
1515 /* Print a memory address as an operand to reference that memory location.
1517 This is exactly the same as legitimate_address_p, except that it the prints
1518 addresses instead of recognizing them. */
1521 i960_print_operand_addr (file
, addr
)
1533 if (GET_CODE (addr
) == REG
)
1535 else if (CONSTANT_P (addr
))
1537 else if (GET_CODE (addr
) == PLUS
)
1541 op0
= XEXP (addr
, 0);
1542 op1
= XEXP (addr
, 1);
1544 if (GET_CODE (op0
) == REG
)
1547 if (GET_CODE (op1
) == REG
)
1549 else if (CONSTANT_P (op1
))
1554 else if (GET_CODE (op0
) == PLUS
)
1556 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1558 ireg
= XEXP (XEXP (op0
, 0), 0);
1559 scale
= XEXP (XEXP (op0
, 0), 1);
1560 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1562 breg
= XEXP (op0
, 1);
1568 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1570 breg
= XEXP (op0
, 0);
1571 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1573 ireg
= XEXP (op0
, 1);
1582 else if (GET_CODE (op0
) == MULT
)
1584 ireg
= XEXP (op0
, 0);
1585 scale
= XEXP (op0
, 1);
1586 if (GET_CODE (op1
) == REG
)
1588 else if (CONSTANT_P (op1
))
1596 else if (GET_CODE (addr
) == MULT
)
1598 ireg
= XEXP (addr
, 0);
1599 scale
= XEXP (addr
, 1);
1605 output_addr_const (file
, offset
);
1607 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1609 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1612 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1613 that is a valid memory address for an instruction.
1614 The MODE argument is the machine mode for the MEM expression
1615 that wants to use this address.
1617 On 80960, legitimate addresses are:
1619 disp (12 or 32 bit) ld foo,r0
1620 base + index ld (g0)[g1*1],r0
1621 base + displ ld 0xf00(g0),r0
1622 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1623 index*scale + base ld (g0)[g1*4],r0
1624 index*scale + displ ld 0xf00[g1*4],r0
1625 index*scale ld [g1*4],r0
1626 index + base + displ ld 0xf00(g0)[g1*1],r0
1628 In each case, scale can be 1, 2, 4, 8, or 16. */
1630 /* This is exactly the same as i960_print_operand_addr, except that
1631 it recognizes addresses instead of printing them.
1633 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1634 convert common non-canonical forms to canonical form so that they will
1637 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1638 where a register is valid. */
1640 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1641 ((GET_CODE (X) == REG \
1642 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1643 || (GET_CODE (X) == SUBREG \
1644 && GET_CODE (SUBREG_REG (X)) == REG \
1645 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1646 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1648 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1649 ((GET_CODE (X) == REG \
1650 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1651 || (GET_CODE (X) == SUBREG \
1652 && GET_CODE (SUBREG_REG (X)) == REG \
1653 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1654 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1657 legitimate_address_p (mode
, addr
, strict
)
1658 enum machine_mode mode
;
1662 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1664 else if (CONSTANT_P (addr
))
1666 else if (GET_CODE (addr
) == PLUS
)
1670 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1673 op0
= XEXP (addr
, 0);
1674 op1
= XEXP (addr
, 1);
1676 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1678 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1680 else if (CONSTANT_P (op1
))
1685 else if (GET_CODE (op0
) == PLUS
)
1687 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1689 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1690 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1693 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1694 && CONSTANT_P (op1
))
1699 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1701 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1702 && CONSTANT_P (op1
))
1710 else if (GET_CODE (op0
) == MULT
)
1712 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1713 && SCALE_TERM_P (XEXP (op0
, 1))))
1716 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1718 else if (CONSTANT_P (op1
))
1726 else if (GET_CODE (addr
) == MULT
)
1728 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1731 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1732 && SCALE_TERM_P (XEXP (addr
, 1)));
1738 /* Try machine-dependent ways of modifying an illegitimate address
1739 to be legitimate. If we find one, return the new, valid address.
1740 This macro is used in only one place: `memory_address' in explow.c.
1742 This converts some non-canonical addresses to canonical form so they
1743 can be recognized. */
1746 legitimize_address (x
, oldx
, mode
)
1749 enum machine_mode mode
;
1751 if (GET_CODE (x
) == SYMBOL_REF
)
1754 x
= copy_to_reg (x
);
1757 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1760 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1761 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1762 created by virtual register instantiation, register elimination, and
1763 similar optimizations. */
1764 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1765 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1766 x
= gen_rtx (PLUS
, Pmode
,
1767 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1768 XEXP (XEXP (x
, 1), 1));
1770 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1771 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1772 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1773 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1774 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1775 && CONSTANT_P (XEXP (x
, 1)))
1777 rtx constant
, other
;
1779 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1781 constant
= XEXP (x
, 1);
1782 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1784 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1786 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1787 other
= XEXP (x
, 1);
1793 x
= gen_rtx (PLUS
, Pmode
,
1794 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1795 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1796 plus_constant (other
, INTVAL (constant
)));
1803 /* Return the most stringent alignment that we are willing to consider
1804 objects of size SIZE and known alignment ALIGN as having. */
1807 i960_alignment (size
, align
)
1813 if (! TARGET_STRICT_ALIGN
)
1814 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1816 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1825 /* Modes for condition codes. */
1827 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1829 /* Modes for single-word (and smaller) quantities. */
1832 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1833 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1835 /* Modes for double-word (and smaller) quantities. */
1838 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1840 /* Modes for quad-word quantities. */
1841 #define T_MODES (~C_MODES)
1843 /* Modes for single-float quantities. */
1844 #define SF_MODES ((1 << (int) SFmode))
1846 /* Modes for double-float quantities. */
1847 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1849 /* Modes for quad-float quantities. */
1850 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1852 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1853 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1854 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1855 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1856 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1858 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1861 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1862 advantage of machine specific facts, such as knowing that the frame pointer
1863 is always 16 byte aligned. */
1866 i960_expr_alignment (x
, size
)
1875 switch (GET_CODE(x
))
1880 if ((align
& 0xf) == 0)
1882 else if ((align
& 0x7) == 0)
1884 else if ((align
& 0x3) == 0)
1886 else if ((align
& 0x1) == 0)
1893 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1894 i960_expr_alignment (XEXP (x
, 1), size
));
1898 /* If this is a valid program, objects are guaranteed to be
1899 correctly aligned for whatever size the reference actually is. */
1900 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1904 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1909 align
= i960_expr_alignment (XEXP (x
, 0));
1911 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1913 align
= align
<< INTVAL (XEXP (x
, 1));
1914 align
= MIN (align
, 16);
1919 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1920 i960_expr_alignment (XEXP (x
, 1), size
));
1922 align
= MIN (align
, 16);
1929 /* Return true if it is possible to reference both BASE and OFFSET, which
1930 have alignment at least as great as 4 byte, as if they had alignment valid
1931 for an object of size SIZE. */
1934 i960_improve_align (base
, offset
, size
)
1941 /* We have at least a word reference to the object, so we know it has to
1942 be aligned at least to 4 bytes. */
1944 i
= MIN (i960_expr_alignment (base
, 4),
1945 i960_expr_alignment (offset
, 4));
1949 /* We know the size of the request. If strict align is not enabled, we
1950 can guess that the alignment is OK for the requested size. */
1952 if (! TARGET_STRICT_ALIGN
)
1953 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1959 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1960 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1963 i960_si_ti (base
, offset
)
1967 return i960_improve_align (base
, offset
, 16);
1970 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1971 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1974 i960_si_di (base
, offset
)
1978 return i960_improve_align (base
, offset
, 8);
1981 /* Return raw values of size and alignment (in words) for the data
1982 type being accessed. These values will be rounded by the caller. */
1985 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
1986 enum machine_mode mode
;
1993 /* Use formal alignment requirements of type being passed, except make
1994 it at least a word. If we don't have a type, this is a library call,
1995 and the parm has to be of scalar type. In this case, consider its
1996 formal alignment requirement to be its size in words. */
1998 if (mode
== BLKmode
)
1999 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2000 else if (mode
== VOIDmode
)
2002 /* End of parm list. */
2003 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2007 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2011 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2012 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2020 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2021 Any arg that is bigger than 4 words is placed on the stack and all
2022 subsequent arguments are placed on the stack.
2024 Additionally, parameters with an alignment requirement stronger than
2025 a word must be be aligned appropriately. */
2027 /* Update CUM to advance past an argument described by MODE and TYPE. */
2030 i960_function_arg_advance (cum
, mode
, type
, named
)
2031 CUMULATIVE_ARGS
*cum
;
2032 enum machine_mode mode
;
2038 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2040 if (size
> 4 || cum
->ca_nstackparms
!= 0
2041 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2042 || MUST_PASS_IN_STACK (mode
, type
))
2043 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2045 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2048 /* Return the register that the argument described by MODE and TYPE is
2049 passed in, or else return 0 if it is passed on the stack. */
2052 i960_function_arg (cum
, mode
, type
, named
)
2053 CUMULATIVE_ARGS
*cum
;
2054 enum machine_mode mode
;
2061 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2063 if (size
> 4 || cum
->ca_nstackparms
!= 0
2064 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2065 || MUST_PASS_IN_STACK (mode
, type
))
2067 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2072 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2073 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2079 /* Floating-point support. */
2082 i960_output_double (file
, value
)
2086 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
2088 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2090 fprintf (file
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
2091 value_long
[0], value
, value_long
[1]);
2093 if (REAL_VALUE_ISINF (value
))
2095 fprintf (file
, "\t.word 0\n");
2096 fprintf (file
, "\t.word 0x7ff00000 # Infinity\n");
2099 fprintf (file
, "\t.double 0d%.17e\n", (value
));
2104 i960_output_float (file
, value
)
2108 #ifdef REAL_VALUE_TO_TARGET_SINGLE
2110 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2112 fprintf (file
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
2114 if (REAL_VALUE_ISINF (value
))
2115 fprintf (file
, "\t.word 0x7f800000 # Infinity\n");
2117 fprintf (file
, "\t.float 0f%.12e\n", (value
));
2121 /* Return the number of bits that an object of size N bytes is aligned to. */
2124 i960_object_bytes_bitalign (n
)
2128 else if (n
> 4) n
= 64;
2129 else if (n
> 2) n
= 32;
2130 else if (n
> 1) n
= 16;
2136 /* Compute the size of an aggregate type TSIZE. */
2139 i960_round_size (tsize
)
2142 int size
, byte_size
, align
;
2144 if (TREE_CODE (tsize
) != INTEGER_CST
)
2147 size
= TREE_INT_CST_LOW (tsize
);
2148 byte_size
= (size
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2149 align
= i960_object_bytes_bitalign (byte_size
);
2151 /* Handle #pragma align. */
2152 if (align
> i960_maxbitalignment
)
2153 align
= i960_maxbitalignment
;
2156 size
= ((size
/ align
) + 1) * align
;
2158 return size_int (size
);
2161 /* Compute the alignment for an aggregate type TSIZE. */
2164 i960_round_align (align
, tsize
)
2170 if (TREE_CODE (tsize
) != INTEGER_CST
)
2173 byte_size
= (TREE_INT_CST_LOW (tsize
) + BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2174 align
= i960_object_bytes_bitalign (byte_size
);
2178 /* Do any needed setup for a varargs function. For the i960, we must
2179 create a register parameter block if one doesn't exist, and then copy
2180 all register parameters to memory. */
2183 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2184 CUMULATIVE_ARGS
*cum
;
2185 enum machine_mode mode
;
2190 if (cum
->ca_nregparms
< NPARM_REGS
)
2192 int first_reg_offset
= cum
->ca_nregparms
;
2196 rtx label
= gen_label_rtx ();
2199 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2200 and we need to allocate a chunk to save the registers (if any
2201 arguments were passed on the stack the caller would allocate the
2202 48 bytes as well). We must allocate all 48 bytes (12*4) because
2203 arg_pointer_rtx is saved at the front, the anonymous args are
2204 saved at the end. */
2205 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2206 emit_jump_insn (gen_bne (label
));
2207 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2208 stack_pointer_rtx
));
2209 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2210 memory_address (SImode
,
2211 plus_constant (stack_pointer_rtx
,
2215 /* Any anonymous args passed in regs? */
2216 if (first_reg_offset
+ 1 < NPARM_REGS
)
2219 regblock
= gen_rtx (MEM
, BLKmode
,
2220 plus_constant (arg_pointer_rtx
,
2221 (first_reg_offset
+ 1) * 4));
2222 move_block_from_reg (first_reg_offset
+ 1, regblock
,
2223 NPARM_REGS
- first_reg_offset
- 1,
2224 ((NPARM_REGS
- first_reg_offset
- 1)
2231 /* Calculate the final size of the reg parm stack space for the current
2232 function, based on how many bytes would be allocated on the stack. */
2235 i960_final_reg_parm_stack_space (const_size
, var_size
)
2239 if (var_size
|| const_size
> 48)
2245 /* Calculate the size of the reg parm stack space. This is a bit complicated
2249 i960_reg_parm_stack_space (fndecl
)
2252 /* In this case, we are called from emit_library_call, and we don't need
2253 to pretend we have more space for parameters than what's apparent. */
2257 /* In this case, we are called from locate_and_pad_parms when we're
2258 not IN_REGS, so we have an arg block. */
2259 if (fndecl
!= current_function_decl
)
2262 /* Otherwise, we have an arg block if the current function has more than
2263 48 bytes of parameters. */
2264 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2270 /* Return the register class of a scratch register needed to copy IN into
2271 or out of a register in CLASS in MODE. If it can be done directly,
2272 NO_REGS is returned. */
2275 secondary_reload_class (class, mode
, in
)
2276 enum reg_class
class;
2277 enum machine_mode mode
;
2282 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2283 regno
= true_regnum (in
);
2285 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2286 LOCAL_OR_GLOBAL_REGS into anything. */
2287 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2288 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2291 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2292 if (class == FP_REGS
2293 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2294 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2297 return LOCAL_OR_GLOBAL_REGS
;
2300 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2301 function unit it executed on. */
2303 /* ??? This would make more sense as an attribute. */
2306 i960_scan_opcode (p
)
2318 /* Ret is not actually of type REG, but it won't matter, because no
2319 insn will ever follow it. */
2322 i960_last_insn_type
= I_TYPE_REG
;
2326 if (p
[1] == 'x' || p
[3] == 'x')
2327 i960_last_insn_type
= I_TYPE_MEM
;
2328 i960_last_insn_type
= I_TYPE_CTRL
;
2333 i960_last_insn_type
= I_TYPE_CTRL
;
2340 i960_last_insn_type
= I_TYPE_MEM
;
2342 i960_last_insn_type
= I_TYPE_CTRL
;
2344 else if (p
[1] == 'm')
2347 i960_last_insn_type
= I_TYPE_REG
;
2348 else if (p
[4] == 'b' || p
[4] == 'j')
2349 i960_last_insn_type
= I_TYPE_CTRL
;
2351 i960_last_insn_type
= I_TYPE_REG
;
2354 i960_last_insn_type
= I_TYPE_REG
;
2358 i960_last_insn_type
= I_TYPE_MEM
;
2363 i960_last_insn_type
= I_TYPE_MEM
;
2365 i960_last_insn_type
= I_TYPE_REG
;