1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* Where to save/restore register 14 to/from before/after a procedure call
61 when it holds an argument block pointer. */
63 static rtx g14_save_reg
;
65 /* The leaf-procedure return register. Set only if this is a leaf routine. */
67 static int i960_leaf_ret_reg
;
69 /* True if replacing tail calls with jumps is OK. */
71 static int tail_call_ok
;
73 /* A string containing a list of insns to emit in the epilogue so as to
74 restore all registers saved by the prologue. Created by the prologue
75 code as it saves registers away. */
77 char epilogue_string
[1000];
79 /* A unique number (per function) for return labels. */
81 static int ret_label
= 0;
84 /* Handle pragmas for compatibility with Intel's compilers. */
86 /* ??? This is incomplete, since it does not handle all pragmas that the
87 intel compilers understand. Also, it needs to be rewritten to accept
88 a stream instead of a string for GCC 2. */
97 if ((i
= sscanf (str
, " align %d", &align
)) == 1)
100 case 0: /* Return to last alignment. */
101 align
= i960_last_maxbitalignment
/ 8;
103 case 16: /* Byte alignments. */
108 i960_last_maxbitalignment
= i960_maxbitalignment
;
109 i960_maxbitalignment
= align
* 8;
112 default: /* Unknown, silently ignore. */
116 /* NOTE: ic960 R3.0 pragma align definition:
118 #pragma align [(size)] | (identifier=size[,...])
119 #pragma noalign [(identifier)[,...]]
121 (all parens are optional)
123 - size is [1,2,4,8,16]
124 - noalign means size==1
125 - applies only to component elements of a struct (and union?)
126 - identifier applies to structure tag (only)
127 - missing identifier means next struct
129 - alignment rules for bitfields need more investigation */
131 /* Should be pragma 'far' or equivalent for callx/balx here. */
135 /* Initialize variables before compiling any files. */
140 if (TARGET_IC_COMPAT2_0
)
142 i960_maxbitalignment
= 8;
143 i960_last_maxbitalignment
= 128;
147 i960_maxbitalignment
= 128;
148 i960_last_maxbitalignment
= 8;
152 /* Return true if OP can be used as the source of an fp move insn. */
155 fpmove_src_operand (op
, mode
)
157 enum machine_mode mode
;
159 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
163 /* Return true if OP is a register or zero. */
166 reg_or_zero_operand (op
, mode
)
168 enum machine_mode mode
;
170 return register_operand (op
, mode
) || op
== const0_rtx
;
174 /* Return truth value of whether OP can be used as an operands in a three
175 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
178 arith_operand (op
, mode
)
180 enum machine_mode mode
;
182 return (register_operand (op
, mode
) || literal (op
, mode
));
185 /* Return true if OP is a register or a valid floating point literal. */
188 fp_arith_operand (op
, mode
)
190 enum machine_mode mode
;
192 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
195 /* Return true is OP is a register or a valid signed integer literal. */
198 signed_arith_operand (op
, mode
)
200 enum machine_mode mode
;
202 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
205 /* Return truth value of whether OP is a integer which fits the
206 range constraining immediate operands in three-address insns. */
211 enum machine_mode mode
;
213 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
216 /* Return true if OP is a float constant of 1. */
219 fp_literal_one (op
, mode
)
221 enum machine_mode mode
;
223 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
224 && (op
== CONST1_RTX (mode
)));
227 /* Return true if OP is a float constant of 0. */
230 fp_literal_zero (op
, mode
)
232 enum machine_mode mode
;
234 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
235 && (op
== CONST0_RTX (mode
)));
238 /* Return true if OP is a valid floating point literal. */
243 enum machine_mode mode
;
245 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
248 /* Return true if OP is a valid signed immediate constant. */
251 signed_literal(op
, mode
)
253 enum machine_mode mode
;
255 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
258 /* Return truth value of statement that OP is a symbolic memory
259 operand of mode MODE. */
262 symbolic_memory_operand (op
, mode
)
264 enum machine_mode mode
;
266 if (GET_CODE (op
) == SUBREG
)
267 op
= SUBREG_REG (op
);
268 if (GET_CODE (op
) != MEM
)
271 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
272 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
275 /* Return truth value of whether OP is EQ or NE. */
280 enum machine_mode mode
;
282 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
285 /* OP is an integer register or a constant. */
288 arith32_operand (op
, mode
)
290 enum machine_mode mode
;
292 if (register_operand (op
, mode
))
294 return (CONSTANT_P (op
));
297 /* Return true if OP is an integer constant which is a power of 2. */
300 power2_operand (op
,mode
)
302 enum machine_mode mode
;
304 if (GET_CODE(op
) != CONST_INT
)
307 return exact_log2 (INTVAL (op
)) >= 0;
310 /* If VAL has only one bit set, return the index of that bit. Otherwise
319 for (i
= 0; val
!= 0; i
++, val
>>= 1)
331 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
332 The return value indicates how many consecutive non-zero bits exist
333 if this is a mask. This is the same as the next function, except that
334 it does not indicate what the start and stop bit positions are. */
340 register int start
, end
, i
;
343 for (i
= 0; val
!= 0; val
>>= 1, i
++)
353 /* Still looking for the first bit. */
357 /* We've seen the start of a bit sequence, and now a zero. There
358 must be more one bits, otherwise we would have exited the loop.
359 Therefore, it is not a mask. */
364 /* The bit string has ones from START to END bit positions only. */
365 return end
- start
+ 1;
368 /* If VAL is a mask, then return nonzero, with S set to the starting bit
369 position and E set to the ending bit position of the mask. The return
370 value indicates how many consecutive bits exist in the mask. This is
371 the same as the previous function, except that it also indicates the
372 start and end bit positions of the mask. */
379 register int start
, end
, i
;
383 for (i
= 0; val
!= 0; val
>>= 1, i
++)
394 /* Still looking for the first bit. */
398 /* We've seen the start of a bit sequence, and now a zero. There
399 must be more one bits, otherwise we would have exited the loop.
400 Therefor, it is not a mask. */
409 /* The bit string has ones from START to END bit positions only. */
412 return ((start
< 0) ? 0 : end
- start
+ 1);
415 /* Return the machine mode to use for a comparison. */
418 select_cc_mode (op
, x
)
422 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
427 /* X and Y are two things to compare using CODE. Emit the compare insn and
428 return the rtx for register 36 in the proper mode. */
431 gen_compare_reg (code
, x
, y
)
436 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
437 enum machine_mode mode
438 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
442 if (! arith_operand (x
, mode
))
443 x
= force_reg (SImode
, x
);
444 if (! arith_operand (y
, mode
))
445 y
= force_reg (SImode
, y
);
448 cc_reg
= gen_rtx (REG
, ccmode
, 36);
449 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
450 gen_rtx (COMPARE
, ccmode
, x
, y
)));
455 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
456 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
457 are 4. Indexed addresses are cost 6. */
459 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
462 i960_address_cost (x
)
466 /* Handled before calling here. */
467 if (GET_CODE (x
) == REG
)
470 if (GET_CODE (x
) == PLUS
)
472 rtx base
= XEXP (x
, 0);
473 rtx offset
= XEXP (x
, 1);
475 if (GET_CODE (base
) == SUBREG
)
476 base
= SUBREG_REG (base
);
477 if (GET_CODE (offset
) == SUBREG
)
478 offset
= SUBREG_REG (offset
);
480 if (GET_CODE (base
) == REG
)
482 if (GET_CODE (offset
) == REG
)
484 if (GET_CODE (offset
) == CONST_INT
)
486 if ((unsigned)INTVAL (offset
) < 2047)
490 if (CONSTANT_P (offset
))
493 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
498 if (GET_CODE (x
) == MULT
)
501 /* Symbol_refs and other unrecognized addresses are cost 4. */
505 /* Emit insns to move operands[1] into operands[0].
507 Return 1 if we have written out everything that needs to be done to
508 do the move. Otherwise, return 0 and the caller will emit the move
512 emit_move_sequence (operands
, mode
)
514 enum machine_mode mode
;
516 register rtx operand0
= operands
[0];
517 register rtx operand1
= operands
[1];
519 /* We can only store registers to memory. */
521 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
522 operands
[1] = force_reg (mode
, operand1
);
527 /* Emit insns to load a constant. Uses several strategies to try to use
528 as few insns as possible. */
531 i960_output_ldconst (dst
, src
)
532 register rtx dst
, src
;
535 register unsigned rsrc2
;
536 enum machine_mode mode
= GET_MODE (dst
);
538 union { long l
[2]; double d
; } x
;
540 operands
[0] = operands
[2] = dst
;
541 operands
[1] = operands
[3] = src
;
543 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
544 must be a ldconst insn. */
546 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
548 output_asm_insn ("ldconst %1,%0", operands
);
551 else if (mode
== DFmode
)
555 if (fp_literal_zero (src
, VOIDmode
))
558 return "movrl %1,%0";
563 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
564 split_double (src
, &first
, &second
);
566 output_asm_insn ("# ldconst %1,%0",operands
);
568 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
570 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
572 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
573 operands
[1] = second
;
574 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
578 if (fp_literal_one (src
, VOIDmode
))
579 return "movrl 0f1.0,%0";
580 fatal ("inline double constants not supported on this host");
583 else if (mode
== TImode
)
585 /* ??? This is currently not handled at all. */
588 /* Note: lowest order word goes in lowest numbered reg. */
589 rsrc1
= INTVAL (src
);
590 if (rsrc1
>= 0 && rsrc1
< 32)
593 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
594 /* Go pick up the low-order word. */
596 else if (mode
== DImode
)
598 rtx upperhalf
, lowerhalf
;
601 if (GET_CODE (src
) == CONST_DOUBLE
)
603 upperhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_HIGH (src
));
604 lowerhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_LOW (src
));
606 else if (GET_CODE (src
) == CONST_INT
)
609 upperhalf
= INTVAL (src
) < 0 ? constm1_rtx
: const0_rtx
;
614 /* Note: lowest order word goes in lowest numbered reg. */
615 /* Numbers from 0 to 31 can be handled with a single insn. */
616 rsrc1
= INTVAL (lowerhalf
);
617 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
620 /* Output the upper half with a recursive call. */
621 string
= i960_output_ldconst (gen_rtx (REG
, SImode
, REGNO (dst
) + 1),
623 output_asm_insn (string
);
624 /* The lower word is emitted as normally. */
626 else if (mode
== SFmode
)
628 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
629 union { long l
; float f
; } flt
;
631 flt
.f
= (float) *((double *) &CONST_DOUBLE_LOW (src
));
633 output_asm_insn ("# ldconst %1,%0",operands
);
634 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
635 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, flt
.l
);
636 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
639 if (fp_literal_zero (src
, VOIDmode
))
640 return "movr 0f0.0,%0";
641 if (fp_literal_one (src
, VOIDmode
))
642 return "movr 0f1.0,%0";
643 fatal ("inline float constants not supported on this host");
649 rsrc1
= INTVAL (src
);
655 else if (mode
== HImode
)
664 /* ldconst 0..31,X -> mov 0..31,X */
667 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
672 /* ldconst 32..63,X -> add 31,nn,X */
675 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
677 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
678 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
684 /* ldconst -1..-31 -> sub 0,0..31,X */
687 /* return 'sub -(%1),0,%0' */
688 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
689 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
693 /* ldconst -32 -> not 31,X */
696 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
697 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
702 /* If const is a single bit. */
703 if (bitpos (rsrc1
) >= 0)
705 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
706 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
710 /* If const is a bit string of less than 6 bits (1..31 shifted). */
715 if (bitstr (rsrc1
, &s
, &e
) < 6)
717 rsrc2
= ((unsigned int) rsrc1
) >> s
;
718 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
719 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
720 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
725 /* Unimplemented cases:
726 const is in range 0..31 but rotated around end of word:
727 ror 31,3,g0 -> ldconst 0xe0000003,g0
729 and any 2 instruction cases that might be worthwhile */
731 output_asm_insn ("ldconst %1,%0", operands
);
735 /* Determine if there is an opportunity for a bypass optimization.
736 Bypass suceeds on the 960K* if the destination of the previous
737 instruction is the second operand of the current instruction.
738 Bypass always succeeds on the C*.
740 Return 1 if the pattern should interchange the operands.
742 CMPBR_FLAG is true if this is for a compare-and-branch insn.
743 OP1 and OP2 are the two source operands of a 3 operand insn. */
746 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
747 register rtx insn
, op1
, op2
;
750 register rtx prev_insn
, prev_dest
;
755 /* Can't do this if op1 isn't a register. */
759 /* Can't do this for a compare-and-branch if both ops aren't regs. */
760 if (cmpbr_flag
&& ! REG_P (op2
))
763 prev_insn
= prev_real_insn (insn
);
765 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
766 && GET_CODE (PATTERN (prev_insn
)) == SET
)
768 prev_dest
= SET_DEST (PATTERN (prev_insn
));
769 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
770 || (GET_CODE (prev_dest
) == SUBREG
771 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
772 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
778 /* Output the code which declares the function name. This also handles
779 leaf routines, which have special requirements, and initializes some
783 i960_function_name_declare (file
, name
, fndecl
)
792 /* Increment global return label. */
796 /* Compute whether tail calls and leaf routine optimizations can be performed
797 for this function. */
809 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
810 argblock, because argblock uses g14 implicitly. */
812 if (current_function_args_size
!= 0)
818 /* See if caller passes in an address to return value. */
820 if (aggregate_value_p (DECL_RESULT (fndecl
)))
826 /* Can not use tail calls or make this a leaf routine if there is a non
829 if (get_frame_size () != 0)
832 /* I don't understand this condition, and do not think that it is correct.
833 Apparently this is just checking whether the frame pointer is used, and
834 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
837 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
838 if (GET_CODE (insn
) == INSN
839 && reg_mentioned_p (frame_pointer_rtx
, insn
))
845 /* Check for CALL insns. Can not be a leaf routine if there are any. */
848 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
849 if (GET_CODE (insn
) == CALL_INSN
)
855 /* Can not be a leaf routine if any non-call clobbered registers are
856 used in this function. */
859 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
860 if (regs_ever_live
[i
]
861 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
863 /* Global registers. */
864 if (i
< 16 && i
> 7 && i
!= 13)
866 /* Local registers. */
871 /* Now choose a leaf return register, if we can find one, and if it is
872 OK for this to be a leaf routine. */
874 i960_leaf_ret_reg
= -1;
876 if (optimize
&& leaf_proc_ok
)
878 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
879 if (regs_ever_live
[i
] == 0)
881 i960_leaf_ret_reg
= i
;
882 regs_ever_live
[i
] = 1;
887 /* Do this after choosing the leaf return register, so it will be listed
888 if one was chosen. */
890 fprintf (file
, "\t# Function '%s'\n", name
);
891 fprintf (file
, "\t# Registers used: ");
893 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
895 if (regs_ever_live
[i
])
897 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
899 if (i
> 15 && j
== 0)
901 fprintf (file
,"\n\t#\t\t ");
907 fprintf (file
, "\n");
909 if (i960_leaf_ret_reg
>= 0)
911 /* Make it a leaf procedure. */
913 if (TREE_PUBLIC (fndecl
))
914 fprintf (file
,"\t.globl %s.lf\n", name
);
916 fprintf (file
, "\t.leafproc\t_%s,%s.lf\n", name
, name
);
917 fprintf (file
, "_%s:\n", name
);
918 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
919 fprintf (file
, "%s.lf:\n", name
);
920 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
924 fprintf (file
, "\tlda 0,g14\n");
925 i960_last_insn_type
= I_TYPE_MEM
;
929 fprintf (file
, "\tmov 0,g14\n");
930 i960_last_insn_type
= I_TYPE_REG
;
935 ASM_OUTPUT_LABEL (file
, name
);
936 i960_last_insn_type
= I_TYPE_CTRL
;
940 /* Compute and return the frame size. */
943 compute_frame_size (size
)
947 int outgoing_args_size
948 = current_function_outgoing_args_size
+ current_function_pretend_args_size
;
950 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
951 as size is concerned. */
952 actual_fsize
= (size
+ 15) & -16;
953 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
958 /* Output code for the function prologue. */
961 i960_function_prologue (file
, size
)
965 register int i
, j
, nr
;
968 int actual_fsize
, offset
;
970 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
972 int regs
[FIRST_PSEUDO_REGISTER
];
974 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
975 if (regs_ever_live
[i
]
976 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
979 /* Count global registers that need saving. */
986 epilogue_string
[0] = '\0';
988 /* First look for local registers to save globals in. */
989 for (i
= 0; i
< 16; i
++)
994 /* Start at r4, not r3. */
995 for (j
= 20; j
< 32; j
++)
1002 regs_ever_live
[j
] = 1;
1004 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1005 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1010 regs_ever_live
[j
+1] = 1;
1012 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1013 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1018 regs_ever_live
[j
+2] = 1;
1020 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1025 regs_ever_live
[j
+3] = 1;
1028 fprintf (file
, "\tmov%s %s,%s\n",
1031 (nr
== 2) ? "l" : ""),
1032 reg_names
[i
], reg_names
[j
]);
1033 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1036 (nr
== 2) ? "l" : ""),
1037 reg_names
[j
], reg_names
[i
]);
1038 strcat (epilogue_string
, tmpstr
);
1046 /* N_iregs is now the number of global registers that haven't been saved
1049 rsize
= (n_iregs
* 4);
1050 actual_fsize
= compute_frame_size (size
) + rsize
;
1052 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1053 size up to the nearest multiple of 16. I don't know whether this is
1054 necessary, or even desirable.
1056 The frame pointer must be aligned, but the call instruction takes care of
1057 that. If we leave the stack pointer unaligned, we may save a little on
1058 dynamic stack allocation. And we don't lose, at least according to the
1060 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1063 /* Allocate space for register save and locals. */
1064 if (actual_fsize
> 0)
1066 if (actual_fsize
< 32)
1067 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1069 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1072 /* Take hardware register save area created by the call instruction
1074 offset
= compute_frame_size (size
) + 64;
1075 /* Save registers on stack if needed. */
1076 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1083 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1086 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1090 if (nr
== 3 && regs
[i
+3] == -1)
1093 fprintf (file
,"\tst%s %s,%d(fp)\n",
1096 (nr
== 2) ? "l" : ""),
1097 reg_names
[i
], offset
);
1098 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1101 (nr
== 2) ? "l" : ""),
1102 offset
, reg_names
[i
]);
1103 strcat (epilogue_string
, tmpstr
);
1109 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1112 fprintf (file
, "\t#Prologue stats:\n");
1113 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1116 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1118 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1120 fprintf (file
, "\t#End Prologue#\n");
1123 /* Output code for the function epilogue. */
1126 i960_function_epilogue (file
, size
)
1130 if (i960_leaf_ret_reg
>= 0)
1132 fprintf (file
, "LR%d: ret\n", ret_label
);
1136 if (*epilogue_string
== 0)
1140 /* Emit a return insn, but only if control can fall through to here. */
1142 tmp
= get_last_insn ();
1145 if (GET_CODE (tmp
) == BARRIER
)
1147 if (GET_CODE (tmp
) == CODE_LABEL
)
1149 if (GET_CODE (tmp
) == JUMP_INSN
)
1151 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1155 if (GET_CODE (tmp
) == NOTE
)
1157 tmp
= PREV_INSN (tmp
);
1162 fprintf (file
, "LR%d: ret\n", ret_label
);
1166 fprintf (file
, "LR%d:\n", ret_label
);
1168 fprintf (file
, "\t#EPILOGUE#\n");
1170 /* Output the string created by the prologue which will restore all
1171 registers saved by the prologue. */
1173 if (epilogue_string
[0] != '\0')
1174 fprintf (file
, "%s", epilogue_string
);
1176 /* Must clear g14 on return. */
1178 if (current_function_args_size
!= 0)
1179 fprintf (file
, "\tmov 0,g14\n");
1181 fprintf (file
, "\tret\n");
1182 fprintf (file
, "\t#End Epilogue#\n");
1185 /* Output code for a call insn. */
1188 i960_output_call_insn (target
, argsize_rtx
, insn
)
1189 register rtx target
, argsize_rtx
, insn
;
1192 int argsize
= INTVAL (argsize_rtx
);
1193 rtx nexti
= next_real_insn (insn
);
1196 operands
[0] = target
;
1198 non_indirect
= ((GET_CODE (target
) == MEM
)
1199 && (GET_CODE (XEXP (target
, 0)) == SYMBOL_REF
));
1201 /* Nexti could be zero if the called routine is volatile. */
1202 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1203 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1205 /* Delete following return insn. */
1206 if (nexti
&& no_labels_between_p (insn
, nexti
))
1207 delete_insn (nexti
);
1208 output_asm_insn (non_indirect
? "b %0" : "bx %0",
1210 return "# notreached";
1213 output_asm_insn (non_indirect
? "callj %0" : "callx %0", operands
);
1217 /* Output code for a return insn. */
1220 i960_output_ret_insn (insn
)
1223 static char lbuf
[20];
1225 if (*epilogue_string
!= 0)
1227 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1230 sprintf (lbuf
, "b LR%d", ret_label
);
1234 if (current_function_args_size
!= 0)
1235 output_asm_insn ("mov 0,g14", 0);
1237 if (i960_leaf_ret_reg
>= 0)
1239 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1246 /* Return a character string representing the branch prediction
1247 opcode to be tacked on an instruction. This must at least
1248 return a null string. */
1251 i960_br_predict_opcode (lab_ref
, insn
)
1254 if (TARGET_BRANCH_PREDICT
)
1256 unsigned long label_uid
;
1258 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1259 label_uid
= INSN_UID (lab_ref
);
1260 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1261 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1265 /* If not optimizing, then the insn_addresses array will not be
1266 valid. In this case, always return ".t" since most branches
1267 are taken. If optimizing, return .t for backward branches
1268 and .f for forward branches. */
1270 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1279 /* Print the operand represented by rtx X formatted by code CODE. */
1282 i960_print_operand (file
, x
, code
)
1287 enum rtx_code rtxcode
= GET_CODE (x
);
1294 /* Second reg of a double. */
1295 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1299 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1307 else if (rtxcode
== MEM
)
1309 output_address (XEXP (x
, 0));
1312 else if (rtxcode
== CONST_INT
)
1314 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1315 fprintf (file
, "0x%x", INTVAL (x
));
1317 fprintf (file
, "%d", INTVAL (x
));
1320 else if (rtxcode
== CONST_DOUBLE
)
1324 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1326 fprintf (file
, "0f0.0");
1329 else if (x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))
1331 fprintf (file
, "0f1.0");
1335 /* This better be a comment. */
1336 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1337 fprintf (file
, "%#g", d
);
1344 /* Branch or jump, depending on assembler. */
1345 if (TARGET_ASM_COMPAT
)
1352 /* Sign of condition. */
1353 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1354 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1356 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1357 || (rtxcode
== GE
) || (rtxcode
== LE
))
1364 /* Inverted condition. */
1365 rtxcode
= reverse_condition (rtxcode
);
1369 /* Inverted condition w/ reversed operands. */
1370 rtxcode
= reverse_condition (rtxcode
);
1374 /* Reversed operand condition. */
1375 rtxcode
= swap_condition (rtxcode
);
1379 /* Normal condition. */
1381 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1382 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1383 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1384 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1385 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1386 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1387 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1388 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1389 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1390 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1395 output_addr_const (file
, x
);
1405 /* Print a memory address as an operand to reference that memory location.
1407 This is exactly the same as legitimate_address_p, except that it the prints
1408 addresses instead of recognizing them. */
1411 i960_print_operand_addr (file
, addr
)
1423 if (GET_CODE (addr
) == REG
)
1425 else if (CONSTANT_P (addr
))
1427 else if (GET_CODE (addr
) == PLUS
)
1431 op0
= XEXP (addr
, 0);
1432 op1
= XEXP (addr
, 1);
1434 if (GET_CODE (op0
) == REG
)
1437 if (GET_CODE (op1
) == REG
)
1439 else if (CONSTANT_P (op1
))
1444 else if (GET_CODE (op0
) == PLUS
)
1446 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1448 ireg
= XEXP (XEXP (op0
, 0), 0);
1449 scale
= XEXP (XEXP (op0
, 0), 1);
1450 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1452 breg
= XEXP (op0
, 1);
1458 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1460 breg
= XEXP (op0
, 0);
1461 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1463 ireg
= XEXP (op0
, 1);
1472 else if (GET_CODE (op0
) == MULT
)
1474 ireg
= XEXP (op0
, 0);
1475 scale
= XEXP (op0
, 1);
1476 if (GET_CODE (op1
) == REG
)
1478 else if (CONSTANT_P (op1
))
1486 else if (GET_CODE (addr
) == MULT
)
1488 breg
= XEXP (addr
, 0);
1489 scale
= XEXP (addr
, 1);
1495 output_addr_const (file
, offset
);
1497 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1499 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1502 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1503 that is a valid memory address for an instruction.
1504 The MODE argument is the machine mode for the MEM expression
1505 that wants to use this address.
1507 On 80960, legitimate addresses are:
1509 disp (12 or 32 bit) ld foo,r0
1510 base + index ld (g0)[g1*1],r0
1511 base + displ ld 0xf00(g0),r0
1512 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1513 index*scale + base ld (g0)[g1*4],r0
1514 index*scale + displ ld 0xf00[g1*4],r0
1515 index*scale ld [g1*4],r0
1516 index + base + displ ld 0xf00(g0)[g1*1],r0
1518 In each case, scale can be 1, 2, 4, 8, or 16. */
1520 /* This is exactly the same as i960_print_operand_addr, except that
1521 it recognizes addresses instead of printing them.
1523 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1524 convert common non-canonical forms to canonical form so that they will
1528 legitimate_address_p (mode
, addr
, strict
)
1529 enum machine_mode mode
;
1533 if (GET_CODE (addr
) == REG
)
1534 return (strict
? REG_OK_FOR_BASE_P_STRICT (addr
)
1535 : REG_OK_FOR_BASE_P (addr
));
1536 else if (CONSTANT_P (addr
))
1538 else if (GET_CODE (addr
) == PLUS
)
1542 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1545 op0
= XEXP (addr
, 0);
1546 op1
= XEXP (addr
, 1);
1548 if (GET_CODE (op0
) == REG
)
1550 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (op0
)
1551 : REG_OK_FOR_BASE_P (op0
)))
1554 if (GET_CODE (op1
) == REG
)
1555 return (strict
? REG_OK_FOR_INDEX_P_STRICT (op1
)
1556 : REG_OK_FOR_INDEX_P (op1
));
1557 else if (CONSTANT_P (op1
))
1562 else if (GET_CODE (op0
) == PLUS
)
1564 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1566 if (! (GET_CODE (XEXP (XEXP (op0
, 0), 0)) == REG
1567 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (XEXP (op0
, 0), 0))
1568 : REG_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0)))
1569 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1572 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1573 return ((strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 1))
1574 : REG_OK_FOR_BASE_P (XEXP (op0
, 1)))
1575 && CONSTANT_P (op1
));
1579 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1581 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 0))
1582 : REG_OK_FOR_BASE_P (XEXP (op0
, 0))))
1585 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1586 return ((strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 1))
1587 : REG_OK_FOR_INDEX_P (XEXP (op0
, 1)))
1588 && CONSTANT_P (op1
));
1595 else if (GET_CODE (op0
) == MULT
)
1597 if (! (GET_CODE (XEXP (op0
, 0)) == REG
1598 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 0))
1599 : REG_OK_FOR_INDEX_P (XEXP (op0
, 0)))
1600 && SCALE_TERM_P (XEXP (op0
, 1))))
1603 if (GET_CODE (op1
) == REG
)
1604 return (strict
? REG_OK_FOR_BASE_P_STRICT (op1
)
1605 : REG_OK_FOR_BASE_P (op1
));
1606 else if (CONSTANT_P (op1
))
1614 else if (GET_CODE (addr
) == MULT
)
1616 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1619 return (GET_CODE (XEXP (addr
, 0)) == REG
1620 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (addr
, 0))
1621 : REG_OK_FOR_INDEX_P (XEXP (addr
, 0)))
1622 && SCALE_TERM_P (XEXP (addr
, 1)));
1628 /* Try machine-dependent ways of modifying an illegitimate address
1629 to be legitimate. If we find one, return the new, valid address.
1630 This macro is used in only one place: `memory_address' in explow.c.
1632 This converts some non-canonical addresses to canonical form so they
1633 can be recognized. */
1636 legitimize_address (x
, oldx
, mode
)
1639 enum machine_mode mode
;
1641 if (GET_CODE (x
) == SYMBOL_REF
)
1644 x
= copy_to_reg (x
);
1647 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1650 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1651 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1652 created by virtual register instantiation, register elimination, and
1653 similar optimizations. */
1654 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1655 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1656 x
= gen_rtx (PLUS
, Pmode
,
1657 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1658 XEXP (XEXP (x
, 1), 1));
1660 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1661 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1662 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1663 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1664 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1665 && CONSTANT_P (XEXP (x
, 1)))
1667 rtx constant
, other
;
1669 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1671 constant
= XEXP (x
, 1);
1672 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1674 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1676 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1677 other
= XEXP (x
, 1);
1683 x
= gen_rtx (PLUS
, Pmode
,
1684 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1685 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1686 plus_constant (other
, INTVAL (constant
)));
1693 /* Return the most stringent alignment that we are willing to consider
1694 objects of size SIZE and known alignment ALIGN as having. */
1697 i960_alignment (size
, align
)
1703 if (! TARGET_STRICT_ALIGN
)
1704 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1706 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1715 /* Modes for condition codes. */
1717 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1719 /* Modes for single-word (and smaller) quantities. */
1722 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1723 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1725 /* Modes for double-word (and smaller) quantities. */
1728 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1730 /* Modes for quad-word quantities. */
1731 #define T_MODES (~C_MODES)
1733 /* Modes for single-float quantities. */
1734 #define SF_MODES ((1 << (int) SFmode))
1736 /* Modes for double-float quantities. */
1737 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1739 /* Modes for quad-float quantities. */
1740 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1742 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1743 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1744 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1745 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1746 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1748 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1751 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1752 advantage of machine specific facts, such as knowing that the frame pointer
1753 is always 16 byte aligned. */
1756 i960_expr_alignment (x
, size
)
1765 switch (GET_CODE(x
))
1770 if ((align
& 0xf) == 0)
1772 else if ((align
& 0x7) == 0)
1774 else if ((align
& 0x3) == 0)
1776 else if ((align
& 0x1) == 0)
1783 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1784 i960_expr_alignment (XEXP (x
, 1), size
));
1788 /* If this is a valid program, objects are guaranteed to be
1789 correctly aligned for whatever size the reference actually is. */
1790 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1794 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1800 align
= i960_expr_alignment (XEXP (x
, 0));
1802 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1804 align
= align
<< INTVAL (XEXP (x
, 1));
1805 align
= MIN (align
, 16);
1810 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1811 i960_expr_alignment (XEXP (x
, 1), size
));
1813 align
= MIN (align
, 16);
1820 /* Return true if it is possible to reference both BASE and OFFSET, which
1821 have alignment at least as great as 4 byte, as if they had alignment valid
1822 for an object of size SIZE. */
1825 i960_improve_align (base
, offset
, size
)
1832 /* We have at least a word reference to the object, so we know it has to
1833 be aligned at least to 4 bytes. */
1835 i
= MIN (i960_expr_alignment (base
, 4),
1836 i960_expr_alignment (offset
, 4));
1840 /* We know the size of the request. If strict align is not enabled, we
1841 can guess that the alignment is OK for the requested size. */
1843 if (! TARGET_STRICT_ALIGN
)
1844 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1850 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1851 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1854 i960_si_ti (base
, offset
)
1858 return i960_improve_align (base
, offset
, 16);
1861 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1862 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1865 i960_si_di (base
, offset
)
1869 return i960_improve_align (base
, offset
, 8);
1872 /* Return raw values of size and alignment (in words) for the data
1873 type being accessed. These values will be rounded by the caller. */
1876 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
1877 enum machine_mode mode
;
1884 /* Use formal alignment requirements of type being passed, except make
1885 it at least a word. If we don't have a type, this is a library call,
1886 and the parm has to be of scalar type. In this case, consider its
1887 formal alignment requirement to be its size in words. */
1889 if (mode
== BLKmode
)
1890 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1891 else if (mode
== VOIDmode
)
1893 /* End of parm list. */
1894 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
1898 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1902 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
1903 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
1911 /* On the 80960 the first 12 args are in registers and the rest are pushed.
1912 Any arg that is bigger than 4 words is placed on the stack and all
1913 subsequent arguments are placed on the stack.
1915 Additionally, parameters with an alignment requirement stronger than
1916 a word must be be aligned appropriately. */
1918 /* Update CUM to advance past an argument described by MODE and TYPE. */
1921 i960_function_arg_advance (cum
, mode
, type
, named
)
1922 CUMULATIVE_ARGS
*cum
;
1923 enum machine_mode mode
;
1929 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1931 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1932 || (size
+ ROUND (cum
->ca_nregparms
, align
)) > NPARM_REGS
1933 || MUST_PASS_IN_STACK (mode
, type
))
1934 cum
->ca_nstackparms
= ROUND (cum
->ca_nstackparms
, align
) + size
;
1936 cum
->ca_nregparms
= ROUND (cum
->ca_nregparms
, align
) + size
;
1939 /* Return the register that the argument described by MODE and TYPE is
1940 passed in, or else return 0 if it is passed on the stack. */
1943 i960_function_arg (cum
, mode
, type
, named
)
1944 CUMULATIVE_ARGS
*cum
;
1945 enum machine_mode mode
;
1952 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1954 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1955 || (size
+ ROUND (cum
->ca_nregparms
, align
)) > NPARM_REGS
1956 || MUST_PASS_IN_STACK (mode
, type
))
1958 cum
->ca_nstackparms
= ROUND (cum
->ca_nstackparms
, align
);
1963 cum
->ca_nregparms
= ROUND (cum
->ca_nregparms
, align
);
1964 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
1970 /* Return the rtx for the register representing the return value, or 0
1971 if the return value must be passed through the stack. */
1974 i960_function_value (type
)
1977 int mode
= TYPE_MODE (type
);
1979 if (mode
== BLKmode
)
1981 unsigned int size
= int_size_in_bytes (type
);
1984 mode
= mode_for_size (i960_object_bytes_bitalign (size
), MODE_INT
, 0);
1987 if (mode
== BLKmode
|| mode
== VOIDmode
)
1988 /* Tell stmt.c and expr.c to pass in address */
1991 return gen_rtx (REG
, mode
, 0);
1994 /* Floating-point support. */
1997 i960_output_double (file
, value
)
2001 if (REAL_VALUE_ISINF (value
))
2003 fprintf (file
, "\t.word 0\n");
2004 fprintf (file
, "\t.word 0x7ff00000 # Infinity\n");
2007 fprintf (file
, "\t.double 0d%.17e\n", (value
));
2011 i960_output_float (file
, value
)
2015 if (REAL_VALUE_ISINF (value
))
2016 fprintf (file
, "\t.word 0x7f800000 # Infinity\n");
2018 fprintf (file
, "\t.float 0f%.12e\n", (value
));
2021 /* Return the number of bits that an object of size N bytes is aligned to. */
2024 i960_object_bytes_bitalign (n
)
2028 else if (n
> 4) n
= 64;
2029 else if (n
> 2) n
= 32;
2030 else if (n
> 1) n
= 16;
2036 /* Compute the size of an aggregate type TSIZE. */
2039 i960_round_size (tsize
)
2044 if (TREE_CODE (tsize
) != INTEGER_CST
)
2047 size
= TREE_INT_CST_LOW (tsize
);
2048 align
= i960_object_bytes_bitalign (size
/ BITS_PER_UNIT
);
2050 /* Handle #pragma align. */
2051 if (align
> i960_maxbitalignment
)
2052 align
= i960_maxbitalignment
;
2055 size
= ((size
/ align
) + 1) * align
;
2057 return size_int (size
);
2060 /* Compute the alignment for an aggregate type TSIZE. */
2063 i960_round_align (align
, tsize
)
2067 if (TREE_CODE (tsize
) != INTEGER_CST
)
2070 align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2075 /* Do any needed setup for a varargs function. For the i960, we must
2076 create a register paramter block if one doesn't exist, and then copy
2077 all register parameters to memory. */
2080 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2081 CUMULATIVE_ARGS
*cum
;
2082 enum machine_mode mode
;
2087 if (cum
->ca_nregparms
< NPARM_REGS
)
2089 int first_reg_offset
= cum
->ca_nregparms
;
2091 if (first_reg_offset
> NPARM_REGS
)
2092 first_reg_offset
= NPARM_REGS
;
2094 if (! (no_rtl
) && first_reg_offset
!= NPARM_REGS
)
2096 rtx label
= gen_label_rtx ();
2097 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2098 emit_jump_insn (gen_bne (label
));
2099 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2100 stack_pointer_rtx
));
2101 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2102 memory_address (SImode
,
2103 plus_constant (stack_pointer_rtx
,
2108 gen_rtx (MEM
, BLKmode
, virtual_incoming_args_rtx
),
2109 NPARM_REGS
- first_reg_offset
);
2111 *pretend_size
= (NPARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
;
2115 /* Calculate the final size of the reg parm stack space for the current
2116 function, based on how many bytes would be allocated on the stack. */
2119 i960_final_reg_parm_stack_space (const_size
, var_size
)
2123 if (var_size
|| const_size
> 48)
2129 /* Calculate the size of the reg parm stack space. This is a bit complicated
2133 i960_reg_parm_stack_space (fndecl
)
2136 /* In this case, we are called from emit_library_call, and we don't need
2137 to pretend we have more space for parameters than what's apparent. */
2141 /* In this case, we are called from locate_and_pad_parms when we're
2142 not IN_REGS, so we have an arg block. */
2143 if (fndecl
!= current_function_decl
)
2146 /* Otherwise, we have an arg block if the current function has more than
2147 48 bytes of parameters. */
2148 if (current_function_args_size
!= 0)
2154 /* Return the register class of a scratch register needed to copy IN into
2155 or out of a register in CLASS in MODE. If it can be done directly,
2156 NO_REGS is returned. */
2159 secondary_reload_class (class, mode
, in
)
2160 enum reg_class
class;
2161 enum machine_mode mode
;
2166 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2167 regno
= true_regnum (in
);
2169 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2170 LOCAL_OR_GLOBAL_REGS into anything. */
2171 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2172 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2175 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2176 if (class == FP_REGS
2177 && ((regno
>= 0 && regno
<= FIRST_PSEUDO_REGISTER
)
2178 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2181 return LOCAL_OR_GLOBAL_REGS
;
2184 /* Emit the code necessary for a procedure call. Return value is needed
2185 after the call if target is non-zero. */
2188 i960_expand_call (first_operand
, second_operand
, target
)
2189 rtx first_operand
, second_operand
, target
;
2191 /* Used to ensure that g14_save_reg is initialized once and only once
2192 for each function if it is needed. */
2193 static char *this_function_name
= 0;
2196 if (this_function_name
!= current_function_name
)
2199 struct sequence_stack
*seq_stack
;
2201 this_function_name
= current_function_name
;
2203 /* If the current function has an argument block, then save g14 into
2204 a pseudo at the top of the function and restore it after this
2205 function call. If the current function has no argument block,
2206 then g14 is zero before and after the call. */
2208 if (current_function_args_size
!= 0)
2211 seq_stack
= sequence_stack
;
2212 while (seq_stack
->next
)
2213 seq_stack
= seq_stack
->next
;
2214 first
= seq_stack
->first
;
2215 g14_save_reg
= copy_to_reg (arg_pointer_rtx
);
2216 seq
= gen_sequence ();
2218 emit_insn_after (seq
, first
);
2222 if (current_function_args_size
!= 0)
2225 if (GET_CODE (second_operand
) != CONST_INT
|| INTVAL (second_operand
) > 48)
2227 /* Calling a function needing an argument block. */
2228 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2229 virtual_outgoing_args_rtx
));
2233 /* Calling a normal function -- only set to zero if we know our g14
2236 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
, const0_rtx
));
2240 emit_call_insn (gen_rtx (SET
, VOIDmode
, target
,
2241 gen_rtx (CALL
, VOIDmode
, first_operand
,
2244 emit_call_insn (gen_rtx (CALL
, VOIDmode
, first_operand
, second_operand
));
2247 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
, g14_save_reg
));
2248 else if (GET_CODE (second_operand
) != CONST_INT
2249 || INTVAL (second_operand
) > 48)
2251 /* Calling a function needing an argument block. It will have set
2252 reg14 back to zero before returning, so we must emit a clobber here
2253 to tell cse that g14 has changed. */
2254 emit_insn (gen_rtx (CLOBBER
, VOIDmode
, arg_pointer_rtx
));
2258 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2259 function unit it executed on. */
2261 /* ??? This would make more sense as an attribute. */
2264 i960_scan_opcode (p
)
2276 /* Ret is not actually of type REG, but it won't matter, because no
2277 insn will ever follow it. */
2280 i960_last_insn_type
= I_TYPE_REG
;
2284 if (p
[1] == 'x' || p
[3] == 'x')
2285 i960_last_insn_type
= I_TYPE_MEM
;
2286 i960_last_insn_type
= I_TYPE_CTRL
;
2291 i960_last_insn_type
= I_TYPE_CTRL
;
2298 i960_last_insn_type
= I_TYPE_MEM
;
2300 i960_last_insn_type
= I_TYPE_CTRL
;
2302 else if (p
[1] == 'm')
2305 i960_last_insn_type
= I_TYPE_REG
;
2306 else if (p
[4] == 'b' || p
[4] == 'j')
2307 i960_last_insn_type
= I_TYPE_CTRL
;
2309 i960_last_insn_type
= I_TYPE_REG
;
2312 i960_last_insn_type
= I_TYPE_REG
;
2316 i960_last_insn_type
= I_TYPE_MEM
;
2321 i960_last_insn_type
= I_TYPE_MEM
;
2323 i960_last_insn_type
= I_TYPE_REG
;