1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
49 rtx i960_compare_op0
, i960_compare_op1
;
51 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
54 static int i960_maxbitalignment
;
55 static int i960_last_maxbitalignment
;
57 /* Used to implement switching between MEM and ALU insn types, for better
58 C series performance. */
60 enum insn_types i960_last_insn_type
;
62 /* The leaf-procedure return register. Set only if this is a leaf routine. */
64 static int i960_leaf_ret_reg
;
66 /* True if replacing tail calls with jumps is OK. */
68 static int tail_call_ok
;
70 /* A string containing a list of insns to emit in the epilogue so as to
71 restore all registers saved by the prologue. Created by the prologue
72 code as it saves registers away. */
74 char epilogue_string
[1000];
76 /* A unique number (per function) for return labels. */
78 static int ret_label
= 0;
80 /* This is true if FNDECL is either a varargs or a stdarg function.
81 This is used to help identify functions that use an argument block. */
83 #define VARARGS_STDARG_FUNCTION(FNDECL) \
84 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
85 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
86 || current_function_varargs)
88 /* Handle pragmas for compatibility with Intel's compilers. */
90 /* ??? This is incomplete, since it does not handle all pragmas that the
91 intel compilers understand. */
94 process_pragma (finput
, t
)
100 register char *pname
;
102 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
105 pname
= IDENTIFIER_POINTER (t
);
107 if (strcmp (pname
, "align") == 0)
115 } while (c
== ' ' || c
== '\t');
119 while (c
>= '0' && c
<= '9')
121 if (s
< buf
+ sizeof buf
- 1)
127 /* We had to read a non-numerical character to get out of the
128 while loop---often a newline. So, we have to put it back to
129 make sure we continue to parse everything properly. */
136 /* Return to last alignment. */
137 align
= i960_last_maxbitalignment
/ 8;
144 i960_last_maxbitalignment
= i960_maxbitalignment
;
145 i960_maxbitalignment
= align
* 8;
149 /* Silently ignore bad values. */
153 /* NOTE: ic960 R3.0 pragma align definition:
155 #pragma align [(size)] | (identifier=size[,...])
156 #pragma noalign [(identifier)[,...]]
158 (all parens are optional)
160 - size is [1,2,4,8,16]
161 - noalign means size==1
162 - applies only to component elements of a struct (and union?)
163 - identifier applies to structure tag (only)
164 - missing identifier means next struct
166 - alignment rules for bitfields need more investigation */
171 /* Should be pragma 'far' or equivalent for callx/balx here. */
176 /* Initialize variables before compiling any files. */
181 if (TARGET_IC_COMPAT2_0
)
183 i960_maxbitalignment
= 8;
184 i960_last_maxbitalignment
= 128;
188 i960_maxbitalignment
= 128;
189 i960_last_maxbitalignment
= 8;
193 /* Return true if OP can be used as the source of an fp move insn. */
196 fpmove_src_operand (op
, mode
)
198 enum machine_mode mode
;
200 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
204 /* Return true if OP is a register or zero. */
207 reg_or_zero_operand (op
, mode
)
209 enum machine_mode mode
;
211 return register_operand (op
, mode
) || op
== const0_rtx
;
215 /* Return truth value of whether OP can be used as an operands in a three
216 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
219 arith_operand (op
, mode
)
221 enum machine_mode mode
;
223 return (register_operand (op
, mode
) || literal (op
, mode
));
226 /* Return truth value of whether OP can be used as an operands in a three
227 address logic insn, possibly complementing OP, of mode MODE. */
230 logic_operand (op
, mode
)
232 enum machine_mode mode
;
234 return (register_operand (op
, mode
)
235 || (GET_CODE (op
) == CONST_INT
236 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
239 /* Return true if OP is a register or a valid floating point literal. */
242 fp_arith_operand (op
, mode
)
244 enum machine_mode mode
;
246 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
249 /* Return true is OP is a register or a valid signed integer literal. */
252 signed_arith_operand (op
, mode
)
254 enum machine_mode mode
;
256 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
259 /* Return truth value of whether OP is a integer which fits the
260 range constraining immediate operands in three-address insns. */
265 enum machine_mode mode
;
267 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
270 /* Return true if OP is a float constant of 1. */
273 fp_literal_one (op
, mode
)
275 enum machine_mode mode
;
277 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
280 /* Return true if OP is a float constant of 0. */
283 fp_literal_zero (op
, mode
)
285 enum machine_mode mode
;
287 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
290 /* Return true if OP is a valid floating point literal. */
295 enum machine_mode mode
;
297 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
300 /* Return true if OP is a valid signed immediate constant. */
303 signed_literal(op
, mode
)
305 enum machine_mode mode
;
307 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
310 /* Return truth value of statement that OP is a symbolic memory
311 operand of mode MODE. */
314 symbolic_memory_operand (op
, mode
)
316 enum machine_mode mode
;
318 if (GET_CODE (op
) == SUBREG
)
319 op
= SUBREG_REG (op
);
320 if (GET_CODE (op
) != MEM
)
323 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
324 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
327 /* Return truth value of whether OP is EQ or NE. */
332 enum machine_mode mode
;
334 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
337 /* OP is an integer register or a constant. */
340 arith32_operand (op
, mode
)
342 enum machine_mode mode
;
344 if (register_operand (op
, mode
))
346 return (CONSTANT_P (op
));
349 /* Return true if OP is an integer constant which is a power of 2. */
352 power2_operand (op
,mode
)
354 enum machine_mode mode
;
356 if (GET_CODE (op
) != CONST_INT
)
359 return exact_log2 (INTVAL (op
)) >= 0;
362 /* Return true if OP is an integer constant which is the complement of a
366 cmplpower2_operand (op
, mode
)
368 enum machine_mode mode
;
370 if (GET_CODE (op
) != CONST_INT
)
373 return exact_log2 (~ INTVAL (op
)) >= 0;
376 /* If VAL has only one bit set, return the index of that bit. Otherwise
385 for (i
= 0; val
!= 0; i
++, val
>>= 1)
397 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
398 The return value indicates how many consecutive non-zero bits exist
399 if this is a mask. This is the same as the next function, except that
400 it does not indicate what the start and stop bit positions are. */
406 register int start
, end
, i
;
409 for (i
= 0; val
!= 0; val
>>= 1, i
++)
419 /* Still looking for the first bit. */
423 /* We've seen the start of a bit sequence, and now a zero. There
424 must be more one bits, otherwise we would have exited the loop.
425 Therefore, it is not a mask. */
430 /* The bit string has ones from START to END bit positions only. */
431 return end
- start
+ 1;
434 /* If VAL is a mask, then return nonzero, with S set to the starting bit
435 position and E set to the ending bit position of the mask. The return
436 value indicates how many consecutive bits exist in the mask. This is
437 the same as the previous function, except that it also indicates the
438 start and end bit positions of the mask. */
445 register int start
, end
, i
;
449 for (i
= 0; val
!= 0; val
>>= 1, i
++)
460 /* Still looking for the first bit. */
464 /* We've seen the start of a bit sequence, and now a zero. There
465 must be more one bits, otherwise we would have exited the loop.
466 Therefor, it is not a mask. */
475 /* The bit string has ones from START to END bit positions only. */
478 return ((start
< 0) ? 0 : end
- start
+ 1);
481 /* Return the machine mode to use for a comparison. */
484 select_cc_mode (op
, x
)
488 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
493 /* X and Y are two things to compare using CODE. Emit the compare insn and
494 return the rtx for register 36 in the proper mode. */
497 gen_compare_reg (code
, x
, y
)
502 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
503 enum machine_mode mode
504 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
508 if (! arith_operand (x
, mode
))
509 x
= force_reg (SImode
, x
);
510 if (! arith_operand (y
, mode
))
511 y
= force_reg (SImode
, y
);
514 cc_reg
= gen_rtx (REG
, ccmode
, 36);
515 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
516 gen_rtx (COMPARE
, ccmode
, x
, y
)));
521 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
522 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
523 are 4. Indexed addresses are cost 6. */
525 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
528 i960_address_cost (x
)
532 /* Handled before calling here. */
533 if (GET_CODE (x
) == REG
)
536 if (GET_CODE (x
) == PLUS
)
538 rtx base
= XEXP (x
, 0);
539 rtx offset
= XEXP (x
, 1);
541 if (GET_CODE (base
) == SUBREG
)
542 base
= SUBREG_REG (base
);
543 if (GET_CODE (offset
) == SUBREG
)
544 offset
= SUBREG_REG (offset
);
546 if (GET_CODE (base
) == REG
)
548 if (GET_CODE (offset
) == REG
)
550 if (GET_CODE (offset
) == CONST_INT
)
552 if ((unsigned)INTVAL (offset
) < 2047)
556 if (CONSTANT_P (offset
))
559 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
562 /* This is an invalid address. The return value doesn't matter, but
563 for convenience we make this more expensive than anything else. */
566 if (GET_CODE (x
) == MULT
)
569 /* Symbol_refs and other unrecognized addresses are cost 4. */
573 /* Emit insns to move operands[1] into operands[0].
575 Return 1 if we have written out everything that needs to be done to
576 do the move. Otherwise, return 0 and the caller will emit the move
580 emit_move_sequence (operands
, mode
)
582 enum machine_mode mode
;
584 /* We can only store registers to memory. */
586 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
587 operands
[1] = force_reg (mode
, operands
[1]);
589 /* Storing multi-word values in unaligned hard registers to memory may
590 require a scratch since we have to store them a register at a time and
591 adding 4 to the memory address may not yield a valid insn. */
592 /* ??? We don't always need the scratch, but that would complicate things.
594 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
595 && GET_CODE (operands
[0]) == MEM
596 && GET_CODE (operands
[1]) == REG
597 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
598 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
600 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
602 gen_rtx (SET
, VOIDmode
,
603 operands
[0], operands
[1]),
604 gen_rtx (CLOBBER
, VOIDmode
,
605 gen_rtx (SCRATCH
, Pmode
)))));
612 /* Output assembler to move a double word value. */
615 i960_output_move_double (dst
, src
)
620 if (GET_CODE (dst
) == REG
621 && GET_CODE (src
) == REG
)
623 if ((REGNO (src
) & 1)
624 || (REGNO (dst
) & 1))
626 /* We normally copy the low-numbered register first. However, if
627 the second source register is the same as the first destination
628 register, we must copy in the opposite order. */
629 if (REGNO (src
) + 1 == REGNO (dst
))
630 return "mov %D1,%D0\n\tmov %1,%0";
632 return "mov %1,%0\n\tmov %D1,%D0";
637 else if (GET_CODE (dst
) == REG
638 && GET_CODE (src
) == CONST_INT
639 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
642 return "mov %1,%0\n\tmov 0,%D0";
646 else if (GET_CODE (dst
) == REG
647 && GET_CODE (src
) == MEM
)
651 /* One can optimize a few cases here, but you have to be
652 careful of clobbering registers used in the address and
656 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
657 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
658 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
659 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
665 else if (GET_CODE (dst
) == MEM
666 && GET_CODE (src
) == REG
)
670 /* This is handled by emit_move_sequence so we shouldn't get here. */
679 /* Output assembler to move a quad word value. */
682 i960_output_move_quad (dst
, src
)
687 if (GET_CODE (dst
) == REG
688 && GET_CODE (src
) == REG
)
690 if ((REGNO (src
) & 3)
691 || (REGNO (dst
) & 3))
693 /* We normally copy starting with the low numbered register.
694 However, if there is an overlap such that the first dest reg
695 is <= the last source reg but not < the first source reg, we
696 must copy in the opposite order. */
697 if (REGNO (dst
) <= REGNO (src
) + 3
698 && REGNO (dst
) >= REGNO (src
))
699 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
701 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
706 else if (GET_CODE (dst
) == REG
707 && GET_CODE (src
) == CONST_INT
708 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
711 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
715 else if (GET_CODE (dst
) == REG
716 && GET_CODE (src
) == MEM
)
720 /* One can optimize a few cases here, but you have to be
721 careful of clobbering registers used in the address and
725 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
726 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
727 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
728 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
729 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
730 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
736 else if (GET_CODE (dst
) == MEM
737 && GET_CODE (src
) == REG
)
741 /* This is handled by emit_move_sequence so we shouldn't get here. */
750 /* Emit insns to load a constant to non-floating point registers.
751 Uses several strategies to try to use as few insns as possible. */
754 i960_output_ldconst (dst
, src
)
755 register rtx dst
, src
;
758 register unsigned rsrc2
;
759 enum machine_mode mode
= GET_MODE (dst
);
762 operands
[0] = operands
[2] = dst
;
763 operands
[1] = operands
[3] = src
;
765 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
766 must be a ldconst insn. */
768 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
770 output_asm_insn ("ldconst %1,%0", operands
);
773 else if (mode
== XFmode
)
779 if (fp_literal_zero (src
, XFmode
))
782 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
783 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
785 output_asm_insn ("# ldconst %1,%0",operands
);
787 for (i
= 0; i
< 3; i
++)
789 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
790 operands
[1] = GEN_INT (value_long
[i
]);
791 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
797 else if (mode
== DFmode
)
801 if (fp_literal_zero (src
, DFmode
))
804 split_double (src
, &first
, &second
);
806 output_asm_insn ("# ldconst %1,%0",operands
);
808 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
810 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
812 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
813 operands
[1] = second
;
814 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
818 else if (mode
== SFmode
)
823 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
824 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
826 output_asm_insn ("# ldconst %1,%0",operands
);
827 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
828 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
829 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
833 else if (mode
== TImode
)
835 /* ??? This is currently not handled at all. */
838 /* Note: lowest order word goes in lowest numbered reg. */
839 rsrc1
= INTVAL (src
);
840 if (rsrc1
>= 0 && rsrc1
< 32)
843 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
844 /* Go pick up the low-order word. */
846 else if (mode
== DImode
)
848 rtx upperhalf
, lowerhalf
, xoperands
[2];
850 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
851 split_double (src
, &lowerhalf
, &upperhalf
);
856 /* Note: lowest order word goes in lowest numbered reg. */
857 /* Numbers from 0 to 31 can be handled with a single insn. */
858 rsrc1
= INTVAL (lowerhalf
);
859 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
862 /* Output the upper half with a recursive call. */
863 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
864 xoperands
[1] = upperhalf
;
865 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
867 /* The lower word is emitted as normally. */
871 rsrc1
= INTVAL (src
);
877 else if (mode
== HImode
)
886 /* ldconst 0..31,X -> mov 0..31,X */
889 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
894 /* ldconst 32..63,X -> add 31,nn,X */
897 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
899 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
900 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
906 /* ldconst -1..-31 -> sub 0,0..31,X */
909 /* return 'sub -(%1),0,%0' */
910 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
911 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
915 /* ldconst -32 -> not 31,X */
918 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
919 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
924 /* If const is a single bit. */
925 if (bitpos (rsrc1
) >= 0)
927 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
928 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
932 /* If const is a bit string of less than 6 bits (1..31 shifted). */
937 if (bitstr (rsrc1
, &s
, &e
) < 6)
939 rsrc2
= ((unsigned int) rsrc1
) >> s
;
940 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
941 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
942 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
947 /* Unimplemented cases:
948 const is in range 0..31 but rotated around end of word:
949 ror 31,3,g0 -> ldconst 0xe0000003,g0
951 and any 2 instruction cases that might be worthwhile */
953 output_asm_insn ("ldconst %1,%0", operands
);
957 /* Determine if there is an opportunity for a bypass optimization.
958 Bypass succeeds on the 960K* if the destination of the previous
959 instruction is the second operand of the current instruction.
960 Bypass always succeeds on the C*.
962 Return 1 if the pattern should interchange the operands.
964 CMPBR_FLAG is true if this is for a compare-and-branch insn.
965 OP1 and OP2 are the two source operands of a 3 operand insn. */
968 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
969 register rtx insn
, op1
, op2
;
972 register rtx prev_insn
, prev_dest
;
977 /* Can't do this if op1 isn't a register. */
981 /* Can't do this for a compare-and-branch if both ops aren't regs. */
982 if (cmpbr_flag
&& ! REG_P (op2
))
985 prev_insn
= prev_real_insn (insn
);
987 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
988 && GET_CODE (PATTERN (prev_insn
)) == SET
)
990 prev_dest
= SET_DEST (PATTERN (prev_insn
));
991 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
992 || (GET_CODE (prev_dest
) == SUBREG
993 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
994 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1000 /* Output the code which declares the function name. This also handles
1001 leaf routines, which have special requirements, and initializes some
1002 global variables. */
1005 i960_function_name_declare (file
, name
, fndecl
)
1014 /* Increment global return label. */
1018 /* Compute whether tail calls and leaf routine optimizations can be performed
1019 for this function. */
1021 if (TARGET_TAILCALL
)
1026 if (TARGET_LEAFPROC
)
1031 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1032 argblock, because argblock uses g14 implicitly. */
1034 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1040 /* See if caller passes in an address to return value. */
1042 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1048 /* Can not use tail calls or make this a leaf routine if there is a non
1051 if (get_frame_size () != 0)
1054 /* I don't understand this condition, and do not think that it is correct.
1055 Apparently this is just checking whether the frame pointer is used, and
1056 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1059 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1060 if (GET_CODE (insn
) == INSN
1061 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1067 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1070 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1071 if (GET_CODE (insn
) == CALL_INSN
)
1077 /* Can not be a leaf routine if any non-call clobbered registers are
1078 used in this function. */
1081 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1082 if (regs_ever_live
[i
]
1083 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1085 /* Global registers. */
1086 if (i
< 16 && i
> 7 && i
!= 13)
1088 /* Local registers. */
1093 /* Now choose a leaf return register, if we can find one, and if it is
1094 OK for this to be a leaf routine. */
1096 i960_leaf_ret_reg
= -1;
1098 if (optimize
&& leaf_proc_ok
)
1100 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1101 if (regs_ever_live
[i
] == 0)
1103 i960_leaf_ret_reg
= i
;
1104 regs_ever_live
[i
] = 1;
1109 /* Do this after choosing the leaf return register, so it will be listed
1110 if one was chosen. */
1112 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1113 fprintf (file
, "\t# Registers used: ");
1115 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1117 if (regs_ever_live
[i
])
1119 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1121 if (i
> 15 && j
== 0)
1123 fprintf (file
,"\n\t#\t\t ");
1129 fprintf (file
, "\n");
1131 if (i960_leaf_ret_reg
>= 0)
1133 /* Make it a leaf procedure. */
1135 if (TREE_PUBLIC (fndecl
))
1136 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1138 fprintf (file
, "\t.leafproc\t");
1139 assemble_name (file
, name
);
1140 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1141 ASM_OUTPUT_LABEL (file
, name
);
1142 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1143 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1144 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1146 if (TARGET_C_SERIES
)
1148 fprintf (file
, "\tlda 0,g14\n");
1149 i960_last_insn_type
= I_TYPE_MEM
;
1153 fprintf (file
, "\tmov 0,g14\n");
1154 i960_last_insn_type
= I_TYPE_REG
;
1159 ASM_OUTPUT_LABEL (file
, name
);
1160 i960_last_insn_type
= I_TYPE_CTRL
;
1164 /* Compute and return the frame size. */
1167 compute_frame_size (size
)
1171 int outgoing_args_size
= current_function_outgoing_args_size
;
1173 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1174 as size is concerned. */
1175 actual_fsize
= (size
+ 15) & -16;
1176 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1178 return actual_fsize
;
1181 /* Output code for the function prologue. */
1184 i960_function_prologue (file
, size
)
1188 register int i
, j
, nr
;
1191 int actual_fsize
, offset
;
1193 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1195 int regs
[FIRST_PSEUDO_REGISTER
];
1197 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1198 if (regs_ever_live
[i
]
1199 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1202 /* Count global registers that need saving. */
1209 epilogue_string
[0] = '\0';
1211 if (profile_flag
|| profile_block_flag
)
1213 /* When profiling, we may use registers 20 to 27 to save arguments, so
1214 they can't be used here for saving globals. J is the number of
1215 argument registers the mcount call will save. */
1216 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1219 for (i
= 20; i
<= j
+ 20; i
++)
1223 /* First look for local registers to save globals in. */
1224 for (i
= 0; i
< 16; i
++)
1229 /* Start at r4, not r3. */
1230 for (j
= 20; j
< 32; j
++)
1237 regs_ever_live
[j
] = 1;
1239 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1240 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1245 regs_ever_live
[j
+1] = 1;
1247 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1248 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1253 regs_ever_live
[j
+2] = 1;
1255 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1260 regs_ever_live
[j
+3] = 1;
1263 fprintf (file
, "\tmov%s %s,%s\n",
1266 (nr
== 2) ? "l" : ""),
1267 reg_names
[i
], reg_names
[j
]);
1268 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1271 (nr
== 2) ? "l" : ""),
1272 reg_names
[j
], reg_names
[i
]);
1273 strcat (epilogue_string
, tmpstr
);
1281 /* N_iregs is now the number of global registers that haven't been saved
1284 rsize
= (n_iregs
* 4);
1285 actual_fsize
= compute_frame_size (size
) + rsize
;
1287 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1288 size up to the nearest multiple of 16. I don't know whether this is
1289 necessary, or even desirable.
1291 The frame pointer must be aligned, but the call instruction takes care of
1292 that. If we leave the stack pointer unaligned, we may save a little on
1293 dynamic stack allocation. And we don't lose, at least according to the
1295 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1298 /* Allocate space for register save and locals. */
1299 if (actual_fsize
> 0)
1301 if (actual_fsize
< 32)
1302 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1304 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1307 /* Take hardware register save area created by the call instruction
1308 into account, but store them before the argument block area. */
1309 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1310 /* Save registers on stack if needed. */
1311 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1318 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1321 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1325 if (nr
== 3 && regs
[i
+3] == -1)
1328 fprintf (file
,"\tst%s %s,%d(fp)\n",
1331 (nr
== 2) ? "l" : ""),
1332 reg_names
[i
], offset
);
1333 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1336 (nr
== 2) ? "l" : ""),
1337 offset
, reg_names
[i
]);
1338 strcat (epilogue_string
, tmpstr
);
1344 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1347 fprintf (file
, "\t#Prologue stats:\n");
1348 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1351 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1353 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1355 fprintf (file
, "\t#End Prologue#\n");
1358 /* Output code for the function profiler. */
1361 output_function_profiler (file
, labelno
)
1365 /* The last used parameter register. */
1367 int i
, j
, increment
;
1368 int varargs_stdarg_function
1369 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1371 /* Figure out the last used parameter register. The proper thing to do
1372 is to walk incoming args of the function. A function might have live
1373 parameter registers even if it has no incoming args. Note that we
1374 don't have to save parameter registers g8 to g11 because they are
1377 /* See also output_function_prologue, which tries to use local registers
1378 for preserved call-saved global registers. */
1380 for (last_parm_reg
= 7;
1381 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1385 /* Save parameter registers in regs r4 (20) to r11 (27). */
1387 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1389 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1391 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1393 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1398 fprintf (file
, "\tmov%s g%d,r%d\n",
1399 (increment
== 4 ? "q" : increment
== 3 ? "t"
1400 : increment
== 2 ? "l": ""), i
, j
);
1403 /* If this function uses the arg pointer, then save it in r3 and then
1406 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1407 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1409 /* Load location address into g0 and call mcount. */
1411 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1413 /* If this function uses the arg pointer, restore it. */
1415 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1416 fprintf (file
, "\tmov r3,g14\n");
1418 /* Restore parameter registers. */
1420 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1422 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1424 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1426 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1431 fprintf (file
, "\tmov%s r%d,g%d\n",
1432 (increment
== 4 ? "q" : increment
== 3 ? "t"
1433 : increment
== 2 ? "l": ""), j
, i
);
1437 /* Output code for the function epilogue. */
1440 i960_function_epilogue (file
, size
)
1444 if (i960_leaf_ret_reg
>= 0)
1446 fprintf (file
, "LR%d: ret\n", ret_label
);
1450 if (*epilogue_string
== 0)
1454 /* Emit a return insn, but only if control can fall through to here. */
1456 tmp
= get_last_insn ();
1459 if (GET_CODE (tmp
) == BARRIER
)
1461 if (GET_CODE (tmp
) == CODE_LABEL
)
1463 if (GET_CODE (tmp
) == JUMP_INSN
)
1465 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1469 if (GET_CODE (tmp
) == NOTE
)
1471 tmp
= PREV_INSN (tmp
);
1476 fprintf (file
, "LR%d: ret\n", ret_label
);
1480 fprintf (file
, "LR%d:\n", ret_label
);
1482 fprintf (file
, "\t#EPILOGUE#\n");
1484 /* Output the string created by the prologue which will restore all
1485 registers saved by the prologue. */
1487 if (epilogue_string
[0] != '\0')
1488 fprintf (file
, "%s", epilogue_string
);
1490 /* Must clear g14 on return if this function set it.
1491 Only varargs/stdarg functions modify g14. */
1493 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1494 fprintf (file
, "\tmov 0,g14\n");
1496 fprintf (file
, "\tret\n");
1497 fprintf (file
, "\t#End Epilogue#\n");
1500 /* Output code for a call insn. */
1503 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1504 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1506 int argsize
= INTVAL (argsize_rtx
);
1507 rtx nexti
= next_real_insn (insn
);
1509 int varargs_stdarg_function
1510 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1512 operands
[0] = target
;
1513 operands
[1] = arg_pointer
;
1515 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1516 output_asm_insn ("mov g14,r3", operands
);
1519 output_asm_insn ("lda %a1,g14", operands
);
1520 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1521 output_asm_insn ("mov 0,g14", operands
);
1523 /* The code used to assume that calls to SYMBOL_REFs could not be more
1524 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1525 feature is now implemented by relaxing in the GNU linker. It can convert
1526 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1528 /* Nexti could be zero if the called routine is volatile. */
1529 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1530 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1532 /* Delete following return insn. */
1533 if (nexti
&& no_labels_between_p (insn
, nexti
))
1534 delete_insn (nexti
);
1535 output_asm_insn ("bx %0", operands
);
1536 return "# notreached";
1539 output_asm_insn ("callx %0", operands
);
1541 /* If the caller sets g14 to the address of the argblock, then the caller
1542 must clear it after the return. */
1544 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1545 output_asm_insn ("mov r3,g14", operands
);
1546 else if (argsize
> 48)
1547 output_asm_insn ("mov 0,g14", operands
);
1552 /* Output code for a return insn. */
1555 i960_output_ret_insn (insn
)
1558 static char lbuf
[20];
1560 if (*epilogue_string
!= 0)
1562 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1565 sprintf (lbuf
, "b LR%d", ret_label
);
1569 /* Must clear g14 on return if this function set it.
1570 Only varargs/stdarg functions modify g14. */
1572 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1573 output_asm_insn ("mov 0,g14", 0);
1575 if (i960_leaf_ret_reg
>= 0)
1577 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1584 /* Return a character string representing the branch prediction
1585 opcode to be tacked on an instruction. This must at least
1586 return a null string. */
1589 i960_br_predict_opcode (lab_ref
, insn
)
1592 if (TARGET_BRANCH_PREDICT
)
1594 unsigned long label_uid
;
1596 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1597 label_uid
= INSN_UID (lab_ref
);
1598 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1599 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1603 /* If not optimizing, then the insn_addresses array will not be
1604 valid. In this case, always return ".t" since most branches
1605 are taken. If optimizing, return .t for backward branches
1606 and .f for forward branches. */
1608 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1617 /* Print the operand represented by rtx X formatted by code CODE. */
1620 i960_print_operand (file
, x
, code
)
1625 enum rtx_code rtxcode
= GET_CODE (x
);
1632 /* Second reg of a double or quad. */
1633 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1637 /* Third reg of a quad. */
1638 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1642 /* Fourth reg of a quad. */
1643 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1647 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1655 else if (rtxcode
== MEM
)
1657 output_address (XEXP (x
, 0));
1660 else if (rtxcode
== CONST_INT
)
1662 HOST_WIDE_INT val
= INTVAL (x
);
1665 if (val
> 9999 || val
< -999)
1666 fprintf (file
, "0x%x", val
);
1668 fprintf (file
, "%d", val
);
1671 else if (rtxcode
== CONST_DOUBLE
)
1676 if (x
== CONST0_RTX (GET_MODE (x
)))
1678 fprintf (file
, "0f0.0");
1681 else if (x
== CONST1_RTX (GET_MODE (x
)))
1683 fprintf (file
, "0f1.0");
1687 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1688 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1689 fprintf (file
, "0f%s", dstr
);
1696 /* Branch or jump, depending on assembler. */
1697 if (TARGET_ASM_COMPAT
)
1704 /* Sign of condition. */
1705 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1706 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1708 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1709 || (rtxcode
== GE
) || (rtxcode
== LE
))
1716 /* Inverted condition. */
1717 rtxcode
= reverse_condition (rtxcode
);
1721 /* Inverted condition w/ reversed operands. */
1722 rtxcode
= reverse_condition (rtxcode
);
1726 /* Reversed operand condition. */
1727 rtxcode
= swap_condition (rtxcode
);
1731 /* Normal condition. */
1733 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1734 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1735 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1736 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1737 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1738 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1739 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1740 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1741 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1742 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1747 output_addr_const (file
, x
);
1757 /* Print a memory address as an operand to reference that memory location.
1759 This is exactly the same as legitimate_address_p, except that it the prints
1760 addresses instead of recognizing them. */
1763 i960_print_operand_addr (file
, addr
)
1775 if (GET_CODE (addr
) == REG
)
1777 else if (CONSTANT_P (addr
))
1779 else if (GET_CODE (addr
) == PLUS
)
1783 op0
= XEXP (addr
, 0);
1784 op1
= XEXP (addr
, 1);
1786 if (GET_CODE (op0
) == REG
)
1789 if (GET_CODE (op1
) == REG
)
1791 else if (CONSTANT_P (op1
))
1796 else if (GET_CODE (op0
) == PLUS
)
1798 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1800 ireg
= XEXP (XEXP (op0
, 0), 0);
1801 scale
= XEXP (XEXP (op0
, 0), 1);
1802 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1804 breg
= XEXP (op0
, 1);
1810 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1812 breg
= XEXP (op0
, 0);
1813 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1815 ireg
= XEXP (op0
, 1);
1824 else if (GET_CODE (op0
) == MULT
)
1826 ireg
= XEXP (op0
, 0);
1827 scale
= XEXP (op0
, 1);
1828 if (GET_CODE (op1
) == REG
)
1830 else if (CONSTANT_P (op1
))
1838 else if (GET_CODE (addr
) == MULT
)
1840 ireg
= XEXP (addr
, 0);
1841 scale
= XEXP (addr
, 1);
1847 output_addr_const (file
, offset
);
1849 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1851 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1854 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1855 that is a valid memory address for an instruction.
1856 The MODE argument is the machine mode for the MEM expression
1857 that wants to use this address.
1859 On 80960, legitimate addresses are:
1861 disp (12 or 32 bit) ld foo,r0
1862 base + index ld (g0)[g1*1],r0
1863 base + displ ld 0xf00(g0),r0
1864 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1865 index*scale + base ld (g0)[g1*4],r0
1866 index*scale + displ ld 0xf00[g1*4],r0
1867 index*scale ld [g1*4],r0
1868 index + base + displ ld 0xf00(g0)[g1*1],r0
1870 In each case, scale can be 1, 2, 4, 8, or 16. */
1872 /* This is exactly the same as i960_print_operand_addr, except that
1873 it recognizes addresses instead of printing them.
1875 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1876 convert common non-canonical forms to canonical form so that they will
1879 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1880 where a register is valid. */
1882 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1883 ((GET_CODE (X) == REG \
1884 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1885 || (GET_CODE (X) == SUBREG \
1886 && GET_CODE (SUBREG_REG (X)) == REG \
1887 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1888 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1890 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1891 ((GET_CODE (X) == REG \
1892 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1893 || (GET_CODE (X) == SUBREG \
1894 && GET_CODE (SUBREG_REG (X)) == REG \
1895 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1896 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1899 legitimate_address_p (mode
, addr
, strict
)
1900 enum machine_mode mode
;
1904 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1906 else if (CONSTANT_P (addr
))
1908 else if (GET_CODE (addr
) == PLUS
)
1912 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1915 op0
= XEXP (addr
, 0);
1916 op1
= XEXP (addr
, 1);
1918 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1920 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1922 else if (CONSTANT_P (op1
))
1927 else if (GET_CODE (op0
) == PLUS
)
1929 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1931 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1932 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1935 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1936 && CONSTANT_P (op1
))
1941 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1943 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1944 && CONSTANT_P (op1
))
1952 else if (GET_CODE (op0
) == MULT
)
1954 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1955 && SCALE_TERM_P (XEXP (op0
, 1))))
1958 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1960 else if (CONSTANT_P (op1
))
1968 else if (GET_CODE (addr
) == MULT
)
1970 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1973 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1974 && SCALE_TERM_P (XEXP (addr
, 1)));
1980 /* Try machine-dependent ways of modifying an illegitimate address
1981 to be legitimate. If we find one, return the new, valid address.
1982 This macro is used in only one place: `memory_address' in explow.c.
1984 This converts some non-canonical addresses to canonical form so they
1985 can be recognized. */
1988 legitimize_address (x
, oldx
, mode
)
1991 enum machine_mode mode
;
1993 if (GET_CODE (x
) == SYMBOL_REF
)
1996 x
= copy_to_reg (x
);
1999 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2002 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2003 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2004 created by virtual register instantiation, register elimination, and
2005 similar optimizations. */
2006 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2007 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2008 x
= gen_rtx (PLUS
, Pmode
,
2009 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2010 XEXP (XEXP (x
, 1), 1));
2012 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2013 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2014 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2015 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2016 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2017 && CONSTANT_P (XEXP (x
, 1)))
2019 rtx constant
, other
;
2021 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2023 constant
= XEXP (x
, 1);
2024 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2026 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2028 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2029 other
= XEXP (x
, 1);
2035 x
= gen_rtx (PLUS
, Pmode
,
2036 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2037 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2038 plus_constant (other
, INTVAL (constant
)));
2045 /* Return the most stringent alignment that we are willing to consider
2046 objects of size SIZE and known alignment ALIGN as having. */
2049 i960_alignment (size
, align
)
2055 if (! TARGET_STRICT_ALIGN
)
2056 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2058 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2067 /* Modes for condition codes. */
2069 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2071 /* Modes for single-word (and smaller) quantities. */
2074 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2075 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2077 /* Modes for double-word (and smaller) quantities. */
2080 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2082 /* Modes for quad-word quantities. */
2083 #define T_MODES (~C_MODES)
2085 /* Modes for single-float quantities. */
2086 #define SF_MODES ((1 << (int) SFmode))
2088 /* Modes for double-float quantities. */
2089 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2091 /* Modes for quad-float quantities. */
2092 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2094 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
2095 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2096 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2097 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2098 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2100 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
2103 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2104 advantage of machine specific facts, such as knowing that the frame pointer
2105 is always 16 byte aligned. */
2108 i960_expr_alignment (x
, size
)
2117 switch (GET_CODE(x
))
2122 if ((align
& 0xf) == 0)
2124 else if ((align
& 0x7) == 0)
2126 else if ((align
& 0x3) == 0)
2128 else if ((align
& 0x1) == 0)
2135 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2136 i960_expr_alignment (XEXP (x
, 1), size
));
2140 /* If this is a valid program, objects are guaranteed to be
2141 correctly aligned for whatever size the reference actually is. */
2142 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2146 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2151 align
= i960_expr_alignment (XEXP (x
, 0));
2153 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2155 align
= align
<< INTVAL (XEXP (x
, 1));
2156 align
= MIN (align
, 16);
2161 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2162 i960_expr_alignment (XEXP (x
, 1), size
));
2164 align
= MIN (align
, 16);
2171 /* Return true if it is possible to reference both BASE and OFFSET, which
2172 have alignment at least as great as 4 byte, as if they had alignment valid
2173 for an object of size SIZE. */
2176 i960_improve_align (base
, offset
, size
)
2183 /* We have at least a word reference to the object, so we know it has to
2184 be aligned at least to 4 bytes. */
2186 i
= MIN (i960_expr_alignment (base
, 4),
2187 i960_expr_alignment (offset
, 4));
2191 /* We know the size of the request. If strict align is not enabled, we
2192 can guess that the alignment is OK for the requested size. */
2194 if (! TARGET_STRICT_ALIGN
)
2195 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2201 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2202 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2205 i960_si_ti (base
, offset
)
2209 return i960_improve_align (base
, offset
, 16);
2212 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2213 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2216 i960_si_di (base
, offset
)
2220 return i960_improve_align (base
, offset
, 8);
2223 /* Return raw values of size and alignment (in words) for the data
2224 type being accessed. These values will be rounded by the caller. */
2227 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2228 enum machine_mode mode
;
2235 /* Use formal alignment requirements of type being passed, except make
2236 it at least a word. If we don't have a type, this is a library call,
2237 and the parm has to be of scalar type. In this case, consider its
2238 formal alignment requirement to be its size in words. */
2240 if (mode
== BLKmode
)
2241 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2242 else if (mode
== VOIDmode
)
2244 /* End of parm list. */
2245 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2249 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2253 /* ??? This is a hack to properly correct the alignment of XFmode
2254 values without affecting anything else. */
2260 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2261 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2269 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2270 Any arg that is bigger than 4 words is placed on the stack and all
2271 subsequent arguments are placed on the stack.
2273 Additionally, parameters with an alignment requirement stronger than
2274 a word must be aligned appropriately. Note that this means that a
2275 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2276 passed in an odd/even register pair. */
2278 /* Update CUM to advance past an argument described by MODE and TYPE. */
2281 i960_function_arg_advance (cum
, mode
, type
, named
)
2282 CUMULATIVE_ARGS
*cum
;
2283 enum machine_mode mode
;
2289 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2291 if (size
> 4 || cum
->ca_nstackparms
!= 0
2292 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2293 || MUST_PASS_IN_STACK (mode
, type
))
2295 /* Indicate that all the registers are in use, even if all are not,
2296 so va_start will compute the right value. */
2297 cum
->ca_nregparms
= NPARM_REGS
;
2298 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2301 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2304 /* Return the register that the argument described by MODE and TYPE is
2305 passed in, or else return 0 if it is passed on the stack. */
2308 i960_function_arg (cum
, mode
, type
, named
)
2309 CUMULATIVE_ARGS
*cum
;
2310 enum machine_mode mode
;
2317 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2319 if (size
> 4 || cum
->ca_nstackparms
!= 0
2320 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2321 || MUST_PASS_IN_STACK (mode
, type
))
2323 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2328 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2329 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2335 /* Floating-point support. */
2338 i960_output_long_double (file
, value
)
2340 REAL_VALUE_TYPE value
;
2345 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2346 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2349 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2350 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2351 fprintf (file
, "\t.word\t0x0\n");
2355 i960_output_double (file
, value
)
2357 REAL_VALUE_TYPE value
;
2362 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2363 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2365 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2366 value_long
[0], dstr
, value_long
[1]);
2370 i960_output_float (file
, value
)
2372 REAL_VALUE_TYPE value
;
2377 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2378 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2380 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2383 /* Return the number of bits that an object of size N bytes is aligned to. */
2386 i960_object_bytes_bitalign (n
)
2390 else if (n
> 4) n
= 64;
2391 else if (n
> 2) n
= 32;
2392 else if (n
> 1) n
= 16;
2398 /* Compute the alignment for an aggregate type TSIZE.
2399 Alignment is MAX (greatest member alignment,
2400 MIN (pragma align, structure size alignment)). */
2403 i960_round_align (align
, tsize
)
2409 if (TREE_CODE (tsize
) != INTEGER_CST
)
2412 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2414 /* Handle #pragma align. */
2415 if (new_align
> i960_maxbitalignment
)
2416 new_align
= i960_maxbitalignment
;
2418 if (align
< new_align
)
2424 /* Do any needed setup for a varargs function. For the i960, we must
2425 create a register parameter block if one doesn't exist, and then copy
2426 all register parameters to memory. */
2429 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2430 CUMULATIVE_ARGS
*cum
;
2431 enum machine_mode mode
;
2436 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2437 int first_reg
= cum
->ca_nregparms
;
2439 /* Copy only unnamed register arguments to memory. If there are
2440 any stack parms, there are no unnamed arguments in registers, and
2441 an argument block was already allocated by the caller.
2442 Remember that any arg bigger than 4 words is passed on the stack as
2443 are all subsequent args.
2445 If there are no stack arguments but there are exactly NPARM_REGS
2446 registers, either there were no extra arguments or the caller
2447 allocated an argument block. */
2449 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2451 rtx label
= gen_label_rtx ();
2454 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2455 and we need to allocate a chunk to save the registers (if any
2456 arguments were passed on the stack the caller would allocate the
2457 48 bytes as well). We must allocate all 48 bytes (12*4) because
2458 va_start assumes it. */
2459 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2460 emit_jump_insn (gen_bne (label
));
2461 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2462 stack_pointer_rtx
));
2463 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2464 memory_address (SImode
,
2465 plus_constant (stack_pointer_rtx
,
2469 /* ??? Note that we unnecessarily store one extra register for stdarg
2470 fns. We could optimize this, but it's kept as for now. */
2471 regblock
= gen_rtx (MEM
, BLKmode
,
2472 plus_constant (arg_pointer_rtx
,
2474 move_block_from_reg (first_reg
, regblock
,
2475 NPARM_REGS
- first_reg
,
2476 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2480 /* Calculate the final size of the reg parm stack space for the current
2481 function, based on how many bytes would be allocated on the stack. */
2484 i960_final_reg_parm_stack_space (const_size
, var_size
)
2488 if (var_size
|| const_size
> 48)
2494 /* Calculate the size of the reg parm stack space. This is a bit complicated
2498 i960_reg_parm_stack_space (fndecl
)
2501 /* In this case, we are called from emit_library_call, and we don't need
2502 to pretend we have more space for parameters than what's apparent. */
2506 /* In this case, we are called from locate_and_pad_parms when we're
2507 not IN_REGS, so we have an arg block. */
2508 if (fndecl
!= current_function_decl
)
2511 /* Otherwise, we have an arg block if the current function has more than
2512 48 bytes of parameters. */
2513 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2519 /* Return the register class of a scratch register needed to copy IN into
2520 or out of a register in CLASS in MODE. If it can be done directly,
2521 NO_REGS is returned. */
2524 secondary_reload_class (class, mode
, in
)
2525 enum reg_class
class;
2526 enum machine_mode mode
;
2531 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2532 regno
= true_regnum (in
);
2534 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2535 LOCAL_OR_GLOBAL_REGS into anything. */
2536 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2537 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2540 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2541 if (class == FP_REGS
2542 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2543 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2546 return LOCAL_OR_GLOBAL_REGS
;
2549 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2550 function unit it executed on. */
2552 /* ??? This would make more sense as an attribute. */
2555 i960_scan_opcode (p
)
2567 /* Ret is not actually of type REG, but it won't matter, because no
2568 insn will ever follow it. */
2571 i960_last_insn_type
= I_TYPE_REG
;
2575 if (p
[1] == 'x' || p
[3] == 'x')
2576 i960_last_insn_type
= I_TYPE_MEM
;
2577 i960_last_insn_type
= I_TYPE_CTRL
;
2582 i960_last_insn_type
= I_TYPE_CTRL
;
2589 i960_last_insn_type
= I_TYPE_MEM
;
2591 i960_last_insn_type
= I_TYPE_CTRL
;
2593 else if (p
[1] == 'm')
2596 i960_last_insn_type
= I_TYPE_REG
;
2597 else if (p
[4] == 'b' || p
[4] == 'j')
2598 i960_last_insn_type
= I_TYPE_CTRL
;
2600 i960_last_insn_type
= I_TYPE_REG
;
2603 i960_last_insn_type
= I_TYPE_REG
;
2607 i960_last_insn_type
= I_TYPE_MEM
;
2612 i960_last_insn_type
= I_TYPE_MEM
;
2614 i960_last_insn_type
= I_TYPE_REG
;