1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
79 /* Handle pragmas for compatibility with Intel's compilers. */
81 /* ??? This is incomplete, since it does not handle all pragmas that the
82 intel compilers understand. Also, it needs to be rewritten to accept
83 a stream instead of a string for GCC 2. */
92 if ((i
= sscanf (str
, " align %d", &align
)) == 1)
95 case 0: /* Return to last alignment. */
96 align
= i960_last_maxbitalignment
/ 8;
98 case 16: /* Byte alignments. */
103 i960_last_maxbitalignment
= i960_maxbitalignment
;
104 i960_maxbitalignment
= align
* 8;
107 default: /* Unknown, silently ignore. */
111 /* NOTE: ic960 R3.0 pragma align definition:
113 #pragma align [(size)] | (identifier=size[,...])
114 #pragma noalign [(identifier)[,...]]
116 (all parens are optional)
118 - size is [1,2,4,8,16]
119 - noalign means size==1
120 - applies only to component elements of a struct (and union?)
121 - identifier applies to structure tag (only)
122 - missing identifier means next struct
124 - alignment rules for bitfields need more investigation */
126 /* Should be pragma 'far' or equivalent for callx/balx here. */
130 /* Initialize variables before compiling any files. */
135 if (TARGET_IC_COMPAT2_0
)
137 i960_maxbitalignment
= 8;
138 i960_last_maxbitalignment
= 128;
142 i960_maxbitalignment
= 128;
143 i960_last_maxbitalignment
= 8;
147 /* Return true if OP can be used as the source of an fp move insn. */
150 fpmove_src_operand (op
, mode
)
152 enum machine_mode mode
;
154 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
158 /* Return true if OP is a register or zero. */
161 reg_or_zero_operand (op
, mode
)
163 enum machine_mode mode
;
165 return register_operand (op
, mode
) || op
== const0_rtx
;
169 /* Return truth value of whether OP can be used as an operands in a three
170 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
173 arith_operand (op
, mode
)
175 enum machine_mode mode
;
177 return (register_operand (op
, mode
) || literal (op
, mode
));
180 /* Return true if OP is a register or a valid floating point literal. */
183 fp_arith_operand (op
, mode
)
185 enum machine_mode mode
;
187 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
190 /* Return true is OP is a register or a valid signed integer literal. */
193 signed_arith_operand (op
, mode
)
195 enum machine_mode mode
;
197 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
200 /* Return truth value of whether OP is a integer which fits the
201 range constraining immediate operands in three-address insns. */
206 enum machine_mode mode
;
208 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
211 /* Return true if OP is a float constant of 1. */
214 fp_literal_one (op
, mode
)
216 enum machine_mode mode
;
218 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
219 && (op
== CONST1_RTX (mode
)));
222 /* Return true if OP is a float constant of 0. */
225 fp_literal_zero (op
, mode
)
227 enum machine_mode mode
;
229 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
230 && (op
== CONST0_RTX (mode
)));
233 /* Return true if OP is a valid floating point literal. */
238 enum machine_mode mode
;
240 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
243 /* Return true if OP is a valid signed immediate constant. */
246 signed_literal(op
, mode
)
248 enum machine_mode mode
;
250 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
253 /* Return truth value of statement that OP is a symbolic memory
254 operand of mode MODE. */
257 symbolic_memory_operand (op
, mode
)
259 enum machine_mode mode
;
261 if (GET_CODE (op
) == SUBREG
)
262 op
= SUBREG_REG (op
);
263 if (GET_CODE (op
) != MEM
)
266 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
267 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
270 /* Return truth value of whether OP is EQ or NE. */
275 enum machine_mode mode
;
277 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
280 /* OP is an integer register or a constant. */
283 arith32_operand (op
, mode
)
285 enum machine_mode mode
;
287 if (register_operand (op
, mode
))
289 return (CONSTANT_P (op
));
292 /* Return true if OP is an integer constant which is a power of 2. */
295 power2_operand (op
,mode
)
297 enum machine_mode mode
;
299 if (GET_CODE (op
) != CONST_INT
)
302 return exact_log2 (INTVAL (op
)) >= 0;
305 /* Return true if OP is an integer constant which is the complement of a
309 cmplpower2_operand (op
, mode
)
311 enum machine_mode mode
;
313 if (GET_CODE (op
) != CONST_INT
)
316 return exact_log2 (~ INTVAL (op
)) >= 0;
319 /* If VAL has only one bit set, return the index of that bit. Otherwise
328 for (i
= 0; val
!= 0; i
++, val
>>= 1)
340 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
341 The return value indicates how many consecutive non-zero bits exist
342 if this is a mask. This is the same as the next function, except that
343 it does not indicate what the start and stop bit positions are. */
349 register int start
, end
, i
;
352 for (i
= 0; val
!= 0; val
>>= 1, i
++)
362 /* Still looking for the first bit. */
366 /* We've seen the start of a bit sequence, and now a zero. There
367 must be more one bits, otherwise we would have exited the loop.
368 Therefore, it is not a mask. */
373 /* The bit string has ones from START to END bit positions only. */
374 return end
- start
+ 1;
377 /* If VAL is a mask, then return nonzero, with S set to the starting bit
378 position and E set to the ending bit position of the mask. The return
379 value indicates how many consecutive bits exist in the mask. This is
380 the same as the previous function, except that it also indicates the
381 start and end bit positions of the mask. */
388 register int start
, end
, i
;
392 for (i
= 0; val
!= 0; val
>>= 1, i
++)
403 /* Still looking for the first bit. */
407 /* We've seen the start of a bit sequence, and now a zero. There
408 must be more one bits, otherwise we would have exited the loop.
409 Therefor, it is not a mask. */
418 /* The bit string has ones from START to END bit positions only. */
421 return ((start
< 0) ? 0 : end
- start
+ 1);
424 /* Return the machine mode to use for a comparison. */
427 select_cc_mode (op
, x
)
431 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
436 /* X and Y are two things to compare using CODE. Emit the compare insn and
437 return the rtx for register 36 in the proper mode. */
440 gen_compare_reg (code
, x
, y
)
445 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
446 enum machine_mode mode
447 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
451 if (! arith_operand (x
, mode
))
452 x
= force_reg (SImode
, x
);
453 if (! arith_operand (y
, mode
))
454 y
= force_reg (SImode
, y
);
457 cc_reg
= gen_rtx (REG
, ccmode
, 36);
458 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
459 gen_rtx (COMPARE
, ccmode
, x
, y
)));
464 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
465 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
466 are 4. Indexed addresses are cost 6. */
468 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
471 i960_address_cost (x
)
475 /* Handled before calling here. */
476 if (GET_CODE (x
) == REG
)
479 if (GET_CODE (x
) == PLUS
)
481 rtx base
= XEXP (x
, 0);
482 rtx offset
= XEXP (x
, 1);
484 if (GET_CODE (base
) == SUBREG
)
485 base
= SUBREG_REG (base
);
486 if (GET_CODE (offset
) == SUBREG
)
487 offset
= SUBREG_REG (offset
);
489 if (GET_CODE (base
) == REG
)
491 if (GET_CODE (offset
) == REG
)
493 if (GET_CODE (offset
) == CONST_INT
)
495 if ((unsigned)INTVAL (offset
) < 2047)
499 if (CONSTANT_P (offset
))
502 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
505 /* This is an invalid address. The return value doesn't matter, but
506 for convenience we make this more expensive than anything else. */
509 if (GET_CODE (x
) == MULT
)
512 /* Symbol_refs and other unrecognized addresses are cost 4. */
516 /* Emit insns to move operands[1] into operands[0].
518 Return 1 if we have written out everything that needs to be done to
519 do the move. Otherwise, return 0 and the caller will emit the move
523 emit_move_sequence (operands
, mode
)
525 enum machine_mode mode
;
527 register rtx operand0
= operands
[0];
528 register rtx operand1
= operands
[1];
530 /* We can only store registers to memory. */
532 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
533 operands
[1] = force_reg (mode
, operand1
);
538 /* Emit insns to load a constant. Uses several strategies to try to use
539 as few insns as possible. */
542 i960_output_ldconst (dst
, src
)
543 register rtx dst
, src
;
546 register unsigned rsrc2
;
547 enum machine_mode mode
= GET_MODE (dst
);
549 union { long l
[2]; double d
; } x
;
551 operands
[0] = operands
[2] = dst
;
552 operands
[1] = operands
[3] = src
;
554 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
555 must be a ldconst insn. */
557 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
559 output_asm_insn ("ldconst %1,%0", operands
);
562 else if (mode
== DFmode
)
566 if (fp_literal_zero (src
, VOIDmode
))
569 return "movrl %1,%0";
574 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
575 split_double (src
, &first
, &second
);
577 output_asm_insn ("# ldconst %1,%0",operands
);
579 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
581 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
583 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
584 operands
[1] = second
;
585 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
589 if (fp_literal_one (src
, VOIDmode
))
590 return "movrl 0f1.0,%0";
591 fatal ("inline double constants not supported on this host");
594 else if (mode
== TImode
)
596 /* ??? This is currently not handled at all. */
599 /* Note: lowest order word goes in lowest numbered reg. */
600 rsrc1
= INTVAL (src
);
601 if (rsrc1
>= 0 && rsrc1
< 32)
604 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
605 /* Go pick up the low-order word. */
607 else if (mode
== DImode
)
609 rtx upperhalf
, lowerhalf
, xoperands
[2];
612 if (GET_CODE (src
) == CONST_DOUBLE
)
614 upperhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_HIGH (src
));
615 lowerhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_LOW (src
));
617 else if (GET_CODE (src
) == CONST_INT
)
620 upperhalf
= INTVAL (src
) < 0 ? constm1_rtx
: const0_rtx
;
625 /* Note: lowest order word goes in lowest numbered reg. */
626 /* Numbers from 0 to 31 can be handled with a single insn. */
627 rsrc1
= INTVAL (lowerhalf
);
628 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
631 /* Output the upper half with a recursive call. */
632 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
633 xoperands
[1] = upperhalf
;
634 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
636 /* The lower word is emitted as normally. */
638 else if (mode
== SFmode
)
640 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
644 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
645 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
647 output_asm_insn ("# ldconst %1,%0",operands
);
648 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
649 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
650 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
653 if (fp_literal_zero (src
, VOIDmode
))
654 return "movr 0f0.0,%0";
655 if (fp_literal_one (src
, VOIDmode
))
656 return "movr 0f1.0,%0";
657 fatal ("inline float constants not supported on this host");
663 rsrc1
= INTVAL (src
);
669 else if (mode
== HImode
)
678 /* ldconst 0..31,X -> mov 0..31,X */
681 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
686 /* ldconst 32..63,X -> add 31,nn,X */
689 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
691 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
692 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
698 /* ldconst -1..-31 -> sub 0,0..31,X */
701 /* return 'sub -(%1),0,%0' */
702 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
703 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
707 /* ldconst -32 -> not 31,X */
710 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
711 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
716 /* If const is a single bit. */
717 if (bitpos (rsrc1
) >= 0)
719 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
720 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
724 /* If const is a bit string of less than 6 bits (1..31 shifted). */
729 if (bitstr (rsrc1
, &s
, &e
) < 6)
731 rsrc2
= ((unsigned int) rsrc1
) >> s
;
732 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
733 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
734 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
739 /* Unimplemented cases:
740 const is in range 0..31 but rotated around end of word:
741 ror 31,3,g0 -> ldconst 0xe0000003,g0
743 and any 2 instruction cases that might be worthwhile */
745 output_asm_insn ("ldconst %1,%0", operands
);
749 /* Determine if there is an opportunity for a bypass optimization.
750 Bypass succeeds on the 960K* if the destination of the previous
751 instruction is the second operand of the current instruction.
752 Bypass always succeeds on the C*.
754 Return 1 if the pattern should interchange the operands.
756 CMPBR_FLAG is true if this is for a compare-and-branch insn.
757 OP1 and OP2 are the two source operands of a 3 operand insn. */
760 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
761 register rtx insn
, op1
, op2
;
764 register rtx prev_insn
, prev_dest
;
769 /* Can't do this if op1 isn't a register. */
773 /* Can't do this for a compare-and-branch if both ops aren't regs. */
774 if (cmpbr_flag
&& ! REG_P (op2
))
777 prev_insn
= prev_real_insn (insn
);
779 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
780 && GET_CODE (PATTERN (prev_insn
)) == SET
)
782 prev_dest
= SET_DEST (PATTERN (prev_insn
));
783 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
784 || (GET_CODE (prev_dest
) == SUBREG
785 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
786 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
792 /* Output the code which declares the function name. This also handles
793 leaf routines, which have special requirements, and initializes some
797 i960_function_name_declare (file
, name
, fndecl
)
806 /* Increment global return label. */
810 /* Compute whether tail calls and leaf routine optimizations can be performed
811 for this function. */
823 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
824 argblock, because argblock uses g14 implicitly. */
826 if (current_function_args_size
!= 0)
832 /* See if caller passes in an address to return value. */
834 if (aggregate_value_p (DECL_RESULT (fndecl
)))
840 /* Can not use tail calls or make this a leaf routine if there is a non
843 if (get_frame_size () != 0)
846 /* I don't understand this condition, and do not think that it is correct.
847 Apparently this is just checking whether the frame pointer is used, and
848 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
851 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
852 if (GET_CODE (insn
) == INSN
853 && reg_mentioned_p (frame_pointer_rtx
, insn
))
859 /* Check for CALL insns. Can not be a leaf routine if there are any. */
862 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
863 if (GET_CODE (insn
) == CALL_INSN
)
869 /* Can not be a leaf routine if any non-call clobbered registers are
870 used in this function. */
873 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
874 if (regs_ever_live
[i
]
875 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
877 /* Global registers. */
878 if (i
< 16 && i
> 7 && i
!= 13)
880 /* Local registers. */
885 /* Now choose a leaf return register, if we can find one, and if it is
886 OK for this to be a leaf routine. */
888 i960_leaf_ret_reg
= -1;
890 if (optimize
&& leaf_proc_ok
)
892 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
893 if (regs_ever_live
[i
] == 0)
895 i960_leaf_ret_reg
= i
;
896 regs_ever_live
[i
] = 1;
901 /* Do this after choosing the leaf return register, so it will be listed
902 if one was chosen. */
904 fprintf (file
, "\t# Function '%s'\n", name
);
905 fprintf (file
, "\t# Registers used: ");
907 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
909 if (regs_ever_live
[i
])
911 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
913 if (i
> 15 && j
== 0)
915 fprintf (file
,"\n\t#\t\t ");
921 fprintf (file
, "\n");
923 if (i960_leaf_ret_reg
>= 0)
925 /* Make it a leaf procedure. */
927 if (TREE_PUBLIC (fndecl
))
928 fprintf (file
,"\t.globl %s.lf\n", name
);
930 fprintf (file
, "\t.leafproc\t_%s,%s.lf\n", name
, name
);
931 fprintf (file
, "_%s:\n", name
);
932 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
933 fprintf (file
, "%s.lf:\n", name
);
934 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
938 fprintf (file
, "\tlda 0,g14\n");
939 i960_last_insn_type
= I_TYPE_MEM
;
943 fprintf (file
, "\tmov 0,g14\n");
944 i960_last_insn_type
= I_TYPE_REG
;
949 ASM_OUTPUT_LABEL (file
, name
);
950 i960_last_insn_type
= I_TYPE_CTRL
;
954 /* Compute and return the frame size. */
957 compute_frame_size (size
)
961 int outgoing_args_size
962 = current_function_outgoing_args_size
+ current_function_pretend_args_size
;
964 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
965 as size is concerned. */
966 actual_fsize
= (size
+ 15) & -16;
967 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
972 /* Output code for the function prologue. */
975 i960_function_prologue (file
, size
)
979 register int i
, j
, nr
;
982 int actual_fsize
, offset
;
984 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
986 int regs
[FIRST_PSEUDO_REGISTER
];
988 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
989 if (regs_ever_live
[i
]
990 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
993 /* Count global registers that need saving. */
1000 epilogue_string
[0] = '\0';
1002 /* First look for local registers to save globals in. */
1003 for (i
= 0; i
< 16; i
++)
1008 /* Start at r4, not r3. */
1009 for (j
= 20; j
< 32; j
++)
1016 regs_ever_live
[j
] = 1;
1018 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1019 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1024 regs_ever_live
[j
+1] = 1;
1026 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1027 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1032 regs_ever_live
[j
+2] = 1;
1034 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1039 regs_ever_live
[j
+3] = 1;
1042 fprintf (file
, "\tmov%s %s,%s\n",
1045 (nr
== 2) ? "l" : ""),
1046 reg_names
[i
], reg_names
[j
]);
1047 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1050 (nr
== 2) ? "l" : ""),
1051 reg_names
[j
], reg_names
[i
]);
1052 strcat (epilogue_string
, tmpstr
);
1060 /* N_iregs is now the number of global registers that haven't been saved
1063 rsize
= (n_iregs
* 4);
1064 actual_fsize
= compute_frame_size (size
) + rsize
;
1066 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1067 size up to the nearest multiple of 16. I don't know whether this is
1068 necessary, or even desirable.
1070 The frame pointer must be aligned, but the call instruction takes care of
1071 that. If we leave the stack pointer unaligned, we may save a little on
1072 dynamic stack allocation. And we don't lose, at least according to the
1074 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1077 /* Allocate space for register save and locals. */
1078 if (actual_fsize
> 0)
1080 if (actual_fsize
< 32)
1081 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1083 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1086 /* Take hardware register save area created by the call instruction
1088 offset
= compute_frame_size (size
) + 64;
1089 /* Save registers on stack if needed. */
1090 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1097 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1100 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1104 if (nr
== 3 && regs
[i
+3] == -1)
1107 fprintf (file
,"\tst%s %s,%d(fp)\n",
1110 (nr
== 2) ? "l" : ""),
1111 reg_names
[i
], offset
);
1112 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1115 (nr
== 2) ? "l" : ""),
1116 offset
, reg_names
[i
]);
1117 strcat (epilogue_string
, tmpstr
);
1123 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1126 fprintf (file
, "\t#Prologue stats:\n");
1127 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1130 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1132 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1134 fprintf (file
, "\t#End Prologue#\n");
1137 /* Output code for the function epilogue. */
1140 i960_function_epilogue (file
, size
)
1144 if (i960_leaf_ret_reg
>= 0)
1146 fprintf (file
, "LR%d: ret\n", ret_label
);
1150 if (*epilogue_string
== 0)
1154 /* Emit a return insn, but only if control can fall through to here. */
1156 tmp
= get_last_insn ();
1159 if (GET_CODE (tmp
) == BARRIER
)
1161 if (GET_CODE (tmp
) == CODE_LABEL
)
1163 if (GET_CODE (tmp
) == JUMP_INSN
)
1165 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1169 if (GET_CODE (tmp
) == NOTE
)
1171 tmp
= PREV_INSN (tmp
);
1176 fprintf (file
, "LR%d: ret\n", ret_label
);
1180 fprintf (file
, "LR%d:\n", ret_label
);
1182 fprintf (file
, "\t#EPILOGUE#\n");
1184 /* Output the string created by the prologue which will restore all
1185 registers saved by the prologue. */
1187 if (epilogue_string
[0] != '\0')
1188 fprintf (file
, "%s", epilogue_string
);
1190 /* Must clear g14 on return. */
1192 if (current_function_args_size
!= 0)
1193 fprintf (file
, "\tmov 0,g14\n");
1195 fprintf (file
, "\tret\n");
1196 fprintf (file
, "\t#End Epilogue#\n");
1199 /* Output code for a call insn. */
1202 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, scratch_reg
, insn
)
1203 register rtx target
, argsize_rtx
, arg_pointer
, scratch_reg
, insn
;
1205 int argsize
= INTVAL (argsize_rtx
);
1206 rtx nexti
= next_real_insn (insn
);
1209 operands
[0] = target
;
1210 operands
[1] = arg_pointer
;
1211 operands
[2] = scratch_reg
;
1213 if (current_function_args_size
!= 0)
1214 output_asm_insn ("mov g14,%2", operands
);
1217 output_asm_insn ("lda %a1,g14", operands
);
1218 else if (current_function_args_size
!= 0)
1219 output_asm_insn ("mov 0,g14", operands
);
1221 /* The code used to assume that calls to SYMBOL_REFs could not be more
1222 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1223 feature is now implemented by relaxing in the GNU linker. It can convert
1224 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1226 /* Nexti could be zero if the called routine is volatile. */
1227 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1228 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1230 /* Delete following return insn. */
1231 if (nexti
&& no_labels_between_p (insn
, nexti
))
1232 delete_insn (nexti
);
1233 output_asm_insn ("bx %0", operands
);
1234 return "# notreached";
1237 output_asm_insn ("callx %0", operands
);
1239 if (current_function_args_size
!= 0)
1240 output_asm_insn ("mov %2,g14", operands
);
1245 /* Output code for a return insn. */
1248 i960_output_ret_insn (insn
)
1251 static char lbuf
[20];
1253 if (*epilogue_string
!= 0)
1255 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1258 sprintf (lbuf
, "b LR%d", ret_label
);
1262 if (current_function_args_size
!= 0)
1263 output_asm_insn ("mov 0,g14", 0);
1265 if (i960_leaf_ret_reg
>= 0)
1267 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1274 /* Return a character string representing the branch prediction
1275 opcode to be tacked on an instruction. This must at least
1276 return a null string. */
1279 i960_br_predict_opcode (lab_ref
, insn
)
1282 if (TARGET_BRANCH_PREDICT
)
1284 unsigned long label_uid
;
1286 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1287 label_uid
= INSN_UID (lab_ref
);
1288 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1289 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1293 /* If not optimizing, then the insn_addresses array will not be
1294 valid. In this case, always return ".t" since most branches
1295 are taken. If optimizing, return .t for backward branches
1296 and .f for forward branches. */
1298 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1307 /* Print the operand represented by rtx X formatted by code CODE. */
1310 i960_print_operand (file
, x
, code
)
1315 enum rtx_code rtxcode
= GET_CODE (x
);
1322 /* Second reg of a double. */
1323 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1327 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1335 else if (rtxcode
== MEM
)
1337 output_address (XEXP (x
, 0));
1340 else if (rtxcode
== CONST_INT
)
1342 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1343 fprintf (file
, "0x%x", INTVAL (x
));
1345 fprintf (file
, "%d", INTVAL (x
));
1348 else if (rtxcode
== CONST_DOUBLE
)
1352 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1354 fprintf (file
, "0f0.0");
1357 else if (x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))
1359 fprintf (file
, "0f1.0");
1363 /* This better be a comment. */
1364 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1365 fprintf (file
, "%#g", d
);
1372 /* Branch or jump, depending on assembler. */
1373 if (TARGET_ASM_COMPAT
)
1380 /* Sign of condition. */
1381 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1382 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1384 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1385 || (rtxcode
== GE
) || (rtxcode
== LE
))
1392 /* Inverted condition. */
1393 rtxcode
= reverse_condition (rtxcode
);
1397 /* Inverted condition w/ reversed operands. */
1398 rtxcode
= reverse_condition (rtxcode
);
1402 /* Reversed operand condition. */
1403 rtxcode
= swap_condition (rtxcode
);
1407 /* Normal condition. */
1409 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1410 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1411 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1412 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1413 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1414 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1415 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1416 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1417 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1418 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1423 output_addr_const (file
, x
);
1433 /* Print a memory address as an operand to reference that memory location.
1435 This is exactly the same as legitimate_address_p, except that it the prints
1436 addresses instead of recognizing them. */
1439 i960_print_operand_addr (file
, addr
)
1451 if (GET_CODE (addr
) == REG
)
1453 else if (CONSTANT_P (addr
))
1455 else if (GET_CODE (addr
) == PLUS
)
1459 op0
= XEXP (addr
, 0);
1460 op1
= XEXP (addr
, 1);
1462 if (GET_CODE (op0
) == REG
)
1465 if (GET_CODE (op1
) == REG
)
1467 else if (CONSTANT_P (op1
))
1472 else if (GET_CODE (op0
) == PLUS
)
1474 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1476 ireg
= XEXP (XEXP (op0
, 0), 0);
1477 scale
= XEXP (XEXP (op0
, 0), 1);
1478 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1480 breg
= XEXP (op0
, 1);
1486 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1488 breg
= XEXP (op0
, 0);
1489 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1491 ireg
= XEXP (op0
, 1);
1500 else if (GET_CODE (op0
) == MULT
)
1502 ireg
= XEXP (op0
, 0);
1503 scale
= XEXP (op0
, 1);
1504 if (GET_CODE (op1
) == REG
)
1506 else if (CONSTANT_P (op1
))
1514 else if (GET_CODE (addr
) == MULT
)
1516 breg
= XEXP (addr
, 0);
1517 scale
= XEXP (addr
, 1);
1523 output_addr_const (file
, offset
);
1525 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1527 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1530 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1531 that is a valid memory address for an instruction.
1532 The MODE argument is the machine mode for the MEM expression
1533 that wants to use this address.
1535 On 80960, legitimate addresses are:
1537 disp (12 or 32 bit) ld foo,r0
1538 base + index ld (g0)[g1*1],r0
1539 base + displ ld 0xf00(g0),r0
1540 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1541 index*scale + base ld (g0)[g1*4],r0
1542 index*scale + displ ld 0xf00[g1*4],r0
1543 index*scale ld [g1*4],r0
1544 index + base + displ ld 0xf00(g0)[g1*1],r0
1546 In each case, scale can be 1, 2, 4, 8, or 16. */
1548 /* This is exactly the same as i960_print_operand_addr, except that
1549 it recognizes addresses instead of printing them.
1551 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1552 convert common non-canonical forms to canonical form so that they will
1556 legitimate_address_p (mode
, addr
, strict
)
1557 enum machine_mode mode
;
1561 if (GET_CODE (addr
) == REG
)
1562 return (strict
? REG_OK_FOR_BASE_P_STRICT (addr
)
1563 : REG_OK_FOR_BASE_P (addr
));
1564 else if (CONSTANT_P (addr
))
1566 else if (GET_CODE (addr
) == PLUS
)
1570 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1573 op0
= XEXP (addr
, 0);
1574 op1
= XEXP (addr
, 1);
1576 if (GET_CODE (op0
) == REG
)
1578 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (op0
)
1579 : REG_OK_FOR_BASE_P (op0
)))
1582 if (GET_CODE (op1
) == REG
)
1583 return (strict
? REG_OK_FOR_INDEX_P_STRICT (op1
)
1584 : REG_OK_FOR_INDEX_P (op1
));
1585 else if (CONSTANT_P (op1
))
1590 else if (GET_CODE (op0
) == PLUS
)
1592 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1594 if (! (GET_CODE (XEXP (XEXP (op0
, 0), 0)) == REG
1595 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (XEXP (op0
, 0), 0))
1596 : REG_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0)))
1597 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1600 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1601 return ((strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 1))
1602 : REG_OK_FOR_BASE_P (XEXP (op0
, 1)))
1603 && CONSTANT_P (op1
));
1607 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1609 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 0))
1610 : REG_OK_FOR_BASE_P (XEXP (op0
, 0))))
1613 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1614 return ((strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 1))
1615 : REG_OK_FOR_INDEX_P (XEXP (op0
, 1)))
1616 && CONSTANT_P (op1
));
1623 else if (GET_CODE (op0
) == MULT
)
1625 if (! (GET_CODE (XEXP (op0
, 0)) == REG
1626 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 0))
1627 : REG_OK_FOR_INDEX_P (XEXP (op0
, 0)))
1628 && SCALE_TERM_P (XEXP (op0
, 1))))
1631 if (GET_CODE (op1
) == REG
)
1632 return (strict
? REG_OK_FOR_BASE_P_STRICT (op1
)
1633 : REG_OK_FOR_BASE_P (op1
));
1634 else if (CONSTANT_P (op1
))
1642 else if (GET_CODE (addr
) == MULT
)
1644 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1647 return (GET_CODE (XEXP (addr
, 0)) == REG
1648 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (addr
, 0))
1649 : REG_OK_FOR_INDEX_P (XEXP (addr
, 0)))
1650 && SCALE_TERM_P (XEXP (addr
, 1)));
1656 /* Try machine-dependent ways of modifying an illegitimate address
1657 to be legitimate. If we find one, return the new, valid address.
1658 This macro is used in only one place: `memory_address' in explow.c.
1660 This converts some non-canonical addresses to canonical form so they
1661 can be recognized. */
1664 legitimize_address (x
, oldx
, mode
)
1667 enum machine_mode mode
;
1669 if (GET_CODE (x
) == SYMBOL_REF
)
1672 x
= copy_to_reg (x
);
1675 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1678 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1679 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1680 created by virtual register instantiation, register elimination, and
1681 similar optimizations. */
1682 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1683 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1684 x
= gen_rtx (PLUS
, Pmode
,
1685 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1686 XEXP (XEXP (x
, 1), 1));
1688 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1689 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1690 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1691 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1692 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1693 && CONSTANT_P (XEXP (x
, 1)))
1695 rtx constant
, other
;
1697 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1699 constant
= XEXP (x
, 1);
1700 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1702 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1704 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1705 other
= XEXP (x
, 1);
1711 x
= gen_rtx (PLUS
, Pmode
,
1712 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1713 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1714 plus_constant (other
, INTVAL (constant
)));
1721 /* Return the most stringent alignment that we are willing to consider
1722 objects of size SIZE and known alignment ALIGN as having. */
1725 i960_alignment (size
, align
)
1731 if (! TARGET_STRICT_ALIGN
)
1732 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1734 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1743 /* Modes for condition codes. */
1745 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1747 /* Modes for single-word (and smaller) quantities. */
1750 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1751 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1753 /* Modes for double-word (and smaller) quantities. */
1756 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1758 /* Modes for quad-word quantities. */
1759 #define T_MODES (~C_MODES)
1761 /* Modes for single-float quantities. */
1762 #define SF_MODES ((1 << (int) SFmode))
1764 /* Modes for double-float quantities. */
1765 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1767 /* Modes for quad-float quantities. */
1768 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1770 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1771 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1772 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1773 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1774 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1776 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1779 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1780 advantage of machine specific facts, such as knowing that the frame pointer
1781 is always 16 byte aligned. */
1784 i960_expr_alignment (x
, size
)
1793 switch (GET_CODE(x
))
1798 if ((align
& 0xf) == 0)
1800 else if ((align
& 0x7) == 0)
1802 else if ((align
& 0x3) == 0)
1804 else if ((align
& 0x1) == 0)
1811 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1812 i960_expr_alignment (XEXP (x
, 1), size
));
1816 /* If this is a valid program, objects are guaranteed to be
1817 correctly aligned for whatever size the reference actually is. */
1818 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1822 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1828 align
= i960_expr_alignment (XEXP (x
, 0));
1830 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1832 align
= align
<< INTVAL (XEXP (x
, 1));
1833 align
= MIN (align
, 16);
1838 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1839 i960_expr_alignment (XEXP (x
, 1), size
));
1841 align
= MIN (align
, 16);
1848 /* Return true if it is possible to reference both BASE and OFFSET, which
1849 have alignment at least as great as 4 byte, as if they had alignment valid
1850 for an object of size SIZE. */
1853 i960_improve_align (base
, offset
, size
)
1860 /* We have at least a word reference to the object, so we know it has to
1861 be aligned at least to 4 bytes. */
1863 i
= MIN (i960_expr_alignment (base
, 4),
1864 i960_expr_alignment (offset
, 4));
1868 /* We know the size of the request. If strict align is not enabled, we
1869 can guess that the alignment is OK for the requested size. */
1871 if (! TARGET_STRICT_ALIGN
)
1872 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1878 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1879 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1882 i960_si_ti (base
, offset
)
1886 return i960_improve_align (base
, offset
, 16);
1889 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1890 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1893 i960_si_di (base
, offset
)
1897 return i960_improve_align (base
, offset
, 8);
1900 /* Return raw values of size and alignment (in words) for the data
1901 type being accessed. These values will be rounded by the caller. */
1904 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
1905 enum machine_mode mode
;
1912 /* Use formal alignment requirements of type being passed, except make
1913 it at least a word. If we don't have a type, this is a library call,
1914 and the parm has to be of scalar type. In this case, consider its
1915 formal alignment requirement to be its size in words. */
1917 if (mode
== BLKmode
)
1918 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1919 else if (mode
== VOIDmode
)
1921 /* End of parm list. */
1922 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
1926 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1930 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
1931 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
1939 /* On the 80960 the first 12 args are in registers and the rest are pushed.
1940 Any arg that is bigger than 4 words is placed on the stack and all
1941 subsequent arguments are placed on the stack.
1943 Additionally, parameters with an alignment requirement stronger than
1944 a word must be be aligned appropriately. */
1946 /* Update CUM to advance past an argument described by MODE and TYPE. */
1949 i960_function_arg_advance (cum
, mode
, type
, named
)
1950 CUMULATIVE_ARGS
*cum
;
1951 enum machine_mode mode
;
1957 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1959 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1960 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
1961 || MUST_PASS_IN_STACK (mode
, type
))
1962 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
1964 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
1967 /* Return the register that the argument described by MODE and TYPE is
1968 passed in, or else return 0 if it is passed on the stack. */
1971 i960_function_arg (cum
, mode
, type
, named
)
1972 CUMULATIVE_ARGS
*cum
;
1973 enum machine_mode mode
;
1980 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1982 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1983 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
1984 || MUST_PASS_IN_STACK (mode
, type
))
1986 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
1991 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
1992 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
1998 /* Floating-point support. */
2001 i960_output_double (file
, value
)
2005 if (REAL_VALUE_ISINF (value
))
2007 fprintf (file
, "\t.word 0\n");
2008 fprintf (file
, "\t.word 0x7ff00000 # Infinity\n");
2011 fprintf (file
, "\t.double 0d%.17e\n", (value
));
2015 i960_output_float (file
, value
)
2019 if (REAL_VALUE_ISINF (value
))
2020 fprintf (file
, "\t.word 0x7f800000 # Infinity\n");
2022 fprintf (file
, "\t.float 0f%.12e\n", (value
));
2025 /* Return the number of bits that an object of size N bytes is aligned to. */
2028 i960_object_bytes_bitalign (n
)
2032 else if (n
> 4) n
= 64;
2033 else if (n
> 2) n
= 32;
2034 else if (n
> 1) n
= 16;
2040 /* Compute the size of an aggregate type TSIZE. */
2043 i960_round_size (tsize
)
2046 int size
, byte_size
, align
;
2048 if (TREE_CODE (tsize
) != INTEGER_CST
)
2051 size
= TREE_INT_CST_LOW (tsize
);
2052 byte_size
= (size
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2053 align
= i960_object_bytes_bitalign (byte_size
);
2055 /* Handle #pragma align. */
2056 if (align
> i960_maxbitalignment
)
2057 align
= i960_maxbitalignment
;
2060 size
= ((size
/ align
) + 1) * align
;
2062 return size_int (size
);
2065 /* Compute the alignment for an aggregate type TSIZE. */
2068 i960_round_align (align
, tsize
)
2074 if (TREE_CODE (tsize
) != INTEGER_CST
)
2077 byte_size
= (TREE_INT_CST_LOW (tsize
) + BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2078 align
= i960_object_bytes_bitalign (byte_size
);
2082 /* Do any needed setup for a varargs function. For the i960, we must
2083 create a register parameter block if one doesn't exist, and then copy
2084 all register parameters to memory. */
2087 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2088 CUMULATIVE_ARGS
*cum
;
2089 enum machine_mode mode
;
2094 if (cum
->ca_nregparms
< NPARM_REGS
)
2096 int first_reg_offset
= cum
->ca_nregparms
;
2098 if (first_reg_offset
> NPARM_REGS
)
2099 first_reg_offset
= NPARM_REGS
;
2101 if (! (no_rtl
) && first_reg_offset
!= NPARM_REGS
)
2103 rtx label
= gen_label_rtx ();
2104 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2105 emit_jump_insn (gen_bne (label
));
2106 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2107 stack_pointer_rtx
));
2108 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2109 memory_address (SImode
,
2110 plus_constant (stack_pointer_rtx
,
2115 gen_rtx (MEM
, BLKmode
, virtual_incoming_args_rtx
),
2116 NPARM_REGS
- first_reg_offset
);
2118 *pretend_size
= (NPARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
;
2122 /* Calculate the final size of the reg parm stack space for the current
2123 function, based on how many bytes would be allocated on the stack. */
2126 i960_final_reg_parm_stack_space (const_size
, var_size
)
2130 if (var_size
|| const_size
> 48)
2136 /* Calculate the size of the reg parm stack space. This is a bit complicated
2140 i960_reg_parm_stack_space (fndecl
)
2143 /* In this case, we are called from emit_library_call, and we don't need
2144 to pretend we have more space for parameters than what's apparent. */
2148 /* In this case, we are called from locate_and_pad_parms when we're
2149 not IN_REGS, so we have an arg block. */
2150 if (fndecl
!= current_function_decl
)
2153 /* Otherwise, we have an arg block if the current function has more than
2154 48 bytes of parameters. */
2155 if (current_function_args_size
!= 0)
2161 /* Return the register class of a scratch register needed to copy IN into
2162 or out of a register in CLASS in MODE. If it can be done directly,
2163 NO_REGS is returned. */
2166 secondary_reload_class (class, mode
, in
)
2167 enum reg_class
class;
2168 enum machine_mode mode
;
2173 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2174 regno
= true_regnum (in
);
2176 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2177 LOCAL_OR_GLOBAL_REGS into anything. */
2178 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2179 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2182 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2183 if (class == FP_REGS
2184 && ((regno
>= 0 && regno
<= FIRST_PSEUDO_REGISTER
)
2185 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2188 return LOCAL_OR_GLOBAL_REGS
;
2191 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2192 function unit it executed on. */
2194 /* ??? This would make more sense as an attribute. */
2197 i960_scan_opcode (p
)
2209 /* Ret is not actually of type REG, but it won't matter, because no
2210 insn will ever follow it. */
2213 i960_last_insn_type
= I_TYPE_REG
;
2217 if (p
[1] == 'x' || p
[3] == 'x')
2218 i960_last_insn_type
= I_TYPE_MEM
;
2219 i960_last_insn_type
= I_TYPE_CTRL
;
2224 i960_last_insn_type
= I_TYPE_CTRL
;
2231 i960_last_insn_type
= I_TYPE_MEM
;
2233 i960_last_insn_type
= I_TYPE_CTRL
;
2235 else if (p
[1] == 'm')
2238 i960_last_insn_type
= I_TYPE_REG
;
2239 else if (p
[4] == 'b' || p
[4] == 'j')
2240 i960_last_insn_type
= I_TYPE_CTRL
;
2242 i960_last_insn_type
= I_TYPE_REG
;
2245 i960_last_insn_type
= I_TYPE_REG
;
2249 i960_last_insn_type
= I_TYPE_MEM
;
2254 i960_last_insn_type
= I_TYPE_MEM
;
2256 i960_last_insn_type
= I_TYPE_REG
;