1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* Where to save/restore register 14 to/from before/after a procedure call
61 when it holds an argument block pointer. */
63 static rtx g14_save_reg
;
65 /* The leaf-procedure return register. Set only if this is a leaf routine. */
67 static int i960_leaf_ret_reg
;
69 /* True if replacing tail calls with jumps is OK. */
71 static int tail_call_ok
;
73 /* A string containing a list of insns to emit in the epilogue so as to
74 restore all registers saved by the prologue. Created by the prologue
75 code as it saves registers away. */
77 char epilogue_string
[1000];
79 /* A unique number (per function) for return labels. */
81 static int ret_label
= 0;
84 /* Handle pragmas for compatibility with Intel's compilers. */
86 /* ??? This is incomplete, since it does not handle all pragmas that the
87 intel compilers understand. Also, it needs to be rewritten to accept
88 a stream instead of a string for GCC 2. */
97 if ((i
= sscanf (str
, " align %d", &align
)) == 1)
100 case 0: /* Return to last alignment. */
101 align
= i960_last_maxbitalignment
/ 8;
103 case 16: /* Byte alignments. */
108 i960_last_maxbitalignment
= i960_maxbitalignment
;
109 i960_maxbitalignment
= align
* 8;
112 default: /* Unknown, silently ignore. */
116 /* NOTE: ic960 R3.0 pragma align definition:
118 #pragma align [(size)] | (identifier=size[,...])
119 #pragma noalign [(identifier)[,...]]
121 (all parens are optional)
123 - size is [1,2,4,8,16]
124 - noalign means size==1
125 - applies only to component elements of a struct (and union?)
126 - identifier applies to structure tag (only)
127 - missing identifier means next struct
129 - alignment rules for bitfields need more investigation */
131 /* Should be pragma 'far' or equivalent for callx/balx here. */
135 /* Initialize variables before compiling any files. */
140 if (TARGET_IC_COMPAT2_0
)
142 i960_maxbitalignment
= 8;
143 i960_last_maxbitalignment
= 128;
147 i960_maxbitalignment
= 128;
148 i960_last_maxbitalignment
= 8;
152 /* Return true if OP can be used as the source of an fp move insn. */
155 fpmove_src_operand (op
, mode
)
157 enum machine_mode mode
;
159 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
163 /* Return true if OP is a register or zero. */
166 reg_or_zero_operand (op
, mode
)
168 enum machine_mode mode
;
170 return register_operand (op
, mode
) || op
== const0_rtx
;
174 /* Return truth value of whether OP can be used as an operands in a three
175 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
178 arith_operand (op
, mode
)
180 enum machine_mode mode
;
182 return (register_operand (op
, mode
) || literal (op
, mode
));
185 /* Return true if OP is a register or a valid floating point literal. */
188 fp_arith_operand (op
, mode
)
190 enum machine_mode mode
;
192 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
195 /* Return true is OP is a register or a valid signed integer literal. */
198 signed_arith_operand (op
, mode
)
200 enum machine_mode mode
;
202 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
205 /* Return truth value of whether OP is a integer which fits the
206 range constraining immediate operands in three-address insns. */
211 enum machine_mode mode
;
213 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
216 /* Return true if OP is a float constant of 1. */
219 fp_literal_one (op
, mode
)
221 enum machine_mode mode
;
223 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
224 && (op
== CONST1_RTX (mode
)));
227 /* Return true if OP is a float constant of 0. */
230 fp_literal_zero (op
, mode
)
232 enum machine_mode mode
;
234 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
235 && (op
== CONST0_RTX (mode
)));
238 /* Return true if OP is a valid floating point literal. */
243 enum machine_mode mode
;
245 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
248 /* Return true if OP is a valid signed immediate constant. */
251 signed_literal(op
, mode
)
253 enum machine_mode mode
;
255 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
258 /* Return truth value of statement that OP is a symbolic memory
259 operand of mode MODE. */
262 symbolic_memory_operand (op
, mode
)
264 enum machine_mode mode
;
266 if (GET_CODE (op
) == SUBREG
)
267 op
= SUBREG_REG (op
);
268 if (GET_CODE (op
) != MEM
)
271 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
272 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
275 /* Return truth value of whether OP is EQ or NE. */
280 enum machine_mode mode
;
282 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
285 /* OP is an integer register or a constant. */
288 arith32_operand (op
, mode
)
290 enum machine_mode mode
;
292 if (register_operand (op
, mode
))
294 return (CONSTANT_P (op
));
297 /* Return true if OP is an integer constant which is a power of 2. */
300 power2_operand (op
,mode
)
302 enum machine_mode mode
;
304 if (GET_CODE(op
) != CONST_INT
)
307 return exact_log2 (INTVAL (op
)) >= 0;
310 /* If VAL has only one bit set, return the index of that bit. Otherwise
319 for (i
= 0; val
!= 0; i
++, val
>>= 1)
331 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
332 The return value indicates how many consecutive non-zero bits exist
333 if this is a mask. This is the same as the next function, except that
334 it does not indicate what the start and stop bit positions are. */
340 register int start
, end
, i
;
343 for (i
= 0; val
!= 0; val
>>= 1, i
++)
353 /* Still looking for the first bit. */
357 /* We've seen the start of a bit sequence, and now a zero. There
358 must be more one bits, otherwise we would have exited the loop.
359 Therefore, it is not a mask. */
364 /* The bit string has ones from START to END bit positions only. */
365 return end
- start
+ 1;
368 /* If VAL is a mask, then return nonzero, with S set to the starting bit
369 position and E set to the ending bit position of the mask. The return
370 value indicates how many consecutive bits exist in the mask. This is
371 the same as the previous function, except that it also indicates the
372 start and end bit positions of the mask. */
379 register int start
, end
, i
;
383 for (i
= 0; val
!= 0; val
>>= 1, i
++)
394 /* Still looking for the first bit. */
398 /* We've seen the start of a bit sequence, and now a zero. There
399 must be more one bits, otherwise we would have exited the loop.
400 Therefor, it is not a mask. */
409 /* The bit string has ones from START to END bit positions only. */
412 return ((start
< 0) ? 0 : end
- start
+ 1);
415 /* Return the machine mode to use for a comparison. */
418 select_cc_mode (op
, x
)
422 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
427 /* X and Y are two things to compare using CODE. Emit the compare insn and
428 return the rtx for register 36 in the proper mode. */
431 gen_compare_reg (code
, x
, y
)
436 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
437 enum machine_mode mode
438 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
442 if (! arith_operand (x
, mode
))
443 x
= force_reg (SImode
, x
);
444 if (! arith_operand (y
, mode
))
445 y
= force_reg (SImode
, y
);
448 cc_reg
= gen_rtx (REG
, ccmode
, 36);
449 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
450 gen_rtx (COMPARE
, ccmode
, x
, y
)));
455 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
456 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
457 are 4. Indexed addresses are cost 6. */
459 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
462 i960_address_cost (x
)
466 /* Handled before calling here. */
467 if (GET_CODE (x
) == REG
)
470 if (GET_CODE (x
) == PLUS
)
472 rtx base
= XEXP (x
, 0);
473 rtx offset
= XEXP (x
, 1);
475 if (GET_CODE (base
) == SUBREG
)
476 base
= SUBREG_REG (base
);
477 if (GET_CODE (offset
) == SUBREG
)
478 offset
= SUBREG_REG (offset
);
480 if (GET_CODE (base
) == REG
)
482 if (GET_CODE (offset
) == REG
)
484 if (GET_CODE (offset
) == CONST_INT
)
486 if ((unsigned)INTVAL (offset
) < 2047)
490 if (CONSTANT_P (offset
))
493 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
496 /* This is an invalid address. The return value doesn't matter, but
497 for convenience we make this more expensive than anything else. */
500 if (GET_CODE (x
) == MULT
)
503 /* Symbol_refs and other unrecognized addresses are cost 4. */
507 /* Emit insns to move operands[1] into operands[0].
509 Return 1 if we have written out everything that needs to be done to
510 do the move. Otherwise, return 0 and the caller will emit the move
514 emit_move_sequence (operands
, mode
)
516 enum machine_mode mode
;
518 register rtx operand0
= operands
[0];
519 register rtx operand1
= operands
[1];
521 /* We can only store registers to memory. */
523 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
524 operands
[1] = force_reg (mode
, operand1
);
529 /* Emit insns to load a constant. Uses several strategies to try to use
530 as few insns as possible. */
533 i960_output_ldconst (dst
, src
)
534 register rtx dst
, src
;
537 register unsigned rsrc2
;
538 enum machine_mode mode
= GET_MODE (dst
);
540 union { long l
[2]; double d
; } x
;
542 operands
[0] = operands
[2] = dst
;
543 operands
[1] = operands
[3] = src
;
545 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
546 must be a ldconst insn. */
548 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
550 output_asm_insn ("ldconst %1,%0", operands
);
553 else if (mode
== DFmode
)
557 if (fp_literal_zero (src
, VOIDmode
))
560 return "movrl %1,%0";
565 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
566 split_double (src
, &first
, &second
);
568 output_asm_insn ("# ldconst %1,%0",operands
);
570 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
572 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
574 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
575 operands
[1] = second
;
576 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
580 if (fp_literal_one (src
, VOIDmode
))
581 return "movrl 0f1.0,%0";
582 fatal ("inline double constants not supported on this host");
585 else if (mode
== TImode
)
587 /* ??? This is currently not handled at all. */
590 /* Note: lowest order word goes in lowest numbered reg. */
591 rsrc1
= INTVAL (src
);
592 if (rsrc1
>= 0 && rsrc1
< 32)
595 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
596 /* Go pick up the low-order word. */
598 else if (mode
== DImode
)
600 rtx upperhalf
, lowerhalf
, xoperands
[2];
603 if (GET_CODE (src
) == CONST_DOUBLE
)
605 upperhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_HIGH (src
));
606 lowerhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_LOW (src
));
608 else if (GET_CODE (src
) == CONST_INT
)
611 upperhalf
= INTVAL (src
) < 0 ? constm1_rtx
: const0_rtx
;
616 /* Note: lowest order word goes in lowest numbered reg. */
617 /* Numbers from 0 to 31 can be handled with a single insn. */
618 rsrc1
= INTVAL (lowerhalf
);
619 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
622 /* Output the upper half with a recursive call. */
623 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
624 xoperands
[1] = upperhalf
;
625 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
627 /* The lower word is emitted as normally. */
629 else if (mode
== SFmode
)
631 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
635 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
636 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
638 output_asm_insn ("# ldconst %1,%0",operands
);
639 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
640 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
641 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
644 if (fp_literal_zero (src
, VOIDmode
))
645 return "movr 0f0.0,%0";
646 if (fp_literal_one (src
, VOIDmode
))
647 return "movr 0f1.0,%0";
648 fatal ("inline float constants not supported on this host");
654 rsrc1
= INTVAL (src
);
660 else if (mode
== HImode
)
669 /* ldconst 0..31,X -> mov 0..31,X */
672 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
677 /* ldconst 32..63,X -> add 31,nn,X */
680 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
682 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
683 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
689 /* ldconst -1..-31 -> sub 0,0..31,X */
692 /* return 'sub -(%1),0,%0' */
693 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
694 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
698 /* ldconst -32 -> not 31,X */
701 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
702 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
707 /* If const is a single bit. */
708 if (bitpos (rsrc1
) >= 0)
710 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
711 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
715 /* If const is a bit string of less than 6 bits (1..31 shifted). */
720 if (bitstr (rsrc1
, &s
, &e
) < 6)
722 rsrc2
= ((unsigned int) rsrc1
) >> s
;
723 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
724 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
725 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
730 /* Unimplemented cases:
731 const is in range 0..31 but rotated around end of word:
732 ror 31,3,g0 -> ldconst 0xe0000003,g0
734 and any 2 instruction cases that might be worthwhile */
736 output_asm_insn ("ldconst %1,%0", operands
);
740 /* Determine if there is an opportunity for a bypass optimization.
741 Bypass succeeds on the 960K* if the destination of the previous
742 instruction is the second operand of the current instruction.
743 Bypass always succeeds on the C*.
745 Return 1 if the pattern should interchange the operands.
747 CMPBR_FLAG is true if this is for a compare-and-branch insn.
748 OP1 and OP2 are the two source operands of a 3 operand insn. */
751 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
752 register rtx insn
, op1
, op2
;
755 register rtx prev_insn
, prev_dest
;
760 /* Can't do this if op1 isn't a register. */
764 /* Can't do this for a compare-and-branch if both ops aren't regs. */
765 if (cmpbr_flag
&& ! REG_P (op2
))
768 prev_insn
= prev_real_insn (insn
);
770 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
771 && GET_CODE (PATTERN (prev_insn
)) == SET
)
773 prev_dest
= SET_DEST (PATTERN (prev_insn
));
774 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
775 || (GET_CODE (prev_dest
) == SUBREG
776 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
777 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
783 /* Output the code which declares the function name. This also handles
784 leaf routines, which have special requirements, and initializes some
788 i960_function_name_declare (file
, name
, fndecl
)
797 /* Increment global return label. */
801 /* Compute whether tail calls and leaf routine optimizations can be performed
802 for this function. */
814 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
815 argblock, because argblock uses g14 implicitly. */
817 if (current_function_args_size
!= 0)
823 /* See if caller passes in an address to return value. */
825 if (aggregate_value_p (DECL_RESULT (fndecl
)))
831 /* Can not use tail calls or make this a leaf routine if there is a non
834 if (get_frame_size () != 0)
837 /* I don't understand this condition, and do not think that it is correct.
838 Apparently this is just checking whether the frame pointer is used, and
839 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
842 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
843 if (GET_CODE (insn
) == INSN
844 && reg_mentioned_p (frame_pointer_rtx
, insn
))
850 /* Check for CALL insns. Can not be a leaf routine if there are any. */
853 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
854 if (GET_CODE (insn
) == CALL_INSN
)
860 /* Can not be a leaf routine if any non-call clobbered registers are
861 used in this function. */
864 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
865 if (regs_ever_live
[i
]
866 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
868 /* Global registers. */
869 if (i
< 16 && i
> 7 && i
!= 13)
871 /* Local registers. */
876 /* Now choose a leaf return register, if we can find one, and if it is
877 OK for this to be a leaf routine. */
879 i960_leaf_ret_reg
= -1;
881 if (optimize
&& leaf_proc_ok
)
883 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
884 if (regs_ever_live
[i
] == 0)
886 i960_leaf_ret_reg
= i
;
887 regs_ever_live
[i
] = 1;
892 /* Do this after choosing the leaf return register, so it will be listed
893 if one was chosen. */
895 fprintf (file
, "\t# Function '%s'\n", name
);
896 fprintf (file
, "\t# Registers used: ");
898 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
900 if (regs_ever_live
[i
])
902 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
904 if (i
> 15 && j
== 0)
906 fprintf (file
,"\n\t#\t\t ");
912 fprintf (file
, "\n");
914 if (i960_leaf_ret_reg
>= 0)
916 /* Make it a leaf procedure. */
918 if (TREE_PUBLIC (fndecl
))
919 fprintf (file
,"\t.globl %s.lf\n", name
);
921 fprintf (file
, "\t.leafproc\t_%s,%s.lf\n", name
, name
);
922 fprintf (file
, "_%s:\n", name
);
923 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
924 fprintf (file
, "%s.lf:\n", name
);
925 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
929 fprintf (file
, "\tlda 0,g14\n");
930 i960_last_insn_type
= I_TYPE_MEM
;
934 fprintf (file
, "\tmov 0,g14\n");
935 i960_last_insn_type
= I_TYPE_REG
;
940 ASM_OUTPUT_LABEL (file
, name
);
941 i960_last_insn_type
= I_TYPE_CTRL
;
945 /* Compute and return the frame size. */
948 compute_frame_size (size
)
952 int outgoing_args_size
953 = current_function_outgoing_args_size
+ current_function_pretend_args_size
;
955 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
956 as size is concerned. */
957 actual_fsize
= (size
+ 15) & -16;
958 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
963 /* Output code for the function prologue. */
966 i960_function_prologue (file
, size
)
970 register int i
, j
, nr
;
973 int actual_fsize
, offset
;
975 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
977 int regs
[FIRST_PSEUDO_REGISTER
];
979 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
980 if (regs_ever_live
[i
]
981 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
984 /* Count global registers that need saving. */
991 epilogue_string
[0] = '\0';
993 /* First look for local registers to save globals in. */
994 for (i
= 0; i
< 16; i
++)
999 /* Start at r4, not r3. */
1000 for (j
= 20; j
< 32; j
++)
1007 regs_ever_live
[j
] = 1;
1009 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1010 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1015 regs_ever_live
[j
+1] = 1;
1017 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1018 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1023 regs_ever_live
[j
+2] = 1;
1025 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1030 regs_ever_live
[j
+3] = 1;
1033 fprintf (file
, "\tmov%s %s,%s\n",
1036 (nr
== 2) ? "l" : ""),
1037 reg_names
[i
], reg_names
[j
]);
1038 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1041 (nr
== 2) ? "l" : ""),
1042 reg_names
[j
], reg_names
[i
]);
1043 strcat (epilogue_string
, tmpstr
);
1051 /* N_iregs is now the number of global registers that haven't been saved
1054 rsize
= (n_iregs
* 4);
1055 actual_fsize
= compute_frame_size (size
) + rsize
;
1057 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1058 size up to the nearest multiple of 16. I don't know whether this is
1059 necessary, or even desirable.
1061 The frame pointer must be aligned, but the call instruction takes care of
1062 that. If we leave the stack pointer unaligned, we may save a little on
1063 dynamic stack allocation. And we don't lose, at least according to the
1065 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1068 /* Allocate space for register save and locals. */
1069 if (actual_fsize
> 0)
1071 if (actual_fsize
< 32)
1072 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1074 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1077 /* Take hardware register save area created by the call instruction
1079 offset
= compute_frame_size (size
) + 64;
1080 /* Save registers on stack if needed. */
1081 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1088 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1091 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1095 if (nr
== 3 && regs
[i
+3] == -1)
1098 fprintf (file
,"\tst%s %s,%d(fp)\n",
1101 (nr
== 2) ? "l" : ""),
1102 reg_names
[i
], offset
);
1103 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1106 (nr
== 2) ? "l" : ""),
1107 offset
, reg_names
[i
]);
1108 strcat (epilogue_string
, tmpstr
);
1114 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1117 fprintf (file
, "\t#Prologue stats:\n");
1118 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1121 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1123 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1125 fprintf (file
, "\t#End Prologue#\n");
1128 /* Output code for the function epilogue. */
1131 i960_function_epilogue (file
, size
)
1135 if (i960_leaf_ret_reg
>= 0)
1137 fprintf (file
, "LR%d: ret\n", ret_label
);
1141 if (*epilogue_string
== 0)
1145 /* Emit a return insn, but only if control can fall through to here. */
1147 tmp
= get_last_insn ();
1150 if (GET_CODE (tmp
) == BARRIER
)
1152 if (GET_CODE (tmp
) == CODE_LABEL
)
1154 if (GET_CODE (tmp
) == JUMP_INSN
)
1156 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1160 if (GET_CODE (tmp
) == NOTE
)
1162 tmp
= PREV_INSN (tmp
);
1167 fprintf (file
, "LR%d: ret\n", ret_label
);
1171 fprintf (file
, "LR%d:\n", ret_label
);
1173 fprintf (file
, "\t#EPILOGUE#\n");
1175 /* Output the string created by the prologue which will restore all
1176 registers saved by the prologue. */
1178 if (epilogue_string
[0] != '\0')
1179 fprintf (file
, "%s", epilogue_string
);
1181 /* Must clear g14 on return. */
1183 if (current_function_args_size
!= 0)
1184 fprintf (file
, "\tmov 0,g14\n");
1186 fprintf (file
, "\tret\n");
1187 fprintf (file
, "\t#End Epilogue#\n");
1190 /* Output code for a call insn. */
1193 i960_output_call_insn (target
, argsize_rtx
, insn
)
1194 register rtx target
, argsize_rtx
, insn
;
1197 int argsize
= INTVAL (argsize_rtx
);
1198 rtx nexti
= next_real_insn (insn
);
1201 operands
[0] = target
;
1203 non_indirect
= ((GET_CODE (target
) == MEM
)
1204 && (GET_CODE (XEXP (target
, 0)) == SYMBOL_REF
));
1206 /* Nexti could be zero if the called routine is volatile. */
1207 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1208 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1210 /* Delete following return insn. */
1211 if (nexti
&& no_labels_between_p (insn
, nexti
))
1212 delete_insn (nexti
);
1213 output_asm_insn (non_indirect
? "b %0" : "bx %0",
1215 return "# notreached";
1218 output_asm_insn (non_indirect
? "callj %0" : "callx %0", operands
);
1222 /* Output code for a return insn. */
1225 i960_output_ret_insn (insn
)
1228 static char lbuf
[20];
1230 if (*epilogue_string
!= 0)
1232 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1235 sprintf (lbuf
, "b LR%d", ret_label
);
1239 if (current_function_args_size
!= 0)
1240 output_asm_insn ("mov 0,g14", 0);
1242 if (i960_leaf_ret_reg
>= 0)
1244 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1251 /* Return a character string representing the branch prediction
1252 opcode to be tacked on an instruction. This must at least
1253 return a null string. */
1256 i960_br_predict_opcode (lab_ref
, insn
)
1259 if (TARGET_BRANCH_PREDICT
)
1261 unsigned long label_uid
;
1263 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1264 label_uid
= INSN_UID (lab_ref
);
1265 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1266 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1270 /* If not optimizing, then the insn_addresses array will not be
1271 valid. In this case, always return ".t" since most branches
1272 are taken. If optimizing, return .t for backward branches
1273 and .f for forward branches. */
1275 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1284 /* Print the operand represented by rtx X formatted by code CODE. */
1287 i960_print_operand (file
, x
, code
)
1292 enum rtx_code rtxcode
= GET_CODE (x
);
1299 /* Second reg of a double. */
1300 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1304 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1312 else if (rtxcode
== MEM
)
1314 output_address (XEXP (x
, 0));
1317 else if (rtxcode
== CONST_INT
)
1319 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1320 fprintf (file
, "0x%x", INTVAL (x
));
1322 fprintf (file
, "%d", INTVAL (x
));
1325 else if (rtxcode
== CONST_DOUBLE
)
1329 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1331 fprintf (file
, "0f0.0");
1334 else if (x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))
1336 fprintf (file
, "0f1.0");
1340 /* This better be a comment. */
1341 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1342 fprintf (file
, "%#g", d
);
1349 /* Branch or jump, depending on assembler. */
1350 if (TARGET_ASM_COMPAT
)
1357 /* Sign of condition. */
1358 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1359 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1361 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1362 || (rtxcode
== GE
) || (rtxcode
== LE
))
1369 /* Inverted condition. */
1370 rtxcode
= reverse_condition (rtxcode
);
1374 /* Inverted condition w/ reversed operands. */
1375 rtxcode
= reverse_condition (rtxcode
);
1379 /* Reversed operand condition. */
1380 rtxcode
= swap_condition (rtxcode
);
1384 /* Normal condition. */
1386 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1387 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1388 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1389 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1390 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1391 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1392 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1393 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1394 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1395 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1400 output_addr_const (file
, x
);
1410 /* Print a memory address as an operand to reference that memory location.
1412 This is exactly the same as legitimate_address_p, except that it the prints
1413 addresses instead of recognizing them. */
1416 i960_print_operand_addr (file
, addr
)
1428 if (GET_CODE (addr
) == REG
)
1430 else if (CONSTANT_P (addr
))
1432 else if (GET_CODE (addr
) == PLUS
)
1436 op0
= XEXP (addr
, 0);
1437 op1
= XEXP (addr
, 1);
1439 if (GET_CODE (op0
) == REG
)
1442 if (GET_CODE (op1
) == REG
)
1444 else if (CONSTANT_P (op1
))
1449 else if (GET_CODE (op0
) == PLUS
)
1451 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1453 ireg
= XEXP (XEXP (op0
, 0), 0);
1454 scale
= XEXP (XEXP (op0
, 0), 1);
1455 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1457 breg
= XEXP (op0
, 1);
1463 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1465 breg
= XEXP (op0
, 0);
1466 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1468 ireg
= XEXP (op0
, 1);
1477 else if (GET_CODE (op0
) == MULT
)
1479 ireg
= XEXP (op0
, 0);
1480 scale
= XEXP (op0
, 1);
1481 if (GET_CODE (op1
) == REG
)
1483 else if (CONSTANT_P (op1
))
1491 else if (GET_CODE (addr
) == MULT
)
1493 breg
= XEXP (addr
, 0);
1494 scale
= XEXP (addr
, 1);
1500 output_addr_const (file
, offset
);
1502 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1504 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1507 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1508 that is a valid memory address for an instruction.
1509 The MODE argument is the machine mode for the MEM expression
1510 that wants to use this address.
1512 On 80960, legitimate addresses are:
1514 disp (12 or 32 bit) ld foo,r0
1515 base + index ld (g0)[g1*1],r0
1516 base + displ ld 0xf00(g0),r0
1517 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1518 index*scale + base ld (g0)[g1*4],r0
1519 index*scale + displ ld 0xf00[g1*4],r0
1520 index*scale ld [g1*4],r0
1521 index + base + displ ld 0xf00(g0)[g1*1],r0
1523 In each case, scale can be 1, 2, 4, 8, or 16. */
1525 /* This is exactly the same as i960_print_operand_addr, except that
1526 it recognizes addresses instead of printing them.
1528 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1529 convert common non-canonical forms to canonical form so that they will
1533 legitimate_address_p (mode
, addr
, strict
)
1534 enum machine_mode mode
;
1538 if (GET_CODE (addr
) == REG
)
1539 return (strict
? REG_OK_FOR_BASE_P_STRICT (addr
)
1540 : REG_OK_FOR_BASE_P (addr
));
1541 else if (CONSTANT_P (addr
))
1543 else if (GET_CODE (addr
) == PLUS
)
1547 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1550 op0
= XEXP (addr
, 0);
1551 op1
= XEXP (addr
, 1);
1553 if (GET_CODE (op0
) == REG
)
1555 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (op0
)
1556 : REG_OK_FOR_BASE_P (op0
)))
1559 if (GET_CODE (op1
) == REG
)
1560 return (strict
? REG_OK_FOR_INDEX_P_STRICT (op1
)
1561 : REG_OK_FOR_INDEX_P (op1
));
1562 else if (CONSTANT_P (op1
))
1567 else if (GET_CODE (op0
) == PLUS
)
1569 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1571 if (! (GET_CODE (XEXP (XEXP (op0
, 0), 0)) == REG
1572 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (XEXP (op0
, 0), 0))
1573 : REG_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0)))
1574 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1577 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1578 return ((strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 1))
1579 : REG_OK_FOR_BASE_P (XEXP (op0
, 1)))
1580 && CONSTANT_P (op1
));
1584 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1586 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 0))
1587 : REG_OK_FOR_BASE_P (XEXP (op0
, 0))))
1590 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1591 return ((strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 1))
1592 : REG_OK_FOR_INDEX_P (XEXP (op0
, 1)))
1593 && CONSTANT_P (op1
));
1600 else if (GET_CODE (op0
) == MULT
)
1602 if (! (GET_CODE (XEXP (op0
, 0)) == REG
1603 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 0))
1604 : REG_OK_FOR_INDEX_P (XEXP (op0
, 0)))
1605 && SCALE_TERM_P (XEXP (op0
, 1))))
1608 if (GET_CODE (op1
) == REG
)
1609 return (strict
? REG_OK_FOR_BASE_P_STRICT (op1
)
1610 : REG_OK_FOR_BASE_P (op1
));
1611 else if (CONSTANT_P (op1
))
1619 else if (GET_CODE (addr
) == MULT
)
1621 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1624 return (GET_CODE (XEXP (addr
, 0)) == REG
1625 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (addr
, 0))
1626 : REG_OK_FOR_INDEX_P (XEXP (addr
, 0)))
1627 && SCALE_TERM_P (XEXP (addr
, 1)));
1633 /* Try machine-dependent ways of modifying an illegitimate address
1634 to be legitimate. If we find one, return the new, valid address.
1635 This macro is used in only one place: `memory_address' in explow.c.
1637 This converts some non-canonical addresses to canonical form so they
1638 can be recognized. */
1641 legitimize_address (x
, oldx
, mode
)
1644 enum machine_mode mode
;
1646 if (GET_CODE (x
) == SYMBOL_REF
)
1649 x
= copy_to_reg (x
);
1652 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1655 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1656 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1657 created by virtual register instantiation, register elimination, and
1658 similar optimizations. */
1659 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1660 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1661 x
= gen_rtx (PLUS
, Pmode
,
1662 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1663 XEXP (XEXP (x
, 1), 1));
1665 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1666 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1667 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1668 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1669 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1670 && CONSTANT_P (XEXP (x
, 1)))
1672 rtx constant
, other
;
1674 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1676 constant
= XEXP (x
, 1);
1677 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1679 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1681 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1682 other
= XEXP (x
, 1);
1688 x
= gen_rtx (PLUS
, Pmode
,
1689 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1690 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1691 plus_constant (other
, INTVAL (constant
)));
1698 /* Return the most stringent alignment that we are willing to consider
1699 objects of size SIZE and known alignment ALIGN as having. */
1702 i960_alignment (size
, align
)
1708 if (! TARGET_STRICT_ALIGN
)
1709 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1711 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1720 /* Modes for condition codes. */
1722 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1724 /* Modes for single-word (and smaller) quantities. */
1727 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1728 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1730 /* Modes for double-word (and smaller) quantities. */
1733 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1735 /* Modes for quad-word quantities. */
1736 #define T_MODES (~C_MODES)
1738 /* Modes for single-float quantities. */
1739 #define SF_MODES ((1 << (int) SFmode))
1741 /* Modes for double-float quantities. */
1742 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1744 /* Modes for quad-float quantities. */
1745 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1747 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1748 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1749 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1750 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1751 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1753 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1756 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1757 advantage of machine specific facts, such as knowing that the frame pointer
1758 is always 16 byte aligned. */
1761 i960_expr_alignment (x
, size
)
1770 switch (GET_CODE(x
))
1775 if ((align
& 0xf) == 0)
1777 else if ((align
& 0x7) == 0)
1779 else if ((align
& 0x3) == 0)
1781 else if ((align
& 0x1) == 0)
1788 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1789 i960_expr_alignment (XEXP (x
, 1), size
));
1793 /* If this is a valid program, objects are guaranteed to be
1794 correctly aligned for whatever size the reference actually is. */
1795 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1799 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1805 align
= i960_expr_alignment (XEXP (x
, 0));
1807 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1809 align
= align
<< INTVAL (XEXP (x
, 1));
1810 align
= MIN (align
, 16);
1815 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1816 i960_expr_alignment (XEXP (x
, 1), size
));
1818 align
= MIN (align
, 16);
1825 /* Return true if it is possible to reference both BASE and OFFSET, which
1826 have alignment at least as great as 4 byte, as if they had alignment valid
1827 for an object of size SIZE. */
1830 i960_improve_align (base
, offset
, size
)
1837 /* We have at least a word reference to the object, so we know it has to
1838 be aligned at least to 4 bytes. */
1840 i
= MIN (i960_expr_alignment (base
, 4),
1841 i960_expr_alignment (offset
, 4));
1845 /* We know the size of the request. If strict align is not enabled, we
1846 can guess that the alignment is OK for the requested size. */
1848 if (! TARGET_STRICT_ALIGN
)
1849 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1855 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1856 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1859 i960_si_ti (base
, offset
)
1863 return i960_improve_align (base
, offset
, 16);
1866 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1867 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1870 i960_si_di (base
, offset
)
1874 return i960_improve_align (base
, offset
, 8);
1877 /* Return raw values of size and alignment (in words) for the data
1878 type being accessed. These values will be rounded by the caller. */
1881 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
1882 enum machine_mode mode
;
1889 /* Use formal alignment requirements of type being passed, except make
1890 it at least a word. If we don't have a type, this is a library call,
1891 and the parm has to be of scalar type. In this case, consider its
1892 formal alignment requirement to be its size in words. */
1894 if (mode
== BLKmode
)
1895 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1896 else if (mode
== VOIDmode
)
1898 /* End of parm list. */
1899 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
1903 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1907 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
1908 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
1916 /* On the 80960 the first 12 args are in registers and the rest are pushed.
1917 Any arg that is bigger than 4 words is placed on the stack and all
1918 subsequent arguments are placed on the stack.
1920 Additionally, parameters with an alignment requirement stronger than
1921 a word must be be aligned appropriately. */
1923 /* Update CUM to advance past an argument described by MODE and TYPE. */
1926 i960_function_arg_advance (cum
, mode
, type
, named
)
1927 CUMULATIVE_ARGS
*cum
;
1928 enum machine_mode mode
;
1934 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1936 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1937 || (size
+ ROUND (cum
->ca_nregparms
, align
)) > NPARM_REGS
1938 || MUST_PASS_IN_STACK (mode
, type
))
1939 cum
->ca_nstackparms
= ROUND (cum
->ca_nstackparms
, align
) + size
;
1941 cum
->ca_nregparms
= ROUND (cum
->ca_nregparms
, align
) + size
;
1944 /* Return the register that the argument described by MODE and TYPE is
1945 passed in, or else return 0 if it is passed on the stack. */
1948 i960_function_arg (cum
, mode
, type
, named
)
1949 CUMULATIVE_ARGS
*cum
;
1950 enum machine_mode mode
;
1957 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1959 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1960 || (size
+ ROUND (cum
->ca_nregparms
, align
)) > NPARM_REGS
1961 || MUST_PASS_IN_STACK (mode
, type
))
1963 cum
->ca_nstackparms
= ROUND (cum
->ca_nstackparms
, align
);
1968 cum
->ca_nregparms
= ROUND (cum
->ca_nregparms
, align
);
1969 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
1975 /* Return the rtx for the register representing the return value, or 0
1976 if the return value must be passed through the stack. */
1979 i960_function_value (type
)
1982 int mode
= TYPE_MODE (type
);
1984 if (mode
== BLKmode
)
1986 unsigned int size
= int_size_in_bytes (type
);
1989 mode
= mode_for_size (i960_object_bytes_bitalign (size
), MODE_INT
, 0);
1992 if (mode
== BLKmode
|| mode
== VOIDmode
)
1993 /* Tell stmt.c and expr.c to pass in address */
1996 return gen_rtx (REG
, mode
, 0);
1999 /* Floating-point support. */
2002 i960_output_double (file
, value
)
2006 if (REAL_VALUE_ISINF (value
))
2008 fprintf (file
, "\t.word 0\n");
2009 fprintf (file
, "\t.word 0x7ff00000 # Infinity\n");
2012 fprintf (file
, "\t.double 0d%.17e\n", (value
));
2016 i960_output_float (file
, value
)
2020 if (REAL_VALUE_ISINF (value
))
2021 fprintf (file
, "\t.word 0x7f800000 # Infinity\n");
2023 fprintf (file
, "\t.float 0f%.12e\n", (value
));
2026 /* Return the number of bits that an object of size N bytes is aligned to. */
2029 i960_object_bytes_bitalign (n
)
2033 else if (n
> 4) n
= 64;
2034 else if (n
> 2) n
= 32;
2035 else if (n
> 1) n
= 16;
2041 /* Compute the size of an aggregate type TSIZE. */
2044 i960_round_size (tsize
)
2047 int size
, byte_size
, align
;
2049 if (TREE_CODE (tsize
) != INTEGER_CST
)
2052 size
= TREE_INT_CST_LOW (tsize
);
2053 byte_size
= (size
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2054 align
= i960_object_bytes_bitalign (byte_size
);
2056 /* Handle #pragma align. */
2057 if (align
> i960_maxbitalignment
)
2058 align
= i960_maxbitalignment
;
2061 size
= ((size
/ align
) + 1) * align
;
2063 return size_int (size
);
2066 /* Compute the alignment for an aggregate type TSIZE. */
2069 i960_round_align (align
, tsize
)
2075 if (TREE_CODE (tsize
) != INTEGER_CST
)
2078 byte_size
= (TREE_INT_CST_LOW (tsize
) + BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
2079 align
= i960_object_bytes_bitalign (byte_size
);
2083 /* Do any needed setup for a varargs function. For the i960, we must
2084 create a register parameter block if one doesn't exist, and then copy
2085 all register parameters to memory. */
2088 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2089 CUMULATIVE_ARGS
*cum
;
2090 enum machine_mode mode
;
2095 if (cum
->ca_nregparms
< NPARM_REGS
)
2097 int first_reg_offset
= cum
->ca_nregparms
;
2099 if (first_reg_offset
> NPARM_REGS
)
2100 first_reg_offset
= NPARM_REGS
;
2102 if (! (no_rtl
) && first_reg_offset
!= NPARM_REGS
)
2104 rtx label
= gen_label_rtx ();
2105 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2106 emit_jump_insn (gen_bne (label
));
2107 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2108 stack_pointer_rtx
));
2109 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2110 memory_address (SImode
,
2111 plus_constant (stack_pointer_rtx
,
2116 gen_rtx (MEM
, BLKmode
, virtual_incoming_args_rtx
),
2117 NPARM_REGS
- first_reg_offset
);
2119 *pretend_size
= (NPARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
;
2123 /* Calculate the final size of the reg parm stack space for the current
2124 function, based on how many bytes would be allocated on the stack. */
2127 i960_final_reg_parm_stack_space (const_size
, var_size
)
2131 if (var_size
|| const_size
> 48)
2137 /* Calculate the size of the reg parm stack space. This is a bit complicated
2141 i960_reg_parm_stack_space (fndecl
)
2144 /* In this case, we are called from emit_library_call, and we don't need
2145 to pretend we have more space for parameters than what's apparent. */
2149 /* In this case, we are called from locate_and_pad_parms when we're
2150 not IN_REGS, so we have an arg block. */
2151 if (fndecl
!= current_function_decl
)
2154 /* Otherwise, we have an arg block if the current function has more than
2155 48 bytes of parameters. */
2156 if (current_function_args_size
!= 0)
2162 /* Return the register class of a scratch register needed to copy IN into
2163 or out of a register in CLASS in MODE. If it can be done directly,
2164 NO_REGS is returned. */
2167 secondary_reload_class (class, mode
, in
)
2168 enum reg_class
class;
2169 enum machine_mode mode
;
2174 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2175 regno
= true_regnum (in
);
2177 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2178 LOCAL_OR_GLOBAL_REGS into anything. */
2179 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2180 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2183 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2184 if (class == FP_REGS
2185 && ((regno
>= 0 && regno
<= FIRST_PSEUDO_REGISTER
)
2186 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2189 return LOCAL_OR_GLOBAL_REGS
;
2192 /* Emit the code necessary for a procedure call. Return value is needed
2193 after the call if target is non-zero. */
2196 i960_expand_call (first_operand
, second_operand
, target
)
2197 rtx first_operand
, second_operand
, target
;
2199 /* Used to ensure that g14_save_reg is initialized once and only once
2200 for each function if it is needed. */
2201 static char *this_function_name
= 0;
2204 if (this_function_name
!= current_function_name
)
2207 struct sequence_stack
*seq_stack
;
2209 this_function_name
= current_function_name
;
2211 /* If the current function has an argument block, then save g14 into
2212 a pseudo at the top of the function and restore it after this
2213 function call. If the current function has no argument block,
2214 then g14 is zero before and after the call. */
2216 if (current_function_args_size
!= 0)
2219 seq_stack
= sequence_stack
;
2220 while (seq_stack
->next
)
2221 seq_stack
= seq_stack
->next
;
2222 first
= seq_stack
->first
;
2223 g14_save_reg
= copy_to_reg (arg_pointer_rtx
);
2224 seq
= gen_sequence ();
2226 emit_insn_after (seq
, first
);
2230 if (current_function_args_size
!= 0)
2233 if (GET_CODE (second_operand
) != CONST_INT
|| INTVAL (second_operand
) > 48)
2235 /* Calling a function needing an argument block. */
2236 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2237 virtual_outgoing_args_rtx
));
2241 /* Calling a normal function -- only set to zero if we know our g14
2244 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
, const0_rtx
));
2248 emit_call_insn (gen_rtx (SET
, VOIDmode
, target
,
2249 gen_rtx (CALL
, VOIDmode
, first_operand
,
2252 emit_call_insn (gen_rtx (CALL
, VOIDmode
, first_operand
, second_operand
));
2255 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
, g14_save_reg
));
2256 else if (GET_CODE (second_operand
) != CONST_INT
2257 || INTVAL (second_operand
) > 48)
2259 /* Calling a function needing an argument block. It will have set
2260 reg14 back to zero before returning, so we must emit a clobber here
2261 to tell cse that g14 has changed. */
2262 emit_insn (gen_rtx (CLOBBER
, VOIDmode
, arg_pointer_rtx
));
2266 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2267 function unit it executed on. */
2269 /* ??? This would make more sense as an attribute. */
2272 i960_scan_opcode (p
)
2284 /* Ret is not actually of type REG, but it won't matter, because no
2285 insn will ever follow it. */
2288 i960_last_insn_type
= I_TYPE_REG
;
2292 if (p
[1] == 'x' || p
[3] == 'x')
2293 i960_last_insn_type
= I_TYPE_MEM
;
2294 i960_last_insn_type
= I_TYPE_CTRL
;
2299 i960_last_insn_type
= I_TYPE_CTRL
;
2306 i960_last_insn_type
= I_TYPE_MEM
;
2308 i960_last_insn_type
= I_TYPE_CTRL
;
2310 else if (p
[1] == 'm')
2313 i960_last_insn_type
= I_TYPE_REG
;
2314 else if (p
[4] == 'b' || p
[4] == 'j')
2315 i960_last_insn_type
= I_TYPE_CTRL
;
2317 i960_last_insn_type
= I_TYPE_REG
;
2320 i960_last_insn_type
= I_TYPE_REG
;
2324 i960_last_insn_type
= I_TYPE_MEM
;
2329 i960_last_insn_type
= I_TYPE_MEM
;
2331 i960_last_insn_type
= I_TYPE_REG
;