1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* Where to save/restore register 14 to/from before/after a procedure call
61 when it holds an argument block pointer. */
63 static rtx g14_save_reg
;
65 /* The leaf-procedure return register. Set only if this is a leaf routine. */
67 static int i960_leaf_ret_reg
;
69 /* True if replacing tail calls with jumps is OK. */
71 static int tail_call_ok
;
73 /* A string containing a list of insns to emit in the epilogue so as to
74 restore all registers saved by the prologue. Created by the prologue
75 code as it saves registers away. */
77 char epilogue_string
[1000];
79 /* A unique number (per function) for return labels. */
81 static int ret_label
= 0;
84 /* Handle pragmas for compatibility with Intel's compilers. */
86 /* ??? This is incomplete, since it does not handle all pragmas that the
87 intel compilers understand. Also, it needs to be rewritten to accept
88 a stream instead of a string for GCC 2. */
97 if ((i
= sscanf (str
, " align %d", &align
)) == 1)
100 case 0: /* Return to last alignment. */
101 align
= i960_last_maxbitalignment
/ 8;
103 case 16: /* Byte alignments. */
108 i960_last_maxbitalignment
= i960_maxbitalignment
;
109 i960_maxbitalignment
= align
* 8;
112 default: /* Unknown, silently ignore. */
116 /* NOTE: ic960 R3.0 pragma align definition:
118 #pragma align [(size)] | (identifier=size[,...])
119 #pragma noalign [(identifier)[,...]]
121 (all parens are optional)
123 - size is [1,2,4,8,16]
124 - noalign means size==1
125 - applies only to component elements of a struct (and union?)
126 - identifier applies to structure tag (only)
127 - missing identifier means next struct
129 - alignment rules for bitfields need more investigation */
131 /* Should be pragma 'far' or equivalent for callx/balx here. */
135 /* Initialize variables before compiling any files. */
140 if (TARGET_IC_COMPAT2_0
)
142 i960_maxbitalignment
= 8;
143 i960_last_maxbitalignment
= 128;
147 i960_maxbitalignment
= 128;
148 i960_last_maxbitalignment
= 8;
152 /* Return true if OP can be used as the source of an fp move insn. */
155 fpmove_src_operand (op
, mode
)
157 enum machine_mode mode
;
159 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
163 /* Return true if OP is a register or zero. */
166 reg_or_zero_operand (op
, mode
)
168 enum machine_mode mode
;
170 return register_operand (op
, mode
) || op
== const0_rtx
;
174 /* Return truth value of whether OP can be used as an operands in a three
175 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
178 arith_operand (op
, mode
)
180 enum machine_mode mode
;
182 return (register_operand (op
, mode
) || literal (op
, mode
));
185 /* Return true if OP is a register or a valid floating point literal. */
188 fp_arith_operand (op
, mode
)
190 enum machine_mode mode
;
192 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
195 /* Return true is OP is a register or a valid signed integer literal. */
198 signed_arith_operand (op
, mode
)
200 enum machine_mode mode
;
202 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
205 /* Return truth value of whether OP is a integer which fits the
206 range constraining immediate operands in three-address insns. */
211 enum machine_mode mode
;
213 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
216 /* Return true if OP is a float constant of 1. */
219 fp_literal_one (op
, mode
)
221 enum machine_mode mode
;
223 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
224 && (op
== CONST1_RTX (mode
)));
227 /* Return true if OP is a float constant of 0. */
230 fp_literal_zero (op
, mode
)
232 enum machine_mode mode
;
234 return (TARGET_NUMERICS
&& (mode
== VOIDmode
|| mode
== GET_MODE (op
))
235 && (op
== CONST0_RTX (mode
)));
238 /* Return true if OP is a valid floating point literal. */
243 enum machine_mode mode
;
245 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
248 /* Return true if OP is a valid signed immediate constant. */
251 signed_literal(op
, mode
)
253 enum machine_mode mode
;
255 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
258 /* Return truth value of statement that OP is a symbolic memory
259 operand of mode MODE. */
262 symbolic_memory_operand (op
, mode
)
264 enum machine_mode mode
;
266 if (GET_CODE (op
) == SUBREG
)
267 op
= SUBREG_REG (op
);
268 if (GET_CODE (op
) != MEM
)
271 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
272 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
275 /* Return truth value of whether OP is EQ or NE. */
280 enum machine_mode mode
;
282 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
285 /* OP is an integer register or a constant. */
288 arith32_operand (op
, mode
)
290 enum machine_mode mode
;
292 if (register_operand (op
, mode
))
294 return (CONSTANT_P (op
));
297 /* Return true if OP is an integer constant which is a power of 2. */
300 power2_operand (op
,mode
)
302 enum machine_mode mode
;
304 if (GET_CODE(op
) != CONST_INT
)
307 return exact_log2 (INTVAL (op
)) >= 0;
310 /* If VAL has only one bit set, return the index of that bit. Otherwise
319 for (i
= 0; val
!= 0; i
++, val
>>= 1)
331 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
332 The return value indicates how many consecutive non-zero bits exist
333 if this is a mask. This is the same as the next function, except that
334 it does not indicate what the start and stop bit positions are. */
340 register int start
, end
, i
;
343 for (i
= 0; val
!= 0; val
>>= 1, i
++)
353 /* Still looking for the first bit. */
357 /* We've seen the start of a bit sequence, and now a zero. There
358 must be more one bits, otherwise we would have exited the loop.
359 Therefore, it is not a mask. */
364 /* The bit string has ones from START to END bit positions only. */
365 return end
- start
+ 1;
368 /* If VAL is a mask, then return nonzero, with S set to the starting bit
369 position and E set to the ending bit position of the mask. The return
370 value indicates how many consecutive bits exist in the mask. This is
371 the same as the previous function, except that it also indicates the
372 start and end bit positions of the mask. */
379 register int start
, end
, i
;
383 for (i
= 0; val
!= 0; val
>>= 1, i
++)
394 /* Still looking for the first bit. */
398 /* We've seen the start of a bit sequence, and now a zero. There
399 must be more one bits, otherwise we would have exited the loop.
400 Therefor, it is not a mask. */
409 /* The bit string has ones from START to END bit positions only. */
412 return ((start
< 0) ? 0 : end
- start
+ 1);
415 /* Return the machine mode to use for a comparison. */
418 select_cc_mode (op
, x
)
422 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
427 /* X and Y are two things to compare using CODE. Emit the compare insn and
428 return the rtx for register 36 in the proper mode. */
431 gen_compare_reg (code
, x
, y
)
436 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
437 enum machine_mode mode
438 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
442 if (! arith_operand (x
, mode
))
443 x
= force_reg (SImode
, x
);
444 if (! arith_operand (y
, mode
))
445 y
= force_reg (SImode
, y
);
448 cc_reg
= gen_rtx (REG
, ccmode
, 36);
449 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
450 gen_rtx (COMPARE
, ccmode
, x
, y
)));
455 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
456 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
457 are 4. Indexed addresses are cost 6. */
459 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
462 i960_address_cost (x
)
466 /* Handled before calling here. */
467 if (GET_CODE (x
) == REG
)
470 if (GET_CODE (x
) == PLUS
)
472 rtx base
= XEXP (x
, 0);
473 rtx offset
= XEXP (x
, 1);
475 if (GET_CODE (base
) == SUBREG
)
476 base
= SUBREG_REG (base
);
477 if (GET_CODE (offset
) == SUBREG
)
478 offset
= SUBREG_REG (offset
);
480 if (GET_CODE (base
) == REG
)
482 if (GET_CODE (offset
) == REG
)
484 if (GET_CODE (offset
) == CONST_INT
)
486 if ((unsigned)INTVAL (offset
) < 2047)
490 if (CONSTANT_P (offset
))
493 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
496 /* This is an invalid address. The return value doesn't matter, but
497 for convenience we make this more expensive than anything else. */
500 if (GET_CODE (x
) == MULT
)
503 /* Symbol_refs and other unrecognized addresses are cost 4. */
507 /* Emit insns to move operands[1] into operands[0].
509 Return 1 if we have written out everything that needs to be done to
510 do the move. Otherwise, return 0 and the caller will emit the move
514 emit_move_sequence (operands
, mode
)
516 enum machine_mode mode
;
518 register rtx operand0
= operands
[0];
519 register rtx operand1
= operands
[1];
521 /* We can only store registers to memory. */
523 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
524 operands
[1] = force_reg (mode
, operand1
);
529 /* Emit insns to load a constant. Uses several strategies to try to use
530 as few insns as possible. */
533 i960_output_ldconst (dst
, src
)
534 register rtx dst
, src
;
537 register unsigned rsrc2
;
538 enum machine_mode mode
= GET_MODE (dst
);
540 union { long l
[2]; double d
; } x
;
542 operands
[0] = operands
[2] = dst
;
543 operands
[1] = operands
[3] = src
;
545 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
546 must be a ldconst insn. */
548 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
550 output_asm_insn ("ldconst %1,%0", operands
);
553 else if (mode
== DFmode
)
557 if (fp_literal_zero (src
, VOIDmode
))
560 return "movrl %1,%0";
565 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
566 split_double (src
, &first
, &second
);
568 output_asm_insn ("# ldconst %1,%0",operands
);
570 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
572 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
574 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
575 operands
[1] = second
;
576 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
580 if (fp_literal_one (src
, VOIDmode
))
581 return "movrl 0f1.0,%0";
582 fatal ("inline double constants not supported on this host");
585 else if (mode
== TImode
)
587 /* ??? This is currently not handled at all. */
590 /* Note: lowest order word goes in lowest numbered reg. */
591 rsrc1
= INTVAL (src
);
592 if (rsrc1
>= 0 && rsrc1
< 32)
595 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
596 /* Go pick up the low-order word. */
598 else if (mode
== DImode
)
600 rtx upperhalf
, lowerhalf
;
603 if (GET_CODE (src
) == CONST_DOUBLE
)
605 upperhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_HIGH (src
));
606 lowerhalf
= gen_rtx (CONST_INT
, VOIDmode
, CONST_DOUBLE_LOW (src
));
608 else if (GET_CODE (src
) == CONST_INT
)
611 upperhalf
= INTVAL (src
) < 0 ? constm1_rtx
: const0_rtx
;
616 /* Note: lowest order word goes in lowest numbered reg. */
617 /* Numbers from 0 to 31 can be handled with a single insn. */
618 rsrc1
= INTVAL (lowerhalf
);
619 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
622 /* Output the upper half with a recursive call. */
623 string
= i960_output_ldconst (gen_rtx (REG
, SImode
, REGNO (dst
) + 1),
625 output_asm_insn (string
);
626 /* The lower word is emitted as normally. */
628 else if (mode
== SFmode
)
630 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
634 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
635 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
637 output_asm_insn ("# ldconst %1,%0",operands
);
638 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
639 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
640 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
643 if (fp_literal_zero (src
, VOIDmode
))
644 return "movr 0f0.0,%0";
645 if (fp_literal_one (src
, VOIDmode
))
646 return "movr 0f1.0,%0";
647 fatal ("inline float constants not supported on this host");
653 rsrc1
= INTVAL (src
);
659 else if (mode
== HImode
)
668 /* ldconst 0..31,X -> mov 0..31,X */
671 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
676 /* ldconst 32..63,X -> add 31,nn,X */
679 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
681 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
682 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
688 /* ldconst -1..-31 -> sub 0,0..31,X */
691 /* return 'sub -(%1),0,%0' */
692 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
693 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
697 /* ldconst -32 -> not 31,X */
700 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
701 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
706 /* If const is a single bit. */
707 if (bitpos (rsrc1
) >= 0)
709 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
710 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
714 /* If const is a bit string of less than 6 bits (1..31 shifted). */
719 if (bitstr (rsrc1
, &s
, &e
) < 6)
721 rsrc2
= ((unsigned int) rsrc1
) >> s
;
722 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
723 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
724 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
729 /* Unimplemented cases:
730 const is in range 0..31 but rotated around end of word:
731 ror 31,3,g0 -> ldconst 0xe0000003,g0
733 and any 2 instruction cases that might be worthwhile */
735 output_asm_insn ("ldconst %1,%0", operands
);
739 /* Determine if there is an opportunity for a bypass optimization.
740 Bypass succeeds on the 960K* if the destination of the previous
741 instruction is the second operand of the current instruction.
742 Bypass always succeeds on the C*.
744 Return 1 if the pattern should interchange the operands.
746 CMPBR_FLAG is true if this is for a compare-and-branch insn.
747 OP1 and OP2 are the two source operands of a 3 operand insn. */
750 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
751 register rtx insn
, op1
, op2
;
754 register rtx prev_insn
, prev_dest
;
759 /* Can't do this if op1 isn't a register. */
763 /* Can't do this for a compare-and-branch if both ops aren't regs. */
764 if (cmpbr_flag
&& ! REG_P (op2
))
767 prev_insn
= prev_real_insn (insn
);
769 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
770 && GET_CODE (PATTERN (prev_insn
)) == SET
)
772 prev_dest
= SET_DEST (PATTERN (prev_insn
));
773 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
774 || (GET_CODE (prev_dest
) == SUBREG
775 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
776 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
782 /* Output the code which declares the function name. This also handles
783 leaf routines, which have special requirements, and initializes some
787 i960_function_name_declare (file
, name
, fndecl
)
796 /* Increment global return label. */
800 /* Compute whether tail calls and leaf routine optimizations can be performed
801 for this function. */
813 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
814 argblock, because argblock uses g14 implicitly. */
816 if (current_function_args_size
!= 0)
822 /* See if caller passes in an address to return value. */
824 if (aggregate_value_p (DECL_RESULT (fndecl
)))
830 /* Can not use tail calls or make this a leaf routine if there is a non
833 if (get_frame_size () != 0)
836 /* I don't understand this condition, and do not think that it is correct.
837 Apparently this is just checking whether the frame pointer is used, and
838 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
841 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
842 if (GET_CODE (insn
) == INSN
843 && reg_mentioned_p (frame_pointer_rtx
, insn
))
849 /* Check for CALL insns. Can not be a leaf routine if there are any. */
852 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
853 if (GET_CODE (insn
) == CALL_INSN
)
859 /* Can not be a leaf routine if any non-call clobbered registers are
860 used in this function. */
863 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
864 if (regs_ever_live
[i
]
865 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
867 /* Global registers. */
868 if (i
< 16 && i
> 7 && i
!= 13)
870 /* Local registers. */
875 /* Now choose a leaf return register, if we can find one, and if it is
876 OK for this to be a leaf routine. */
878 i960_leaf_ret_reg
= -1;
880 if (optimize
&& leaf_proc_ok
)
882 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
883 if (regs_ever_live
[i
] == 0)
885 i960_leaf_ret_reg
= i
;
886 regs_ever_live
[i
] = 1;
891 /* Do this after choosing the leaf return register, so it will be listed
892 if one was chosen. */
894 fprintf (file
, "\t# Function '%s'\n", name
);
895 fprintf (file
, "\t# Registers used: ");
897 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
899 if (regs_ever_live
[i
])
901 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
903 if (i
> 15 && j
== 0)
905 fprintf (file
,"\n\t#\t\t ");
911 fprintf (file
, "\n");
913 if (i960_leaf_ret_reg
>= 0)
915 /* Make it a leaf procedure. */
917 if (TREE_PUBLIC (fndecl
))
918 fprintf (file
,"\t.globl %s.lf\n", name
);
920 fprintf (file
, "\t.leafproc\t_%s,%s.lf\n", name
, name
);
921 fprintf (file
, "_%s:\n", name
);
922 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
923 fprintf (file
, "%s.lf:\n", name
);
924 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
928 fprintf (file
, "\tlda 0,g14\n");
929 i960_last_insn_type
= I_TYPE_MEM
;
933 fprintf (file
, "\tmov 0,g14\n");
934 i960_last_insn_type
= I_TYPE_REG
;
939 ASM_OUTPUT_LABEL (file
, name
);
940 i960_last_insn_type
= I_TYPE_CTRL
;
944 /* Compute and return the frame size. */
947 compute_frame_size (size
)
951 int outgoing_args_size
952 = current_function_outgoing_args_size
+ current_function_pretend_args_size
;
954 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
955 as size is concerned. */
956 actual_fsize
= (size
+ 15) & -16;
957 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
962 /* Output code for the function prologue. */
965 i960_function_prologue (file
, size
)
969 register int i
, j
, nr
;
972 int actual_fsize
, offset
;
974 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
976 int regs
[FIRST_PSEUDO_REGISTER
];
978 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
979 if (regs_ever_live
[i
]
980 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
983 /* Count global registers that need saving. */
990 epilogue_string
[0] = '\0';
992 /* First look for local registers to save globals in. */
993 for (i
= 0; i
< 16; i
++)
998 /* Start at r4, not r3. */
999 for (j
= 20; j
< 32; j
++)
1006 regs_ever_live
[j
] = 1;
1008 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1009 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1014 regs_ever_live
[j
+1] = 1;
1016 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1017 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1022 regs_ever_live
[j
+2] = 1;
1024 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1029 regs_ever_live
[j
+3] = 1;
1032 fprintf (file
, "\tmov%s %s,%s\n",
1035 (nr
== 2) ? "l" : ""),
1036 reg_names
[i
], reg_names
[j
]);
1037 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1040 (nr
== 2) ? "l" : ""),
1041 reg_names
[j
], reg_names
[i
]);
1042 strcat (epilogue_string
, tmpstr
);
1050 /* N_iregs is now the number of global registers that haven't been saved
1053 rsize
= (n_iregs
* 4);
1054 actual_fsize
= compute_frame_size (size
) + rsize
;
1056 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1057 size up to the nearest multiple of 16. I don't know whether this is
1058 necessary, or even desirable.
1060 The frame pointer must be aligned, but the call instruction takes care of
1061 that. If we leave the stack pointer unaligned, we may save a little on
1062 dynamic stack allocation. And we don't lose, at least according to the
1064 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1067 /* Allocate space for register save and locals. */
1068 if (actual_fsize
> 0)
1070 if (actual_fsize
< 32)
1071 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1073 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1076 /* Take hardware register save area created by the call instruction
1078 offset
= compute_frame_size (size
) + 64;
1079 /* Save registers on stack if needed. */
1080 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1087 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1090 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1094 if (nr
== 3 && regs
[i
+3] == -1)
1097 fprintf (file
,"\tst%s %s,%d(fp)\n",
1100 (nr
== 2) ? "l" : ""),
1101 reg_names
[i
], offset
);
1102 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1105 (nr
== 2) ? "l" : ""),
1106 offset
, reg_names
[i
]);
1107 strcat (epilogue_string
, tmpstr
);
1113 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1116 fprintf (file
, "\t#Prologue stats:\n");
1117 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1120 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1122 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1124 fprintf (file
, "\t#End Prologue#\n");
1127 /* Output code for the function epilogue. */
1130 i960_function_epilogue (file
, size
)
1134 if (i960_leaf_ret_reg
>= 0)
1136 fprintf (file
, "LR%d: ret\n", ret_label
);
1140 if (*epilogue_string
== 0)
1144 /* Emit a return insn, but only if control can fall through to here. */
1146 tmp
= get_last_insn ();
1149 if (GET_CODE (tmp
) == BARRIER
)
1151 if (GET_CODE (tmp
) == CODE_LABEL
)
1153 if (GET_CODE (tmp
) == JUMP_INSN
)
1155 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1159 if (GET_CODE (tmp
) == NOTE
)
1161 tmp
= PREV_INSN (tmp
);
1166 fprintf (file
, "LR%d: ret\n", ret_label
);
1170 fprintf (file
, "LR%d:\n", ret_label
);
1172 fprintf (file
, "\t#EPILOGUE#\n");
1174 /* Output the string created by the prologue which will restore all
1175 registers saved by the prologue. */
1177 if (epilogue_string
[0] != '\0')
1178 fprintf (file
, "%s", epilogue_string
);
1180 /* Must clear g14 on return. */
1182 if (current_function_args_size
!= 0)
1183 fprintf (file
, "\tmov 0,g14\n");
1185 fprintf (file
, "\tret\n");
1186 fprintf (file
, "\t#End Epilogue#\n");
1189 /* Output code for a call insn. */
1192 i960_output_call_insn (target
, argsize_rtx
, insn
)
1193 register rtx target
, argsize_rtx
, insn
;
1196 int argsize
= INTVAL (argsize_rtx
);
1197 rtx nexti
= next_real_insn (insn
);
1200 operands
[0] = target
;
1202 non_indirect
= ((GET_CODE (target
) == MEM
)
1203 && (GET_CODE (XEXP (target
, 0)) == SYMBOL_REF
));
1205 /* Nexti could be zero if the called routine is volatile. */
1206 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1207 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1209 /* Delete following return insn. */
1210 if (nexti
&& no_labels_between_p (insn
, nexti
))
1211 delete_insn (nexti
);
1212 output_asm_insn (non_indirect
? "b %0" : "bx %0",
1214 return "# notreached";
1217 output_asm_insn (non_indirect
? "callj %0" : "callx %0", operands
);
1221 /* Output code for a return insn. */
1224 i960_output_ret_insn (insn
)
1227 static char lbuf
[20];
1229 if (*epilogue_string
!= 0)
1231 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1234 sprintf (lbuf
, "b LR%d", ret_label
);
1238 if (current_function_args_size
!= 0)
1239 output_asm_insn ("mov 0,g14", 0);
1241 if (i960_leaf_ret_reg
>= 0)
1243 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1250 /* Return a character string representing the branch prediction
1251 opcode to be tacked on an instruction. This must at least
1252 return a null string. */
1255 i960_br_predict_opcode (lab_ref
, insn
)
1258 if (TARGET_BRANCH_PREDICT
)
1260 unsigned long label_uid
;
1262 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1263 label_uid
= INSN_UID (lab_ref
);
1264 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1265 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1269 /* If not optimizing, then the insn_addresses array will not be
1270 valid. In this case, always return ".t" since most branches
1271 are taken. If optimizing, return .t for backward branches
1272 and .f for forward branches. */
1274 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1283 /* Print the operand represented by rtx X formatted by code CODE. */
1286 i960_print_operand (file
, x
, code
)
1291 enum rtx_code rtxcode
= GET_CODE (x
);
1298 /* Second reg of a double. */
1299 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1303 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1311 else if (rtxcode
== MEM
)
1313 output_address (XEXP (x
, 0));
1316 else if (rtxcode
== CONST_INT
)
1318 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1319 fprintf (file
, "0x%x", INTVAL (x
));
1321 fprintf (file
, "%d", INTVAL (x
));
1324 else if (rtxcode
== CONST_DOUBLE
)
1328 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1330 fprintf (file
, "0f0.0");
1333 else if (x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))
1335 fprintf (file
, "0f1.0");
1339 /* This better be a comment. */
1340 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1341 fprintf (file
, "%#g", d
);
1348 /* Branch or jump, depending on assembler. */
1349 if (TARGET_ASM_COMPAT
)
1356 /* Sign of condition. */
1357 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1358 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1360 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1361 || (rtxcode
== GE
) || (rtxcode
== LE
))
1368 /* Inverted condition. */
1369 rtxcode
= reverse_condition (rtxcode
);
1373 /* Inverted condition w/ reversed operands. */
1374 rtxcode
= reverse_condition (rtxcode
);
1378 /* Reversed operand condition. */
1379 rtxcode
= swap_condition (rtxcode
);
1383 /* Normal condition. */
1385 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1386 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1387 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1388 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1389 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1390 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1391 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1392 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1393 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1394 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1399 output_addr_const (file
, x
);
1409 /* Print a memory address as an operand to reference that memory location.
1411 This is exactly the same as legitimate_address_p, except that it the prints
1412 addresses instead of recognizing them. */
1415 i960_print_operand_addr (file
, addr
)
1427 if (GET_CODE (addr
) == REG
)
1429 else if (CONSTANT_P (addr
))
1431 else if (GET_CODE (addr
) == PLUS
)
1435 op0
= XEXP (addr
, 0);
1436 op1
= XEXP (addr
, 1);
1438 if (GET_CODE (op0
) == REG
)
1441 if (GET_CODE (op1
) == REG
)
1443 else if (CONSTANT_P (op1
))
1448 else if (GET_CODE (op0
) == PLUS
)
1450 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1452 ireg
= XEXP (XEXP (op0
, 0), 0);
1453 scale
= XEXP (XEXP (op0
, 0), 1);
1454 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1456 breg
= XEXP (op0
, 1);
1462 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1464 breg
= XEXP (op0
, 0);
1465 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1467 ireg
= XEXP (op0
, 1);
1476 else if (GET_CODE (op0
) == MULT
)
1478 ireg
= XEXP (op0
, 0);
1479 scale
= XEXP (op0
, 1);
1480 if (GET_CODE (op1
) == REG
)
1482 else if (CONSTANT_P (op1
))
1490 else if (GET_CODE (addr
) == MULT
)
1492 breg
= XEXP (addr
, 0);
1493 scale
= XEXP (addr
, 1);
1499 output_addr_const (file
, offset
);
1501 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1503 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1506 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1507 that is a valid memory address for an instruction.
1508 The MODE argument is the machine mode for the MEM expression
1509 that wants to use this address.
1511 On 80960, legitimate addresses are:
1513 disp (12 or 32 bit) ld foo,r0
1514 base + index ld (g0)[g1*1],r0
1515 base + displ ld 0xf00(g0),r0
1516 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1517 index*scale + base ld (g0)[g1*4],r0
1518 index*scale + displ ld 0xf00[g1*4],r0
1519 index*scale ld [g1*4],r0
1520 index + base + displ ld 0xf00(g0)[g1*1],r0
1522 In each case, scale can be 1, 2, 4, 8, or 16. */
1524 /* This is exactly the same as i960_print_operand_addr, except that
1525 it recognizes addresses instead of printing them.
1527 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1528 convert common non-canonical forms to canonical form so that they will
1532 legitimate_address_p (mode
, addr
, strict
)
1533 enum machine_mode mode
;
1537 if (GET_CODE (addr
) == REG
)
1538 return (strict
? REG_OK_FOR_BASE_P_STRICT (addr
)
1539 : REG_OK_FOR_BASE_P (addr
));
1540 else if (CONSTANT_P (addr
))
1542 else if (GET_CODE (addr
) == PLUS
)
1546 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1549 op0
= XEXP (addr
, 0);
1550 op1
= XEXP (addr
, 1);
1552 if (GET_CODE (op0
) == REG
)
1554 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (op0
)
1555 : REG_OK_FOR_BASE_P (op0
)))
1558 if (GET_CODE (op1
) == REG
)
1559 return (strict
? REG_OK_FOR_INDEX_P_STRICT (op1
)
1560 : REG_OK_FOR_INDEX_P (op1
));
1561 else if (CONSTANT_P (op1
))
1566 else if (GET_CODE (op0
) == PLUS
)
1568 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1570 if (! (GET_CODE (XEXP (XEXP (op0
, 0), 0)) == REG
1571 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (XEXP (op0
, 0), 0))
1572 : REG_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0)))
1573 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1576 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1577 return ((strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 1))
1578 : REG_OK_FOR_BASE_P (XEXP (op0
, 1)))
1579 && CONSTANT_P (op1
));
1583 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1585 if (! (strict
? REG_OK_FOR_BASE_P_STRICT (XEXP (op0
, 0))
1586 : REG_OK_FOR_BASE_P (XEXP (op0
, 0))))
1589 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1590 return ((strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 1))
1591 : REG_OK_FOR_INDEX_P (XEXP (op0
, 1)))
1592 && CONSTANT_P (op1
));
1599 else if (GET_CODE (op0
) == MULT
)
1601 if (! (GET_CODE (XEXP (op0
, 0)) == REG
1602 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0
, 0))
1603 : REG_OK_FOR_INDEX_P (XEXP (op0
, 0)))
1604 && SCALE_TERM_P (XEXP (op0
, 1))))
1607 if (GET_CODE (op1
) == REG
)
1608 return (strict
? REG_OK_FOR_BASE_P_STRICT (op1
)
1609 : REG_OK_FOR_BASE_P (op1
));
1610 else if (CONSTANT_P (op1
))
1618 else if (GET_CODE (addr
) == MULT
)
1620 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1623 return (GET_CODE (XEXP (addr
, 0)) == REG
1624 && (strict
? REG_OK_FOR_INDEX_P_STRICT (XEXP (addr
, 0))
1625 : REG_OK_FOR_INDEX_P (XEXP (addr
, 0)))
1626 && SCALE_TERM_P (XEXP (addr
, 1)));
1632 /* Try machine-dependent ways of modifying an illegitimate address
1633 to be legitimate. If we find one, return the new, valid address.
1634 This macro is used in only one place: `memory_address' in explow.c.
1636 This converts some non-canonical addresses to canonical form so they
1637 can be recognized. */
1640 legitimize_address (x
, oldx
, mode
)
1643 enum machine_mode mode
;
1645 if (GET_CODE (x
) == SYMBOL_REF
)
1648 x
= copy_to_reg (x
);
1651 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1654 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1655 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1656 created by virtual register instantiation, register elimination, and
1657 similar optimizations. */
1658 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1659 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1660 x
= gen_rtx (PLUS
, Pmode
,
1661 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1662 XEXP (XEXP (x
, 1), 1));
1664 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1665 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1666 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1667 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1668 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1669 && CONSTANT_P (XEXP (x
, 1)))
1671 rtx constant
, other
;
1673 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1675 constant
= XEXP (x
, 1);
1676 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1678 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1680 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1681 other
= XEXP (x
, 1);
1687 x
= gen_rtx (PLUS
, Pmode
,
1688 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1689 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1690 plus_constant (other
, INTVAL (constant
)));
1697 /* Return the most stringent alignment that we are willing to consider
1698 objects of size SIZE and known alignment ALIGN as having. */
1701 i960_alignment (size
, align
)
1707 if (! TARGET_STRICT_ALIGN
)
1708 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1710 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1719 /* Modes for condition codes. */
1721 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1723 /* Modes for single-word (and smaller) quantities. */
1726 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1727 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1729 /* Modes for double-word (and smaller) quantities. */
1732 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1734 /* Modes for quad-word quantities. */
1735 #define T_MODES (~C_MODES)
1737 /* Modes for single-float quantities. */
1738 #define SF_MODES ((1 << (int) SFmode))
1740 /* Modes for double-float quantities. */
1741 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1743 /* Modes for quad-float quantities. */
1744 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1746 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1747 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1748 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1749 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1750 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1752 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1755 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1756 advantage of machine specific facts, such as knowing that the frame pointer
1757 is always 16 byte aligned. */
1760 i960_expr_alignment (x
, size
)
1769 switch (GET_CODE(x
))
1774 if ((align
& 0xf) == 0)
1776 else if ((align
& 0x7) == 0)
1778 else if ((align
& 0x3) == 0)
1780 else if ((align
& 0x1) == 0)
1787 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1788 i960_expr_alignment (XEXP (x
, 1), size
));
1792 /* If this is a valid program, objects are guaranteed to be
1793 correctly aligned for whatever size the reference actually is. */
1794 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1798 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1804 align
= i960_expr_alignment (XEXP (x
, 0));
1806 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1808 align
= align
<< INTVAL (XEXP (x
, 1));
1809 align
= MIN (align
, 16);
1814 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1815 i960_expr_alignment (XEXP (x
, 1), size
));
1817 align
= MIN (align
, 16);
1824 /* Return true if it is possible to reference both BASE and OFFSET, which
1825 have alignment at least as great as 4 byte, as if they had alignment valid
1826 for an object of size SIZE. */
1829 i960_improve_align (base
, offset
, size
)
1836 /* We have at least a word reference to the object, so we know it has to
1837 be aligned at least to 4 bytes. */
1839 i
= MIN (i960_expr_alignment (base
, 4),
1840 i960_expr_alignment (offset
, 4));
1844 /* We know the size of the request. If strict align is not enabled, we
1845 can guess that the alignment is OK for the requested size. */
1847 if (! TARGET_STRICT_ALIGN
)
1848 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1854 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1855 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1858 i960_si_ti (base
, offset
)
1862 return i960_improve_align (base
, offset
, 16);
1865 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1866 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1869 i960_si_di (base
, offset
)
1873 return i960_improve_align (base
, offset
, 8);
1876 /* Return raw values of size and alignment (in words) for the data
1877 type being accessed. These values will be rounded by the caller. */
1880 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
1881 enum machine_mode mode
;
1888 /* Use formal alignment requirements of type being passed, except make
1889 it at least a word. If we don't have a type, this is a library call,
1890 and the parm has to be of scalar type. In this case, consider its
1891 formal alignment requirement to be its size in words. */
1893 if (mode
== BLKmode
)
1894 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1895 else if (mode
== VOIDmode
)
1897 /* End of parm list. */
1898 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
1902 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1906 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
1907 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
1915 /* On the 80960 the first 12 args are in registers and the rest are pushed.
1916 Any arg that is bigger than 4 words is placed on the stack and all
1917 subsequent arguments are placed on the stack.
1919 Additionally, parameters with an alignment requirement stronger than
1920 a word must be be aligned appropriately. */
1922 /* Update CUM to advance past an argument described by MODE and TYPE. */
1925 i960_function_arg_advance (cum
, mode
, type
, named
)
1926 CUMULATIVE_ARGS
*cum
;
1927 enum machine_mode mode
;
1933 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1935 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1936 || (size
+ ROUND (cum
->ca_nregparms
, align
)) > NPARM_REGS
1937 || MUST_PASS_IN_STACK (mode
, type
))
1938 cum
->ca_nstackparms
= ROUND (cum
->ca_nstackparms
, align
) + size
;
1940 cum
->ca_nregparms
= ROUND (cum
->ca_nregparms
, align
) + size
;
1943 /* Return the register that the argument described by MODE and TYPE is
1944 passed in, or else return 0 if it is passed on the stack. */
1947 i960_function_arg (cum
, mode
, type
, named
)
1948 CUMULATIVE_ARGS
*cum
;
1949 enum machine_mode mode
;
1956 i960_arg_size_and_align (mode
, type
, &size
, &align
);
1958 if (named
== 0 || size
> 4 || cum
->ca_nstackparms
!= 0
1959 || (size
+ ROUND (cum
->ca_nregparms
, align
)) > NPARM_REGS
1960 || MUST_PASS_IN_STACK (mode
, type
))
1962 cum
->ca_nstackparms
= ROUND (cum
->ca_nstackparms
, align
);
1967 cum
->ca_nregparms
= ROUND (cum
->ca_nregparms
, align
);
1968 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
1974 /* Return the rtx for the register representing the return value, or 0
1975 if the return value must be passed through the stack. */
1978 i960_function_value (type
)
1981 int mode
= TYPE_MODE (type
);
1983 if (mode
== BLKmode
)
1985 unsigned int size
= int_size_in_bytes (type
);
1988 mode
= mode_for_size (i960_object_bytes_bitalign (size
), MODE_INT
, 0);
1991 if (mode
== BLKmode
|| mode
== VOIDmode
)
1992 /* Tell stmt.c and expr.c to pass in address */
1995 return gen_rtx (REG
, mode
, 0);
1998 /* Floating-point support. */
2001 i960_output_double (file
, value
)
2005 if (REAL_VALUE_ISINF (value
))
2007 fprintf (file
, "\t.word 0\n");
2008 fprintf (file
, "\t.word 0x7ff00000 # Infinity\n");
2011 fprintf (file
, "\t.double 0d%.17e\n", (value
));
2015 i960_output_float (file
, value
)
2019 if (REAL_VALUE_ISINF (value
))
2020 fprintf (file
, "\t.word 0x7f800000 # Infinity\n");
2022 fprintf (file
, "\t.float 0f%.12e\n", (value
));
2025 /* Return the number of bits that an object of size N bytes is aligned to. */
2028 i960_object_bytes_bitalign (n
)
2032 else if (n
> 4) n
= 64;
2033 else if (n
> 2) n
= 32;
2034 else if (n
> 1) n
= 16;
2040 /* Compute the size of an aggregate type TSIZE. */
2043 i960_round_size (tsize
)
2048 if (TREE_CODE (tsize
) != INTEGER_CST
)
2051 size
= TREE_INT_CST_LOW (tsize
);
2052 align
= i960_object_bytes_bitalign (size
/ BITS_PER_UNIT
);
2054 /* Handle #pragma align. */
2055 if (align
> i960_maxbitalignment
)
2056 align
= i960_maxbitalignment
;
2059 size
= ((size
/ align
) + 1) * align
;
2061 return size_int (size
);
2064 /* Compute the alignment for an aggregate type TSIZE. */
2067 i960_round_align (align
, tsize
)
2071 if (TREE_CODE (tsize
) != INTEGER_CST
)
2074 align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2079 /* Do any needed setup for a varargs function. For the i960, we must
2080 create a register parameter block if one doesn't exist, and then copy
2081 all register parameters to memory. */
2084 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2085 CUMULATIVE_ARGS
*cum
;
2086 enum machine_mode mode
;
2091 if (cum
->ca_nregparms
< NPARM_REGS
)
2093 int first_reg_offset
= cum
->ca_nregparms
;
2095 if (first_reg_offset
> NPARM_REGS
)
2096 first_reg_offset
= NPARM_REGS
;
2098 if (! (no_rtl
) && first_reg_offset
!= NPARM_REGS
)
2100 rtx label
= gen_label_rtx ();
2101 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2102 emit_jump_insn (gen_bne (label
));
2103 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2104 stack_pointer_rtx
));
2105 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2106 memory_address (SImode
,
2107 plus_constant (stack_pointer_rtx
,
2112 gen_rtx (MEM
, BLKmode
, virtual_incoming_args_rtx
),
2113 NPARM_REGS
- first_reg_offset
);
2115 *pretend_size
= (NPARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
;
2119 /* Calculate the final size of the reg parm stack space for the current
2120 function, based on how many bytes would be allocated on the stack. */
2123 i960_final_reg_parm_stack_space (const_size
, var_size
)
2127 if (var_size
|| const_size
> 48)
2133 /* Calculate the size of the reg parm stack space. This is a bit complicated
2137 i960_reg_parm_stack_space (fndecl
)
2140 /* In this case, we are called from emit_library_call, and we don't need
2141 to pretend we have more space for parameters than what's apparent. */
2145 /* In this case, we are called from locate_and_pad_parms when we're
2146 not IN_REGS, so we have an arg block. */
2147 if (fndecl
!= current_function_decl
)
2150 /* Otherwise, we have an arg block if the current function has more than
2151 48 bytes of parameters. */
2152 if (current_function_args_size
!= 0)
2158 /* Return the register class of a scratch register needed to copy IN into
2159 or out of a register in CLASS in MODE. If it can be done directly,
2160 NO_REGS is returned. */
2163 secondary_reload_class (class, mode
, in
)
2164 enum reg_class
class;
2165 enum machine_mode mode
;
2170 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2171 regno
= true_regnum (in
);
2173 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2174 LOCAL_OR_GLOBAL_REGS into anything. */
2175 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2176 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2179 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2180 if (class == FP_REGS
2181 && ((regno
>= 0 && regno
<= FIRST_PSEUDO_REGISTER
)
2182 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2185 return LOCAL_OR_GLOBAL_REGS
;
2188 /* Emit the code necessary for a procedure call. Return value is needed
2189 after the call if target is non-zero. */
2192 i960_expand_call (first_operand
, second_operand
, target
)
2193 rtx first_operand
, second_operand
, target
;
2195 /* Used to ensure that g14_save_reg is initialized once and only once
2196 for each function if it is needed. */
2197 static char *this_function_name
= 0;
2200 if (this_function_name
!= current_function_name
)
2203 struct sequence_stack
*seq_stack
;
2205 this_function_name
= current_function_name
;
2207 /* If the current function has an argument block, then save g14 into
2208 a pseudo at the top of the function and restore it after this
2209 function call. If the current function has no argument block,
2210 then g14 is zero before and after the call. */
2212 if (current_function_args_size
!= 0)
2215 seq_stack
= sequence_stack
;
2216 while (seq_stack
->next
)
2217 seq_stack
= seq_stack
->next
;
2218 first
= seq_stack
->first
;
2219 g14_save_reg
= copy_to_reg (arg_pointer_rtx
);
2220 seq
= gen_sequence ();
2222 emit_insn_after (seq
, first
);
2226 if (current_function_args_size
!= 0)
2229 if (GET_CODE (second_operand
) != CONST_INT
|| INTVAL (second_operand
) > 48)
2231 /* Calling a function needing an argument block. */
2232 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2233 virtual_outgoing_args_rtx
));
2237 /* Calling a normal function -- only set to zero if we know our g14
2240 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
, const0_rtx
));
2244 emit_call_insn (gen_rtx (SET
, VOIDmode
, target
,
2245 gen_rtx (CALL
, VOIDmode
, first_operand
,
2248 emit_call_insn (gen_rtx (CALL
, VOIDmode
, first_operand
, second_operand
));
2251 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
, g14_save_reg
));
2252 else if (GET_CODE (second_operand
) != CONST_INT
2253 || INTVAL (second_operand
) > 48)
2255 /* Calling a function needing an argument block. It will have set
2256 reg14 back to zero before returning, so we must emit a clobber here
2257 to tell cse that g14 has changed. */
2258 emit_insn (gen_rtx (CLOBBER
, VOIDmode
, arg_pointer_rtx
));
2262 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2263 function unit it executed on. */
2265 /* ??? This would make more sense as an attribute. */
2268 i960_scan_opcode (p
)
2280 /* Ret is not actually of type REG, but it won't matter, because no
2281 insn will ever follow it. */
2284 i960_last_insn_type
= I_TYPE_REG
;
2288 if (p
[1] == 'x' || p
[3] == 'x')
2289 i960_last_insn_type
= I_TYPE_MEM
;
2290 i960_last_insn_type
= I_TYPE_CTRL
;
2295 i960_last_insn_type
= I_TYPE_CTRL
;
2302 i960_last_insn_type
= I_TYPE_MEM
;
2304 i960_last_insn_type
= I_TYPE_CTRL
;
2306 else if (p
[1] == 'm')
2309 i960_last_insn_type
= I_TYPE_REG
;
2310 else if (p
[4] == 'b' || p
[4] == 'j')
2311 i960_last_insn_type
= I_TYPE_CTRL
;
2313 i960_last_insn_type
= I_TYPE_REG
;
2316 i960_last_insn_type
= I_TYPE_REG
;
2320 i960_last_insn_type
= I_TYPE_MEM
;
2325 i960_last_insn_type
= I_TYPE_MEM
;
2327 i960_last_insn_type
= I_TYPE_REG
;