1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (finput
)
99 while (c
== ' ' || c
== '\t')
103 && getc (finput
) == 'l'
104 && getc (finput
) == 'i'
105 && getc (finput
) == 'g'
106 && getc (finput
) == 'n'
107 && ((c
= getc (finput
)) == ' ' || c
== '\t' || c
== '\n'))
113 while (c
== ' ' || c
== '\t')
117 while (c
>= '0' && c
<= '9')
119 if (s
< buf
+ sizeof buf
- 1)
129 /* Return to last alignment. */
130 align
= i960_last_maxbitalignment
/ 8;
137 i960_last_maxbitalignment
= i960_maxbitalignment
;
138 i960_maxbitalignment
= align
* 8;
142 /* Silently ignore bad values. */
146 /* NOTE: ic960 R3.0 pragma align definition:
148 #pragma align [(size)] | (identifier=size[,...])
149 #pragma noalign [(identifier)[,...]]
151 (all parens are optional)
153 - size is [1,2,4,8,16]
154 - noalign means size==1
155 - applies only to component elements of a struct (and union?)
156 - identifier applies to structure tag (only)
157 - missing identifier means next struct
159 - alignment rules for bitfields need more investigation */
162 /* Should be pragma 'far' or equivalent for callx/balx here. */
167 /* Initialize variables before compiling any files. */
172 if (TARGET_IC_COMPAT2_0
)
174 i960_maxbitalignment
= 8;
175 i960_last_maxbitalignment
= 128;
179 i960_maxbitalignment
= 128;
180 i960_last_maxbitalignment
= 8;
184 /* Return true if OP can be used as the source of an fp move insn. */
187 fpmove_src_operand (op
, mode
)
189 enum machine_mode mode
;
191 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
195 /* Return true if OP is a register or zero. */
198 reg_or_zero_operand (op
, mode
)
200 enum machine_mode mode
;
202 return register_operand (op
, mode
) || op
== const0_rtx
;
206 /* Return truth value of whether OP can be used as an operands in a three
207 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
210 arith_operand (op
, mode
)
212 enum machine_mode mode
;
214 return (register_operand (op
, mode
) || literal (op
, mode
));
217 /* Return true if OP is a register or a valid floating point literal. */
220 fp_arith_operand (op
, mode
)
222 enum machine_mode mode
;
224 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
227 /* Return true is OP is a register or a valid signed integer literal. */
230 signed_arith_operand (op
, mode
)
232 enum machine_mode mode
;
234 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
237 /* Return truth value of whether OP is a integer which fits the
238 range constraining immediate operands in three-address insns. */
243 enum machine_mode mode
;
245 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
248 /* Return true if OP is a float constant of 1. */
251 fp_literal_one (op
, mode
)
253 enum machine_mode mode
;
255 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
258 /* Return true if OP is a float constant of 0. */
261 fp_literal_zero (op
, mode
)
263 enum machine_mode mode
;
265 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
268 /* Return true if OP is a valid floating point literal. */
273 enum machine_mode mode
;
275 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
278 /* Return true if OP is a valid signed immediate constant. */
281 signed_literal(op
, mode
)
283 enum machine_mode mode
;
285 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
288 /* Return truth value of statement that OP is a symbolic memory
289 operand of mode MODE. */
292 symbolic_memory_operand (op
, mode
)
294 enum machine_mode mode
;
296 if (GET_CODE (op
) == SUBREG
)
297 op
= SUBREG_REG (op
);
298 if (GET_CODE (op
) != MEM
)
301 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
302 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
305 /* Return truth value of whether OP is EQ or NE. */
310 enum machine_mode mode
;
312 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
315 /* OP is an integer register or a constant. */
318 arith32_operand (op
, mode
)
320 enum machine_mode mode
;
322 if (register_operand (op
, mode
))
324 return (CONSTANT_P (op
));
327 /* Return true if OP is an integer constant which is a power of 2. */
330 power2_operand (op
,mode
)
332 enum machine_mode mode
;
334 if (GET_CODE (op
) != CONST_INT
)
337 return exact_log2 (INTVAL (op
)) >= 0;
340 /* Return true if OP is an integer constant which is the complement of a
344 cmplpower2_operand (op
, mode
)
346 enum machine_mode mode
;
348 if (GET_CODE (op
) != CONST_INT
)
351 return exact_log2 (~ INTVAL (op
)) >= 0;
354 /* If VAL has only one bit set, return the index of that bit. Otherwise
363 for (i
= 0; val
!= 0; i
++, val
>>= 1)
375 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
376 The return value indicates how many consecutive non-zero bits exist
377 if this is a mask. This is the same as the next function, except that
378 it does not indicate what the start and stop bit positions are. */
384 register int start
, end
, i
;
387 for (i
= 0; val
!= 0; val
>>= 1, i
++)
397 /* Still looking for the first bit. */
401 /* We've seen the start of a bit sequence, and now a zero. There
402 must be more one bits, otherwise we would have exited the loop.
403 Therefore, it is not a mask. */
408 /* The bit string has ones from START to END bit positions only. */
409 return end
- start
+ 1;
412 /* If VAL is a mask, then return nonzero, with S set to the starting bit
413 position and E set to the ending bit position of the mask. The return
414 value indicates how many consecutive bits exist in the mask. This is
415 the same as the previous function, except that it also indicates the
416 start and end bit positions of the mask. */
423 register int start
, end
, i
;
427 for (i
= 0; val
!= 0; val
>>= 1, i
++)
438 /* Still looking for the first bit. */
442 /* We've seen the start of a bit sequence, and now a zero. There
443 must be more one bits, otherwise we would have exited the loop.
444 Therefor, it is not a mask. */
453 /* The bit string has ones from START to END bit positions only. */
456 return ((start
< 0) ? 0 : end
- start
+ 1);
459 /* Return the machine mode to use for a comparison. */
462 select_cc_mode (op
, x
)
466 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
471 /* X and Y are two things to compare using CODE. Emit the compare insn and
472 return the rtx for register 36 in the proper mode. */
475 gen_compare_reg (code
, x
, y
)
480 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
481 enum machine_mode mode
482 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
486 if (! arith_operand (x
, mode
))
487 x
= force_reg (SImode
, x
);
488 if (! arith_operand (y
, mode
))
489 y
= force_reg (SImode
, y
);
492 cc_reg
= gen_rtx (REG
, ccmode
, 36);
493 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
494 gen_rtx (COMPARE
, ccmode
, x
, y
)));
499 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
500 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
501 are 4. Indexed addresses are cost 6. */
503 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
506 i960_address_cost (x
)
510 /* Handled before calling here. */
511 if (GET_CODE (x
) == REG
)
514 if (GET_CODE (x
) == PLUS
)
516 rtx base
= XEXP (x
, 0);
517 rtx offset
= XEXP (x
, 1);
519 if (GET_CODE (base
) == SUBREG
)
520 base
= SUBREG_REG (base
);
521 if (GET_CODE (offset
) == SUBREG
)
522 offset
= SUBREG_REG (offset
);
524 if (GET_CODE (base
) == REG
)
526 if (GET_CODE (offset
) == REG
)
528 if (GET_CODE (offset
) == CONST_INT
)
530 if ((unsigned)INTVAL (offset
) < 2047)
534 if (CONSTANT_P (offset
))
537 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
540 /* This is an invalid address. The return value doesn't matter, but
541 for convenience we make this more expensive than anything else. */
544 if (GET_CODE (x
) == MULT
)
547 /* Symbol_refs and other unrecognized addresses are cost 4. */
551 /* Emit insns to move operands[1] into operands[0].
553 Return 1 if we have written out everything that needs to be done to
554 do the move. Otherwise, return 0 and the caller will emit the move
558 emit_move_sequence (operands
, mode
)
560 enum machine_mode mode
;
562 register rtx operand0
= operands
[0];
563 register rtx operand1
= operands
[1];
565 /* We can only store registers to memory. */
567 if (GET_CODE (operand0
) == MEM
&& GET_CODE (operand1
) != REG
)
568 operands
[1] = force_reg (mode
, operand1
);
573 /* Emit insns to load a constant. Uses several strategies to try to use
574 as few insns as possible. */
577 i960_output_ldconst (dst
, src
)
578 register rtx dst
, src
;
581 register unsigned rsrc2
;
582 enum machine_mode mode
= GET_MODE (dst
);
585 operands
[0] = operands
[2] = dst
;
586 operands
[1] = operands
[3] = src
;
588 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
589 must be a ldconst insn. */
591 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
593 output_asm_insn ("ldconst %1,%0", operands
);
596 else if (mode
== DFmode
)
600 if (fp_literal_zero (src
, DFmode
))
603 split_double (src
, &first
, &second
);
605 output_asm_insn ("# ldconst %1,%0",operands
);
607 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
609 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
611 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
612 operands
[1] = second
;
613 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
617 else if (mode
== TImode
)
619 /* ??? This is currently not handled at all. */
622 /* Note: lowest order word goes in lowest numbered reg. */
623 rsrc1
= INTVAL (src
);
624 if (rsrc1
>= 0 && rsrc1
< 32)
627 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
628 /* Go pick up the low-order word. */
630 else if (mode
== DImode
)
632 rtx upperhalf
, lowerhalf
, xoperands
[2];
634 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
635 split_double (src
, &lowerhalf
, &upperhalf
);
640 /* Note: lowest order word goes in lowest numbered reg. */
641 /* Numbers from 0 to 31 can be handled with a single insn. */
642 rsrc1
= INTVAL (lowerhalf
);
643 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
646 /* Output the upper half with a recursive call. */
647 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
648 xoperands
[1] = upperhalf
;
649 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
651 /* The lower word is emitted as normally. */
653 else if (mode
== SFmode
)
658 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
659 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
661 output_asm_insn ("# ldconst %1,%0",operands
);
662 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
663 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
664 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
670 rsrc1
= INTVAL (src
);
676 else if (mode
== HImode
)
685 /* ldconst 0..31,X -> mov 0..31,X */
688 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
693 /* ldconst 32..63,X -> add 31,nn,X */
696 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
698 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
699 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
705 /* ldconst -1..-31 -> sub 0,0..31,X */
708 /* return 'sub -(%1),0,%0' */
709 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
710 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
714 /* ldconst -32 -> not 31,X */
717 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
718 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
723 /* If const is a single bit. */
724 if (bitpos (rsrc1
) >= 0)
726 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
727 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
731 /* If const is a bit string of less than 6 bits (1..31 shifted). */
736 if (bitstr (rsrc1
, &s
, &e
) < 6)
738 rsrc2
= ((unsigned int) rsrc1
) >> s
;
739 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
740 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
741 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
746 /* Unimplemented cases:
747 const is in range 0..31 but rotated around end of word:
748 ror 31,3,g0 -> ldconst 0xe0000003,g0
750 and any 2 instruction cases that might be worthwhile */
752 output_asm_insn ("ldconst %1,%0", operands
);
756 /* Determine if there is an opportunity for a bypass optimization.
757 Bypass succeeds on the 960K* if the destination of the previous
758 instruction is the second operand of the current instruction.
759 Bypass always succeeds on the C*.
761 Return 1 if the pattern should interchange the operands.
763 CMPBR_FLAG is true if this is for a compare-and-branch insn.
764 OP1 and OP2 are the two source operands of a 3 operand insn. */
767 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
768 register rtx insn
, op1
, op2
;
771 register rtx prev_insn
, prev_dest
;
776 /* Can't do this if op1 isn't a register. */
780 /* Can't do this for a compare-and-branch if both ops aren't regs. */
781 if (cmpbr_flag
&& ! REG_P (op2
))
784 prev_insn
= prev_real_insn (insn
);
786 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
787 && GET_CODE (PATTERN (prev_insn
)) == SET
)
789 prev_dest
= SET_DEST (PATTERN (prev_insn
));
790 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
791 || (GET_CODE (prev_dest
) == SUBREG
792 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
793 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
799 /* Output the code which declares the function name. This also handles
800 leaf routines, which have special requirements, and initializes some
804 i960_function_name_declare (file
, name
, fndecl
)
813 /* Increment global return label. */
817 /* Compute whether tail calls and leaf routine optimizations can be performed
818 for this function. */
830 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
831 argblock, because argblock uses g14 implicitly. */
833 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
839 /* See if caller passes in an address to return value. */
841 if (aggregate_value_p (DECL_RESULT (fndecl
)))
847 /* Can not use tail calls or make this a leaf routine if there is a non
850 if (get_frame_size () != 0)
853 /* I don't understand this condition, and do not think that it is correct.
854 Apparently this is just checking whether the frame pointer is used, and
855 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
858 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
859 if (GET_CODE (insn
) == INSN
860 && reg_mentioned_p (frame_pointer_rtx
, insn
))
866 /* Check for CALL insns. Can not be a leaf routine if there are any. */
869 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
870 if (GET_CODE (insn
) == CALL_INSN
)
876 /* Can not be a leaf routine if any non-call clobbered registers are
877 used in this function. */
880 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
881 if (regs_ever_live
[i
]
882 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
884 /* Global registers. */
885 if (i
< 16 && i
> 7 && i
!= 13)
887 /* Local registers. */
892 /* Now choose a leaf return register, if we can find one, and if it is
893 OK for this to be a leaf routine. */
895 i960_leaf_ret_reg
= -1;
897 if (optimize
&& leaf_proc_ok
)
899 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
900 if (regs_ever_live
[i
] == 0)
902 i960_leaf_ret_reg
= i
;
903 regs_ever_live
[i
] = 1;
908 /* Do this after choosing the leaf return register, so it will be listed
909 if one was chosen. */
911 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
912 fprintf (file
, "\t# Registers used: ");
914 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
916 if (regs_ever_live
[i
])
918 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
920 if (i
> 15 && j
== 0)
922 fprintf (file
,"\n\t#\t\t ");
928 fprintf (file
, "\n");
930 if (i960_leaf_ret_reg
>= 0)
932 /* Make it a leaf procedure. */
934 if (TREE_PUBLIC (fndecl
))
935 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
937 fprintf (file
, "\t.leafproc\t");
938 assemble_name (file
, name
);
939 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
940 ASM_OUTPUT_LABEL (file
, name
);
941 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
942 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
943 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
947 fprintf (file
, "\tlda 0,g14\n");
948 i960_last_insn_type
= I_TYPE_MEM
;
952 fprintf (file
, "\tmov 0,g14\n");
953 i960_last_insn_type
= I_TYPE_REG
;
958 ASM_OUTPUT_LABEL (file
, name
);
959 i960_last_insn_type
= I_TYPE_CTRL
;
963 /* Compute and return the frame size. */
966 compute_frame_size (size
)
970 int outgoing_args_size
= current_function_outgoing_args_size
;
972 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
973 as size is concerned. */
974 actual_fsize
= (size
+ 15) & -16;
975 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
980 /* Output code for the function prologue. */
983 i960_function_prologue (file
, size
)
987 register int i
, j
, nr
;
990 int actual_fsize
, offset
;
992 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
994 int regs
[FIRST_PSEUDO_REGISTER
];
996 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
997 if (regs_ever_live
[i
]
998 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1001 /* Count global registers that need saving. */
1008 epilogue_string
[0] = '\0';
1010 if (profile_flag
|| profile_block_flag
)
1012 /* When profiling, we may use registers 20 to 27 to save arguments, so
1013 they can't be used here for saving globals. J is the number of
1014 argument registers the mcount call will save. */
1015 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1018 for (i
= 20; i
<= j
+ 20; i
++)
1022 /* First look for local registers to save globals in. */
1023 for (i
= 0; i
< 16; i
++)
1028 /* Start at r4, not r3. */
1029 for (j
= 20; j
< 32; j
++)
1036 regs_ever_live
[j
] = 1;
1038 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1039 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1044 regs_ever_live
[j
+1] = 1;
1046 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1047 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1052 regs_ever_live
[j
+2] = 1;
1054 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1059 regs_ever_live
[j
+3] = 1;
1062 fprintf (file
, "\tmov%s %s,%s\n",
1065 (nr
== 2) ? "l" : ""),
1066 reg_names
[i
], reg_names
[j
]);
1067 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1070 (nr
== 2) ? "l" : ""),
1071 reg_names
[j
], reg_names
[i
]);
1072 strcat (epilogue_string
, tmpstr
);
1080 /* N_iregs is now the number of global registers that haven't been saved
1083 rsize
= (n_iregs
* 4);
1084 actual_fsize
= compute_frame_size (size
) + rsize
;
1086 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1087 size up to the nearest multiple of 16. I don't know whether this is
1088 necessary, or even desirable.
1090 The frame pointer must be aligned, but the call instruction takes care of
1091 that. If we leave the stack pointer unaligned, we may save a little on
1092 dynamic stack allocation. And we don't lose, at least according to the
1094 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1097 /* Allocate space for register save and locals. */
1098 if (actual_fsize
> 0)
1100 if (actual_fsize
< 32)
1101 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1103 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1106 /* Take hardware register save area created by the call instruction
1107 into account, but store them before the argument block area. */
1108 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1109 /* Save registers on stack if needed. */
1110 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1117 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1120 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1124 if (nr
== 3 && regs
[i
+3] == -1)
1127 fprintf (file
,"\tst%s %s,%d(fp)\n",
1130 (nr
== 2) ? "l" : ""),
1131 reg_names
[i
], offset
);
1132 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1135 (nr
== 2) ? "l" : ""),
1136 offset
, reg_names
[i
]);
1137 strcat (epilogue_string
, tmpstr
);
1143 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1146 fprintf (file
, "\t#Prologue stats:\n");
1147 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1150 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1152 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1154 fprintf (file
, "\t#End Prologue#\n");
1157 /* Output code for the function profiler. */
1160 output_function_profiler (file
, labelno
)
1164 /* The last used parameter register. */
1166 int i
, j
, increment
;
1167 int varargs_stdarg_function
1168 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1170 /* Figure out the last used parameter register. The proper thing to do
1171 is to walk incoming args of the function. A function might have live
1172 parameter registers even if it has no incoming args. Note that we
1173 don't have to save parameter registers g8 to g11 because they are
1176 /* See also output_function_prologue, which tries to use local registers
1177 for preserved call-saved global registers. */
1179 for (last_parm_reg
= 7;
1180 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1184 /* Save parameter registers in regs r4 (20) to r11 (27). */
1186 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1188 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1190 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1192 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1197 fprintf (file
, "\tmov%s g%d,r%d\n",
1198 (increment
== 4 ? "q" : increment
== 3 ? "t"
1199 : increment
== 2 ? "l": ""), i
, j
);
1202 /* If this function uses the arg pointer, then save it in r3 and then
1205 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1206 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1208 /* Load location address into g0 and call mcount. */
1210 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1212 /* If this function uses the arg pointer, restore it. */
1214 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1215 fprintf (file
, "\tmov r3,g14\n");
1217 /* Restore parameter registers. */
1219 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1221 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1223 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1225 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1230 fprintf (file
, "\tmov%s r%d,g%d\n",
1231 (increment
== 4 ? "q" : increment
== 3 ? "t"
1232 : increment
== 2 ? "l": ""), j
, i
);
1236 /* Output code for the function epilogue. */
1239 i960_function_epilogue (file
, size
)
1243 if (i960_leaf_ret_reg
>= 0)
1245 fprintf (file
, "LR%d: ret\n", ret_label
);
1249 if (*epilogue_string
== 0)
1253 /* Emit a return insn, but only if control can fall through to here. */
1255 tmp
= get_last_insn ();
1258 if (GET_CODE (tmp
) == BARRIER
)
1260 if (GET_CODE (tmp
) == CODE_LABEL
)
1262 if (GET_CODE (tmp
) == JUMP_INSN
)
1264 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1268 if (GET_CODE (tmp
) == NOTE
)
1270 tmp
= PREV_INSN (tmp
);
1275 fprintf (file
, "LR%d: ret\n", ret_label
);
1279 fprintf (file
, "LR%d:\n", ret_label
);
1281 fprintf (file
, "\t#EPILOGUE#\n");
1283 /* Output the string created by the prologue which will restore all
1284 registers saved by the prologue. */
1286 if (epilogue_string
[0] != '\0')
1287 fprintf (file
, "%s", epilogue_string
);
1289 /* Must clear g14 on return. */
1291 if (current_function_args_size
!= 0
1292 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1293 fprintf (file
, "\tmov 0,g14\n");
1295 fprintf (file
, "\tret\n");
1296 fprintf (file
, "\t#End Epilogue#\n");
1299 /* Output code for a call insn. */
1302 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1303 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1305 int argsize
= INTVAL (argsize_rtx
);
1306 rtx nexti
= next_real_insn (insn
);
1308 int varargs_stdarg_function
1309 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1311 operands
[0] = target
;
1312 operands
[1] = arg_pointer
;
1314 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1315 output_asm_insn ("mov g14,r3", operands
);
1318 output_asm_insn ("lda %a1,g14", operands
);
1319 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1320 output_asm_insn ("mov 0,g14", operands
);
1322 /* The code used to assume that calls to SYMBOL_REFs could not be more
1323 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1324 feature is now implemented by relaxing in the GNU linker. It can convert
1325 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1327 /* Nexti could be zero if the called routine is volatile. */
1328 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1329 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1331 /* Delete following return insn. */
1332 if (nexti
&& no_labels_between_p (insn
, nexti
))
1333 delete_insn (nexti
);
1334 output_asm_insn ("bx %0", operands
);
1335 return "# notreached";
1338 output_asm_insn ("callx %0", operands
);
1340 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1341 output_asm_insn ("mov r3,g14", operands
);
1346 /* Output code for a return insn. */
1349 i960_output_ret_insn (insn
)
1352 static char lbuf
[20];
1354 if (*epilogue_string
!= 0)
1356 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1359 sprintf (lbuf
, "b LR%d", ret_label
);
1363 if (current_function_args_size
!= 0
1364 || VARARGS_STDARG_FUNCTION (current_function_decl
))
1365 output_asm_insn ("mov 0,g14", 0);
1367 if (i960_leaf_ret_reg
>= 0)
1369 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1376 /* Return a character string representing the branch prediction
1377 opcode to be tacked on an instruction. This must at least
1378 return a null string. */
1381 i960_br_predict_opcode (lab_ref
, insn
)
1384 if (TARGET_BRANCH_PREDICT
)
1386 unsigned long label_uid
;
1388 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1389 label_uid
= INSN_UID (lab_ref
);
1390 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1391 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1395 /* If not optimizing, then the insn_addresses array will not be
1396 valid. In this case, always return ".t" since most branches
1397 are taken. If optimizing, return .t for backward branches
1398 and .f for forward branches. */
1400 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1409 /* Print the operand represented by rtx X formatted by code CODE. */
1412 i960_print_operand (file
, x
, code
)
1417 enum rtx_code rtxcode
= GET_CODE (x
);
1424 /* Second reg of a double. */
1425 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1429 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1437 else if (rtxcode
== MEM
)
1439 output_address (XEXP (x
, 0));
1442 else if (rtxcode
== CONST_INT
)
1444 if (INTVAL (x
) > 9999 || INTVAL (x
) < -999)
1445 fprintf (file
, "0x%x", INTVAL (x
));
1447 fprintf (file
, "%d", INTVAL (x
));
1450 else if (rtxcode
== CONST_DOUBLE
)
1455 if (x
== CONST0_RTX (GET_MODE (x
)))
1457 fprintf (file
, "0f0.0");
1460 else if (x
== CONST1_RTX (GET_MODE (x
)))
1462 fprintf (file
, "0f1.0");
1466 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1467 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1468 fprintf (file
, "0f%s", dstr
);
1475 /* Branch or jump, depending on assembler. */
1476 if (TARGET_ASM_COMPAT
)
1483 /* Sign of condition. */
1484 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1485 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1487 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1488 || (rtxcode
== GE
) || (rtxcode
== LE
))
1495 /* Inverted condition. */
1496 rtxcode
= reverse_condition (rtxcode
);
1500 /* Inverted condition w/ reversed operands. */
1501 rtxcode
= reverse_condition (rtxcode
);
1505 /* Reversed operand condition. */
1506 rtxcode
= swap_condition (rtxcode
);
1510 /* Normal condition. */
1512 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1513 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1514 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1515 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1516 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1517 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1518 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1519 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1520 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1521 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1526 output_addr_const (file
, x
);
1536 /* Print a memory address as an operand to reference that memory location.
1538 This is exactly the same as legitimate_address_p, except that it the prints
1539 addresses instead of recognizing them. */
1542 i960_print_operand_addr (file
, addr
)
1554 if (GET_CODE (addr
) == REG
)
1556 else if (CONSTANT_P (addr
))
1558 else if (GET_CODE (addr
) == PLUS
)
1562 op0
= XEXP (addr
, 0);
1563 op1
= XEXP (addr
, 1);
1565 if (GET_CODE (op0
) == REG
)
1568 if (GET_CODE (op1
) == REG
)
1570 else if (CONSTANT_P (op1
))
1575 else if (GET_CODE (op0
) == PLUS
)
1577 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1579 ireg
= XEXP (XEXP (op0
, 0), 0);
1580 scale
= XEXP (XEXP (op0
, 0), 1);
1581 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1583 breg
= XEXP (op0
, 1);
1589 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1591 breg
= XEXP (op0
, 0);
1592 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1594 ireg
= XEXP (op0
, 1);
1603 else if (GET_CODE (op0
) == MULT
)
1605 ireg
= XEXP (op0
, 0);
1606 scale
= XEXP (op0
, 1);
1607 if (GET_CODE (op1
) == REG
)
1609 else if (CONSTANT_P (op1
))
1617 else if (GET_CODE (addr
) == MULT
)
1619 ireg
= XEXP (addr
, 0);
1620 scale
= XEXP (addr
, 1);
1626 output_addr_const (file
, offset
);
1628 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1630 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1633 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1634 that is a valid memory address for an instruction.
1635 The MODE argument is the machine mode for the MEM expression
1636 that wants to use this address.
1638 On 80960, legitimate addresses are:
1640 disp (12 or 32 bit) ld foo,r0
1641 base + index ld (g0)[g1*1],r0
1642 base + displ ld 0xf00(g0),r0
1643 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1644 index*scale + base ld (g0)[g1*4],r0
1645 index*scale + displ ld 0xf00[g1*4],r0
1646 index*scale ld [g1*4],r0
1647 index + base + displ ld 0xf00(g0)[g1*1],r0
1649 In each case, scale can be 1, 2, 4, 8, or 16. */
1651 /* This is exactly the same as i960_print_operand_addr, except that
1652 it recognizes addresses instead of printing them.
1654 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1655 convert common non-canonical forms to canonical form so that they will
1658 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1659 where a register is valid. */
1661 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1662 ((GET_CODE (X) == REG \
1663 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1664 || (GET_CODE (X) == SUBREG \
1665 && GET_CODE (SUBREG_REG (X)) == REG \
1666 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1667 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1669 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1670 ((GET_CODE (X) == REG \
1671 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1672 || (GET_CODE (X) == SUBREG \
1673 && GET_CODE (SUBREG_REG (X)) == REG \
1674 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1675 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1678 legitimate_address_p (mode
, addr
, strict
)
1679 enum machine_mode mode
;
1683 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1685 else if (CONSTANT_P (addr
))
1687 else if (GET_CODE (addr
) == PLUS
)
1691 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1694 op0
= XEXP (addr
, 0);
1695 op1
= XEXP (addr
, 1);
1697 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1699 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1701 else if (CONSTANT_P (op1
))
1706 else if (GET_CODE (op0
) == PLUS
)
1708 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1710 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1711 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1714 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1715 && CONSTANT_P (op1
))
1720 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1722 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1723 && CONSTANT_P (op1
))
1731 else if (GET_CODE (op0
) == MULT
)
1733 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1734 && SCALE_TERM_P (XEXP (op0
, 1))))
1737 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1739 else if (CONSTANT_P (op1
))
1747 else if (GET_CODE (addr
) == MULT
)
1749 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1752 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1753 && SCALE_TERM_P (XEXP (addr
, 1)));
1759 /* Try machine-dependent ways of modifying an illegitimate address
1760 to be legitimate. If we find one, return the new, valid address.
1761 This macro is used in only one place: `memory_address' in explow.c.
1763 This converts some non-canonical addresses to canonical form so they
1764 can be recognized. */
1767 legitimize_address (x
, oldx
, mode
)
1770 enum machine_mode mode
;
1772 if (GET_CODE (x
) == SYMBOL_REF
)
1775 x
= copy_to_reg (x
);
1778 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1781 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1782 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1783 created by virtual register instantiation, register elimination, and
1784 similar optimizations. */
1785 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1786 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1787 x
= gen_rtx (PLUS
, Pmode
,
1788 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
1789 XEXP (XEXP (x
, 1), 1));
1791 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1792 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1793 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
1794 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1795 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
1796 && CONSTANT_P (XEXP (x
, 1)))
1798 rtx constant
, other
;
1800 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1802 constant
= XEXP (x
, 1);
1803 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1805 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
1807 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
1808 other
= XEXP (x
, 1);
1814 x
= gen_rtx (PLUS
, Pmode
,
1815 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
1816 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
1817 plus_constant (other
, INTVAL (constant
)));
1824 /* Return the most stringent alignment that we are willing to consider
1825 objects of size SIZE and known alignment ALIGN as having. */
1828 i960_alignment (size
, align
)
1834 if (! TARGET_STRICT_ALIGN
)
1835 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
1837 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1846 /* Modes for condition codes. */
1848 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1850 /* Modes for single-word (and smaller) quantities. */
1853 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1854 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1856 /* Modes for double-word (and smaller) quantities. */
1859 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1861 /* Modes for quad-word quantities. */
1862 #define T_MODES (~C_MODES)
1864 /* Modes for single-float quantities. */
1865 #define SF_MODES ((1 << (int) SFmode))
1867 /* Modes for double-float quantities. */
1868 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1870 /* Modes for quad-float quantities. */
1871 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1873 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
1874 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1875 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1876 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1877 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1879 TF_MODES
, TF_MODES
, TF_MODES
, TF_MODES
, C_MODES
};
1882 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1883 advantage of machine specific facts, such as knowing that the frame pointer
1884 is always 16 byte aligned. */
1887 i960_expr_alignment (x
, size
)
1896 switch (GET_CODE(x
))
1901 if ((align
& 0xf) == 0)
1903 else if ((align
& 0x7) == 0)
1905 else if ((align
& 0x3) == 0)
1907 else if ((align
& 0x1) == 0)
1914 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
1915 i960_expr_alignment (XEXP (x
, 1), size
));
1919 /* If this is a valid program, objects are guaranteed to be
1920 correctly aligned for whatever size the reference actually is. */
1921 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
1925 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
1930 align
= i960_expr_alignment (XEXP (x
, 0));
1932 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1934 align
= align
<< INTVAL (XEXP (x
, 1));
1935 align
= MIN (align
, 16);
1940 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
1941 i960_expr_alignment (XEXP (x
, 1), size
));
1943 align
= MIN (align
, 16);
1950 /* Return true if it is possible to reference both BASE and OFFSET, which
1951 have alignment at least as great as 4 byte, as if they had alignment valid
1952 for an object of size SIZE. */
1955 i960_improve_align (base
, offset
, size
)
1962 /* We have at least a word reference to the object, so we know it has to
1963 be aligned at least to 4 bytes. */
1965 i
= MIN (i960_expr_alignment (base
, 4),
1966 i960_expr_alignment (offset
, 4));
1970 /* We know the size of the request. If strict align is not enabled, we
1971 can guess that the alignment is OK for the requested size. */
1973 if (! TARGET_STRICT_ALIGN
)
1974 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
1980 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1981 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1984 i960_si_ti (base
, offset
)
1988 return i960_improve_align (base
, offset
, 16);
1991 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1992 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1995 i960_si_di (base
, offset
)
1999 return i960_improve_align (base
, offset
, 8);
2002 /* Return raw values of size and alignment (in words) for the data
2003 type being accessed. These values will be rounded by the caller. */
2006 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2007 enum machine_mode mode
;
2014 /* Use formal alignment requirements of type being passed, except make
2015 it at least a word. If we don't have a type, this is a library call,
2016 and the parm has to be of scalar type. In this case, consider its
2017 formal alignment requirement to be its size in words. */
2019 if (mode
== BLKmode
)
2020 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2021 else if (mode
== VOIDmode
)
2023 /* End of parm list. */
2024 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2028 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2032 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2033 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2041 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2042 Any arg that is bigger than 4 words is placed on the stack and all
2043 subsequent arguments are placed on the stack.
2045 Additionally, parameters with an alignment requirement stronger than
2046 a word must be be aligned appropriately. */
2048 /* Update CUM to advance past an argument described by MODE and TYPE. */
2051 i960_function_arg_advance (cum
, mode
, type
, named
)
2052 CUMULATIVE_ARGS
*cum
;
2053 enum machine_mode mode
;
2059 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2061 if (size
> 4 || cum
->ca_nstackparms
!= 0
2062 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2063 || MUST_PASS_IN_STACK (mode
, type
))
2065 /* Indicate that all the registers are in use, even if all are not,
2066 so va_start will compute the right value. */
2067 cum
->ca_nregparms
= NPARM_REGS
;
2068 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2071 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2074 /* Return the register that the argument described by MODE and TYPE is
2075 passed in, or else return 0 if it is passed on the stack. */
2078 i960_function_arg (cum
, mode
, type
, named
)
2079 CUMULATIVE_ARGS
*cum
;
2080 enum machine_mode mode
;
2087 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2089 if (size
> 4 || cum
->ca_nstackparms
!= 0
2090 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2091 || MUST_PASS_IN_STACK (mode
, type
))
2093 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2098 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2099 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2105 /* Floating-point support. */
2108 i960_output_double (file
, value
)
2110 REAL_VALUE_TYPE value
;
2113 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2115 fprintf (file
, "\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2116 value_long
[0], value_long
[1]);
2120 i960_output_float (file
, value
)
2122 REAL_VALUE_TYPE value
;
2125 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2127 fprintf (file
, "\t.word\t0x%08lx\n", value_long
);
2130 /* Return the number of bits that an object of size N bytes is aligned to. */
2133 i960_object_bytes_bitalign (n
)
2137 else if (n
> 4) n
= 64;
2138 else if (n
> 2) n
= 32;
2139 else if (n
> 1) n
= 16;
2145 /* Compute the alignment for an aggregate type TSIZE.
2146 Alignment is MAX (greatest member alignment,
2147 MIN (pragma align, structure size alignment)). */
2150 i960_round_align (align
, tsize
)
2156 if (TREE_CODE (tsize
) != INTEGER_CST
)
2159 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2161 /* Handle #pragma align. */
2162 if (new_align
> i960_maxbitalignment
)
2163 new_align
= i960_maxbitalignment
;
2165 if (align
< new_align
)
2171 /* Do any needed setup for a varargs function. For the i960, we must
2172 create a register parameter block if one doesn't exist, and then copy
2173 all register parameters to memory. */
2176 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2177 CUMULATIVE_ARGS
*cum
;
2178 enum machine_mode mode
;
2183 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2184 int first_reg
= cum
->ca_nregparms
;
2186 /* Copy only unnamed register arguments to memory. If there are
2187 any stack parms, there are no unnamed arguments in registers, and
2188 an argument block was already allocated by the caller.
2189 Remember that any arg bigger than 4 words is passed on the stack as
2190 are all subsequent args.
2192 If there are no stack arguments but there are exactly NPARM_REGS
2193 registers, either there were no extra arguments or the caller
2194 allocated an argument block. */
2196 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2198 rtx label
= gen_label_rtx ();
2201 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2202 and we need to allocate a chunk to save the registers (if any
2203 arguments were passed on the stack the caller would allocate the
2204 48 bytes as well). We must allocate all 48 bytes (12*4) because
2205 va_start assumes it. */
2206 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2207 emit_jump_insn (gen_bne (label
));
2208 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2209 stack_pointer_rtx
));
2210 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2211 memory_address (SImode
,
2212 plus_constant (stack_pointer_rtx
,
2216 /* ??? Note that we unnecessarily store one extra register for stdarg
2217 fns. We could optimize this, but it's kept as for now. */
2218 regblock
= gen_rtx (MEM
, BLKmode
,
2219 plus_constant (arg_pointer_rtx
,
2221 move_block_from_reg (first_reg
, regblock
,
2222 NPARM_REGS
- first_reg
,
2223 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2227 /* Calculate the final size of the reg parm stack space for the current
2228 function, based on how many bytes would be allocated on the stack. */
2231 i960_final_reg_parm_stack_space (const_size
, var_size
)
2235 if (var_size
|| const_size
> 48)
2241 /* Calculate the size of the reg parm stack space. This is a bit complicated
2245 i960_reg_parm_stack_space (fndecl
)
2248 /* In this case, we are called from emit_library_call, and we don't need
2249 to pretend we have more space for parameters than what's apparent. */
2253 /* In this case, we are called from locate_and_pad_parms when we're
2254 not IN_REGS, so we have an arg block. */
2255 if (fndecl
!= current_function_decl
)
2258 /* Otherwise, we have an arg block if the current function has more than
2259 48 bytes of parameters. */
2260 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2266 /* Return the register class of a scratch register needed to copy IN into
2267 or out of a register in CLASS in MODE. If it can be done directly,
2268 NO_REGS is returned. */
2271 secondary_reload_class (class, mode
, in
)
2272 enum reg_class
class;
2273 enum machine_mode mode
;
2278 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2279 regno
= true_regnum (in
);
2281 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2282 LOCAL_OR_GLOBAL_REGS into anything. */
2283 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2284 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2287 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2288 if (class == FP_REGS
2289 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2290 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2293 return LOCAL_OR_GLOBAL_REGS
;
2296 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2297 function unit it executed on. */
2299 /* ??? This would make more sense as an attribute. */
2302 i960_scan_opcode (p
)
2314 /* Ret is not actually of type REG, but it won't matter, because no
2315 insn will ever follow it. */
2318 i960_last_insn_type
= I_TYPE_REG
;
2322 if (p
[1] == 'x' || p
[3] == 'x')
2323 i960_last_insn_type
= I_TYPE_MEM
;
2324 i960_last_insn_type
= I_TYPE_CTRL
;
2329 i960_last_insn_type
= I_TYPE_CTRL
;
2336 i960_last_insn_type
= I_TYPE_MEM
;
2338 i960_last_insn_type
= I_TYPE_CTRL
;
2340 else if (p
[1] == 'm')
2343 i960_last_insn_type
= I_TYPE_REG
;
2344 else if (p
[4] == 'b' || p
[4] == 'j')
2345 i960_last_insn_type
= I_TYPE_CTRL
;
2347 i960_last_insn_type
= I_TYPE_REG
;
2350 i960_last_insn_type
= I_TYPE_REG
;
2354 i960_last_insn_type
= I_TYPE_MEM
;
2359 i960_last_insn_type
= I_TYPE_MEM
;
2361 i960_last_insn_type
= I_TYPE_REG
;