1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
48 rtx i960_compare_op0
, i960_compare_op1
;
50 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
53 static int i960_maxbitalignment
;
54 static int i960_last_maxbitalignment
;
56 /* Used to implement switching between MEM and ALU insn types, for better
57 C series performance. */
59 enum insn_types i960_last_insn_type
;
61 /* The leaf-procedure return register. Set only if this is a leaf routine. */
63 static int i960_leaf_ret_reg
;
65 /* True if replacing tail calls with jumps is OK. */
67 static int tail_call_ok
;
69 /* A string containing a list of insns to emit in the epilogue so as to
70 restore all registers saved by the prologue. Created by the prologue
71 code as it saves registers away. */
73 char epilogue_string
[1000];
75 /* A unique number (per function) for return labels. */
77 static int ret_label
= 0;
79 /* This is true if FNDECL is either a varargs or a stdarg function.
80 This is used to help identify functions that use an argument block. */
82 #define VARARGS_STDARG_FUNCTION(FNDECL) \
83 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
84 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
85 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. */
93 process_pragma (finput
)
100 while (c
== ' ' || c
== '\t')
104 && getc (finput
) == 'l'
105 && getc (finput
) == 'i'
106 && getc (finput
) == 'g'
107 && getc (finput
) == 'n'
108 && ((c
= getc (finput
)) == ' ' || c
== '\t' || c
== '\n'))
114 while (c
== ' ' || c
== '\t')
118 while (c
>= '0' && c
<= '9')
120 if (s
< buf
+ sizeof buf
- 1)
130 /* Return to last alignment. */
131 align
= i960_last_maxbitalignment
/ 8;
138 i960_last_maxbitalignment
= i960_maxbitalignment
;
139 i960_maxbitalignment
= align
* 8;
143 /* Silently ignore bad values. */
147 /* NOTE: ic960 R3.0 pragma align definition:
149 #pragma align [(size)] | (identifier=size[,...])
150 #pragma noalign [(identifier)[,...]]
152 (all parens are optional)
154 - size is [1,2,4,8,16]
155 - noalign means size==1
156 - applies only to component elements of a struct (and union?)
157 - identifier applies to structure tag (only)
158 - missing identifier means next struct
160 - alignment rules for bitfields need more investigation */
163 /* Should be pragma 'far' or equivalent for callx/balx here. */
168 /* Initialize variables before compiling any files. */
173 if (TARGET_IC_COMPAT2_0
)
175 i960_maxbitalignment
= 8;
176 i960_last_maxbitalignment
= 128;
180 i960_maxbitalignment
= 128;
181 i960_last_maxbitalignment
= 8;
185 /* Return true if OP can be used as the source of an fp move insn. */
188 fpmove_src_operand (op
, mode
)
190 enum machine_mode mode
;
192 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
196 /* Return true if OP is a register or zero. */
199 reg_or_zero_operand (op
, mode
)
201 enum machine_mode mode
;
203 return register_operand (op
, mode
) || op
== const0_rtx
;
207 /* Return truth value of whether OP can be used as an operands in a three
208 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
211 arith_operand (op
, mode
)
213 enum machine_mode mode
;
215 return (register_operand (op
, mode
) || literal (op
, mode
));
218 /* Return truth value of whether OP can be used as an operands in a three
219 address logic insn, possibly complementing OP, of mode MODE. */
222 logic_operand (op
, mode
)
224 enum machine_mode mode
;
226 return (register_operand (op
, mode
)
227 || (GET_CODE (op
) == CONST_INT
228 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
231 /* Return true if OP is a register or a valid floating point literal. */
234 fp_arith_operand (op
, mode
)
236 enum machine_mode mode
;
238 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
241 /* Return true is OP is a register or a valid signed integer literal. */
244 signed_arith_operand (op
, mode
)
246 enum machine_mode mode
;
248 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
251 /* Return truth value of whether OP is a integer which fits the
252 range constraining immediate operands in three-address insns. */
257 enum machine_mode mode
;
259 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
262 /* Return true if OP is a float constant of 1. */
265 fp_literal_one (op
, mode
)
267 enum machine_mode mode
;
269 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
272 /* Return true if OP is a float constant of 0. */
275 fp_literal_zero (op
, mode
)
277 enum machine_mode mode
;
279 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
282 /* Return true if OP is a valid floating point literal. */
287 enum machine_mode mode
;
289 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
292 /* Return true if OP is a valid signed immediate constant. */
295 signed_literal(op
, mode
)
297 enum machine_mode mode
;
299 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
302 /* Return truth value of statement that OP is a symbolic memory
303 operand of mode MODE. */
306 symbolic_memory_operand (op
, mode
)
308 enum machine_mode mode
;
310 if (GET_CODE (op
) == SUBREG
)
311 op
= SUBREG_REG (op
);
312 if (GET_CODE (op
) != MEM
)
315 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
316 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
319 /* Return truth value of whether OP is EQ or NE. */
324 enum machine_mode mode
;
326 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
329 /* OP is an integer register or a constant. */
332 arith32_operand (op
, mode
)
334 enum machine_mode mode
;
336 if (register_operand (op
, mode
))
338 return (CONSTANT_P (op
));
341 /* Return true if OP is an integer constant which is a power of 2. */
344 power2_operand (op
,mode
)
346 enum machine_mode mode
;
348 if (GET_CODE (op
) != CONST_INT
)
351 return exact_log2 (INTVAL (op
)) >= 0;
354 /* Return true if OP is an integer constant which is the complement of a
358 cmplpower2_operand (op
, mode
)
360 enum machine_mode mode
;
362 if (GET_CODE (op
) != CONST_INT
)
365 return exact_log2 (~ INTVAL (op
)) >= 0;
368 /* If VAL has only one bit set, return the index of that bit. Otherwise
377 for (i
= 0; val
!= 0; i
++, val
>>= 1)
389 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
390 The return value indicates how many consecutive non-zero bits exist
391 if this is a mask. This is the same as the next function, except that
392 it does not indicate what the start and stop bit positions are. */
398 register int start
, end
, i
;
401 for (i
= 0; val
!= 0; val
>>= 1, i
++)
411 /* Still looking for the first bit. */
415 /* We've seen the start of a bit sequence, and now a zero. There
416 must be more one bits, otherwise we would have exited the loop.
417 Therefore, it is not a mask. */
422 /* The bit string has ones from START to END bit positions only. */
423 return end
- start
+ 1;
426 /* If VAL is a mask, then return nonzero, with S set to the starting bit
427 position and E set to the ending bit position of the mask. The return
428 value indicates how many consecutive bits exist in the mask. This is
429 the same as the previous function, except that it also indicates the
430 start and end bit positions of the mask. */
437 register int start
, end
, i
;
441 for (i
= 0; val
!= 0; val
>>= 1, i
++)
452 /* Still looking for the first bit. */
456 /* We've seen the start of a bit sequence, and now a zero. There
457 must be more one bits, otherwise we would have exited the loop.
458 Therefor, it is not a mask. */
467 /* The bit string has ones from START to END bit positions only. */
470 return ((start
< 0) ? 0 : end
- start
+ 1);
473 /* Return the machine mode to use for a comparison. */
476 select_cc_mode (op
, x
)
480 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
485 /* X and Y are two things to compare using CODE. Emit the compare insn and
486 return the rtx for register 36 in the proper mode. */
489 gen_compare_reg (code
, x
, y
)
494 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
495 enum machine_mode mode
496 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
500 if (! arith_operand (x
, mode
))
501 x
= force_reg (SImode
, x
);
502 if (! arith_operand (y
, mode
))
503 y
= force_reg (SImode
, y
);
506 cc_reg
= gen_rtx (REG
, ccmode
, 36);
507 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
508 gen_rtx (COMPARE
, ccmode
, x
, y
)));
513 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
514 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
515 are 4. Indexed addresses are cost 6. */
517 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
520 i960_address_cost (x
)
524 /* Handled before calling here. */
525 if (GET_CODE (x
) == REG
)
528 if (GET_CODE (x
) == PLUS
)
530 rtx base
= XEXP (x
, 0);
531 rtx offset
= XEXP (x
, 1);
533 if (GET_CODE (base
) == SUBREG
)
534 base
= SUBREG_REG (base
);
535 if (GET_CODE (offset
) == SUBREG
)
536 offset
= SUBREG_REG (offset
);
538 if (GET_CODE (base
) == REG
)
540 if (GET_CODE (offset
) == REG
)
542 if (GET_CODE (offset
) == CONST_INT
)
544 if ((unsigned)INTVAL (offset
) < 2047)
548 if (CONSTANT_P (offset
))
551 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
554 /* This is an invalid address. The return value doesn't matter, but
555 for convenience we make this more expensive than anything else. */
558 if (GET_CODE (x
) == MULT
)
561 /* Symbol_refs and other unrecognized addresses are cost 4. */
565 /* Emit insns to move operands[1] into operands[0].
567 Return 1 if we have written out everything that needs to be done to
568 do the move. Otherwise, return 0 and the caller will emit the move
572 emit_move_sequence (operands
, mode
)
574 enum machine_mode mode
;
576 /* We can only store registers to memory. */
578 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
579 operands
[1] = force_reg (mode
, operands
[1]);
581 /* Storing multi-word values in unaligned hard registers to memory may
582 require a scratch since we have to store them a register at a time and
583 adding 4 to the memory address may not yield a valid insn. */
584 /* ??? We don't always need the scratch, but that would complicate things.
586 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
587 && GET_CODE (operands
[0]) == MEM
588 && GET_CODE (operands
[1]) == REG
589 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
590 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
592 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
594 gen_rtx (SET
, VOIDmode
,
595 operands
[0], operands
[1]),
596 gen_rtx (CLOBBER
, VOIDmode
,
597 gen_rtx (SCRATCH
, Pmode
)))));
604 /* Output assembler to move a double word value. */
607 i960_output_move_double (dst
, src
)
612 if (GET_CODE (dst
) == REG
613 && GET_CODE (src
) == REG
)
615 if ((REGNO (src
) & 1)
616 || (REGNO (dst
) & 1))
618 /* We normally copy the low-numbered register first. However, if
619 the second source register is the same as the first destination
620 register, we must copy in the opposite order. */
621 if (REGNO (src
) + 1 == REGNO (dst
))
622 return "mov %D1,%D0\n\tmov %1,%0";
624 return "mov %1,%0\n\tmov %D1,%D0";
629 else if (GET_CODE (dst
) == REG
630 && GET_CODE (src
) == CONST_INT
631 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
634 return "mov %1,%0\n\tmov 0,%D0";
638 else if (GET_CODE (dst
) == REG
639 && GET_CODE (src
) == MEM
)
643 /* One can optimize a few cases here, but you have to be
644 careful of clobbering registers used in the address and
648 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
649 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
650 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
651 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
657 else if (GET_CODE (dst
) == MEM
658 && GET_CODE (src
) == REG
)
662 /* This is handled by emit_move_sequence so we shouldn't get here. */
671 /* Output assembler to move a quad word value. */
674 i960_output_move_quad (dst
, src
)
679 if (GET_CODE (dst
) == REG
680 && GET_CODE (src
) == REG
)
682 if ((REGNO (src
) & 3)
683 || (REGNO (dst
) & 3))
685 /* We normally copy starting with the low numbered register.
686 However, if there is an overlap such that the first dest reg
687 is <= the last source reg but not < the first source reg, we
688 must copy in the opposite order. */
689 if (REGNO (dst
) <= REGNO (src
) + 3
690 && REGNO (dst
) >= REGNO (src
))
691 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
693 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
698 else if (GET_CODE (dst
) == REG
699 && GET_CODE (src
) == CONST_INT
700 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
703 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
707 else if (GET_CODE (dst
) == REG
708 && GET_CODE (src
) == MEM
)
712 /* One can optimize a few cases here, but you have to be
713 careful of clobbering registers used in the address and
717 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
718 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
719 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
720 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
721 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
722 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
728 else if (GET_CODE (dst
) == MEM
729 && GET_CODE (src
) == REG
)
733 /* This is handled by emit_move_sequence so we shouldn't get here. */
742 /* Emit insns to load a constant to non-floating point registers.
743 Uses several strategies to try to use as few insns as possible. */
746 i960_output_ldconst (dst
, src
)
747 register rtx dst
, src
;
750 register unsigned rsrc2
;
751 enum machine_mode mode
= GET_MODE (dst
);
754 operands
[0] = operands
[2] = dst
;
755 operands
[1] = operands
[3] = src
;
757 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
758 must be a ldconst insn. */
760 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
762 output_asm_insn ("ldconst %1,%0", operands
);
765 else if (mode
== XFmode
)
771 if (fp_literal_zero (src
, XFmode
))
774 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
775 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
777 output_asm_insn ("# ldconst %1,%0",operands
);
779 for (i
= 0; i
< 3; i
++)
781 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
782 operands
[1] = GEN_INT (value_long
[i
]);
783 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
789 else if (mode
== DFmode
)
793 if (fp_literal_zero (src
, DFmode
))
796 split_double (src
, &first
, &second
);
798 output_asm_insn ("# ldconst %1,%0",operands
);
800 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
802 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
804 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
805 operands
[1] = second
;
806 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
810 else if (mode
== SFmode
)
815 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
816 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
818 output_asm_insn ("# ldconst %1,%0",operands
);
819 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
820 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, value
);
821 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
825 else if (mode
== TImode
)
827 /* ??? This is currently not handled at all. */
830 /* Note: lowest order word goes in lowest numbered reg. */
831 rsrc1
= INTVAL (src
);
832 if (rsrc1
>= 0 && rsrc1
< 32)
835 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
836 /* Go pick up the low-order word. */
838 else if (mode
== DImode
)
840 rtx upperhalf
, lowerhalf
, xoperands
[2];
842 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
843 split_double (src
, &lowerhalf
, &upperhalf
);
848 /* Note: lowest order word goes in lowest numbered reg. */
849 /* Numbers from 0 to 31 can be handled with a single insn. */
850 rsrc1
= INTVAL (lowerhalf
);
851 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
854 /* Output the upper half with a recursive call. */
855 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
856 xoperands
[1] = upperhalf
;
857 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
859 /* The lower word is emitted as normally. */
863 rsrc1
= INTVAL (src
);
869 else if (mode
== HImode
)
878 /* ldconst 0..31,X -> mov 0..31,X */
881 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
886 /* ldconst 32..63,X -> add 31,nn,X */
889 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
891 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc1
- 31);
892 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
898 /* ldconst -1..-31 -> sub 0,0..31,X */
901 /* return 'sub -(%1),0,%0' */
902 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, - rsrc1
);
903 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
907 /* ldconst -32 -> not 31,X */
910 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, ~rsrc1
);
911 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
916 /* If const is a single bit. */
917 if (bitpos (rsrc1
) >= 0)
919 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, bitpos (rsrc1
));
920 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
924 /* If const is a bit string of less than 6 bits (1..31 shifted). */
929 if (bitstr (rsrc1
, &s
, &e
) < 6)
931 rsrc2
= ((unsigned int) rsrc1
) >> s
;
932 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, rsrc2
);
933 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, s
);
934 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
939 /* Unimplemented cases:
940 const is in range 0..31 but rotated around end of word:
941 ror 31,3,g0 -> ldconst 0xe0000003,g0
943 and any 2 instruction cases that might be worthwhile */
945 output_asm_insn ("ldconst %1,%0", operands
);
949 /* Determine if there is an opportunity for a bypass optimization.
950 Bypass succeeds on the 960K* if the destination of the previous
951 instruction is the second operand of the current instruction.
952 Bypass always succeeds on the C*.
954 Return 1 if the pattern should interchange the operands.
956 CMPBR_FLAG is true if this is for a compare-and-branch insn.
957 OP1 and OP2 are the two source operands of a 3 operand insn. */
960 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
961 register rtx insn
, op1
, op2
;
964 register rtx prev_insn
, prev_dest
;
969 /* Can't do this if op1 isn't a register. */
973 /* Can't do this for a compare-and-branch if both ops aren't regs. */
974 if (cmpbr_flag
&& ! REG_P (op2
))
977 prev_insn
= prev_real_insn (insn
);
979 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
980 && GET_CODE (PATTERN (prev_insn
)) == SET
)
982 prev_dest
= SET_DEST (PATTERN (prev_insn
));
983 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
984 || (GET_CODE (prev_dest
) == SUBREG
985 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
986 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
992 /* Output the code which declares the function name. This also handles
993 leaf routines, which have special requirements, and initializes some
997 i960_function_name_declare (file
, name
, fndecl
)
1006 /* Increment global return label. */
1010 /* Compute whether tail calls and leaf routine optimizations can be performed
1011 for this function. */
1013 if (TARGET_TAILCALL
)
1018 if (TARGET_LEAFPROC
)
1023 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1024 argblock, because argblock uses g14 implicitly. */
1026 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1032 /* See if caller passes in an address to return value. */
1034 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1040 /* Can not use tail calls or make this a leaf routine if there is a non
1043 if (get_frame_size () != 0)
1046 /* I don't understand this condition, and do not think that it is correct.
1047 Apparently this is just checking whether the frame pointer is used, and
1048 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1051 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1052 if (GET_CODE (insn
) == INSN
1053 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1059 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1062 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1063 if (GET_CODE (insn
) == CALL_INSN
)
1069 /* Can not be a leaf routine if any non-call clobbered registers are
1070 used in this function. */
1073 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1074 if (regs_ever_live
[i
]
1075 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1077 /* Global registers. */
1078 if (i
< 16 && i
> 7 && i
!= 13)
1080 /* Local registers. */
1085 /* Now choose a leaf return register, if we can find one, and if it is
1086 OK for this to be a leaf routine. */
1088 i960_leaf_ret_reg
= -1;
1090 if (optimize
&& leaf_proc_ok
)
1092 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1093 if (regs_ever_live
[i
] == 0)
1095 i960_leaf_ret_reg
= i
;
1096 regs_ever_live
[i
] = 1;
1101 /* Do this after choosing the leaf return register, so it will be listed
1102 if one was chosen. */
1104 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1105 fprintf (file
, "\t# Registers used: ");
1107 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1109 if (regs_ever_live
[i
])
1111 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1113 if (i
> 15 && j
== 0)
1115 fprintf (file
,"\n\t#\t\t ");
1121 fprintf (file
, "\n");
1123 if (i960_leaf_ret_reg
>= 0)
1125 /* Make it a leaf procedure. */
1127 if (TREE_PUBLIC (fndecl
))
1128 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1130 fprintf (file
, "\t.leafproc\t");
1131 assemble_name (file
, name
);
1132 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1133 ASM_OUTPUT_LABEL (file
, name
);
1134 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1135 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1136 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1138 if (TARGET_C_SERIES
)
1140 fprintf (file
, "\tlda 0,g14\n");
1141 i960_last_insn_type
= I_TYPE_MEM
;
1145 fprintf (file
, "\tmov 0,g14\n");
1146 i960_last_insn_type
= I_TYPE_REG
;
1151 ASM_OUTPUT_LABEL (file
, name
);
1152 i960_last_insn_type
= I_TYPE_CTRL
;
1156 /* Compute and return the frame size. */
1159 compute_frame_size (size
)
1163 int outgoing_args_size
= current_function_outgoing_args_size
;
1165 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1166 as size is concerned. */
1167 actual_fsize
= (size
+ 15) & -16;
1168 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1170 return actual_fsize
;
1173 /* Output code for the function prologue. */
1176 i960_function_prologue (file
, size
)
1180 register int i
, j
, nr
;
1183 int actual_fsize
, offset
;
1185 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1187 int regs
[FIRST_PSEUDO_REGISTER
];
1189 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1190 if (regs_ever_live
[i
]
1191 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1194 /* Count global registers that need saving. */
1201 epilogue_string
[0] = '\0';
1203 if (profile_flag
|| profile_block_flag
)
1205 /* When profiling, we may use registers 20 to 27 to save arguments, so
1206 they can't be used here for saving globals. J is the number of
1207 argument registers the mcount call will save. */
1208 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1211 for (i
= 20; i
<= j
+ 20; i
++)
1215 /* First look for local registers to save globals in. */
1216 for (i
= 0; i
< 16; i
++)
1221 /* Start at r4, not r3. */
1222 for (j
= 20; j
< 32; j
++)
1229 regs_ever_live
[j
] = 1;
1231 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1232 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1237 regs_ever_live
[j
+1] = 1;
1239 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1240 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1245 regs_ever_live
[j
+2] = 1;
1247 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1252 regs_ever_live
[j
+3] = 1;
1255 fprintf (file
, "\tmov%s %s,%s\n",
1258 (nr
== 2) ? "l" : ""),
1259 reg_names
[i
], reg_names
[j
]);
1260 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1263 (nr
== 2) ? "l" : ""),
1264 reg_names
[j
], reg_names
[i
]);
1265 strcat (epilogue_string
, tmpstr
);
1273 /* N_iregs is now the number of global registers that haven't been saved
1276 rsize
= (n_iregs
* 4);
1277 actual_fsize
= compute_frame_size (size
) + rsize
;
1279 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1280 size up to the nearest multiple of 16. I don't know whether this is
1281 necessary, or even desirable.
1283 The frame pointer must be aligned, but the call instruction takes care of
1284 that. If we leave the stack pointer unaligned, we may save a little on
1285 dynamic stack allocation. And we don't lose, at least according to the
1287 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1290 /* Allocate space for register save and locals. */
1291 if (actual_fsize
> 0)
1293 if (actual_fsize
< 32)
1294 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1296 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1299 /* Take hardware register save area created by the call instruction
1300 into account, but store them before the argument block area. */
1301 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1302 /* Save registers on stack if needed. */
1303 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1310 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1313 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1317 if (nr
== 3 && regs
[i
+3] == -1)
1320 fprintf (file
,"\tst%s %s,%d(fp)\n",
1323 (nr
== 2) ? "l" : ""),
1324 reg_names
[i
], offset
);
1325 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1328 (nr
== 2) ? "l" : ""),
1329 offset
, reg_names
[i
]);
1330 strcat (epilogue_string
, tmpstr
);
1336 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1339 fprintf (file
, "\t#Prologue stats:\n");
1340 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1343 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1345 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1347 fprintf (file
, "\t#End Prologue#\n");
1350 /* Output code for the function profiler. */
1353 output_function_profiler (file
, labelno
)
1357 /* The last used parameter register. */
1359 int i
, j
, increment
;
1360 int varargs_stdarg_function
1361 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1363 /* Figure out the last used parameter register. The proper thing to do
1364 is to walk incoming args of the function. A function might have live
1365 parameter registers even if it has no incoming args. Note that we
1366 don't have to save parameter registers g8 to g11 because they are
1369 /* See also output_function_prologue, which tries to use local registers
1370 for preserved call-saved global registers. */
1372 for (last_parm_reg
= 7;
1373 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1377 /* Save parameter registers in regs r4 (20) to r11 (27). */
1379 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1381 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1383 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1385 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1390 fprintf (file
, "\tmov%s g%d,r%d\n",
1391 (increment
== 4 ? "q" : increment
== 3 ? "t"
1392 : increment
== 2 ? "l": ""), i
, j
);
1395 /* If this function uses the arg pointer, then save it in r3 and then
1398 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1399 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1401 /* Load location address into g0 and call mcount. */
1403 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1405 /* If this function uses the arg pointer, restore it. */
1407 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1408 fprintf (file
, "\tmov r3,g14\n");
1410 /* Restore parameter registers. */
1412 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1414 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1416 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1418 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1423 fprintf (file
, "\tmov%s r%d,g%d\n",
1424 (increment
== 4 ? "q" : increment
== 3 ? "t"
1425 : increment
== 2 ? "l": ""), j
, i
);
1429 /* Output code for the function epilogue. */
1432 i960_function_epilogue (file
, size
)
1436 if (i960_leaf_ret_reg
>= 0)
1438 fprintf (file
, "LR%d: ret\n", ret_label
);
1442 if (*epilogue_string
== 0)
1446 /* Emit a return insn, but only if control can fall through to here. */
1448 tmp
= get_last_insn ();
1451 if (GET_CODE (tmp
) == BARRIER
)
1453 if (GET_CODE (tmp
) == CODE_LABEL
)
1455 if (GET_CODE (tmp
) == JUMP_INSN
)
1457 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1461 if (GET_CODE (tmp
) == NOTE
)
1463 tmp
= PREV_INSN (tmp
);
1468 fprintf (file
, "LR%d: ret\n", ret_label
);
1472 fprintf (file
, "LR%d:\n", ret_label
);
1474 fprintf (file
, "\t#EPILOGUE#\n");
1476 /* Output the string created by the prologue which will restore all
1477 registers saved by the prologue. */
1479 if (epilogue_string
[0] != '\0')
1480 fprintf (file
, "%s", epilogue_string
);
1482 /* Must clear g14 on return if this function set it.
1483 Only varargs/stdarg functions modify g14. */
1485 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1486 fprintf (file
, "\tmov 0,g14\n");
1488 fprintf (file
, "\tret\n");
1489 fprintf (file
, "\t#End Epilogue#\n");
1492 /* Output code for a call insn. */
1495 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1496 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1498 int argsize
= INTVAL (argsize_rtx
);
1499 rtx nexti
= next_real_insn (insn
);
1501 int varargs_stdarg_function
1502 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1504 operands
[0] = target
;
1505 operands
[1] = arg_pointer
;
1507 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1508 output_asm_insn ("mov g14,r3", operands
);
1511 output_asm_insn ("lda %a1,g14", operands
);
1512 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1513 output_asm_insn ("mov 0,g14", operands
);
1515 /* The code used to assume that calls to SYMBOL_REFs could not be more
1516 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1517 feature is now implemented by relaxing in the GNU linker. It can convert
1518 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1520 /* Nexti could be zero if the called routine is volatile. */
1521 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1522 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1524 /* Delete following return insn. */
1525 if (nexti
&& no_labels_between_p (insn
, nexti
))
1526 delete_insn (nexti
);
1527 output_asm_insn ("bx %0", operands
);
1528 return "# notreached";
1531 output_asm_insn ("callx %0", operands
);
1533 /* If the caller sets g14 to the address of the argblock, then the caller
1534 must clear it after the return. */
1536 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1537 output_asm_insn ("mov r3,g14", operands
);
1538 else if (argsize
> 48)
1539 output_asm_insn ("mov 0,g14", operands
);
1544 /* Output code for a return insn. */
1547 i960_output_ret_insn (insn
)
1550 static char lbuf
[20];
1552 if (*epilogue_string
!= 0)
1554 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1557 sprintf (lbuf
, "b LR%d", ret_label
);
1561 /* Must clear g14 on return if this function set it.
1562 Only varargs/stdarg functions modify g14. */
1564 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1565 output_asm_insn ("mov 0,g14", 0);
1567 if (i960_leaf_ret_reg
>= 0)
1569 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1576 /* Return a character string representing the branch prediction
1577 opcode to be tacked on an instruction. This must at least
1578 return a null string. */
1581 i960_br_predict_opcode (lab_ref
, insn
)
1584 if (TARGET_BRANCH_PREDICT
)
1586 unsigned long label_uid
;
1588 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1589 label_uid
= INSN_UID (lab_ref
);
1590 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1591 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1595 /* If not optimizing, then the insn_addresses array will not be
1596 valid. In this case, always return ".t" since most branches
1597 are taken. If optimizing, return .t for backward branches
1598 and .f for forward branches. */
1600 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1609 /* Print the operand represented by rtx X formatted by code CODE. */
1612 i960_print_operand (file
, x
, code
)
1617 enum rtx_code rtxcode
= GET_CODE (x
);
1624 /* Second reg of a double or quad. */
1625 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1629 /* Third reg of a quad. */
1630 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1634 /* Fourth reg of a quad. */
1635 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1639 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1647 else if (rtxcode
== MEM
)
1649 output_address (XEXP (x
, 0));
1652 else if (rtxcode
== CONST_INT
)
1654 HOST_WIDE_INT val
= INTVAL (x
);
1657 if (val
> 9999 || val
< -999)
1658 fprintf (file
, "0x%x", val
);
1660 fprintf (file
, "%d", val
);
1663 else if (rtxcode
== CONST_DOUBLE
)
1668 if (x
== CONST0_RTX (GET_MODE (x
)))
1670 fprintf (file
, "0f0.0");
1673 else if (x
== CONST1_RTX (GET_MODE (x
)))
1675 fprintf (file
, "0f1.0");
1679 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1680 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1681 fprintf (file
, "0f%s", dstr
);
1688 /* Branch or jump, depending on assembler. */
1689 if (TARGET_ASM_COMPAT
)
1696 /* Sign of condition. */
1697 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1698 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1700 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1701 || (rtxcode
== GE
) || (rtxcode
== LE
))
1708 /* Inverted condition. */
1709 rtxcode
= reverse_condition (rtxcode
);
1713 /* Inverted condition w/ reversed operands. */
1714 rtxcode
= reverse_condition (rtxcode
);
1718 /* Reversed operand condition. */
1719 rtxcode
= swap_condition (rtxcode
);
1723 /* Normal condition. */
1725 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1726 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1727 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1728 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1729 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1730 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1731 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1732 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1733 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1734 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1739 output_addr_const (file
, x
);
1749 /* Print a memory address as an operand to reference that memory location.
1751 This is exactly the same as legitimate_address_p, except that it the prints
1752 addresses instead of recognizing them. */
1755 i960_print_operand_addr (file
, addr
)
1767 if (GET_CODE (addr
) == REG
)
1769 else if (CONSTANT_P (addr
))
1771 else if (GET_CODE (addr
) == PLUS
)
1775 op0
= XEXP (addr
, 0);
1776 op1
= XEXP (addr
, 1);
1778 if (GET_CODE (op0
) == REG
)
1781 if (GET_CODE (op1
) == REG
)
1783 else if (CONSTANT_P (op1
))
1788 else if (GET_CODE (op0
) == PLUS
)
1790 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1792 ireg
= XEXP (XEXP (op0
, 0), 0);
1793 scale
= XEXP (XEXP (op0
, 0), 1);
1794 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1796 breg
= XEXP (op0
, 1);
1802 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1804 breg
= XEXP (op0
, 0);
1805 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1807 ireg
= XEXP (op0
, 1);
1816 else if (GET_CODE (op0
) == MULT
)
1818 ireg
= XEXP (op0
, 0);
1819 scale
= XEXP (op0
, 1);
1820 if (GET_CODE (op1
) == REG
)
1822 else if (CONSTANT_P (op1
))
1830 else if (GET_CODE (addr
) == MULT
)
1832 ireg
= XEXP (addr
, 0);
1833 scale
= XEXP (addr
, 1);
1839 output_addr_const (file
, offset
);
1841 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1843 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1846 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1847 that is a valid memory address for an instruction.
1848 The MODE argument is the machine mode for the MEM expression
1849 that wants to use this address.
1851 On 80960, legitimate addresses are:
1853 disp (12 or 32 bit) ld foo,r0
1854 base + index ld (g0)[g1*1],r0
1855 base + displ ld 0xf00(g0),r0
1856 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1857 index*scale + base ld (g0)[g1*4],r0
1858 index*scale + displ ld 0xf00[g1*4],r0
1859 index*scale ld [g1*4],r0
1860 index + base + displ ld 0xf00(g0)[g1*1],r0
1862 In each case, scale can be 1, 2, 4, 8, or 16. */
1864 /* This is exactly the same as i960_print_operand_addr, except that
1865 it recognizes addresses instead of printing them.
1867 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1868 convert common non-canonical forms to canonical form so that they will
1871 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1872 where a register is valid. */
1874 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1875 ((GET_CODE (X) == REG \
1876 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1877 || (GET_CODE (X) == SUBREG \
1878 && GET_CODE (SUBREG_REG (X)) == REG \
1879 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1880 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1882 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1883 ((GET_CODE (X) == REG \
1884 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1885 || (GET_CODE (X) == SUBREG \
1886 && GET_CODE (SUBREG_REG (X)) == REG \
1887 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1888 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1891 legitimate_address_p (mode
, addr
, strict
)
1892 enum machine_mode mode
;
1896 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1898 else if (CONSTANT_P (addr
))
1900 else if (GET_CODE (addr
) == PLUS
)
1904 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1907 op0
= XEXP (addr
, 0);
1908 op1
= XEXP (addr
, 1);
1910 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1912 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1914 else if (CONSTANT_P (op1
))
1919 else if (GET_CODE (op0
) == PLUS
)
1921 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1923 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1924 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1927 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1928 && CONSTANT_P (op1
))
1933 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1935 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1936 && CONSTANT_P (op1
))
1944 else if (GET_CODE (op0
) == MULT
)
1946 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1947 && SCALE_TERM_P (XEXP (op0
, 1))))
1950 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1952 else if (CONSTANT_P (op1
))
1960 else if (GET_CODE (addr
) == MULT
)
1962 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1965 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1966 && SCALE_TERM_P (XEXP (addr
, 1)));
1972 /* Try machine-dependent ways of modifying an illegitimate address
1973 to be legitimate. If we find one, return the new, valid address.
1974 This macro is used in only one place: `memory_address' in explow.c.
1976 This converts some non-canonical addresses to canonical form so they
1977 can be recognized. */
1980 legitimize_address (x
, oldx
, mode
)
1983 enum machine_mode mode
;
1985 if (GET_CODE (x
) == SYMBOL_REF
)
1988 x
= copy_to_reg (x
);
1991 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1994 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1995 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1996 created by virtual register instantiation, register elimination, and
1997 similar optimizations. */
1998 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1999 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2000 x
= gen_rtx (PLUS
, Pmode
,
2001 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2002 XEXP (XEXP (x
, 1), 1));
2004 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2005 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2006 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2007 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2008 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2009 && CONSTANT_P (XEXP (x
, 1)))
2011 rtx constant
, other
;
2013 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2015 constant
= XEXP (x
, 1);
2016 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2018 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2020 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2021 other
= XEXP (x
, 1);
2027 x
= gen_rtx (PLUS
, Pmode
,
2028 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2029 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2030 plus_constant (other
, INTVAL (constant
)));
2037 /* Return the most stringent alignment that we are willing to consider
2038 objects of size SIZE and known alignment ALIGN as having. */
2041 i960_alignment (size
, align
)
2047 if (! TARGET_STRICT_ALIGN
)
2048 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2050 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2059 /* Modes for condition codes. */
2061 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2063 /* Modes for single-word (and smaller) quantities. */
2066 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2067 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2069 /* Modes for double-word (and smaller) quantities. */
2072 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2074 /* Modes for quad-word quantities. */
2075 #define T_MODES (~C_MODES)
2077 /* Modes for single-float quantities. */
2078 #define SF_MODES ((1 << (int) SFmode))
2080 /* Modes for double-float quantities. */
2081 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2083 /* Modes for quad-float quantities. */
2084 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2086 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
2087 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2088 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2089 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2090 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2092 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
2095 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2096 advantage of machine specific facts, such as knowing that the frame pointer
2097 is always 16 byte aligned. */
2100 i960_expr_alignment (x
, size
)
2109 switch (GET_CODE(x
))
2114 if ((align
& 0xf) == 0)
2116 else if ((align
& 0x7) == 0)
2118 else if ((align
& 0x3) == 0)
2120 else if ((align
& 0x1) == 0)
2127 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2128 i960_expr_alignment (XEXP (x
, 1), size
));
2132 /* If this is a valid program, objects are guaranteed to be
2133 correctly aligned for whatever size the reference actually is. */
2134 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2138 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2143 align
= i960_expr_alignment (XEXP (x
, 0));
2145 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2147 align
= align
<< INTVAL (XEXP (x
, 1));
2148 align
= MIN (align
, 16);
2153 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2154 i960_expr_alignment (XEXP (x
, 1), size
));
2156 align
= MIN (align
, 16);
2163 /* Return true if it is possible to reference both BASE and OFFSET, which
2164 have alignment at least as great as 4 byte, as if they had alignment valid
2165 for an object of size SIZE. */
2168 i960_improve_align (base
, offset
, size
)
2175 /* We have at least a word reference to the object, so we know it has to
2176 be aligned at least to 4 bytes. */
2178 i
= MIN (i960_expr_alignment (base
, 4),
2179 i960_expr_alignment (offset
, 4));
2183 /* We know the size of the request. If strict align is not enabled, we
2184 can guess that the alignment is OK for the requested size. */
2186 if (! TARGET_STRICT_ALIGN
)
2187 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2193 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2194 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2197 i960_si_ti (base
, offset
)
2201 return i960_improve_align (base
, offset
, 16);
2204 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2205 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2208 i960_si_di (base
, offset
)
2212 return i960_improve_align (base
, offset
, 8);
2215 /* Return raw values of size and alignment (in words) for the data
2216 type being accessed. These values will be rounded by the caller. */
2219 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2220 enum machine_mode mode
;
2227 /* Use formal alignment requirements of type being passed, except make
2228 it at least a word. If we don't have a type, this is a library call,
2229 and the parm has to be of scalar type. In this case, consider its
2230 formal alignment requirement to be its size in words. */
2232 if (mode
== BLKmode
)
2233 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2234 else if (mode
== VOIDmode
)
2236 /* End of parm list. */
2237 assert (type
!= 0 && TYPE_MODE (type
) == VOIDmode
);
2241 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2245 /* ??? This is a hack to properly correct the alignment of XFmode
2246 values without affecting anything else. */
2252 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2253 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2261 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2262 Any arg that is bigger than 4 words is placed on the stack and all
2263 subsequent arguments are placed on the stack.
2265 Additionally, parameters with an alignment requirement stronger than
2266 a word must be aligned appropriately. Note that this means that a
2267 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2268 passed in an odd/even register pair. */
2270 /* Update CUM to advance past an argument described by MODE and TYPE. */
2273 i960_function_arg_advance (cum
, mode
, type
, named
)
2274 CUMULATIVE_ARGS
*cum
;
2275 enum machine_mode mode
;
2281 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2283 if (size
> 4 || cum
->ca_nstackparms
!= 0
2284 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2285 || MUST_PASS_IN_STACK (mode
, type
))
2287 /* Indicate that all the registers are in use, even if all are not,
2288 so va_start will compute the right value. */
2289 cum
->ca_nregparms
= NPARM_REGS
;
2290 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2293 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2296 /* Return the register that the argument described by MODE and TYPE is
2297 passed in, or else return 0 if it is passed on the stack. */
2300 i960_function_arg (cum
, mode
, type
, named
)
2301 CUMULATIVE_ARGS
*cum
;
2302 enum machine_mode mode
;
2309 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2311 if (size
> 4 || cum
->ca_nstackparms
!= 0
2312 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2313 || MUST_PASS_IN_STACK (mode
, type
))
2315 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2320 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2321 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2327 /* Floating-point support. */
2330 i960_output_long_double (file
, value
)
2332 REAL_VALUE_TYPE value
;
2337 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2338 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2341 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2342 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2343 fprintf (file
, "\t.word\t0x0\n");
2347 i960_output_double (file
, value
)
2349 REAL_VALUE_TYPE value
;
2354 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2355 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2357 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2358 value_long
[0], dstr
, value_long
[1]);
2362 i960_output_float (file
, value
)
2364 REAL_VALUE_TYPE value
;
2369 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2370 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2372 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2375 /* Return the number of bits that an object of size N bytes is aligned to. */
2378 i960_object_bytes_bitalign (n
)
2382 else if (n
> 4) n
= 64;
2383 else if (n
> 2) n
= 32;
2384 else if (n
> 1) n
= 16;
2390 /* Compute the alignment for an aggregate type TSIZE.
2391 Alignment is MAX (greatest member alignment,
2392 MIN (pragma align, structure size alignment)). */
2395 i960_round_align (align
, tsize
)
2401 if (TREE_CODE (tsize
) != INTEGER_CST
)
2404 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2406 /* Handle #pragma align. */
2407 if (new_align
> i960_maxbitalignment
)
2408 new_align
= i960_maxbitalignment
;
2410 if (align
< new_align
)
2416 /* Do any needed setup for a varargs function. For the i960, we must
2417 create a register parameter block if one doesn't exist, and then copy
2418 all register parameters to memory. */
2421 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2422 CUMULATIVE_ARGS
*cum
;
2423 enum machine_mode mode
;
2428 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2429 int first_reg
= cum
->ca_nregparms
;
2431 /* Copy only unnamed register arguments to memory. If there are
2432 any stack parms, there are no unnamed arguments in registers, and
2433 an argument block was already allocated by the caller.
2434 Remember that any arg bigger than 4 words is passed on the stack as
2435 are all subsequent args.
2437 If there are no stack arguments but there are exactly NPARM_REGS
2438 registers, either there were no extra arguments or the caller
2439 allocated an argument block. */
2441 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2443 rtx label
= gen_label_rtx ();
2446 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2447 and we need to allocate a chunk to save the registers (if any
2448 arguments were passed on the stack the caller would allocate the
2449 48 bytes as well). We must allocate all 48 bytes (12*4) because
2450 va_start assumes it. */
2451 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2452 emit_jump_insn (gen_bne (label
));
2453 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2454 stack_pointer_rtx
));
2455 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2456 memory_address (SImode
,
2457 plus_constant (stack_pointer_rtx
,
2461 /* ??? Note that we unnecessarily store one extra register for stdarg
2462 fns. We could optimize this, but it's kept as for now. */
2463 regblock
= gen_rtx (MEM
, BLKmode
,
2464 plus_constant (arg_pointer_rtx
,
2466 move_block_from_reg (first_reg
, regblock
,
2467 NPARM_REGS
- first_reg
,
2468 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2472 /* Calculate the final size of the reg parm stack space for the current
2473 function, based on how many bytes would be allocated on the stack. */
2476 i960_final_reg_parm_stack_space (const_size
, var_size
)
2480 if (var_size
|| const_size
> 48)
2486 /* Calculate the size of the reg parm stack space. This is a bit complicated
2490 i960_reg_parm_stack_space (fndecl
)
2493 /* In this case, we are called from emit_library_call, and we don't need
2494 to pretend we have more space for parameters than what's apparent. */
2498 /* In this case, we are called from locate_and_pad_parms when we're
2499 not IN_REGS, so we have an arg block. */
2500 if (fndecl
!= current_function_decl
)
2503 /* Otherwise, we have an arg block if the current function has more than
2504 48 bytes of parameters. */
2505 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2511 /* Return the register class of a scratch register needed to copy IN into
2512 or out of a register in CLASS in MODE. If it can be done directly,
2513 NO_REGS is returned. */
2516 secondary_reload_class (class, mode
, in
)
2517 enum reg_class
class;
2518 enum machine_mode mode
;
2523 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2524 regno
= true_regnum (in
);
2526 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2527 LOCAL_OR_GLOBAL_REGS into anything. */
2528 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2529 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2532 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2533 if (class == FP_REGS
2534 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2535 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2538 return LOCAL_OR_GLOBAL_REGS
;
2541 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2542 function unit it executed on. */
2544 /* ??? This would make more sense as an attribute. */
2547 i960_scan_opcode (p
)
2559 /* Ret is not actually of type REG, but it won't matter, because no
2560 insn will ever follow it. */
2563 i960_last_insn_type
= I_TYPE_REG
;
2567 if (p
[1] == 'x' || p
[3] == 'x')
2568 i960_last_insn_type
= I_TYPE_MEM
;
2569 i960_last_insn_type
= I_TYPE_CTRL
;
2574 i960_last_insn_type
= I_TYPE_CTRL
;
2581 i960_last_insn_type
= I_TYPE_MEM
;
2583 i960_last_insn_type
= I_TYPE_CTRL
;
2585 else if (p
[1] == 'm')
2588 i960_last_insn_type
= I_TYPE_REG
;
2589 else if (p
[4] == 'b' || p
[4] == 'j')
2590 i960_last_insn_type
= I_TYPE_CTRL
;
2592 i960_last_insn_type
= I_TYPE_REG
;
2595 i960_last_insn_type
= I_TYPE_REG
;
2599 i960_last_insn_type
= I_TYPE_MEM
;
2604 i960_last_insn_type
= I_TYPE_MEM
;
2606 i960_last_insn_type
= I_TYPE_REG
;