1 /* Definitions of target machine for GNU compiler, for Intel 80960
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Note that some other tm.h files may include this one and then override
24 many of the definitions that relate to assembler syntax. */
26 /* Names to predefine in the preprocessor for this target machine. */
27 #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960"
29 /* Name to predefine in the preprocessor for processor variations. */
30 #define CPP_SPEC "%{mic*:-D__i960\
31 %{mka:-D__i960KA}%{mkb:-D__i960KB}\
32 %{msa:-D__i960SA}%{msb:-D__i960SB}\
34 %{mca:-D__i960CA}%{mcc:-D__i960CC}\
36 %{mka:-D__i960KA__ -D__i960_KA__}\
37 %{mkb:-D__i960KB__ -D__i960_KB__}\
38 %{msa:-D__i960SA__ -D__i960_SA__}\
39 %{msb:-D__i960SB__ -D__i960_SB__}\
40 %{mmc:-D__i960MC__ -D__i960_MC__}\
41 %{mca:-D__i960CA__ -D__i960_CA__}\
42 %{mcc:-D__i960CC__ -D__i960_CC__}\
43 %{mcf:-D__i960CF__ -D__i960_CF__}\
44 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
45 %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"
47 /* -mic* options make characters signed by default. */
48 #define SIGNED_CHAR_SPEC \
49 (DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \
50 : "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}")
52 /* Specs for the compiler, to handle processor variations. */
54 "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\
55 %{mbout:%{g*:-gstabs}}\
56 %{mcoff:%{g*:-gcoff}}\
57 %{!mbout:%{!mcoff:%{g*:-gstabs}}}"
59 /* Specs for the assembler, to handle processor variations.
60 For compatibility with Intel's gnu960 tool chain, pass -A options to
63 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
64 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
65 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
66 %{mlink-relax:-link-relax}"
68 /* Specs for the linker, to handle processor variations.
69 For compatibility with Intel's gnu960 tool chain, pass -F and -A options
72 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
73 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
74 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
75 %{mbout:-Fbout}%{mcoff:-Fcoff}\
76 %{mlink-relax:-relax}"
78 /* Specs for the libraries to link with, to handle processor variations.
79 Compatible with Intel's gnu960 tool chain. */
80 #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
81 %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
83 /* Omit frame pointer at -O2. Inline functions at -O3. */
84 #define OPTIMIZATION_OPTIONS(LEVEL) \
88 flag_omit_frame_pointer = 1; \
89 target_flags |= TARGET_FLAG_LEAFPROC; \
90 target_flags |= TARGET_FLAG_TAILCALL; \
94 /* Print subsidiary information on the compiler version in use. */
95 #define TARGET_VERSION fprintf (stderr," (intel 80960)");
97 /* Generate DBX debugging information. */
98 #define DBX_DEBUGGING_INFO
100 /* Generate SDB style debugging information. */
101 #define SDB_DEBUGGING_INFO
103 /* Generate DBX_DEBUGGING_INFO by default. */
104 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
106 /* Redefine this to print in hex like iC960. */
107 #define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A)
109 /* Run-time compilation parameters selecting different hardware subsets. */
111 /* 960 architecture with floating-point. */
112 #define TARGET_FLAG_NUMERICS 0x01
113 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
115 /* 960 architecture with memory management. */
116 /* ??? Not used currently. */
117 #define TARGET_FLAG_PROTECTED 0x02
118 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
120 /* The following three are mainly used to provide a little sanity checking
121 against the -mARCH flags given. */
123 /* Nonzero if we should generate code for the KA and similar processors.
124 No FPU, no microcode instructions. */
125 #define TARGET_FLAG_K_SERIES 0x04
126 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
128 /* Nonzero if we should generate code for the MC processor.
129 Not really different from KB for our purposes. */
130 #define TARGET_FLAG_MC 0x08
131 #define TARGET_MC (target_flags & TARGET_FLAG_MC)
133 /* Nonzero if we should generate code for the CA processor.
134 Enables different optimization strategies. */
135 #define TARGET_FLAG_C_SERIES 0x10
136 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
138 /* Nonzero if we should generate leaf-procedures when we find them.
139 You may not want to do this because leaf-proc entries are
140 slower when not entered via BAL - this would be true when
141 a linker not supporting the optimization is used. */
142 #define TARGET_FLAG_LEAFPROC 0x20
143 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
145 /* Nonzero if we should perform tail-call optimizations when we find them.
146 You may not want to do this because the detection of cases where
147 this is not valid is not totally complete. */
148 #define TARGET_FLAG_TAILCALL 0x40
149 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
151 /* Nonzero if use of a complex addressing mode is a win on this implementation.
152 Complex addressing modes are probably not worthwhile on the K-series,
153 but they definitely are on the C-series. */
154 #define TARGET_FLAG_COMPLEX_ADDR 0x80
155 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
157 /* Align code to 8 byte boundaries for faster fetching. */
158 #define TARGET_FLAG_CODE_ALIGN 0x100
159 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
161 /* Append branch prediction suffixes to branch opcodes. */
162 /* ??? Not used currently. */
163 #define TARGET_FLAG_BRANCH_PREDICT 0x200
164 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
166 /* Forces prototype and return promotions. */
167 /* ??? This does not work. */
168 #define TARGET_FLAG_CLEAN_LINKAGE 0x400
169 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
171 /* For compatibility with iC960 v3.0. */
172 #define TARGET_FLAG_IC_COMPAT3_0 0x800
173 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
175 /* For compatibility with iC960 v2.0. */
176 #define TARGET_FLAG_IC_COMPAT2_0 0x1000
177 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
179 /* If no unaligned accesses are to be permitted. */
180 #define TARGET_FLAG_STRICT_ALIGN 0x2000
181 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
183 /* For compatibility with iC960 assembler. */
184 #define TARGET_FLAG_ASM_COMPAT 0x4000
185 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
187 /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
188 alignment rules. Also, turns on STRICT_ALIGNMENT. */
189 #define TARGET_FLAG_OLD_ALIGN 0x8000
190 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
192 extern int target_flags
;
194 /* Macro to define tables used to set the flags.
195 This is a list in braces of pairs in braces,
196 each pair being { "NAME", VALUE }
197 where VALUE is the bits to set or minus the bits to clear.
198 An empty string NAME is used to identify the default VALUE. */
200 /* ??? Not all ten of these architecture variations actually exist, but I
201 am not sure which are real and which aren't. */
203 #define TARGET_SWITCHES \
204 { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
205 {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
206 TARGET_FLAG_COMPLEX_ADDR)},\
207 /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
208 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
209 {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
210 {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
211 TARGET_FLAG_COMPLEX_ADDR)},\
212 /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
213 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
214 {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
215 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
216 {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
217 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
218 /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
219 TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
220 {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
221 TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
222 TARGET_FLAG_CODE_ALIGN)}, */ \
223 {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
224 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
225 {"numerics", (TARGET_FLAG_NUMERICS)}, \
226 {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
227 {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
228 {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
229 {"tail-call",TARGET_FLAG_TAILCALL}, \
230 {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
231 {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
232 {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
233 {"code-align",TARGET_FLAG_CODE_ALIGN}, \
234 {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
235 {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
236 {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
237 {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
238 {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
239 {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
240 {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
241 {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
242 {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
243 {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
244 {"old-align", TARGET_FLAG_OLD_ALIGN}, \
245 {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \
247 {"no-link-relax", 0}, \
248 { "", TARGET_DEFAULT}}
250 /* Override conflicting target switch options.
251 Doesn't actually detect if more than one -mARCH option is given, but
252 does handle the case of two blatantly conflicting -mARCH options. */
253 #define OVERRIDE_OPTIONS \
255 if (TARGET_K_SERIES && TARGET_C_SERIES) \
257 warning ("conflicting architectures defined - using C series", 0); \
258 target_flags &= ~TARGET_FLAG_K_SERIES; \
260 if (TARGET_K_SERIES && TARGET_MC) \
262 warning ("conflicting architectures defined - using K series", 0); \
263 target_flags &= ~TARGET_FLAG_MC; \
265 if (TARGET_C_SERIES && TARGET_MC) \
267 warning ("conflicting architectures defined - using C series", 0);\
268 target_flags &= ~TARGET_FLAG_MC; \
270 if (TARGET_IC_COMPAT3_0) \
272 flag_short_enums = 1; \
273 flag_signed_char = 1; \
274 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
275 if (TARGET_IC_COMPAT2_0) \
277 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
278 target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
281 if (TARGET_IC_COMPAT2_0) \
283 flag_signed_char = 1; \
284 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
286 i960_initialize (); \
289 /* Don't enable anything by default. The user is expected to supply a -mARCH
290 option. If none is given, then -mkb is added by CC1_SPEC. */
291 #define TARGET_DEFAULT 0
293 /* Target machine storage layout. */
295 /* Define this if most significant bit is lowest numbered
296 in instructions that operate on numbered bit-fields. */
297 #define BITS_BIG_ENDIAN 0
299 /* Define this if most significant byte of a word is the lowest numbered.
300 The i960 case be either big endian or little endian. We only support
301 little endian, which is the most common. */
302 #define BYTES_BIG_ENDIAN 0
304 /* Define this if most significant word of a multiword number is lowest
306 #define WORDS_BIG_ENDIAN 0
308 /* Number of bits in an addressable storage unit. */
309 #define BITS_PER_UNIT 8
311 /* Bitfields cannot cross word boundaries. */
312 #define BITFIELD_NBYTES_LIMITED 1
314 /* Width in bits of a "word", which is the contents of a machine register.
315 Note that this is not necessarily the width of data type `int';
316 if using 16-bit ints on a 68000, this would still be 32.
317 But on a machine with 16-bit registers, this would be 16. */
318 #define BITS_PER_WORD 32
320 /* Width of a word, in units (bytes). */
321 #define UNITS_PER_WORD 4
323 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
324 #define POINTER_SIZE 32
326 /* Width in bits of a long double. Identical to double for now. */
327 #define LONG_DOUBLE_TYPE_SIZE 64
329 /* Allocation boundary (in *bits*) for storing pointers in memory. */
330 #define POINTER_BOUNDARY 32
332 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
333 #define PARM_BOUNDARY 32
335 /* Boundary (in *bits*) on which stack pointer should be aligned. */
336 #define STACK_BOUNDARY 128
338 /* Allocation boundary (in *bits*) for the code of a function. */
339 #define FUNCTION_BOUNDARY 128
341 /* Alignment of field after `int : 0' in a structure. */
342 #define EMPTY_FIELD_BOUNDARY 32
344 /* This makes zero-length anonymous fields lay the next field
345 at a word boundary. It also makes the whole struct have
346 at least word alignment if there are any bitfields at all. */
347 #define PCC_BITFIELD_TYPE_MATTERS 1
349 /* Every structure's size must be a multiple of this. */
350 #define STRUCTURE_SIZE_BOUNDARY 8
352 /* No data type wants to be aligned rounder than this.
353 Extended precision floats gets 4-word alignment. */
354 #define BIGGEST_ALIGNMENT 128
356 /* Define this if move instructions will actually fail to work
357 when given unaligned data.
358 80960 will work even with unaligned data, but it is slow. */
359 #define STRICT_ALIGNMENT TARGET_OLD_ALIGN
361 /* Specify alignment for string literals (which might be higher than the
362 base type's minimal alignment requirement. This allows strings to be
363 aligned on word boundaries, and optimizes calls to the str* and mem*
364 library functions. */
365 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
366 (i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
367 ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
370 /* Macros to determine size of aggregates (structures and unions
371 in C). Normally, these may be defined to simply return the maximum
372 alignment and simple rounded-up size, but on some machines (like
373 the i960), the total size of a structure is based on a non-trivial
376 #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
377 ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
378 ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \
379 : MAX ((COMPUTED), (SPECIFIED)))
381 #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \
382 ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
383 ? (tree) i960_round_size (SIZE) \
384 : round_up ((SIZE), (ALIGN)))
386 /* Standard register usage. */
388 /* Number of actual hardware registers.
389 The hardware registers are assigned numbers for the compiler
390 from 0 to just below FIRST_PSEUDO_REGISTER.
391 All registers that the compiler knows about must be given numbers,
392 even those that are not normally considered general registers.
394 Registers 0-15 are the global registers (g0-g15).
395 Registers 16-31 are the local registers (r0-r15).
396 Register 32-35 are the fp registers (fp0-fp3).
397 Register 36 is the condition code register.
398 Register 37 is unused. */
400 #define FIRST_PSEUDO_REGISTER 38
402 /* 1 for registers that have pervasive standard uses and are not available
403 for the register allocator. On 80960, this includes the frame pointer
404 (g15), the previous FP (r0), the stack pointer (r1), the return
405 instruction pointer (r2), and the argument pointer (g14). */
406 #define FIXED_REGISTERS \
407 {0, 0, 0, 0, 0, 0, 0, 0, \
408 0, 0, 0, 0, 0, 0, 1, 1, \
409 1, 1, 1, 0, 0, 0, 0, 0, \
410 0, 0, 0, 0, 0, 0, 0, 0, \
413 /* 1 for registers not available across function calls.
414 These must include the FIXED_REGISTERS and also any
415 registers that can be used without being saved.
416 The latter must include the registers where values are returned
417 and the register where structure-value addresses are passed.
418 Aside from that, you can include as many other registers as you like. */
420 /* On the 80960, note that:
421 g0..g3 are used for return values,
422 g0..g7 may always be used for parameters,
423 g8..g11 may be used for parameters, but are preserved if they aren't,
424 g12 is always preserved, but otherwise unused,
425 g13 is the struct return ptr if used, or temp, but may be trashed,
426 g14 is the leaf return ptr or the arg block ptr otherwise zero,
427 must be reset to zero before returning if it was used,
428 g15 is the frame pointer,
429 r0 is the previous FP,
430 r1 is the stack pointer,
431 r2 is the return instruction pointer,
432 r3-r15 are always available,
433 fp0..fp3 are never available. */
434 #define CALL_USED_REGISTERS \
435 {1, 1, 1, 1, 1, 1, 1, 1, \
436 0, 0, 0, 0, 0, 1, 1, 1, \
437 1, 1, 1, 0, 0, 0, 0, 0, \
438 0, 0, 0, 0, 0, 0, 0, 0, \
441 /* If no fp unit, make all of the fp registers fixed so that they can't
443 #define CONDITIONAL_REGISTER_USAGE \
444 if (! TARGET_NUMERICS) { \
445 fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
448 /* Return number of consecutive hard regs needed starting at reg REGNO
449 to hold something of mode MODE.
450 This is ordinarily the length in words of a value of mode MODE
451 but can be less for certain modes in special long registers.
453 On 80960, ordinary registers hold 32 bits worth, but can be ganged
454 together to hold double or extended precision floating point numbers,
455 and the floating point registers hold any size floating point number */
456 #define HARD_REGNO_NREGS(REGNO, MODE) \
458 ? (((MODE) == VOIDmode) \
459 ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
460 : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
462 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
463 On 80960, the cpu registers can hold any mode but the float registers
464 can only hold SFmode, DFmode, or TFmode. */
465 extern unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
466 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
467 ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0)
469 /* Value is 1 if it is a good idea to tie two pseudo registers
470 when one has mode MODE1 and one has mode MODE2.
471 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
472 for any hard reg, then this must be 0 for correct output. */
474 #define MODES_TIEABLE_P(MODE1, MODE2) \
475 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
477 /* Specify the registers used for certain standard purposes.
478 The values of these macros are register numbers. */
480 /* 80960 pc isn't overloaded on a register that the compiler knows about. */
481 /* #define PC_REGNUM */
483 /* Register to use for pushing function arguments. */
484 #define STACK_POINTER_REGNUM 17
486 /* Actual top-of-stack address is same as
487 the contents of the stack pointer register. */
488 #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
490 /* Base register for access to local variables of the function. */
491 #define FRAME_POINTER_REGNUM 15
493 /* Value should be nonzero if functions must have frame pointers.
494 Zero means the frame pointer need not be set up (and parms
495 may be accessed via the stack pointer) in functions that seem suitable.
496 This is computed in `reload', in reload1.c. */
497 #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
499 /* C statement to store the difference between the frame pointer
500 and the stack pointer values immediately after the function prologue. */
502 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
503 do { (VAR) = compute_frame_size (get_frame_size ()); } while (0)
505 /* Base register for access to arguments of the function. */
506 #define ARG_POINTER_REGNUM 14
508 /* Register in which static-chain is passed to a function.
509 On i960, we use r3. */
510 #define STATIC_CHAIN_REGNUM 19
512 /* Functions which return large structures get the address
513 to place the wanted value at in g13. */
515 #define STRUCT_VALUE_REGNUM 13
517 /* The order in which to allocate registers. */
519 #define REG_ALLOC_ORDER \
520 { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
521 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
522 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
523 11, 12, /* g11, g12 */ \
524 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
525 /* We can't actually allocate these. */ \
526 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
528 /* Define the classes of registers for register constraints in the
529 machine description. Also define ranges of constants.
531 One of the classes must always be named ALL_REGS and include all hard regs.
532 If there is more than one class, another class must be named NO_REGS
533 and contain no registers.
535 The name GENERAL_REGS must be the name of a class (or an alias for
536 another name such as ALL_REGS). This is the class of registers
537 that is allowed by "g" or "r" in a register constraint.
538 Also, registers outside this class are allocated only when
539 instructions express preferences for them.
541 The classes must be numbered in nondecreasing order; that is,
542 a larger-numbered class must never be contained completely
543 in a smaller-numbered class.
545 For any two classes, it is very desirable that there be another
546 class that represents their union. */
548 /* The 80960 has four kinds of registers, global, local, floating point,
549 and condition code. The cc register is never allocated, so no class
550 needs to be defined for it. */
552 enum reg_class
{ NO_REGS
, GLOBAL_REGS
, LOCAL_REGS
, LOCAL_OR_GLOBAL_REGS
,
553 FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
555 /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
557 #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
559 #define N_REG_CLASSES (int) LIM_REG_CLASSES
561 /* Give names of register classes as strings for dump file. */
563 #define REG_CLASS_NAMES \
564 { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
565 "FP_REGS", "ALL_REGS" }
567 /* Define which registers fit in which classes.
568 This is an initializer for a vector of HARD_REG_SET
569 of length N_REG_CLASSES. */
571 #define REG_CLASS_CONTENTS \
572 { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
574 /* The same information, inverted:
575 Return the class number of the smallest class containing
576 reg number REGNO. This could be a conditional expression
577 or could index an array. */
579 #define REGNO_REG_CLASS(REGNO) \
580 ((REGNO) < 16 ? GLOBAL_REGS \
581 : (REGNO) < 32 ? LOCAL_REGS \
582 : (REGNO) < 36 ? FP_REGS \
585 /* The class value for index registers, and the one for base regs.
586 There is currently no difference between base and index registers on the
587 i960, but this distinction may one day be useful. */
588 #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
589 #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
591 /* Get reg_class from a letter such as appears in the machine description.
592 'f' is a floating point register (fp0..fp3)
593 'l' is a local register (r0-r15)
594 'b' is a global register (g0-g15)
595 'd' is any local or global register
596 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
597 /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
598 the same thing, since 'r' may include the fp registers. */
599 #define REG_CLASS_FROM_LETTER(C) \
600 (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
601 (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
603 /* The letters I, J, K, L and M in a register constraint string
604 can be used to stand for particular ranges of immediate operands.
605 This macro defines what the ranges are.
606 C is the letter, and VALUE is a constant value.
607 Return 1 if VALUE is in the range specified by C.
610 'I' is used for literal values 0..31
614 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
615 ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
616 : (C) == 'J' ? ((VALUE) == 0) \
617 : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \
620 /* Similar, but for floating constants, and defining letters G and H.
621 Here VALUE is the CONST_DOUBLE rtx itself.
622 For the 80960, G is 0.0 and H is 1.0. */
624 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
625 ((TARGET_NUMERICS) && \
626 (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \
627 || (VALUE) == CONST0_RTX (SFmode))) \
628 || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \
629 || (VALUE) == CONST1_RTX (SFmode)))))
631 /* Given an rtx X being reloaded into a reg required to be
632 in class CLASS, return the class of reg to actually use.
633 In general this is just CLASS; but on some machines
634 in some cases it is preferable to use a more restrictive class. */
636 /* On 960, can't load constant into floating-point reg except
639 Any hard reg is ok as a src operand of a reload insn. */
641 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
642 (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
644 : ((CLASS) == FP_REGS && CONSTANT_P (X) \
645 && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
646 && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
648 : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
650 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
651 secondary_reload_class (CLASS, MODE, IN)
653 /* Return the maximum number of consecutive registers
654 needed to represent mode MODE in a register of class CLASS. */
655 /* On 80960, this is the size of MODE in words,
656 except in the FP regs, where a single reg is always enough. */
657 #define CLASS_MAX_NREGS(CLASS, MODE) \
658 ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
660 /* Stack layout; function entry, exit and calling. */
662 /* Define this if pushing a word on the stack
663 makes the stack pointer a smaller address. */
664 /* #define STACK_GROWS_DOWNWARD */
666 /* Define this if the nominal address of the stack frame
667 is at the high-address end of the local variables;
668 that is, each additional local variable allocated
669 goes at a more negative offset in the frame. */
670 /* #define FRAME_GROWS_DOWNWARD */
672 /* Offset within stack frame to start allocating local variables at.
673 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
674 first local allocated. Otherwise, it is the offset to the BEGINNING
675 of the first local allocated.
677 The i960 has a 64 byte register save area, plus possibly some extra
678 bytes allocated for varargs functions. */
679 #define STARTING_FRAME_OFFSET 64
681 /* If we generate an insn to push BYTES bytes,
682 this says how many the stack pointer really advances by.
683 On 80960, don't define this because there are no push insns. */
684 /* #define PUSH_ROUNDING(BYTES) BYTES */
686 /* Offset of first parameter from the argument pointer register value. */
687 #define FIRST_PARM_OFFSET(FNDECL) 0
689 /* When a parameter is passed in a register, no stack space is
690 allocated for it. However, when args are passed in the
691 stack, space is allocated for every register parameter. */
692 #define MAYBE_REG_PARM_STACK_SPACE 48
693 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
694 i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
695 #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
696 #define OUTGOING_REG_PARM_STACK_SPACE
698 /* Keep the stack pointer constant throughout the function. */
699 #define ACCUMULATE_OUTGOING_ARGS
701 /* Value is 1 if returning from a function call automatically
702 pops the arguments described by the number-of-args field in the call.
703 FUNTYPE is the data type of the function (as a tree),
704 or for a library call it is an identifier node for the subroutine name. */
706 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
708 /* Define how to find the value returned by a library function
709 assuming the value has mode MODE. */
711 #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
713 /* 1 if N is a possible register number for a function value
714 as seen by the caller.
715 On 80960, returns are in g0..g3 */
717 #define FUNCTION_VALUE_REGNO_P(N) ((N) < 4)
719 /* 1 if N is a possible register number for function argument passing.
720 On 80960, parameters are passed in g0..g11 */
722 #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
724 /* Perform any needed actions needed for a function that is receiving a
725 variable number of arguments.
729 MODE and TYPE are the mode and type of the current parameter.
731 PRETEND_SIZE is a variable that should be set to the amount of stack
732 that must be pushed by the prolog to pretend that our caller pushed
735 Normally, this macro will push all remaining incoming registers on the
736 stack and set PRETEND_SIZE to the length of the registers pushed. */
738 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
739 i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
741 /* Define a data type for recording info about an argument list
742 during the scan of that argument list. This data type should
743 hold all necessary information about the function itself
744 and about the args processed so far, enough to enable macros
745 such as FUNCTION_ARG to determine where the next arg should go.
747 On 80960, this is two integers, which count the number of register
748 parameters and the number of stack parameters seen so far. */
750 struct cum_args
{ int ca_nregparms
; int ca_nstackparms
; };
752 #define CUMULATIVE_ARGS struct cum_args
754 /* Define the number of registers that can hold parameters.
755 This macro is used only in macro definitions below and/or i960.c. */
756 #define NPARM_REGS 12
758 /* Define how to round to the next parameter boundary.
759 This macro is used only in macro definitions below and/or i960.c. */
760 #define ROUND(X, MULTIPLE_OF) \
761 ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
763 /* Initialize a variable CUM of type CUMULATIVE_ARGS
764 for a call to a function whose data type is FNTYPE.
765 For a library call, FNTYPE is 0.
767 On 80960, the offset always starts at 0; the first parm reg is g0. */
769 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
770 ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
772 /* Update the data in CUM to advance over an argument
773 of mode MODE and data type TYPE.
774 CUM should be advanced to align with the data type accessed and
775 also the size of that data type in # of regs.
776 (TYPE is null for libcalls where that information may not be available.) */
778 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
779 i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
781 /* Indicate the alignment boundary for an argument of the specified mode and
783 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
785 ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
787 : TYPE_ALIGN (TYPE)) \
788 : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
790 : GET_MODE_ALIGNMENT (MODE)))
792 /* Determine where to put an argument to a function.
793 Value is zero to push the argument on the stack,
794 or a hard register in which to store the argument.
796 MODE is the argument's machine mode.
797 TYPE is the data type of the argument (as a tree).
798 This is null for libcalls where that information may
800 CUM is a variable of type CUMULATIVE_ARGS which gives info about
801 the preceding args and about the function being called.
802 NAMED is nonzero if this argument is a named parameter
803 (otherwise it is an extra parameter matching an ellipsis). */
805 extern struct rtx_def
*i960_function_arg ();
806 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
807 i960_function_arg(&CUM, MODE, TYPE, NAMED)
809 /* Define how to find the value returned by a function.
810 VALTYPE is the data type of the value (as a tree).
811 If the precise function being called is known, FUNC is its FUNCTION_DECL;
812 otherwise, FUNC is 0. */
814 #define FUNCTION_VALUE(TYPE, FUNC) \
815 gen_rtx (REG, TYPE_MODE (TYPE), 0)
817 /* Force objects larger than 16 bytes to be returned in memory, since we
818 only have 4 registers available for return values. */
820 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 16)
822 /* For an arg passed partly in registers and partly in memory,
823 this is the number of registers used.
824 This never happens on 80960. */
826 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
828 /* Output the label for a function definition.
829 This handles leaf functions and a few other things for the i960. */
831 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
832 i960_function_name_declare (FILE, NAME, DECL)
834 /* This macro generates the assembly code for function entry.
835 FILE is a stdio stream to output the code to.
836 SIZE is an int: how many units of temporary storage to allocate.
837 Refer to the array `regs_ever_live' to determine which registers
838 to save; `regs_ever_live[I]' is nonzero if register number I
839 is ever used in the function. This macro is responsible for
840 knowing which registers should not be saved even if used. */
842 #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
844 /* Output assembler code to FILE to increment profiler label # LABELNO
845 for profiling a function entry. */
847 #define FUNCTION_PROFILER(FILE, LABELNO) \
848 fprintf (FILE, "\tlda LP%d,g0\n\tbal mcount\n", (LABELNO))
850 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
851 the stack pointer does not matter. The value is tested only in
852 functions that have frame pointers.
853 No definition is equivalent to always zero. */
855 #define EXIT_IGNORE_STACK 1
857 /* This macro generates the assembly code for function exit,
858 on machines that need it. If FUNCTION_EPILOGUE is not defined
859 then individual return instructions are generated for each
860 return statement. Args are same as for FUNCTION_PROLOGUE.
862 The function epilogue should not depend on the current stack pointer!
863 It should use the frame pointer only. This is mandatory because
864 of alloca; we also take advantage of it to omit stack adjustments
867 #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
869 /* Addressing modes, and classification of registers for them. */
871 /* #define HAVE_POST_INCREMENT */
872 /* #define HAVE_POST_DECREMENT */
874 /* #define HAVE_PRE_DECREMENT */
875 /* #define HAVE_PRE_INCREMENT */
877 /* Macros to check register numbers against specific register classes. */
879 /* These assume that REGNO is a hard or pseudo reg number.
880 They give nonzero only if REGNO is a hard reg of the suitable class
881 or a pseudo reg currently allocated to a suitable hard reg.
882 Since they use reg_renumber, they are safe only once reg_renumber
883 has been allocated, which happens in local-alloc.c. */
885 #define REGNO_OK_FOR_INDEX_P(REGNO) \
886 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
887 #define REGNO_OK_FOR_BASE_P(REGNO) \
888 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
889 #define REGNO_OK_FOR_FP_P(REGNO) \
890 ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
892 /* Now macros that check whether X is a register and also,
893 strictly, whether it is in a specified class.
895 These macros are specific to the 960, and may be used only
896 in code for printing assembler insns and in conditions for
897 define_optimization. */
899 /* 1 if X is an fp register. */
901 #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
903 /* Maximum number of registers that can appear in a valid memory address. */
904 #define MAX_REGS_PER_ADDRESS 2
906 #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
908 /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
909 is a legitimate general operand.
910 It is given that X satisfies CONSTANT_P.
912 Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */
914 #define LEGITIMATE_CONSTANT_P(X) \
915 ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode))
917 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
918 and check its validity for a certain class.
919 We have two alternate definitions for each of them.
920 The usual definition accepts all pseudo regs; the other rejects
921 them unless they have been allocated suitable hard regs.
922 The symbol REG_OK_STRICT causes the latter definition to be used.
924 Most source files want to accept pseudo regs in the hope that
925 they will get allocated to the class that the insn wants them to be in.
926 Source files for reload pass need to be strict.
927 After reload, it makes no difference, since pseudo regs have
928 been eliminated by then. */
930 #ifndef REG_OK_STRICT
932 /* Nonzero if X is a hard reg that can be used as an index
933 or if it is a pseudo reg. */
934 #define REG_OK_FOR_INDEX_P(X) \
935 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
936 /* Nonzero if X is a hard reg that can be used as a base reg
937 or if it is a pseudo reg. */
938 #define REG_OK_FOR_BASE_P(X) \
939 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
941 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
942 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
946 /* Nonzero if X is a hard reg that can be used as an index. */
947 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
948 /* Nonzero if X is a hard reg that can be used as a base reg. */
949 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
953 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
954 that is a valid memory address for an instruction.
955 The MODE argument is the machine mode for the MEM expression
956 that wants to use this address.
958 On 80960, legitimate addresses are:
960 disp (12 or 32 bit) ld foo,r0
961 base + index ld (g0)[g1*1],r0
962 base + displ ld 0xf00(g0),r0
963 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
964 index*scale + base ld (g0)[g1*4],r0
965 index*scale + displ ld 0xf00[g1*4],r0
966 index*scale ld [g1*4],r0
967 index + base + displ ld 0xf00(g0)[g1*1],r0
969 In each case, scale can be 1, 2, 4, 8, or 16. */
971 /* Returns 1 if the scale factor of an index term is valid. */
972 #define SCALE_TERM_P(X) \
973 (GET_CODE (X) == CONST_INT \
974 && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
975 || INTVAL(X) == 8 || INTVAL (X) == 16))
979 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
980 { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
982 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
983 { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
986 /* Try machine-dependent ways of modifying an illegitimate address
987 to be legitimate. If we find one, return the new, valid address.
988 This macro is used in only one place: `memory_address' in explow.c.
990 OLDX is the address as it was before break_out_memory_refs was called.
991 In some cases it is useful to look at this to decide what needs to be done.
993 MODE and WIN are passed so that this macro can use
994 GO_IF_LEGITIMATE_ADDRESS.
996 It is always safe for this macro to do nothing. It exists to recognize
997 opportunities to optimize the output. */
999 /* On 80960, convert non-canonical addresses to canonical form. */
1001 extern struct rtx_def
*legitimize_address ();
1002 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1003 { rtx orig_x = (X); \
1004 (X) = legitimize_address (X, OLDX, MODE); \
1005 if ((X) != orig_x && memory_address_p (MODE, X)) \
1008 /* Go to LABEL if ADDR (a legitimate address expression)
1009 has an effect that depends on the machine mode it is used for.
1010 On the 960 this is never true. */
1012 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1014 /* Specify the machine mode that this machine uses
1015 for the index in the tablejump instruction. */
1016 #define CASE_VECTOR_MODE SImode
1018 /* Define this if the tablejump instruction expects the table
1019 to contain offsets from the address of the table.
1020 Do not define this if the table should contain absolute addresses. */
1021 /* #define CASE_VECTOR_PC_RELATIVE */
1023 /* Specify the tree operation to be used to convert reals to integers. */
1024 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1026 /* This is the kind of divide that is easiest to do in the general case. */
1027 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1029 /* Define this as 1 if `char' should by default be signed; else as 0. */
1030 #define DEFAULT_SIGNED_CHAR 0
1032 /* Allow and ignore #sccs directives. */
1033 #define SCCS_DIRECTIVE
1035 /* Max number of bytes we can move from memory to memory
1036 in one reasonably fast instruction. */
1039 /* Define if normal loads of shorter-than-word items from memory clears
1040 the rest of the bigs in the register. */
1041 #define BYTE_LOADS_ZERO_EXTEND
1043 /* Nonzero if access to memory by bytes is no faster than for words.
1044 Defining this results in worse code on the i960. */
1046 #define SLOW_BYTE_ACCESS 0
1048 /* We assume that the store-condition-codes instructions store 0 for false
1049 and some other value for true. This is the value stored for true. */
1051 #define STORE_FLAG_VALUE 1
1053 /* Define if shifts truncate the shift count
1054 which implies one can omit a sign-extension or zero-extension
1055 of a shift count. */
1056 #define SHIFT_COUNT_TRUNCATED
1058 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1059 is done just by pretending it is already truncated. */
1060 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1062 /* Specify the machine mode that pointers have.
1063 After generation of rtl, the compiler makes no further distinction
1064 between pointers and any other objects of this machine mode. */
1065 #define Pmode SImode
1067 /* Specify the widest mode that BLKmode objects can be promoted to */
1068 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1070 /* These global variables are used to pass information between
1071 cc setter and cc user at insn emit time. */
1073 extern struct rtx_def
*i960_compare_op0
, *i960_compare_op1
;
1075 /* Define the function that build the compare insn for scc and bcc. */
1077 extern struct rtx_def
*gen_compare_reg ();
1079 /* Add any extra modes needed to represent the condition code.
1081 Also, signed and unsigned comparisons are distinguished, as
1082 are operations which are compatible with chkbit insns. */
1083 #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1085 /* Define the names for the modes specified above. */
1086 #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1088 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1089 return the mode to be used for the comparison. For floating-point, CCFPmode
1090 should be used. CC_NOOVmode should be used when the first operand is a
1091 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1093 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1095 /* A function address in a call instruction is a byte address
1096 (for indexing purposes) so give the MEM rtx a byte's mode. */
1097 #define FUNCTION_MODE SImode
1099 /* Define this if addresses of constant functions
1100 shouldn't be put through pseudo regs where they can be cse'd.
1101 Desirable on machines where ordinary constants are expensive
1102 but a CALL with constant address is cheap. */
1103 #define NO_FUNCTION_CSE
1105 /* Use memcpy, etc. instead of bcopy. */
1108 #define TARGET_MEM_FUNCTIONS 1
1111 /* Compute the cost of computing a constant rtl expression RTX
1112 whose rtx-code is CODE. The body of this macro is a portion
1113 of a switch statement. If the code is computed here,
1114 return it with a return statement. Otherwise, break from the switch. */
1116 /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1117 that can be non-ldconst operands in rare cases are cost 1. Other constants
1118 have higher costs. */
1120 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1122 if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1123 || power2_operand (RTX, VOIDmode)) \
1125 else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1130 return (TARGET_FLAG_C_SERIES ? 6 : 8); \
1131 case CONST_DOUBLE: \
1132 if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1133 || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1137 /* The i960 offers addressing modes which are "as cheap as a register".
1138 See i960.c (or gcc.texinfo) for details. */
1140 #define ADDRESS_COST(RTX) \
1141 (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1143 /* Control the assembler format that we output. */
1145 /* Output at beginning of assembler file. */
1147 #define ASM_FILE_START(file)
1149 /* Output to assembler file text saying following lines
1150 may contain character constants, extra white space, comments, etc. */
1152 #define ASM_APP_ON ""
1154 /* Output to assembler file text saying following lines
1155 no longer contain unusual constructs. */
1157 #define ASM_APP_OFF ""
1159 /* Output before read-only data. */
1161 #define TEXT_SECTION_ASM_OP ".text"
1163 /* Output before writable data. */
1165 #define DATA_SECTION_ASM_OP ".data"
1167 /* How to refer to registers in assembler output.
1168 This sequence is indexed by compiler's hard-register-number (see above). */
1170 #define REGISTER_NAMES { \
1171 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1172 "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1173 "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1174 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1175 "fp0","fp1","fp2", "fp3", "cc", "fake" }
1177 /* How to renumber registers for dbx and gdb.
1178 In the 960 encoding, g0..g15 are registers 16..31. */
1180 #define DBX_REGISTER_NUMBER(REGNO) \
1181 (((REGNO) < 16) ? (REGNO) + 16 \
1182 : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1184 /* Don't emit dbx records longer than this. This is an arbitrary value. */
1185 #define DBX_CONTIN_LENGTH 1500
1187 /* This is how to output a note to DBX telling it the line number
1188 to which the following sequence of instructions corresponds. */
1190 #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1191 { if (write_symbols == SDB_DEBUG) { \
1192 fprintf ((FILE), "\t.ln %d\n", \
1193 (sdb_begin_function_line \
1194 ? (LINE) - sdb_begin_function_line : 1)); \
1195 } else if (write_symbols == DBX_DEBUG) { \
1196 fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1199 /* This is how to output the definition of a user-level label named NAME,
1200 such as the label on a static function or variable NAME. */
1202 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1203 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1205 /* This is how to output a command to make the user-level label named NAME
1206 defined for reference from other files. */
1208 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1209 { fputs ("\t.globl ", FILE); \
1210 assemble_name (FILE, NAME); \
1211 fputs ("\n", FILE); }
1213 /* This is how to output a reference to a user-level label named NAME.
1214 `assemble_name' uses this. */
1216 #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME)
1218 /* This is how to output an internal numbered label where
1219 PREFIX is the class of label and NUM is the number within the class. */
1221 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1222 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1224 /* This is how to store into the string LABEL
1225 the symbol_ref name of an internal numbered label where
1226 PREFIX is the class of label and NUM is the number within the class.
1227 This is suitable for output with `assemble_name'. */
1229 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1230 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1232 /* This is how to output an assembler line defining a `double' constant. */
1234 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1236 /* This is how to output an assembler line defining a `float' constant. */
1238 #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1240 /* This is how to output an assembler line defining an `int' constant. */
1242 #define ASM_OUTPUT_INT(FILE,VALUE) \
1243 ( fprintf (FILE, "\t.word "), \
1244 output_addr_const (FILE, (VALUE)), \
1245 fprintf (FILE, "\n"))
1247 /* Likewise for `char' and `short' constants. */
1249 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1250 ( fprintf (FILE, "\t.short "), \
1251 output_addr_const (FILE, (VALUE)), \
1252 fprintf (FILE, "\n"))
1254 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1255 ( fprintf (FILE, "\t.byte "), \
1256 output_addr_const (FILE, (VALUE)), \
1257 fprintf (FILE, "\n"))
1259 /* This is how to output an assembler line for a numeric constant byte. */
1261 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1262 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1264 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1265 fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1267 /* This is how to output an insn to pop a register from the stack.
1268 It need not be very fast code. */
1270 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1271 fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1273 /* This is how to output an element of a case-vector that is absolute. */
1275 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1276 fprintf (FILE, "\t.word L%d\n", VALUE)
1278 /* This is how to output an element of a case-vector that is relative. */
1280 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1281 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1283 /* This is how to output an assembler line that says to advance the
1284 location counter to a multiple of 2**LOG bytes. */
1286 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1287 fprintf (FILE, "\t.align %d\n", (LOG))
1289 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1290 fprintf (FILE, "\t.space %d\n", (SIZE))
1292 /* This says how to output an assembler line
1293 to define a global common symbol. */
1295 /* For common objects, output unpadded size... gld960 & lnk960 both
1296 have code to align each common object at link time. Also, if size
1297 is 0, treat this as a declaration, not a definition - i.e.,
1298 do nothing at all. */
1300 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1301 { if ((SIZE) != 0) \
1303 fputs (".globl ", (FILE)), \
1304 assemble_name ((FILE), (NAME)), \
1305 fputs ("\n.comm ", (FILE)), \
1306 assemble_name ((FILE), (NAME)), \
1307 fprintf ((FILE), ",%d\n", (ROUNDED)); \
1311 /* This says how to output an assembler line to define a local common symbol.
1312 Output unpadded size, with request to linker to align as requested.
1313 0 size should not be possible here. */
1315 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1316 ( fputs (".bss\t", (FILE)), \
1317 assemble_name ((FILE), (NAME)), \
1318 fprintf ((FILE), ",%d,%d\n", (SIZE), \
1320 : ((ALIGN) <= 16 ? 1 \
1321 : ((ALIGN) <= 32 ? 2 \
1322 : ((ALIGN <= 64 ? 3 : 4)))))))
1324 /* Output text for an #ident directive. */
1325 #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1327 /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1329 #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1330 { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); }
1332 /* Store in OUTPUT a string (made with alloca) containing
1333 an assembler-name for a local static variable named NAME.
1334 LABELNO is an integer which is different for each call. */
1336 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1337 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1338 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1340 /* Define the parentheses used to group arithmetic operations
1341 in assembler code. */
1343 #define ASM_OPEN_PAREN "("
1344 #define ASM_CLOSE_PAREN ")"
1346 /* Define results of standard character escape sequences. */
1347 #define TARGET_BELL 007
1348 #define TARGET_BS 010
1349 #define TARGET_TAB 011
1350 #define TARGET_NEWLINE 012
1351 #define TARGET_VT 013
1352 #define TARGET_FF 014
1353 #define TARGET_CR 015
1355 /* Output assembler code to FILE to initialize this source file's
1356 basic block profiling info, if that has not already been done. */
1358 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1359 { fprintf (FILE, "\tld LPBX0,g12\n"); \
1360 fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1361 fprintf (FILE, "\tlda LPBX0,g12\n"); \
1362 fprintf (FILE, "\tcall ___bb_init_func\n"); \
1363 fprintf (FILE, "LPY%d:\n",LABELNO); }
1365 /* Output assembler code to FILE to increment the entry-count for
1366 the BLOCKNO'th basic block in this source file. */
1368 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1369 { int blockn = (BLOCKNO); \
1370 fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1371 fprintf (FILE, "\taddo g12,1,g12\n"); \
1372 fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1374 /* Print operand X (an rtx) in assembler syntax to file FILE.
1375 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1376 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1378 #define PRINT_OPERAND(FILE, X, CODE) \
1379 i960_print_operand (FILE, X, CODE);
1381 /* Print a memory address as an operand to reference that memory location. */
1383 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1384 i960_print_operand_addr (FILE, ADDR)
1386 /* Output assembler code for a block containing the constant parts
1387 of a trampoline, leaving space for the variable parts. */
1389 /* On the i960, the trampoline contains three instructions:
1390 ldconst _function, r4
1391 ldconst static addr, r3
1394 #define TRAMPOLINE_TEMPLATE(FILE) \
1396 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \
1397 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1398 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \
1399 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1400 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \
1403 /* Length in units of the trampoline for entering a nested function. */
1405 #define TRAMPOLINE_SIZE 20
1407 /* Emit RTL insns to initialize the variable parts of a trampoline.
1408 FNADDR is an RTX for the address of the function's pure code.
1409 CXT is an RTX for the static chain value for the function. */
1411 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1413 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1415 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1420 /* Promote char and short arguments to ints, when want compatibility with
1421 the iC960 compilers. */
1423 /* ??? In order for this to work, all users would need to be changed
1424 to test the value of the macro at run time. */
1425 #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1426 /* ??? This does not exist. */
1427 #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1430 /* Instruction type definitions. Used to alternate instructions types for
1431 better performance on the C series chips. */
1433 enum insn_types
{ I_TYPE_REG
, I_TYPE_MEM
, I_TYPE_CTRL
};
1435 /* Holds the insn type of the last insn output to the assembly file. */
1437 extern enum insn_types i960_last_insn_type
;
1439 /* Parse opcodes, and set the insn last insn type based on them. */
1441 #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1443 /* Table listing what rtl codes each predicate in i960.c will accept. */
1445 #define PREDICATE_CODES \
1446 {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1447 LABEL_REF, SUBREG, REG, MEM}}, \
1448 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1449 {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1450 {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1451 {"literal", {CONST_INT}}, \
1452 {"fp_literal_one", {CONST_DOUBLE}}, \
1453 {"fp_literal_double", {CONST_DOUBLE}}, \
1454 {"fp_literal", {CONST_DOUBLE}}, \
1455 {"signed_literal", {CONST_INT}}, \
1456 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1457 {"eq_or_neq", {EQ, NE}}, \
1458 {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1459 CONST_DOUBLE, CONST}}, \
1460 {"power2_operand", {CONST_INT}},
1462 /* Define functions in i960.c and used in insn-output.c. */
1464 extern char *i960_output_ldconst ();
1465 extern char *i960_output_call_insn ();
1466 extern char *i960_output_ret_insn ();