1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
47 #include "diagnostic-core.h"
48 #include "sched-int.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
54 #include "hash-table.h"
55 #include "langhooks.h"
56 #include "pointer-set.h"
58 #include "basic-block.h"
59 #include "tree-ssa-alias.h"
60 #include "internal-fn.h"
61 #include "gimple-fold.h"
63 #include "gimple-expr.h"
72 #include "tm-constrs.h"
73 #include "sel-sched.h"
78 /* This is used for communication between ASM_OUTPUT_LABEL and
79 ASM_OUTPUT_LABELREF. */
80 int ia64_asm_output_label
= 0;
82 /* Register names for ia64_expand_prologue. */
83 static const char * const ia64_reg_numbers
[96] =
84 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
85 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
86 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
87 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
88 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
89 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
90 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
91 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
92 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
93 "r104","r105","r106","r107","r108","r109","r110","r111",
94 "r112","r113","r114","r115","r116","r117","r118","r119",
95 "r120","r121","r122","r123","r124","r125","r126","r127"};
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_input_reg_names
[8] =
99 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
101 /* ??? These strings could be shared with REGISTER_NAMES. */
102 static const char * const ia64_local_reg_names
[80] =
103 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
104 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
105 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
106 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
107 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
108 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
109 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
110 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
111 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
112 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
114 /* ??? These strings could be shared with REGISTER_NAMES. */
115 static const char * const ia64_output_reg_names
[8] =
116 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
118 /* Variables which are this size or smaller are put in the sdata/sbss
121 unsigned int ia64_section_threshold
;
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
136 number_of_ia64_frame_regs
139 /* Structure to be filled in by ia64_compute_frame_size with register
140 save masks and offsets for the current function. */
142 struct ia64_frame_info
144 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
145 the caller's scratch area. */
146 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
147 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
148 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
149 HARD_REG_SET mask
; /* mask of saved registers. */
150 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
151 registers or long-term scratches. */
152 int n_spilled
; /* number of spilled registers. */
153 int r
[number_of_ia64_frame_regs
]; /* Frame related registers. */
154 int n_input_regs
; /* number of input registers used. */
155 int n_local_regs
; /* number of local registers used. */
156 int n_output_regs
; /* number of output registers used. */
157 int n_rotate_regs
; /* number of rotating registers used. */
159 char need_regstk
; /* true if a .regstk directive needed. */
160 char initialized
; /* true if the data is finalized. */
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info
;
165 /* The actual registers that are emitted. */
166 static int emitted_frame_related_regs
[number_of_ia64_frame_regs
];
168 static int ia64_first_cycle_multipass_dfa_lookahead (void);
169 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
170 static void ia64_init_dfa_pre_cycle_insn (void);
171 static rtx
ia64_dfa_pre_cycle_insn (void);
172 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
173 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx
);
174 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
175 static void ia64_h_i_d_extended (void);
176 static void * ia64_alloc_sched_context (void);
177 static void ia64_init_sched_context (void *, bool);
178 static void ia64_set_sched_context (void *);
179 static void ia64_clear_sched_context (void *);
180 static void ia64_free_sched_context (void *);
181 static int ia64_mode_to_int (enum machine_mode
);
182 static void ia64_set_sched_flags (spec_info_t
);
183 static ds_t
ia64_get_insn_spec_ds (rtx
);
184 static ds_t
ia64_get_insn_checked_ds (rtx
);
185 static bool ia64_skip_rtx_p (const_rtx
);
186 static int ia64_speculate_insn (rtx
, ds_t
, rtx
*);
187 static bool ia64_needs_block_p (ds_t
);
188 static rtx
ia64_gen_spec_check (rtx
, rtx
, ds_t
);
189 static int ia64_spec_check_p (rtx
);
190 static int ia64_spec_check_src_p (rtx
);
191 static rtx
gen_tls_get_addr (void);
192 static rtx
gen_thread_pointer (void);
193 static int find_gr_spill (enum ia64_frame_regs
, int);
194 static int next_scratch_gr_reg (void);
195 static void mark_reg_gr_used_mask (rtx
, void *);
196 static void ia64_compute_frame_size (HOST_WIDE_INT
);
197 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
198 static void finish_spill_pointers (void);
199 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
200 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
201 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
202 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
203 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
204 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
206 static void ia64_option_override (void);
207 static bool ia64_can_eliminate (const int, const int);
208 static enum machine_mode
hfa_element_mode (const_tree
, bool);
209 static void ia64_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
211 static int ia64_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
213 static rtx
ia64_function_arg_1 (cumulative_args_t
, enum machine_mode
,
214 const_tree
, bool, bool);
215 static rtx
ia64_function_arg (cumulative_args_t
, enum machine_mode
,
217 static rtx
ia64_function_incoming_arg (cumulative_args_t
,
218 enum machine_mode
, const_tree
, bool);
219 static void ia64_function_arg_advance (cumulative_args_t
, enum machine_mode
,
221 static unsigned int ia64_function_arg_boundary (enum machine_mode
,
223 static bool ia64_function_ok_for_sibcall (tree
, tree
);
224 static bool ia64_return_in_memory (const_tree
, const_tree
);
225 static rtx
ia64_function_value (const_tree
, const_tree
, bool);
226 static rtx
ia64_libcall_value (enum machine_mode
, const_rtx
);
227 static bool ia64_function_value_regno_p (const unsigned int);
228 static int ia64_register_move_cost (enum machine_mode
, reg_class_t
,
230 static int ia64_memory_move_cost (enum machine_mode mode
, reg_class_t
,
232 static bool ia64_rtx_costs (rtx
, int, int, int, int *, bool);
233 static int ia64_unspec_may_trap_p (const_rtx
, unsigned);
234 static void fix_range (const char *);
235 static struct machine_function
* ia64_init_machine_status (void);
236 static void emit_insn_group_barriers (FILE *);
237 static void emit_all_insn_group_barriers (FILE *);
238 static void final_emit_insn_group_barriers (FILE *);
239 static void emit_predicate_relation_info (void);
240 static void ia64_reorg (void);
241 static bool ia64_in_small_data_p (const_tree
);
242 static void process_epilogue (FILE *, rtx
, bool, bool);
244 static bool ia64_assemble_integer (rtx
, unsigned int, int);
245 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
246 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
247 static void ia64_output_function_end_prologue (FILE *);
249 static void ia64_print_operand (FILE *, rtx
, int);
250 static void ia64_print_operand_address (FILE *, rtx
);
251 static bool ia64_print_operand_punct_valid_p (unsigned char code
);
253 static int ia64_issue_rate (void);
254 static int ia64_adjust_cost_2 (rtx
, int, rtx
, int, dw_t
);
255 static void ia64_sched_init (FILE *, int, int);
256 static void ia64_sched_init_global (FILE *, int, int);
257 static void ia64_sched_finish_global (FILE *, int);
258 static void ia64_sched_finish (FILE *, int);
259 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
260 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
261 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
262 static int ia64_variable_issue (FILE *, int, rtx
, int);
264 static void ia64_asm_unwind_emit (FILE *, rtx
);
265 static void ia64_asm_emit_except_personality (rtx
);
266 static void ia64_asm_init_sections (void);
268 static enum unwind_info_type
ia64_debug_unwind_info (void);
270 static struct bundle_state
*get_free_bundle_state (void);
271 static void free_bundle_state (struct bundle_state
*);
272 static void initiate_bundle_states (void);
273 static void finish_bundle_states (void);
274 static int insert_bundle_state (struct bundle_state
*);
275 static void initiate_bundle_state_table (void);
276 static void finish_bundle_state_table (void);
277 static int try_issue_nops (struct bundle_state
*, int);
278 static int try_issue_insn (struct bundle_state
*, rtx
);
279 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
280 static int get_max_pos (state_t
);
281 static int get_template (state_t
, int);
283 static rtx
get_next_important_insn (rtx
, rtx
);
284 static bool important_for_bundling_p (rtx
);
285 static bool unknown_for_bundling_p (rtx
);
286 static void bundling (FILE *, int, rtx
, rtx
);
288 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
289 HOST_WIDE_INT
, tree
);
290 static void ia64_file_start (void);
291 static void ia64_globalize_decl_name (FILE *, tree
);
293 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
294 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
295 static section
*ia64_select_rtx_section (enum machine_mode
, rtx
,
296 unsigned HOST_WIDE_INT
);
297 static void ia64_output_dwarf_dtprel (FILE *, int, rtx
)
299 static unsigned int ia64_section_type_flags (tree
, const char *, int);
300 static void ia64_init_libfuncs (void)
302 static void ia64_hpux_init_libfuncs (void)
304 static void ia64_sysv4_init_libfuncs (void)
306 static void ia64_vms_init_libfuncs (void)
308 static void ia64_soft_fp_init_libfuncs (void)
310 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode
)
312 static tree
ia64_vms_common_object_attribute (tree
*, tree
, tree
, int, bool *)
315 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
316 static tree
ia64_handle_version_id_attribute (tree
*, tree
, tree
, int, bool *);
317 static void ia64_encode_section_info (tree
, rtx
, int);
318 static rtx
ia64_struct_value_rtx (tree
, int);
319 static tree
ia64_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
320 static bool ia64_scalar_mode_supported_p (enum machine_mode mode
);
321 static bool ia64_vector_mode_supported_p (enum machine_mode mode
);
322 static bool ia64_legitimate_constant_p (enum machine_mode
, rtx
);
323 static bool ia64_legitimate_address_p (enum machine_mode
, rtx
, bool);
324 static bool ia64_cannot_force_const_mem (enum machine_mode
, rtx
);
325 static const char *ia64_mangle_type (const_tree
);
326 static const char *ia64_invalid_conversion (const_tree
, const_tree
);
327 static const char *ia64_invalid_unary_op (int, const_tree
);
328 static const char *ia64_invalid_binary_op (int, const_tree
, const_tree
);
329 static enum machine_mode
ia64_c_mode_for_suffix (char);
330 static void ia64_trampoline_init (rtx
, tree
, rtx
);
331 static void ia64_override_options_after_change (void);
332 static bool ia64_member_type_forces_blk (const_tree
, enum machine_mode
);
334 static tree
ia64_builtin_decl (unsigned, bool);
336 static reg_class_t
ia64_preferred_reload_class (rtx
, reg_class_t
);
337 static enum machine_mode
ia64_get_reg_raw_mode (int regno
);
338 static section
* ia64_hpux_function_section (tree
, enum node_frequency
,
341 static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
342 const unsigned char *sel
);
344 #define MAX_VECT_LEN 8
346 struct expand_vec_perm_d
348 rtx target
, op0
, op1
;
349 unsigned char perm
[MAX_VECT_LEN
];
350 enum machine_mode vmode
;
356 static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
);
359 /* Table of valid machine attributes. */
360 static const struct attribute_spec ia64_attribute_table
[] =
362 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
363 affects_type_identity } */
364 { "syscall_linkage", 0, 0, false, true, true, NULL
, false },
365 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
,
367 #if TARGET_ABI_OPEN_VMS
368 { "common_object", 1, 1, true, false, false,
369 ia64_vms_common_object_attribute
, false },
371 { "version_id", 1, 1, true, false, false,
372 ia64_handle_version_id_attribute
, false },
373 { NULL
, 0, 0, false, false, false, NULL
, false }
376 /* Initialize the GCC target structure. */
377 #undef TARGET_ATTRIBUTE_TABLE
378 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
380 #undef TARGET_INIT_BUILTINS
381 #define TARGET_INIT_BUILTINS ia64_init_builtins
383 #undef TARGET_EXPAND_BUILTIN
384 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
386 #undef TARGET_BUILTIN_DECL
387 #define TARGET_BUILTIN_DECL ia64_builtin_decl
389 #undef TARGET_ASM_BYTE_OP
390 #define TARGET_ASM_BYTE_OP "\tdata1\t"
391 #undef TARGET_ASM_ALIGNED_HI_OP
392 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
393 #undef TARGET_ASM_ALIGNED_SI_OP
394 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
395 #undef TARGET_ASM_ALIGNED_DI_OP
396 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
397 #undef TARGET_ASM_UNALIGNED_HI_OP
398 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
399 #undef TARGET_ASM_UNALIGNED_SI_OP
400 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
401 #undef TARGET_ASM_UNALIGNED_DI_OP
402 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
403 #undef TARGET_ASM_INTEGER
404 #define TARGET_ASM_INTEGER ia64_assemble_integer
406 #undef TARGET_OPTION_OVERRIDE
407 #define TARGET_OPTION_OVERRIDE ia64_option_override
409 #undef TARGET_ASM_FUNCTION_PROLOGUE
410 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
411 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
412 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
413 #undef TARGET_ASM_FUNCTION_EPILOGUE
414 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
416 #undef TARGET_PRINT_OPERAND
417 #define TARGET_PRINT_OPERAND ia64_print_operand
418 #undef TARGET_PRINT_OPERAND_ADDRESS
419 #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address
420 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
421 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p
423 #undef TARGET_IN_SMALL_DATA_P
424 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
426 #undef TARGET_SCHED_ADJUST_COST_2
427 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
428 #undef TARGET_SCHED_ISSUE_RATE
429 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
430 #undef TARGET_SCHED_VARIABLE_ISSUE
431 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
432 #undef TARGET_SCHED_INIT
433 #define TARGET_SCHED_INIT ia64_sched_init
434 #undef TARGET_SCHED_FINISH
435 #define TARGET_SCHED_FINISH ia64_sched_finish
436 #undef TARGET_SCHED_INIT_GLOBAL
437 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
438 #undef TARGET_SCHED_FINISH_GLOBAL
439 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
440 #undef TARGET_SCHED_REORDER
441 #define TARGET_SCHED_REORDER ia64_sched_reorder
442 #undef TARGET_SCHED_REORDER2
443 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
445 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
446 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
448 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
449 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
451 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
452 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
453 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
454 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
456 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
457 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
458 ia64_first_cycle_multipass_dfa_lookahead_guard
460 #undef TARGET_SCHED_DFA_NEW_CYCLE
461 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
463 #undef TARGET_SCHED_H_I_D_EXTENDED
464 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
466 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
467 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
469 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
470 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
472 #undef TARGET_SCHED_SET_SCHED_CONTEXT
473 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
475 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
476 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
478 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
479 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
481 #undef TARGET_SCHED_SET_SCHED_FLAGS
482 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
484 #undef TARGET_SCHED_GET_INSN_SPEC_DS
485 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
487 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
488 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
490 #undef TARGET_SCHED_SPECULATE_INSN
491 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
493 #undef TARGET_SCHED_NEEDS_BLOCK_P
494 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
496 #undef TARGET_SCHED_GEN_SPEC_CHECK
497 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
499 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
500 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
501 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
503 #undef TARGET_SCHED_SKIP_RTX_P
504 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
506 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
507 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
508 #undef TARGET_ARG_PARTIAL_BYTES
509 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
510 #undef TARGET_FUNCTION_ARG
511 #define TARGET_FUNCTION_ARG ia64_function_arg
512 #undef TARGET_FUNCTION_INCOMING_ARG
513 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
514 #undef TARGET_FUNCTION_ARG_ADVANCE
515 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
516 #undef TARGET_FUNCTION_ARG_BOUNDARY
517 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
519 #undef TARGET_ASM_OUTPUT_MI_THUNK
520 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
521 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
522 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
524 #undef TARGET_ASM_FILE_START
525 #define TARGET_ASM_FILE_START ia64_file_start
527 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
528 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
530 #undef TARGET_REGISTER_MOVE_COST
531 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
532 #undef TARGET_MEMORY_MOVE_COST
533 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
534 #undef TARGET_RTX_COSTS
535 #define TARGET_RTX_COSTS ia64_rtx_costs
536 #undef TARGET_ADDRESS_COST
537 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
539 #undef TARGET_UNSPEC_MAY_TRAP_P
540 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
542 #undef TARGET_MACHINE_DEPENDENT_REORG
543 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
545 #undef TARGET_ENCODE_SECTION_INFO
546 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
548 #undef TARGET_SECTION_TYPE_FLAGS
549 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
552 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
553 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
556 /* ??? Investigate. */
558 #undef TARGET_PROMOTE_PROTOTYPES
559 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
562 #undef TARGET_FUNCTION_VALUE
563 #define TARGET_FUNCTION_VALUE ia64_function_value
564 #undef TARGET_LIBCALL_VALUE
565 #define TARGET_LIBCALL_VALUE ia64_libcall_value
566 #undef TARGET_FUNCTION_VALUE_REGNO_P
567 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
569 #undef TARGET_STRUCT_VALUE_RTX
570 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
571 #undef TARGET_RETURN_IN_MEMORY
572 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
573 #undef TARGET_SETUP_INCOMING_VARARGS
574 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
575 #undef TARGET_STRICT_ARGUMENT_NAMING
576 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
577 #undef TARGET_MUST_PASS_IN_STACK
578 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
579 #undef TARGET_GET_RAW_RESULT_MODE
580 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
581 #undef TARGET_GET_RAW_ARG_MODE
582 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
584 #undef TARGET_MEMBER_TYPE_FORCES_BLK
585 #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk
587 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
588 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
590 #undef TARGET_ASM_UNWIND_EMIT
591 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
592 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
593 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
594 #undef TARGET_ASM_INIT_SECTIONS
595 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
597 #undef TARGET_DEBUG_UNWIND_INFO
598 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
600 #undef TARGET_SCALAR_MODE_SUPPORTED_P
601 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
602 #undef TARGET_VECTOR_MODE_SUPPORTED_P
603 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
605 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
606 in an order different from the specified program order. */
607 #undef TARGET_RELAXED_ORDERING
608 #define TARGET_RELAXED_ORDERING true
610 #undef TARGET_LEGITIMATE_CONSTANT_P
611 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
612 #undef TARGET_LEGITIMATE_ADDRESS_P
613 #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p
615 #undef TARGET_CANNOT_FORCE_CONST_MEM
616 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
618 #undef TARGET_MANGLE_TYPE
619 #define TARGET_MANGLE_TYPE ia64_mangle_type
621 #undef TARGET_INVALID_CONVERSION
622 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
623 #undef TARGET_INVALID_UNARY_OP
624 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
625 #undef TARGET_INVALID_BINARY_OP
626 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
628 #undef TARGET_C_MODE_FOR_SUFFIX
629 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
631 #undef TARGET_CAN_ELIMINATE
632 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
634 #undef TARGET_TRAMPOLINE_INIT
635 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
637 #undef TARGET_CAN_USE_DOLOOP_P
638 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
639 #undef TARGET_INVALID_WITHIN_DOLOOP
640 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
642 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
643 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
645 #undef TARGET_PREFERRED_RELOAD_CLASS
646 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
648 #undef TARGET_DELAY_SCHED2
649 #define TARGET_DELAY_SCHED2 true
651 /* Variable tracking should be run after all optimizations which
652 change order of insns. It also needs a valid CFG. */
653 #undef TARGET_DELAY_VARTRACK
654 #define TARGET_DELAY_VARTRACK true
656 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
657 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok
659 struct gcc_target targetm
= TARGET_INITIALIZER
;
663 ADDR_AREA_NORMAL
, /* normal address area */
664 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
668 static GTY(()) tree small_ident1
;
669 static GTY(()) tree small_ident2
;
674 if (small_ident1
== 0)
676 small_ident1
= get_identifier ("small");
677 small_ident2
= get_identifier ("__small__");
681 /* Retrieve the address area that has been chosen for the given decl. */
683 static ia64_addr_area
684 ia64_get_addr_area (tree decl
)
688 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
694 id
= TREE_VALUE (TREE_VALUE (model_attr
));
695 if (id
== small_ident1
|| id
== small_ident2
)
696 return ADDR_AREA_SMALL
;
698 return ADDR_AREA_NORMAL
;
702 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
,
703 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
705 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
707 tree arg
, decl
= *node
;
710 arg
= TREE_VALUE (args
);
711 if (arg
== small_ident1
|| arg
== small_ident2
)
713 addr_area
= ADDR_AREA_SMALL
;
717 warning (OPT_Wattributes
, "invalid argument of %qE attribute",
719 *no_add_attrs
= true;
722 switch (TREE_CODE (decl
))
725 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
727 && !TREE_STATIC (decl
))
729 error_at (DECL_SOURCE_LOCATION (decl
),
730 "an address area attribute cannot be specified for "
732 *no_add_attrs
= true;
734 area
= ia64_get_addr_area (decl
);
735 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
737 error ("address area of %q+D conflicts with previous "
738 "declaration", decl
);
739 *no_add_attrs
= true;
744 error_at (DECL_SOURCE_LOCATION (decl
),
745 "address area attribute cannot be specified for "
747 *no_add_attrs
= true;
751 warning (OPT_Wattributes
, "%qE attribute ignored",
753 *no_add_attrs
= true;
760 /* Part of the low level implementation of DEC Ada pragma Common_Object which
761 enables the shared use of variables stored in overlaid linker areas
762 corresponding to the use of Fortran COMMON. */
765 ia64_vms_common_object_attribute (tree
*node
, tree name
, tree args
,
766 int flags ATTRIBUTE_UNUSED
,
772 gcc_assert (DECL_P (decl
));
774 DECL_COMMON (decl
) = 1;
775 id
= TREE_VALUE (args
);
776 if (TREE_CODE (id
) != IDENTIFIER_NODE
&& TREE_CODE (id
) != STRING_CST
)
778 error ("%qE attribute requires a string constant argument", name
);
779 *no_add_attrs
= true;
785 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
788 ia64_vms_output_aligned_decl_common (FILE *file
, tree decl
, const char *name
,
789 unsigned HOST_WIDE_INT size
,
792 tree attr
= DECL_ATTRIBUTES (decl
);
795 attr
= lookup_attribute ("common_object", attr
);
798 tree id
= TREE_VALUE (TREE_VALUE (attr
));
801 if (TREE_CODE (id
) == IDENTIFIER_NODE
)
802 name
= IDENTIFIER_POINTER (id
);
803 else if (TREE_CODE (id
) == STRING_CST
)
804 name
= TREE_STRING_POINTER (id
);
808 fprintf (file
, "\t.vms_common\t\"%s\",", name
);
811 fprintf (file
, "%s", COMMON_ASM_OP
);
813 /* Code from elfos.h. */
814 assemble_name (file
, name
);
815 fprintf (file
, ","HOST_WIDE_INT_PRINT_UNSIGNED
",%u",
816 size
, align
/ BITS_PER_UNIT
);
822 ia64_encode_addr_area (tree decl
, rtx symbol
)
826 flags
= SYMBOL_REF_FLAGS (symbol
);
827 switch (ia64_get_addr_area (decl
))
829 case ADDR_AREA_NORMAL
: break;
830 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
831 default: gcc_unreachable ();
833 SYMBOL_REF_FLAGS (symbol
) = flags
;
837 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
839 default_encode_section_info (decl
, rtl
, first
);
841 /* Careful not to prod global register variables. */
842 if (TREE_CODE (decl
) == VAR_DECL
843 && GET_CODE (DECL_RTL (decl
)) == MEM
844 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
845 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
846 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
849 /* Return 1 if the operands of a move are ok. */
852 ia64_move_ok (rtx dst
, rtx src
)
854 /* If we're under init_recog_no_volatile, we'll not be able to use
855 memory_operand. So check the code directly and don't worry about
856 the validity of the underlying address, which should have been
857 checked elsewhere anyway. */
858 if (GET_CODE (dst
) != MEM
)
860 if (GET_CODE (src
) == MEM
)
862 if (register_operand (src
, VOIDmode
))
865 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
866 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
867 return src
== const0_rtx
;
869 return satisfies_constraint_G (src
);
872 /* Return 1 if the operands are ok for a floating point load pair. */
875 ia64_load_pair_ok (rtx dst
, rtx src
)
877 /* ??? There is a thinko in the implementation of the "x" constraint and the
878 FP_REGS class. The constraint will also reject (reg f30:TI) so we must
879 also return false for it. */
880 if (GET_CODE (dst
) != REG
881 || !(FP_REGNO_P (REGNO (dst
)) && FP_REGNO_P (REGNO (dst
) + 1)))
883 if (GET_CODE (src
) != MEM
|| MEM_VOLATILE_P (src
))
885 switch (GET_CODE (XEXP (src
, 0)))
894 rtx adjust
= XEXP (XEXP (XEXP (src
, 0), 1), 1);
896 if (GET_CODE (adjust
) != CONST_INT
897 || INTVAL (adjust
) != GET_MODE_SIZE (GET_MODE (src
)))
908 addp4_optimize_ok (rtx op1
, rtx op2
)
910 return (basereg_operand (op1
, GET_MODE(op1
)) !=
911 basereg_operand (op2
, GET_MODE(op2
)));
914 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
915 Return the length of the field, or <= 0 on failure. */
918 ia64_depz_field_mask (rtx rop
, rtx rshift
)
920 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
921 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
923 /* Get rid of the zero bits we're shifting in. */
926 /* We must now have a solid block of 1's at bit 0. */
927 return exact_log2 (op
+ 1);
930 /* Return the TLS model to use for ADDR. */
932 static enum tls_model
933 tls_symbolic_operand_type (rtx addr
)
935 enum tls_model tls_kind
= TLS_MODEL_NONE
;
937 if (GET_CODE (addr
) == CONST
)
939 if (GET_CODE (XEXP (addr
, 0)) == PLUS
940 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
941 tls_kind
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr
, 0), 0));
943 else if (GET_CODE (addr
) == SYMBOL_REF
)
944 tls_kind
= SYMBOL_REF_TLS_MODEL (addr
);
949 /* Returns true if REG (assumed to be a `reg' RTX) is valid for use
950 as a base register. */
953 ia64_reg_ok_for_base_p (const_rtx reg
, bool strict
)
956 && REGNO_OK_FOR_BASE_P (REGNO (reg
)))
959 && (GENERAL_REGNO_P (REGNO (reg
))
960 || !HARD_REGISTER_P (reg
)))
967 ia64_legitimate_address_reg (const_rtx reg
, bool strict
)
969 if ((REG_P (reg
) && ia64_reg_ok_for_base_p (reg
, strict
))
970 || (GET_CODE (reg
) == SUBREG
&& REG_P (XEXP (reg
, 0))
971 && ia64_reg_ok_for_base_p (XEXP (reg
, 0), strict
)))
978 ia64_legitimate_address_disp (const_rtx reg
, const_rtx disp
, bool strict
)
980 if (GET_CODE (disp
) == PLUS
981 && rtx_equal_p (reg
, XEXP (disp
, 0))
982 && (ia64_legitimate_address_reg (XEXP (disp
, 1), strict
)
983 || (CONST_INT_P (XEXP (disp
, 1))
984 && IN_RANGE (INTVAL (XEXP (disp
, 1)), -256, 255))))
990 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
993 ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
996 if (ia64_legitimate_address_reg (x
, strict
))
998 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == POST_DEC
)
999 && ia64_legitimate_address_reg (XEXP (x
, 0), strict
)
1000 && XEXP (x
, 0) != arg_pointer_rtx
)
1002 else if (GET_CODE (x
) == POST_MODIFY
1003 && ia64_legitimate_address_reg (XEXP (x
, 0), strict
)
1004 && XEXP (x
, 0) != arg_pointer_rtx
1005 && ia64_legitimate_address_disp (XEXP (x
, 0), XEXP (x
, 1), strict
))
1011 /* Return true if X is a constant that is valid for some immediate
1012 field in an instruction. */
1015 ia64_legitimate_constant_p (enum machine_mode mode
, rtx x
)
1017 switch (GET_CODE (x
))
1024 if (GET_MODE (x
) == VOIDmode
|| mode
== SFmode
|| mode
== DFmode
)
1026 return satisfies_constraint_G (x
);
1030 /* ??? Short term workaround for PR 28490. We must make the code here
1031 match the code in ia64_expand_move and move_operand, even though they
1032 are both technically wrong. */
1033 if (tls_symbolic_operand_type (x
) == 0)
1035 HOST_WIDE_INT addend
= 0;
1038 if (GET_CODE (op
) == CONST
1039 && GET_CODE (XEXP (op
, 0)) == PLUS
1040 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1042 addend
= INTVAL (XEXP (XEXP (op
, 0), 1));
1043 op
= XEXP (XEXP (op
, 0), 0);
1046 if (any_offset_symbol_operand (op
, mode
)
1047 || function_operand (op
, mode
))
1049 if (aligned_offset_symbol_operand (op
, mode
))
1050 return (addend
& 0x3fff) == 0;
1056 if (mode
== V2SFmode
)
1057 return satisfies_constraint_Y (x
);
1059 return (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
1060 && GET_MODE_SIZE (mode
) <= 8);
1067 /* Don't allow TLS addresses to get spilled to memory. */
1070 ia64_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1074 return tls_symbolic_operand_type (x
) != 0;
1077 /* Expand a symbolic constant load. */
1080 ia64_expand_load_address (rtx dest
, rtx src
)
1082 gcc_assert (GET_CODE (dest
) == REG
);
1084 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1085 having to pointer-extend the value afterward. Other forms of address
1086 computation below are also more natural to compute as 64-bit quantities.
1087 If we've been given an SImode destination register, change it. */
1088 if (GET_MODE (dest
) != Pmode
)
1089 dest
= gen_rtx_REG_offset (dest
, Pmode
, REGNO (dest
),
1090 byte_lowpart_offset (Pmode
, GET_MODE (dest
)));
1094 if (small_addr_symbolic_operand (src
, VOIDmode
))
1097 if (TARGET_AUTO_PIC
)
1098 emit_insn (gen_load_gprel64 (dest
, src
));
1099 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1100 emit_insn (gen_load_fptr (dest
, src
));
1101 else if (sdata_symbolic_operand (src
, VOIDmode
))
1102 emit_insn (gen_load_gprel (dest
, src
));
1105 HOST_WIDE_INT addend
= 0;
1108 /* We did split constant offsets in ia64_expand_move, and we did try
1109 to keep them split in move_operand, but we also allowed reload to
1110 rematerialize arbitrary constants rather than spill the value to
1111 the stack and reload it. So we have to be prepared here to split
1112 them apart again. */
1113 if (GET_CODE (src
) == CONST
)
1115 HOST_WIDE_INT hi
, lo
;
1117 hi
= INTVAL (XEXP (XEXP (src
, 0), 1));
1118 lo
= ((hi
& 0x3fff) ^ 0x2000) - 0x2000;
1124 src
= plus_constant (Pmode
, XEXP (XEXP (src
, 0), 0), hi
);
1128 tmp
= gen_rtx_HIGH (Pmode
, src
);
1129 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1130 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1132 tmp
= gen_rtx_LO_SUM (Pmode
, gen_const_mem (Pmode
, dest
), src
);
1133 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1137 tmp
= gen_rtx_PLUS (Pmode
, dest
, GEN_INT (addend
));
1138 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1145 static GTY(()) rtx gen_tls_tga
;
1147 gen_tls_get_addr (void)
1150 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1154 static GTY(()) rtx thread_pointer_rtx
;
1156 gen_thread_pointer (void)
1158 if (!thread_pointer_rtx
)
1159 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1160 return thread_pointer_rtx
;
1164 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
,
1165 rtx orig_op1
, HOST_WIDE_INT addend
)
1167 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1169 HOST_WIDE_INT addend_lo
, addend_hi
;
1173 case TLS_MODEL_GLOBAL_DYNAMIC
:
1176 tga_op1
= gen_reg_rtx (Pmode
);
1177 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1179 tga_op2
= gen_reg_rtx (Pmode
);
1180 emit_insn (gen_load_dtprel (tga_op2
, op1
));
1182 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1183 LCT_CONST
, Pmode
, 2, tga_op1
,
1184 Pmode
, tga_op2
, Pmode
);
1186 insns
= get_insns ();
1189 if (GET_MODE (op0
) != Pmode
)
1191 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1194 case TLS_MODEL_LOCAL_DYNAMIC
:
1195 /* ??? This isn't the completely proper way to do local-dynamic
1196 If the call to __tls_get_addr is used only by a single symbol,
1197 then we should (somehow) move the dtprel to the second arg
1198 to avoid the extra add. */
1201 tga_op1
= gen_reg_rtx (Pmode
);
1202 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1204 tga_op2
= const0_rtx
;
1206 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1207 LCT_CONST
, Pmode
, 2, tga_op1
,
1208 Pmode
, tga_op2
, Pmode
);
1210 insns
= get_insns ();
1213 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1215 tmp
= gen_reg_rtx (Pmode
);
1216 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1218 if (!register_operand (op0
, Pmode
))
1219 op0
= gen_reg_rtx (Pmode
);
1222 emit_insn (gen_load_dtprel (op0
, op1
));
1223 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1226 emit_insn (gen_add_dtprel (op0
, op1
, tmp
));
1229 case TLS_MODEL_INITIAL_EXEC
:
1230 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1231 addend_hi
= addend
- addend_lo
;
1233 op1
= plus_constant (Pmode
, op1
, addend_hi
);
1236 tmp
= gen_reg_rtx (Pmode
);
1237 emit_insn (gen_load_tprel (tmp
, op1
));
1239 if (!register_operand (op0
, Pmode
))
1240 op0
= gen_reg_rtx (Pmode
);
1241 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1244 case TLS_MODEL_LOCAL_EXEC
:
1245 if (!register_operand (op0
, Pmode
))
1246 op0
= gen_reg_rtx (Pmode
);
1252 emit_insn (gen_load_tprel (op0
, op1
));
1253 emit_insn (gen_adddi3 (op0
, op0
, gen_thread_pointer ()));
1256 emit_insn (gen_add_tprel (op0
, op1
, gen_thread_pointer ()));
1264 op0
= expand_simple_binop (Pmode
, PLUS
, op0
, GEN_INT (addend
),
1265 orig_op0
, 1, OPTAB_DIRECT
);
1266 if (orig_op0
== op0
)
1268 if (GET_MODE (orig_op0
) == Pmode
)
1270 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1274 ia64_expand_move (rtx op0
, rtx op1
)
1276 enum machine_mode mode
= GET_MODE (op0
);
1278 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1279 op1
= force_reg (mode
, op1
);
1281 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1283 HOST_WIDE_INT addend
= 0;
1284 enum tls_model tls_kind
;
1287 if (GET_CODE (op1
) == CONST
1288 && GET_CODE (XEXP (op1
, 0)) == PLUS
1289 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
)
1291 addend
= INTVAL (XEXP (XEXP (op1
, 0), 1));
1292 sym
= XEXP (XEXP (op1
, 0), 0);
1295 tls_kind
= tls_symbolic_operand_type (sym
);
1297 return ia64_expand_tls_address (tls_kind
, op0
, sym
, op1
, addend
);
1299 if (any_offset_symbol_operand (sym
, mode
))
1301 else if (aligned_offset_symbol_operand (sym
, mode
))
1303 HOST_WIDE_INT addend_lo
, addend_hi
;
1305 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1306 addend_hi
= addend
- addend_lo
;
1310 op1
= plus_constant (mode
, sym
, addend_hi
);
1319 if (reload_completed
)
1321 /* We really should have taken care of this offset earlier. */
1322 gcc_assert (addend
== 0);
1323 if (ia64_expand_load_address (op0
, op1
))
1329 rtx subtarget
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (mode
);
1331 emit_insn (gen_rtx_SET (VOIDmode
, subtarget
, op1
));
1333 op1
= expand_simple_binop (mode
, PLUS
, subtarget
,
1334 GEN_INT (addend
), op0
, 1, OPTAB_DIRECT
);
1343 /* Split a move from OP1 to OP0 conditional on COND. */
1346 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1348 rtx insn
, first
= get_last_insn ();
1350 emit_move_insn (op0
, op1
);
1352 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1354 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1358 /* Split a post-reload TImode or TFmode reference into two DImode
1359 components. This is made extra difficult by the fact that we do
1360 not get any scratch registers to work with, because reload cannot
1361 be prevented from giving us a scratch that overlaps the register
1362 pair involved. So instead, when addressing memory, we tweak the
1363 pointer register up and back down with POST_INCs. Or up and not
1364 back down when we can get away with it.
1366 REVERSED is true when the loads must be done in reversed order
1367 (high word first) for correctness. DEAD is true when the pointer
1368 dies with the second insn we generate and therefore the second
1369 address must not carry a postmodify.
1371 May return an insn which is to be emitted after the moves. */
1374 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1378 switch (GET_CODE (in
))
1381 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1382 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1387 /* Cannot occur reversed. */
1388 gcc_assert (!reversed
);
1390 if (GET_MODE (in
) != TFmode
)
1391 split_double (in
, &out
[0], &out
[1]);
1393 /* split_double does not understand how to split a TFmode
1394 quantity into a pair of DImode constants. */
1397 unsigned HOST_WIDE_INT p
[2];
1398 long l
[4]; /* TFmode is 128 bits */
1400 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1401 real_to_target (l
, &r
, TFmode
);
1403 if (FLOAT_WORDS_BIG_ENDIAN
)
1405 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1406 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1410 p
[0] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1411 p
[1] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1413 out
[0] = GEN_INT (p
[0]);
1414 out
[1] = GEN_INT (p
[1]);
1420 rtx base
= XEXP (in
, 0);
1423 switch (GET_CODE (base
))
1428 out
[0] = adjust_automodify_address
1429 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1430 out
[1] = adjust_automodify_address
1431 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1435 /* Reversal requires a pre-increment, which can only
1436 be done as a separate insn. */
1437 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1438 out
[0] = adjust_automodify_address
1439 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1440 out
[1] = adjust_address (in
, DImode
, 0);
1445 gcc_assert (!reversed
&& !dead
);
1447 /* Just do the increment in two steps. */
1448 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1449 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1453 gcc_assert (!reversed
&& !dead
);
1455 /* Add 8, subtract 24. */
1456 base
= XEXP (base
, 0);
1457 out
[0] = adjust_automodify_address
1458 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1459 out
[1] = adjust_automodify_address
1461 gen_rtx_POST_MODIFY (Pmode
, base
,
1462 plus_constant (Pmode
, base
, -24)),
1467 gcc_assert (!reversed
&& !dead
);
1469 /* Extract and adjust the modification. This case is
1470 trickier than the others, because we might have an
1471 index register, or we might have a combined offset that
1472 doesn't fit a signed 9-bit displacement field. We can
1473 assume the incoming expression is already legitimate. */
1474 offset
= XEXP (base
, 1);
1475 base
= XEXP (base
, 0);
1477 out
[0] = adjust_automodify_address
1478 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1480 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1482 /* Can't adjust the postmodify to match. Emit the
1483 original, then a separate addition insn. */
1484 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1485 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1489 gcc_assert (GET_CODE (XEXP (offset
, 1)) == CONST_INT
);
1490 if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1492 /* Again the postmodify cannot be made to match,
1493 but in this case it's more efficient to get rid
1494 of the postmodify entirely and fix up with an
1496 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1498 (base
, base
, GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1502 /* Combined offset still fits in the displacement field.
1503 (We cannot overflow it at the high end.) */
1504 out
[1] = adjust_automodify_address
1505 (in
, DImode
, gen_rtx_POST_MODIFY
1506 (Pmode
, base
, gen_rtx_PLUS
1508 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1527 /* Split a TImode or TFmode move instruction after reload.
1528 This is used by *movtf_internal and *movti_internal. */
1530 ia64_split_tmode_move (rtx operands
[])
1532 rtx in
[2], out
[2], insn
;
1535 bool reversed
= false;
1537 /* It is possible for reload to decide to overwrite a pointer with
1538 the value it points to. In that case we have to do the loads in
1539 the appropriate order so that the pointer is not destroyed too
1540 early. Also we must not generate a postmodify for that second
1541 load, or rws_access_regno will die. And we must not generate a
1542 postmodify for the second load if the destination register
1543 overlaps with the base register. */
1544 if (GET_CODE (operands
[1]) == MEM
1545 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1547 rtx base
= XEXP (operands
[1], 0);
1548 while (GET_CODE (base
) != REG
)
1549 base
= XEXP (base
, 0);
1551 if (REGNO (base
) == REGNO (operands
[0]))
1554 if (refers_to_regno_p (REGNO (operands
[0]),
1555 REGNO (operands
[0])+2,
1559 /* Another reason to do the moves in reversed order is if the first
1560 element of the target register pair is also the second element of
1561 the source register pair. */
1562 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1563 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1566 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1567 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1569 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1570 if (GET_CODE (EXP) == MEM \
1571 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1572 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1573 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1574 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1576 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1577 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1578 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1580 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1581 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1582 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1585 emit_insn (fixup
[0]);
1587 emit_insn (fixup
[1]);
1589 #undef MAYBE_ADD_REG_INC_NOTE
1592 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1593 through memory plus an extra GR scratch register. Except that you can
1594 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1595 SECONDARY_RELOAD_CLASS, but not both.
1597 We got into problems in the first place by allowing a construct like
1598 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1599 This solution attempts to prevent this situation from occurring. When
1600 we see something like the above, we spill the inner register to memory. */
1603 spill_xfmode_rfmode_operand (rtx in
, int force
, enum machine_mode mode
)
1605 if (GET_CODE (in
) == SUBREG
1606 && GET_MODE (SUBREG_REG (in
)) == TImode
1607 && GET_CODE (SUBREG_REG (in
)) == REG
)
1609 rtx memt
= assign_stack_temp (TImode
, 16);
1610 emit_move_insn (memt
, SUBREG_REG (in
));
1611 return adjust_address (memt
, mode
, 0);
1613 else if (force
&& GET_CODE (in
) == REG
)
1615 rtx memx
= assign_stack_temp (mode
, 16);
1616 emit_move_insn (memx
, in
);
1623 /* Expand the movxf or movrf pattern (MODE says which) with the given
1624 OPERANDS, returning true if the pattern should then invoke
1628 ia64_expand_movxf_movrf (enum machine_mode mode
, rtx operands
[])
1630 rtx op0
= operands
[0];
1632 if (GET_CODE (op0
) == SUBREG
)
1633 op0
= SUBREG_REG (op0
);
1635 /* We must support XFmode loads into general registers for stdarg/vararg,
1636 unprototyped calls, and a rare case where a long double is passed as
1637 an argument after a float HFA fills the FP registers. We split them into
1638 DImode loads for convenience. We also need to support XFmode stores
1639 for the last case. This case does not happen for stdarg/vararg routines,
1640 because we do a block store to memory of unnamed arguments. */
1642 if (GET_CODE (op0
) == REG
&& GR_REGNO_P (REGNO (op0
)))
1646 /* We're hoping to transform everything that deals with XFmode
1647 quantities and GR registers early in the compiler. */
1648 gcc_assert (can_create_pseudo_p ());
1650 /* Struct to register can just use TImode instead. */
1651 if ((GET_CODE (operands
[1]) == SUBREG
1652 && GET_MODE (SUBREG_REG (operands
[1])) == TImode
)
1653 || (GET_CODE (operands
[1]) == REG
1654 && GR_REGNO_P (REGNO (operands
[1]))))
1656 rtx op1
= operands
[1];
1658 if (GET_CODE (op1
) == SUBREG
)
1659 op1
= SUBREG_REG (op1
);
1661 op1
= gen_rtx_REG (TImode
, REGNO (op1
));
1663 emit_move_insn (gen_rtx_REG (TImode
, REGNO (op0
)), op1
);
1667 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1669 /* Don't word-swap when reading in the constant. */
1670 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
)),
1671 operand_subword (operands
[1], WORDS_BIG_ENDIAN
,
1673 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
) + 1),
1674 operand_subword (operands
[1], !WORDS_BIG_ENDIAN
,
1679 /* If the quantity is in a register not known to be GR, spill it. */
1680 if (register_operand (operands
[1], mode
))
1681 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 1, mode
);
1683 gcc_assert (GET_CODE (operands
[1]) == MEM
);
1685 /* Don't word-swap when reading in the value. */
1686 out
[0] = gen_rtx_REG (DImode
, REGNO (op0
));
1687 out
[1] = gen_rtx_REG (DImode
, REGNO (op0
) + 1);
1689 emit_move_insn (out
[0], adjust_address (operands
[1], DImode
, 0));
1690 emit_move_insn (out
[1], adjust_address (operands
[1], DImode
, 8));
1694 if (GET_CODE (operands
[1]) == REG
&& GR_REGNO_P (REGNO (operands
[1])))
1696 /* We're hoping to transform everything that deals with XFmode
1697 quantities and GR registers early in the compiler. */
1698 gcc_assert (can_create_pseudo_p ());
1700 /* Op0 can't be a GR_REG here, as that case is handled above.
1701 If op0 is a register, then we spill op1, so that we now have a
1702 MEM operand. This requires creating an XFmode subreg of a TImode reg
1703 to force the spill. */
1704 if (register_operand (operands
[0], mode
))
1706 rtx op1
= gen_rtx_REG (TImode
, REGNO (operands
[1]));
1707 op1
= gen_rtx_SUBREG (mode
, op1
, 0);
1708 operands
[1] = spill_xfmode_rfmode_operand (op1
, 0, mode
);
1715 gcc_assert (GET_CODE (operands
[0]) == MEM
);
1717 /* Don't word-swap when writing out the value. */
1718 in
[0] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
1719 in
[1] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
1721 emit_move_insn (adjust_address (operands
[0], DImode
, 0), in
[0]);
1722 emit_move_insn (adjust_address (operands
[0], DImode
, 8), in
[1]);
1727 if (!reload_in_progress
&& !reload_completed
)
1729 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 0, mode
);
1731 if (GET_MODE (op0
) == TImode
&& GET_CODE (op0
) == REG
)
1733 rtx memt
, memx
, in
= operands
[1];
1734 if (CONSTANT_P (in
))
1735 in
= validize_mem (force_const_mem (mode
, in
));
1736 if (GET_CODE (in
) == MEM
)
1737 memt
= adjust_address (in
, TImode
, 0);
1740 memt
= assign_stack_temp (TImode
, 16);
1741 memx
= adjust_address (memt
, mode
, 0);
1742 emit_move_insn (memx
, in
);
1744 emit_move_insn (op0
, memt
);
1748 if (!ia64_move_ok (operands
[0], operands
[1]))
1749 operands
[1] = force_reg (mode
, operands
[1]);
1755 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1756 with the expression that holds the compare result (in VOIDmode). */
1758 static GTY(()) rtx cmptf_libfunc
;
1761 ia64_expand_compare (rtx
*expr
, rtx
*op0
, rtx
*op1
)
1763 enum rtx_code code
= GET_CODE (*expr
);
1766 /* If we have a BImode input, then we already have a compare result, and
1767 do not need to emit another comparison. */
1768 if (GET_MODE (*op0
) == BImode
)
1770 gcc_assert ((code
== NE
|| code
== EQ
) && *op1
== const0_rtx
);
1773 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1774 magic number as its third argument, that indicates what to do.
1775 The return value is an integer to be compared against zero. */
1776 else if (TARGET_HPUX
&& GET_MODE (*op0
) == TFmode
)
1779 QCMP_INV
= 1, /* Raise FP_INVALID on NaNs as a side effect. */
1786 enum rtx_code ncode
;
1789 gcc_assert (cmptf_libfunc
&& GET_MODE (*op1
) == TFmode
);
1792 /* 1 = equal, 0 = not equal. Equality operators do
1793 not raise FP_INVALID when given a NaN operand. */
1794 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1795 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1796 /* isunordered() from C99. */
1797 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1798 case ORDERED
: magic
= QCMP_UNORD
; ncode
= EQ
; break;
1799 /* Relational operators raise FP_INVALID when given
1801 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1802 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1803 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1804 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1805 /* Unordered relational operators do not raise FP_INVALID
1806 when given a NaN operand. */
1807 case UNLT
: magic
= QCMP_LT
|QCMP_UNORD
; ncode
= NE
; break;
1808 case UNLE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_UNORD
; ncode
= NE
; break;
1809 case UNGT
: magic
= QCMP_GT
|QCMP_UNORD
; ncode
= NE
; break;
1810 case UNGE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_UNORD
; ncode
= NE
; break;
1811 /* Not supported. */
1814 default: gcc_unreachable ();
1819 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1820 *op0
, TFmode
, *op1
, TFmode
,
1821 GEN_INT (magic
), DImode
);
1822 cmp
= gen_reg_rtx (BImode
);
1823 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1824 gen_rtx_fmt_ee (ncode
, BImode
,
1827 insns
= get_insns ();
1830 emit_libcall_block (insns
, cmp
, cmp
,
1831 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
));
1836 cmp
= gen_reg_rtx (BImode
);
1837 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1838 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
)));
1842 *expr
= gen_rtx_fmt_ee (code
, VOIDmode
, cmp
, const0_rtx
);
1847 /* Generate an integral vector comparison. Return true if the condition has
1848 been reversed, and so the sense of the comparison should be inverted. */
1851 ia64_expand_vecint_compare (enum rtx_code code
, enum machine_mode mode
,
1852 rtx dest
, rtx op0
, rtx op1
)
1854 bool negate
= false;
1857 /* Canonicalize the comparison to EQ, GT, GTU. */
1868 code
= reverse_condition (code
);
1874 code
= reverse_condition (code
);
1880 code
= swap_condition (code
);
1881 x
= op0
, op0
= op1
, op1
= x
;
1888 /* Unsigned parallel compare is not supported by the hardware. Play some
1889 tricks to turn this into a signed comparison against 0. */
1898 /* Subtract (-(INT MAX) - 1) from both operands to make
1900 mask
= GEN_INT (0x80000000);
1901 mask
= gen_rtx_CONST_VECTOR (V2SImode
, gen_rtvec (2, mask
, mask
));
1902 mask
= force_reg (mode
, mask
);
1903 t1
= gen_reg_rtx (mode
);
1904 emit_insn (gen_subv2si3 (t1
, op0
, mask
));
1905 t2
= gen_reg_rtx (mode
);
1906 emit_insn (gen_subv2si3 (t2
, op1
, mask
));
1915 /* Perform a parallel unsigned saturating subtraction. */
1916 x
= gen_reg_rtx (mode
);
1917 emit_insn (gen_rtx_SET (VOIDmode
, x
,
1918 gen_rtx_US_MINUS (mode
, op0
, op1
)));
1922 op1
= CONST0_RTX (mode
);
1931 x
= gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
1932 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1937 /* Emit an integral vector conditional move. */
1940 ia64_expand_vecint_cmov (rtx operands
[])
1942 enum machine_mode mode
= GET_MODE (operands
[0]);
1943 enum rtx_code code
= GET_CODE (operands
[3]);
1947 cmp
= gen_reg_rtx (mode
);
1948 negate
= ia64_expand_vecint_compare (code
, mode
, cmp
,
1949 operands
[4], operands
[5]);
1951 ot
= operands
[1+negate
];
1952 of
= operands
[2-negate
];
1954 if (ot
== CONST0_RTX (mode
))
1956 if (of
== CONST0_RTX (mode
))
1958 emit_move_insn (operands
[0], ot
);
1962 x
= gen_rtx_NOT (mode
, cmp
);
1963 x
= gen_rtx_AND (mode
, x
, of
);
1964 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1966 else if (of
== CONST0_RTX (mode
))
1968 x
= gen_rtx_AND (mode
, cmp
, ot
);
1969 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1975 t
= gen_reg_rtx (mode
);
1976 x
= gen_rtx_AND (mode
, cmp
, operands
[1+negate
]);
1977 emit_insn (gen_rtx_SET (VOIDmode
, t
, x
));
1979 f
= gen_reg_rtx (mode
);
1980 x
= gen_rtx_NOT (mode
, cmp
);
1981 x
= gen_rtx_AND (mode
, x
, operands
[2-negate
]);
1982 emit_insn (gen_rtx_SET (VOIDmode
, f
, x
));
1984 x
= gen_rtx_IOR (mode
, t
, f
);
1985 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1989 /* Emit an integral vector min or max operation. Return true if all done. */
1992 ia64_expand_vecint_minmax (enum rtx_code code
, enum machine_mode mode
,
1997 /* These four combinations are supported directly. */
1998 if (mode
== V8QImode
&& (code
== UMIN
|| code
== UMAX
))
2000 if (mode
== V4HImode
&& (code
== SMIN
|| code
== SMAX
))
2003 /* This combination can be implemented with only saturating subtraction. */
2004 if (mode
== V4HImode
&& code
== UMAX
)
2006 rtx x
, tmp
= gen_reg_rtx (mode
);
2008 x
= gen_rtx_US_MINUS (mode
, operands
[1], operands
[2]);
2009 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, x
));
2011 emit_insn (gen_addv4hi3 (operands
[0], tmp
, operands
[2]));
2015 /* Everything else implemented via vector comparisons. */
2016 xops
[0] = operands
[0];
2017 xops
[4] = xops
[1] = operands
[1];
2018 xops
[5] = xops
[2] = operands
[2];
2037 xops
[3] = gen_rtx_fmt_ee (code
, VOIDmode
, operands
[1], operands
[2]);
2039 ia64_expand_vecint_cmov (xops
);
2043 /* The vectors LO and HI each contain N halves of a double-wide vector.
2044 Reassemble either the first N/2 or the second N/2 elements. */
2047 ia64_unpack_assemble (rtx out
, rtx lo
, rtx hi
, bool highp
)
2049 enum machine_mode vmode
= GET_MODE (lo
);
2050 unsigned int i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
2051 struct expand_vec_perm_d d
;
2054 d
.target
= gen_lowpart (vmode
, out
);
2055 d
.op0
= (TARGET_BIG_ENDIAN
? hi
: lo
);
2056 d
.op1
= (TARGET_BIG_ENDIAN
? lo
: hi
);
2059 d
.one_operand_p
= false;
2060 d
.testing_p
= false;
2062 high
= (highp
? nelt
/ 2 : 0);
2063 for (i
= 0; i
< nelt
/ 2; ++i
)
2065 d
.perm
[i
* 2] = i
+ high
;
2066 d
.perm
[i
* 2 + 1] = i
+ high
+ nelt
;
2069 ok
= ia64_expand_vec_perm_const_1 (&d
);
2073 /* Return a vector of the sign-extension of VEC. */
2076 ia64_unpack_sign (rtx vec
, bool unsignedp
)
2078 enum machine_mode mode
= GET_MODE (vec
);
2079 rtx zero
= CONST0_RTX (mode
);
2085 rtx sign
= gen_reg_rtx (mode
);
2088 neg
= ia64_expand_vecint_compare (LT
, mode
, sign
, vec
, zero
);
2095 /* Emit an integral vector unpack operation. */
2098 ia64_expand_unpack (rtx operands
[3], bool unsignedp
, bool highp
)
2100 rtx sign
= ia64_unpack_sign (operands
[1], unsignedp
);
2101 ia64_unpack_assemble (operands
[0], operands
[1], sign
, highp
);
2104 /* Emit an integral vector widening sum operations. */
2107 ia64_expand_widen_sum (rtx operands
[3], bool unsignedp
)
2109 enum machine_mode wmode
;
2112 sign
= ia64_unpack_sign (operands
[1], unsignedp
);
2114 wmode
= GET_MODE (operands
[0]);
2115 l
= gen_reg_rtx (wmode
);
2116 h
= gen_reg_rtx (wmode
);
2118 ia64_unpack_assemble (l
, operands
[1], sign
, false);
2119 ia64_unpack_assemble (h
, operands
[1], sign
, true);
2121 t
= expand_binop (wmode
, add_optab
, l
, operands
[2], NULL
, 0, OPTAB_DIRECT
);
2122 t
= expand_binop (wmode
, add_optab
, h
, t
, operands
[0], 0, OPTAB_DIRECT
);
2123 if (t
!= operands
[0])
2124 emit_move_insn (operands
[0], t
);
2127 /* Emit the appropriate sequence for a call. */
2130 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
2135 addr
= XEXP (addr
, 0);
2136 addr
= convert_memory_address (DImode
, addr
);
2137 b0
= gen_rtx_REG (DImode
, R_BR (0));
2139 /* ??? Should do this for functions known to bind local too. */
2140 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
2143 insn
= gen_sibcall_nogp (addr
);
2145 insn
= gen_call_nogp (addr
, b0
);
2147 insn
= gen_call_value_nogp (retval
, addr
, b0
);
2148 insn
= emit_call_insn (insn
);
2153 insn
= gen_sibcall_gp (addr
);
2155 insn
= gen_call_gp (addr
, b0
);
2157 insn
= gen_call_value_gp (retval
, addr
, b0
);
2158 insn
= emit_call_insn (insn
);
2160 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2164 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
2166 if (TARGET_ABI_OPEN_VMS
)
2167 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2168 gen_rtx_REG (DImode
, GR_REG (25)));
2172 reg_emitted (enum ia64_frame_regs r
)
2174 if (emitted_frame_related_regs
[r
] == 0)
2175 emitted_frame_related_regs
[r
] = current_frame_info
.r
[r
];
2177 gcc_assert (emitted_frame_related_regs
[r
] == current_frame_info
.r
[r
]);
2181 get_reg (enum ia64_frame_regs r
)
2184 return current_frame_info
.r
[r
];
2188 is_emitted (int regno
)
2192 for (r
= reg_fp
; r
< number_of_ia64_frame_regs
; r
++)
2193 if (emitted_frame_related_regs
[r
] == regno
)
2199 ia64_reload_gp (void)
2203 if (current_frame_info
.r
[reg_save_gp
])
2205 tmp
= gen_rtx_REG (DImode
, get_reg (reg_save_gp
));
2209 HOST_WIDE_INT offset
;
2212 offset
= (current_frame_info
.spill_cfa_off
2213 + current_frame_info
.spill_size
);
2214 if (frame_pointer_needed
)
2216 tmp
= hard_frame_pointer_rtx
;
2221 tmp
= stack_pointer_rtx
;
2222 offset
= current_frame_info
.total_size
- offset
;
2225 offset_r
= GEN_INT (offset
);
2226 if (satisfies_constraint_I (offset_r
))
2227 emit_insn (gen_adddi3 (pic_offset_table_rtx
, tmp
, offset_r
));
2230 emit_move_insn (pic_offset_table_rtx
, offset_r
);
2231 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
2232 pic_offset_table_rtx
, tmp
));
2235 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
2238 emit_move_insn (pic_offset_table_rtx
, tmp
);
2242 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
2243 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
2246 bool is_desc
= false;
2248 /* If we find we're calling through a register, then we're actually
2249 calling through a descriptor, so load up the values. */
2250 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
2255 /* ??? We are currently constrained to *not* use peep2, because
2256 we can legitimately change the global lifetime of the GP
2257 (in the form of killing where previously live). This is
2258 because a call through a descriptor doesn't use the previous
2259 value of the GP, while a direct call does, and we do not
2260 commit to either form until the split here.
2262 That said, this means that we lack precise life info for
2263 whether ADDR is dead after this call. This is not terribly
2264 important, since we can fix things up essentially for free
2265 with the POST_DEC below, but it's nice to not use it when we
2266 can immediately tell it's not necessary. */
2267 addr_dead_p
= ((noreturn_p
|| sibcall_p
2268 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
2270 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
2272 /* Load the code address into scratch_b. */
2273 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
2274 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2275 emit_move_insn (scratch_r
, tmp
);
2276 emit_move_insn (scratch_b
, scratch_r
);
2278 /* Load the GP address. If ADDR is not dead here, then we must
2279 revert the change made above via the POST_INCREMENT. */
2281 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
2284 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2285 emit_move_insn (pic_offset_table_rtx
, tmp
);
2292 insn
= gen_sibcall_nogp (addr
);
2294 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
2296 insn
= gen_call_nogp (addr
, retaddr
);
2297 emit_call_insn (insn
);
2299 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
2303 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2305 This differs from the generic code in that we know about the zero-extending
2306 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2307 also know that ld.acq+cmpxchg.rel equals a full barrier.
2309 The loop we want to generate looks like
2314 new_reg = cmp_reg op val;
2315 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2316 if (cmp_reg != old_reg)
2319 Note that we only do the plain load from memory once. Subsequent
2320 iterations use the value loaded by the compare-and-swap pattern. */
2323 ia64_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
2324 rtx old_dst
, rtx new_dst
, enum memmodel model
)
2326 enum machine_mode mode
= GET_MODE (mem
);
2327 rtx old_reg
, new_reg
, cmp_reg
, ar_ccv
, label
;
2328 enum insn_code icode
;
2330 /* Special case for using fetchadd. */
2331 if ((mode
== SImode
|| mode
== DImode
)
2332 && (code
== PLUS
|| code
== MINUS
)
2333 && fetchadd_operand (val
, mode
))
2336 val
= GEN_INT (-INTVAL (val
));
2339 old_dst
= gen_reg_rtx (mode
);
2343 case MEMMODEL_ACQ_REL
:
2344 case MEMMODEL_SEQ_CST
:
2345 emit_insn (gen_memory_barrier ());
2347 case MEMMODEL_RELAXED
:
2348 case MEMMODEL_ACQUIRE
:
2349 case MEMMODEL_CONSUME
:
2351 icode
= CODE_FOR_fetchadd_acq_si
;
2353 icode
= CODE_FOR_fetchadd_acq_di
;
2355 case MEMMODEL_RELEASE
:
2357 icode
= CODE_FOR_fetchadd_rel_si
;
2359 icode
= CODE_FOR_fetchadd_rel_di
;
2366 emit_insn (GEN_FCN (icode
) (old_dst
, mem
, val
));
2370 new_reg
= expand_simple_binop (mode
, PLUS
, old_dst
, val
, new_dst
,
2372 if (new_reg
!= new_dst
)
2373 emit_move_insn (new_dst
, new_reg
);
2378 /* Because of the volatile mem read, we get an ld.acq, which is the
2379 front half of the full barrier. The end half is the cmpxchg.rel.
2380 For relaxed and release memory models, we don't need this. But we
2381 also don't bother trying to prevent it either. */
2382 gcc_assert (model
== MEMMODEL_RELAXED
2383 || model
== MEMMODEL_RELEASE
2384 || MEM_VOLATILE_P (mem
));
2386 old_reg
= gen_reg_rtx (DImode
);
2387 cmp_reg
= gen_reg_rtx (DImode
);
2388 label
= gen_label_rtx ();
2392 val
= simplify_gen_subreg (DImode
, val
, mode
, 0);
2393 emit_insn (gen_extend_insn (cmp_reg
, mem
, DImode
, mode
, 1));
2396 emit_move_insn (cmp_reg
, mem
);
2400 ar_ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
2401 emit_move_insn (old_reg
, cmp_reg
);
2402 emit_move_insn (ar_ccv
, cmp_reg
);
2405 emit_move_insn (old_dst
, gen_lowpart (mode
, cmp_reg
));
2410 new_reg
= expand_simple_binop (DImode
, AND
, new_reg
, val
, NULL_RTX
,
2411 true, OPTAB_DIRECT
);
2412 new_reg
= expand_simple_unop (DImode
, code
, new_reg
, NULL_RTX
, true);
2415 new_reg
= expand_simple_binop (DImode
, code
, new_reg
, val
, NULL_RTX
,
2416 true, OPTAB_DIRECT
);
2419 new_reg
= gen_lowpart (mode
, new_reg
);
2421 emit_move_insn (new_dst
, new_reg
);
2425 case MEMMODEL_RELAXED
:
2426 case MEMMODEL_ACQUIRE
:
2427 case MEMMODEL_CONSUME
:
2430 case QImode
: icode
= CODE_FOR_cmpxchg_acq_qi
; break;
2431 case HImode
: icode
= CODE_FOR_cmpxchg_acq_hi
; break;
2432 case SImode
: icode
= CODE_FOR_cmpxchg_acq_si
; break;
2433 case DImode
: icode
= CODE_FOR_cmpxchg_acq_di
; break;
2439 case MEMMODEL_RELEASE
:
2440 case MEMMODEL_ACQ_REL
:
2441 case MEMMODEL_SEQ_CST
:
2444 case QImode
: icode
= CODE_FOR_cmpxchg_rel_qi
; break;
2445 case HImode
: icode
= CODE_FOR_cmpxchg_rel_hi
; break;
2446 case SImode
: icode
= CODE_FOR_cmpxchg_rel_si
; break;
2447 case DImode
: icode
= CODE_FOR_cmpxchg_rel_di
; break;
2457 emit_insn (GEN_FCN (icode
) (cmp_reg
, mem
, ar_ccv
, new_reg
));
2459 emit_cmp_and_jump_insns (cmp_reg
, old_reg
, NE
, NULL
, DImode
, true, label
);
2462 /* Begin the assembly file. */
2465 ia64_file_start (void)
2467 default_file_start ();
2468 emit_safe_across_calls ();
2472 emit_safe_across_calls (void)
2474 unsigned int rs
, re
;
2481 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
2485 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
2489 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
2493 fputc (',', asm_out_file
);
2495 fprintf (asm_out_file
, "p%u", rs
);
2497 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
2501 fputc ('\n', asm_out_file
);
2504 /* Globalize a declaration. */
2507 ia64_globalize_decl_name (FILE * stream
, tree decl
)
2509 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2510 tree version_attr
= lookup_attribute ("version_id", DECL_ATTRIBUTES (decl
));
2513 tree v
= TREE_VALUE (TREE_VALUE (version_attr
));
2514 const char *p
= TREE_STRING_POINTER (v
);
2515 fprintf (stream
, "\t.alias %s#, \"%s{%s}\"\n", name
, name
, p
);
2517 targetm
.asm_out
.globalize_label (stream
, name
);
2518 if (TREE_CODE (decl
) == FUNCTION_DECL
)
2519 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "function");
2522 /* Helper function for ia64_compute_frame_size: find an appropriate general
2523 register to spill some special register to. SPECIAL_SPILL_MASK contains
2524 bits in GR0 to GR31 that have already been allocated by this routine.
2525 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2528 find_gr_spill (enum ia64_frame_regs r
, int try_locals
)
2532 if (emitted_frame_related_regs
[r
] != 0)
2534 regno
= emitted_frame_related_regs
[r
];
2535 if (regno
>= LOC_REG (0) && regno
< LOC_REG (80 - frame_pointer_needed
)
2536 && current_frame_info
.n_local_regs
< regno
- LOC_REG (0) + 1)
2537 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2538 else if (crtl
->is_leaf
2539 && regno
>= GR_REG (1) && regno
<= GR_REG (31))
2540 current_frame_info
.gr_used_mask
|= 1 << regno
;
2545 /* If this is a leaf function, first try an otherwise unused
2546 call-clobbered register. */
2549 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2550 if (! df_regs_ever_live_p (regno
)
2551 && call_used_regs
[regno
]
2552 && ! fixed_regs
[regno
]
2553 && ! global_regs
[regno
]
2554 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0
2555 && ! is_emitted (regno
))
2557 current_frame_info
.gr_used_mask
|= 1 << regno
;
2564 regno
= current_frame_info
.n_local_regs
;
2565 /* If there is a frame pointer, then we can't use loc79, because
2566 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2567 reg_name switching code in ia64_expand_prologue. */
2568 while (regno
< (80 - frame_pointer_needed
))
2569 if (! is_emitted (LOC_REG (regno
++)))
2571 current_frame_info
.n_local_regs
= regno
;
2572 return LOC_REG (regno
- 1);
2576 /* Failed to find a general register to spill to. Must use stack. */
2580 /* In order to make for nice schedules, we try to allocate every temporary
2581 to a different register. We must of course stay away from call-saved,
2582 fixed, and global registers. We must also stay away from registers
2583 allocated in current_frame_info.gr_used_mask, since those include regs
2584 used all through the prologue.
2586 Any register allocated here must be used immediately. The idea is to
2587 aid scheduling, not to solve data flow problems. */
2589 static int last_scratch_gr_reg
;
2592 next_scratch_gr_reg (void)
2596 for (i
= 0; i
< 32; ++i
)
2598 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
2599 if (call_used_regs
[regno
]
2600 && ! fixed_regs
[regno
]
2601 && ! global_regs
[regno
]
2602 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
2604 last_scratch_gr_reg
= regno
;
2609 /* There must be _something_ available. */
2613 /* Helper function for ia64_compute_frame_size, called through
2614 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2617 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2619 unsigned int regno
= REGNO (reg
);
2622 unsigned int i
, n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2623 for (i
= 0; i
< n
; ++i
)
2624 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2629 /* Returns the number of bytes offset between the frame pointer and the stack
2630 pointer for the current function. SIZE is the number of bytes of space
2631 needed for local variables. */
2634 ia64_compute_frame_size (HOST_WIDE_INT size
)
2636 HOST_WIDE_INT total_size
;
2637 HOST_WIDE_INT spill_size
= 0;
2638 HOST_WIDE_INT extra_spill_size
= 0;
2639 HOST_WIDE_INT pretend_args_size
;
2642 int spilled_gr_p
= 0;
2643 int spilled_fr_p
= 0;
2649 if (current_frame_info
.initialized
)
2652 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2653 CLEAR_HARD_REG_SET (mask
);
2655 /* Don't allocate scratches to the return register. */
2656 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2658 /* Don't allocate scratches to the EH scratch registers. */
2659 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2660 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2661 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2662 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2664 /* Static stack checking uses r2 and r3. */
2665 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
2666 current_frame_info
.gr_used_mask
|= 0xc;
2668 /* Find the size of the register stack frame. We have only 80 local
2669 registers, because we reserve 8 for the inputs and 8 for the
2672 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2673 since we'll be adjusting that down later. */
2674 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2675 for (; regno
>= LOC_REG (0); regno
--)
2676 if (df_regs_ever_live_p (regno
) && !is_emitted (regno
))
2678 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2680 /* For functions marked with the syscall_linkage attribute, we must mark
2681 all eight input registers as in use, so that locals aren't visible to
2684 if (cfun
->machine
->n_varargs
> 0
2685 || lookup_attribute ("syscall_linkage",
2686 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2687 current_frame_info
.n_input_regs
= 8;
2690 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2691 if (df_regs_ever_live_p (regno
))
2693 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2696 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2697 if (df_regs_ever_live_p (regno
))
2699 i
= regno
- OUT_REG (0) + 1;
2701 #ifndef PROFILE_HOOK
2702 /* When -p profiling, we need one output register for the mcount argument.
2703 Likewise for -a profiling for the bb_init_func argument. For -ax
2704 profiling, we need two output registers for the two bb_init_trace_func
2709 current_frame_info
.n_output_regs
= i
;
2711 /* ??? No rotating register support yet. */
2712 current_frame_info
.n_rotate_regs
= 0;
2714 /* Discover which registers need spilling, and how much room that
2715 will take. Begin with floating point and general registers,
2716 which will always wind up on the stack. */
2718 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2719 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2721 SET_HARD_REG_BIT (mask
, regno
);
2727 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2728 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2730 SET_HARD_REG_BIT (mask
, regno
);
2736 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2737 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2739 SET_HARD_REG_BIT (mask
, regno
);
2744 /* Now come all special registers that might get saved in other
2745 general registers. */
2747 if (frame_pointer_needed
)
2749 current_frame_info
.r
[reg_fp
] = find_gr_spill (reg_fp
, 1);
2750 /* If we did not get a register, then we take LOC79. This is guaranteed
2751 to be free, even if regs_ever_live is already set, because this is
2752 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2753 as we don't count loc79 above. */
2754 if (current_frame_info
.r
[reg_fp
] == 0)
2756 current_frame_info
.r
[reg_fp
] = LOC_REG (79);
2757 current_frame_info
.n_local_regs
= LOC_REG (79) - LOC_REG (0) + 1;
2761 if (! crtl
->is_leaf
)
2763 /* Emit a save of BR0 if we call other functions. Do this even
2764 if this function doesn't return, as EH depends on this to be
2765 able to unwind the stack. */
2766 SET_HARD_REG_BIT (mask
, BR_REG (0));
2768 current_frame_info
.r
[reg_save_b0
] = find_gr_spill (reg_save_b0
, 1);
2769 if (current_frame_info
.r
[reg_save_b0
] == 0)
2771 extra_spill_size
+= 8;
2775 /* Similarly for ar.pfs. */
2776 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2777 current_frame_info
.r
[reg_save_ar_pfs
] = find_gr_spill (reg_save_ar_pfs
, 1);
2778 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2780 extra_spill_size
+= 8;
2784 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2785 registers are clobbered, so we fall back to the stack. */
2786 current_frame_info
.r
[reg_save_gp
]
2787 = (cfun
->calls_setjmp
? 0 : find_gr_spill (reg_save_gp
, 1));
2788 if (current_frame_info
.r
[reg_save_gp
] == 0)
2790 SET_HARD_REG_BIT (mask
, GR_REG (1));
2797 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs
[BR_REG (0)])
2799 SET_HARD_REG_BIT (mask
, BR_REG (0));
2800 extra_spill_size
+= 8;
2804 if (df_regs_ever_live_p (AR_PFS_REGNUM
))
2806 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2807 current_frame_info
.r
[reg_save_ar_pfs
]
2808 = find_gr_spill (reg_save_ar_pfs
, 1);
2809 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2811 extra_spill_size
+= 8;
2817 /* Unwind descriptor hackery: things are most efficient if we allocate
2818 consecutive GR save registers for RP, PFS, FP in that order. However,
2819 it is absolutely critical that FP get the only hard register that's
2820 guaranteed to be free, so we allocated it first. If all three did
2821 happen to be allocated hard regs, and are consecutive, rearrange them
2822 into the preferred order now.
2824 If we have already emitted code for any of those registers,
2825 then it's already too late to change. */
2826 min_regno
= MIN (current_frame_info
.r
[reg_fp
],
2827 MIN (current_frame_info
.r
[reg_save_b0
],
2828 current_frame_info
.r
[reg_save_ar_pfs
]));
2829 max_regno
= MAX (current_frame_info
.r
[reg_fp
],
2830 MAX (current_frame_info
.r
[reg_save_b0
],
2831 current_frame_info
.r
[reg_save_ar_pfs
]));
2833 && min_regno
+ 2 == max_regno
2834 && (current_frame_info
.r
[reg_fp
] == min_regno
+ 1
2835 || current_frame_info
.r
[reg_save_b0
] == min_regno
+ 1
2836 || current_frame_info
.r
[reg_save_ar_pfs
] == min_regno
+ 1)
2837 && (emitted_frame_related_regs
[reg_save_b0
] == 0
2838 || emitted_frame_related_regs
[reg_save_b0
] == min_regno
)
2839 && (emitted_frame_related_regs
[reg_save_ar_pfs
] == 0
2840 || emitted_frame_related_regs
[reg_save_ar_pfs
] == min_regno
+ 1)
2841 && (emitted_frame_related_regs
[reg_fp
] == 0
2842 || emitted_frame_related_regs
[reg_fp
] == min_regno
+ 2))
2844 current_frame_info
.r
[reg_save_b0
] = min_regno
;
2845 current_frame_info
.r
[reg_save_ar_pfs
] = min_regno
+ 1;
2846 current_frame_info
.r
[reg_fp
] = min_regno
+ 2;
2849 /* See if we need to store the predicate register block. */
2850 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2851 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2853 if (regno
<= PR_REG (63))
2855 SET_HARD_REG_BIT (mask
, PR_REG (0));
2856 current_frame_info
.r
[reg_save_pr
] = find_gr_spill (reg_save_pr
, 1);
2857 if (current_frame_info
.r
[reg_save_pr
] == 0)
2859 extra_spill_size
+= 8;
2863 /* ??? Mark them all as used so that register renaming and such
2864 are free to use them. */
2865 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2866 df_set_regs_ever_live (regno
, true);
2869 /* If we're forced to use st8.spill, we're forced to save and restore
2870 ar.unat as well. The check for existing liveness allows inline asm
2871 to touch ar.unat. */
2872 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2873 || df_regs_ever_live_p (AR_UNAT_REGNUM
))
2875 df_set_regs_ever_live (AR_UNAT_REGNUM
, true);
2876 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2877 current_frame_info
.r
[reg_save_ar_unat
]
2878 = find_gr_spill (reg_save_ar_unat
, spill_size
== 0);
2879 if (current_frame_info
.r
[reg_save_ar_unat
] == 0)
2881 extra_spill_size
+= 8;
2886 if (df_regs_ever_live_p (AR_LC_REGNUM
))
2888 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2889 current_frame_info
.r
[reg_save_ar_lc
]
2890 = find_gr_spill (reg_save_ar_lc
, spill_size
== 0);
2891 if (current_frame_info
.r
[reg_save_ar_lc
] == 0)
2893 extra_spill_size
+= 8;
2898 /* If we have an odd number of words of pretend arguments written to
2899 the stack, then the FR save area will be unaligned. We round the
2900 size of this area up to keep things 16 byte aligned. */
2902 pretend_args_size
= IA64_STACK_ALIGN (crtl
->args
.pretend_args_size
);
2904 pretend_args_size
= crtl
->args
.pretend_args_size
;
2906 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2907 + crtl
->outgoing_args_size
);
2908 total_size
= IA64_STACK_ALIGN (total_size
);
2910 /* We always use the 16-byte scratch area provided by the caller, but
2911 if we are a leaf function, there's no one to which we need to provide
2912 a scratch area. However, if the function allocates dynamic stack space,
2913 the dynamic offset is computed early and contains STACK_POINTER_OFFSET,
2914 so we need to cope. */
2915 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
2916 total_size
= MAX (0, total_size
- 16);
2918 current_frame_info
.total_size
= total_size
;
2919 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2920 current_frame_info
.spill_size
= spill_size
;
2921 current_frame_info
.extra_spill_size
= extra_spill_size
;
2922 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2923 current_frame_info
.n_spilled
= n_spilled
;
2924 current_frame_info
.initialized
= reload_completed
;
2927 /* Worker function for TARGET_CAN_ELIMINATE. */
2930 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2932 return (to
== BR_REG (0) ? crtl
->is_leaf
: true);
2935 /* Compute the initial difference between the specified pair of registers. */
2938 ia64_initial_elimination_offset (int from
, int to
)
2940 HOST_WIDE_INT offset
;
2942 ia64_compute_frame_size (get_frame_size ());
2945 case FRAME_POINTER_REGNUM
:
2948 case HARD_FRAME_POINTER_REGNUM
:
2949 offset
= -current_frame_info
.total_size
;
2950 if (!crtl
->is_leaf
|| cfun
->calls_alloca
)
2951 offset
+= 16 + crtl
->outgoing_args_size
;
2954 case STACK_POINTER_REGNUM
:
2956 if (!crtl
->is_leaf
|| cfun
->calls_alloca
)
2957 offset
+= 16 + crtl
->outgoing_args_size
;
2965 case ARG_POINTER_REGNUM
:
2966 /* Arguments start above the 16 byte save area, unless stdarg
2967 in which case we store through the 16 byte save area. */
2970 case HARD_FRAME_POINTER_REGNUM
:
2971 offset
= 16 - crtl
->args
.pretend_args_size
;
2974 case STACK_POINTER_REGNUM
:
2975 offset
= (current_frame_info
.total_size
2976 + 16 - crtl
->args
.pretend_args_size
);
2991 /* If there are more than a trivial number of register spills, we use
2992 two interleaved iterators so that we can get two memory references
2995 In order to simplify things in the prologue and epilogue expanders,
2996 we use helper functions to fix up the memory references after the
2997 fact with the appropriate offsets to a POST_MODIFY memory mode.
2998 The following data structure tracks the state of the two iterators
2999 while insns are being emitted. */
3001 struct spill_fill_data
3003 rtx init_after
; /* point at which to emit initializations */
3004 rtx init_reg
[2]; /* initial base register */
3005 rtx iter_reg
[2]; /* the iterator registers */
3006 rtx
*prev_addr
[2]; /* address of last memory use */
3007 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
3008 HOST_WIDE_INT prev_off
[2]; /* last offset */
3009 int n_iter
; /* number of iterators in use */
3010 int next_iter
; /* next iterator to use */
3011 unsigned int save_gr_used_mask
;
3014 static struct spill_fill_data spill_fill_data
;
3017 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
3021 spill_fill_data
.init_after
= get_last_insn ();
3022 spill_fill_data
.init_reg
[0] = init_reg
;
3023 spill_fill_data
.init_reg
[1] = init_reg
;
3024 spill_fill_data
.prev_addr
[0] = NULL
;
3025 spill_fill_data
.prev_addr
[1] = NULL
;
3026 spill_fill_data
.prev_insn
[0] = NULL
;
3027 spill_fill_data
.prev_insn
[1] = NULL
;
3028 spill_fill_data
.prev_off
[0] = cfa_off
;
3029 spill_fill_data
.prev_off
[1] = cfa_off
;
3030 spill_fill_data
.next_iter
= 0;
3031 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
3033 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
3034 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
3036 int regno
= next_scratch_gr_reg ();
3037 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
3038 current_frame_info
.gr_used_mask
|= 1 << regno
;
3043 finish_spill_pointers (void)
3045 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
3049 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
3051 int iter
= spill_fill_data
.next_iter
;
3052 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
3053 rtx disp_rtx
= GEN_INT (disp
);
3056 if (spill_fill_data
.prev_addr
[iter
])
3058 if (satisfies_constraint_N (disp_rtx
))
3060 *spill_fill_data
.prev_addr
[iter
]
3061 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
3062 gen_rtx_PLUS (DImode
,
3063 spill_fill_data
.iter_reg
[iter
],
3065 add_reg_note (spill_fill_data
.prev_insn
[iter
],
3066 REG_INC
, spill_fill_data
.iter_reg
[iter
]);
3070 /* ??? Could use register post_modify for loads. */
3071 if (!satisfies_constraint_I (disp_rtx
))
3073 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
3074 emit_move_insn (tmp
, disp_rtx
);
3077 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
3078 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
3081 /* Micro-optimization: if we've created a frame pointer, it's at
3082 CFA 0, which may allow the real iterator to be initialized lower,
3083 slightly increasing parallelism. Also, if there are few saves
3084 it may eliminate the iterator entirely. */
3086 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
3087 && frame_pointer_needed
)
3089 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
3090 set_mem_alias_set (mem
, get_varargs_alias_set ());
3098 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
3099 spill_fill_data
.init_reg
[iter
]);
3104 if (!satisfies_constraint_I (disp_rtx
))
3106 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
3107 emit_move_insn (tmp
, disp_rtx
);
3111 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
3112 spill_fill_data
.init_reg
[iter
],
3119 /* Careful for being the first insn in a sequence. */
3120 if (spill_fill_data
.init_after
)
3121 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
3124 rtx first
= get_insns ();
3126 insn
= emit_insn_before (seq
, first
);
3128 insn
= emit_insn (seq
);
3130 spill_fill_data
.init_after
= insn
;
3133 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
3135 /* ??? Not all of the spills are for varargs, but some of them are.
3136 The rest of the spills belong in an alias set of their own. But
3137 it doesn't actually hurt to include them here. */
3138 set_mem_alias_set (mem
, get_varargs_alias_set ());
3140 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
3141 spill_fill_data
.prev_off
[iter
] = cfa_off
;
3143 if (++iter
>= spill_fill_data
.n_iter
)
3145 spill_fill_data
.next_iter
= iter
;
3151 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
3154 int iter
= spill_fill_data
.next_iter
;
3157 mem
= spill_restore_mem (reg
, cfa_off
);
3158 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
3159 spill_fill_data
.prev_insn
[iter
] = insn
;
3166 RTX_FRAME_RELATED_P (insn
) = 1;
3168 /* Don't even pretend that the unwind code can intuit its way
3169 through a pair of interleaved post_modify iterators. Just
3170 provide the correct answer. */
3172 if (frame_pointer_needed
)
3174 base
= hard_frame_pointer_rtx
;
3179 base
= stack_pointer_rtx
;
3180 off
= current_frame_info
.total_size
- cfa_off
;
3183 add_reg_note (insn
, REG_CFA_OFFSET
,
3184 gen_rtx_SET (VOIDmode
,
3185 gen_rtx_MEM (GET_MODE (reg
),
3186 plus_constant (Pmode
,
3193 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
3195 int iter
= spill_fill_data
.next_iter
;
3198 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
3199 GEN_INT (cfa_off
)));
3200 spill_fill_data
.prev_insn
[iter
] = insn
;
3203 /* Wrapper functions that discards the CONST_INT spill offset. These
3204 exist so that we can give gr_spill/gr_fill the offset they need and
3205 use a consistent function interface. */
3208 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3210 return gen_movdi (dest
, src
);
3214 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3216 return gen_fr_spill (dest
, src
);
3220 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3222 return gen_fr_restore (dest
, src
);
3225 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3227 /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */
3228 #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0)
3230 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
3231 inclusive. These are offsets from the current stack pointer. BS_SIZE
3232 is the size of the backing store. ??? This clobbers r2 and r3. */
3235 ia64_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
,
3238 rtx r2
= gen_rtx_REG (Pmode
, GR_REG (2));
3239 rtx r3
= gen_rtx_REG (Pmode
, GR_REG (3));
3240 rtx p6
= gen_rtx_REG (BImode
, PR_REG (6));
3242 /* On the IA-64 there is a second stack in memory, namely the Backing Store
3243 of the Register Stack Engine. We also need to probe it after checking
3244 that the 2 stacks don't overlap. */
3245 emit_insn (gen_bsp_value (r3
));
3246 emit_move_insn (r2
, GEN_INT (-(first
+ size
)));
3248 /* Compare current value of BSP and SP registers. */
3249 emit_insn (gen_rtx_SET (VOIDmode
, p6
,
3250 gen_rtx_fmt_ee (LTU
, BImode
,
3251 r3
, stack_pointer_rtx
)));
3253 /* Compute the address of the probe for the Backing Store (which grows
3254 towards higher addresses). We probe only at the first offset of
3255 the next page because some OS (eg Linux/ia64) only extend the
3256 backing store when this specific address is hit (but generate a SEGV
3257 on other address). Page size is the worst case (4KB). The reserve
3258 size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough.
3259 Also compute the address of the last probe for the memory stack
3260 (which grows towards lower addresses). */
3261 emit_insn (gen_rtx_SET (VOIDmode
, r3
, plus_constant (Pmode
, r3
, 4095)));
3262 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3263 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3265 /* Compare them and raise SEGV if the former has topped the latter. */
3266 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
3267 gen_rtx_fmt_ee (NE
, VOIDmode
, p6
, const0_rtx
),
3268 gen_rtx_SET (VOIDmode
, p6
,
3269 gen_rtx_fmt_ee (GEU
, BImode
,
3271 emit_insn (gen_rtx_SET (VOIDmode
,
3272 gen_rtx_ZERO_EXTRACT (DImode
, r3
, GEN_INT (12),
3275 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
3276 gen_rtx_fmt_ee (NE
, VOIDmode
, p6
, const0_rtx
),
3277 gen_rtx_TRAP_IF (VOIDmode
, const1_rtx
,
3280 /* Probe the Backing Store if necessary. */
3282 emit_stack_probe (r3
);
3284 /* Probe the memory stack if necessary. */
3288 /* See if we have a constant small number of probes to generate. If so,
3289 that's the easy case. */
3290 else if (size
<= PROBE_INTERVAL
)
3291 emit_stack_probe (r2
);
3293 /* The run-time loop is made up of 8 insns in the generic case while this
3294 compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */
3295 else if (size
<= 4 * PROBE_INTERVAL
)
3299 emit_move_insn (r2
, GEN_INT (-(first
+ PROBE_INTERVAL
)));
3300 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3301 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3302 emit_stack_probe (r2
);
3304 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3305 it exceeds SIZE. If only two probes are needed, this will not
3306 generate any code. Then probe at FIRST + SIZE. */
3307 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
3309 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3310 plus_constant (Pmode
, r2
, -PROBE_INTERVAL
)));
3311 emit_stack_probe (r2
);
3314 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3315 plus_constant (Pmode
, r2
,
3316 (i
- PROBE_INTERVAL
) - size
)));
3317 emit_stack_probe (r2
);
3320 /* Otherwise, do the same as above, but in a loop. Note that we must be
3321 extra careful with variables wrapping around because we might be at
3322 the very top (or the very bottom) of the address space and we have
3323 to be able to handle this case properly; in particular, we use an
3324 equality test for the loop condition. */
3327 HOST_WIDE_INT rounded_size
;
3329 emit_move_insn (r2
, GEN_INT (-first
));
3332 /* Step 1: round SIZE to the previous multiple of the interval. */
3334 rounded_size
= size
& -PROBE_INTERVAL
;
3337 /* Step 2: compute initial and final value of the loop counter. */
3339 /* TEST_ADDR = SP + FIRST. */
3340 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3341 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3343 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3344 if (rounded_size
> (1 << 21))
3346 emit_move_insn (r3
, GEN_INT (-rounded_size
));
3347 emit_insn (gen_rtx_SET (VOIDmode
, r3
, gen_rtx_PLUS (Pmode
, r2
, r3
)));
3350 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
3351 gen_rtx_PLUS (Pmode
, r2
,
3352 GEN_INT (-rounded_size
))));
3357 while (TEST_ADDR != LAST_ADDR)
3359 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3363 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3364 until it is equal to ROUNDED_SIZE. */
3366 emit_insn (gen_probe_stack_range (r2
, r2
, r3
));
3369 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3370 that SIZE is equal to ROUNDED_SIZE. */
3372 /* TEMP = SIZE - ROUNDED_SIZE. */
3373 if (size
!= rounded_size
)
3375 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3376 plus_constant (Pmode
, r2
,
3377 rounded_size
- size
)));
3378 emit_stack_probe (r2
);
3382 /* Make sure nothing is scheduled before we are done. */
3383 emit_insn (gen_blockage ());
3386 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3387 absolute addresses. */
3390 output_probe_stack_range (rtx reg1
, rtx reg2
)
3392 static int labelno
= 0;
3393 char loop_lab
[32], end_lab
[32];
3396 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
3397 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
3399 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
3401 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
3404 xops
[2] = gen_rtx_REG (BImode
, PR_REG (6));
3405 output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops
);
3406 fprintf (asm_out_file
, "\t(%s) br.cond.dpnt ", reg_names
[REGNO (xops
[2])]);
3407 assemble_name_raw (asm_out_file
, end_lab
);
3408 fputc ('\n', asm_out_file
);
3410 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3411 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
3412 output_asm_insn ("addl %0 = %1, %0", xops
);
3413 fputs ("\t;;\n", asm_out_file
);
3415 /* Probe at TEST_ADDR and branch. */
3416 output_asm_insn ("probe.w.fault %0, 0", xops
);
3417 fprintf (asm_out_file
, "\tbr ");
3418 assemble_name_raw (asm_out_file
, loop_lab
);
3419 fputc ('\n', asm_out_file
);
3421 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
3426 /* Called after register allocation to add any instructions needed for the
3427 prologue. Using a prologue insn is favored compared to putting all of the
3428 instructions in output_function_prologue(), since it allows the scheduler
3429 to intermix instructions with the saves of the caller saved registers. In
3430 some cases, it might be necessary to emit a barrier instruction as the last
3431 insn to prevent such scheduling.
3433 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3434 so that the debug info generation code can handle them properly.
3436 The register save area is laid out like so:
3438 [ varargs spill area ]
3439 [ fr register spill area ]
3440 [ br register spill area ]
3441 [ ar register spill area ]
3442 [ pr register spill area ]
3443 [ gr register spill area ] */
3445 /* ??? Get inefficient code when the frame size is larger than can fit in an
3446 adds instruction. */
3449 ia64_expand_prologue (void)
3451 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
3452 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
3455 ia64_compute_frame_size (get_frame_size ());
3456 last_scratch_gr_reg
= 15;
3458 if (flag_stack_usage_info
)
3459 current_function_static_stack_size
= current_frame_info
.total_size
;
3461 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
3463 HOST_WIDE_INT size
= current_frame_info
.total_size
;
3464 int bs_size
= BACKING_STORE_SIZE (current_frame_info
.n_input_regs
3465 + current_frame_info
.n_local_regs
);
3467 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
3469 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
3470 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
,
3471 size
- STACK_CHECK_PROTECT
,
3473 else if (size
+ bs_size
> STACK_CHECK_PROTECT
)
3474 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
, 0, bs_size
);
3476 else if (size
+ bs_size
> 0)
3477 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
, bs_size
);
3482 fprintf (dump_file
, "ia64 frame related registers "
3483 "recorded in current_frame_info.r[]:\n");
3484 #define PRINTREG(a) if (current_frame_info.r[a]) \
3485 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3487 PRINTREG(reg_save_b0
);
3488 PRINTREG(reg_save_pr
);
3489 PRINTREG(reg_save_ar_pfs
);
3490 PRINTREG(reg_save_ar_unat
);
3491 PRINTREG(reg_save_ar_lc
);
3492 PRINTREG(reg_save_gp
);
3496 /* If there is no epilogue, then we don't need some prologue insns.
3497 We need to avoid emitting the dead prologue insns, because flow
3498 will complain about them. */
3504 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
)
3505 if ((e
->flags
& EDGE_FAKE
) == 0
3506 && (e
->flags
& EDGE_FALLTHRU
) != 0)
3508 epilogue_p
= (e
!= NULL
);
3513 /* Set the local, input, and output register names. We need to do this
3514 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3515 half. If we use in/loc/out register names, then we get assembler errors
3516 in crtn.S because there is no alloc insn or regstk directive in there. */
3517 if (! TARGET_REG_NAMES
)
3519 int inputs
= current_frame_info
.n_input_regs
;
3520 int locals
= current_frame_info
.n_local_regs
;
3521 int outputs
= current_frame_info
.n_output_regs
;
3523 for (i
= 0; i
< inputs
; i
++)
3524 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
3525 for (i
= 0; i
< locals
; i
++)
3526 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
3527 for (i
= 0; i
< outputs
; i
++)
3528 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
3531 /* Set the frame pointer register name. The regnum is logically loc79,
3532 but of course we'll not have allocated that many locals. Rather than
3533 worrying about renumbering the existing rtxs, we adjust the name. */
3534 /* ??? This code means that we can never use one local register when
3535 there is a frame pointer. loc79 gets wasted in this case, as it is
3536 renamed to a register that will never be used. See also the try_locals
3537 code in find_gr_spill. */
3538 if (current_frame_info
.r
[reg_fp
])
3540 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3541 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3542 = reg_names
[current_frame_info
.r
[reg_fp
]];
3543 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
3546 /* We don't need an alloc instruction if we've used no outputs or locals. */
3547 if (current_frame_info
.n_local_regs
== 0
3548 && current_frame_info
.n_output_regs
== 0
3549 && current_frame_info
.n_input_regs
<= crtl
->args
.info
.int_regs
3550 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3552 /* If there is no alloc, but there are input registers used, then we
3553 need a .regstk directive. */
3554 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
3555 ar_pfs_save_reg
= NULL_RTX
;
3559 current_frame_info
.need_regstk
= 0;
3561 if (current_frame_info
.r
[reg_save_ar_pfs
])
3563 regno
= current_frame_info
.r
[reg_save_ar_pfs
];
3564 reg_emitted (reg_save_ar_pfs
);
3567 regno
= next_scratch_gr_reg ();
3568 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
3570 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
3571 GEN_INT (current_frame_info
.n_input_regs
),
3572 GEN_INT (current_frame_info
.n_local_regs
),
3573 GEN_INT (current_frame_info
.n_output_regs
),
3574 GEN_INT (current_frame_info
.n_rotate_regs
)));
3575 if (current_frame_info
.r
[reg_save_ar_pfs
])
3577 RTX_FRAME_RELATED_P (insn
) = 1;
3578 add_reg_note (insn
, REG_CFA_REGISTER
,
3579 gen_rtx_SET (VOIDmode
,
3581 gen_rtx_REG (DImode
, AR_PFS_REGNUM
)));
3585 /* Set up frame pointer, stack pointer, and spill iterators. */
3587 n_varargs
= cfun
->machine
->n_varargs
;
3588 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
3589 stack_pointer_rtx
, 0);
3591 if (frame_pointer_needed
)
3593 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3594 RTX_FRAME_RELATED_P (insn
) = 1;
3596 /* Force the unwind info to recognize this as defining a new CFA,
3597 rather than some temp register setup. */
3598 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL_RTX
);
3601 if (current_frame_info
.total_size
!= 0)
3603 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
3606 if (satisfies_constraint_I (frame_size_rtx
))
3607 offset
= frame_size_rtx
;
3610 regno
= next_scratch_gr_reg ();
3611 offset
= gen_rtx_REG (DImode
, regno
);
3612 emit_move_insn (offset
, frame_size_rtx
);
3615 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
3616 stack_pointer_rtx
, offset
));
3618 if (! frame_pointer_needed
)
3620 RTX_FRAME_RELATED_P (insn
) = 1;
3621 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3622 gen_rtx_SET (VOIDmode
,
3624 gen_rtx_PLUS (DImode
,
3629 /* ??? At this point we must generate a magic insn that appears to
3630 modify the stack pointer, the frame pointer, and all spill
3631 iterators. This would allow the most scheduling freedom. For
3632 now, just hard stop. */
3633 emit_insn (gen_blockage ());
3636 /* Must copy out ar.unat before doing any integer spills. */
3637 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3639 if (current_frame_info
.r
[reg_save_ar_unat
])
3642 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3643 reg_emitted (reg_save_ar_unat
);
3647 alt_regno
= next_scratch_gr_reg ();
3648 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3649 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3652 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3653 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
3654 if (current_frame_info
.r
[reg_save_ar_unat
])
3656 RTX_FRAME_RELATED_P (insn
) = 1;
3657 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3660 /* Even if we're not going to generate an epilogue, we still
3661 need to save the register so that EH works. */
3662 if (! epilogue_p
&& current_frame_info
.r
[reg_save_ar_unat
])
3663 emit_insn (gen_prologue_use (ar_unat_save_reg
));
3666 ar_unat_save_reg
= NULL_RTX
;
3668 /* Spill all varargs registers. Do this before spilling any GR registers,
3669 since we want the UNAT bits for the GR registers to override the UNAT
3670 bits from varargs, which we don't care about. */
3673 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
3675 reg
= gen_rtx_REG (DImode
, regno
);
3676 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
3679 /* Locate the bottom of the register save area. */
3680 cfa_off
= (current_frame_info
.spill_cfa_off
3681 + current_frame_info
.spill_size
3682 + current_frame_info
.extra_spill_size
);
3684 /* Save the predicate register block either in a register or in memory. */
3685 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3687 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3688 if (current_frame_info
.r
[reg_save_pr
] != 0)
3690 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3691 reg_emitted (reg_save_pr
);
3692 insn
= emit_move_insn (alt_reg
, reg
);
3694 /* ??? Denote pr spill/fill by a DImode move that modifies all
3695 64 hard registers. */
3696 RTX_FRAME_RELATED_P (insn
) = 1;
3697 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3699 /* Even if we're not going to generate an epilogue, we still
3700 need to save the register so that EH works. */
3702 emit_insn (gen_prologue_use (alt_reg
));
3706 alt_regno
= next_scratch_gr_reg ();
3707 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3708 insn
= emit_move_insn (alt_reg
, reg
);
3709 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3714 /* Handle AR regs in numerical order. All of them get special handling. */
3715 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
3716 && current_frame_info
.r
[reg_save_ar_unat
] == 0)
3718 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3719 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
3723 /* The alloc insn already copied ar.pfs into a general register. The
3724 only thing we have to do now is copy that register to a stack slot
3725 if we'd not allocated a local register for the job. */
3726 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
3727 && current_frame_info
.r
[reg_save_ar_pfs
] == 0)
3729 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3730 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
3734 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3736 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3737 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3739 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3740 reg_emitted (reg_save_ar_lc
);
3741 insn
= emit_move_insn (alt_reg
, reg
);
3742 RTX_FRAME_RELATED_P (insn
) = 1;
3743 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3745 /* Even if we're not going to generate an epilogue, we still
3746 need to save the register so that EH works. */
3748 emit_insn (gen_prologue_use (alt_reg
));
3752 alt_regno
= next_scratch_gr_reg ();
3753 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3754 emit_move_insn (alt_reg
, reg
);
3755 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3760 /* Save the return pointer. */
3761 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3763 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3764 if (current_frame_info
.r
[reg_save_b0
] != 0)
3766 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3767 reg_emitted (reg_save_b0
);
3768 insn
= emit_move_insn (alt_reg
, reg
);
3769 RTX_FRAME_RELATED_P (insn
) = 1;
3770 add_reg_note (insn
, REG_CFA_REGISTER
,
3771 gen_rtx_SET (VOIDmode
, alt_reg
, pc_rtx
));
3773 /* Even if we're not going to generate an epilogue, we still
3774 need to save the register so that EH works. */
3776 emit_insn (gen_prologue_use (alt_reg
));
3780 alt_regno
= next_scratch_gr_reg ();
3781 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3782 emit_move_insn (alt_reg
, reg
);
3783 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3788 if (current_frame_info
.r
[reg_save_gp
])
3790 reg_emitted (reg_save_gp
);
3791 insn
= emit_move_insn (gen_rtx_REG (DImode
,
3792 current_frame_info
.r
[reg_save_gp
]),
3793 pic_offset_table_rtx
);
3796 /* We should now be at the base of the gr/br/fr spill area. */
3797 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3798 + current_frame_info
.spill_size
));
3800 /* Spill all general registers. */
3801 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3802 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3804 reg
= gen_rtx_REG (DImode
, regno
);
3805 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
3809 /* Spill the rest of the BR registers. */
3810 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3811 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3813 alt_regno
= next_scratch_gr_reg ();
3814 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3815 reg
= gen_rtx_REG (DImode
, regno
);
3816 emit_move_insn (alt_reg
, reg
);
3817 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3821 /* Align the frame and spill all FR registers. */
3822 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3823 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3825 gcc_assert (!(cfa_off
& 15));
3826 reg
= gen_rtx_REG (XFmode
, regno
);
3827 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
3831 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
3833 finish_spill_pointers ();
3836 /* Output the textual info surrounding the prologue. */
3839 ia64_start_function (FILE *file
, const char *fnname
,
3840 tree decl ATTRIBUTE_UNUSED
)
3842 #if TARGET_ABI_OPEN_VMS
3843 vms_start_function (fnname
);
3846 fputs ("\t.proc ", file
);
3847 assemble_name (file
, fnname
);
3849 ASM_OUTPUT_LABEL (file
, fnname
);
3852 /* Called after register allocation to add any instructions needed for the
3853 epilogue. Using an epilogue insn is favored compared to putting all of the
3854 instructions in output_function_prologue(), since it allows the scheduler
3855 to intermix instructions with the saves of the caller saved registers. In
3856 some cases, it might be necessary to emit a barrier instruction as the last
3857 insn to prevent such scheduling. */
3860 ia64_expand_epilogue (int sibcall_p
)
3862 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
3863 int regno
, alt_regno
, cfa_off
;
3865 ia64_compute_frame_size (get_frame_size ());
3867 /* If there is a frame pointer, then we use it instead of the stack
3868 pointer, so that the stack pointer does not need to be valid when
3869 the epilogue starts. See EXIT_IGNORE_STACK. */
3870 if (frame_pointer_needed
)
3871 setup_spill_pointers (current_frame_info
.n_spilled
,
3872 hard_frame_pointer_rtx
, 0);
3874 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
3875 current_frame_info
.total_size
);
3877 if (current_frame_info
.total_size
!= 0)
3879 /* ??? At this point we must generate a magic insn that appears to
3880 modify the spill iterators and the frame pointer. This would
3881 allow the most scheduling freedom. For now, just hard stop. */
3882 emit_insn (gen_blockage ());
3885 /* Locate the bottom of the register save area. */
3886 cfa_off
= (current_frame_info
.spill_cfa_off
3887 + current_frame_info
.spill_size
3888 + current_frame_info
.extra_spill_size
);
3890 /* Restore the predicate registers. */
3891 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3893 if (current_frame_info
.r
[reg_save_pr
] != 0)
3895 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3896 reg_emitted (reg_save_pr
);
3900 alt_regno
= next_scratch_gr_reg ();
3901 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3902 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3905 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3906 emit_move_insn (reg
, alt_reg
);
3909 /* Restore the application registers. */
3911 /* Load the saved unat from the stack, but do not restore it until
3912 after the GRs have been restored. */
3913 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3915 if (current_frame_info
.r
[reg_save_ar_unat
] != 0)
3918 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3919 reg_emitted (reg_save_ar_unat
);
3923 alt_regno
= next_scratch_gr_reg ();
3924 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3925 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3926 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3931 ar_unat_save_reg
= NULL_RTX
;
3933 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0)
3935 reg_emitted (reg_save_ar_pfs
);
3936 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_pfs
]);
3937 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3938 emit_move_insn (reg
, alt_reg
);
3940 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3942 alt_regno
= next_scratch_gr_reg ();
3943 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3944 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3946 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3947 emit_move_insn (reg
, alt_reg
);
3950 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3952 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3954 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3955 reg_emitted (reg_save_ar_lc
);
3959 alt_regno
= next_scratch_gr_reg ();
3960 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3961 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3964 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3965 emit_move_insn (reg
, alt_reg
);
3968 /* Restore the return pointer. */
3969 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3971 if (current_frame_info
.r
[reg_save_b0
] != 0)
3973 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3974 reg_emitted (reg_save_b0
);
3978 alt_regno
= next_scratch_gr_reg ();
3979 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3980 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3983 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3984 emit_move_insn (reg
, alt_reg
);
3987 /* We should now be at the base of the gr/br/fr spill area. */
3988 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3989 + current_frame_info
.spill_size
));
3991 /* The GP may be stored on the stack in the prologue, but it's
3992 never restored in the epilogue. Skip the stack slot. */
3993 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3996 /* Restore all general registers. */
3997 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3998 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4000 reg
= gen_rtx_REG (DImode
, regno
);
4001 do_restore (gen_gr_restore
, reg
, cfa_off
);
4005 /* Restore the branch registers. */
4006 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
4007 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4009 alt_regno
= next_scratch_gr_reg ();
4010 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
4011 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
4013 reg
= gen_rtx_REG (DImode
, regno
);
4014 emit_move_insn (reg
, alt_reg
);
4017 /* Restore floating point registers. */
4018 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
4019 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4021 gcc_assert (!(cfa_off
& 15));
4022 reg
= gen_rtx_REG (XFmode
, regno
);
4023 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
4027 /* Restore ar.unat for real. */
4028 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
4030 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
4031 emit_move_insn (reg
, ar_unat_save_reg
);
4034 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
4036 finish_spill_pointers ();
4038 if (current_frame_info
.total_size
4039 || cfun
->machine
->ia64_eh_epilogue_sp
4040 || frame_pointer_needed
)
4042 /* ??? At this point we must generate a magic insn that appears to
4043 modify the spill iterators, the stack pointer, and the frame
4044 pointer. This would allow the most scheduling freedom. For now,
4046 emit_insn (gen_blockage ());
4049 if (cfun
->machine
->ia64_eh_epilogue_sp
)
4050 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
4051 else if (frame_pointer_needed
)
4053 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
4054 RTX_FRAME_RELATED_P (insn
) = 1;
4055 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL
);
4057 else if (current_frame_info
.total_size
)
4059 rtx offset
, frame_size_rtx
;
4061 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
4062 if (satisfies_constraint_I (frame_size_rtx
))
4063 offset
= frame_size_rtx
;
4066 regno
= next_scratch_gr_reg ();
4067 offset
= gen_rtx_REG (DImode
, regno
);
4068 emit_move_insn (offset
, frame_size_rtx
);
4071 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
4074 RTX_FRAME_RELATED_P (insn
) = 1;
4075 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4076 gen_rtx_SET (VOIDmode
,
4078 gen_rtx_PLUS (DImode
,
4083 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
4084 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
4087 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
4090 int fp
= GR_REG (2);
4091 /* We need a throw away register here, r0 and r1 are reserved,
4092 so r2 is the first available call clobbered register. If
4093 there was a frame_pointer register, we may have swapped the
4094 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
4095 sure we're using the string "r2" when emitting the register
4096 name for the assembler. */
4097 if (current_frame_info
.r
[reg_fp
]
4098 && current_frame_info
.r
[reg_fp
] == GR_REG (2))
4099 fp
= HARD_FRAME_POINTER_REGNUM
;
4101 /* We must emit an alloc to force the input registers to become output
4102 registers. Otherwise, if the callee tries to pass its parameters
4103 through to another call without an intervening alloc, then these
4105 /* ??? We don't need to preserve all input registers. We only need to
4106 preserve those input registers used as arguments to the sibling call.
4107 It is unclear how to compute that number here. */
4108 if (current_frame_info
.n_input_regs
!= 0)
4110 rtx n_inputs
= GEN_INT (current_frame_info
.n_input_regs
);
4112 insn
= emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
4113 const0_rtx
, const0_rtx
,
4114 n_inputs
, const0_rtx
));
4115 RTX_FRAME_RELATED_P (insn
) = 1;
4117 /* ??? We need to mark the alloc as frame-related so that it gets
4118 passed into ia64_asm_unwind_emit for ia64-specific unwinding.
4119 But there's nothing dwarf2 related to be done wrt the register
4120 windows. If we do nothing, dwarf2out will abort on the UNSPEC;
4121 the empty parallel means dwarf2out will not see anything. */
4122 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4123 gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (0)));
4128 /* Return 1 if br.ret can do all the work required to return from a
4132 ia64_direct_return (void)
4134 if (reload_completed
&& ! frame_pointer_needed
)
4136 ia64_compute_frame_size (get_frame_size ());
4138 return (current_frame_info
.total_size
== 0
4139 && current_frame_info
.n_spilled
== 0
4140 && current_frame_info
.r
[reg_save_b0
] == 0
4141 && current_frame_info
.r
[reg_save_pr
] == 0
4142 && current_frame_info
.r
[reg_save_ar_pfs
] == 0
4143 && current_frame_info
.r
[reg_save_ar_unat
] == 0
4144 && current_frame_info
.r
[reg_save_ar_lc
] == 0);
4149 /* Return the magic cookie that we use to hold the return address
4150 during early compilation. */
4153 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
4157 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
4160 /* Split this value after reload, now that we know where the return
4161 address is saved. */
4164 ia64_split_return_addr_rtx (rtx dest
)
4168 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
4170 if (current_frame_info
.r
[reg_save_b0
] != 0)
4172 src
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
4173 reg_emitted (reg_save_b0
);
4181 /* Compute offset from CFA for BR0. */
4182 /* ??? Must be kept in sync with ia64_expand_prologue. */
4183 off
= (current_frame_info
.spill_cfa_off
4184 + current_frame_info
.spill_size
);
4185 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
4186 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4189 /* Convert CFA offset to a register based offset. */
4190 if (frame_pointer_needed
)
4191 src
= hard_frame_pointer_rtx
;
4194 src
= stack_pointer_rtx
;
4195 off
+= current_frame_info
.total_size
;
4198 /* Load address into scratch register. */
4199 off_r
= GEN_INT (off
);
4200 if (satisfies_constraint_I (off_r
))
4201 emit_insn (gen_adddi3 (dest
, src
, off_r
));
4204 emit_move_insn (dest
, off_r
);
4205 emit_insn (gen_adddi3 (dest
, src
, dest
));
4208 src
= gen_rtx_MEM (Pmode
, dest
);
4212 src
= gen_rtx_REG (DImode
, BR_REG (0));
4214 emit_move_insn (dest
, src
);
4218 ia64_hard_regno_rename_ok (int from
, int to
)
4220 /* Don't clobber any of the registers we reserved for the prologue. */
4223 for (r
= reg_fp
; r
<= reg_save_ar_lc
; r
++)
4224 if (to
== current_frame_info
.r
[r
]
4225 || from
== current_frame_info
.r
[r
]
4226 || to
== emitted_frame_related_regs
[r
]
4227 || from
== emitted_frame_related_regs
[r
])
4230 /* Don't use output registers outside the register frame. */
4231 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
4234 /* Retain even/oddness on predicate register pairs. */
4235 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
4236 return (from
& 1) == (to
& 1);
4241 /* Target hook for assembling integer objects. Handle word-sized
4242 aligned objects and detect the cases when @fptr is needed. */
4245 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
4247 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
4248 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
4249 && GET_CODE (x
) == SYMBOL_REF
4250 && SYMBOL_REF_FUNCTION_P (x
))
4252 static const char * const directive
[2][2] = {
4253 /* 64-bit pointer */ /* 32-bit pointer */
4254 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
4255 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
4257 fputs (directive
[(aligned_p
!= 0)][POINTER_SIZE
== 32], asm_out_file
);
4258 output_addr_const (asm_out_file
, x
);
4259 fputs (")\n", asm_out_file
);
4262 return default_assemble_integer (x
, size
, aligned_p
);
4265 /* Emit the function prologue. */
4268 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4270 int mask
, grsave
, grsave_prev
;
4272 if (current_frame_info
.need_regstk
)
4273 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
4274 current_frame_info
.n_input_regs
,
4275 current_frame_info
.n_local_regs
,
4276 current_frame_info
.n_output_regs
,
4277 current_frame_info
.n_rotate_regs
);
4279 if (ia64_except_unwind_info (&global_options
) != UI_TARGET
)
4282 /* Emit the .prologue directive. */
4285 grsave
= grsave_prev
= 0;
4286 if (current_frame_info
.r
[reg_save_b0
] != 0)
4289 grsave
= grsave_prev
= current_frame_info
.r
[reg_save_b0
];
4291 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0
4292 && (grsave_prev
== 0
4293 || current_frame_info
.r
[reg_save_ar_pfs
] == grsave_prev
+ 1))
4296 if (grsave_prev
== 0)
4297 grsave
= current_frame_info
.r
[reg_save_ar_pfs
];
4298 grsave_prev
= current_frame_info
.r
[reg_save_ar_pfs
];
4300 if (current_frame_info
.r
[reg_fp
] != 0
4301 && (grsave_prev
== 0
4302 || current_frame_info
.r
[reg_fp
] == grsave_prev
+ 1))
4305 if (grsave_prev
== 0)
4306 grsave
= HARD_FRAME_POINTER_REGNUM
;
4307 grsave_prev
= current_frame_info
.r
[reg_fp
];
4309 if (current_frame_info
.r
[reg_save_pr
] != 0
4310 && (grsave_prev
== 0
4311 || current_frame_info
.r
[reg_save_pr
] == grsave_prev
+ 1))
4314 if (grsave_prev
== 0)
4315 grsave
= current_frame_info
.r
[reg_save_pr
];
4318 if (mask
&& TARGET_GNU_AS
)
4319 fprintf (file
, "\t.prologue %d, %d\n", mask
,
4320 ia64_dbx_register_number (grsave
));
4322 fputs ("\t.prologue\n", file
);
4324 /* Emit a .spill directive, if necessary, to relocate the base of
4325 the register spill area. */
4326 if (current_frame_info
.spill_cfa_off
!= -16)
4327 fprintf (file
, "\t.spill %ld\n",
4328 (long) (current_frame_info
.spill_cfa_off
4329 + current_frame_info
.spill_size
));
4332 /* Emit the .body directive at the scheduled end of the prologue. */
4335 ia64_output_function_end_prologue (FILE *file
)
4337 if (ia64_except_unwind_info (&global_options
) != UI_TARGET
)
4340 fputs ("\t.body\n", file
);
4343 /* Emit the function epilogue. */
4346 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
4347 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4351 if (current_frame_info
.r
[reg_fp
])
4353 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
4354 reg_names
[HARD_FRAME_POINTER_REGNUM
]
4355 = reg_names
[current_frame_info
.r
[reg_fp
]];
4356 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
4357 reg_emitted (reg_fp
);
4359 if (! TARGET_REG_NAMES
)
4361 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
4362 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
4363 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
4364 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
4365 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
4366 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
4369 current_frame_info
.initialized
= 0;
4373 ia64_dbx_register_number (int regno
)
4375 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4376 from its home at loc79 to something inside the register frame. We
4377 must perform the same renumbering here for the debug info. */
4378 if (current_frame_info
.r
[reg_fp
])
4380 if (regno
== HARD_FRAME_POINTER_REGNUM
)
4381 regno
= current_frame_info
.r
[reg_fp
];
4382 else if (regno
== current_frame_info
.r
[reg_fp
])
4383 regno
= HARD_FRAME_POINTER_REGNUM
;
4386 if (IN_REGNO_P (regno
))
4387 return 32 + regno
- IN_REG (0);
4388 else if (LOC_REGNO_P (regno
))
4389 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
4390 else if (OUT_REGNO_P (regno
))
4391 return (32 + current_frame_info
.n_input_regs
4392 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
4397 /* Implement TARGET_TRAMPOLINE_INIT.
4399 The trampoline should set the static chain pointer to value placed
4400 into the trampoline and should branch to the specified routine.
4401 To make the normal indirect-subroutine calling convention work,
4402 the trampoline must look like a function descriptor; the first
4403 word being the target address and the second being the target's
4406 We abuse the concept of a global pointer by arranging for it
4407 to point to the data we need to load. The complete trampoline
4408 has the following form:
4410 +-------------------+ \
4411 TRAMP: | __ia64_trampoline | |
4412 +-------------------+ > fake function descriptor
4414 +-------------------+ /
4415 | target descriptor |
4416 +-------------------+
4418 +-------------------+
4422 ia64_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
4424 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4425 rtx addr
, addr_reg
, tramp
, eight
= GEN_INT (8);
4427 /* The Intel assembler requires that the global __ia64_trampoline symbol
4428 be declared explicitly */
4431 static bool declared_ia64_trampoline
= false;
4433 if (!declared_ia64_trampoline
)
4435 declared_ia64_trampoline
= true;
4436 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
4437 "__ia64_trampoline");
4441 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4442 addr
= convert_memory_address (Pmode
, XEXP (m_tramp
, 0));
4443 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
4444 static_chain
= convert_memory_address (Pmode
, static_chain
);
4446 /* Load up our iterator. */
4447 addr_reg
= copy_to_reg (addr
);
4448 m_tramp
= adjust_automodify_address (m_tramp
, Pmode
, addr_reg
, 0);
4450 /* The first two words are the fake descriptor:
4451 __ia64_trampoline, ADDR+16. */
4452 tramp
= gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline");
4453 if (TARGET_ABI_OPEN_VMS
)
4455 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4456 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4457 relocation against function symbols to make it identical to the
4458 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4459 strict ELF and dereference to get the bare code address. */
4460 rtx reg
= gen_reg_rtx (Pmode
);
4461 SYMBOL_REF_FLAGS (tramp
) |= SYMBOL_FLAG_FUNCTION
;
4462 emit_move_insn (reg
, tramp
);
4463 emit_move_insn (reg
, gen_rtx_MEM (Pmode
, reg
));
4466 emit_move_insn (m_tramp
, tramp
);
4467 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4468 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4470 emit_move_insn (m_tramp
, force_reg (Pmode
, plus_constant (Pmode
, addr
, 16)));
4471 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4472 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4474 /* The third word is the target descriptor. */
4475 emit_move_insn (m_tramp
, force_reg (Pmode
, fnaddr
));
4476 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4477 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4479 /* The fourth word is the static chain. */
4480 emit_move_insn (m_tramp
, static_chain
);
4483 /* Do any needed setup for a variadic function. CUM has not been updated
4484 for the last named argument which has type TYPE and mode MODE.
4486 We generate the actual spill instructions during prologue generation. */
4489 ia64_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
4490 tree type
, int * pretend_size
,
4491 int second_time ATTRIBUTE_UNUSED
)
4493 CUMULATIVE_ARGS next_cum
= *get_cumulative_args (cum
);
4495 /* Skip the current argument. */
4496 ia64_function_arg_advance (pack_cumulative_args (&next_cum
), mode
, type
, 1);
4498 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
4500 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
4501 *pretend_size
= n
* UNITS_PER_WORD
;
4502 cfun
->machine
->n_varargs
= n
;
4506 /* Check whether TYPE is a homogeneous floating point aggregate. If
4507 it is, return the mode of the floating point type that appears
4508 in all leafs. If it is not, return VOIDmode.
4510 An aggregate is a homogeneous floating point aggregate is if all
4511 fields/elements in it have the same floating point type (e.g,
4512 SFmode). 128-bit quad-precision floats are excluded.
4514 Variable sized aggregates should never arrive here, since we should
4515 have already decided to pass them by reference. Top-level zero-sized
4516 aggregates are excluded because our parallels crash the middle-end. */
4518 static enum machine_mode
4519 hfa_element_mode (const_tree type
, bool nested
)
4521 enum machine_mode element_mode
= VOIDmode
;
4522 enum machine_mode mode
;
4523 enum tree_code code
= TREE_CODE (type
);
4524 int know_element_mode
= 0;
4527 if (!nested
&& (!TYPE_SIZE (type
) || integer_zerop (TYPE_SIZE (type
))))
4532 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
4533 case BOOLEAN_TYPE
: case POINTER_TYPE
:
4534 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
4535 case LANG_TYPE
: case FUNCTION_TYPE
:
4538 /* Fortran complex types are supposed to be HFAs, so we need to handle
4539 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4542 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
4543 && TYPE_MODE (type
) != TCmode
)
4544 return GET_MODE_INNER (TYPE_MODE (type
));
4549 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4550 mode if this is contained within an aggregate. */
4551 if (nested
&& TYPE_MODE (type
) != TFmode
)
4552 return TYPE_MODE (type
);
4557 return hfa_element_mode (TREE_TYPE (type
), 1);
4561 case QUAL_UNION_TYPE
:
4562 for (t
= TYPE_FIELDS (type
); t
; t
= DECL_CHAIN (t
))
4564 if (TREE_CODE (t
) != FIELD_DECL
)
4567 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
4568 if (know_element_mode
)
4570 if (mode
!= element_mode
)
4573 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
4577 know_element_mode
= 1;
4578 element_mode
= mode
;
4581 return element_mode
;
4584 /* If we reach here, we probably have some front-end specific type
4585 that the backend doesn't know about. This can happen via the
4586 aggregate_value_p call in init_function_start. All we can do is
4587 ignore unknown tree types. */
4594 /* Return the number of words required to hold a quantity of TYPE and MODE
4595 when passed as an argument. */
4597 ia64_function_arg_words (const_tree type
, enum machine_mode mode
)
4601 if (mode
== BLKmode
)
4602 words
= int_size_in_bytes (type
);
4604 words
= GET_MODE_SIZE (mode
);
4606 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
4609 /* Return the number of registers that should be skipped so the current
4610 argument (described by TYPE and WORDS) will be properly aligned.
4612 Integer and float arguments larger than 8 bytes start at the next
4613 even boundary. Aggregates larger than 8 bytes start at the next
4614 even boundary if the aggregate has 16 byte alignment. Note that
4615 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4616 but are still to be aligned in registers.
4618 ??? The ABI does not specify how to handle aggregates with
4619 alignment from 9 to 15 bytes, or greater than 16. We handle them
4620 all as if they had 16 byte alignment. Such aggregates can occur
4621 only if gcc extensions are used. */
4623 ia64_function_arg_offset (const CUMULATIVE_ARGS
*cum
,
4624 const_tree type
, int words
)
4626 /* No registers are skipped on VMS. */
4627 if (TARGET_ABI_OPEN_VMS
|| (cum
->words
& 1) == 0)
4631 && TREE_CODE (type
) != INTEGER_TYPE
4632 && TREE_CODE (type
) != REAL_TYPE
)
4633 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
4638 /* Return rtx for register where argument is passed, or zero if it is passed
4640 /* ??? 128-bit quad-precision floats are always passed in general
4644 ia64_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
4645 const_tree type
, bool named
, bool incoming
)
4647 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4649 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
4650 int words
= ia64_function_arg_words (type
, mode
);
4651 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4652 enum machine_mode hfa_mode
= VOIDmode
;
4654 /* For OPEN VMS, emit the instruction setting up the argument register here,
4655 when we know this will be together with the other arguments setup related
4656 insns. This is not the conceptually best place to do this, but this is
4657 the easiest as we have convenient access to cumulative args info. */
4659 if (TARGET_ABI_OPEN_VMS
&& mode
== VOIDmode
&& type
== void_type_node
4662 unsigned HOST_WIDE_INT regval
= cum
->words
;
4665 for (i
= 0; i
< 8; i
++)
4666 regval
|= ((int) cum
->atypes
[i
]) << (i
* 3 + 8);
4668 emit_move_insn (gen_rtx_REG (DImode
, GR_REG (25)),
4672 /* If all argument slots are used, then it must go on the stack. */
4673 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4676 /* On OpenVMS argument is either in Rn or Fn. */
4677 if (TARGET_ABI_OPEN_VMS
)
4679 if (FLOAT_MODE_P (mode
))
4680 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->words
);
4682 return gen_rtx_REG (mode
, basereg
+ cum
->words
);
4685 /* Check for and handle homogeneous FP aggregates. */
4687 hfa_mode
= hfa_element_mode (type
, 0);
4689 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4690 and unprototyped hfas are passed specially. */
4691 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4695 int fp_regs
= cum
->fp_regs
;
4696 int int_regs
= cum
->words
+ offset
;
4697 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4701 /* If prototyped, pass it in FR regs then GR regs.
4702 If not prototyped, pass it in both FR and GR regs.
4704 If this is an SFmode aggregate, then it is possible to run out of
4705 FR regs while GR regs are still left. In that case, we pass the
4706 remaining part in the GR regs. */
4708 /* Fill the FP regs. We do this always. We stop if we reach the end
4709 of the argument, the last FP register, or the last argument slot. */
4711 byte_size
= ((mode
== BLKmode
)
4712 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4713 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4715 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4716 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
4718 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4719 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
4723 args_byte_size
+= hfa_size
;
4727 /* If no prototype, then the whole thing must go in GR regs. */
4728 if (! cum
->prototype
)
4730 /* If this is an SFmode aggregate, then we might have some left over
4731 that needs to go in GR regs. */
4732 else if (byte_size
!= offset
)
4733 int_regs
+= offset
/ UNITS_PER_WORD
;
4735 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4737 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
4739 enum machine_mode gr_mode
= DImode
;
4740 unsigned int gr_size
;
4742 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4743 then this goes in a GR reg left adjusted/little endian, right
4744 adjusted/big endian. */
4745 /* ??? Currently this is handled wrong, because 4-byte hunks are
4746 always right adjusted/little endian. */
4749 /* If we have an even 4 byte hunk because the aggregate is a
4750 multiple of 4 bytes in size, then this goes in a GR reg right
4751 adjusted/little endian. */
4752 else if (byte_size
- offset
== 4)
4755 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4756 gen_rtx_REG (gr_mode
, (basereg
4760 gr_size
= GET_MODE_SIZE (gr_mode
);
4762 if (gr_size
== UNITS_PER_WORD
4763 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
4765 else if (gr_size
> UNITS_PER_WORD
)
4766 int_regs
+= gr_size
/ UNITS_PER_WORD
;
4768 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4771 /* Integral and aggregates go in general registers. If we have run out of
4772 FR registers, then FP values must also go in general registers. This can
4773 happen when we have a SFmode HFA. */
4774 else if (mode
== TFmode
|| mode
== TCmode
4775 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4777 int byte_size
= ((mode
== BLKmode
)
4778 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4779 if (BYTES_BIG_ENDIAN
4780 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
4781 && byte_size
< UNITS_PER_WORD
4784 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4785 gen_rtx_REG (DImode
,
4786 (basereg
+ cum
->words
4789 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
4792 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4796 /* If there is a prototype, then FP values go in a FR register when
4797 named, and in a GR register when unnamed. */
4798 else if (cum
->prototype
)
4801 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
4802 /* In big-endian mode, an anonymous SFmode value must be represented
4803 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4804 the value into the high half of the general register. */
4805 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
4806 return gen_rtx_PARALLEL (mode
,
4808 gen_rtx_EXPR_LIST (VOIDmode
,
4809 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
4812 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4814 /* If there is no prototype, then FP values go in both FR and GR
4818 /* See comment above. */
4819 enum machine_mode inner_mode
=
4820 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
4822 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4823 gen_rtx_REG (mode
, (FR_ARG_FIRST
4826 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4827 gen_rtx_REG (inner_mode
,
4828 (basereg
+ cum
->words
4832 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
4836 /* Implement TARGET_FUNCION_ARG target hook. */
4839 ia64_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
4840 const_tree type
, bool named
)
4842 return ia64_function_arg_1 (cum
, mode
, type
, named
, false);
4845 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4848 ia64_function_incoming_arg (cumulative_args_t cum
,
4849 enum machine_mode mode
,
4850 const_tree type
, bool named
)
4852 return ia64_function_arg_1 (cum
, mode
, type
, named
, true);
4855 /* Return number of bytes, at the beginning of the argument, that must be
4856 put in registers. 0 is the argument is entirely in registers or entirely
4860 ia64_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
4861 tree type
, bool named ATTRIBUTE_UNUSED
)
4863 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4865 int words
= ia64_function_arg_words (type
, mode
);
4866 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4868 /* If all argument slots are used, then it must go on the stack. */
4869 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4872 /* It doesn't matter whether the argument goes in FR or GR regs. If
4873 it fits within the 8 argument slots, then it goes entirely in
4874 registers. If it extends past the last argument slot, then the rest
4875 goes on the stack. */
4877 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
4880 return (MAX_ARGUMENT_SLOTS
- cum
->words
- offset
) * UNITS_PER_WORD
;
4883 /* Return ivms_arg_type based on machine_mode. */
4885 static enum ivms_arg_type
4886 ia64_arg_type (enum machine_mode mode
)
4899 /* Update CUM to point after this argument. This is patterned after
4900 ia64_function_arg. */
4903 ia64_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
4904 const_tree type
, bool named
)
4906 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4907 int words
= ia64_function_arg_words (type
, mode
);
4908 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4909 enum machine_mode hfa_mode
= VOIDmode
;
4911 /* If all arg slots are already full, then there is nothing to do. */
4912 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
4914 cum
->words
+= words
+ offset
;
4918 cum
->atypes
[cum
->words
] = ia64_arg_type (mode
);
4919 cum
->words
+= words
+ offset
;
4921 /* On OpenVMS argument is either in Rn or Fn. */
4922 if (TARGET_ABI_OPEN_VMS
)
4924 cum
->int_regs
= cum
->words
;
4925 cum
->fp_regs
= cum
->words
;
4929 /* Check for and handle homogeneous FP aggregates. */
4931 hfa_mode
= hfa_element_mode (type
, 0);
4933 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4934 and unprototyped hfas are passed specially. */
4935 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4937 int fp_regs
= cum
->fp_regs
;
4938 /* This is the original value of cum->words + offset. */
4939 int int_regs
= cum
->words
- words
;
4940 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4944 /* If prototyped, pass it in FR regs then GR regs.
4945 If not prototyped, pass it in both FR and GR regs.
4947 If this is an SFmode aggregate, then it is possible to run out of
4948 FR regs while GR regs are still left. In that case, we pass the
4949 remaining part in the GR regs. */
4951 /* Fill the FP regs. We do this always. We stop if we reach the end
4952 of the argument, the last FP register, or the last argument slot. */
4954 byte_size
= ((mode
== BLKmode
)
4955 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4956 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4958 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4959 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
4962 args_byte_size
+= hfa_size
;
4966 cum
->fp_regs
= fp_regs
;
4969 /* Integral and aggregates go in general registers. So do TFmode FP values.
4970 If we have run out of FR registers, then other FP values must also go in
4971 general registers. This can happen when we have a SFmode HFA. */
4972 else if (mode
== TFmode
|| mode
== TCmode
4973 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4974 cum
->int_regs
= cum
->words
;
4976 /* If there is a prototype, then FP values go in a FR register when
4977 named, and in a GR register when unnamed. */
4978 else if (cum
->prototype
)
4981 cum
->int_regs
= cum
->words
;
4983 /* ??? Complex types should not reach here. */
4984 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4986 /* If there is no prototype, then FP values go in both FR and GR
4990 /* ??? Complex types should not reach here. */
4991 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4992 cum
->int_regs
= cum
->words
;
4996 /* Arguments with alignment larger than 8 bytes start at the next even
4997 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4998 even though their normal alignment is 8 bytes. See ia64_function_arg. */
5001 ia64_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5003 if (mode
== TFmode
&& TARGET_HPUX
&& TARGET_ILP32
)
5004 return PARM_BOUNDARY
* 2;
5008 if (TYPE_ALIGN (type
) > PARM_BOUNDARY
)
5009 return PARM_BOUNDARY
* 2;
5011 return PARM_BOUNDARY
;
5014 if (GET_MODE_BITSIZE (mode
) > PARM_BOUNDARY
)
5015 return PARM_BOUNDARY
* 2;
5017 return PARM_BOUNDARY
;
5020 /* True if it is OK to do sibling call optimization for the specified
5021 call expression EXP. DECL will be the called function, or NULL if
5022 this is an indirect call. */
5024 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
5026 /* We can't perform a sibcall if the current function has the syscall_linkage
5028 if (lookup_attribute ("syscall_linkage",
5029 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
5032 /* We must always return with our current GP. This means we can
5033 only sibcall to functions defined in the current module unless
5034 TARGET_CONST_GP is set to true. */
5035 return (decl
&& (*targetm
.binds_local_p
) (decl
)) || TARGET_CONST_GP
;
5039 /* Implement va_arg. */
5042 ia64_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
5045 /* Variable sized types are passed by reference. */
5046 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5048 tree ptrtype
= build_pointer_type (type
);
5049 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
5050 return build_va_arg_indirect_ref (addr
);
5053 /* Aggregate arguments with alignment larger than 8 bytes start at
5054 the next even boundary. Integer and floating point arguments
5055 do so if they are larger than 8 bytes, whether or not they are
5056 also aligned larger than 8 bytes. */
5057 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
5058 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
5060 tree t
= fold_build_pointer_plus_hwi (valist
, 2 * UNITS_PER_WORD
- 1);
5061 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5062 build_int_cst (TREE_TYPE (t
), -2 * UNITS_PER_WORD
));
5063 gimplify_assign (unshare_expr (valist
), t
, pre_p
);
5066 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5069 /* Return 1 if function return value returned in memory. Return 0 if it is
5073 ia64_return_in_memory (const_tree valtype
, const_tree fntype ATTRIBUTE_UNUSED
)
5075 enum machine_mode mode
;
5076 enum machine_mode hfa_mode
;
5077 HOST_WIDE_INT byte_size
;
5079 mode
= TYPE_MODE (valtype
);
5080 byte_size
= GET_MODE_SIZE (mode
);
5081 if (mode
== BLKmode
)
5083 byte_size
= int_size_in_bytes (valtype
);
5088 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
5090 hfa_mode
= hfa_element_mode (valtype
, 0);
5091 if (hfa_mode
!= VOIDmode
)
5093 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
5095 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
5100 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
5106 /* Return rtx for register that holds the function return value. */
5109 ia64_function_value (const_tree valtype
,
5110 const_tree fn_decl_or_type
,
5111 bool outgoing ATTRIBUTE_UNUSED
)
5113 enum machine_mode mode
;
5114 enum machine_mode hfa_mode
;
5116 const_tree func
= fn_decl_or_type
;
5119 && !DECL_P (fn_decl_or_type
))
5122 mode
= TYPE_MODE (valtype
);
5123 hfa_mode
= hfa_element_mode (valtype
, 0);
5125 if (hfa_mode
!= VOIDmode
)
5133 hfa_size
= GET_MODE_SIZE (hfa_mode
);
5134 byte_size
= ((mode
== BLKmode
)
5135 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
5137 for (i
= 0; offset
< byte_size
; i
++)
5139 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
5140 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
5144 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
5146 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
5147 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
5150 bool need_parallel
= false;
5152 /* In big-endian mode, we need to manage the layout of aggregates
5153 in the registers so that we get the bits properly aligned in
5154 the highpart of the registers. */
5155 if (BYTES_BIG_ENDIAN
5156 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
5157 need_parallel
= true;
5159 /* Something like struct S { long double x; char a[0] } is not an
5160 HFA structure, and therefore doesn't go in fp registers. But
5161 the middle-end will give it XFmode anyway, and XFmode values
5162 don't normally fit in integer registers. So we need to smuggle
5163 the value inside a parallel. */
5164 else if (mode
== XFmode
|| mode
== XCmode
|| mode
== RFmode
)
5165 need_parallel
= true;
5175 bytesize
= int_size_in_bytes (valtype
);
5176 /* An empty PARALLEL is invalid here, but the return value
5177 doesn't matter for empty structs. */
5179 return gen_rtx_REG (mode
, GR_RET_FIRST
);
5180 for (i
= 0; offset
< bytesize
; i
++)
5182 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
5183 gen_rtx_REG (DImode
,
5186 offset
+= UNITS_PER_WORD
;
5188 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
5191 mode
= promote_function_mode (valtype
, mode
, &unsignedp
,
5192 func
? TREE_TYPE (func
) : NULL_TREE
,
5195 return gen_rtx_REG (mode
, GR_RET_FIRST
);
5199 /* Worker function for TARGET_LIBCALL_VALUE. */
5202 ia64_libcall_value (enum machine_mode mode
,
5203 const_rtx fun ATTRIBUTE_UNUSED
)
5205 return gen_rtx_REG (mode
,
5206 (((GET_MODE_CLASS (mode
) == MODE_FLOAT
5207 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5208 && (mode
) != TFmode
)
5209 ? FR_RET_FIRST
: GR_RET_FIRST
));
5212 /* Worker function for FUNCTION_VALUE_REGNO_P. */
5215 ia64_function_value_regno_p (const unsigned int regno
)
5217 return ((regno
>= GR_RET_FIRST
&& regno
<= GR_RET_LAST
)
5218 || (regno
>= FR_RET_FIRST
&& regno
<= FR_RET_LAST
));
5221 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5222 We need to emit DTP-relative relocations. */
5225 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5227 gcc_assert (size
== 4 || size
== 8);
5229 fputs ("\tdata4.ua\t@dtprel(", file
);
5231 fputs ("\tdata8.ua\t@dtprel(", file
);
5232 output_addr_const (file
, x
);
5236 /* Print a memory address as an operand to reference that memory location. */
5238 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
5239 also call this from ia64_print_operand for memory addresses. */
5242 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
5243 rtx address ATTRIBUTE_UNUSED
)
5247 /* Print an operand to an assembler instruction.
5248 C Swap and print a comparison operator.
5249 D Print an FP comparison operator.
5250 E Print 32 - constant, for SImode shifts as extract.
5251 e Print 64 - constant, for DImode rotates.
5252 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
5253 a floating point register emitted normally.
5254 G A floating point constant.
5255 I Invert a predicate register by adding 1.
5256 J Select the proper predicate register for a condition.
5257 j Select the inverse predicate register for a condition.
5258 O Append .acq for volatile load.
5259 P Postincrement of a MEM.
5260 Q Append .rel for volatile store.
5261 R Print .s .d or nothing for a single, double or no truncation.
5262 S Shift amount for shladd instruction.
5263 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
5264 for Intel assembler.
5265 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
5266 for Intel assembler.
5267 X A pair of floating point registers.
5268 r Print register name, or constant 0 as r0. HP compatibility for
5270 v Print vector constant value as an 8-byte integer value. */
5273 ia64_print_operand (FILE * file
, rtx x
, int code
)
5280 /* Handled below. */
5285 enum rtx_code c
= swap_condition (GET_CODE (x
));
5286 fputs (GET_RTX_NAME (c
), file
);
5291 switch (GET_CODE (x
))
5318 str
= GET_RTX_NAME (GET_CODE (x
));
5325 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
5329 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
5333 if (x
== CONST0_RTX (GET_MODE (x
)))
5334 str
= reg_names
[FR_REG (0)];
5335 else if (x
== CONST1_RTX (GET_MODE (x
)))
5336 str
= reg_names
[FR_REG (1)];
5339 gcc_assert (GET_CODE (x
) == REG
);
5340 str
= reg_names
[REGNO (x
)];
5349 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
5350 real_to_target (val
, &rv
, GET_MODE (x
));
5351 if (GET_MODE (x
) == SFmode
)
5352 fprintf (file
, "0x%08lx", val
[0] & 0xffffffff);
5353 else if (GET_MODE (x
) == DFmode
)
5354 fprintf (file
, "0x%08lx%08lx", (WORDS_BIG_ENDIAN
? val
[0] : val
[1])
5356 (WORDS_BIG_ENDIAN
? val
[1] : val
[0])
5359 output_operand_lossage ("invalid %%G mode");
5364 fputs (reg_names
[REGNO (x
) + 1], file
);
5370 unsigned int regno
= REGNO (XEXP (x
, 0));
5371 if (GET_CODE (x
) == EQ
)
5375 fputs (reg_names
[regno
], file
);
5380 if (MEM_VOLATILE_P (x
))
5381 fputs(".acq", file
);
5386 HOST_WIDE_INT value
;
5388 switch (GET_CODE (XEXP (x
, 0)))
5394 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5395 if (GET_CODE (x
) == CONST_INT
)
5399 gcc_assert (GET_CODE (x
) == REG
);
5400 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
5406 value
= GET_MODE_SIZE (GET_MODE (x
));
5410 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
5414 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
5419 if (MEM_VOLATILE_P (x
))
5420 fputs(".rel", file
);
5424 if (x
== CONST0_RTX (GET_MODE (x
)))
5426 else if (x
== CONST1_RTX (GET_MODE (x
)))
5428 else if (x
== CONST2_RTX (GET_MODE (x
)))
5431 output_operand_lossage ("invalid %%R value");
5435 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5439 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5441 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
5447 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5449 const char *prefix
= "0x";
5450 if (INTVAL (x
) & 0x80000000)
5452 fprintf (file
, "0xffffffff");
5455 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
5462 unsigned int regno
= REGNO (x
);
5463 fprintf (file
, "%s, %s", reg_names
[regno
], reg_names
[regno
+ 1]);
5468 /* If this operand is the constant zero, write it as register zero.
5469 Any register, zero, or CONST_INT value is OK here. */
5470 if (GET_CODE (x
) == REG
)
5471 fputs (reg_names
[REGNO (x
)], file
);
5472 else if (x
== CONST0_RTX (GET_MODE (x
)))
5474 else if (GET_CODE (x
) == CONST_INT
)
5475 output_addr_const (file
, x
);
5477 output_operand_lossage ("invalid %%r value");
5481 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
5482 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
5489 /* For conditional branches, returns or calls, substitute
5490 sptk, dptk, dpnt, or spnt for %s. */
5491 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
5494 int pred_val
= XINT (x
, 0);
5496 /* Guess top and bottom 10% statically predicted. */
5497 if (pred_val
< REG_BR_PROB_BASE
/ 50
5498 && br_prob_note_reliable_p (x
))
5500 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
5502 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98
5503 || !br_prob_note_reliable_p (x
))
5508 else if (CALL_P (current_output_insn
))
5513 fputs (which
, file
);
5518 x
= current_insn_predicate
;
5521 unsigned int regno
= REGNO (XEXP (x
, 0));
5522 if (GET_CODE (x
) == EQ
)
5524 fprintf (file
, "(%s) ", reg_names
[regno
]);
5529 output_operand_lossage ("ia64_print_operand: unknown code");
5533 switch (GET_CODE (x
))
5535 /* This happens for the spill/restore instructions. */
5540 /* ... fall through ... */
5543 fputs (reg_names
[REGNO (x
)], file
);
5548 rtx addr
= XEXP (x
, 0);
5549 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
5550 addr
= XEXP (addr
, 0);
5551 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
5556 output_addr_const (file
, x
);
5563 /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
5566 ia64_print_operand_punct_valid_p (unsigned char code
)
5568 return (code
== '+' || code
== ',');
5571 /* Compute a (partial) cost for rtx X. Return true if the complete
5572 cost has been computed, and false if subexpressions should be
5573 scanned. In either case, *TOTAL contains the cost result. */
5574 /* ??? This is incomplete. */
5577 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
5578 int *total
, bool speed ATTRIBUTE_UNUSED
)
5586 *total
= satisfies_constraint_J (x
) ? 0 : COSTS_N_INSNS (1);
5589 if (satisfies_constraint_I (x
))
5591 else if (satisfies_constraint_J (x
))
5594 *total
= COSTS_N_INSNS (1);
5597 if (satisfies_constraint_K (x
) || satisfies_constraint_L (x
))
5600 *total
= COSTS_N_INSNS (1);
5605 *total
= COSTS_N_INSNS (1);
5611 *total
= COSTS_N_INSNS (3);
5615 *total
= COSTS_N_INSNS (4);
5619 /* For multiplies wider than HImode, we have to go to the FPU,
5620 which normally involves copies. Plus there's the latency
5621 of the multiply itself, and the latency of the instructions to
5622 transfer integer regs to FP regs. */
5623 if (FLOAT_MODE_P (GET_MODE (x
)))
5624 *total
= COSTS_N_INSNS (4);
5625 else if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
5626 *total
= COSTS_N_INSNS (10);
5628 *total
= COSTS_N_INSNS (2);
5633 if (FLOAT_MODE_P (GET_MODE (x
)))
5635 *total
= COSTS_N_INSNS (4);
5643 *total
= COSTS_N_INSNS (1);
5650 /* We make divide expensive, so that divide-by-constant will be
5651 optimized to a multiply. */
5652 *total
= COSTS_N_INSNS (60);
5660 /* Calculate the cost of moving data from a register in class FROM to
5661 one in class TO, using MODE. */
5664 ia64_register_move_cost (enum machine_mode mode
, reg_class_t from
,
5667 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5668 if (to
== ADDL_REGS
)
5670 if (from
== ADDL_REGS
)
5673 /* All costs are symmetric, so reduce cases by putting the
5674 lower number class as the destination. */
5677 reg_class_t tmp
= to
;
5678 to
= from
, from
= tmp
;
5681 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5682 so that we get secondary memory reloads. Between FR_REGS,
5683 we have to make this at least as expensive as memory_move_cost
5684 to avoid spectacularly poor register class preferencing. */
5685 if (mode
== XFmode
|| mode
== RFmode
)
5687 if (to
!= GR_REGS
|| from
!= GR_REGS
)
5688 return memory_move_cost (mode
, to
, false);
5696 /* Moving between PR registers takes two insns. */
5697 if (from
== PR_REGS
)
5699 /* Moving between PR and anything but GR is impossible. */
5700 if (from
!= GR_REGS
)
5701 return memory_move_cost (mode
, to
, false);
5705 /* Moving between BR and anything but GR is impossible. */
5706 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
5707 return memory_move_cost (mode
, to
, false);
5712 /* Moving between AR and anything but GR is impossible. */
5713 if (from
!= GR_REGS
)
5714 return memory_move_cost (mode
, to
, false);
5720 case GR_AND_FR_REGS
:
5721 case GR_AND_BR_REGS
:
5732 /* Calculate the cost of moving data of MODE from a register to or from
5736 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
5738 bool in ATTRIBUTE_UNUSED
)
5740 if (rclass
== GENERAL_REGS
5741 || rclass
== FR_REGS
5742 || rclass
== FP_REGS
5743 || rclass
== GR_AND_FR_REGS
)
5749 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5750 on RCLASS to use when copying X into that class. */
5753 ia64_preferred_reload_class (rtx x
, reg_class_t rclass
)
5759 /* Don't allow volatile mem reloads into floating point registers.
5760 This is defined to force reload to choose the r/m case instead
5761 of the f/f case when reloading (set (reg fX) (mem/v)). */
5762 if (MEM_P (x
) && MEM_VOLATILE_P (x
))
5765 /* Force all unrecognized constants into the constant pool. */
5783 /* This function returns the register class required for a secondary
5784 register when copying between one of the registers in RCLASS, and X,
5785 using MODE. A return value of NO_REGS means that no secondary register
5789 ia64_secondary_reload_class (enum reg_class rclass
,
5790 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
5794 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5795 regno
= true_regnum (x
);
5802 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5803 interaction. We end up with two pseudos with overlapping lifetimes
5804 both of which are equiv to the same constant, and both which need
5805 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5806 changes depending on the path length, which means the qty_first_reg
5807 check in make_regs_eqv can give different answers at different times.
5808 At some point I'll probably need a reload_indi pattern to handle
5811 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5812 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5813 non-general registers for good measure. */
5814 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
5817 /* This is needed if a pseudo used as a call_operand gets spilled to a
5819 if (GET_CODE (x
) == MEM
)
5825 /* Need to go through general registers to get to other class regs. */
5826 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
5829 /* This can happen when a paradoxical subreg is an operand to the
5831 /* ??? This shouldn't be necessary after instruction scheduling is
5832 enabled, because paradoxical subregs are not accepted by
5833 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5834 stop the paradoxical subreg stupidity in the *_operand functions
5836 if (GET_CODE (x
) == MEM
5837 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
5838 || GET_MODE (x
) == QImode
))
5841 /* This can happen because of the ior/and/etc patterns that accept FP
5842 registers as operands. If the third operand is a constant, then it
5843 needs to be reloaded into a FP register. */
5844 if (GET_CODE (x
) == CONST_INT
)
5847 /* This can happen because of register elimination in a muldi3 insn.
5848 E.g. `26107 * (unsigned long)&u'. */
5849 if (GET_CODE (x
) == PLUS
)
5854 /* ??? This happens if we cse/gcse a BImode value across a call,
5855 and the function has a nonlocal goto. This is because global
5856 does not allocate call crossing pseudos to hard registers when
5857 crtl->has_nonlocal_goto is true. This is relatively
5858 common for C++ programs that use exceptions. To reproduce,
5859 return NO_REGS and compile libstdc++. */
5860 if (GET_CODE (x
) == MEM
)
5863 /* This can happen when we take a BImode subreg of a DImode value,
5864 and that DImode value winds up in some non-GR register. */
5865 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
5877 /* Implement targetm.unspec_may_trap_p hook. */
5879 ia64_unspec_may_trap_p (const_rtx x
, unsigned flags
)
5881 switch (XINT (x
, 1))
5887 case UNSPEC_CHKACLR
:
5889 /* These unspecs are just wrappers. */
5890 return may_trap_p_1 (XVECEXP (x
, 0, 0), flags
);
5893 return default_unspec_may_trap_p (x
, flags
);
5897 /* Parse the -mfixed-range= option string. */
5900 fix_range (const char *const_str
)
5903 char *str
, *dash
, *comma
;
5905 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5906 REG2 are either register names or register numbers. The effect
5907 of this option is to mark the registers in the range from REG1 to
5908 REG2 as ``fixed'' so they won't be used by the compiler. This is
5909 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5911 i
= strlen (const_str
);
5912 str
= (char *) alloca (i
+ 1);
5913 memcpy (str
, const_str
, i
+ 1);
5917 dash
= strchr (str
, '-');
5920 warning (0, "value of -mfixed-range must have form REG1-REG2");
5925 comma
= strchr (dash
+ 1, ',');
5929 first
= decode_reg_name (str
);
5932 warning (0, "unknown register name: %s", str
);
5936 last
= decode_reg_name (dash
+ 1);
5939 warning (0, "unknown register name: %s", dash
+ 1);
5947 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
5951 for (i
= first
; i
<= last
; ++i
)
5952 fixed_regs
[i
] = call_used_regs
[i
] = 1;
5962 /* Implement TARGET_OPTION_OVERRIDE. */
5965 ia64_option_override (void)
5968 cl_deferred_option
*opt
;
5969 vec
<cl_deferred_option
> *v
5970 = (vec
<cl_deferred_option
> *) ia64_deferred_options
;
5973 FOR_EACH_VEC_ELT (*v
, i
, opt
)
5975 switch (opt
->opt_index
)
5977 case OPT_mfixed_range_
:
5978 fix_range (opt
->arg
);
5986 if (TARGET_AUTO_PIC
)
5987 target_flags
|= MASK_CONST_GP
;
5989 /* Numerous experiment shows that IRA based loop pressure
5990 calculation works better for RTL loop invariant motion on targets
5991 with enough (>= 32) registers. It is an expensive optimization.
5992 So it is on only for peak performance. */
5994 flag_ira_loop_pressure
= 1;
5997 ia64_section_threshold
= (global_options_set
.x_g_switch_value
5999 : IA64_DEFAULT_GVALUE
);
6001 init_machine_status
= ia64_init_machine_status
;
6003 if (align_functions
<= 0)
6004 align_functions
= 64;
6005 if (align_loops
<= 0)
6007 if (TARGET_ABI_OPEN_VMS
)
6010 ia64_override_options_after_change();
6013 /* Implement targetm.override_options_after_change. */
6016 ia64_override_options_after_change (void)
6019 && !global_options_set
.x_flag_selective_scheduling
6020 && !global_options_set
.x_flag_selective_scheduling2
)
6022 flag_selective_scheduling2
= 1;
6023 flag_sel_sched_pipelining
= 1;
6025 if (mflag_sched_control_spec
== 2)
6027 /* Control speculation is on by default for the selective scheduler,
6028 but not for the Haifa scheduler. */
6029 mflag_sched_control_spec
= flag_selective_scheduling2
? 1 : 0;
6031 if (flag_sel_sched_pipelining
&& flag_auto_inc_dec
)
6033 /* FIXME: remove this when we'd implement breaking autoinsns as
6034 a transformation. */
6035 flag_auto_inc_dec
= 0;
6039 /* Initialize the record of emitted frame related registers. */
6041 void ia64_init_expanders (void)
6043 memset (&emitted_frame_related_regs
, 0, sizeof (emitted_frame_related_regs
));
6046 static struct machine_function
*
6047 ia64_init_machine_status (void)
6049 return ggc_alloc_cleared_machine_function ();
6052 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
6053 static enum attr_type
ia64_safe_type (rtx
);
6055 static enum attr_itanium_class
6056 ia64_safe_itanium_class (rtx insn
)
6058 if (recog_memoized (insn
) >= 0)
6059 return get_attr_itanium_class (insn
);
6060 else if (DEBUG_INSN_P (insn
))
6061 return ITANIUM_CLASS_IGNORE
;
6063 return ITANIUM_CLASS_UNKNOWN
;
6066 static enum attr_type
6067 ia64_safe_type (rtx insn
)
6069 if (recog_memoized (insn
) >= 0)
6070 return get_attr_type (insn
);
6072 return TYPE_UNKNOWN
;
6075 /* The following collection of routines emit instruction group stop bits as
6076 necessary to avoid dependencies. */
6078 /* Need to track some additional registers as far as serialization is
6079 concerned so we can properly handle br.call and br.ret. We could
6080 make these registers visible to gcc, but since these registers are
6081 never explicitly used in gcc generated code, it seems wasteful to
6082 do so (plus it would make the call and return patterns needlessly
6084 #define REG_RP (BR_REG (0))
6085 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
6086 /* This is used for volatile asms which may require a stop bit immediately
6087 before and after them. */
6088 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
6089 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
6090 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
6092 /* For each register, we keep track of how it has been written in the
6093 current instruction group.
6095 If a register is written unconditionally (no qualifying predicate),
6096 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
6098 If a register is written if its qualifying predicate P is true, we
6099 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
6100 may be written again by the complement of P (P^1) and when this happens,
6101 WRITE_COUNT gets set to 2.
6103 The result of this is that whenever an insn attempts to write a register
6104 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
6106 If a predicate register is written by a floating-point insn, we set
6107 WRITTEN_BY_FP to true.
6109 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
6110 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
6112 #if GCC_VERSION >= 4000
6113 #define RWS_FIELD_TYPE __extension__ unsigned short
6115 #define RWS_FIELD_TYPE unsigned int
6117 struct reg_write_state
6119 RWS_FIELD_TYPE write_count
: 2;
6120 RWS_FIELD_TYPE first_pred
: 10;
6121 RWS_FIELD_TYPE written_by_fp
: 1;
6122 RWS_FIELD_TYPE written_by_and
: 1;
6123 RWS_FIELD_TYPE written_by_or
: 1;
6126 /* Cumulative info for the current instruction group. */
6127 struct reg_write_state rws_sum
[NUM_REGS
];
6128 #ifdef ENABLE_CHECKING
6129 /* Bitmap whether a register has been written in the current insn. */
6130 HARD_REG_ELT_TYPE rws_insn
[(NUM_REGS
+ HOST_BITS_PER_WIDEST_FAST_INT
- 1)
6131 / HOST_BITS_PER_WIDEST_FAST_INT
];
6134 rws_insn_set (int regno
)
6136 gcc_assert (!TEST_HARD_REG_BIT (rws_insn
, regno
));
6137 SET_HARD_REG_BIT (rws_insn
, regno
);
6141 rws_insn_test (int regno
)
6143 return TEST_HARD_REG_BIT (rws_insn
, regno
);
6146 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
6147 unsigned char rws_insn
[2];
6150 rws_insn_set (int regno
)
6152 if (regno
== REG_AR_CFM
)
6154 else if (regno
== REG_VOLATILE
)
6159 rws_insn_test (int regno
)
6161 if (regno
== REG_AR_CFM
)
6163 if (regno
== REG_VOLATILE
)
6169 /* Indicates whether this is the first instruction after a stop bit,
6170 in which case we don't need another stop bit. Without this,
6171 ia64_variable_issue will die when scheduling an alloc. */
6172 static int first_instruction
;
6174 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
6175 RTL for one instruction. */
6178 unsigned int is_write
: 1; /* Is register being written? */
6179 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
6180 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
6181 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
6182 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
6183 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
6186 static void rws_update (int, struct reg_flags
, int);
6187 static int rws_access_regno (int, struct reg_flags
, int);
6188 static int rws_access_reg (rtx
, struct reg_flags
, int);
6189 static void update_set_flags (rtx
, struct reg_flags
*);
6190 static int set_src_needs_barrier (rtx
, struct reg_flags
, int);
6191 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
6192 static void init_insn_group_barriers (void);
6193 static int group_barrier_needed (rtx
);
6194 static int safe_group_barrier_needed (rtx
);
6195 static int in_safe_group_barrier
;
6197 /* Update *RWS for REGNO, which is being written by the current instruction,
6198 with predicate PRED, and associated register flags in FLAGS. */
6201 rws_update (int regno
, struct reg_flags flags
, int pred
)
6204 rws_sum
[regno
].write_count
++;
6206 rws_sum
[regno
].write_count
= 2;
6207 rws_sum
[regno
].written_by_fp
|= flags
.is_fp
;
6208 /* ??? Not tracking and/or across differing predicates. */
6209 rws_sum
[regno
].written_by_and
= flags
.is_and
;
6210 rws_sum
[regno
].written_by_or
= flags
.is_or
;
6211 rws_sum
[regno
].first_pred
= pred
;
6214 /* Handle an access to register REGNO of type FLAGS using predicate register
6215 PRED. Update rws_sum array. Return 1 if this access creates
6216 a dependency with an earlier instruction in the same group. */
6219 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
6221 int need_barrier
= 0;
6223 gcc_assert (regno
< NUM_REGS
);
6225 if (! PR_REGNO_P (regno
))
6226 flags
.is_and
= flags
.is_or
= 0;
6232 rws_insn_set (regno
);
6233 write_count
= rws_sum
[regno
].write_count
;
6235 switch (write_count
)
6238 /* The register has not been written yet. */
6239 if (!in_safe_group_barrier
)
6240 rws_update (regno
, flags
, pred
);
6244 /* The register has been written via a predicate. Treat
6245 it like a unconditional write and do not try to check
6246 for complementary pred reg in earlier write. */
6247 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6249 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6253 if (!in_safe_group_barrier
)
6254 rws_update (regno
, flags
, pred
);
6258 /* The register has been unconditionally written already. We
6260 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6262 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6266 if (!in_safe_group_barrier
)
6268 rws_sum
[regno
].written_by_and
= flags
.is_and
;
6269 rws_sum
[regno
].written_by_or
= flags
.is_or
;
6279 if (flags
.is_branch
)
6281 /* Branches have several RAW exceptions that allow to avoid
6284 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
6285 /* RAW dependencies on branch regs are permissible as long
6286 as the writer is a non-branch instruction. Since we
6287 never generate code that uses a branch register written
6288 by a branch instruction, handling this case is
6292 if (REGNO_REG_CLASS (regno
) == PR_REGS
6293 && ! rws_sum
[regno
].written_by_fp
)
6294 /* The predicates of a branch are available within the
6295 same insn group as long as the predicate was written by
6296 something other than a floating-point instruction. */
6300 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6302 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6305 switch (rws_sum
[regno
].write_count
)
6308 /* The register has not been written yet. */
6312 /* The register has been written via a predicate, assume we
6313 need a barrier (don't check for complementary regs). */
6318 /* The register has been unconditionally written already. We
6328 return need_barrier
;
6332 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
6334 int regno
= REGNO (reg
);
6335 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
6338 return rws_access_regno (regno
, flags
, pred
);
6341 int need_barrier
= 0;
6343 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
6344 return need_barrier
;
6348 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6349 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6352 update_set_flags (rtx x
, struct reg_flags
*pflags
)
6354 rtx src
= SET_SRC (x
);
6356 switch (GET_CODE (src
))
6362 /* There are four cases here:
6363 (1) The destination is (pc), in which case this is a branch,
6364 nothing here applies.
6365 (2) The destination is ar.lc, in which case this is a
6366 doloop_end_internal,
6367 (3) The destination is an fp register, in which case this is
6368 an fselect instruction.
6369 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6370 this is a check load.
6371 In all cases, nothing we do in this function applies. */
6375 if (COMPARISON_P (src
)
6376 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src
, 0))))
6377 /* Set pflags->is_fp to 1 so that we know we're dealing
6378 with a floating point comparison when processing the
6379 destination of the SET. */
6382 /* Discover if this is a parallel comparison. We only handle
6383 and.orcm and or.andcm at present, since we must retain a
6384 strict inverse on the predicate pair. */
6385 else if (GET_CODE (src
) == AND
)
6387 else if (GET_CODE (src
) == IOR
)
6394 /* Subroutine of rtx_needs_barrier; this function determines whether the
6395 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6396 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6400 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6402 int need_barrier
= 0;
6404 rtx src
= SET_SRC (x
);
6406 if (GET_CODE (src
) == CALL
)
6407 /* We don't need to worry about the result registers that
6408 get written by subroutine call. */
6409 return rtx_needs_barrier (src
, flags
, pred
);
6410 else if (SET_DEST (x
) == pc_rtx
)
6412 /* X is a conditional branch. */
6413 /* ??? This seems redundant, as the caller sets this bit for
6415 if (!ia64_spec_check_src_p (src
))
6416 flags
.is_branch
= 1;
6417 return rtx_needs_barrier (src
, flags
, pred
);
6420 if (ia64_spec_check_src_p (src
))
6421 /* Avoid checking one register twice (in condition
6422 and in 'then' section) for ldc pattern. */
6424 gcc_assert (REG_P (XEXP (src
, 2)));
6425 need_barrier
= rtx_needs_barrier (XEXP (src
, 2), flags
, pred
);
6427 /* We process MEM below. */
6428 src
= XEXP (src
, 1);
6431 need_barrier
|= rtx_needs_barrier (src
, flags
, pred
);
6434 if (GET_CODE (dst
) == ZERO_EXTRACT
)
6436 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
6437 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
6439 return need_barrier
;
6442 /* Handle an access to rtx X of type FLAGS using predicate register
6443 PRED. Return 1 if this access creates a dependency with an earlier
6444 instruction in the same group. */
6447 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6450 int is_complemented
= 0;
6451 int need_barrier
= 0;
6452 const char *format_ptr
;
6453 struct reg_flags new_flags
;
6461 switch (GET_CODE (x
))
6464 update_set_flags (x
, &new_flags
);
6465 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
);
6466 if (GET_CODE (SET_SRC (x
)) != CALL
)
6468 new_flags
.is_write
= 1;
6469 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
6474 new_flags
.is_write
= 0;
6475 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6477 /* Avoid multiple register writes, in case this is a pattern with
6478 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6479 if (! flags
.is_sibcall
&& ! rws_insn_test (REG_AR_CFM
))
6481 new_flags
.is_write
= 1;
6482 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
6483 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
6484 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6489 /* X is a predicated instruction. */
6491 cond
= COND_EXEC_TEST (x
);
6493 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
6495 if (GET_CODE (cond
) == EQ
)
6496 is_complemented
= 1;
6497 cond
= XEXP (cond
, 0);
6498 gcc_assert (GET_CODE (cond
) == REG
6499 && REGNO_REG_CLASS (REGNO (cond
)) == PR_REGS
);
6500 pred
= REGNO (cond
);
6501 if (is_complemented
)
6504 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
6505 return need_barrier
;
6509 /* Clobber & use are for earlier compiler-phases only. */
6514 /* We always emit stop bits for traditional asms. We emit stop bits
6515 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6516 if (GET_CODE (x
) != ASM_OPERANDS
6517 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
6519 /* Avoid writing the register multiple times if we have multiple
6520 asm outputs. This avoids a failure in rws_access_reg. */
6521 if (! rws_insn_test (REG_VOLATILE
))
6523 new_flags
.is_write
= 1;
6524 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
6529 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6530 We cannot just fall through here since then we would be confused
6531 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6532 traditional asms unlike their normal usage. */
6534 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
6535 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
6540 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6542 rtx pat
= XVECEXP (x
, 0, i
);
6543 switch (GET_CODE (pat
))
6546 update_set_flags (pat
, &new_flags
);
6547 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
);
6553 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6557 if (REG_P (XEXP (pat
, 0))
6558 && extract_asm_operands (x
) != NULL_RTX
6559 && REGNO (XEXP (pat
, 0)) != AR_UNAT_REGNUM
)
6561 new_flags
.is_write
= 1;
6562 need_barrier
|= rtx_needs_barrier (XEXP (pat
, 0),
6575 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6577 rtx pat
= XVECEXP (x
, 0, i
);
6578 if (GET_CODE (pat
) == SET
)
6580 if (GET_CODE (SET_SRC (pat
)) != CALL
)
6582 new_flags
.is_write
= 1;
6583 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
6587 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
6588 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6593 need_barrier
|= rtx_needs_barrier (SUBREG_REG (x
), flags
, pred
);
6596 if (REGNO (x
) == AR_UNAT_REGNUM
)
6598 for (i
= 0; i
< 64; ++i
)
6599 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
6602 need_barrier
= rws_access_reg (x
, flags
, pred
);
6606 /* Find the regs used in memory address computation. */
6607 new_flags
.is_write
= 0;
6608 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6611 case CONST_INT
: case CONST_DOUBLE
: case CONST_VECTOR
:
6612 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
6615 /* Operators with side-effects. */
6616 case POST_INC
: case POST_DEC
:
6617 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6619 new_flags
.is_write
= 0;
6620 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6621 new_flags
.is_write
= 1;
6622 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6626 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6628 new_flags
.is_write
= 0;
6629 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6630 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6631 new_flags
.is_write
= 1;
6632 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6635 /* Handle common unary and binary ops for efficiency. */
6636 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
6637 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
6638 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
6639 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
6640 case NE
: case EQ
: case GE
: case GT
: case LE
:
6641 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
6642 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6643 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6646 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
6647 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
6648 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
6649 case SQRT
: case FFS
: case POPCOUNT
:
6650 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6654 /* VEC_SELECT's second argument is a PARALLEL with integers that
6655 describe the elements selected. On ia64, those integers are
6656 always constants. Avoid walking the PARALLEL so that we don't
6657 get confused with "normal" parallels and then die. */
6658 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6662 switch (XINT (x
, 1))
6664 case UNSPEC_LTOFF_DTPMOD
:
6665 case UNSPEC_LTOFF_DTPREL
:
6667 case UNSPEC_LTOFF_TPREL
:
6669 case UNSPEC_PRED_REL_MUTEX
:
6670 case UNSPEC_PIC_CALL
:
6672 case UNSPEC_FETCHADD_ACQ
:
6673 case UNSPEC_FETCHADD_REL
:
6674 case UNSPEC_BSP_VALUE
:
6675 case UNSPEC_FLUSHRS
:
6676 case UNSPEC_BUNDLE_SELECTOR
:
6679 case UNSPEC_GR_SPILL
:
6680 case UNSPEC_GR_RESTORE
:
6682 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
6683 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
6685 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6686 new_flags
.is_write
= (XINT (x
, 1) == UNSPEC_GR_SPILL
);
6687 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
6692 case UNSPEC_FR_SPILL
:
6693 case UNSPEC_FR_RESTORE
:
6694 case UNSPEC_GETF_EXP
:
6695 case UNSPEC_SETF_EXP
:
6697 case UNSPEC_FR_SQRT_RECIP_APPROX
:
6698 case UNSPEC_FR_SQRT_RECIP_APPROX_RES
:
6703 case UNSPEC_CHKACLR
:
6705 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6708 case UNSPEC_FR_RECIP_APPROX
:
6710 case UNSPEC_COPYSIGN
:
6711 case UNSPEC_FR_RECIP_APPROX_RES
:
6712 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6713 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6716 case UNSPEC_CMPXCHG_ACQ
:
6717 case UNSPEC_CMPXCHG_REL
:
6718 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6719 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
6727 case UNSPEC_VOLATILE
:
6728 switch (XINT (x
, 1))
6731 /* Alloc must always be the first instruction of a group.
6732 We force this by always returning true. */
6733 /* ??? We might get better scheduling if we explicitly check for
6734 input/local/output register dependencies, and modify the
6735 scheduler so that alloc is always reordered to the start of
6736 the current group. We could then eliminate all of the
6737 first_instruction code. */
6738 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6740 new_flags
.is_write
= 1;
6741 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6744 case UNSPECV_SET_BSP
:
6745 case UNSPECV_PROBE_STACK_RANGE
:
6749 case UNSPECV_BLOCKAGE
:
6750 case UNSPECV_INSN_GROUP_BARRIER
:
6752 case UNSPECV_PSAC_ALL
:
6753 case UNSPECV_PSAC_NORMAL
:
6756 case UNSPECV_PROBE_STACK_ADDRESS
:
6757 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6766 new_flags
.is_write
= 0;
6767 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
6768 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6770 new_flags
.is_write
= 1;
6771 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6772 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6776 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
6777 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6778 switch (format_ptr
[i
])
6780 case '0': /* unused field */
6781 case 'i': /* integer */
6782 case 'n': /* note */
6783 case 'w': /* wide integer */
6784 case 's': /* pointer to string */
6785 case 'S': /* optional pointer to string */
6789 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
6794 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
6795 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
6804 return need_barrier
;
6807 /* Clear out the state for group_barrier_needed at the start of a
6808 sequence of insns. */
6811 init_insn_group_barriers (void)
6813 memset (rws_sum
, 0, sizeof (rws_sum
));
6814 first_instruction
= 1;
6817 /* Given the current state, determine whether a group barrier (a stop bit) is
6818 necessary before INSN. Return nonzero if so. This modifies the state to
6819 include the effects of INSN as a side-effect. */
6822 group_barrier_needed (rtx insn
)
6825 int need_barrier
= 0;
6826 struct reg_flags flags
;
6828 memset (&flags
, 0, sizeof (flags
));
6829 switch (GET_CODE (insn
))
6836 /* A barrier doesn't imply an instruction group boundary. */
6840 memset (rws_insn
, 0, sizeof (rws_insn
));
6844 flags
.is_branch
= 1;
6845 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
6846 memset (rws_insn
, 0, sizeof (rws_insn
));
6848 /* Don't bundle a call following another call. */
6849 if ((pat
= prev_active_insn (insn
)) && CALL_P (pat
))
6855 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
6859 if (!ia64_spec_check_p (insn
))
6860 flags
.is_branch
= 1;
6862 /* Don't bundle a jump following a call. */
6863 if ((pat
= prev_active_insn (insn
)) && CALL_P (pat
))
6871 if (GET_CODE (PATTERN (insn
)) == USE
6872 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6873 /* Don't care about USE and CLOBBER "insns"---those are used to
6874 indicate to the optimizer that it shouldn't get rid of
6875 certain operations. */
6878 pat
= PATTERN (insn
);
6880 /* Ug. Hack hacks hacked elsewhere. */
6881 switch (recog_memoized (insn
))
6883 /* We play dependency tricks with the epilogue in order
6884 to get proper schedules. Undo this for dv analysis. */
6885 case CODE_FOR_epilogue_deallocate_stack
:
6886 case CODE_FOR_prologue_allocate_stack
:
6887 pat
= XVECEXP (pat
, 0, 0);
6890 /* The pattern we use for br.cloop confuses the code above.
6891 The second element of the vector is representative. */
6892 case CODE_FOR_doloop_end_internal
:
6893 pat
= XVECEXP (pat
, 0, 1);
6896 /* Doesn't generate code. */
6897 case CODE_FOR_pred_rel_mutex
:
6898 case CODE_FOR_prologue_use
:
6905 memset (rws_insn
, 0, sizeof (rws_insn
));
6906 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
6908 /* Check to see if the previous instruction was a volatile
6911 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
6919 if (first_instruction
&& important_for_bundling_p (insn
))
6922 first_instruction
= 0;
6925 return need_barrier
;
6928 /* Like group_barrier_needed, but do not clobber the current state. */
6931 safe_group_barrier_needed (rtx insn
)
6933 int saved_first_instruction
;
6936 saved_first_instruction
= first_instruction
;
6937 in_safe_group_barrier
= 1;
6939 t
= group_barrier_needed (insn
);
6941 first_instruction
= saved_first_instruction
;
6942 in_safe_group_barrier
= 0;
6947 /* Scan the current function and insert stop bits as necessary to
6948 eliminate dependencies. This function assumes that a final
6949 instruction scheduling pass has been run which has already
6950 inserted most of the necessary stop bits. This function only
6951 inserts new ones at basic block boundaries, since these are
6952 invisible to the scheduler. */
6955 emit_insn_group_barriers (FILE *dump
)
6959 int insns_since_last_label
= 0;
6961 init_insn_group_barriers ();
6963 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6967 if (insns_since_last_label
)
6969 insns_since_last_label
= 0;
6971 else if (NOTE_P (insn
)
6972 && NOTE_KIND (insn
) == NOTE_INSN_BASIC_BLOCK
)
6974 if (insns_since_last_label
)
6976 insns_since_last_label
= 0;
6978 else if (NONJUMP_INSN_P (insn
)
6979 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
6980 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
6982 init_insn_group_barriers ();
6985 else if (NONDEBUG_INSN_P (insn
))
6987 insns_since_last_label
= 1;
6989 if (group_barrier_needed (insn
))
6994 fprintf (dump
, "Emitting stop before label %d\n",
6995 INSN_UID (last_label
));
6996 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
6999 init_insn_group_barriers ();
7007 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
7008 This function has to emit all necessary group barriers. */
7011 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
7015 init_insn_group_barriers ();
7017 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7019 if (BARRIER_P (insn
))
7021 rtx last
= prev_active_insn (insn
);
7025 if (JUMP_TABLE_DATA_P (last
))
7026 last
= prev_active_insn (last
);
7027 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7028 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
7030 init_insn_group_barriers ();
7032 else if (NONDEBUG_INSN_P (insn
))
7034 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
7035 init_insn_group_barriers ();
7036 else if (group_barrier_needed (insn
))
7038 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
7039 init_insn_group_barriers ();
7040 group_barrier_needed (insn
);
7048 /* Instruction scheduling support. */
7050 #define NR_BUNDLES 10
7052 /* A list of names of all available bundles. */
7054 static const char *bundle_name
[NR_BUNDLES
] =
7060 #if NR_BUNDLES == 10
7070 /* Nonzero if we should insert stop bits into the schedule. */
7072 int ia64_final_schedule
= 0;
7074 /* Codes of the corresponding queried units: */
7076 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
7077 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
7079 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
7080 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
7082 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
7084 /* The following variable value is an insn group barrier. */
7086 static rtx dfa_stop_insn
;
7088 /* The following variable value is the last issued insn. */
7090 static rtx last_scheduled_insn
;
7092 /* The following variable value is pointer to a DFA state used as
7093 temporary variable. */
7095 static state_t temp_dfa_state
= NULL
;
7097 /* The following variable value is DFA state after issuing the last
7100 static state_t prev_cycle_state
= NULL
;
7102 /* The following array element values are TRUE if the corresponding
7103 insn requires to add stop bits before it. */
7105 static char *stops_p
= NULL
;
7107 /* The following variable is used to set up the mentioned above array. */
7109 static int stop_before_p
= 0;
7111 /* The following variable value is length of the arrays `clocks' and
7114 static int clocks_length
;
7116 /* The following variable value is number of data speculations in progress. */
7117 static int pending_data_specs
= 0;
7119 /* Number of memory references on current and three future processor cycles. */
7120 static char mem_ops_in_group
[4];
7122 /* Number of current processor cycle (from scheduler's point of view). */
7123 static int current_cycle
;
7125 static rtx
ia64_single_set (rtx
);
7126 static void ia64_emit_insn_before (rtx
, rtx
);
7128 /* Map a bundle number to its pseudo-op. */
7131 get_bundle_name (int b
)
7133 return bundle_name
[b
];
7137 /* Return the maximum number of instructions a cpu can issue. */
7140 ia64_issue_rate (void)
7145 /* Helper function - like single_set, but look inside COND_EXEC. */
7148 ia64_single_set (rtx insn
)
7150 rtx x
= PATTERN (insn
), ret
;
7151 if (GET_CODE (x
) == COND_EXEC
)
7152 x
= COND_EXEC_CODE (x
);
7153 if (GET_CODE (x
) == SET
)
7156 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
7157 Although they are not classical single set, the second set is there just
7158 to protect it from moving past FP-relative stack accesses. */
7159 switch (recog_memoized (insn
))
7161 case CODE_FOR_prologue_allocate_stack
:
7162 case CODE_FOR_prologue_allocate_stack_pr
:
7163 case CODE_FOR_epilogue_deallocate_stack
:
7164 case CODE_FOR_epilogue_deallocate_stack_pr
:
7165 ret
= XVECEXP (x
, 0, 0);
7169 ret
= single_set_2 (insn
, x
);
7176 /* Adjust the cost of a scheduling dependency.
7177 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
7178 COST is the current cost, DW is dependency weakness. */
7180 ia64_adjust_cost_2 (rtx insn
, int dep_type1
, rtx dep_insn
, int cost
, dw_t dw
)
7182 enum reg_note dep_type
= (enum reg_note
) dep_type1
;
7183 enum attr_itanium_class dep_class
;
7184 enum attr_itanium_class insn_class
;
7186 insn_class
= ia64_safe_itanium_class (insn
);
7187 dep_class
= ia64_safe_itanium_class (dep_insn
);
7189 /* Treat true memory dependencies separately. Ignore apparent true
7190 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
7191 if (dep_type
== REG_DEP_TRUE
7192 && (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
)
7193 && (insn_class
== ITANIUM_CLASS_BR
|| insn_class
== ITANIUM_CLASS_SCALL
))
7196 if (dw
== MIN_DEP_WEAK
)
7197 /* Store and load are likely to alias, use higher cost to avoid stall. */
7198 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST
);
7199 else if (dw
> MIN_DEP_WEAK
)
7201 /* Store and load are less likely to alias. */
7202 if (mflag_sched_fp_mem_deps_zero_cost
&& dep_class
== ITANIUM_CLASS_STF
)
7203 /* Assume there will be no cache conflict for floating-point data.
7204 For integer data, L1 conflict penalty is huge (17 cycles), so we
7205 never assume it will not cause a conflict. */
7211 if (dep_type
!= REG_DEP_OUTPUT
)
7214 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
7215 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
7221 /* Like emit_insn_before, but skip cycle_display notes.
7222 ??? When cycle display notes are implemented, update this. */
7225 ia64_emit_insn_before (rtx insn
, rtx before
)
7227 emit_insn_before (insn
, before
);
7230 /* The following function marks insns who produce addresses for load
7231 and store insns. Such insns will be placed into M slots because it
7232 decrease latency time for Itanium1 (see function
7233 `ia64_produce_address_p' and the DFA descriptions). */
7236 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
7238 rtx insn
, next
, next_tail
;
7240 /* Before reload, which_alternative is not set, which means that
7241 ia64_safe_itanium_class will produce wrong results for (at least)
7242 move instructions. */
7243 if (!reload_completed
)
7246 next_tail
= NEXT_INSN (tail
);
7247 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
7250 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
7252 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
7254 sd_iterator_def sd_it
;
7256 bool has_mem_op_consumer_p
= false;
7258 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
7260 enum attr_itanium_class c
;
7262 if (DEP_TYPE (dep
) != REG_DEP_TRUE
)
7265 next
= DEP_CON (dep
);
7266 c
= ia64_safe_itanium_class (next
);
7267 if ((c
== ITANIUM_CLASS_ST
7268 || c
== ITANIUM_CLASS_STF
)
7269 && ia64_st_address_bypass_p (insn
, next
))
7271 has_mem_op_consumer_p
= true;
7274 else if ((c
== ITANIUM_CLASS_LD
7275 || c
== ITANIUM_CLASS_FLD
7276 || c
== ITANIUM_CLASS_FLDP
)
7277 && ia64_ld_address_bypass_p (insn
, next
))
7279 has_mem_op_consumer_p
= true;
7284 insn
->call
= has_mem_op_consumer_p
;
7288 /* We're beginning a new block. Initialize data structures as necessary. */
7291 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7292 int sched_verbose ATTRIBUTE_UNUSED
,
7293 int max_ready ATTRIBUTE_UNUSED
)
7295 #ifdef ENABLE_CHECKING
7298 if (!sel_sched_p () && reload_completed
)
7299 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7300 insn
!= current_sched_info
->next_tail
;
7301 insn
= NEXT_INSN (insn
))
7302 gcc_assert (!SCHED_GROUP_P (insn
));
7304 last_scheduled_insn
= NULL_RTX
;
7305 init_insn_group_barriers ();
7308 memset (mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7311 /* We're beginning a scheduling pass. Check assertion. */
7314 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED
,
7315 int sched_verbose ATTRIBUTE_UNUSED
,
7316 int max_ready ATTRIBUTE_UNUSED
)
7318 gcc_assert (pending_data_specs
== 0);
7321 /* Scheduling pass is now finished. Free/reset static variable. */
7323 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
7324 int sched_verbose ATTRIBUTE_UNUSED
)
7326 gcc_assert (pending_data_specs
== 0);
7329 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7330 speculation check), FALSE otherwise. */
7332 is_load_p (rtx insn
)
7334 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
7337 ((insn_class
== ITANIUM_CLASS_LD
|| insn_class
== ITANIUM_CLASS_FLD
)
7338 && get_attr_check_load (insn
) == CHECK_LOAD_NO
);
7341 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7342 (taking account for 3-cycle cache reference postponing for stores: Intel
7343 Itanium 2 Reference Manual for Software Development and Optimization,
7346 record_memory_reference (rtx insn
)
7348 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
7350 switch (insn_class
) {
7351 case ITANIUM_CLASS_FLD
:
7352 case ITANIUM_CLASS_LD
:
7353 mem_ops_in_group
[current_cycle
% 4]++;
7355 case ITANIUM_CLASS_STF
:
7356 case ITANIUM_CLASS_ST
:
7357 mem_ops_in_group
[(current_cycle
+ 3) % 4]++;
7363 /* We are about to being issuing insns for this clock cycle.
7364 Override the default sort algorithm to better slot instructions. */
7367 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
7368 int *pn_ready
, int clock_var
,
7372 int n_ready
= *pn_ready
;
7373 rtx
*e_ready
= ready
+ n_ready
;
7377 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
7379 if (reorder_type
== 0)
7381 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7383 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7384 if (insnp
< e_ready
)
7387 enum attr_type t
= ia64_safe_type (insn
);
7388 if (t
== TYPE_UNKNOWN
)
7390 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
7391 || asm_noperands (PATTERN (insn
)) >= 0)
7393 rtx lowest
= ready
[n_asms
];
7394 ready
[n_asms
] = insn
;
7400 rtx highest
= ready
[n_ready
- 1];
7401 ready
[n_ready
- 1] = insn
;
7408 if (n_asms
< n_ready
)
7410 /* Some normal insns to process. Skip the asms. */
7414 else if (n_ready
> 0)
7418 if (ia64_final_schedule
)
7421 int nr_need_stop
= 0;
7423 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7424 if (safe_group_barrier_needed (*insnp
))
7427 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
7429 if (reorder_type
== 0)
7432 /* Move down everything that needs a stop bit, preserving
7434 while (insnp
-- > ready
+ deleted
)
7435 while (insnp
>= ready
+ deleted
)
7438 if (! safe_group_barrier_needed (insn
))
7440 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7448 current_cycle
= clock_var
;
7449 if (reload_completed
&& mem_ops_in_group
[clock_var
% 4] >= ia64_max_memory_insns
)
7454 /* Move down loads/stores, preserving relative order. */
7455 while (insnp
-- > ready
+ moved
)
7456 while (insnp
>= ready
+ moved
)
7459 if (! is_load_p (insn
))
7461 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7472 /* We are about to being issuing insns for this clock cycle. Override
7473 the default sort algorithm to better slot instructions. */
7476 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
7479 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
7480 pn_ready
, clock_var
, 0);
7483 /* Like ia64_sched_reorder, but called after issuing each insn.
7484 Override the default sort algorithm to better slot instructions. */
7487 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
7488 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
7489 int *pn_ready
, int clock_var
)
7491 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
7495 /* We are about to issue INSN. Return the number of insns left on the
7496 ready queue that can be issued this cycle. */
7499 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
7500 int sched_verbose ATTRIBUTE_UNUSED
,
7501 rtx insn ATTRIBUTE_UNUSED
,
7502 int can_issue_more ATTRIBUTE_UNUSED
)
7504 if (sched_deps_info
->generate_spec_deps
&& !sel_sched_p ())
7505 /* Modulo scheduling does not extend h_i_d when emitting
7506 new instructions. Don't use h_i_d, if we don't have to. */
7508 if (DONE_SPEC (insn
) & BEGIN_DATA
)
7509 pending_data_specs
++;
7510 if (CHECK_SPEC (insn
) & BEGIN_DATA
)
7511 pending_data_specs
--;
7514 if (DEBUG_INSN_P (insn
))
7517 last_scheduled_insn
= insn
;
7518 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
7519 if (reload_completed
)
7521 int needed
= group_barrier_needed (insn
);
7523 gcc_assert (!needed
);
7525 init_insn_group_barriers ();
7526 stops_p
[INSN_UID (insn
)] = stop_before_p
;
7529 record_memory_reference (insn
);
7534 /* We are choosing insn from the ready queue. Return nonzero if INSN
7538 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
7540 gcc_assert (insn
&& INSN_P (insn
));
7541 return ((!reload_completed
7542 || !safe_group_barrier_needed (insn
))
7543 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn
)
7544 && (!mflag_sched_mem_insns_hard_limit
7545 || !is_load_p (insn
)
7546 || mem_ops_in_group
[current_cycle
% 4] < ia64_max_memory_insns
));
7549 /* We are choosing insn from the ready queue. Return nonzero if INSN
7553 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn
)
7555 gcc_assert (insn
&& INSN_P (insn
));
7556 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7557 we keep ALAT half-empty. */
7558 return (pending_data_specs
< 16
7559 || !(TODO_SPEC (insn
) & BEGIN_DATA
));
7562 /* The following variable value is pseudo-insn used by the DFA insn
7563 scheduler to change the DFA state when the simulated clock is
7566 static rtx dfa_pre_cycle_insn
;
7568 /* Returns 1 when a meaningful insn was scheduled between the last group
7569 barrier and LAST. */
7571 scheduled_good_insn (rtx last
)
7573 if (last
&& recog_memoized (last
) >= 0)
7577 last
!= NULL
&& !NOTE_INSN_BASIC_BLOCK_P (last
)
7578 && !stops_p
[INSN_UID (last
)];
7579 last
= PREV_INSN (last
))
7580 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7581 the ebb we're scheduling. */
7582 if (INSN_P (last
) && recog_memoized (last
) >= 0)
7588 /* We are about to being issuing INSN. Return nonzero if we cannot
7589 issue it on given cycle CLOCK and return zero if we should not sort
7590 the ready queue on the next clock start. */
7593 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
7594 int clock
, int *sort_p
)
7596 gcc_assert (insn
&& INSN_P (insn
));
7598 if (DEBUG_INSN_P (insn
))
7601 /* When a group barrier is needed for insn, last_scheduled_insn
7603 gcc_assert (!(reload_completed
&& safe_group_barrier_needed (insn
))
7604 || last_scheduled_insn
);
7606 if ((reload_completed
7607 && (safe_group_barrier_needed (insn
)
7608 || (mflag_sched_stop_bits_after_every_cycle
7609 && last_clock
!= clock
7610 && last_scheduled_insn
7611 && scheduled_good_insn (last_scheduled_insn
))))
7612 || (last_scheduled_insn
7613 && (CALL_P (last_scheduled_insn
)
7614 || unknown_for_bundling_p (last_scheduled_insn
))))
7616 init_insn_group_barriers ();
7618 if (verbose
&& dump
)
7619 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
7620 last_clock
== clock
? " + cycle advance" : "");
7623 current_cycle
= clock
;
7624 mem_ops_in_group
[current_cycle
% 4] = 0;
7626 if (last_clock
== clock
)
7628 state_transition (curr_state
, dfa_stop_insn
);
7629 if (TARGET_EARLY_STOP_BITS
)
7630 *sort_p
= (last_scheduled_insn
== NULL_RTX
7631 || ! CALL_P (last_scheduled_insn
));
7637 if (last_scheduled_insn
)
7639 if (unknown_for_bundling_p (last_scheduled_insn
))
7640 state_reset (curr_state
);
7643 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
7644 state_transition (curr_state
, dfa_stop_insn
);
7645 state_transition (curr_state
, dfa_pre_cycle_insn
);
7646 state_transition (curr_state
, NULL
);
7653 /* Implement targetm.sched.h_i_d_extended hook.
7654 Extend internal data structures. */
7656 ia64_h_i_d_extended (void)
7658 if (stops_p
!= NULL
)
7660 int new_clocks_length
= get_max_uid () * 3 / 2;
7661 stops_p
= (char *) xrecalloc (stops_p
, new_clocks_length
, clocks_length
, 1);
7662 clocks_length
= new_clocks_length
;
7667 /* This structure describes the data used by the backend to guide scheduling.
7668 When the current scheduling point is switched, this data should be saved
7669 and restored later, if the scheduler returns to this point. */
7670 struct _ia64_sched_context
7672 state_t prev_cycle_state
;
7673 rtx last_scheduled_insn
;
7674 struct reg_write_state rws_sum
[NUM_REGS
];
7675 struct reg_write_state rws_insn
[NUM_REGS
];
7676 int first_instruction
;
7677 int pending_data_specs
;
7679 char mem_ops_in_group
[4];
7681 typedef struct _ia64_sched_context
*ia64_sched_context_t
;
7683 /* Allocates a scheduling context. */
7685 ia64_alloc_sched_context (void)
7687 return xmalloc (sizeof (struct _ia64_sched_context
));
7690 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7691 the global context otherwise. */
7693 ia64_init_sched_context (void *_sc
, bool clean_p
)
7695 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7697 sc
->prev_cycle_state
= xmalloc (dfa_state_size
);
7700 state_reset (sc
->prev_cycle_state
);
7701 sc
->last_scheduled_insn
= NULL_RTX
;
7702 memset (sc
->rws_sum
, 0, sizeof (rws_sum
));
7703 memset (sc
->rws_insn
, 0, sizeof (rws_insn
));
7704 sc
->first_instruction
= 1;
7705 sc
->pending_data_specs
= 0;
7706 sc
->current_cycle
= 0;
7707 memset (sc
->mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7711 memcpy (sc
->prev_cycle_state
, prev_cycle_state
, dfa_state_size
);
7712 sc
->last_scheduled_insn
= last_scheduled_insn
;
7713 memcpy (sc
->rws_sum
, rws_sum
, sizeof (rws_sum
));
7714 memcpy (sc
->rws_insn
, rws_insn
, sizeof (rws_insn
));
7715 sc
->first_instruction
= first_instruction
;
7716 sc
->pending_data_specs
= pending_data_specs
;
7717 sc
->current_cycle
= current_cycle
;
7718 memcpy (sc
->mem_ops_in_group
, mem_ops_in_group
, sizeof (mem_ops_in_group
));
7722 /* Sets the global scheduling context to the one pointed to by _SC. */
7724 ia64_set_sched_context (void *_sc
)
7726 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7728 gcc_assert (sc
!= NULL
);
7730 memcpy (prev_cycle_state
, sc
->prev_cycle_state
, dfa_state_size
);
7731 last_scheduled_insn
= sc
->last_scheduled_insn
;
7732 memcpy (rws_sum
, sc
->rws_sum
, sizeof (rws_sum
));
7733 memcpy (rws_insn
, sc
->rws_insn
, sizeof (rws_insn
));
7734 first_instruction
= sc
->first_instruction
;
7735 pending_data_specs
= sc
->pending_data_specs
;
7736 current_cycle
= sc
->current_cycle
;
7737 memcpy (mem_ops_in_group
, sc
->mem_ops_in_group
, sizeof (mem_ops_in_group
));
7740 /* Clears the data in the _SC scheduling context. */
7742 ia64_clear_sched_context (void *_sc
)
7744 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7746 free (sc
->prev_cycle_state
);
7747 sc
->prev_cycle_state
= NULL
;
7750 /* Frees the _SC scheduling context. */
7752 ia64_free_sched_context (void *_sc
)
7754 gcc_assert (_sc
!= NULL
);
7759 typedef rtx (* gen_func_t
) (rtx
, rtx
);
7761 /* Return a function that will generate a load of mode MODE_NO
7762 with speculation types TS. */
7764 get_spec_load_gen_function (ds_t ts
, int mode_no
)
7766 static gen_func_t gen_ld_
[] = {
7776 gen_zero_extendqidi2
,
7777 gen_zero_extendhidi2
,
7778 gen_zero_extendsidi2
,
7781 static gen_func_t gen_ld_a
[] = {
7791 gen_zero_extendqidi2_advanced
,
7792 gen_zero_extendhidi2_advanced
,
7793 gen_zero_extendsidi2_advanced
,
7795 static gen_func_t gen_ld_s
[] = {
7796 gen_movbi_speculative
,
7797 gen_movqi_speculative
,
7798 gen_movhi_speculative
,
7799 gen_movsi_speculative
,
7800 gen_movdi_speculative
,
7801 gen_movsf_speculative
,
7802 gen_movdf_speculative
,
7803 gen_movxf_speculative
,
7804 gen_movti_speculative
,
7805 gen_zero_extendqidi2_speculative
,
7806 gen_zero_extendhidi2_speculative
,
7807 gen_zero_extendsidi2_speculative
,
7809 static gen_func_t gen_ld_sa
[] = {
7810 gen_movbi_speculative_advanced
,
7811 gen_movqi_speculative_advanced
,
7812 gen_movhi_speculative_advanced
,
7813 gen_movsi_speculative_advanced
,
7814 gen_movdi_speculative_advanced
,
7815 gen_movsf_speculative_advanced
,
7816 gen_movdf_speculative_advanced
,
7817 gen_movxf_speculative_advanced
,
7818 gen_movti_speculative_advanced
,
7819 gen_zero_extendqidi2_speculative_advanced
,
7820 gen_zero_extendhidi2_speculative_advanced
,
7821 gen_zero_extendsidi2_speculative_advanced
,
7823 static gen_func_t gen_ld_s_a
[] = {
7824 gen_movbi_speculative_a
,
7825 gen_movqi_speculative_a
,
7826 gen_movhi_speculative_a
,
7827 gen_movsi_speculative_a
,
7828 gen_movdi_speculative_a
,
7829 gen_movsf_speculative_a
,
7830 gen_movdf_speculative_a
,
7831 gen_movxf_speculative_a
,
7832 gen_movti_speculative_a
,
7833 gen_zero_extendqidi2_speculative_a
,
7834 gen_zero_extendhidi2_speculative_a
,
7835 gen_zero_extendsidi2_speculative_a
,
7840 if (ts
& BEGIN_DATA
)
7842 if (ts
& BEGIN_CONTROL
)
7847 else if (ts
& BEGIN_CONTROL
)
7849 if ((spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
)
7850 || ia64_needs_block_p (ts
))
7853 gen_ld
= gen_ld_s_a
;
7860 return gen_ld
[mode_no
];
7863 /* Constants that help mapping 'enum machine_mode' to int. */
7866 SPEC_MODE_INVALID
= -1,
7867 SPEC_MODE_FIRST
= 0,
7868 SPEC_MODE_FOR_EXTEND_FIRST
= 1,
7869 SPEC_MODE_FOR_EXTEND_LAST
= 3,
7875 /* Offset to reach ZERO_EXTEND patterns. */
7876 SPEC_GEN_EXTEND_OFFSET
= SPEC_MODE_LAST
- SPEC_MODE_FOR_EXTEND_FIRST
+ 1
7879 /* Return index of the MODE. */
7881 ia64_mode_to_int (enum machine_mode mode
)
7885 case BImode
: return 0; /* SPEC_MODE_FIRST */
7886 case QImode
: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7887 case HImode
: return 2;
7888 case SImode
: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7889 case DImode
: return 4;
7890 case SFmode
: return 5;
7891 case DFmode
: return 6;
7892 case XFmode
: return 7;
7894 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7895 mentioned in itanium[12].md. Predicate fp_register_operand also
7896 needs to be defined. Bottom line: better disable for now. */
7897 return SPEC_MODE_INVALID
;
7898 default: return SPEC_MODE_INVALID
;
7902 /* Provide information about speculation capabilities. */
7904 ia64_set_sched_flags (spec_info_t spec_info
)
7906 unsigned int *flags
= &(current_sched_info
->flags
);
7908 if (*flags
& SCHED_RGN
7909 || *flags
& SCHED_EBB
7910 || *flags
& SEL_SCHED
)
7914 if ((mflag_sched_br_data_spec
&& !reload_completed
&& optimize
> 0)
7915 || (mflag_sched_ar_data_spec
&& reload_completed
))
7920 && ((mflag_sched_br_in_data_spec
&& !reload_completed
)
7921 || (mflag_sched_ar_in_data_spec
&& reload_completed
)))
7925 if (mflag_sched_control_spec
7927 || reload_completed
))
7929 mask
|= BEGIN_CONTROL
;
7931 if (!sel_sched_p () && mflag_sched_in_control_spec
)
7932 mask
|= BE_IN_CONTROL
;
7935 spec_info
->mask
= mask
;
7939 *flags
|= USE_DEPS_LIST
| DO_SPECULATION
;
7941 if (mask
& BE_IN_SPEC
)
7944 spec_info
->flags
= 0;
7946 if ((mask
& DATA_SPEC
) && mflag_sched_prefer_non_data_spec_insns
)
7947 spec_info
->flags
|= PREFER_NON_DATA_SPEC
;
7949 if (mask
& CONTROL_SPEC
)
7951 if (mflag_sched_prefer_non_control_spec_insns
)
7952 spec_info
->flags
|= PREFER_NON_CONTROL_SPEC
;
7954 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec
)
7955 spec_info
->flags
|= SEL_SCHED_SPEC_DONT_CHECK_CONTROL
;
7958 if (sched_verbose
>= 1)
7959 spec_info
->dump
= sched_dump
;
7961 spec_info
->dump
= 0;
7963 if (mflag_sched_count_spec_in_critical_path
)
7964 spec_info
->flags
|= COUNT_SPEC_IN_CRITICAL_PATH
;
7968 spec_info
->mask
= 0;
7971 /* If INSN is an appropriate load return its mode.
7972 Return -1 otherwise. */
7974 get_mode_no_for_insn (rtx insn
)
7976 rtx reg
, mem
, mode_rtx
;
7980 extract_insn_cached (insn
);
7982 /* We use WHICH_ALTERNATIVE only after reload. This will
7983 guarantee that reload won't touch a speculative insn. */
7985 if (recog_data
.n_operands
!= 2)
7988 reg
= recog_data
.operand
[0];
7989 mem
= recog_data
.operand
[1];
7991 /* We should use MEM's mode since REG's mode in presence of
7992 ZERO_EXTEND will always be DImode. */
7993 if (get_attr_speculable1 (insn
) == SPECULABLE1_YES
)
7994 /* Process non-speculative ld. */
7996 if (!reload_completed
)
7998 /* Do not speculate into regs like ar.lc. */
7999 if (!REG_P (reg
) || AR_REGNO_P (REGNO (reg
)))
8006 rtx mem_reg
= XEXP (mem
, 0);
8008 if (!REG_P (mem_reg
))
8014 else if (get_attr_speculable2 (insn
) == SPECULABLE2_YES
)
8016 gcc_assert (REG_P (reg
) && MEM_P (mem
));
8022 else if (get_attr_data_speculative (insn
) == DATA_SPECULATIVE_YES
8023 || get_attr_control_speculative (insn
) == CONTROL_SPECULATIVE_YES
8024 || get_attr_check_load (insn
) == CHECK_LOAD_YES
)
8025 /* Process speculative ld or ld.c. */
8027 gcc_assert (REG_P (reg
) && MEM_P (mem
));
8032 enum attr_itanium_class attr_class
= get_attr_itanium_class (insn
);
8034 if (attr_class
== ITANIUM_CLASS_CHK_A
8035 || attr_class
== ITANIUM_CLASS_CHK_S_I
8036 || attr_class
== ITANIUM_CLASS_CHK_S_F
)
8043 mode_no
= ia64_mode_to_int (GET_MODE (mode_rtx
));
8045 if (mode_no
== SPEC_MODE_INVALID
)
8048 extend_p
= (GET_MODE (reg
) != GET_MODE (mode_rtx
));
8052 if (!(SPEC_MODE_FOR_EXTEND_FIRST
<= mode_no
8053 && mode_no
<= SPEC_MODE_FOR_EXTEND_LAST
))
8056 mode_no
+= SPEC_GEN_EXTEND_OFFSET
;
8062 /* If X is an unspec part of a speculative load, return its code.
8063 Return -1 otherwise. */
8065 get_spec_unspec_code (const_rtx x
)
8067 if (GET_CODE (x
) != UNSPEC
)
8089 /* Implement skip_rtx_p hook. */
8091 ia64_skip_rtx_p (const_rtx x
)
8093 return get_spec_unspec_code (x
) != -1;
8096 /* If INSN is a speculative load, return its UNSPEC code.
8097 Return -1 otherwise. */
8099 get_insn_spec_code (const_rtx insn
)
8103 pat
= PATTERN (insn
);
8105 if (GET_CODE (pat
) == COND_EXEC
)
8106 pat
= COND_EXEC_CODE (pat
);
8108 if (GET_CODE (pat
) != SET
)
8111 reg
= SET_DEST (pat
);
8115 mem
= SET_SRC (pat
);
8116 if (GET_CODE (mem
) == ZERO_EXTEND
)
8117 mem
= XEXP (mem
, 0);
8119 return get_spec_unspec_code (mem
);
8122 /* If INSN is a speculative load, return a ds with the speculation types.
8123 Otherwise [if INSN is a normal instruction] return 0. */
8125 ia64_get_insn_spec_ds (rtx insn
)
8127 int code
= get_insn_spec_code (insn
);
8136 return BEGIN_CONTROL
;
8139 return BEGIN_DATA
| BEGIN_CONTROL
;
8146 /* If INSN is a speculative load return a ds with the speculation types that
8148 Otherwise [if INSN is a normal instruction] return 0. */
8150 ia64_get_insn_checked_ds (rtx insn
)
8152 int code
= get_insn_spec_code (insn
);
8157 return BEGIN_DATA
| BEGIN_CONTROL
;
8160 return BEGIN_CONTROL
;
8164 return BEGIN_DATA
| BEGIN_CONTROL
;
8171 /* If GEN_P is true, calculate the index of needed speculation check and return
8172 speculative pattern for INSN with speculative mode TS, machine mode
8173 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
8174 If GEN_P is false, just calculate the index of needed speculation check. */
8176 ia64_gen_spec_load (rtx insn
, ds_t ts
, int mode_no
)
8179 gen_func_t gen_load
;
8181 gen_load
= get_spec_load_gen_function (ts
, mode_no
);
8183 new_pat
= gen_load (copy_rtx (recog_data
.operand
[0]),
8184 copy_rtx (recog_data
.operand
[1]));
8186 pat
= PATTERN (insn
);
8187 if (GET_CODE (pat
) == COND_EXEC
)
8188 new_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8195 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED
,
8196 ds_t ds ATTRIBUTE_UNUSED
)
8201 /* Implement targetm.sched.speculate_insn hook.
8202 Check if the INSN can be TS speculative.
8203 If 'no' - return -1.
8204 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
8205 If current pattern of the INSN already provides TS speculation,
8208 ia64_speculate_insn (rtx insn
, ds_t ts
, rtx
*new_pat
)
8213 gcc_assert (!(ts
& ~SPECULATIVE
));
8215 if (ia64_spec_check_p (insn
))
8218 if ((ts
& BE_IN_SPEC
)
8219 && !insn_can_be_in_speculative_p (insn
, ts
))
8222 mode_no
= get_mode_no_for_insn (insn
);
8224 if (mode_no
!= SPEC_MODE_INVALID
)
8226 if (ia64_get_insn_spec_ds (insn
) == ds_get_speculation_types (ts
))
8231 *new_pat
= ia64_gen_spec_load (insn
, ts
, mode_no
);
8240 /* Return a function that will generate a check for speculation TS with mode
8242 If simple check is needed, pass true for SIMPLE_CHECK_P.
8243 If clearing check is needed, pass true for CLEARING_CHECK_P. */
8245 get_spec_check_gen_function (ds_t ts
, int mode_no
,
8246 bool simple_check_p
, bool clearing_check_p
)
8248 static gen_func_t gen_ld_c_clr
[] = {
8258 gen_zero_extendqidi2_clr
,
8259 gen_zero_extendhidi2_clr
,
8260 gen_zero_extendsidi2_clr
,
8262 static gen_func_t gen_ld_c_nc
[] = {
8272 gen_zero_extendqidi2_nc
,
8273 gen_zero_extendhidi2_nc
,
8274 gen_zero_extendsidi2_nc
,
8276 static gen_func_t gen_chk_a_clr
[] = {
8277 gen_advanced_load_check_clr_bi
,
8278 gen_advanced_load_check_clr_qi
,
8279 gen_advanced_load_check_clr_hi
,
8280 gen_advanced_load_check_clr_si
,
8281 gen_advanced_load_check_clr_di
,
8282 gen_advanced_load_check_clr_sf
,
8283 gen_advanced_load_check_clr_df
,
8284 gen_advanced_load_check_clr_xf
,
8285 gen_advanced_load_check_clr_ti
,
8286 gen_advanced_load_check_clr_di
,
8287 gen_advanced_load_check_clr_di
,
8288 gen_advanced_load_check_clr_di
,
8290 static gen_func_t gen_chk_a_nc
[] = {
8291 gen_advanced_load_check_nc_bi
,
8292 gen_advanced_load_check_nc_qi
,
8293 gen_advanced_load_check_nc_hi
,
8294 gen_advanced_load_check_nc_si
,
8295 gen_advanced_load_check_nc_di
,
8296 gen_advanced_load_check_nc_sf
,
8297 gen_advanced_load_check_nc_df
,
8298 gen_advanced_load_check_nc_xf
,
8299 gen_advanced_load_check_nc_ti
,
8300 gen_advanced_load_check_nc_di
,
8301 gen_advanced_load_check_nc_di
,
8302 gen_advanced_load_check_nc_di
,
8304 static gen_func_t gen_chk_s
[] = {
8305 gen_speculation_check_bi
,
8306 gen_speculation_check_qi
,
8307 gen_speculation_check_hi
,
8308 gen_speculation_check_si
,
8309 gen_speculation_check_di
,
8310 gen_speculation_check_sf
,
8311 gen_speculation_check_df
,
8312 gen_speculation_check_xf
,
8313 gen_speculation_check_ti
,
8314 gen_speculation_check_di
,
8315 gen_speculation_check_di
,
8316 gen_speculation_check_di
,
8319 gen_func_t
*gen_check
;
8321 if (ts
& BEGIN_DATA
)
8323 /* We don't need recovery because even if this is ld.sa
8324 ALAT entry will be allocated only if NAT bit is set to zero.
8325 So it is enough to use ld.c here. */
8329 gcc_assert (mflag_sched_spec_ldc
);
8331 if (clearing_check_p
)
8332 gen_check
= gen_ld_c_clr
;
8334 gen_check
= gen_ld_c_nc
;
8338 if (clearing_check_p
)
8339 gen_check
= gen_chk_a_clr
;
8341 gen_check
= gen_chk_a_nc
;
8344 else if (ts
& BEGIN_CONTROL
)
8347 /* We might want to use ld.sa -> ld.c instead of
8350 gcc_assert (!ia64_needs_block_p (ts
));
8352 if (clearing_check_p
)
8353 gen_check
= gen_ld_c_clr
;
8355 gen_check
= gen_ld_c_nc
;
8359 gen_check
= gen_chk_s
;
8365 gcc_assert (mode_no
>= 0);
8366 return gen_check
[mode_no
];
8369 /* Return nonzero, if INSN needs branchy recovery check. */
8371 ia64_needs_block_p (ds_t ts
)
8373 if (ts
& BEGIN_DATA
)
8374 return !mflag_sched_spec_ldc
;
8376 gcc_assert ((ts
& BEGIN_CONTROL
) != 0);
8378 return !(mflag_sched_spec_control_ldc
&& mflag_sched_spec_ldc
);
8381 /* Generate (or regenerate) a recovery check for INSN. */
8383 ia64_gen_spec_check (rtx insn
, rtx label
, ds_t ds
)
8385 rtx op1
, pat
, check_pat
;
8386 gen_func_t gen_check
;
8389 mode_no
= get_mode_no_for_insn (insn
);
8390 gcc_assert (mode_no
>= 0);
8396 gcc_assert (!ia64_needs_block_p (ds
));
8397 op1
= copy_rtx (recog_data
.operand
[1]);
8400 gen_check
= get_spec_check_gen_function (ds
, mode_no
, label
== NULL_RTX
,
8403 check_pat
= gen_check (copy_rtx (recog_data
.operand
[0]), op1
);
8405 pat
= PATTERN (insn
);
8406 if (GET_CODE (pat
) == COND_EXEC
)
8407 check_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8413 /* Return nonzero, if X is branchy recovery check. */
8415 ia64_spec_check_p (rtx x
)
8418 if (GET_CODE (x
) == COND_EXEC
)
8419 x
= COND_EXEC_CODE (x
);
8420 if (GET_CODE (x
) == SET
)
8421 return ia64_spec_check_src_p (SET_SRC (x
));
8425 /* Return nonzero, if SRC belongs to recovery check. */
8427 ia64_spec_check_src_p (rtx src
)
8429 if (GET_CODE (src
) == IF_THEN_ELSE
)
8434 if (GET_CODE (t
) == NE
)
8438 if (GET_CODE (t
) == UNSPEC
)
8444 if (code
== UNSPEC_LDCCLR
8445 || code
== UNSPEC_LDCNC
8446 || code
== UNSPEC_CHKACLR
8447 || code
== UNSPEC_CHKANC
8448 || code
== UNSPEC_CHKS
)
8450 gcc_assert (code
!= 0);
8460 /* The following page contains abstract data `bundle states' which are
8461 used for bundling insns (inserting nops and template generation). */
8463 /* The following describes state of insn bundling. */
8467 /* Unique bundle state number to identify them in the debugging
8470 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
8471 /* number nops before and after the insn */
8472 short before_nops_num
, after_nops_num
;
8473 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
8475 int cost
; /* cost of the state in cycles */
8476 int accumulated_insns_num
; /* number of all previous insns including
8477 nops. L is considered as 2 insns */
8478 int branch_deviation
; /* deviation of previous branches from 3rd slots */
8479 int middle_bundle_stops
; /* number of stop bits in the middle of bundles */
8480 struct bundle_state
*next
; /* next state with the same insn_num */
8481 struct bundle_state
*originator
; /* originator (previous insn state) */
8482 /* All bundle states are in the following chain. */
8483 struct bundle_state
*allocated_states_chain
;
8484 /* The DFA State after issuing the insn and the nops. */
8488 /* The following is map insn number to the corresponding bundle state. */
8490 static struct bundle_state
**index_to_bundle_states
;
8492 /* The unique number of next bundle state. */
8494 static int bundle_states_num
;
8496 /* All allocated bundle states are in the following chain. */
8498 static struct bundle_state
*allocated_bundle_states_chain
;
8500 /* All allocated but not used bundle states are in the following
8503 static struct bundle_state
*free_bundle_state_chain
;
8506 /* The following function returns a free bundle state. */
8508 static struct bundle_state
*
8509 get_free_bundle_state (void)
8511 struct bundle_state
*result
;
8513 if (free_bundle_state_chain
!= NULL
)
8515 result
= free_bundle_state_chain
;
8516 free_bundle_state_chain
= result
->next
;
8520 result
= XNEW (struct bundle_state
);
8521 result
->dfa_state
= xmalloc (dfa_state_size
);
8522 result
->allocated_states_chain
= allocated_bundle_states_chain
;
8523 allocated_bundle_states_chain
= result
;
8525 result
->unique_num
= bundle_states_num
++;
8530 /* The following function frees given bundle state. */
8533 free_bundle_state (struct bundle_state
*state
)
8535 state
->next
= free_bundle_state_chain
;
8536 free_bundle_state_chain
= state
;
8539 /* Start work with abstract data `bundle states'. */
8542 initiate_bundle_states (void)
8544 bundle_states_num
= 0;
8545 free_bundle_state_chain
= NULL
;
8546 allocated_bundle_states_chain
= NULL
;
8549 /* Finish work with abstract data `bundle states'. */
8552 finish_bundle_states (void)
8554 struct bundle_state
*curr_state
, *next_state
;
8556 for (curr_state
= allocated_bundle_states_chain
;
8558 curr_state
= next_state
)
8560 next_state
= curr_state
->allocated_states_chain
;
8561 free (curr_state
->dfa_state
);
8566 /* Hashtable helpers. */
8568 struct bundle_state_hasher
: typed_noop_remove
<bundle_state
>
8570 typedef bundle_state value_type
;
8571 typedef bundle_state compare_type
;
8572 static inline hashval_t
hash (const value_type
*);
8573 static inline bool equal (const value_type
*, const compare_type
*);
8576 /* The function returns hash of BUNDLE_STATE. */
8579 bundle_state_hasher::hash (const value_type
*state
)
8583 for (result
= i
= 0; i
< dfa_state_size
; i
++)
8584 result
+= (((unsigned char *) state
->dfa_state
) [i
]
8585 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
8586 return result
+ state
->insn_num
;
8589 /* The function returns nonzero if the bundle state keys are equal. */
8592 bundle_state_hasher::equal (const value_type
*state1
,
8593 const compare_type
*state2
)
8595 return (state1
->insn_num
== state2
->insn_num
8596 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
8597 dfa_state_size
) == 0);
8600 /* Hash table of the bundle states. The key is dfa_state and insn_num
8601 of the bundle states. */
8603 static hash_table
<bundle_state_hasher
> bundle_state_table
;
8605 /* The function inserts the BUNDLE_STATE into the hash table. The
8606 function returns nonzero if the bundle has been inserted into the
8607 table. The table contains the best bundle state with given key. */
8610 insert_bundle_state (struct bundle_state
*bundle_state
)
8612 struct bundle_state
**entry_ptr
;
8614 entry_ptr
= bundle_state_table
.find_slot (bundle_state
, INSERT
);
8615 if (*entry_ptr
== NULL
)
8617 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
8618 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
8619 *entry_ptr
= bundle_state
;
8622 else if (bundle_state
->cost
< (*entry_ptr
)->cost
8623 || (bundle_state
->cost
== (*entry_ptr
)->cost
8624 && ((*entry_ptr
)->accumulated_insns_num
8625 > bundle_state
->accumulated_insns_num
8626 || ((*entry_ptr
)->accumulated_insns_num
8627 == bundle_state
->accumulated_insns_num
8628 && ((*entry_ptr
)->branch_deviation
8629 > bundle_state
->branch_deviation
8630 || ((*entry_ptr
)->branch_deviation
8631 == bundle_state
->branch_deviation
8632 && (*entry_ptr
)->middle_bundle_stops
8633 > bundle_state
->middle_bundle_stops
))))))
8636 struct bundle_state temp
;
8639 **entry_ptr
= *bundle_state
;
8640 (*entry_ptr
)->next
= temp
.next
;
8641 *bundle_state
= temp
;
8646 /* Start work with the hash table. */
8649 initiate_bundle_state_table (void)
8651 bundle_state_table
.create (50);
8654 /* Finish work with the hash table. */
8657 finish_bundle_state_table (void)
8659 bundle_state_table
.dispose ();
8664 /* The following variable is a insn `nop' used to check bundle states
8665 with different number of inserted nops. */
8667 static rtx ia64_nop
;
8669 /* The following function tries to issue NOPS_NUM nops for the current
8670 state without advancing processor cycle. If it failed, the
8671 function returns FALSE and frees the current state. */
8674 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
8678 for (i
= 0; i
< nops_num
; i
++)
8679 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
8681 free_bundle_state (curr_state
);
8687 /* The following function tries to issue INSN for the current
8688 state without advancing processor cycle. If it failed, the
8689 function returns FALSE and frees the current state. */
8692 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
8694 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
8696 free_bundle_state (curr_state
);
8702 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8703 starting with ORIGINATOR without advancing processor cycle. If
8704 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8705 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8706 If it was successful, the function creates new bundle state and
8707 insert into the hash table and into `index_to_bundle_states'. */
8710 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
8711 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
8713 struct bundle_state
*curr_state
;
8715 curr_state
= get_free_bundle_state ();
8716 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
8717 curr_state
->insn
= insn
;
8718 curr_state
->insn_num
= originator
->insn_num
+ 1;
8719 curr_state
->cost
= originator
->cost
;
8720 curr_state
->originator
= originator
;
8721 curr_state
->before_nops_num
= before_nops_num
;
8722 curr_state
->after_nops_num
= 0;
8723 curr_state
->accumulated_insns_num
8724 = originator
->accumulated_insns_num
+ before_nops_num
;
8725 curr_state
->branch_deviation
= originator
->branch_deviation
;
8726 curr_state
->middle_bundle_stops
= originator
->middle_bundle_stops
;
8728 if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
8730 gcc_assert (GET_MODE (insn
) != TImode
);
8731 if (!try_issue_nops (curr_state
, before_nops_num
))
8733 if (!try_issue_insn (curr_state
, insn
))
8735 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
8736 if (curr_state
->accumulated_insns_num
% 3 != 0)
8737 curr_state
->middle_bundle_stops
++;
8738 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
8739 && curr_state
->accumulated_insns_num
% 3 != 0)
8741 free_bundle_state (curr_state
);
8745 else if (GET_MODE (insn
) != TImode
)
8747 if (!try_issue_nops (curr_state
, before_nops_num
))
8749 if (!try_issue_insn (curr_state
, insn
))
8751 curr_state
->accumulated_insns_num
++;
8752 gcc_assert (!unknown_for_bundling_p (insn
));
8754 if (ia64_safe_type (insn
) == TYPE_L
)
8755 curr_state
->accumulated_insns_num
++;
8759 /* If this is an insn that must be first in a group, then don't allow
8760 nops to be emitted before it. Currently, alloc is the only such
8761 supported instruction. */
8762 /* ??? The bundling automatons should handle this for us, but they do
8763 not yet have support for the first_insn attribute. */
8764 if (before_nops_num
> 0 && get_attr_first_insn (insn
) == FIRST_INSN_YES
)
8766 free_bundle_state (curr_state
);
8770 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
8771 state_transition (curr_state
->dfa_state
, NULL
);
8773 if (!try_issue_nops (curr_state
, before_nops_num
))
8775 if (!try_issue_insn (curr_state
, insn
))
8777 curr_state
->accumulated_insns_num
++;
8778 if (unknown_for_bundling_p (insn
))
8780 /* Finish bundle containing asm insn. */
8781 curr_state
->after_nops_num
8782 = 3 - curr_state
->accumulated_insns_num
% 3;
8783 curr_state
->accumulated_insns_num
8784 += 3 - curr_state
->accumulated_insns_num
% 3;
8786 else if (ia64_safe_type (insn
) == TYPE_L
)
8787 curr_state
->accumulated_insns_num
++;
8789 if (ia64_safe_type (insn
) == TYPE_B
)
8790 curr_state
->branch_deviation
8791 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
8792 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
8794 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
8797 struct bundle_state
*curr_state1
;
8798 struct bundle_state
*allocated_states_chain
;
8800 curr_state1
= get_free_bundle_state ();
8801 dfa_state
= curr_state1
->dfa_state
;
8802 allocated_states_chain
= curr_state1
->allocated_states_chain
;
8803 *curr_state1
= *curr_state
;
8804 curr_state1
->dfa_state
= dfa_state
;
8805 curr_state1
->allocated_states_chain
= allocated_states_chain
;
8806 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
8808 curr_state
= curr_state1
;
8810 if (!try_issue_nops (curr_state
,
8811 3 - curr_state
->accumulated_insns_num
% 3))
8813 curr_state
->after_nops_num
8814 = 3 - curr_state
->accumulated_insns_num
% 3;
8815 curr_state
->accumulated_insns_num
8816 += 3 - curr_state
->accumulated_insns_num
% 3;
8818 if (!insert_bundle_state (curr_state
))
8819 free_bundle_state (curr_state
);
8823 /* The following function returns position in the two window bundle
8827 get_max_pos (state_t state
)
8829 if (cpu_unit_reservation_p (state
, pos_6
))
8831 else if (cpu_unit_reservation_p (state
, pos_5
))
8833 else if (cpu_unit_reservation_p (state
, pos_4
))
8835 else if (cpu_unit_reservation_p (state
, pos_3
))
8837 else if (cpu_unit_reservation_p (state
, pos_2
))
8839 else if (cpu_unit_reservation_p (state
, pos_1
))
8845 /* The function returns code of a possible template for given position
8846 and state. The function should be called only with 2 values of
8847 position equal to 3 or 6. We avoid generating F NOPs by putting
8848 templates containing F insns at the end of the template search
8849 because undocumented anomaly in McKinley derived cores which can
8850 cause stalls if an F-unit insn (including a NOP) is issued within a
8851 six-cycle window after reading certain application registers (such
8852 as ar.bsp). Furthermore, power-considerations also argue against
8853 the use of F-unit instructions unless they're really needed. */
8856 get_template (state_t state
, int pos
)
8861 if (cpu_unit_reservation_p (state
, _0mmi_
))
8863 else if (cpu_unit_reservation_p (state
, _0mii_
))
8865 else if (cpu_unit_reservation_p (state
, _0mmb_
))
8867 else if (cpu_unit_reservation_p (state
, _0mib_
))
8869 else if (cpu_unit_reservation_p (state
, _0mbb_
))
8871 else if (cpu_unit_reservation_p (state
, _0bbb_
))
8873 else if (cpu_unit_reservation_p (state
, _0mmf_
))
8875 else if (cpu_unit_reservation_p (state
, _0mfi_
))
8877 else if (cpu_unit_reservation_p (state
, _0mfb_
))
8879 else if (cpu_unit_reservation_p (state
, _0mlx_
))
8884 if (cpu_unit_reservation_p (state
, _1mmi_
))
8886 else if (cpu_unit_reservation_p (state
, _1mii_
))
8888 else if (cpu_unit_reservation_p (state
, _1mmb_
))
8890 else if (cpu_unit_reservation_p (state
, _1mib_
))
8892 else if (cpu_unit_reservation_p (state
, _1mbb_
))
8894 else if (cpu_unit_reservation_p (state
, _1bbb_
))
8896 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
8898 else if (cpu_unit_reservation_p (state
, _1mfi_
))
8900 else if (cpu_unit_reservation_p (state
, _1mfb_
))
8902 else if (cpu_unit_reservation_p (state
, _1mlx_
))
8911 /* True when INSN is important for bundling. */
8914 important_for_bundling_p (rtx insn
)
8916 return (INSN_P (insn
)
8917 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
8918 && GET_CODE (PATTERN (insn
)) != USE
8919 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8922 /* The following function returns an insn important for insn bundling
8923 followed by INSN and before TAIL. */
8926 get_next_important_insn (rtx insn
, rtx tail
)
8928 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
8929 if (important_for_bundling_p (insn
))
8934 /* True when INSN is unknown, but important, for bundling. */
8937 unknown_for_bundling_p (rtx insn
)
8939 return (INSN_P (insn
)
8940 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_UNKNOWN
8941 && GET_CODE (PATTERN (insn
)) != USE
8942 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8945 /* Add a bundle selector TEMPLATE0 before INSN. */
8948 ia64_add_bundle_selector_before (int template0
, rtx insn
)
8950 rtx b
= gen_bundle_selector (GEN_INT (template0
));
8952 ia64_emit_insn_before (b
, insn
);
8953 #if NR_BUNDLES == 10
8954 if ((template0
== 4 || template0
== 5)
8955 && ia64_except_unwind_info (&global_options
) == UI_TARGET
)
8958 rtx note
= NULL_RTX
;
8960 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8961 first or second slot. If it is and has REG_EH_NOTE set, copy it
8962 to following nops, as br.call sets rp to the address of following
8963 bundle and therefore an EH region end must be on a bundle
8965 insn
= PREV_INSN (insn
);
8966 for (i
= 0; i
< 3; i
++)
8969 insn
= next_active_insn (insn
);
8970 while (NONJUMP_INSN_P (insn
)
8971 && get_attr_empty (insn
) == EMPTY_YES
);
8973 note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8978 gcc_assert ((code
= recog_memoized (insn
)) == CODE_FOR_nop
8979 || code
== CODE_FOR_nop_b
);
8980 if (find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
8983 add_reg_note (insn
, REG_EH_REGION
, XEXP (note
, 0));
8990 /* The following function does insn bundling. Bundling means
8991 inserting templates and nop insns to fit insn groups into permitted
8992 templates. Instruction scheduling uses NDFA (non-deterministic
8993 finite automata) encoding informations about the templates and the
8994 inserted nops. Nondeterminism of the automata permits follows
8995 all possible insn sequences very fast.
8997 Unfortunately it is not possible to get information about inserting
8998 nop insns and used templates from the automata states. The
8999 automata only says that we can issue an insn possibly inserting
9000 some nops before it and using some template. Therefore insn
9001 bundling in this function is implemented by using DFA
9002 (deterministic finite automata). We follow all possible insn
9003 sequences by inserting 0-2 nops (that is what the NDFA describe for
9004 insn scheduling) before/after each insn being bundled. We know the
9005 start of simulated processor cycle from insn scheduling (insn
9006 starting a new cycle has TImode).
9008 Simple implementation of insn bundling would create enormous
9009 number of possible insn sequences satisfying information about new
9010 cycle ticks taken from the insn scheduling. To make the algorithm
9011 practical we use dynamic programming. Each decision (about
9012 inserting nops and implicitly about previous decisions) is described
9013 by structure bundle_state (see above). If we generate the same
9014 bundle state (key is automaton state after issuing the insns and
9015 nops for it), we reuse already generated one. As consequence we
9016 reject some decisions which cannot improve the solution and
9017 reduce memory for the algorithm.
9019 When we reach the end of EBB (extended basic block), we choose the
9020 best sequence and then, moving back in EBB, insert templates for
9021 the best alternative. The templates are taken from querying
9022 automaton state for each insn in chosen bundle states.
9024 So the algorithm makes two (forward and backward) passes through
9028 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
9030 struct bundle_state
*curr_state
, *next_state
, *best_state
;
9031 rtx insn
, next_insn
;
9033 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
9034 int pos
= 0, max_pos
, template0
, template1
;
9037 enum attr_type type
;
9040 /* Count insns in the EBB. */
9041 for (insn
= NEXT_INSN (prev_head_insn
);
9042 insn
&& insn
!= tail
;
9043 insn
= NEXT_INSN (insn
))
9049 dfa_clean_insn_cache ();
9050 initiate_bundle_state_table ();
9051 index_to_bundle_states
= XNEWVEC (struct bundle_state
*, insn_num
+ 2);
9052 /* First (forward) pass -- generation of bundle states. */
9053 curr_state
= get_free_bundle_state ();
9054 curr_state
->insn
= NULL
;
9055 curr_state
->before_nops_num
= 0;
9056 curr_state
->after_nops_num
= 0;
9057 curr_state
->insn_num
= 0;
9058 curr_state
->cost
= 0;
9059 curr_state
->accumulated_insns_num
= 0;
9060 curr_state
->branch_deviation
= 0;
9061 curr_state
->middle_bundle_stops
= 0;
9062 curr_state
->next
= NULL
;
9063 curr_state
->originator
= NULL
;
9064 state_reset (curr_state
->dfa_state
);
9065 index_to_bundle_states
[0] = curr_state
;
9067 /* Shift cycle mark if it is put on insn which could be ignored. */
9068 for (insn
= NEXT_INSN (prev_head_insn
);
9070 insn
= NEXT_INSN (insn
))
9072 && !important_for_bundling_p (insn
)
9073 && GET_MODE (insn
) == TImode
)
9075 PUT_MODE (insn
, VOIDmode
);
9076 for (next_insn
= NEXT_INSN (insn
);
9078 next_insn
= NEXT_INSN (next_insn
))
9079 if (important_for_bundling_p (next_insn
)
9080 && INSN_CODE (next_insn
) != CODE_FOR_insn_group_barrier
)
9082 PUT_MODE (next_insn
, TImode
);
9086 /* Forward pass: generation of bundle states. */
9087 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
9091 gcc_assert (important_for_bundling_p (insn
));
9092 type
= ia64_safe_type (insn
);
9093 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
9095 index_to_bundle_states
[insn_num
] = NULL
;
9096 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
9098 curr_state
= next_state
)
9100 pos
= curr_state
->accumulated_insns_num
% 3;
9101 next_state
= curr_state
->next
;
9102 /* We must fill up the current bundle in order to start a
9103 subsequent asm insn in a new bundle. Asm insn is always
9104 placed in a separate bundle. */
9106 = (next_insn
!= NULL_RTX
9107 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
9108 && unknown_for_bundling_p (next_insn
));
9109 /* We may fill up the current bundle if it is the cycle end
9110 without a group barrier. */
9112 = (only_bundle_end_p
|| next_insn
== NULL_RTX
9113 || (GET_MODE (next_insn
) == TImode
9114 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
9115 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
9117 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
9119 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
9121 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
9124 gcc_assert (index_to_bundle_states
[insn_num
]);
9125 for (curr_state
= index_to_bundle_states
[insn_num
];
9127 curr_state
= curr_state
->next
)
9128 if (verbose
>= 2 && dump
)
9130 /* This structure is taken from generated code of the
9131 pipeline hazard recognizer (see file insn-attrtab.c).
9132 Please don't forget to change the structure if a new
9133 automaton is added to .md file. */
9136 unsigned short one_automaton_state
;
9137 unsigned short oneb_automaton_state
;
9138 unsigned short two_automaton_state
;
9139 unsigned short twob_automaton_state
;
9144 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
9145 curr_state
->unique_num
,
9146 (curr_state
->originator
== NULL
9147 ? -1 : curr_state
->originator
->unique_num
),
9149 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
9150 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
9151 curr_state
->middle_bundle_stops
,
9152 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
9157 /* We should find a solution because the 2nd insn scheduling has
9159 gcc_assert (index_to_bundle_states
[insn_num
]);
9160 /* Find a state corresponding to the best insn sequence. */
9162 for (curr_state
= index_to_bundle_states
[insn_num
];
9164 curr_state
= curr_state
->next
)
9165 /* We are just looking at the states with fully filled up last
9166 bundle. The first we prefer insn sequences with minimal cost
9167 then with minimal inserted nops and finally with branch insns
9168 placed in the 3rd slots. */
9169 if (curr_state
->accumulated_insns_num
% 3 == 0
9170 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
9171 || (best_state
->cost
== curr_state
->cost
9172 && (curr_state
->accumulated_insns_num
9173 < best_state
->accumulated_insns_num
9174 || (curr_state
->accumulated_insns_num
9175 == best_state
->accumulated_insns_num
9176 && (curr_state
->branch_deviation
9177 < best_state
->branch_deviation
9178 || (curr_state
->branch_deviation
9179 == best_state
->branch_deviation
9180 && curr_state
->middle_bundle_stops
9181 < best_state
->middle_bundle_stops
)))))))
9182 best_state
= curr_state
;
9183 /* Second (backward) pass: adding nops and templates. */
9184 gcc_assert (best_state
);
9185 insn_num
= best_state
->before_nops_num
;
9186 template0
= template1
= -1;
9187 for (curr_state
= best_state
;
9188 curr_state
->originator
!= NULL
;
9189 curr_state
= curr_state
->originator
)
9191 insn
= curr_state
->insn
;
9192 asm_p
= unknown_for_bundling_p (insn
);
9194 if (verbose
>= 2 && dump
)
9198 unsigned short one_automaton_state
;
9199 unsigned short oneb_automaton_state
;
9200 unsigned short two_automaton_state
;
9201 unsigned short twob_automaton_state
;
9206 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
9207 curr_state
->unique_num
,
9208 (curr_state
->originator
== NULL
9209 ? -1 : curr_state
->originator
->unique_num
),
9211 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
9212 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
9213 curr_state
->middle_bundle_stops
,
9214 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
9217 /* Find the position in the current bundle window. The window can
9218 contain at most two bundles. Two bundle window means that
9219 the processor will make two bundle rotation. */
9220 max_pos
= get_max_pos (curr_state
->dfa_state
);
9222 /* The following (negative template number) means that the
9223 processor did one bundle rotation. */
9224 || (max_pos
== 3 && template0
< 0))
9226 /* We are at the end of the window -- find template(s) for
9230 template0
= get_template (curr_state
->dfa_state
, 3);
9233 template1
= get_template (curr_state
->dfa_state
, 3);
9234 template0
= get_template (curr_state
->dfa_state
, 6);
9237 if (max_pos
> 3 && template1
< 0)
9238 /* It may happen when we have the stop inside a bundle. */
9240 gcc_assert (pos
<= 3);
9241 template1
= get_template (curr_state
->dfa_state
, 3);
9245 /* Emit nops after the current insn. */
9246 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
9249 emit_insn_after (nop
, insn
);
9251 gcc_assert (pos
>= 0);
9254 /* We are at the start of a bundle: emit the template
9255 (it should be defined). */
9256 gcc_assert (template0
>= 0);
9257 ia64_add_bundle_selector_before (template0
, nop
);
9258 /* If we have two bundle window, we make one bundle
9259 rotation. Otherwise template0 will be undefined
9260 (negative value). */
9261 template0
= template1
;
9265 /* Move the position backward in the window. Group barrier has
9266 no slot. Asm insn takes all bundle. */
9267 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
9268 && !unknown_for_bundling_p (insn
))
9270 /* Long insn takes 2 slots. */
9271 if (ia64_safe_type (insn
) == TYPE_L
)
9273 gcc_assert (pos
>= 0);
9275 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
9276 && !unknown_for_bundling_p (insn
))
9278 /* The current insn is at the bundle start: emit the
9280 gcc_assert (template0
>= 0);
9281 ia64_add_bundle_selector_before (template0
, insn
);
9282 b
= PREV_INSN (insn
);
9284 /* See comment above in analogous place for emitting nops
9286 template0
= template1
;
9289 /* Emit nops after the current insn. */
9290 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
9293 ia64_emit_insn_before (nop
, insn
);
9294 nop
= PREV_INSN (insn
);
9297 gcc_assert (pos
>= 0);
9300 /* See comment above in analogous place for emitting nops
9302 gcc_assert (template0
>= 0);
9303 ia64_add_bundle_selector_before (template0
, insn
);
9304 b
= PREV_INSN (insn
);
9306 template0
= template1
;
9312 #ifdef ENABLE_CHECKING
9314 /* Assert right calculation of middle_bundle_stops. */
9315 int num
= best_state
->middle_bundle_stops
;
9316 bool start_bundle
= true, end_bundle
= false;
9318 for (insn
= NEXT_INSN (prev_head_insn
);
9319 insn
&& insn
!= tail
;
9320 insn
= NEXT_INSN (insn
))
9324 if (recog_memoized (insn
) == CODE_FOR_bundle_selector
)
9325 start_bundle
= true;
9330 for (next_insn
= NEXT_INSN (insn
);
9331 next_insn
&& next_insn
!= tail
;
9332 next_insn
= NEXT_INSN (next_insn
))
9333 if (INSN_P (next_insn
)
9334 && (ia64_safe_itanium_class (next_insn
)
9335 != ITANIUM_CLASS_IGNORE
9336 || recog_memoized (next_insn
)
9337 == CODE_FOR_bundle_selector
)
9338 && GET_CODE (PATTERN (next_insn
)) != USE
9339 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
9342 end_bundle
= next_insn
== NULL_RTX
9343 || next_insn
== tail
9344 || (INSN_P (next_insn
)
9345 && recog_memoized (next_insn
)
9346 == CODE_FOR_bundle_selector
);
9347 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
9348 && !start_bundle
&& !end_bundle
9350 && !unknown_for_bundling_p (next_insn
))
9353 start_bundle
= false;
9357 gcc_assert (num
== 0);
9361 free (index_to_bundle_states
);
9362 finish_bundle_state_table ();
9364 dfa_clean_insn_cache ();
9367 /* The following function is called at the end of scheduling BB or
9368 EBB. After reload, it inserts stop bits and does insn bundling. */
9371 ia64_sched_finish (FILE *dump
, int sched_verbose
)
9374 fprintf (dump
, "// Finishing schedule.\n");
9375 if (!reload_completed
)
9377 if (reload_completed
)
9379 final_emit_insn_group_barriers (dump
);
9380 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
9381 current_sched_info
->next_tail
);
9382 if (sched_verbose
&& dump
)
9383 fprintf (dump
, "// finishing %d-%d\n",
9384 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
9385 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
9391 /* The following function inserts stop bits in scheduled BB or EBB. */
9394 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
9397 int need_barrier_p
= 0;
9398 int seen_good_insn
= 0;
9400 init_insn_group_barriers ();
9402 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
9403 insn
!= current_sched_info
->next_tail
;
9404 insn
= NEXT_INSN (insn
))
9406 if (BARRIER_P (insn
))
9408 rtx last
= prev_active_insn (insn
);
9412 if (JUMP_TABLE_DATA_P (last
))
9413 last
= prev_active_insn (last
);
9414 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9415 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
9417 init_insn_group_barriers ();
9421 else if (NONDEBUG_INSN_P (insn
))
9423 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
9425 init_insn_group_barriers ();
9429 else if (need_barrier_p
|| group_barrier_needed (insn
)
9430 || (mflag_sched_stop_bits_after_every_cycle
9431 && GET_MODE (insn
) == TImode
9434 if (TARGET_EARLY_STOP_BITS
)
9439 last
!= current_sched_info
->prev_head
;
9440 last
= PREV_INSN (last
))
9441 if (INSN_P (last
) && GET_MODE (last
) == TImode
9442 && stops_p
[INSN_UID (last
)])
9444 if (last
== current_sched_info
->prev_head
)
9446 last
= prev_active_insn (last
);
9448 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9449 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9451 init_insn_group_barriers ();
9452 for (last
= NEXT_INSN (last
);
9454 last
= NEXT_INSN (last
))
9457 group_barrier_needed (last
);
9458 if (recog_memoized (last
) >= 0
9459 && important_for_bundling_p (last
))
9465 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9467 init_insn_group_barriers ();
9470 group_barrier_needed (insn
);
9471 if (recog_memoized (insn
) >= 0
9472 && important_for_bundling_p (insn
))
9475 else if (recog_memoized (insn
) >= 0
9476 && important_for_bundling_p (insn
))
9478 need_barrier_p
= (CALL_P (insn
) || unknown_for_bundling_p (insn
));
9485 /* If the following function returns TRUE, we will use the DFA
9489 ia64_first_cycle_multipass_dfa_lookahead (void)
9491 return (reload_completed
? 6 : 4);
9494 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9497 ia64_init_dfa_pre_cycle_insn (void)
9499 if (temp_dfa_state
== NULL
)
9501 dfa_state_size
= state_size ();
9502 temp_dfa_state
= xmalloc (dfa_state_size
);
9503 prev_cycle_state
= xmalloc (dfa_state_size
);
9505 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
9506 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
9507 recog_memoized (dfa_pre_cycle_insn
);
9508 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9509 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
9510 recog_memoized (dfa_stop_insn
);
9513 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9514 used by the DFA insn scheduler. */
9517 ia64_dfa_pre_cycle_insn (void)
9519 return dfa_pre_cycle_insn
;
9522 /* The following function returns TRUE if PRODUCER (of type ilog or
9523 ld) produces address for CONSUMER (of type st or stf). */
9526 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
9530 gcc_assert (producer
&& consumer
);
9531 dest
= ia64_single_set (producer
);
9533 reg
= SET_DEST (dest
);
9535 if (GET_CODE (reg
) == SUBREG
)
9536 reg
= SUBREG_REG (reg
);
9537 gcc_assert (GET_CODE (reg
) == REG
);
9539 dest
= ia64_single_set (consumer
);
9541 mem
= SET_DEST (dest
);
9542 gcc_assert (mem
&& GET_CODE (mem
) == MEM
);
9543 return reg_mentioned_p (reg
, mem
);
9546 /* The following function returns TRUE if PRODUCER (of type ilog or
9547 ld) produces address for CONSUMER (of type ld or fld). */
9550 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
9552 rtx dest
, src
, reg
, mem
;
9554 gcc_assert (producer
&& consumer
);
9555 dest
= ia64_single_set (producer
);
9557 reg
= SET_DEST (dest
);
9559 if (GET_CODE (reg
) == SUBREG
)
9560 reg
= SUBREG_REG (reg
);
9561 gcc_assert (GET_CODE (reg
) == REG
);
9563 src
= ia64_single_set (consumer
);
9565 mem
= SET_SRC (src
);
9568 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
9569 mem
= XVECEXP (mem
, 0, 0);
9570 else if (GET_CODE (mem
) == IF_THEN_ELSE
)
9571 /* ??? Is this bypass necessary for ld.c? */
9573 gcc_assert (XINT (XEXP (XEXP (mem
, 0), 0), 1) == UNSPEC_LDCCLR
);
9574 mem
= XEXP (mem
, 1);
9577 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
9578 mem
= XEXP (mem
, 0);
9580 if (GET_CODE (mem
) == UNSPEC
)
9582 int c
= XINT (mem
, 1);
9584 gcc_assert (c
== UNSPEC_LDA
|| c
== UNSPEC_LDS
|| c
== UNSPEC_LDS_A
9585 || c
== UNSPEC_LDSA
);
9586 mem
= XVECEXP (mem
, 0, 0);
9589 /* Note that LO_SUM is used for GOT loads. */
9590 gcc_assert (GET_CODE (mem
) == LO_SUM
|| GET_CODE (mem
) == MEM
);
9592 return reg_mentioned_p (reg
, mem
);
9595 /* The following function returns TRUE if INSN produces address for a
9596 load/store insn. We will place such insns into M slot because it
9597 decreases its latency time. */
9600 ia64_produce_address_p (rtx insn
)
9606 /* Emit pseudo-ops for the assembler to describe predicate relations.
9607 At present this assumes that we only consider predicate pairs to
9608 be mutex, and that the assembler can deduce proper values from
9609 straight-line code. */
9612 emit_predicate_relation_info (void)
9616 FOR_EACH_BB_REVERSE (bb
)
9619 rtx head
= BB_HEAD (bb
);
9621 /* We only need such notes at code labels. */
9622 if (! LABEL_P (head
))
9624 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head
)))
9625 head
= NEXT_INSN (head
);
9627 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9628 grabbing the entire block of predicate registers. */
9629 for (r
= PR_REG (2); r
< PR_REG (64); r
+= 2)
9630 if (REGNO_REG_SET_P (df_get_live_in (bb
), r
))
9632 rtx p
= gen_rtx_REG (BImode
, r
);
9633 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
9634 if (head
== BB_END (bb
))
9640 /* Look for conditional calls that do not return, and protect predicate
9641 relations around them. Otherwise the assembler will assume the call
9642 returns, and complain about uses of call-clobbered predicates after
9644 FOR_EACH_BB_REVERSE (bb
)
9646 rtx insn
= BB_HEAD (bb
);
9651 && GET_CODE (PATTERN (insn
)) == COND_EXEC
9652 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
9654 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
9655 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
9656 if (BB_HEAD (bb
) == insn
)
9658 if (BB_END (bb
) == insn
)
9662 if (insn
== BB_END (bb
))
9664 insn
= NEXT_INSN (insn
);
9669 /* Perform machine dependent operations on the rtl chain INSNS. */
9674 /* We are freeing block_for_insn in the toplev to keep compatibility
9675 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9676 compute_bb_for_insn ();
9678 /* If optimizing, we'll have split before scheduling. */
9682 if (optimize
&& flag_schedule_insns_after_reload
9683 && dbg_cnt (ia64_sched2
))
9686 timevar_push (TV_SCHED2
);
9687 ia64_final_schedule
= 1;
9689 /* We can't let modulo-sched prevent us from scheduling any bbs,
9690 since we need the final schedule to produce bundle information. */
9692 bb
->flags
&= ~BB_DISABLE_SCHEDULE
;
9694 initiate_bundle_states ();
9695 ia64_nop
= make_insn_raw (gen_nop ());
9696 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
9697 recog_memoized (ia64_nop
);
9698 clocks_length
= get_max_uid () + 1;
9699 stops_p
= XCNEWVEC (char, clocks_length
);
9701 if (ia64_tune
== PROCESSOR_ITANIUM2
)
9703 pos_1
= get_cpu_unit_code ("2_1");
9704 pos_2
= get_cpu_unit_code ("2_2");
9705 pos_3
= get_cpu_unit_code ("2_3");
9706 pos_4
= get_cpu_unit_code ("2_4");
9707 pos_5
= get_cpu_unit_code ("2_5");
9708 pos_6
= get_cpu_unit_code ("2_6");
9709 _0mii_
= get_cpu_unit_code ("2b_0mii.");
9710 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
9711 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
9712 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
9713 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
9714 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
9715 _0mib_
= get_cpu_unit_code ("2b_0mib.");
9716 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
9717 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
9718 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
9719 _1mii_
= get_cpu_unit_code ("2b_1mii.");
9720 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
9721 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
9722 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
9723 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
9724 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
9725 _1mib_
= get_cpu_unit_code ("2b_1mib.");
9726 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
9727 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
9728 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
9732 pos_1
= get_cpu_unit_code ("1_1");
9733 pos_2
= get_cpu_unit_code ("1_2");
9734 pos_3
= get_cpu_unit_code ("1_3");
9735 pos_4
= get_cpu_unit_code ("1_4");
9736 pos_5
= get_cpu_unit_code ("1_5");
9737 pos_6
= get_cpu_unit_code ("1_6");
9738 _0mii_
= get_cpu_unit_code ("1b_0mii.");
9739 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
9740 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
9741 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
9742 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
9743 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
9744 _0mib_
= get_cpu_unit_code ("1b_0mib.");
9745 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
9746 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
9747 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
9748 _1mii_
= get_cpu_unit_code ("1b_1mii.");
9749 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
9750 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
9751 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
9752 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
9753 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
9754 _1mib_
= get_cpu_unit_code ("1b_1mib.");
9755 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
9756 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
9757 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
9760 if (flag_selective_scheduling2
9761 && !maybe_skip_selective_scheduling ())
9762 run_selective_scheduling ();
9766 /* Redo alignment computation, as it might gone wrong. */
9767 compute_alignments ();
9769 /* We cannot reuse this one because it has been corrupted by the
9771 finish_bundle_states ();
9774 emit_insn_group_barriers (dump_file
);
9776 ia64_final_schedule
= 0;
9777 timevar_pop (TV_SCHED2
);
9780 emit_all_insn_group_barriers (dump_file
);
9784 /* A call must not be the last instruction in a function, so that the
9785 return address is still within the function, so that unwinding works
9786 properly. Note that IA-64 differs from dwarf2 on this point. */
9787 if (ia64_except_unwind_info (&global_options
) == UI_TARGET
)
9792 insn
= get_last_insn ();
9793 if (! INSN_P (insn
))
9794 insn
= prev_active_insn (insn
);
9797 /* Skip over insns that expand to nothing. */
9798 while (NONJUMP_INSN_P (insn
)
9799 && get_attr_empty (insn
) == EMPTY_YES
)
9801 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
9802 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
9804 insn
= prev_active_insn (insn
);
9809 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9810 emit_insn (gen_break_f ());
9811 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9816 emit_predicate_relation_info ();
9818 if (flag_var_tracking
)
9820 timevar_push (TV_VAR_TRACKING
);
9821 variable_tracking_main ();
9822 timevar_pop (TV_VAR_TRACKING
);
9824 df_finish_pass (false);
9827 /* Return true if REGNO is used by the epilogue. */
9830 ia64_epilogue_uses (int regno
)
9835 /* With a call to a function in another module, we will write a new
9836 value to "gp". After returning from such a call, we need to make
9837 sure the function restores the original gp-value, even if the
9838 function itself does not use the gp anymore. */
9839 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
9841 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9842 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9843 /* For functions defined with the syscall_linkage attribute, all
9844 input registers are marked as live at all function exits. This
9845 prevents the register allocator from using the input registers,
9846 which in turn makes it possible to restart a system call after
9847 an interrupt without having to save/restore the input registers.
9848 This also prevents kernel data from leaking to application code. */
9849 return lookup_attribute ("syscall_linkage",
9850 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
9853 /* Conditional return patterns can't represent the use of `b0' as
9854 the return address, so we force the value live this way. */
9858 /* Likewise for ar.pfs, which is used by br.ret. */
9866 /* Return true if REGNO is used by the frame unwinder. */
9869 ia64_eh_uses (int regno
)
9873 if (! reload_completed
)
9879 for (r
= reg_save_b0
; r
<= reg_save_ar_lc
; r
++)
9880 if (regno
== current_frame_info
.r
[r
]
9881 || regno
== emitted_frame_related_regs
[r
])
9887 /* Return true if this goes in small data/bss. */
9889 /* ??? We could also support own long data here. Generating movl/add/ld8
9890 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9891 code faster because there is one less load. This also includes incomplete
9892 types which can't go in sdata/sbss. */
9895 ia64_in_small_data_p (const_tree exp
)
9897 if (TARGET_NO_SDATA
)
9900 /* We want to merge strings, so we never consider them small data. */
9901 if (TREE_CODE (exp
) == STRING_CST
)
9904 /* Functions are never small data. */
9905 if (TREE_CODE (exp
) == FUNCTION_DECL
)
9908 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
9910 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
9912 if (strcmp (section
, ".sdata") == 0
9913 || strncmp (section
, ".sdata.", 7) == 0
9914 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
9915 || strcmp (section
, ".sbss") == 0
9916 || strncmp (section
, ".sbss.", 6) == 0
9917 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0)
9922 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
9924 /* If this is an incomplete type with size 0, then we can't put it
9925 in sdata because it might be too big when completed. */
9926 if (size
> 0 && size
<= ia64_section_threshold
)
9933 /* Output assembly directives for prologue regions. */
9935 /* The current basic block number. */
9937 static bool last_block
;
9939 /* True if we need a copy_state command at the start of the next block. */
9941 static bool need_copy_state
;
9943 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9944 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9947 /* The function emits unwind directives for the start of an epilogue. */
9950 process_epilogue (FILE *asm_out_file
, rtx insn ATTRIBUTE_UNUSED
,
9951 bool unwind
, bool frame ATTRIBUTE_UNUSED
)
9953 /* If this isn't the last block of the function, then we need to label the
9954 current state, and copy it back in at the start of the next block. */
9959 fprintf (asm_out_file
, "\t.label_state %d\n",
9960 ++cfun
->machine
->state_num
);
9961 need_copy_state
= true;
9965 fprintf (asm_out_file
, "\t.restore sp\n");
9968 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9971 process_cfa_adjust_cfa (FILE *asm_out_file
, rtx pat
, rtx insn
,
9972 bool unwind
, bool frame
)
9974 rtx dest
= SET_DEST (pat
);
9975 rtx src
= SET_SRC (pat
);
9977 if (dest
== stack_pointer_rtx
)
9979 if (GET_CODE (src
) == PLUS
)
9981 rtx op0
= XEXP (src
, 0);
9982 rtx op1
= XEXP (src
, 1);
9984 gcc_assert (op0
== dest
&& GET_CODE (op1
) == CONST_INT
);
9986 if (INTVAL (op1
) < 0)
9988 gcc_assert (!frame_pointer_needed
);
9990 fprintf (asm_out_file
,
9991 "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
9995 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9999 gcc_assert (src
== hard_frame_pointer_rtx
);
10000 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
10003 else if (dest
== hard_frame_pointer_rtx
)
10005 gcc_assert (src
== stack_pointer_rtx
);
10006 gcc_assert (frame_pointer_needed
);
10009 fprintf (asm_out_file
, "\t.vframe r%d\n",
10010 ia64_dbx_register_number (REGNO (dest
)));
10013 gcc_unreachable ();
10016 /* This function processes a SET pattern for REG_CFA_REGISTER. */
10019 process_cfa_register (FILE *asm_out_file
, rtx pat
, bool unwind
)
10021 rtx dest
= SET_DEST (pat
);
10022 rtx src
= SET_SRC (pat
);
10023 int dest_regno
= REGNO (dest
);
10028 /* Saving return address pointer. */
10030 fprintf (asm_out_file
, "\t.save rp, r%d\n",
10031 ia64_dbx_register_number (dest_regno
));
10035 src_regno
= REGNO (src
);
10040 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_pr
]);
10042 fprintf (asm_out_file
, "\t.save pr, r%d\n",
10043 ia64_dbx_register_number (dest_regno
));
10046 case AR_UNAT_REGNUM
:
10047 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_unat
]);
10049 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
10050 ia64_dbx_register_number (dest_regno
));
10054 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_lc
]);
10056 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
10057 ia64_dbx_register_number (dest_regno
));
10061 /* Everything else should indicate being stored to memory. */
10062 gcc_unreachable ();
10066 /* This function processes a SET pattern for REG_CFA_OFFSET. */
10069 process_cfa_offset (FILE *asm_out_file
, rtx pat
, bool unwind
)
10071 rtx dest
= SET_DEST (pat
);
10072 rtx src
= SET_SRC (pat
);
10073 int src_regno
= REGNO (src
);
10074 const char *saveop
;
10078 gcc_assert (MEM_P (dest
));
10079 if (GET_CODE (XEXP (dest
, 0)) == REG
)
10081 base
= XEXP (dest
, 0);
10086 gcc_assert (GET_CODE (XEXP (dest
, 0)) == PLUS
10087 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
);
10088 base
= XEXP (XEXP (dest
, 0), 0);
10089 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
10092 if (base
== hard_frame_pointer_rtx
)
10094 saveop
= ".savepsp";
10099 gcc_assert (base
== stack_pointer_rtx
);
10100 saveop
= ".savesp";
10103 src_regno
= REGNO (src
);
10107 gcc_assert (!current_frame_info
.r
[reg_save_b0
]);
10109 fprintf (asm_out_file
, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC
"\n",
10114 gcc_assert (!current_frame_info
.r
[reg_save_pr
]);
10116 fprintf (asm_out_file
, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC
"\n",
10121 gcc_assert (!current_frame_info
.r
[reg_save_ar_lc
]);
10123 fprintf (asm_out_file
, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC
"\n",
10127 case AR_PFS_REGNUM
:
10128 gcc_assert (!current_frame_info
.r
[reg_save_ar_pfs
]);
10130 fprintf (asm_out_file
, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC
"\n",
10134 case AR_UNAT_REGNUM
:
10135 gcc_assert (!current_frame_info
.r
[reg_save_ar_unat
]);
10137 fprintf (asm_out_file
, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC
"\n",
10146 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
10147 1 << (src_regno
- GR_REG (4)));
10156 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
10157 1 << (src_regno
- BR_REG (1)));
10165 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
10166 1 << (src_regno
- FR_REG (2)));
10169 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
10170 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
10171 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
10172 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
10174 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
10175 1 << (src_regno
- FR_REG (12)));
10179 /* ??? For some reason we mark other general registers, even those
10180 we can't represent in the unwind info. Ignore them. */
10185 /* This function looks at a single insn and emits any directives
10186 required to unwind this insn. */
10189 ia64_asm_unwind_emit (FILE *asm_out_file
, rtx insn
)
10191 bool unwind
= ia64_except_unwind_info (&global_options
) == UI_TARGET
;
10192 bool frame
= dwarf2out_do_frame ();
10196 if (!unwind
&& !frame
)
10199 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
10201 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
10202 == EXIT_BLOCK_PTR_FOR_FN (cfun
);
10204 /* Restore unwind state from immediately before the epilogue. */
10205 if (need_copy_state
)
10209 fprintf (asm_out_file
, "\t.body\n");
10210 fprintf (asm_out_file
, "\t.copy_state %d\n",
10211 cfun
->machine
->state_num
);
10213 need_copy_state
= false;
10217 if (NOTE_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
10220 /* Look for the ALLOC insn. */
10221 if (INSN_CODE (insn
) == CODE_FOR_alloc
)
10223 rtx dest
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
10224 int dest_regno
= REGNO (dest
);
10226 /* If this is the final destination for ar.pfs, then this must
10227 be the alloc in the prologue. */
10228 if (dest_regno
== current_frame_info
.r
[reg_save_ar_pfs
])
10231 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
10232 ia64_dbx_register_number (dest_regno
));
10236 /* This must be an alloc before a sibcall. We must drop the
10237 old frame info. The easiest way to drop the old frame
10238 info is to ensure we had a ".restore sp" directive
10239 followed by a new prologue. If the procedure doesn't
10240 have a memory-stack frame, we'll issue a dummy ".restore
10242 if (current_frame_info
.total_size
== 0 && !frame_pointer_needed
)
10243 /* if haven't done process_epilogue() yet, do it now */
10244 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
10246 fprintf (asm_out_file
, "\t.prologue\n");
10251 handled_one
= false;
10252 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
10253 switch (REG_NOTE_KIND (note
))
10255 case REG_CFA_ADJUST_CFA
:
10256 pat
= XEXP (note
, 0);
10258 pat
= PATTERN (insn
);
10259 process_cfa_adjust_cfa (asm_out_file
, pat
, insn
, unwind
, frame
);
10260 handled_one
= true;
10263 case REG_CFA_OFFSET
:
10264 pat
= XEXP (note
, 0);
10266 pat
= PATTERN (insn
);
10267 process_cfa_offset (asm_out_file
, pat
, unwind
);
10268 handled_one
= true;
10271 case REG_CFA_REGISTER
:
10272 pat
= XEXP (note
, 0);
10274 pat
= PATTERN (insn
);
10275 process_cfa_register (asm_out_file
, pat
, unwind
);
10276 handled_one
= true;
10279 case REG_FRAME_RELATED_EXPR
:
10280 case REG_CFA_DEF_CFA
:
10281 case REG_CFA_EXPRESSION
:
10282 case REG_CFA_RESTORE
:
10283 case REG_CFA_SET_VDRAP
:
10284 /* Not used in the ia64 port. */
10285 gcc_unreachable ();
10288 /* Not a frame-related note. */
10292 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10293 explicit action to take. No guessing required. */
10294 gcc_assert (handled_one
);
10297 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10300 ia64_asm_emit_except_personality (rtx personality
)
10302 fputs ("\t.personality\t", asm_out_file
);
10303 output_addr_const (asm_out_file
, personality
);
10304 fputc ('\n', asm_out_file
);
10307 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10310 ia64_asm_init_sections (void)
10312 exception_section
= get_unnamed_section (0, output_section_asm_op
,
10316 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10318 static enum unwind_info_type
10319 ia64_debug_unwind_info (void)
10327 IA64_BUILTIN_COPYSIGNQ
,
10328 IA64_BUILTIN_FABSQ
,
10329 IA64_BUILTIN_FLUSHRS
,
10331 IA64_BUILTIN_HUGE_VALQ
,
10335 static GTY(()) tree ia64_builtins
[(int) IA64_BUILTIN_max
];
10338 ia64_init_builtins (void)
10344 /* The __fpreg type. */
10345 fpreg_type
= make_node (REAL_TYPE
);
10346 TYPE_PRECISION (fpreg_type
) = 82;
10347 layout_type (fpreg_type
);
10348 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
10350 /* The __float80 type. */
10351 float80_type
= make_node (REAL_TYPE
);
10352 TYPE_PRECISION (float80_type
) = 80;
10353 layout_type (float80_type
);
10354 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
10356 /* The __float128 type. */
10360 tree float128_type
= make_node (REAL_TYPE
);
10362 TYPE_PRECISION (float128_type
) = 128;
10363 layout_type (float128_type
);
10364 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
10366 /* TFmode support builtins. */
10367 ftype
= build_function_type_list (float128_type
, NULL_TREE
);
10368 decl
= add_builtin_function ("__builtin_infq", ftype
,
10369 IA64_BUILTIN_INFQ
, BUILT_IN_MD
,
10371 ia64_builtins
[IA64_BUILTIN_INFQ
] = decl
;
10373 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
10374 IA64_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
10376 ia64_builtins
[IA64_BUILTIN_HUGE_VALQ
] = decl
;
10378 ftype
= build_function_type_list (float128_type
,
10381 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
10382 IA64_BUILTIN_FABSQ
, BUILT_IN_MD
,
10383 "__fabstf2", NULL_TREE
);
10384 TREE_READONLY (decl
) = 1;
10385 ia64_builtins
[IA64_BUILTIN_FABSQ
] = decl
;
10387 ftype
= build_function_type_list (float128_type
,
10391 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
10392 IA64_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
10393 "__copysigntf3", NULL_TREE
);
10394 TREE_READONLY (decl
) = 1;
10395 ia64_builtins
[IA64_BUILTIN_COPYSIGNQ
] = decl
;
10398 /* Under HPUX, this is a synonym for "long double". */
10399 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
10402 /* Fwrite on VMS is non-standard. */
10403 #if TARGET_ABI_OPEN_VMS
10404 vms_patch_builtins ();
10407 #define def_builtin(name, type, code) \
10408 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10411 decl
= def_builtin ("__builtin_ia64_bsp",
10412 build_function_type_list (ptr_type_node
, NULL_TREE
),
10414 ia64_builtins
[IA64_BUILTIN_BSP
] = decl
;
10416 decl
= def_builtin ("__builtin_ia64_flushrs",
10417 build_function_type_list (void_type_node
, NULL_TREE
),
10418 IA64_BUILTIN_FLUSHRS
);
10419 ia64_builtins
[IA64_BUILTIN_FLUSHRS
] = decl
;
10425 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITE
)) != NULL_TREE
)
10426 set_user_assembler_name (decl
, "_Isfinite");
10427 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEF
)) != NULL_TREE
)
10428 set_user_assembler_name (decl
, "_Isfinitef");
10429 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEL
)) != NULL_TREE
)
10430 set_user_assembler_name (decl
, "_Isfinitef128");
10435 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10436 enum machine_mode mode ATTRIBUTE_UNUSED
,
10437 int ignore ATTRIBUTE_UNUSED
)
10439 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10440 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10444 case IA64_BUILTIN_BSP
:
10445 if (! target
|| ! register_operand (target
, DImode
))
10446 target
= gen_reg_rtx (DImode
);
10447 emit_insn (gen_bsp_value (target
));
10448 #ifdef POINTERS_EXTEND_UNSIGNED
10449 target
= convert_memory_address (ptr_mode
, target
);
10453 case IA64_BUILTIN_FLUSHRS
:
10454 emit_insn (gen_flushrs ());
10457 case IA64_BUILTIN_INFQ
:
10458 case IA64_BUILTIN_HUGE_VALQ
:
10460 enum machine_mode target_mode
= TYPE_MODE (TREE_TYPE (exp
));
10461 REAL_VALUE_TYPE inf
;
10465 tmp
= CONST_DOUBLE_FROM_REAL_VALUE (inf
, target_mode
);
10467 tmp
= validize_mem (force_const_mem (target_mode
, tmp
));
10470 target
= gen_reg_rtx (target_mode
);
10472 emit_move_insn (target
, tmp
);
10476 case IA64_BUILTIN_FABSQ
:
10477 case IA64_BUILTIN_COPYSIGNQ
:
10478 return expand_call (exp
, target
, ignore
);
10481 gcc_unreachable ();
10487 /* Return the ia64 builtin for CODE. */
10490 ia64_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10492 if (code
>= IA64_BUILTIN_max
)
10493 return error_mark_node
;
10495 return ia64_builtins
[code
];
10498 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10499 most significant bits of the stack slot. */
10502 ia64_hpux_function_arg_padding (enum machine_mode mode
, const_tree type
)
10504 /* Exception to normal case for structures/unions/etc. */
10506 if (type
&& AGGREGATE_TYPE_P (type
)
10507 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
10510 /* Fall back to the default. */
10511 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
10514 /* Emit text to declare externally defined variables and functions, because
10515 the Intel assembler does not support undefined externals. */
10518 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
10520 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10521 set in order to avoid putting out names that are never really
10523 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
10525 /* maybe_assemble_visibility will return 1 if the assembler
10526 visibility directive is output. */
10527 int need_visibility
= ((*targetm
.binds_local_p
) (decl
)
10528 && maybe_assemble_visibility (decl
));
10530 /* GNU as does not need anything here, but the HP linker does
10531 need something for external functions. */
10532 if ((TARGET_HPUX_LD
|| !TARGET_GNU_AS
)
10533 && TREE_CODE (decl
) == FUNCTION_DECL
)
10534 (*targetm
.asm_out
.globalize_decl_name
) (file
, decl
);
10535 else if (need_visibility
&& !TARGET_GNU_AS
)
10536 (*targetm
.asm_out
.globalize_label
) (file
, name
);
10540 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10541 modes of word_mode and larger. Rename the TFmode libfuncs using the
10542 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10543 backward compatibility. */
10546 ia64_init_libfuncs (void)
10548 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
10549 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
10550 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
10551 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
10553 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
10554 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
10555 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
10556 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
10557 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
10559 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
10560 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
10561 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
10562 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
10563 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
10564 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
10566 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
10567 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
10568 set_conv_libfunc (sfix_optab
, TImode
, TFmode
, "_U_Qfcnvfxt_quad_to_quad");
10569 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
10570 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
10572 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
10573 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
10574 set_conv_libfunc (sfloat_optab
, TFmode
, TImode
, "_U_Qfcnvxf_quad_to_quad");
10575 /* HP-UX 11.23 libc does not have a function for unsigned
10576 SImode-to-TFmode conversion. */
10577 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_U_Qfcnvxuf_dbl_to_quad");
10580 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10583 ia64_hpux_init_libfuncs (void)
10585 ia64_init_libfuncs ();
10587 /* The HP SI millicode division and mod functions expect DI arguments.
10588 By turning them off completely we avoid using both libgcc and the
10589 non-standard millicode routines and use the HP DI millicode routines
10592 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10593 set_optab_libfunc (udiv_optab
, SImode
, 0);
10594 set_optab_libfunc (smod_optab
, SImode
, 0);
10595 set_optab_libfunc (umod_optab
, SImode
, 0);
10597 set_optab_libfunc (sdiv_optab
, DImode
, "__milli_divI");
10598 set_optab_libfunc (udiv_optab
, DImode
, "__milli_divU");
10599 set_optab_libfunc (smod_optab
, DImode
, "__milli_remI");
10600 set_optab_libfunc (umod_optab
, DImode
, "__milli_remU");
10602 /* HP-UX libc has TF min/max/abs routines in it. */
10603 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
10604 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
10605 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
10607 /* ia64_expand_compare uses this. */
10608 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
10610 /* These should never be used. */
10611 set_optab_libfunc (eq_optab
, TFmode
, 0);
10612 set_optab_libfunc (ne_optab
, TFmode
, 0);
10613 set_optab_libfunc (gt_optab
, TFmode
, 0);
10614 set_optab_libfunc (ge_optab
, TFmode
, 0);
10615 set_optab_libfunc (lt_optab
, TFmode
, 0);
10616 set_optab_libfunc (le_optab
, TFmode
, 0);
10619 /* Rename the division and modulus functions in VMS. */
10622 ia64_vms_init_libfuncs (void)
10624 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10625 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10626 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10627 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10628 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10629 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10630 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10631 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10632 abort_libfunc
= init_one_libfunc ("decc$abort");
10633 memcmp_libfunc
= init_one_libfunc ("decc$memcmp");
10634 #ifdef MEM_LIBFUNCS_INIT
10639 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10640 the HPUX conventions. */
10643 ia64_sysv4_init_libfuncs (void)
10645 ia64_init_libfuncs ();
10647 /* These functions are not part of the HPUX TFmode interface. We
10648 use them instead of _U_Qfcmp, which doesn't work the way we
10650 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
10651 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
10652 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
10653 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
10654 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
10655 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
10657 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10658 glibc doesn't have them. */
10664 ia64_soft_fp_init_libfuncs (void)
10669 ia64_vms_valid_pointer_mode (enum machine_mode mode
)
10671 return (mode
== SImode
|| mode
== DImode
);
10674 /* For HPUX, it is illegal to have relocations in shared segments. */
10677 ia64_hpux_reloc_rw_mask (void)
10682 /* For others, relax this so that relocations to local data goes in
10683 read-only segments, but we still cannot allow global relocations
10684 in read-only segments. */
10687 ia64_reloc_rw_mask (void)
10689 return flag_pic
? 3 : 2;
10692 /* Return the section to use for X. The only special thing we do here
10693 is to honor small data. */
10696 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
10697 unsigned HOST_WIDE_INT align
)
10699 if (GET_MODE_SIZE (mode
) > 0
10700 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
10701 && !TARGET_NO_SDATA
)
10702 return sdata_section
;
10704 return default_elf_select_rtx_section (mode
, x
, align
);
10707 static unsigned int
10708 ia64_section_type_flags (tree decl
, const char *name
, int reloc
)
10710 unsigned int flags
= 0;
10712 if (strcmp (name
, ".sdata") == 0
10713 || strncmp (name
, ".sdata.", 7) == 0
10714 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
10715 || strncmp (name
, ".sdata2.", 8) == 0
10716 || strncmp (name
, ".gnu.linkonce.s2.", 17) == 0
10717 || strcmp (name
, ".sbss") == 0
10718 || strncmp (name
, ".sbss.", 6) == 0
10719 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
10720 flags
= SECTION_SMALL
;
10722 flags
|= default_section_type_flags (decl
, name
, reloc
);
10726 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10727 structure type and that the address of that type should be passed
10728 in out0, rather than in r8. */
10731 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
10733 tree ret_type
= TREE_TYPE (fntype
);
10735 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10736 as the structure return address parameter, if the return value
10737 type has a non-trivial copy constructor or destructor. It is not
10738 clear if this same convention should be used for other
10739 programming languages. Until G++ 3.4, we incorrectly used r8 for
10740 these return values. */
10741 return (abi_version_at_least (2)
10743 && TYPE_MODE (ret_type
) == BLKmode
10744 && TREE_ADDRESSABLE (ret_type
)
10745 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
10748 /* Output the assembler code for a thunk function. THUNK_DECL is the
10749 declaration for the thunk function itself, FUNCTION is the decl for
10750 the target function. DELTA is an immediate constant offset to be
10751 added to THIS. If VCALL_OFFSET is nonzero, the word at
10752 *(*this + vcall_offset) should be added to THIS. */
10755 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
10756 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10759 rtx this_rtx
, insn
, funexp
;
10760 unsigned int this_parmno
;
10761 unsigned int this_regno
;
10764 reload_completed
= 1;
10765 epilogue_completed
= 1;
10767 /* Set things up as ia64_expand_prologue might. */
10768 last_scratch_gr_reg
= 15;
10770 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
10771 current_frame_info
.spill_cfa_off
= -16;
10772 current_frame_info
.n_input_regs
= 1;
10773 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
10775 /* Mark the end of the (empty) prologue. */
10776 emit_note (NOTE_INSN_PROLOGUE_END
);
10778 /* Figure out whether "this" will be the first parameter (the
10779 typical case) or the second parameter (as happens when the
10780 virtual function returns certain class objects). */
10782 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
10784 this_regno
= IN_REG (this_parmno
);
10785 if (!TARGET_REG_NAMES
)
10786 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
10788 this_rtx
= gen_rtx_REG (Pmode
, this_regno
);
10790 /* Apply the constant offset, if required. */
10791 delta_rtx
= GEN_INT (delta
);
10794 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
10795 REG_POINTER (tmp
) = 1;
10796 if (delta
&& satisfies_constraint_I (delta_rtx
))
10798 emit_insn (gen_ptr_extend_plus_imm (this_rtx
, tmp
, delta_rtx
));
10802 emit_insn (gen_ptr_extend (this_rtx
, tmp
));
10806 if (!satisfies_constraint_I (delta_rtx
))
10808 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10809 emit_move_insn (tmp
, delta_rtx
);
10812 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, delta_rtx
));
10815 /* Apply the offset from the vtable, if required. */
10818 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10819 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10823 rtx t
= gen_rtx_REG (ptr_mode
, 2);
10824 REG_POINTER (t
) = 1;
10825 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this_rtx
));
10826 if (satisfies_constraint_I (vcall_offset_rtx
))
10828 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
, vcall_offset_rtx
));
10832 emit_insn (gen_ptr_extend (tmp
, t
));
10835 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
10839 if (!satisfies_constraint_J (vcall_offset_rtx
))
10841 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
10842 emit_move_insn (tmp2
, vcall_offset_rtx
);
10843 vcall_offset_rtx
= tmp2
;
10845 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
10849 emit_insn (gen_zero_extendsidi2 (tmp
, gen_rtx_MEM (ptr_mode
, tmp
)));
10851 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
10853 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
10856 /* Generate a tail call to the target function. */
10857 if (! TREE_USED (function
))
10859 assemble_external (function
);
10860 TREE_USED (function
) = 1;
10862 funexp
= XEXP (DECL_RTL (function
), 0);
10863 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10864 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
10865 insn
= get_last_insn ();
10866 SIBLING_CALL_P (insn
) = 1;
10868 /* Code generation for calls relies on splitting. */
10869 reload_completed
= 1;
10870 epilogue_completed
= 1;
10871 try_split (PATTERN (insn
), insn
, 0);
10875 /* Run just enough of rest_of_compilation to get the insns emitted.
10876 There's not really enough bulk here to make other passes such as
10877 instruction scheduling worth while. Note that use_thunk calls
10878 assemble_start_function and assemble_end_function. */
10880 emit_all_insn_group_barriers (NULL
);
10881 insn
= get_insns ();
10882 shorten_branches (insn
);
10883 final_start_function (insn
, file
, 1);
10884 final (insn
, file
, 1);
10885 final_end_function ();
10887 reload_completed
= 0;
10888 epilogue_completed
= 0;
10891 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10894 ia64_struct_value_rtx (tree fntype
,
10895 int incoming ATTRIBUTE_UNUSED
)
10897 if (TARGET_ABI_OPEN_VMS
||
10898 (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
)))
10900 return gen_rtx_REG (Pmode
, GR_REG (8));
10904 ia64_scalar_mode_supported_p (enum machine_mode mode
)
10930 ia64_vector_mode_supported_p (enum machine_mode mode
)
10947 /* Implement the FUNCTION_PROFILER macro. */
10950 ia64_output_function_profiler (FILE *file
, int labelno
)
10952 bool indirect_call
;
10954 /* If the function needs a static chain and the static chain
10955 register is r15, we use an indirect call so as to bypass
10956 the PLT stub in case the executable is dynamically linked,
10957 because the stub clobbers r15 as per 5.3.6 of the psABI.
10958 We don't need to do that in non canonical PIC mode. */
10960 if (cfun
->static_chain_decl
&& !TARGET_NO_PIC
&& !TARGET_AUTO_PIC
)
10962 gcc_assert (STATIC_CHAIN_REGNUM
== 15);
10963 indirect_call
= true;
10966 indirect_call
= false;
10969 fputs ("\t.prologue 4, r40\n", file
);
10971 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file
);
10972 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file
);
10974 if (NO_PROFILE_COUNTERS
)
10975 fputs ("\tmov out3 = r0\n", file
);
10979 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10981 if (TARGET_AUTO_PIC
)
10982 fputs ("\tmovl out3 = @gprel(", file
);
10984 fputs ("\taddl out3 = @ltoff(", file
);
10985 assemble_name (file
, buf
);
10986 if (TARGET_AUTO_PIC
)
10987 fputs (")\n", file
);
10989 fputs ("), r1\n", file
);
10993 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file
);
10994 fputs ("\t;;\n", file
);
10996 fputs ("\t.save rp, r42\n", file
);
10997 fputs ("\tmov out2 = b0\n", file
);
10999 fputs ("\tld8 r14 = [r14]\n\t;;\n", file
);
11000 fputs ("\t.body\n", file
);
11001 fputs ("\tmov out1 = r1\n", file
);
11004 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file
);
11005 fputs ("\tmov b6 = r16\n", file
);
11006 fputs ("\tld8 r1 = [r14]\n", file
);
11007 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file
);
11010 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file
);
11013 static GTY(()) rtx mcount_func_rtx
;
11015 gen_mcount_func_rtx (void)
11017 if (!mcount_func_rtx
)
11018 mcount_func_rtx
= init_one_libfunc ("_mcount");
11019 return mcount_func_rtx
;
11023 ia64_profile_hook (int labelno
)
11027 if (NO_PROFILE_COUNTERS
)
11028 label
= const0_rtx
;
11032 const char *label_name
;
11033 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
11034 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
11035 label
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
11036 SYMBOL_REF_FLAGS (label
) = SYMBOL_FLAG_LOCAL
;
11038 ip
= gen_reg_rtx (Pmode
);
11039 emit_insn (gen_ip_value (ip
));
11040 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL
,
11042 gen_rtx_REG (Pmode
, BR_REG (0)), Pmode
,
11047 /* Return the mangling of TYPE if it is an extended fundamental type. */
11049 static const char *
11050 ia64_mangle_type (const_tree type
)
11052 type
= TYPE_MAIN_VARIANT (type
);
11054 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
11055 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
11058 /* On HP-UX, "long double" is mangled as "e" so __float128 is
11060 if (!TARGET_HPUX
&& TYPE_MODE (type
) == TFmode
)
11062 /* On HP-UX, "e" is not available as a mangling of __float80 so use
11063 an extended mangling. Elsewhere, "e" is available since long
11064 double is 80 bits. */
11065 if (TYPE_MODE (type
) == XFmode
)
11066 return TARGET_HPUX
? "u9__float80" : "e";
11067 if (TYPE_MODE (type
) == RFmode
)
11068 return "u7__fpreg";
11072 /* Return the diagnostic message string if conversion from FROMTYPE to
11073 TOTYPE is not allowed, NULL otherwise. */
11074 static const char *
11075 ia64_invalid_conversion (const_tree fromtype
, const_tree totype
)
11077 /* Reject nontrivial conversion to or from __fpreg. */
11078 if (TYPE_MODE (fromtype
) == RFmode
11079 && TYPE_MODE (totype
) != RFmode
11080 && TYPE_MODE (totype
) != VOIDmode
)
11081 return N_("invalid conversion from %<__fpreg%>");
11082 if (TYPE_MODE (totype
) == RFmode
11083 && TYPE_MODE (fromtype
) != RFmode
)
11084 return N_("invalid conversion to %<__fpreg%>");
11088 /* Return the diagnostic message string if the unary operation OP is
11089 not permitted on TYPE, NULL otherwise. */
11090 static const char *
11091 ia64_invalid_unary_op (int op
, const_tree type
)
11093 /* Reject operations on __fpreg other than unary + or &. */
11094 if (TYPE_MODE (type
) == RFmode
11095 && op
!= CONVERT_EXPR
11096 && op
!= ADDR_EXPR
)
11097 return N_("invalid operation on %<__fpreg%>");
11101 /* Return the diagnostic message string if the binary operation OP is
11102 not permitted on TYPE1 and TYPE2, NULL otherwise. */
11103 static const char *
11104 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
11106 /* Reject operations on __fpreg. */
11107 if (TYPE_MODE (type1
) == RFmode
|| TYPE_MODE (type2
) == RFmode
)
11108 return N_("invalid operation on %<__fpreg%>");
11112 /* HP-UX version_id attribute.
11113 For object foo, if the version_id is set to 1234 put out an alias
11114 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
11115 other than an alias statement because it is an illegal symbol name. */
11118 ia64_handle_version_id_attribute (tree
*node ATTRIBUTE_UNUSED
,
11119 tree name ATTRIBUTE_UNUSED
,
11121 int flags ATTRIBUTE_UNUSED
,
11122 bool *no_add_attrs
)
11124 tree arg
= TREE_VALUE (args
);
11126 if (TREE_CODE (arg
) != STRING_CST
)
11128 error("version attribute is not a string");
11129 *no_add_attrs
= true;
11135 /* Target hook for c_mode_for_suffix. */
11137 static enum machine_mode
11138 ia64_c_mode_for_suffix (char suffix
)
11148 static GTY(()) rtx ia64_dconst_0_5_rtx
;
11151 ia64_dconst_0_5 (void)
11153 if (! ia64_dconst_0_5_rtx
)
11155 REAL_VALUE_TYPE rv
;
11156 real_from_string (&rv
, "0.5");
11157 ia64_dconst_0_5_rtx
= const_double_from_real_value (rv
, DFmode
);
11159 return ia64_dconst_0_5_rtx
;
11162 static GTY(()) rtx ia64_dconst_0_375_rtx
;
11165 ia64_dconst_0_375 (void)
11167 if (! ia64_dconst_0_375_rtx
)
11169 REAL_VALUE_TYPE rv
;
11170 real_from_string (&rv
, "0.375");
11171 ia64_dconst_0_375_rtx
= const_double_from_real_value (rv
, DFmode
);
11173 return ia64_dconst_0_375_rtx
;
11176 static enum machine_mode
11177 ia64_get_reg_raw_mode (int regno
)
11179 if (FR_REGNO_P (regno
))
11181 return default_get_reg_raw_mode(regno
);
11184 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed
11188 ia64_member_type_forces_blk (const_tree
, enum machine_mode mode
)
11190 return TARGET_HPUX
&& mode
== TFmode
;
11193 /* Always default to .text section until HP-UX linker is fixed. */
11195 ATTRIBUTE_UNUSED
static section
*
11196 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED
,
11197 enum node_frequency freq ATTRIBUTE_UNUSED
,
11198 bool startup ATTRIBUTE_UNUSED
,
11199 bool exit ATTRIBUTE_UNUSED
)
11204 /* Construct (set target (vec_select op0 (parallel perm))) and
11205 return true if that's a valid instruction in the active ISA. */
11208 expand_vselect (rtx target
, rtx op0
, const unsigned char *perm
, unsigned nelt
)
11210 rtx rperm
[MAX_VECT_LEN
], x
;
11213 for (i
= 0; i
< nelt
; ++i
)
11214 rperm
[i
] = GEN_INT (perm
[i
]);
11216 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
11217 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
11218 x
= gen_rtx_SET (VOIDmode
, target
, x
);
11221 if (recog_memoized (x
) < 0)
11229 /* Similar, but generate a vec_concat from op0 and op1 as well. */
11232 expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
11233 const unsigned char *perm
, unsigned nelt
)
11235 enum machine_mode v2mode
;
11238 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
11239 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
11240 return expand_vselect (target
, x
, perm
, nelt
);
11243 /* Try to expand a no-op permutation. */
11246 expand_vec_perm_identity (struct expand_vec_perm_d
*d
)
11248 unsigned i
, nelt
= d
->nelt
;
11250 for (i
= 0; i
< nelt
; ++i
)
11251 if (d
->perm
[i
] != i
)
11255 emit_move_insn (d
->target
, d
->op0
);
11260 /* Try to expand D via a shrp instruction. */
11263 expand_vec_perm_shrp (struct expand_vec_perm_d
*d
)
11265 unsigned i
, nelt
= d
->nelt
, shift
, mask
;
11268 /* ??? Don't force V2SFmode into the integer registers. */
11269 if (d
->vmode
== V2SFmode
)
11272 mask
= (d
->one_operand_p
? nelt
- 1 : 2 * nelt
- 1);
11274 shift
= d
->perm
[0];
11275 if (BYTES_BIG_ENDIAN
&& shift
> nelt
)
11278 for (i
= 1; i
< nelt
; ++i
)
11279 if (d
->perm
[i
] != ((shift
+ i
) & mask
))
11285 hi
= shift
< nelt
? d
->op1
: d
->op0
;
11286 lo
= shift
< nelt
? d
->op0
: d
->op1
;
11290 shift
*= GET_MODE_UNIT_SIZE (d
->vmode
) * BITS_PER_UNIT
;
11292 /* We've eliminated the shift 0 case via expand_vec_perm_identity. */
11293 gcc_assert (IN_RANGE (shift
, 1, 63));
11295 /* Recall that big-endian elements are numbered starting at the top of
11296 the register. Ideally we'd have a shift-left-pair. But since we
11297 don't, convert to a shift the other direction. */
11298 if (BYTES_BIG_ENDIAN
)
11299 shift
= 64 - shift
;
11301 tmp
= gen_reg_rtx (DImode
);
11302 hi
= gen_lowpart (DImode
, hi
);
11303 lo
= gen_lowpart (DImode
, lo
);
11304 emit_insn (gen_shrp (tmp
, hi
, lo
, GEN_INT (shift
)));
11306 emit_move_insn (d
->target
, gen_lowpart (d
->vmode
, tmp
));
11310 /* Try to instantiate D in a single instruction. */
11313 expand_vec_perm_1 (struct expand_vec_perm_d
*d
)
11315 unsigned i
, nelt
= d
->nelt
;
11316 unsigned char perm2
[MAX_VECT_LEN
];
11318 /* Try single-operand selections. */
11319 if (d
->one_operand_p
)
11321 if (expand_vec_perm_identity (d
))
11323 if (expand_vselect (d
->target
, d
->op0
, d
->perm
, nelt
))
11327 /* Try two operand selections. */
11328 if (expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, d
->perm
, nelt
))
11331 /* Recognize interleave style patterns with reversed operands. */
11332 if (!d
->one_operand_p
)
11334 for (i
= 0; i
< nelt
; ++i
)
11336 unsigned e
= d
->perm
[i
];
11344 if (expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
11348 if (expand_vec_perm_shrp (d
))
11351 /* ??? Look for deposit-like permutations where most of the result
11352 comes from one vector unchanged and the rest comes from a
11353 sequential hunk of the other vector. */
11358 /* Pattern match broadcast permutations. */
11361 expand_vec_perm_broadcast (struct expand_vec_perm_d
*d
)
11363 unsigned i
, elt
, nelt
= d
->nelt
;
11364 unsigned char perm2
[2];
11368 if (!d
->one_operand_p
)
11372 for (i
= 1; i
< nelt
; ++i
)
11373 if (d
->perm
[i
] != elt
)
11380 /* Implementable by interleave. */
11382 perm2
[1] = elt
+ 2;
11383 ok
= expand_vselect_vconcat (d
->target
, d
->op0
, d
->op0
, perm2
, 2);
11388 /* Implementable by extract + broadcast. */
11389 if (BYTES_BIG_ENDIAN
)
11391 elt
*= BITS_PER_UNIT
;
11392 temp
= gen_reg_rtx (DImode
);
11393 emit_insn (gen_extzv (temp
, gen_lowpart (DImode
, d
->op0
),
11394 GEN_INT (8), GEN_INT (elt
)));
11395 emit_insn (gen_mux1_brcst_qi (d
->target
, gen_lowpart (QImode
, temp
)));
11399 /* Should have been matched directly by vec_select. */
11401 gcc_unreachable ();
11407 /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a
11408 two vector permutation into a single vector permutation by using
11409 an interleave operation to merge the vectors. */
11412 expand_vec_perm_interleave_2 (struct expand_vec_perm_d
*d
)
11414 struct expand_vec_perm_d dremap
, dfinal
;
11415 unsigned char remap
[2 * MAX_VECT_LEN
];
11416 unsigned contents
, i
, nelt
, nelt2
;
11417 unsigned h0
, h1
, h2
, h3
;
11421 if (d
->one_operand_p
)
11427 /* Examine from whence the elements come. */
11429 for (i
= 0; i
< nelt
; ++i
)
11430 contents
|= 1u << d
->perm
[i
];
11432 memset (remap
, 0xff, sizeof (remap
));
11435 h0
= (1u << nelt2
) - 1;
11438 h3
= h0
<< (nelt
+ nelt2
);
11440 if ((contents
& (h0
| h2
)) == contents
) /* punpck even halves */
11442 for (i
= 0; i
< nelt
; ++i
)
11444 unsigned which
= i
/ 2 + (i
& 1 ? nelt
: 0);
11446 dremap
.perm
[i
] = which
;
11449 else if ((contents
& (h1
| h3
)) == contents
) /* punpck odd halves */
11451 for (i
= 0; i
< nelt
; ++i
)
11453 unsigned which
= i
/ 2 + nelt2
+ (i
& 1 ? nelt
: 0);
11455 dremap
.perm
[i
] = which
;
11458 else if ((contents
& 0x5555) == contents
) /* mix even elements */
11460 for (i
= 0; i
< nelt
; ++i
)
11462 unsigned which
= (i
& ~1) + (i
& 1 ? nelt
: 0);
11464 dremap
.perm
[i
] = which
;
11467 else if ((contents
& 0xaaaa) == contents
) /* mix odd elements */
11469 for (i
= 0; i
< nelt
; ++i
)
11471 unsigned which
= (i
| 1) + (i
& 1 ? nelt
: 0);
11473 dremap
.perm
[i
] = which
;
11476 else if (floor_log2 (contents
) - ctz_hwi (contents
) < (int)nelt
) /* shrp */
11478 unsigned shift
= ctz_hwi (contents
);
11479 for (i
= 0; i
< nelt
; ++i
)
11481 unsigned which
= (i
+ shift
) & (2 * nelt
- 1);
11483 dremap
.perm
[i
] = which
;
11489 /* Use the remapping array set up above to move the elements from their
11490 swizzled locations into their final destinations. */
11492 for (i
= 0; i
< nelt
; ++i
)
11494 unsigned e
= remap
[d
->perm
[i
]];
11495 gcc_assert (e
< nelt
);
11496 dfinal
.perm
[i
] = e
;
11498 dfinal
.op0
= gen_reg_rtx (dfinal
.vmode
);
11499 dfinal
.op1
= dfinal
.op0
;
11500 dfinal
.one_operand_p
= true;
11501 dremap
.target
= dfinal
.op0
;
11503 /* Test if the final remap can be done with a single insn. For V4HImode
11504 this *will* succeed. For V8QImode or V2SImode it may not. */
11506 ok
= expand_vec_perm_1 (&dfinal
);
11507 seq
= get_insns ();
11514 ok
= expand_vec_perm_1 (&dremap
);
11521 /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode
11522 constant permutation via two mux2 and a merge. */
11525 expand_vec_perm_v4hi_5 (struct expand_vec_perm_d
*d
)
11527 unsigned char perm2
[4];
11530 rtx t0
, t1
, mask
, x
;
11533 if (d
->vmode
!= V4HImode
|| d
->one_operand_p
)
11538 for (i
= 0; i
< 4; ++i
)
11540 perm2
[i
] = d
->perm
[i
] & 3;
11541 rmask
[i
] = (d
->perm
[i
] & 4 ? const0_rtx
: constm1_rtx
);
11543 mask
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmask
));
11544 mask
= force_reg (V4HImode
, mask
);
11546 t0
= gen_reg_rtx (V4HImode
);
11547 t1
= gen_reg_rtx (V4HImode
);
11549 ok
= expand_vselect (t0
, d
->op0
, perm2
, 4);
11551 ok
= expand_vselect (t1
, d
->op1
, perm2
, 4);
11554 x
= gen_rtx_AND (V4HImode
, mask
, t0
);
11555 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
11557 x
= gen_rtx_NOT (V4HImode
, mask
);
11558 x
= gen_rtx_AND (V4HImode
, x
, t1
);
11559 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
11561 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
11562 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
11567 /* The guts of ia64_expand_vec_perm_const, also used by the ok hook.
11568 With all of the interface bits taken care of, perform the expansion
11569 in D and return true on success. */
11572 ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
11574 if (expand_vec_perm_1 (d
))
11576 if (expand_vec_perm_broadcast (d
))
11578 if (expand_vec_perm_interleave_2 (d
))
11580 if (expand_vec_perm_v4hi_5 (d
))
11586 ia64_expand_vec_perm_const (rtx operands
[4])
11588 struct expand_vec_perm_d d
;
11589 unsigned char perm
[MAX_VECT_LEN
];
11590 int i
, nelt
, which
;
11593 d
.target
= operands
[0];
11594 d
.op0
= operands
[1];
11595 d
.op1
= operands
[2];
11598 d
.vmode
= GET_MODE (d
.target
);
11599 gcc_assert (VECTOR_MODE_P (d
.vmode
));
11600 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
11601 d
.testing_p
= false;
11603 gcc_assert (GET_CODE (sel
) == CONST_VECTOR
);
11604 gcc_assert (XVECLEN (sel
, 0) == nelt
);
11605 gcc_checking_assert (sizeof (d
.perm
) == sizeof (perm
));
11607 for (i
= which
= 0; i
< nelt
; ++i
)
11609 rtx e
= XVECEXP (sel
, 0, i
);
11610 int ei
= INTVAL (e
) & (2 * nelt
- 1);
11612 which
|= (ei
< nelt
? 1 : 2);
11623 if (!rtx_equal_p (d
.op0
, d
.op1
))
11625 d
.one_operand_p
= false;
11629 /* The elements of PERM do not suggest that only the first operand
11630 is used, but both operands are identical. Allow easier matching
11631 of the permutation by folding the permutation into the single
11633 for (i
= 0; i
< nelt
; ++i
)
11634 if (d
.perm
[i
] >= nelt
)
11640 d
.one_operand_p
= true;
11644 for (i
= 0; i
< nelt
; ++i
)
11647 d
.one_operand_p
= true;
11651 if (ia64_expand_vec_perm_const_1 (&d
))
11654 /* If the mask says both arguments are needed, but they are the same,
11655 the above tried to expand with one_operand_p true. If that didn't
11656 work, retry with one_operand_p false, as that's what we used in _ok. */
11657 if (which
== 3 && d
.one_operand_p
)
11659 memcpy (d
.perm
, perm
, sizeof (perm
));
11660 d
.one_operand_p
= false;
11661 return ia64_expand_vec_perm_const_1 (&d
);
11667 /* Implement targetm.vectorize.vec_perm_const_ok. */
11670 ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
11671 const unsigned char *sel
)
11673 struct expand_vec_perm_d d
;
11674 unsigned int i
, nelt
, which
;
11678 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
11679 d
.testing_p
= true;
11681 /* Extract the values from the vector CST into the permutation
11683 memcpy (d
.perm
, sel
, nelt
);
11684 for (i
= which
= 0; i
< nelt
; ++i
)
11686 unsigned char e
= d
.perm
[i
];
11687 gcc_assert (e
< 2 * nelt
);
11688 which
|= (e
< nelt
? 1 : 2);
11691 /* For all elements from second vector, fold the elements to first. */
11693 for (i
= 0; i
< nelt
; ++i
)
11696 /* Check whether the mask can be applied to the vector type. */
11697 d
.one_operand_p
= (which
!= 3);
11699 /* Otherwise we have to go through the motions and see if we can
11700 figure out how to generate the requested permutation. */
11701 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
11702 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
11703 if (!d
.one_operand_p
)
11704 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
11707 ret
= ia64_expand_vec_perm_const_1 (&d
);
11714 ia64_expand_vec_setv2sf (rtx operands
[3])
11716 struct expand_vec_perm_d d
;
11717 unsigned int which
;
11720 d
.target
= operands
[0];
11721 d
.op0
= operands
[0];
11722 d
.op1
= gen_reg_rtx (V2SFmode
);
11723 d
.vmode
= V2SFmode
;
11725 d
.one_operand_p
= false;
11726 d
.testing_p
= false;
11728 which
= INTVAL (operands
[2]);
11729 gcc_assert (which
<= 1);
11730 d
.perm
[0] = 1 - which
;
11731 d
.perm
[1] = which
+ 2;
11733 emit_insn (gen_fpack (d
.op1
, operands
[1], CONST0_RTX (SFmode
)));
11735 ok
= ia64_expand_vec_perm_const_1 (&d
);
11740 ia64_expand_vec_perm_even_odd (rtx target
, rtx op0
, rtx op1
, int odd
)
11742 struct expand_vec_perm_d d
;
11743 enum machine_mode vmode
= GET_MODE (target
);
11744 unsigned int i
, nelt
= GET_MODE_NUNITS (vmode
);
11752 d
.one_operand_p
= false;
11753 d
.testing_p
= false;
11755 for (i
= 0; i
< nelt
; ++i
)
11756 d
.perm
[i
] = i
* 2 + odd
;
11758 ok
= ia64_expand_vec_perm_const_1 (&d
);
11762 #include "gt-ia64.h"