1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
4 Free Software Foundation, Inc.
5 Contributed by James E. Wilson <wilson@cygnus.com> and
6 David Mosberger <davidm@hpl.hp.com>.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "diagnostic-core.h"
47 #include "sched-int.h"
50 #include "target-def.h"
53 #include "langhooks.h"
54 #include "cfglayout.h"
61 #include "tm-constrs.h"
62 #include "sel-sched.h"
65 /* This is used for communication between ASM_OUTPUT_LABEL and
66 ASM_OUTPUT_LABELREF. */
67 int ia64_asm_output_label
= 0;
69 /* Register names for ia64_expand_prologue. */
70 static const char * const ia64_reg_numbers
[96] =
71 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
72 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
73 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
74 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
75 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
76 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
77 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
78 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
79 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
80 "r104","r105","r106","r107","r108","r109","r110","r111",
81 "r112","r113","r114","r115","r116","r117","r118","r119",
82 "r120","r121","r122","r123","r124","r125","r126","r127"};
84 /* ??? These strings could be shared with REGISTER_NAMES. */
85 static const char * const ia64_input_reg_names
[8] =
86 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
88 /* ??? These strings could be shared with REGISTER_NAMES. */
89 static const char * const ia64_local_reg_names
[80] =
90 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
91 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
92 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
93 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
94 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
95 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
96 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
97 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
98 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
99 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
101 /* ??? These strings could be shared with REGISTER_NAMES. */
102 static const char * const ia64_output_reg_names
[8] =
103 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
105 /* Which cpu are we scheduling for. */
106 enum processor_type ia64_tune
= PROCESSOR_ITANIUM2
;
108 /* Determines whether we run our final scheduling pass or not. We always
109 avoid the normal second scheduling pass. */
110 static int ia64_flag_schedule_insns2
;
112 /* Determines whether we run variable tracking in machine dependent
114 static int ia64_flag_var_tracking
;
116 /* Variables which are this size or smaller are put in the sdata/sbss
119 unsigned int ia64_section_threshold
;
121 /* The following variable is used by the DFA insn scheduler. The value is
122 TRUE if we do insn bundling instead of insn scheduling. */
134 number_of_ia64_frame_regs
137 /* Structure to be filled in by ia64_compute_frame_size with register
138 save masks and offsets for the current function. */
140 struct ia64_frame_info
142 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
143 the caller's scratch area. */
144 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
145 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
146 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
147 HARD_REG_SET mask
; /* mask of saved registers. */
148 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
149 registers or long-term scratches. */
150 int n_spilled
; /* number of spilled registers. */
151 int r
[number_of_ia64_frame_regs
]; /* Frame related registers. */
152 int n_input_regs
; /* number of input registers used. */
153 int n_local_regs
; /* number of local registers used. */
154 int n_output_regs
; /* number of output registers used. */
155 int n_rotate_regs
; /* number of rotating registers used. */
157 char need_regstk
; /* true if a .regstk directive needed. */
158 char initialized
; /* true if the data is finalized. */
161 /* Current frame information calculated by ia64_compute_frame_size. */
162 static struct ia64_frame_info current_frame_info
;
163 /* The actual registers that are emitted. */
164 static int emitted_frame_related_regs
[number_of_ia64_frame_regs
];
166 static int ia64_first_cycle_multipass_dfa_lookahead (void);
167 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
168 static void ia64_init_dfa_pre_cycle_insn (void);
169 static rtx
ia64_dfa_pre_cycle_insn (void);
170 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
171 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx
);
172 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
173 static void ia64_h_i_d_extended (void);
174 static void * ia64_alloc_sched_context (void);
175 static void ia64_init_sched_context (void *, bool);
176 static void ia64_set_sched_context (void *);
177 static void ia64_clear_sched_context (void *);
178 static void ia64_free_sched_context (void *);
179 static int ia64_mode_to_int (enum machine_mode
);
180 static void ia64_set_sched_flags (spec_info_t
);
181 static ds_t
ia64_get_insn_spec_ds (rtx
);
182 static ds_t
ia64_get_insn_checked_ds (rtx
);
183 static bool ia64_skip_rtx_p (const_rtx
);
184 static int ia64_speculate_insn (rtx
, ds_t
, rtx
*);
185 static bool ia64_needs_block_p (int);
186 static rtx
ia64_gen_spec_check (rtx
, rtx
, ds_t
);
187 static int ia64_spec_check_p (rtx
);
188 static int ia64_spec_check_src_p (rtx
);
189 static rtx
gen_tls_get_addr (void);
190 static rtx
gen_thread_pointer (void);
191 static int find_gr_spill (enum ia64_frame_regs
, int);
192 static int next_scratch_gr_reg (void);
193 static void mark_reg_gr_used_mask (rtx
, void *);
194 static void ia64_compute_frame_size (HOST_WIDE_INT
);
195 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
196 static void finish_spill_pointers (void);
197 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
198 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
199 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
200 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
201 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
202 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
204 static void ia64_option_override (void);
205 static void ia64_option_optimization (int, int);
206 static bool ia64_can_eliminate (const int, const int);
207 static enum machine_mode
hfa_element_mode (const_tree
, bool);
208 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
210 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
212 static bool ia64_function_ok_for_sibcall (tree
, tree
);
213 static bool ia64_return_in_memory (const_tree
, const_tree
);
214 static rtx
ia64_function_value (const_tree
, const_tree
, bool);
215 static rtx
ia64_libcall_value (enum machine_mode
, const_rtx
);
216 static bool ia64_function_value_regno_p (const unsigned int);
217 static int ia64_register_move_cost (enum machine_mode
, reg_class_t
,
219 static int ia64_memory_move_cost (enum machine_mode mode
, reg_class_t
,
221 static bool ia64_rtx_costs (rtx
, int, int, int *, bool);
222 static int ia64_unspec_may_trap_p (const_rtx
, unsigned);
223 static void fix_range (const char *);
224 static bool ia64_handle_option (size_t, const char *, int);
225 static struct machine_function
* ia64_init_machine_status (void);
226 static void emit_insn_group_barriers (FILE *);
227 static void emit_all_insn_group_barriers (FILE *);
228 static void final_emit_insn_group_barriers (FILE *);
229 static void emit_predicate_relation_info (void);
230 static void ia64_reorg (void);
231 static bool ia64_in_small_data_p (const_tree
);
232 static void process_epilogue (FILE *, rtx
, bool, bool);
234 static bool ia64_assemble_integer (rtx
, unsigned int, int);
235 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
236 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
237 static void ia64_output_function_end_prologue (FILE *);
239 static int ia64_issue_rate (void);
240 static int ia64_adjust_cost_2 (rtx
, int, rtx
, int, dw_t
);
241 static void ia64_sched_init (FILE *, int, int);
242 static void ia64_sched_init_global (FILE *, int, int);
243 static void ia64_sched_finish_global (FILE *, int);
244 static void ia64_sched_finish (FILE *, int);
245 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
246 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
247 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
248 static int ia64_variable_issue (FILE *, int, rtx
, int);
250 static void ia64_asm_unwind_emit (FILE *, rtx
);
251 static void ia64_asm_emit_except_personality (rtx
);
252 static void ia64_asm_init_sections (void);
254 static enum unwind_info_type
ia64_debug_unwind_info (void);
255 static enum unwind_info_type
ia64_except_unwind_info (void);
257 static struct bundle_state
*get_free_bundle_state (void);
258 static void free_bundle_state (struct bundle_state
*);
259 static void initiate_bundle_states (void);
260 static void finish_bundle_states (void);
261 static unsigned bundle_state_hash (const void *);
262 static int bundle_state_eq_p (const void *, const void *);
263 static int insert_bundle_state (struct bundle_state
*);
264 static void initiate_bundle_state_table (void);
265 static void finish_bundle_state_table (void);
266 static int try_issue_nops (struct bundle_state
*, int);
267 static int try_issue_insn (struct bundle_state
*, rtx
);
268 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
269 static int get_max_pos (state_t
);
270 static int get_template (state_t
, int);
272 static rtx
get_next_important_insn (rtx
, rtx
);
273 static bool important_for_bundling_p (rtx
);
274 static void bundling (FILE *, int, rtx
, rtx
);
276 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
277 HOST_WIDE_INT
, tree
);
278 static void ia64_file_start (void);
279 static void ia64_globalize_decl_name (FILE *, tree
);
281 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
282 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
283 static section
*ia64_select_rtx_section (enum machine_mode
, rtx
,
284 unsigned HOST_WIDE_INT
);
285 static void ia64_output_dwarf_dtprel (FILE *, int, rtx
)
287 static unsigned int ia64_section_type_flags (tree
, const char *, int);
288 static void ia64_init_libfuncs (void)
290 static void ia64_hpux_init_libfuncs (void)
292 static void ia64_sysv4_init_libfuncs (void)
294 static void ia64_vms_init_libfuncs (void)
296 static void ia64_soft_fp_init_libfuncs (void)
298 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode
)
300 static tree
ia64_vms_common_object_attribute (tree
*, tree
, tree
, int, bool *)
303 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
304 static tree
ia64_handle_version_id_attribute (tree
*, tree
, tree
, int, bool *);
305 static void ia64_encode_section_info (tree
, rtx
, int);
306 static rtx
ia64_struct_value_rtx (tree
, int);
307 static tree
ia64_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
308 static bool ia64_scalar_mode_supported_p (enum machine_mode mode
);
309 static bool ia64_vector_mode_supported_p (enum machine_mode mode
);
310 static bool ia64_cannot_force_const_mem (rtx
);
311 static const char *ia64_mangle_type (const_tree
);
312 static const char *ia64_invalid_conversion (const_tree
, const_tree
);
313 static const char *ia64_invalid_unary_op (int, const_tree
);
314 static const char *ia64_invalid_binary_op (int, const_tree
, const_tree
);
315 static enum machine_mode
ia64_c_mode_for_suffix (char);
316 static enum machine_mode
ia64_promote_function_mode (const_tree
,
321 static void ia64_trampoline_init (rtx
, tree
, rtx
);
322 static void ia64_override_options_after_change (void);
324 static void ia64_dwarf_handle_frame_unspec (const char *, rtx
, int);
325 static tree
ia64_builtin_decl (unsigned, bool);
327 /* Table of valid machine attributes. */
328 static const struct attribute_spec ia64_attribute_table
[] =
330 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
331 { "syscall_linkage", 0, 0, false, true, true, NULL
},
332 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
},
333 #if TARGET_ABI_OPEN_VMS
334 { "common_object", 1, 1, true, false, false, ia64_vms_common_object_attribute
},
336 { "version_id", 1, 1, true, false, false,
337 ia64_handle_version_id_attribute
},
338 { NULL
, 0, 0, false, false, false, NULL
}
341 /* Initialize the GCC target structure. */
342 #undef TARGET_ATTRIBUTE_TABLE
343 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
345 #undef TARGET_INIT_BUILTINS
346 #define TARGET_INIT_BUILTINS ia64_init_builtins
348 #undef TARGET_EXPAND_BUILTIN
349 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
351 #undef TARGET_BUILTIN_DECL
352 #define TARGET_BUILTIN_DECL ia64_builtin_decl
354 #undef TARGET_ASM_BYTE_OP
355 #define TARGET_ASM_BYTE_OP "\tdata1\t"
356 #undef TARGET_ASM_ALIGNED_HI_OP
357 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
358 #undef TARGET_ASM_ALIGNED_SI_OP
359 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
360 #undef TARGET_ASM_ALIGNED_DI_OP
361 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
362 #undef TARGET_ASM_UNALIGNED_HI_OP
363 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
364 #undef TARGET_ASM_UNALIGNED_SI_OP
365 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
366 #undef TARGET_ASM_UNALIGNED_DI_OP
367 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
368 #undef TARGET_ASM_INTEGER
369 #define TARGET_ASM_INTEGER ia64_assemble_integer
371 #undef TARGET_OPTION_OVERRIDE
372 #define TARGET_OPTION_OVERRIDE ia64_option_override
373 #undef TARGET_OPTION_OPTIMIZATION
374 #define TARGET_OPTION_OPTIMIZATION ia64_option_optimization
376 #undef TARGET_ASM_FUNCTION_PROLOGUE
377 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
378 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
379 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
380 #undef TARGET_ASM_FUNCTION_EPILOGUE
381 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
383 #undef TARGET_IN_SMALL_DATA_P
384 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
386 #undef TARGET_SCHED_ADJUST_COST_2
387 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
388 #undef TARGET_SCHED_ISSUE_RATE
389 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
390 #undef TARGET_SCHED_VARIABLE_ISSUE
391 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
392 #undef TARGET_SCHED_INIT
393 #define TARGET_SCHED_INIT ia64_sched_init
394 #undef TARGET_SCHED_FINISH
395 #define TARGET_SCHED_FINISH ia64_sched_finish
396 #undef TARGET_SCHED_INIT_GLOBAL
397 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
398 #undef TARGET_SCHED_FINISH_GLOBAL
399 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
400 #undef TARGET_SCHED_REORDER
401 #define TARGET_SCHED_REORDER ia64_sched_reorder
402 #undef TARGET_SCHED_REORDER2
403 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
405 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
406 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
408 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
409 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
411 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
412 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
413 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
414 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
416 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
417 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
418 ia64_first_cycle_multipass_dfa_lookahead_guard
420 #undef TARGET_SCHED_DFA_NEW_CYCLE
421 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
423 #undef TARGET_SCHED_H_I_D_EXTENDED
424 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
426 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
427 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
429 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
430 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
432 #undef TARGET_SCHED_SET_SCHED_CONTEXT
433 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
435 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
436 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
438 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
439 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
441 #undef TARGET_SCHED_SET_SCHED_FLAGS
442 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
444 #undef TARGET_SCHED_GET_INSN_SPEC_DS
445 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
447 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
448 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
450 #undef TARGET_SCHED_SPECULATE_INSN
451 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
453 #undef TARGET_SCHED_NEEDS_BLOCK_P
454 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
456 #undef TARGET_SCHED_GEN_SPEC_CHECK
457 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
459 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
460 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
461 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
463 #undef TARGET_SCHED_SKIP_RTX_P
464 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
466 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
467 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
468 #undef TARGET_ARG_PARTIAL_BYTES
469 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
471 #undef TARGET_ASM_OUTPUT_MI_THUNK
472 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
473 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
474 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
476 #undef TARGET_ASM_FILE_START
477 #define TARGET_ASM_FILE_START ia64_file_start
479 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
480 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
482 #undef TARGET_REGISTER_MOVE_COST
483 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
484 #undef TARGET_MEMORY_MOVE_COST
485 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
486 #undef TARGET_RTX_COSTS
487 #define TARGET_RTX_COSTS ia64_rtx_costs
488 #undef TARGET_ADDRESS_COST
489 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
491 #undef TARGET_UNSPEC_MAY_TRAP_P
492 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
494 #undef TARGET_MACHINE_DEPENDENT_REORG
495 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
497 #undef TARGET_ENCODE_SECTION_INFO
498 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
500 #undef TARGET_SECTION_TYPE_FLAGS
501 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
504 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
505 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
508 #undef TARGET_PROMOTE_FUNCTION_MODE
509 #define TARGET_PROMOTE_FUNCTION_MODE ia64_promote_function_mode
511 /* ??? Investigate. */
513 #undef TARGET_PROMOTE_PROTOTYPES
514 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
517 #undef TARGET_FUNCTION_VALUE
518 #define TARGET_FUNCTION_VALUE ia64_function_value
519 #undef TARGET_LIBCALL_VALUE
520 #define TARGET_LIBCALL_VALUE ia64_libcall_value
521 #undef TARGET_FUNCTION_VALUE_REGNO_P
522 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
524 #undef TARGET_STRUCT_VALUE_RTX
525 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
526 #undef TARGET_RETURN_IN_MEMORY
527 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
528 #undef TARGET_SETUP_INCOMING_VARARGS
529 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
530 #undef TARGET_STRICT_ARGUMENT_NAMING
531 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
532 #undef TARGET_MUST_PASS_IN_STACK
533 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
535 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
536 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
538 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
539 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ia64_dwarf_handle_frame_unspec
540 #undef TARGET_ASM_UNWIND_EMIT
541 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
542 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
543 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
544 #undef TARGET_ASM_INIT_SECTIONS
545 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
547 #undef TARGET_DEBUG_UNWIND_INFO
548 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
549 #undef TARGET_EXCEPT_UNWIND_INFO
550 #define TARGET_EXCEPT_UNWIND_INFO ia64_except_unwind_info
552 #undef TARGET_SCALAR_MODE_SUPPORTED_P
553 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
554 #undef TARGET_VECTOR_MODE_SUPPORTED_P
555 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
557 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
558 in an order different from the specified program order. */
559 #undef TARGET_RELAXED_ORDERING
560 #define TARGET_RELAXED_ORDERING true
562 #undef TARGET_DEFAULT_TARGET_FLAGS
563 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
564 #undef TARGET_HANDLE_OPTION
565 #define TARGET_HANDLE_OPTION ia64_handle_option
567 #undef TARGET_CANNOT_FORCE_CONST_MEM
568 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
570 #undef TARGET_MANGLE_TYPE
571 #define TARGET_MANGLE_TYPE ia64_mangle_type
573 #undef TARGET_INVALID_CONVERSION
574 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
575 #undef TARGET_INVALID_UNARY_OP
576 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
577 #undef TARGET_INVALID_BINARY_OP
578 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
580 #undef TARGET_C_MODE_FOR_SUFFIX
581 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
583 #undef TARGET_CAN_ELIMINATE
584 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
586 #undef TARGET_TRAMPOLINE_INIT
587 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
589 #undef TARGET_INVALID_WITHIN_DOLOOP
590 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
592 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
593 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
595 struct gcc_target targetm
= TARGET_INITIALIZER
;
599 ADDR_AREA_NORMAL
, /* normal address area */
600 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
604 static GTY(()) tree small_ident1
;
605 static GTY(()) tree small_ident2
;
610 if (small_ident1
== 0)
612 small_ident1
= get_identifier ("small");
613 small_ident2
= get_identifier ("__small__");
617 /* Retrieve the address area that has been chosen for the given decl. */
619 static ia64_addr_area
620 ia64_get_addr_area (tree decl
)
624 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
630 id
= TREE_VALUE (TREE_VALUE (model_attr
));
631 if (id
== small_ident1
|| id
== small_ident2
)
632 return ADDR_AREA_SMALL
;
634 return ADDR_AREA_NORMAL
;
638 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
,
639 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
641 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
643 tree arg
, decl
= *node
;
646 arg
= TREE_VALUE (args
);
647 if (arg
== small_ident1
|| arg
== small_ident2
)
649 addr_area
= ADDR_AREA_SMALL
;
653 warning (OPT_Wattributes
, "invalid argument of %qE attribute",
655 *no_add_attrs
= true;
658 switch (TREE_CODE (decl
))
661 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
663 && !TREE_STATIC (decl
))
665 error_at (DECL_SOURCE_LOCATION (decl
),
666 "an address area attribute cannot be specified for "
668 *no_add_attrs
= true;
670 area
= ia64_get_addr_area (decl
);
671 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
673 error ("address area of %q+D conflicts with previous "
674 "declaration", decl
);
675 *no_add_attrs
= true;
680 error_at (DECL_SOURCE_LOCATION (decl
),
681 "address area attribute cannot be specified for "
683 *no_add_attrs
= true;
687 warning (OPT_Wattributes
, "%qE attribute ignored",
689 *no_add_attrs
= true;
696 /* The section must have global and overlaid attributes. */
697 #define SECTION_VMS_OVERLAY SECTION_MACH_DEP
699 /* Part of the low level implementation of DEC Ada pragma Common_Object which
700 enables the shared use of variables stored in overlaid linker areas
701 corresponding to the use of Fortran COMMON. */
704 ia64_vms_common_object_attribute (tree
*node
, tree name
, tree args
,
705 int flags ATTRIBUTE_UNUSED
,
713 DECL_COMMON (decl
) = 1;
714 id
= TREE_VALUE (args
);
715 if (TREE_CODE (id
) == IDENTIFIER_NODE
)
716 val
= build_string (IDENTIFIER_LENGTH (id
), IDENTIFIER_POINTER (id
));
717 else if (TREE_CODE (id
) == STRING_CST
)
721 warning (OPT_Wattributes
,
722 "%qE attribute requires a string constant argument", name
);
723 *no_add_attrs
= true;
726 DECL_SECTION_NAME (decl
) = val
;
730 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
733 ia64_vms_output_aligned_decl_common (FILE *file
, tree decl
, const char *name
,
734 unsigned HOST_WIDE_INT size
,
737 tree attr
= DECL_ATTRIBUTES (decl
);
739 /* As common_object attribute set DECL_SECTION_NAME check it before
740 looking up the attribute. */
741 if (DECL_SECTION_NAME (decl
) && attr
)
742 attr
= lookup_attribute ("common_object", attr
);
748 /* Code from elfos.h. */
749 fprintf (file
, "%s", COMMON_ASM_OP
);
750 assemble_name (file
, name
);
751 fprintf (file
, ","HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
752 size
, align
/ BITS_PER_UNIT
);
756 ASM_OUTPUT_ALIGN (file
, floor_log2 (align
/ BITS_PER_UNIT
));
757 ASM_OUTPUT_LABEL (file
, name
);
758 ASM_OUTPUT_SKIP (file
, size
? size
: 1);
762 /* Definition of TARGET_ASM_NAMED_SECTION for VMS. */
765 ia64_vms_elf_asm_named_section (const char *name
, unsigned int flags
,
768 if (!(flags
& SECTION_VMS_OVERLAY
))
770 default_elf_asm_named_section (name
, flags
, decl
);
773 if (flags
!= (SECTION_VMS_OVERLAY
| SECTION_WRITE
))
776 if (flags
& SECTION_DECLARED
)
778 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
782 fprintf (asm_out_file
, "\t.section\t%s,\"awgO\"\n", name
);
786 ia64_encode_addr_area (tree decl
, rtx symbol
)
790 flags
= SYMBOL_REF_FLAGS (symbol
);
791 switch (ia64_get_addr_area (decl
))
793 case ADDR_AREA_NORMAL
: break;
794 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
795 default: gcc_unreachable ();
797 SYMBOL_REF_FLAGS (symbol
) = flags
;
801 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
803 default_encode_section_info (decl
, rtl
, first
);
805 /* Careful not to prod global register variables. */
806 if (TREE_CODE (decl
) == VAR_DECL
807 && GET_CODE (DECL_RTL (decl
)) == MEM
808 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
809 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
810 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
813 /* Return 1 if the operands of a move are ok. */
816 ia64_move_ok (rtx dst
, rtx src
)
818 /* If we're under init_recog_no_volatile, we'll not be able to use
819 memory_operand. So check the code directly and don't worry about
820 the validity of the underlying address, which should have been
821 checked elsewhere anyway. */
822 if (GET_CODE (dst
) != MEM
)
824 if (GET_CODE (src
) == MEM
)
826 if (register_operand (src
, VOIDmode
))
829 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
830 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
831 return src
== const0_rtx
;
833 return satisfies_constraint_G (src
);
836 /* Return 1 if the operands are ok for a floating point load pair. */
839 ia64_load_pair_ok (rtx dst
, rtx src
)
841 if (GET_CODE (dst
) != REG
|| !FP_REGNO_P (REGNO (dst
)))
843 if (GET_CODE (src
) != MEM
|| MEM_VOLATILE_P (src
))
845 switch (GET_CODE (XEXP (src
, 0)))
854 rtx adjust
= XEXP (XEXP (XEXP (src
, 0), 1), 1);
856 if (GET_CODE (adjust
) != CONST_INT
857 || INTVAL (adjust
) != GET_MODE_SIZE (GET_MODE (src
)))
868 addp4_optimize_ok (rtx op1
, rtx op2
)
870 return (basereg_operand (op1
, GET_MODE(op1
)) !=
871 basereg_operand (op2
, GET_MODE(op2
)));
874 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
875 Return the length of the field, or <= 0 on failure. */
878 ia64_depz_field_mask (rtx rop
, rtx rshift
)
880 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
881 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
883 /* Get rid of the zero bits we're shifting in. */
886 /* We must now have a solid block of 1's at bit 0. */
887 return exact_log2 (op
+ 1);
890 /* Return the TLS model to use for ADDR. */
892 static enum tls_model
893 tls_symbolic_operand_type (rtx addr
)
895 enum tls_model tls_kind
= TLS_MODEL_NONE
;
897 if (GET_CODE (addr
) == CONST
)
899 if (GET_CODE (XEXP (addr
, 0)) == PLUS
900 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
901 tls_kind
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr
, 0), 0));
903 else if (GET_CODE (addr
) == SYMBOL_REF
)
904 tls_kind
= SYMBOL_REF_TLS_MODEL (addr
);
909 /* Return true if X is a constant that is valid for some immediate
910 field in an instruction. */
913 ia64_legitimate_constant_p (rtx x
)
915 switch (GET_CODE (x
))
922 if (GET_MODE (x
) == VOIDmode
|| GET_MODE (x
) == SFmode
923 || GET_MODE (x
) == DFmode
)
925 return satisfies_constraint_G (x
);
929 /* ??? Short term workaround for PR 28490. We must make the code here
930 match the code in ia64_expand_move and move_operand, even though they
931 are both technically wrong. */
932 if (tls_symbolic_operand_type (x
) == 0)
934 HOST_WIDE_INT addend
= 0;
937 if (GET_CODE (op
) == CONST
938 && GET_CODE (XEXP (op
, 0)) == PLUS
939 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
941 addend
= INTVAL (XEXP (XEXP (op
, 0), 1));
942 op
= XEXP (XEXP (op
, 0), 0);
945 if (any_offset_symbol_operand (op
, GET_MODE (op
))
946 || function_operand (op
, GET_MODE (op
)))
948 if (aligned_offset_symbol_operand (op
, GET_MODE (op
)))
949 return (addend
& 0x3fff) == 0;
956 enum machine_mode mode
= GET_MODE (x
);
958 if (mode
== V2SFmode
)
959 return satisfies_constraint_Y (x
);
961 return (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
962 && GET_MODE_SIZE (mode
) <= 8);
970 /* Don't allow TLS addresses to get spilled to memory. */
973 ia64_cannot_force_const_mem (rtx x
)
975 if (GET_MODE (x
) == RFmode
)
977 return tls_symbolic_operand_type (x
) != 0;
980 /* Expand a symbolic constant load. */
983 ia64_expand_load_address (rtx dest
, rtx src
)
985 gcc_assert (GET_CODE (dest
) == REG
);
987 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
988 having to pointer-extend the value afterward. Other forms of address
989 computation below are also more natural to compute as 64-bit quantities.
990 If we've been given an SImode destination register, change it. */
991 if (GET_MODE (dest
) != Pmode
)
992 dest
= gen_rtx_REG_offset (dest
, Pmode
, REGNO (dest
),
993 byte_lowpart_offset (Pmode
, GET_MODE (dest
)));
997 if (small_addr_symbolic_operand (src
, VOIDmode
))
1000 if (TARGET_AUTO_PIC
)
1001 emit_insn (gen_load_gprel64 (dest
, src
));
1002 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1003 emit_insn (gen_load_fptr (dest
, src
));
1004 else if (sdata_symbolic_operand (src
, VOIDmode
))
1005 emit_insn (gen_load_gprel (dest
, src
));
1008 HOST_WIDE_INT addend
= 0;
1011 /* We did split constant offsets in ia64_expand_move, and we did try
1012 to keep them split in move_operand, but we also allowed reload to
1013 rematerialize arbitrary constants rather than spill the value to
1014 the stack and reload it. So we have to be prepared here to split
1015 them apart again. */
1016 if (GET_CODE (src
) == CONST
)
1018 HOST_WIDE_INT hi
, lo
;
1020 hi
= INTVAL (XEXP (XEXP (src
, 0), 1));
1021 lo
= ((hi
& 0x3fff) ^ 0x2000) - 0x2000;
1027 src
= plus_constant (XEXP (XEXP (src
, 0), 0), hi
);
1031 tmp
= gen_rtx_HIGH (Pmode
, src
);
1032 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1033 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1035 tmp
= gen_rtx_LO_SUM (Pmode
, dest
, src
);
1036 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1040 tmp
= gen_rtx_PLUS (Pmode
, dest
, GEN_INT (addend
));
1041 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1048 static GTY(()) rtx gen_tls_tga
;
1050 gen_tls_get_addr (void)
1053 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1057 static GTY(()) rtx thread_pointer_rtx
;
1059 gen_thread_pointer (void)
1061 if (!thread_pointer_rtx
)
1062 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1063 return thread_pointer_rtx
;
1067 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
,
1068 rtx orig_op1
, HOST_WIDE_INT addend
)
1070 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1072 HOST_WIDE_INT addend_lo
, addend_hi
;
1076 case TLS_MODEL_GLOBAL_DYNAMIC
:
1079 tga_op1
= gen_reg_rtx (Pmode
);
1080 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1082 tga_op2
= gen_reg_rtx (Pmode
);
1083 emit_insn (gen_load_dtprel (tga_op2
, op1
));
1085 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1086 LCT_CONST
, Pmode
, 2, tga_op1
,
1087 Pmode
, tga_op2
, Pmode
);
1089 insns
= get_insns ();
1092 if (GET_MODE (op0
) != Pmode
)
1094 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1097 case TLS_MODEL_LOCAL_DYNAMIC
:
1098 /* ??? This isn't the completely proper way to do local-dynamic
1099 If the call to __tls_get_addr is used only by a single symbol,
1100 then we should (somehow) move the dtprel to the second arg
1101 to avoid the extra add. */
1104 tga_op1
= gen_reg_rtx (Pmode
);
1105 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1107 tga_op2
= const0_rtx
;
1109 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1110 LCT_CONST
, Pmode
, 2, tga_op1
,
1111 Pmode
, tga_op2
, Pmode
);
1113 insns
= get_insns ();
1116 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1118 tmp
= gen_reg_rtx (Pmode
);
1119 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1121 if (!register_operand (op0
, Pmode
))
1122 op0
= gen_reg_rtx (Pmode
);
1125 emit_insn (gen_load_dtprel (op0
, op1
));
1126 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1129 emit_insn (gen_add_dtprel (op0
, op1
, tmp
));
1132 case TLS_MODEL_INITIAL_EXEC
:
1133 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1134 addend_hi
= addend
- addend_lo
;
1136 op1
= plus_constant (op1
, addend_hi
);
1139 tmp
= gen_reg_rtx (Pmode
);
1140 emit_insn (gen_load_tprel (tmp
, op1
));
1142 if (!register_operand (op0
, Pmode
))
1143 op0
= gen_reg_rtx (Pmode
);
1144 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1147 case TLS_MODEL_LOCAL_EXEC
:
1148 if (!register_operand (op0
, Pmode
))
1149 op0
= gen_reg_rtx (Pmode
);
1155 emit_insn (gen_load_tprel (op0
, op1
));
1156 emit_insn (gen_adddi3 (op0
, op0
, gen_thread_pointer ()));
1159 emit_insn (gen_add_tprel (op0
, op1
, gen_thread_pointer ()));
1167 op0
= expand_simple_binop (Pmode
, PLUS
, op0
, GEN_INT (addend
),
1168 orig_op0
, 1, OPTAB_DIRECT
);
1169 if (orig_op0
== op0
)
1171 if (GET_MODE (orig_op0
) == Pmode
)
1173 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1177 ia64_expand_move (rtx op0
, rtx op1
)
1179 enum machine_mode mode
= GET_MODE (op0
);
1181 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1182 op1
= force_reg (mode
, op1
);
1184 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1186 HOST_WIDE_INT addend
= 0;
1187 enum tls_model tls_kind
;
1190 if (GET_CODE (op1
) == CONST
1191 && GET_CODE (XEXP (op1
, 0)) == PLUS
1192 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
)
1194 addend
= INTVAL (XEXP (XEXP (op1
, 0), 1));
1195 sym
= XEXP (XEXP (op1
, 0), 0);
1198 tls_kind
= tls_symbolic_operand_type (sym
);
1200 return ia64_expand_tls_address (tls_kind
, op0
, sym
, op1
, addend
);
1202 if (any_offset_symbol_operand (sym
, mode
))
1204 else if (aligned_offset_symbol_operand (sym
, mode
))
1206 HOST_WIDE_INT addend_lo
, addend_hi
;
1208 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1209 addend_hi
= addend
- addend_lo
;
1213 op1
= plus_constant (sym
, addend_hi
);
1222 if (reload_completed
)
1224 /* We really should have taken care of this offset earlier. */
1225 gcc_assert (addend
== 0);
1226 if (ia64_expand_load_address (op0
, op1
))
1232 rtx subtarget
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (mode
);
1234 emit_insn (gen_rtx_SET (VOIDmode
, subtarget
, op1
));
1236 op1
= expand_simple_binop (mode
, PLUS
, subtarget
,
1237 GEN_INT (addend
), op0
, 1, OPTAB_DIRECT
);
1246 /* Split a move from OP1 to OP0 conditional on COND. */
1249 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1251 rtx insn
, first
= get_last_insn ();
1253 emit_move_insn (op0
, op1
);
1255 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1257 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1261 /* Split a post-reload TImode or TFmode reference into two DImode
1262 components. This is made extra difficult by the fact that we do
1263 not get any scratch registers to work with, because reload cannot
1264 be prevented from giving us a scratch that overlaps the register
1265 pair involved. So instead, when addressing memory, we tweak the
1266 pointer register up and back down with POST_INCs. Or up and not
1267 back down when we can get away with it.
1269 REVERSED is true when the loads must be done in reversed order
1270 (high word first) for correctness. DEAD is true when the pointer
1271 dies with the second insn we generate and therefore the second
1272 address must not carry a postmodify.
1274 May return an insn which is to be emitted after the moves. */
1277 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1281 switch (GET_CODE (in
))
1284 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1285 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1290 /* Cannot occur reversed. */
1291 gcc_assert (!reversed
);
1293 if (GET_MODE (in
) != TFmode
)
1294 split_double (in
, &out
[0], &out
[1]);
1296 /* split_double does not understand how to split a TFmode
1297 quantity into a pair of DImode constants. */
1300 unsigned HOST_WIDE_INT p
[2];
1301 long l
[4]; /* TFmode is 128 bits */
1303 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1304 real_to_target (l
, &r
, TFmode
);
1306 if (FLOAT_WORDS_BIG_ENDIAN
)
1308 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1309 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1313 p
[0] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1314 p
[1] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1316 out
[0] = GEN_INT (p
[0]);
1317 out
[1] = GEN_INT (p
[1]);
1323 rtx base
= XEXP (in
, 0);
1326 switch (GET_CODE (base
))
1331 out
[0] = adjust_automodify_address
1332 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1333 out
[1] = adjust_automodify_address
1334 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1338 /* Reversal requires a pre-increment, which can only
1339 be done as a separate insn. */
1340 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1341 out
[0] = adjust_automodify_address
1342 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1343 out
[1] = adjust_address (in
, DImode
, 0);
1348 gcc_assert (!reversed
&& !dead
);
1350 /* Just do the increment in two steps. */
1351 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1352 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1356 gcc_assert (!reversed
&& !dead
);
1358 /* Add 8, subtract 24. */
1359 base
= XEXP (base
, 0);
1360 out
[0] = adjust_automodify_address
1361 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1362 out
[1] = adjust_automodify_address
1364 gen_rtx_POST_MODIFY (Pmode
, base
, plus_constant (base
, -24)),
1369 gcc_assert (!reversed
&& !dead
);
1371 /* Extract and adjust the modification. This case is
1372 trickier than the others, because we might have an
1373 index register, or we might have a combined offset that
1374 doesn't fit a signed 9-bit displacement field. We can
1375 assume the incoming expression is already legitimate. */
1376 offset
= XEXP (base
, 1);
1377 base
= XEXP (base
, 0);
1379 out
[0] = adjust_automodify_address
1380 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1382 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1384 /* Can't adjust the postmodify to match. Emit the
1385 original, then a separate addition insn. */
1386 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1387 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1391 gcc_assert (GET_CODE (XEXP (offset
, 1)) == CONST_INT
);
1392 if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1394 /* Again the postmodify cannot be made to match,
1395 but in this case it's more efficient to get rid
1396 of the postmodify entirely and fix up with an
1398 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1400 (base
, base
, GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1404 /* Combined offset still fits in the displacement field.
1405 (We cannot overflow it at the high end.) */
1406 out
[1] = adjust_automodify_address
1407 (in
, DImode
, gen_rtx_POST_MODIFY
1408 (Pmode
, base
, gen_rtx_PLUS
1410 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1429 /* Split a TImode or TFmode move instruction after reload.
1430 This is used by *movtf_internal and *movti_internal. */
1432 ia64_split_tmode_move (rtx operands
[])
1434 rtx in
[2], out
[2], insn
;
1437 bool reversed
= false;
1439 /* It is possible for reload to decide to overwrite a pointer with
1440 the value it points to. In that case we have to do the loads in
1441 the appropriate order so that the pointer is not destroyed too
1442 early. Also we must not generate a postmodify for that second
1443 load, or rws_access_regno will die. */
1444 if (GET_CODE (operands
[1]) == MEM
1445 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1447 rtx base
= XEXP (operands
[1], 0);
1448 while (GET_CODE (base
) != REG
)
1449 base
= XEXP (base
, 0);
1451 if (REGNO (base
) == REGNO (operands
[0]))
1455 /* Another reason to do the moves in reversed order is if the first
1456 element of the target register pair is also the second element of
1457 the source register pair. */
1458 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1459 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1462 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1463 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1465 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1466 if (GET_CODE (EXP) == MEM \
1467 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1468 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1469 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1470 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1472 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1473 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1474 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1476 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1477 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1478 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1481 emit_insn (fixup
[0]);
1483 emit_insn (fixup
[1]);
1485 #undef MAYBE_ADD_REG_INC_NOTE
1488 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1489 through memory plus an extra GR scratch register. Except that you can
1490 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1491 SECONDARY_RELOAD_CLASS, but not both.
1493 We got into problems in the first place by allowing a construct like
1494 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1495 This solution attempts to prevent this situation from occurring. When
1496 we see something like the above, we spill the inner register to memory. */
1499 spill_xfmode_rfmode_operand (rtx in
, int force
, enum machine_mode mode
)
1501 if (GET_CODE (in
) == SUBREG
1502 && GET_MODE (SUBREG_REG (in
)) == TImode
1503 && GET_CODE (SUBREG_REG (in
)) == REG
)
1505 rtx memt
= assign_stack_temp (TImode
, 16, 0);
1506 emit_move_insn (memt
, SUBREG_REG (in
));
1507 return adjust_address (memt
, mode
, 0);
1509 else if (force
&& GET_CODE (in
) == REG
)
1511 rtx memx
= assign_stack_temp (mode
, 16, 0);
1512 emit_move_insn (memx
, in
);
1519 /* Expand the movxf or movrf pattern (MODE says which) with the given
1520 OPERANDS, returning true if the pattern should then invoke
1524 ia64_expand_movxf_movrf (enum machine_mode mode
, rtx operands
[])
1526 rtx op0
= operands
[0];
1528 if (GET_CODE (op0
) == SUBREG
)
1529 op0
= SUBREG_REG (op0
);
1531 /* We must support XFmode loads into general registers for stdarg/vararg,
1532 unprototyped calls, and a rare case where a long double is passed as
1533 an argument after a float HFA fills the FP registers. We split them into
1534 DImode loads for convenience. We also need to support XFmode stores
1535 for the last case. This case does not happen for stdarg/vararg routines,
1536 because we do a block store to memory of unnamed arguments. */
1538 if (GET_CODE (op0
) == REG
&& GR_REGNO_P (REGNO (op0
)))
1542 /* We're hoping to transform everything that deals with XFmode
1543 quantities and GR registers early in the compiler. */
1544 gcc_assert (can_create_pseudo_p ());
1546 /* Struct to register can just use TImode instead. */
1547 if ((GET_CODE (operands
[1]) == SUBREG
1548 && GET_MODE (SUBREG_REG (operands
[1])) == TImode
)
1549 || (GET_CODE (operands
[1]) == REG
1550 && GR_REGNO_P (REGNO (operands
[1]))))
1552 rtx op1
= operands
[1];
1554 if (GET_CODE (op1
) == SUBREG
)
1555 op1
= SUBREG_REG (op1
);
1557 op1
= gen_rtx_REG (TImode
, REGNO (op1
));
1559 emit_move_insn (gen_rtx_REG (TImode
, REGNO (op0
)), op1
);
1563 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1565 /* Don't word-swap when reading in the constant. */
1566 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
)),
1567 operand_subword (operands
[1], WORDS_BIG_ENDIAN
,
1569 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
) + 1),
1570 operand_subword (operands
[1], !WORDS_BIG_ENDIAN
,
1575 /* If the quantity is in a register not known to be GR, spill it. */
1576 if (register_operand (operands
[1], mode
))
1577 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 1, mode
);
1579 gcc_assert (GET_CODE (operands
[1]) == MEM
);
1581 /* Don't word-swap when reading in the value. */
1582 out
[0] = gen_rtx_REG (DImode
, REGNO (op0
));
1583 out
[1] = gen_rtx_REG (DImode
, REGNO (op0
) + 1);
1585 emit_move_insn (out
[0], adjust_address (operands
[1], DImode
, 0));
1586 emit_move_insn (out
[1], adjust_address (operands
[1], DImode
, 8));
1590 if (GET_CODE (operands
[1]) == REG
&& GR_REGNO_P (REGNO (operands
[1])))
1592 /* We're hoping to transform everything that deals with XFmode
1593 quantities and GR registers early in the compiler. */
1594 gcc_assert (can_create_pseudo_p ());
1596 /* Op0 can't be a GR_REG here, as that case is handled above.
1597 If op0 is a register, then we spill op1, so that we now have a
1598 MEM operand. This requires creating an XFmode subreg of a TImode reg
1599 to force the spill. */
1600 if (register_operand (operands
[0], mode
))
1602 rtx op1
= gen_rtx_REG (TImode
, REGNO (operands
[1]));
1603 op1
= gen_rtx_SUBREG (mode
, op1
, 0);
1604 operands
[1] = spill_xfmode_rfmode_operand (op1
, 0, mode
);
1611 gcc_assert (GET_CODE (operands
[0]) == MEM
);
1613 /* Don't word-swap when writing out the value. */
1614 in
[0] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
1615 in
[1] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
1617 emit_move_insn (adjust_address (operands
[0], DImode
, 0), in
[0]);
1618 emit_move_insn (adjust_address (operands
[0], DImode
, 8), in
[1]);
1623 if (!reload_in_progress
&& !reload_completed
)
1625 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 0, mode
);
1627 if (GET_MODE (op0
) == TImode
&& GET_CODE (op0
) == REG
)
1629 rtx memt
, memx
, in
= operands
[1];
1630 if (CONSTANT_P (in
))
1631 in
= validize_mem (force_const_mem (mode
, in
));
1632 if (GET_CODE (in
) == MEM
)
1633 memt
= adjust_address (in
, TImode
, 0);
1636 memt
= assign_stack_temp (TImode
, 16, 0);
1637 memx
= adjust_address (memt
, mode
, 0);
1638 emit_move_insn (memx
, in
);
1640 emit_move_insn (op0
, memt
);
1644 if (!ia64_move_ok (operands
[0], operands
[1]))
1645 operands
[1] = force_reg (mode
, operands
[1]);
1651 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1652 with the expression that holds the compare result (in VOIDmode). */
1654 static GTY(()) rtx cmptf_libfunc
;
1657 ia64_expand_compare (rtx
*expr
, rtx
*op0
, rtx
*op1
)
1659 enum rtx_code code
= GET_CODE (*expr
);
1662 /* If we have a BImode input, then we already have a compare result, and
1663 do not need to emit another comparison. */
1664 if (GET_MODE (*op0
) == BImode
)
1666 gcc_assert ((code
== NE
|| code
== EQ
) && *op1
== const0_rtx
);
1669 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1670 magic number as its third argument, that indicates what to do.
1671 The return value is an integer to be compared against zero. */
1672 else if (TARGET_HPUX
&& GET_MODE (*op0
) == TFmode
)
1675 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1682 enum rtx_code ncode
;
1685 gcc_assert (cmptf_libfunc
&& GET_MODE (*op1
) == TFmode
);
1688 /* 1 = equal, 0 = not equal. Equality operators do
1689 not raise FP_INVALID when given an SNaN operand. */
1690 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1691 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1692 /* isunordered() from C99. */
1693 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1694 case ORDERED
: magic
= QCMP_UNORD
; ncode
= EQ
; break;
1695 /* Relational operators raise FP_INVALID when given
1697 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1698 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1699 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1700 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1701 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1702 Expanders for buneq etc. weuld have to be added to ia64.md
1703 for this to be useful. */
1704 default: gcc_unreachable ();
1709 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1710 *op0
, TFmode
, *op1
, TFmode
,
1711 GEN_INT (magic
), DImode
);
1712 cmp
= gen_reg_rtx (BImode
);
1713 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1714 gen_rtx_fmt_ee (ncode
, BImode
,
1717 insns
= get_insns ();
1720 emit_libcall_block (insns
, cmp
, cmp
,
1721 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
));
1726 cmp
= gen_reg_rtx (BImode
);
1727 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1728 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
)));
1732 *expr
= gen_rtx_fmt_ee (code
, VOIDmode
, cmp
, const0_rtx
);
1737 /* Generate an integral vector comparison. Return true if the condition has
1738 been reversed, and so the sense of the comparison should be inverted. */
1741 ia64_expand_vecint_compare (enum rtx_code code
, enum machine_mode mode
,
1742 rtx dest
, rtx op0
, rtx op1
)
1744 bool negate
= false;
1747 /* Canonicalize the comparison to EQ, GT, GTU. */
1758 code
= reverse_condition (code
);
1764 code
= reverse_condition (code
);
1770 code
= swap_condition (code
);
1771 x
= op0
, op0
= op1
, op1
= x
;
1778 /* Unsigned parallel compare is not supported by the hardware. Play some
1779 tricks to turn this into a signed comparison against 0. */
1788 /* Subtract (-(INT MAX) - 1) from both operands to make
1790 mask
= GEN_INT (0x80000000);
1791 mask
= gen_rtx_CONST_VECTOR (V2SImode
, gen_rtvec (2, mask
, mask
));
1792 mask
= force_reg (mode
, mask
);
1793 t1
= gen_reg_rtx (mode
);
1794 emit_insn (gen_subv2si3 (t1
, op0
, mask
));
1795 t2
= gen_reg_rtx (mode
);
1796 emit_insn (gen_subv2si3 (t2
, op1
, mask
));
1805 /* Perform a parallel unsigned saturating subtraction. */
1806 x
= gen_reg_rtx (mode
);
1807 emit_insn (gen_rtx_SET (VOIDmode
, x
,
1808 gen_rtx_US_MINUS (mode
, op0
, op1
)));
1812 op1
= CONST0_RTX (mode
);
1821 x
= gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
1822 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1827 /* Emit an integral vector conditional move. */
1830 ia64_expand_vecint_cmov (rtx operands
[])
1832 enum machine_mode mode
= GET_MODE (operands
[0]);
1833 enum rtx_code code
= GET_CODE (operands
[3]);
1837 cmp
= gen_reg_rtx (mode
);
1838 negate
= ia64_expand_vecint_compare (code
, mode
, cmp
,
1839 operands
[4], operands
[5]);
1841 ot
= operands
[1+negate
];
1842 of
= operands
[2-negate
];
1844 if (ot
== CONST0_RTX (mode
))
1846 if (of
== CONST0_RTX (mode
))
1848 emit_move_insn (operands
[0], ot
);
1852 x
= gen_rtx_NOT (mode
, cmp
);
1853 x
= gen_rtx_AND (mode
, x
, of
);
1854 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1856 else if (of
== CONST0_RTX (mode
))
1858 x
= gen_rtx_AND (mode
, cmp
, ot
);
1859 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1865 t
= gen_reg_rtx (mode
);
1866 x
= gen_rtx_AND (mode
, cmp
, operands
[1+negate
]);
1867 emit_insn (gen_rtx_SET (VOIDmode
, t
, x
));
1869 f
= gen_reg_rtx (mode
);
1870 x
= gen_rtx_NOT (mode
, cmp
);
1871 x
= gen_rtx_AND (mode
, x
, operands
[2-negate
]);
1872 emit_insn (gen_rtx_SET (VOIDmode
, f
, x
));
1874 x
= gen_rtx_IOR (mode
, t
, f
);
1875 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1879 /* Emit an integral vector min or max operation. Return true if all done. */
1882 ia64_expand_vecint_minmax (enum rtx_code code
, enum machine_mode mode
,
1887 /* These four combinations are supported directly. */
1888 if (mode
== V8QImode
&& (code
== UMIN
|| code
== UMAX
))
1890 if (mode
== V4HImode
&& (code
== SMIN
|| code
== SMAX
))
1893 /* This combination can be implemented with only saturating subtraction. */
1894 if (mode
== V4HImode
&& code
== UMAX
)
1896 rtx x
, tmp
= gen_reg_rtx (mode
);
1898 x
= gen_rtx_US_MINUS (mode
, operands
[1], operands
[2]);
1899 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, x
));
1901 emit_insn (gen_addv4hi3 (operands
[0], tmp
, operands
[2]));
1905 /* Everything else implemented via vector comparisons. */
1906 xops
[0] = operands
[0];
1907 xops
[4] = xops
[1] = operands
[1];
1908 xops
[5] = xops
[2] = operands
[2];
1927 xops
[3] = gen_rtx_fmt_ee (code
, VOIDmode
, operands
[1], operands
[2]);
1929 ia64_expand_vecint_cmov (xops
);
1933 /* Emit an integral vector widening sum operations. */
1936 ia64_expand_widen_sum (rtx operands
[3], bool unsignedp
)
1939 enum machine_mode wmode
, mode
;
1940 rtx (*unpack_l
) (rtx
, rtx
, rtx
);
1941 rtx (*unpack_h
) (rtx
, rtx
, rtx
);
1942 rtx (*plus
) (rtx
, rtx
, rtx
);
1944 wmode
= GET_MODE (operands
[0]);
1945 mode
= GET_MODE (operands
[1]);
1950 unpack_l
= gen_unpack1_l
;
1951 unpack_h
= gen_unpack1_h
;
1952 plus
= gen_addv4hi3
;
1955 unpack_l
= gen_unpack2_l
;
1956 unpack_h
= gen_unpack2_h
;
1957 plus
= gen_addv2si3
;
1963 /* Fill in x with the sign extension of each element in op1. */
1965 x
= CONST0_RTX (mode
);
1970 x
= gen_reg_rtx (mode
);
1972 neg
= ia64_expand_vecint_compare (LT
, mode
, x
, operands
[1],
1977 l
= gen_reg_rtx (wmode
);
1978 h
= gen_reg_rtx (wmode
);
1979 s
= gen_reg_rtx (wmode
);
1981 emit_insn (unpack_l (gen_lowpart (mode
, l
), operands
[1], x
));
1982 emit_insn (unpack_h (gen_lowpart (mode
, h
), operands
[1], x
));
1983 emit_insn (plus (s
, l
, operands
[2]));
1984 emit_insn (plus (operands
[0], h
, s
));
1987 /* Emit a signed or unsigned V8QI dot product operation. */
1990 ia64_expand_dot_prod_v8qi (rtx operands
[4], bool unsignedp
)
1992 rtx l1
, l2
, h1
, h2
, x1
, x2
, p1
, p2
, p3
, p4
, s1
, s2
, s3
;
1994 /* Fill in x1 and x2 with the sign extension of each element. */
1996 x1
= x2
= CONST0_RTX (V8QImode
);
2001 x1
= gen_reg_rtx (V8QImode
);
2002 x2
= gen_reg_rtx (V8QImode
);
2004 neg
= ia64_expand_vecint_compare (LT
, V8QImode
, x1
, operands
[1],
2005 CONST0_RTX (V8QImode
));
2007 neg
= ia64_expand_vecint_compare (LT
, V8QImode
, x2
, operands
[2],
2008 CONST0_RTX (V8QImode
));
2012 l1
= gen_reg_rtx (V4HImode
);
2013 l2
= gen_reg_rtx (V4HImode
);
2014 h1
= gen_reg_rtx (V4HImode
);
2015 h2
= gen_reg_rtx (V4HImode
);
2017 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode
, l1
), operands
[1], x1
));
2018 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode
, l2
), operands
[2], x2
));
2019 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode
, h1
), operands
[1], x1
));
2020 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode
, h2
), operands
[2], x2
));
2022 p1
= gen_reg_rtx (V2SImode
);
2023 p2
= gen_reg_rtx (V2SImode
);
2024 p3
= gen_reg_rtx (V2SImode
);
2025 p4
= gen_reg_rtx (V2SImode
);
2026 emit_insn (gen_pmpy2_r (p1
, l1
, l2
));
2027 emit_insn (gen_pmpy2_l (p2
, l1
, l2
));
2028 emit_insn (gen_pmpy2_r (p3
, h1
, h2
));
2029 emit_insn (gen_pmpy2_l (p4
, h1
, h2
));
2031 s1
= gen_reg_rtx (V2SImode
);
2032 s2
= gen_reg_rtx (V2SImode
);
2033 s3
= gen_reg_rtx (V2SImode
);
2034 emit_insn (gen_addv2si3 (s1
, p1
, p2
));
2035 emit_insn (gen_addv2si3 (s2
, p3
, p4
));
2036 emit_insn (gen_addv2si3 (s3
, s1
, operands
[3]));
2037 emit_insn (gen_addv2si3 (operands
[0], s2
, s3
));
2040 /* Emit the appropriate sequence for a call. */
2043 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
2048 addr
= XEXP (addr
, 0);
2049 addr
= convert_memory_address (DImode
, addr
);
2050 b0
= gen_rtx_REG (DImode
, R_BR (0));
2052 /* ??? Should do this for functions known to bind local too. */
2053 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
2056 insn
= gen_sibcall_nogp (addr
);
2058 insn
= gen_call_nogp (addr
, b0
);
2060 insn
= gen_call_value_nogp (retval
, addr
, b0
);
2061 insn
= emit_call_insn (insn
);
2066 insn
= gen_sibcall_gp (addr
);
2068 insn
= gen_call_gp (addr
, b0
);
2070 insn
= gen_call_value_gp (retval
, addr
, b0
);
2071 insn
= emit_call_insn (insn
);
2073 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2077 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
2079 if (TARGET_ABI_OPEN_VMS
)
2080 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2081 gen_rtx_REG (DImode
, GR_REG (25)));
2085 reg_emitted (enum ia64_frame_regs r
)
2087 if (emitted_frame_related_regs
[r
] == 0)
2088 emitted_frame_related_regs
[r
] = current_frame_info
.r
[r
];
2090 gcc_assert (emitted_frame_related_regs
[r
] == current_frame_info
.r
[r
]);
2094 get_reg (enum ia64_frame_regs r
)
2097 return current_frame_info
.r
[r
];
2101 is_emitted (int regno
)
2105 for (r
= reg_fp
; r
< number_of_ia64_frame_regs
; r
++)
2106 if (emitted_frame_related_regs
[r
] == regno
)
2112 ia64_reload_gp (void)
2116 if (current_frame_info
.r
[reg_save_gp
])
2118 tmp
= gen_rtx_REG (DImode
, get_reg (reg_save_gp
));
2122 HOST_WIDE_INT offset
;
2125 offset
= (current_frame_info
.spill_cfa_off
2126 + current_frame_info
.spill_size
);
2127 if (frame_pointer_needed
)
2129 tmp
= hard_frame_pointer_rtx
;
2134 tmp
= stack_pointer_rtx
;
2135 offset
= current_frame_info
.total_size
- offset
;
2138 offset_r
= GEN_INT (offset
);
2139 if (satisfies_constraint_I (offset_r
))
2140 emit_insn (gen_adddi3 (pic_offset_table_rtx
, tmp
, offset_r
));
2143 emit_move_insn (pic_offset_table_rtx
, offset_r
);
2144 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
2145 pic_offset_table_rtx
, tmp
));
2148 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
2151 emit_move_insn (pic_offset_table_rtx
, tmp
);
2155 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
2156 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
2159 bool is_desc
= false;
2161 /* If we find we're calling through a register, then we're actually
2162 calling through a descriptor, so load up the values. */
2163 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
2168 /* ??? We are currently constrained to *not* use peep2, because
2169 we can legitimately change the global lifetime of the GP
2170 (in the form of killing where previously live). This is
2171 because a call through a descriptor doesn't use the previous
2172 value of the GP, while a direct call does, and we do not
2173 commit to either form until the split here.
2175 That said, this means that we lack precise life info for
2176 whether ADDR is dead after this call. This is not terribly
2177 important, since we can fix things up essentially for free
2178 with the POST_DEC below, but it's nice to not use it when we
2179 can immediately tell it's not necessary. */
2180 addr_dead_p
= ((noreturn_p
|| sibcall_p
2181 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
2183 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
2185 /* Load the code address into scratch_b. */
2186 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
2187 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2188 emit_move_insn (scratch_r
, tmp
);
2189 emit_move_insn (scratch_b
, scratch_r
);
2191 /* Load the GP address. If ADDR is not dead here, then we must
2192 revert the change made above via the POST_INCREMENT. */
2194 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
2197 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2198 emit_move_insn (pic_offset_table_rtx
, tmp
);
2205 insn
= gen_sibcall_nogp (addr
);
2207 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
2209 insn
= gen_call_nogp (addr
, retaddr
);
2210 emit_call_insn (insn
);
2212 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
2216 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2218 This differs from the generic code in that we know about the zero-extending
2219 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2220 also know that ld.acq+cmpxchg.rel equals a full barrier.
2222 The loop we want to generate looks like
2227 new_reg = cmp_reg op val;
2228 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2229 if (cmp_reg != old_reg)
2232 Note that we only do the plain load from memory once. Subsequent
2233 iterations use the value loaded by the compare-and-swap pattern. */
2236 ia64_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
2237 rtx old_dst
, rtx new_dst
)
2239 enum machine_mode mode
= GET_MODE (mem
);
2240 rtx old_reg
, new_reg
, cmp_reg
, ar_ccv
, label
;
2241 enum insn_code icode
;
2243 /* Special case for using fetchadd. */
2244 if ((mode
== SImode
|| mode
== DImode
)
2245 && (code
== PLUS
|| code
== MINUS
)
2246 && fetchadd_operand (val
, mode
))
2249 val
= GEN_INT (-INTVAL (val
));
2252 old_dst
= gen_reg_rtx (mode
);
2254 emit_insn (gen_memory_barrier ());
2257 icode
= CODE_FOR_fetchadd_acq_si
;
2259 icode
= CODE_FOR_fetchadd_acq_di
;
2260 emit_insn (GEN_FCN (icode
) (old_dst
, mem
, val
));
2264 new_reg
= expand_simple_binop (mode
, PLUS
, old_dst
, val
, new_dst
,
2266 if (new_reg
!= new_dst
)
2267 emit_move_insn (new_dst
, new_reg
);
2272 /* Because of the volatile mem read, we get an ld.acq, which is the
2273 front half of the full barrier. The end half is the cmpxchg.rel. */
2274 gcc_assert (MEM_VOLATILE_P (mem
));
2276 old_reg
= gen_reg_rtx (DImode
);
2277 cmp_reg
= gen_reg_rtx (DImode
);
2278 label
= gen_label_rtx ();
2282 val
= simplify_gen_subreg (DImode
, val
, mode
, 0);
2283 emit_insn (gen_extend_insn (cmp_reg
, mem
, DImode
, mode
, 1));
2286 emit_move_insn (cmp_reg
, mem
);
2290 ar_ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
2291 emit_move_insn (old_reg
, cmp_reg
);
2292 emit_move_insn (ar_ccv
, cmp_reg
);
2295 emit_move_insn (old_dst
, gen_lowpart (mode
, cmp_reg
));
2300 new_reg
= expand_simple_binop (DImode
, AND
, new_reg
, val
, NULL_RTX
,
2301 true, OPTAB_DIRECT
);
2302 new_reg
= expand_simple_unop (DImode
, code
, new_reg
, NULL_RTX
, true);
2305 new_reg
= expand_simple_binop (DImode
, code
, new_reg
, val
, NULL_RTX
,
2306 true, OPTAB_DIRECT
);
2309 new_reg
= gen_lowpart (mode
, new_reg
);
2311 emit_move_insn (new_dst
, new_reg
);
2315 case QImode
: icode
= CODE_FOR_cmpxchg_rel_qi
; break;
2316 case HImode
: icode
= CODE_FOR_cmpxchg_rel_hi
; break;
2317 case SImode
: icode
= CODE_FOR_cmpxchg_rel_si
; break;
2318 case DImode
: icode
= CODE_FOR_cmpxchg_rel_di
; break;
2323 emit_insn (GEN_FCN (icode
) (cmp_reg
, mem
, ar_ccv
, new_reg
));
2325 emit_cmp_and_jump_insns (cmp_reg
, old_reg
, NE
, NULL
, DImode
, true, label
);
2328 /* Begin the assembly file. */
2331 ia64_file_start (void)
2333 /* Variable tracking should be run after all optimizations which change order
2334 of insns. It also needs a valid CFG. This can't be done in
2335 ia64_option_override, because flag_var_tracking is finalized after
2337 ia64_flag_var_tracking
= flag_var_tracking
;
2338 flag_var_tracking
= 0;
2340 default_file_start ();
2341 emit_safe_across_calls ();
2345 emit_safe_across_calls (void)
2347 unsigned int rs
, re
;
2354 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
2358 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
2362 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
2366 fputc (',', asm_out_file
);
2368 fprintf (asm_out_file
, "p%u", rs
);
2370 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
2374 fputc ('\n', asm_out_file
);
2377 /* Globalize a declaration. */
2380 ia64_globalize_decl_name (FILE * stream
, tree decl
)
2382 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2383 tree version_attr
= lookup_attribute ("version_id", DECL_ATTRIBUTES (decl
));
2386 tree v
= TREE_VALUE (TREE_VALUE (version_attr
));
2387 const char *p
= TREE_STRING_POINTER (v
);
2388 fprintf (stream
, "\t.alias %s#, \"%s{%s}\"\n", name
, name
, p
);
2390 targetm
.asm_out
.globalize_label (stream
, name
);
2391 if (TREE_CODE (decl
) == FUNCTION_DECL
)
2392 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "function");
2395 /* Helper function for ia64_compute_frame_size: find an appropriate general
2396 register to spill some special register to. SPECIAL_SPILL_MASK contains
2397 bits in GR0 to GR31 that have already been allocated by this routine.
2398 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2401 find_gr_spill (enum ia64_frame_regs r
, int try_locals
)
2405 if (emitted_frame_related_regs
[r
] != 0)
2407 regno
= emitted_frame_related_regs
[r
];
2408 if (regno
>= LOC_REG (0) && regno
< LOC_REG (80 - frame_pointer_needed
)
2409 && current_frame_info
.n_local_regs
< regno
- LOC_REG (0) + 1)
2410 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2411 else if (current_function_is_leaf
2412 && regno
>= GR_REG (1) && regno
<= GR_REG (31))
2413 current_frame_info
.gr_used_mask
|= 1 << regno
;
2418 /* If this is a leaf function, first try an otherwise unused
2419 call-clobbered register. */
2420 if (current_function_is_leaf
)
2422 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2423 if (! df_regs_ever_live_p (regno
)
2424 && call_used_regs
[regno
]
2425 && ! fixed_regs
[regno
]
2426 && ! global_regs
[regno
]
2427 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0
2428 && ! is_emitted (regno
))
2430 current_frame_info
.gr_used_mask
|= 1 << regno
;
2437 regno
= current_frame_info
.n_local_regs
;
2438 /* If there is a frame pointer, then we can't use loc79, because
2439 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2440 reg_name switching code in ia64_expand_prologue. */
2441 while (regno
< (80 - frame_pointer_needed
))
2442 if (! is_emitted (LOC_REG (regno
++)))
2444 current_frame_info
.n_local_regs
= regno
;
2445 return LOC_REG (regno
- 1);
2449 /* Failed to find a general register to spill to. Must use stack. */
2453 /* In order to make for nice schedules, we try to allocate every temporary
2454 to a different register. We must of course stay away from call-saved,
2455 fixed, and global registers. We must also stay away from registers
2456 allocated in current_frame_info.gr_used_mask, since those include regs
2457 used all through the prologue.
2459 Any register allocated here must be used immediately. The idea is to
2460 aid scheduling, not to solve data flow problems. */
2462 static int last_scratch_gr_reg
;
2465 next_scratch_gr_reg (void)
2469 for (i
= 0; i
< 32; ++i
)
2471 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
2472 if (call_used_regs
[regno
]
2473 && ! fixed_regs
[regno
]
2474 && ! global_regs
[regno
]
2475 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
2477 last_scratch_gr_reg
= regno
;
2482 /* There must be _something_ available. */
2486 /* Helper function for ia64_compute_frame_size, called through
2487 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2490 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2492 unsigned int regno
= REGNO (reg
);
2495 unsigned int i
, n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2496 for (i
= 0; i
< n
; ++i
)
2497 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2502 /* Returns the number of bytes offset between the frame pointer and the stack
2503 pointer for the current function. SIZE is the number of bytes of space
2504 needed for local variables. */
2507 ia64_compute_frame_size (HOST_WIDE_INT size
)
2509 HOST_WIDE_INT total_size
;
2510 HOST_WIDE_INT spill_size
= 0;
2511 HOST_WIDE_INT extra_spill_size
= 0;
2512 HOST_WIDE_INT pretend_args_size
;
2515 int spilled_gr_p
= 0;
2516 int spilled_fr_p
= 0;
2522 if (current_frame_info
.initialized
)
2525 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2526 CLEAR_HARD_REG_SET (mask
);
2528 /* Don't allocate scratches to the return register. */
2529 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2531 /* Don't allocate scratches to the EH scratch registers. */
2532 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2533 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2534 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2535 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2537 /* Find the size of the register stack frame. We have only 80 local
2538 registers, because we reserve 8 for the inputs and 8 for the
2541 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2542 since we'll be adjusting that down later. */
2543 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2544 for (; regno
>= LOC_REG (0); regno
--)
2545 if (df_regs_ever_live_p (regno
) && !is_emitted (regno
))
2547 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2549 /* For functions marked with the syscall_linkage attribute, we must mark
2550 all eight input registers as in use, so that locals aren't visible to
2553 if (cfun
->machine
->n_varargs
> 0
2554 || lookup_attribute ("syscall_linkage",
2555 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2556 current_frame_info
.n_input_regs
= 8;
2559 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2560 if (df_regs_ever_live_p (regno
))
2562 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2565 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2566 if (df_regs_ever_live_p (regno
))
2568 i
= regno
- OUT_REG (0) + 1;
2570 #ifndef PROFILE_HOOK
2571 /* When -p profiling, we need one output register for the mcount argument.
2572 Likewise for -a profiling for the bb_init_func argument. For -ax
2573 profiling, we need two output registers for the two bb_init_trace_func
2578 current_frame_info
.n_output_regs
= i
;
2580 /* ??? No rotating register support yet. */
2581 current_frame_info
.n_rotate_regs
= 0;
2583 /* Discover which registers need spilling, and how much room that
2584 will take. Begin with floating point and general registers,
2585 which will always wind up on the stack. */
2587 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2588 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2590 SET_HARD_REG_BIT (mask
, regno
);
2596 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2597 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2599 SET_HARD_REG_BIT (mask
, regno
);
2605 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2606 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2608 SET_HARD_REG_BIT (mask
, regno
);
2613 /* Now come all special registers that might get saved in other
2614 general registers. */
2616 if (frame_pointer_needed
)
2618 current_frame_info
.r
[reg_fp
] = find_gr_spill (reg_fp
, 1);
2619 /* If we did not get a register, then we take LOC79. This is guaranteed
2620 to be free, even if regs_ever_live is already set, because this is
2621 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2622 as we don't count loc79 above. */
2623 if (current_frame_info
.r
[reg_fp
] == 0)
2625 current_frame_info
.r
[reg_fp
] = LOC_REG (79);
2626 current_frame_info
.n_local_regs
= LOC_REG (79) - LOC_REG (0) + 1;
2630 if (! current_function_is_leaf
)
2632 /* Emit a save of BR0 if we call other functions. Do this even
2633 if this function doesn't return, as EH depends on this to be
2634 able to unwind the stack. */
2635 SET_HARD_REG_BIT (mask
, BR_REG (0));
2637 current_frame_info
.r
[reg_save_b0
] = find_gr_spill (reg_save_b0
, 1);
2638 if (current_frame_info
.r
[reg_save_b0
] == 0)
2640 extra_spill_size
+= 8;
2644 /* Similarly for ar.pfs. */
2645 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2646 current_frame_info
.r
[reg_save_ar_pfs
] = find_gr_spill (reg_save_ar_pfs
, 1);
2647 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2649 extra_spill_size
+= 8;
2653 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2654 registers are clobbered, so we fall back to the stack. */
2655 current_frame_info
.r
[reg_save_gp
]
2656 = (cfun
->calls_setjmp
? 0 : find_gr_spill (reg_save_gp
, 1));
2657 if (current_frame_info
.r
[reg_save_gp
] == 0)
2659 SET_HARD_REG_BIT (mask
, GR_REG (1));
2666 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs
[BR_REG (0)])
2668 SET_HARD_REG_BIT (mask
, BR_REG (0));
2669 extra_spill_size
+= 8;
2673 if (df_regs_ever_live_p (AR_PFS_REGNUM
))
2675 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2676 current_frame_info
.r
[reg_save_ar_pfs
]
2677 = find_gr_spill (reg_save_ar_pfs
, 1);
2678 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2680 extra_spill_size
+= 8;
2686 /* Unwind descriptor hackery: things are most efficient if we allocate
2687 consecutive GR save registers for RP, PFS, FP in that order. However,
2688 it is absolutely critical that FP get the only hard register that's
2689 guaranteed to be free, so we allocated it first. If all three did
2690 happen to be allocated hard regs, and are consecutive, rearrange them
2691 into the preferred order now.
2693 If we have already emitted code for any of those registers,
2694 then it's already too late to change. */
2695 min_regno
= MIN (current_frame_info
.r
[reg_fp
],
2696 MIN (current_frame_info
.r
[reg_save_b0
],
2697 current_frame_info
.r
[reg_save_ar_pfs
]));
2698 max_regno
= MAX (current_frame_info
.r
[reg_fp
],
2699 MAX (current_frame_info
.r
[reg_save_b0
],
2700 current_frame_info
.r
[reg_save_ar_pfs
]));
2702 && min_regno
+ 2 == max_regno
2703 && (current_frame_info
.r
[reg_fp
] == min_regno
+ 1
2704 || current_frame_info
.r
[reg_save_b0
] == min_regno
+ 1
2705 || current_frame_info
.r
[reg_save_ar_pfs
] == min_regno
+ 1)
2706 && (emitted_frame_related_regs
[reg_save_b0
] == 0
2707 || emitted_frame_related_regs
[reg_save_b0
] == min_regno
)
2708 && (emitted_frame_related_regs
[reg_save_ar_pfs
] == 0
2709 || emitted_frame_related_regs
[reg_save_ar_pfs
] == min_regno
+ 1)
2710 && (emitted_frame_related_regs
[reg_fp
] == 0
2711 || emitted_frame_related_regs
[reg_fp
] == min_regno
+ 2))
2713 current_frame_info
.r
[reg_save_b0
] = min_regno
;
2714 current_frame_info
.r
[reg_save_ar_pfs
] = min_regno
+ 1;
2715 current_frame_info
.r
[reg_fp
] = min_regno
+ 2;
2718 /* See if we need to store the predicate register block. */
2719 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2720 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2722 if (regno
<= PR_REG (63))
2724 SET_HARD_REG_BIT (mask
, PR_REG (0));
2725 current_frame_info
.r
[reg_save_pr
] = find_gr_spill (reg_save_pr
, 1);
2726 if (current_frame_info
.r
[reg_save_pr
] == 0)
2728 extra_spill_size
+= 8;
2732 /* ??? Mark them all as used so that register renaming and such
2733 are free to use them. */
2734 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2735 df_set_regs_ever_live (regno
, true);
2738 /* If we're forced to use st8.spill, we're forced to save and restore
2739 ar.unat as well. The check for existing liveness allows inline asm
2740 to touch ar.unat. */
2741 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2742 || df_regs_ever_live_p (AR_UNAT_REGNUM
))
2744 df_set_regs_ever_live (AR_UNAT_REGNUM
, true);
2745 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2746 current_frame_info
.r
[reg_save_ar_unat
]
2747 = find_gr_spill (reg_save_ar_unat
, spill_size
== 0);
2748 if (current_frame_info
.r
[reg_save_ar_unat
] == 0)
2750 extra_spill_size
+= 8;
2755 if (df_regs_ever_live_p (AR_LC_REGNUM
))
2757 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2758 current_frame_info
.r
[reg_save_ar_lc
]
2759 = find_gr_spill (reg_save_ar_lc
, spill_size
== 0);
2760 if (current_frame_info
.r
[reg_save_ar_lc
] == 0)
2762 extra_spill_size
+= 8;
2767 /* If we have an odd number of words of pretend arguments written to
2768 the stack, then the FR save area will be unaligned. We round the
2769 size of this area up to keep things 16 byte aligned. */
2771 pretend_args_size
= IA64_STACK_ALIGN (crtl
->args
.pretend_args_size
);
2773 pretend_args_size
= crtl
->args
.pretend_args_size
;
2775 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2776 + crtl
->outgoing_args_size
);
2777 total_size
= IA64_STACK_ALIGN (total_size
);
2779 /* We always use the 16-byte scratch area provided by the caller, but
2780 if we are a leaf function, there's no one to which we need to provide
2782 if (current_function_is_leaf
)
2783 total_size
= MAX (0, total_size
- 16);
2785 current_frame_info
.total_size
= total_size
;
2786 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2787 current_frame_info
.spill_size
= spill_size
;
2788 current_frame_info
.extra_spill_size
= extra_spill_size
;
2789 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2790 current_frame_info
.n_spilled
= n_spilled
;
2791 current_frame_info
.initialized
= reload_completed
;
2794 /* Worker function for TARGET_CAN_ELIMINATE. */
2797 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2799 return (to
== BR_REG (0) ? current_function_is_leaf
: true);
2802 /* Compute the initial difference between the specified pair of registers. */
2805 ia64_initial_elimination_offset (int from
, int to
)
2807 HOST_WIDE_INT offset
;
2809 ia64_compute_frame_size (get_frame_size ());
2812 case FRAME_POINTER_REGNUM
:
2815 case HARD_FRAME_POINTER_REGNUM
:
2816 if (current_function_is_leaf
)
2817 offset
= -current_frame_info
.total_size
;
2819 offset
= -(current_frame_info
.total_size
2820 - crtl
->outgoing_args_size
- 16);
2823 case STACK_POINTER_REGNUM
:
2824 if (current_function_is_leaf
)
2827 offset
= 16 + crtl
->outgoing_args_size
;
2835 case ARG_POINTER_REGNUM
:
2836 /* Arguments start above the 16 byte save area, unless stdarg
2837 in which case we store through the 16 byte save area. */
2840 case HARD_FRAME_POINTER_REGNUM
:
2841 offset
= 16 - crtl
->args
.pretend_args_size
;
2844 case STACK_POINTER_REGNUM
:
2845 offset
= (current_frame_info
.total_size
2846 + 16 - crtl
->args
.pretend_args_size
);
2861 /* If there are more than a trivial number of register spills, we use
2862 two interleaved iterators so that we can get two memory references
2865 In order to simplify things in the prologue and epilogue expanders,
2866 we use helper functions to fix up the memory references after the
2867 fact with the appropriate offsets to a POST_MODIFY memory mode.
2868 The following data structure tracks the state of the two iterators
2869 while insns are being emitted. */
2871 struct spill_fill_data
2873 rtx init_after
; /* point at which to emit initializations */
2874 rtx init_reg
[2]; /* initial base register */
2875 rtx iter_reg
[2]; /* the iterator registers */
2876 rtx
*prev_addr
[2]; /* address of last memory use */
2877 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2878 HOST_WIDE_INT prev_off
[2]; /* last offset */
2879 int n_iter
; /* number of iterators in use */
2880 int next_iter
; /* next iterator to use */
2881 unsigned int save_gr_used_mask
;
2884 static struct spill_fill_data spill_fill_data
;
2887 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2891 spill_fill_data
.init_after
= get_last_insn ();
2892 spill_fill_data
.init_reg
[0] = init_reg
;
2893 spill_fill_data
.init_reg
[1] = init_reg
;
2894 spill_fill_data
.prev_addr
[0] = NULL
;
2895 spill_fill_data
.prev_addr
[1] = NULL
;
2896 spill_fill_data
.prev_insn
[0] = NULL
;
2897 spill_fill_data
.prev_insn
[1] = NULL
;
2898 spill_fill_data
.prev_off
[0] = cfa_off
;
2899 spill_fill_data
.prev_off
[1] = cfa_off
;
2900 spill_fill_data
.next_iter
= 0;
2901 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2903 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2904 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2906 int regno
= next_scratch_gr_reg ();
2907 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2908 current_frame_info
.gr_used_mask
|= 1 << regno
;
2913 finish_spill_pointers (void)
2915 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2919 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
2921 int iter
= spill_fill_data
.next_iter
;
2922 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2923 rtx disp_rtx
= GEN_INT (disp
);
2926 if (spill_fill_data
.prev_addr
[iter
])
2928 if (satisfies_constraint_N (disp_rtx
))
2930 *spill_fill_data
.prev_addr
[iter
]
2931 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2932 gen_rtx_PLUS (DImode
,
2933 spill_fill_data
.iter_reg
[iter
],
2935 add_reg_note (spill_fill_data
.prev_insn
[iter
],
2936 REG_INC
, spill_fill_data
.iter_reg
[iter
]);
2940 /* ??? Could use register post_modify for loads. */
2941 if (!satisfies_constraint_I (disp_rtx
))
2943 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2944 emit_move_insn (tmp
, disp_rtx
);
2947 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2948 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2951 /* Micro-optimization: if we've created a frame pointer, it's at
2952 CFA 0, which may allow the real iterator to be initialized lower,
2953 slightly increasing parallelism. Also, if there are few saves
2954 it may eliminate the iterator entirely. */
2956 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2957 && frame_pointer_needed
)
2959 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2960 set_mem_alias_set (mem
, get_varargs_alias_set ());
2968 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2969 spill_fill_data
.init_reg
[iter
]);
2974 if (!satisfies_constraint_I (disp_rtx
))
2976 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2977 emit_move_insn (tmp
, disp_rtx
);
2981 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2982 spill_fill_data
.init_reg
[iter
],
2989 /* Careful for being the first insn in a sequence. */
2990 if (spill_fill_data
.init_after
)
2991 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2994 rtx first
= get_insns ();
2996 insn
= emit_insn_before (seq
, first
);
2998 insn
= emit_insn (seq
);
3000 spill_fill_data
.init_after
= insn
;
3003 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
3005 /* ??? Not all of the spills are for varargs, but some of them are.
3006 The rest of the spills belong in an alias set of their own. But
3007 it doesn't actually hurt to include them here. */
3008 set_mem_alias_set (mem
, get_varargs_alias_set ());
3010 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
3011 spill_fill_data
.prev_off
[iter
] = cfa_off
;
3013 if (++iter
>= spill_fill_data
.n_iter
)
3015 spill_fill_data
.next_iter
= iter
;
3021 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
3024 int iter
= spill_fill_data
.next_iter
;
3027 mem
= spill_restore_mem (reg
, cfa_off
);
3028 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
3029 spill_fill_data
.prev_insn
[iter
] = insn
;
3036 RTX_FRAME_RELATED_P (insn
) = 1;
3038 /* Don't even pretend that the unwind code can intuit its way
3039 through a pair of interleaved post_modify iterators. Just
3040 provide the correct answer. */
3042 if (frame_pointer_needed
)
3044 base
= hard_frame_pointer_rtx
;
3049 base
= stack_pointer_rtx
;
3050 off
= current_frame_info
.total_size
- cfa_off
;
3053 add_reg_note (insn
, REG_CFA_OFFSET
,
3054 gen_rtx_SET (VOIDmode
,
3055 gen_rtx_MEM (GET_MODE (reg
),
3056 plus_constant (base
, off
)),
3062 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
3064 int iter
= spill_fill_data
.next_iter
;
3067 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
3068 GEN_INT (cfa_off
)));
3069 spill_fill_data
.prev_insn
[iter
] = insn
;
3072 /* Wrapper functions that discards the CONST_INT spill offset. These
3073 exist so that we can give gr_spill/gr_fill the offset they need and
3074 use a consistent function interface. */
3077 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3079 return gen_movdi (dest
, src
);
3083 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3085 return gen_fr_spill (dest
, src
);
3089 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3091 return gen_fr_restore (dest
, src
);
3094 /* Called after register allocation to add any instructions needed for the
3095 prologue. Using a prologue insn is favored compared to putting all of the
3096 instructions in output_function_prologue(), since it allows the scheduler
3097 to intermix instructions with the saves of the caller saved registers. In
3098 some cases, it might be necessary to emit a barrier instruction as the last
3099 insn to prevent such scheduling.
3101 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3102 so that the debug info generation code can handle them properly.
3104 The register save area is layed out like so:
3106 [ varargs spill area ]
3107 [ fr register spill area ]
3108 [ br register spill area ]
3109 [ ar register spill area ]
3110 [ pr register spill area ]
3111 [ gr register spill area ] */
3113 /* ??? Get inefficient code when the frame size is larger than can fit in an
3114 adds instruction. */
3117 ia64_expand_prologue (void)
3119 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
3120 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
3123 ia64_compute_frame_size (get_frame_size ());
3124 last_scratch_gr_reg
= 15;
3126 if (flag_stack_usage
)
3127 current_function_static_stack_size
= current_frame_info
.total_size
;
3131 fprintf (dump_file
, "ia64 frame related registers "
3132 "recorded in current_frame_info.r[]:\n");
3133 #define PRINTREG(a) if (current_frame_info.r[a]) \
3134 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3136 PRINTREG(reg_save_b0
);
3137 PRINTREG(reg_save_pr
);
3138 PRINTREG(reg_save_ar_pfs
);
3139 PRINTREG(reg_save_ar_unat
);
3140 PRINTREG(reg_save_ar_lc
);
3141 PRINTREG(reg_save_gp
);
3145 /* If there is no epilogue, then we don't need some prologue insns.
3146 We need to avoid emitting the dead prologue insns, because flow
3147 will complain about them. */
3153 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
3154 if ((e
->flags
& EDGE_FAKE
) == 0
3155 && (e
->flags
& EDGE_FALLTHRU
) != 0)
3157 epilogue_p
= (e
!= NULL
);
3162 /* Set the local, input, and output register names. We need to do this
3163 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3164 half. If we use in/loc/out register names, then we get assembler errors
3165 in crtn.S because there is no alloc insn or regstk directive in there. */
3166 if (! TARGET_REG_NAMES
)
3168 int inputs
= current_frame_info
.n_input_regs
;
3169 int locals
= current_frame_info
.n_local_regs
;
3170 int outputs
= current_frame_info
.n_output_regs
;
3172 for (i
= 0; i
< inputs
; i
++)
3173 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
3174 for (i
= 0; i
< locals
; i
++)
3175 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
3176 for (i
= 0; i
< outputs
; i
++)
3177 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
3180 /* Set the frame pointer register name. The regnum is logically loc79,
3181 but of course we'll not have allocated that many locals. Rather than
3182 worrying about renumbering the existing rtxs, we adjust the name. */
3183 /* ??? This code means that we can never use one local register when
3184 there is a frame pointer. loc79 gets wasted in this case, as it is
3185 renamed to a register that will never be used. See also the try_locals
3186 code in find_gr_spill. */
3187 if (current_frame_info
.r
[reg_fp
])
3189 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3190 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3191 = reg_names
[current_frame_info
.r
[reg_fp
]];
3192 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
3195 /* We don't need an alloc instruction if we've used no outputs or locals. */
3196 if (current_frame_info
.n_local_regs
== 0
3197 && current_frame_info
.n_output_regs
== 0
3198 && current_frame_info
.n_input_regs
<= crtl
->args
.info
.int_regs
3199 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3201 /* If there is no alloc, but there are input registers used, then we
3202 need a .regstk directive. */
3203 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
3204 ar_pfs_save_reg
= NULL_RTX
;
3208 current_frame_info
.need_regstk
= 0;
3210 if (current_frame_info
.r
[reg_save_ar_pfs
])
3212 regno
= current_frame_info
.r
[reg_save_ar_pfs
];
3213 reg_emitted (reg_save_ar_pfs
);
3216 regno
= next_scratch_gr_reg ();
3217 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
3219 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
3220 GEN_INT (current_frame_info
.n_input_regs
),
3221 GEN_INT (current_frame_info
.n_local_regs
),
3222 GEN_INT (current_frame_info
.n_output_regs
),
3223 GEN_INT (current_frame_info
.n_rotate_regs
)));
3224 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.r
[reg_save_ar_pfs
] != 0);
3227 /* Set up frame pointer, stack pointer, and spill iterators. */
3229 n_varargs
= cfun
->machine
->n_varargs
;
3230 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
3231 stack_pointer_rtx
, 0);
3233 if (frame_pointer_needed
)
3235 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3236 RTX_FRAME_RELATED_P (insn
) = 1;
3238 /* Force the unwind info to recognize this as defining a new CFA,
3239 rather than some temp register setup. */
3240 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL_RTX
);
3243 if (current_frame_info
.total_size
!= 0)
3245 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
3248 if (satisfies_constraint_I (frame_size_rtx
))
3249 offset
= frame_size_rtx
;
3252 regno
= next_scratch_gr_reg ();
3253 offset
= gen_rtx_REG (DImode
, regno
);
3254 emit_move_insn (offset
, frame_size_rtx
);
3257 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
3258 stack_pointer_rtx
, offset
));
3260 if (! frame_pointer_needed
)
3262 RTX_FRAME_RELATED_P (insn
) = 1;
3263 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3264 gen_rtx_SET (VOIDmode
,
3266 gen_rtx_PLUS (DImode
,
3271 /* ??? At this point we must generate a magic insn that appears to
3272 modify the stack pointer, the frame pointer, and all spill
3273 iterators. This would allow the most scheduling freedom. For
3274 now, just hard stop. */
3275 emit_insn (gen_blockage ());
3278 /* Must copy out ar.unat before doing any integer spills. */
3279 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3281 if (current_frame_info
.r
[reg_save_ar_unat
])
3284 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3285 reg_emitted (reg_save_ar_unat
);
3289 alt_regno
= next_scratch_gr_reg ();
3290 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3291 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3294 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3295 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
3296 if (current_frame_info
.r
[reg_save_ar_unat
])
3298 RTX_FRAME_RELATED_P (insn
) = 1;
3299 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3302 /* Even if we're not going to generate an epilogue, we still
3303 need to save the register so that EH works. */
3304 if (! epilogue_p
&& current_frame_info
.r
[reg_save_ar_unat
])
3305 emit_insn (gen_prologue_use (ar_unat_save_reg
));
3308 ar_unat_save_reg
= NULL_RTX
;
3310 /* Spill all varargs registers. Do this before spilling any GR registers,
3311 since we want the UNAT bits for the GR registers to override the UNAT
3312 bits from varargs, which we don't care about. */
3315 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
3317 reg
= gen_rtx_REG (DImode
, regno
);
3318 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
3321 /* Locate the bottom of the register save area. */
3322 cfa_off
= (current_frame_info
.spill_cfa_off
3323 + current_frame_info
.spill_size
3324 + current_frame_info
.extra_spill_size
);
3326 /* Save the predicate register block either in a register or in memory. */
3327 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3329 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3330 if (current_frame_info
.r
[reg_save_pr
] != 0)
3332 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3333 reg_emitted (reg_save_pr
);
3334 insn
= emit_move_insn (alt_reg
, reg
);
3336 /* ??? Denote pr spill/fill by a DImode move that modifies all
3337 64 hard registers. */
3338 RTX_FRAME_RELATED_P (insn
) = 1;
3339 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3341 /* Even if we're not going to generate an epilogue, we still
3342 need to save the register so that EH works. */
3344 emit_insn (gen_prologue_use (alt_reg
));
3348 alt_regno
= next_scratch_gr_reg ();
3349 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3350 insn
= emit_move_insn (alt_reg
, reg
);
3351 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3356 /* Handle AR regs in numerical order. All of them get special handling. */
3357 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
3358 && current_frame_info
.r
[reg_save_ar_unat
] == 0)
3360 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3361 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
3365 /* The alloc insn already copied ar.pfs into a general register. The
3366 only thing we have to do now is copy that register to a stack slot
3367 if we'd not allocated a local register for the job. */
3368 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
3369 && current_frame_info
.r
[reg_save_ar_pfs
] == 0)
3371 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3372 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
3376 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3378 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3379 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3381 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3382 reg_emitted (reg_save_ar_lc
);
3383 insn
= emit_move_insn (alt_reg
, reg
);
3384 RTX_FRAME_RELATED_P (insn
) = 1;
3385 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3387 /* Even if we're not going to generate an epilogue, we still
3388 need to save the register so that EH works. */
3390 emit_insn (gen_prologue_use (alt_reg
));
3394 alt_regno
= next_scratch_gr_reg ();
3395 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3396 emit_move_insn (alt_reg
, reg
);
3397 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3402 /* Save the return pointer. */
3403 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3405 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3406 if (current_frame_info
.r
[reg_save_b0
] != 0)
3408 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3409 reg_emitted (reg_save_b0
);
3410 insn
= emit_move_insn (alt_reg
, reg
);
3411 RTX_FRAME_RELATED_P (insn
) = 1;
3412 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3414 /* Even if we're not going to generate an epilogue, we still
3415 need to save the register so that EH works. */
3417 emit_insn (gen_prologue_use (alt_reg
));
3421 alt_regno
= next_scratch_gr_reg ();
3422 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3423 emit_move_insn (alt_reg
, reg
);
3424 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3429 if (current_frame_info
.r
[reg_save_gp
])
3431 reg_emitted (reg_save_gp
);
3432 insn
= emit_move_insn (gen_rtx_REG (DImode
,
3433 current_frame_info
.r
[reg_save_gp
]),
3434 pic_offset_table_rtx
);
3437 /* We should now be at the base of the gr/br/fr spill area. */
3438 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3439 + current_frame_info
.spill_size
));
3441 /* Spill all general registers. */
3442 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3443 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3445 reg
= gen_rtx_REG (DImode
, regno
);
3446 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
3450 /* Spill the rest of the BR registers. */
3451 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3452 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3454 alt_regno
= next_scratch_gr_reg ();
3455 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3456 reg
= gen_rtx_REG (DImode
, regno
);
3457 emit_move_insn (alt_reg
, reg
);
3458 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3462 /* Align the frame and spill all FR registers. */
3463 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3464 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3466 gcc_assert (!(cfa_off
& 15));
3467 reg
= gen_rtx_REG (XFmode
, regno
);
3468 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
3472 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
3474 finish_spill_pointers ();
3477 /* Output the textual info surrounding the prologue. */
3480 ia64_start_function (FILE *file
, const char *fnname
,
3481 tree decl ATTRIBUTE_UNUSED
)
3483 #if VMS_DEBUGGING_INFO
3485 && strncmp (vms_debug_main
, fnname
, strlen (vms_debug_main
)) == 0)
3487 targetm
.asm_out
.globalize_label (asm_out_file
, VMS_DEBUG_MAIN_POINTER
);
3488 ASM_OUTPUT_DEF (asm_out_file
, VMS_DEBUG_MAIN_POINTER
, fnname
);
3489 dwarf2out_vms_debug_main_pointer ();
3494 fputs ("\t.proc ", file
);
3495 assemble_name (file
, fnname
);
3497 ASM_OUTPUT_LABEL (file
, fnname
);
3500 /* Called after register allocation to add any instructions needed for the
3501 epilogue. Using an epilogue insn is favored compared to putting all of the
3502 instructions in output_function_prologue(), since it allows the scheduler
3503 to intermix instructions with the saves of the caller saved registers. In
3504 some cases, it might be necessary to emit a barrier instruction as the last
3505 insn to prevent such scheduling. */
3508 ia64_expand_epilogue (int sibcall_p
)
3510 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
3511 int regno
, alt_regno
, cfa_off
;
3513 ia64_compute_frame_size (get_frame_size ());
3515 /* If there is a frame pointer, then we use it instead of the stack
3516 pointer, so that the stack pointer does not need to be valid when
3517 the epilogue starts. See EXIT_IGNORE_STACK. */
3518 if (frame_pointer_needed
)
3519 setup_spill_pointers (current_frame_info
.n_spilled
,
3520 hard_frame_pointer_rtx
, 0);
3522 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
3523 current_frame_info
.total_size
);
3525 if (current_frame_info
.total_size
!= 0)
3527 /* ??? At this point we must generate a magic insn that appears to
3528 modify the spill iterators and the frame pointer. This would
3529 allow the most scheduling freedom. For now, just hard stop. */
3530 emit_insn (gen_blockage ());
3533 /* Locate the bottom of the register save area. */
3534 cfa_off
= (current_frame_info
.spill_cfa_off
3535 + current_frame_info
.spill_size
3536 + current_frame_info
.extra_spill_size
);
3538 /* Restore the predicate registers. */
3539 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3541 if (current_frame_info
.r
[reg_save_pr
] != 0)
3543 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3544 reg_emitted (reg_save_pr
);
3548 alt_regno
= next_scratch_gr_reg ();
3549 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3550 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3553 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3554 emit_move_insn (reg
, alt_reg
);
3557 /* Restore the application registers. */
3559 /* Load the saved unat from the stack, but do not restore it until
3560 after the GRs have been restored. */
3561 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3563 if (current_frame_info
.r
[reg_save_ar_unat
] != 0)
3566 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3567 reg_emitted (reg_save_ar_unat
);
3571 alt_regno
= next_scratch_gr_reg ();
3572 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3573 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3574 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3579 ar_unat_save_reg
= NULL_RTX
;
3581 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0)
3583 reg_emitted (reg_save_ar_pfs
);
3584 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_pfs
]);
3585 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3586 emit_move_insn (reg
, alt_reg
);
3588 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3590 alt_regno
= next_scratch_gr_reg ();
3591 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3592 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3594 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3595 emit_move_insn (reg
, alt_reg
);
3598 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3600 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3602 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3603 reg_emitted (reg_save_ar_lc
);
3607 alt_regno
= next_scratch_gr_reg ();
3608 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3609 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3612 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3613 emit_move_insn (reg
, alt_reg
);
3616 /* Restore the return pointer. */
3617 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3619 if (current_frame_info
.r
[reg_save_b0
] != 0)
3621 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3622 reg_emitted (reg_save_b0
);
3626 alt_regno
= next_scratch_gr_reg ();
3627 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3628 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3631 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3632 emit_move_insn (reg
, alt_reg
);
3635 /* We should now be at the base of the gr/br/fr spill area. */
3636 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3637 + current_frame_info
.spill_size
));
3639 /* The GP may be stored on the stack in the prologue, but it's
3640 never restored in the epilogue. Skip the stack slot. */
3641 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3644 /* Restore all general registers. */
3645 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3646 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3648 reg
= gen_rtx_REG (DImode
, regno
);
3649 do_restore (gen_gr_restore
, reg
, cfa_off
);
3653 /* Restore the branch registers. */
3654 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3655 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3657 alt_regno
= next_scratch_gr_reg ();
3658 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3659 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3661 reg
= gen_rtx_REG (DImode
, regno
);
3662 emit_move_insn (reg
, alt_reg
);
3665 /* Restore floating point registers. */
3666 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3667 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3669 gcc_assert (!(cfa_off
& 15));
3670 reg
= gen_rtx_REG (XFmode
, regno
);
3671 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
3675 /* Restore ar.unat for real. */
3676 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3678 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3679 emit_move_insn (reg
, ar_unat_save_reg
);
3682 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
3684 finish_spill_pointers ();
3686 if (current_frame_info
.total_size
3687 || cfun
->machine
->ia64_eh_epilogue_sp
3688 || frame_pointer_needed
)
3690 /* ??? At this point we must generate a magic insn that appears to
3691 modify the spill iterators, the stack pointer, and the frame
3692 pointer. This would allow the most scheduling freedom. For now,
3694 emit_insn (gen_blockage ());
3697 if (cfun
->machine
->ia64_eh_epilogue_sp
)
3698 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
3699 else if (frame_pointer_needed
)
3701 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3702 RTX_FRAME_RELATED_P (insn
) = 1;
3703 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL
);
3705 else if (current_frame_info
.total_size
)
3707 rtx offset
, frame_size_rtx
;
3709 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
3710 if (satisfies_constraint_I (frame_size_rtx
))
3711 offset
= frame_size_rtx
;
3714 regno
= next_scratch_gr_reg ();
3715 offset
= gen_rtx_REG (DImode
, regno
);
3716 emit_move_insn (offset
, frame_size_rtx
);
3719 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
3722 RTX_FRAME_RELATED_P (insn
) = 1;
3723 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3724 gen_rtx_SET (VOIDmode
,
3726 gen_rtx_PLUS (DImode
,
3731 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
3732 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
3735 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
3738 int fp
= GR_REG (2);
3739 /* We need a throw away register here, r0 and r1 are reserved,
3740 so r2 is the first available call clobbered register. If
3741 there was a frame_pointer register, we may have swapped the
3742 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
3743 sure we're using the string "r2" when emitting the register
3744 name for the assembler. */
3745 if (current_frame_info
.r
[reg_fp
]
3746 && current_frame_info
.r
[reg_fp
] == GR_REG (2))
3747 fp
= HARD_FRAME_POINTER_REGNUM
;
3749 /* We must emit an alloc to force the input registers to become output
3750 registers. Otherwise, if the callee tries to pass its parameters
3751 through to another call without an intervening alloc, then these
3753 /* ??? We don't need to preserve all input registers. We only need to
3754 preserve those input registers used as arguments to the sibling call.
3755 It is unclear how to compute that number here. */
3756 if (current_frame_info
.n_input_regs
!= 0)
3758 rtx n_inputs
= GEN_INT (current_frame_info
.n_input_regs
);
3759 insn
= emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
3760 const0_rtx
, const0_rtx
,
3761 n_inputs
, const0_rtx
));
3762 RTX_FRAME_RELATED_P (insn
) = 1;
3767 /* Return 1 if br.ret can do all the work required to return from a
3771 ia64_direct_return (void)
3773 if (reload_completed
&& ! frame_pointer_needed
)
3775 ia64_compute_frame_size (get_frame_size ());
3777 return (current_frame_info
.total_size
== 0
3778 && current_frame_info
.n_spilled
== 0
3779 && current_frame_info
.r
[reg_save_b0
] == 0
3780 && current_frame_info
.r
[reg_save_pr
] == 0
3781 && current_frame_info
.r
[reg_save_ar_pfs
] == 0
3782 && current_frame_info
.r
[reg_save_ar_unat
] == 0
3783 && current_frame_info
.r
[reg_save_ar_lc
] == 0);
3788 /* Return the magic cookie that we use to hold the return address
3789 during early compilation. */
3792 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
3796 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
3799 /* Split this value after reload, now that we know where the return
3800 address is saved. */
3803 ia64_split_return_addr_rtx (rtx dest
)
3807 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3809 if (current_frame_info
.r
[reg_save_b0
] != 0)
3811 src
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3812 reg_emitted (reg_save_b0
);
3820 /* Compute offset from CFA for BR0. */
3821 /* ??? Must be kept in sync with ia64_expand_prologue. */
3822 off
= (current_frame_info
.spill_cfa_off
3823 + current_frame_info
.spill_size
);
3824 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3825 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3828 /* Convert CFA offset to a register based offset. */
3829 if (frame_pointer_needed
)
3830 src
= hard_frame_pointer_rtx
;
3833 src
= stack_pointer_rtx
;
3834 off
+= current_frame_info
.total_size
;
3837 /* Load address into scratch register. */
3838 off_r
= GEN_INT (off
);
3839 if (satisfies_constraint_I (off_r
))
3840 emit_insn (gen_adddi3 (dest
, src
, off_r
));
3843 emit_move_insn (dest
, off_r
);
3844 emit_insn (gen_adddi3 (dest
, src
, dest
));
3847 src
= gen_rtx_MEM (Pmode
, dest
);
3851 src
= gen_rtx_REG (DImode
, BR_REG (0));
3853 emit_move_insn (dest
, src
);
3857 ia64_hard_regno_rename_ok (int from
, int to
)
3859 /* Don't clobber any of the registers we reserved for the prologue. */
3862 for (r
= reg_fp
; r
<= reg_save_ar_lc
; r
++)
3863 if (to
== current_frame_info
.r
[r
]
3864 || from
== current_frame_info
.r
[r
]
3865 || to
== emitted_frame_related_regs
[r
]
3866 || from
== emitted_frame_related_regs
[r
])
3869 /* Don't use output registers outside the register frame. */
3870 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
3873 /* Retain even/oddness on predicate register pairs. */
3874 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
3875 return (from
& 1) == (to
& 1);
3880 /* Target hook for assembling integer objects. Handle word-sized
3881 aligned objects and detect the cases when @fptr is needed. */
3884 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3886 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
3887 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3888 && GET_CODE (x
) == SYMBOL_REF
3889 && SYMBOL_REF_FUNCTION_P (x
))
3891 static const char * const directive
[2][2] = {
3892 /* 64-bit pointer */ /* 32-bit pointer */
3893 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3894 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3896 fputs (directive
[(aligned_p
!= 0)][POINTER_SIZE
== 32], asm_out_file
);
3897 output_addr_const (asm_out_file
, x
);
3898 fputs (")\n", asm_out_file
);
3901 return default_assemble_integer (x
, size
, aligned_p
);
3904 /* Emit the function prologue. */
3907 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3909 int mask
, grsave
, grsave_prev
;
3911 if (current_frame_info
.need_regstk
)
3912 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3913 current_frame_info
.n_input_regs
,
3914 current_frame_info
.n_local_regs
,
3915 current_frame_info
.n_output_regs
,
3916 current_frame_info
.n_rotate_regs
);
3918 if (ia64_except_unwind_info () != UI_TARGET
)
3921 /* Emit the .prologue directive. */
3924 grsave
= grsave_prev
= 0;
3925 if (current_frame_info
.r
[reg_save_b0
] != 0)
3928 grsave
= grsave_prev
= current_frame_info
.r
[reg_save_b0
];
3930 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0
3931 && (grsave_prev
== 0
3932 || current_frame_info
.r
[reg_save_ar_pfs
] == grsave_prev
+ 1))
3935 if (grsave_prev
== 0)
3936 grsave
= current_frame_info
.r
[reg_save_ar_pfs
];
3937 grsave_prev
= current_frame_info
.r
[reg_save_ar_pfs
];
3939 if (current_frame_info
.r
[reg_fp
] != 0
3940 && (grsave_prev
== 0
3941 || current_frame_info
.r
[reg_fp
] == grsave_prev
+ 1))
3944 if (grsave_prev
== 0)
3945 grsave
= HARD_FRAME_POINTER_REGNUM
;
3946 grsave_prev
= current_frame_info
.r
[reg_fp
];
3948 if (current_frame_info
.r
[reg_save_pr
] != 0
3949 && (grsave_prev
== 0
3950 || current_frame_info
.r
[reg_save_pr
] == grsave_prev
+ 1))
3953 if (grsave_prev
== 0)
3954 grsave
= current_frame_info
.r
[reg_save_pr
];
3957 if (mask
&& TARGET_GNU_AS
)
3958 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3959 ia64_dbx_register_number (grsave
));
3961 fputs ("\t.prologue\n", file
);
3963 /* Emit a .spill directive, if necessary, to relocate the base of
3964 the register spill area. */
3965 if (current_frame_info
.spill_cfa_off
!= -16)
3966 fprintf (file
, "\t.spill %ld\n",
3967 (long) (current_frame_info
.spill_cfa_off
3968 + current_frame_info
.spill_size
));
3971 /* Emit the .body directive at the scheduled end of the prologue. */
3974 ia64_output_function_end_prologue (FILE *file
)
3976 if (ia64_except_unwind_info () != UI_TARGET
)
3979 fputs ("\t.body\n", file
);
3982 /* Emit the function epilogue. */
3985 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
3986 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3990 if (current_frame_info
.r
[reg_fp
])
3992 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3993 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3994 = reg_names
[current_frame_info
.r
[reg_fp
]];
3995 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
3996 reg_emitted (reg_fp
);
3998 if (! TARGET_REG_NAMES
)
4000 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
4001 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
4002 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
4003 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
4004 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
4005 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
4008 current_frame_info
.initialized
= 0;
4012 ia64_dbx_register_number (int regno
)
4014 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4015 from its home at loc79 to something inside the register frame. We
4016 must perform the same renumbering here for the debug info. */
4017 if (current_frame_info
.r
[reg_fp
])
4019 if (regno
== HARD_FRAME_POINTER_REGNUM
)
4020 regno
= current_frame_info
.r
[reg_fp
];
4021 else if (regno
== current_frame_info
.r
[reg_fp
])
4022 regno
= HARD_FRAME_POINTER_REGNUM
;
4025 if (IN_REGNO_P (regno
))
4026 return 32 + regno
- IN_REG (0);
4027 else if (LOC_REGNO_P (regno
))
4028 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
4029 else if (OUT_REGNO_P (regno
))
4030 return (32 + current_frame_info
.n_input_regs
4031 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
4036 /* Implement TARGET_TRAMPOLINE_INIT.
4038 The trampoline should set the static chain pointer to value placed
4039 into the trampoline and should branch to the specified routine.
4040 To make the normal indirect-subroutine calling convention work,
4041 the trampoline must look like a function descriptor; the first
4042 word being the target address and the second being the target's
4045 We abuse the concept of a global pointer by arranging for it
4046 to point to the data we need to load. The complete trampoline
4047 has the following form:
4049 +-------------------+ \
4050 TRAMP: | __ia64_trampoline | |
4051 +-------------------+ > fake function descriptor
4053 +-------------------+ /
4054 | target descriptor |
4055 +-------------------+
4057 +-------------------+
4061 ia64_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
4063 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4064 rtx addr
, addr_reg
, tramp
, eight
= GEN_INT (8);
4066 /* The Intel assembler requires that the global __ia64_trampoline symbol
4067 be declared explicitly */
4070 static bool declared_ia64_trampoline
= false;
4072 if (!declared_ia64_trampoline
)
4074 declared_ia64_trampoline
= true;
4075 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
4076 "__ia64_trampoline");
4080 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4081 addr
= convert_memory_address (Pmode
, XEXP (m_tramp
, 0));
4082 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
4083 static_chain
= convert_memory_address (Pmode
, static_chain
);
4085 /* Load up our iterator. */
4086 addr_reg
= copy_to_reg (addr
);
4087 m_tramp
= adjust_automodify_address (m_tramp
, Pmode
, addr_reg
, 0);
4089 /* The first two words are the fake descriptor:
4090 __ia64_trampoline, ADDR+16. */
4091 tramp
= gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline");
4092 if (TARGET_ABI_OPEN_VMS
)
4094 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4095 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4096 relocation against function symbols to make it identical to the
4097 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4098 strict ELF and dereference to get the bare code address. */
4099 rtx reg
= gen_reg_rtx (Pmode
);
4100 SYMBOL_REF_FLAGS (tramp
) |= SYMBOL_FLAG_FUNCTION
;
4101 emit_move_insn (reg
, tramp
);
4102 emit_move_insn (reg
, gen_rtx_MEM (Pmode
, reg
));
4105 emit_move_insn (m_tramp
, tramp
);
4106 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4107 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4109 emit_move_insn (m_tramp
, force_reg (Pmode
, plus_constant (addr
, 16)));
4110 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4111 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4113 /* The third word is the target descriptor. */
4114 emit_move_insn (m_tramp
, force_reg (Pmode
, fnaddr
));
4115 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4116 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4118 /* The fourth word is the static chain. */
4119 emit_move_insn (m_tramp
, static_chain
);
4122 /* Do any needed setup for a variadic function. CUM has not been updated
4123 for the last named argument which has type TYPE and mode MODE.
4125 We generate the actual spill instructions during prologue generation. */
4128 ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4129 tree type
, int * pretend_size
,
4130 int second_time ATTRIBUTE_UNUSED
)
4132 CUMULATIVE_ARGS next_cum
= *cum
;
4134 /* Skip the current argument. */
4135 ia64_function_arg_advance (&next_cum
, mode
, type
, 1);
4137 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
4139 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
4140 *pretend_size
= n
* UNITS_PER_WORD
;
4141 cfun
->machine
->n_varargs
= n
;
4145 /* Check whether TYPE is a homogeneous floating point aggregate. If
4146 it is, return the mode of the floating point type that appears
4147 in all leafs. If it is not, return VOIDmode.
4149 An aggregate is a homogeneous floating point aggregate is if all
4150 fields/elements in it have the same floating point type (e.g,
4151 SFmode). 128-bit quad-precision floats are excluded.
4153 Variable sized aggregates should never arrive here, since we should
4154 have already decided to pass them by reference. Top-level zero-sized
4155 aggregates are excluded because our parallels crash the middle-end. */
4157 static enum machine_mode
4158 hfa_element_mode (const_tree type
, bool nested
)
4160 enum machine_mode element_mode
= VOIDmode
;
4161 enum machine_mode mode
;
4162 enum tree_code code
= TREE_CODE (type
);
4163 int know_element_mode
= 0;
4166 if (!nested
&& (!TYPE_SIZE (type
) || integer_zerop (TYPE_SIZE (type
))))
4171 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
4172 case BOOLEAN_TYPE
: case POINTER_TYPE
:
4173 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
4174 case LANG_TYPE
: case FUNCTION_TYPE
:
4177 /* Fortran complex types are supposed to be HFAs, so we need to handle
4178 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4181 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
4182 && TYPE_MODE (type
) != TCmode
)
4183 return GET_MODE_INNER (TYPE_MODE (type
));
4188 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4189 mode if this is contained within an aggregate. */
4190 if (nested
&& TYPE_MODE (type
) != TFmode
)
4191 return TYPE_MODE (type
);
4196 return hfa_element_mode (TREE_TYPE (type
), 1);
4200 case QUAL_UNION_TYPE
:
4201 for (t
= TYPE_FIELDS (type
); t
; t
= DECL_CHAIN (t
))
4203 if (TREE_CODE (t
) != FIELD_DECL
)
4206 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
4207 if (know_element_mode
)
4209 if (mode
!= element_mode
)
4212 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
4216 know_element_mode
= 1;
4217 element_mode
= mode
;
4220 return element_mode
;
4223 /* If we reach here, we probably have some front-end specific type
4224 that the backend doesn't know about. This can happen via the
4225 aggregate_value_p call in init_function_start. All we can do is
4226 ignore unknown tree types. */
4233 /* Return the number of words required to hold a quantity of TYPE and MODE
4234 when passed as an argument. */
4236 ia64_function_arg_words (tree type
, enum machine_mode mode
)
4240 if (mode
== BLKmode
)
4241 words
= int_size_in_bytes (type
);
4243 words
= GET_MODE_SIZE (mode
);
4245 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
4248 /* Return the number of registers that should be skipped so the current
4249 argument (described by TYPE and WORDS) will be properly aligned.
4251 Integer and float arguments larger than 8 bytes start at the next
4252 even boundary. Aggregates larger than 8 bytes start at the next
4253 even boundary if the aggregate has 16 byte alignment. Note that
4254 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4255 but are still to be aligned in registers.
4257 ??? The ABI does not specify how to handle aggregates with
4258 alignment from 9 to 15 bytes, or greater than 16. We handle them
4259 all as if they had 16 byte alignment. Such aggregates can occur
4260 only if gcc extensions are used. */
4262 ia64_function_arg_offset (CUMULATIVE_ARGS
*cum
, tree type
, int words
)
4264 /* No registers are skipped on VMS. */
4265 if (TARGET_ABI_OPEN_VMS
|| (cum
->words
& 1) == 0)
4269 && TREE_CODE (type
) != INTEGER_TYPE
4270 && TREE_CODE (type
) != REAL_TYPE
)
4271 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
4276 /* Return rtx for register where argument is passed, or zero if it is passed
4278 /* ??? 128-bit quad-precision floats are always passed in general
4282 ia64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
4283 int named
, int incoming
)
4285 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
4286 int words
= ia64_function_arg_words (type
, mode
);
4287 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4288 enum machine_mode hfa_mode
= VOIDmode
;
4290 /* For OPEN VMS, emit the instruction setting up the argument register here,
4291 when we know this will be together with the other arguments setup related
4292 insns. This is not the conceptually best place to do this, but this is
4293 the easiest as we have convenient access to cumulative args info. */
4295 if (TARGET_ABI_OPEN_VMS
&& mode
== VOIDmode
&& type
== void_type_node
4298 unsigned HOST_WIDE_INT regval
= cum
->words
;
4301 for (i
= 0; i
< 8; i
++)
4302 regval
|= ((int) cum
->atypes
[i
]) << (i
* 3 + 8);
4304 emit_move_insn (gen_rtx_REG (DImode
, GR_REG (25)),
4308 /* If all argument slots are used, then it must go on the stack. */
4309 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4312 /* Check for and handle homogeneous FP aggregates. */
4314 hfa_mode
= hfa_element_mode (type
, 0);
4316 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4317 and unprototyped hfas are passed specially. */
4318 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4322 int fp_regs
= cum
->fp_regs
;
4323 int int_regs
= cum
->words
+ offset
;
4324 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4328 /* If prototyped, pass it in FR regs then GR regs.
4329 If not prototyped, pass it in both FR and GR regs.
4331 If this is an SFmode aggregate, then it is possible to run out of
4332 FR regs while GR regs are still left. In that case, we pass the
4333 remaining part in the GR regs. */
4335 /* Fill the FP regs. We do this always. We stop if we reach the end
4336 of the argument, the last FP register, or the last argument slot. */
4338 byte_size
= ((mode
== BLKmode
)
4339 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4340 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4342 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4343 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
4345 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4346 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
4350 args_byte_size
+= hfa_size
;
4354 /* If no prototype, then the whole thing must go in GR regs. */
4355 if (! cum
->prototype
)
4357 /* If this is an SFmode aggregate, then we might have some left over
4358 that needs to go in GR regs. */
4359 else if (byte_size
!= offset
)
4360 int_regs
+= offset
/ UNITS_PER_WORD
;
4362 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4364 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
4366 enum machine_mode gr_mode
= DImode
;
4367 unsigned int gr_size
;
4369 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4370 then this goes in a GR reg left adjusted/little endian, right
4371 adjusted/big endian. */
4372 /* ??? Currently this is handled wrong, because 4-byte hunks are
4373 always right adjusted/little endian. */
4376 /* If we have an even 4 byte hunk because the aggregate is a
4377 multiple of 4 bytes in size, then this goes in a GR reg right
4378 adjusted/little endian. */
4379 else if (byte_size
- offset
== 4)
4382 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4383 gen_rtx_REG (gr_mode
, (basereg
4387 gr_size
= GET_MODE_SIZE (gr_mode
);
4389 if (gr_size
== UNITS_PER_WORD
4390 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
4392 else if (gr_size
> UNITS_PER_WORD
)
4393 int_regs
+= gr_size
/ UNITS_PER_WORD
;
4395 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4398 /* On OpenVMS variable argument is either in Rn or Fn. */
4399 else if (TARGET_ABI_OPEN_VMS
&& named
== 0)
4401 if (FLOAT_MODE_P (mode
))
4402 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->words
);
4404 return gen_rtx_REG (mode
, basereg
+ cum
->words
);
4407 /* Integral and aggregates go in general registers. If we have run out of
4408 FR registers, then FP values must also go in general registers. This can
4409 happen when we have a SFmode HFA. */
4410 else if (mode
== TFmode
|| mode
== TCmode
4411 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4413 int byte_size
= ((mode
== BLKmode
)
4414 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4415 if (BYTES_BIG_ENDIAN
4416 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
4417 && byte_size
< UNITS_PER_WORD
4420 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4421 gen_rtx_REG (DImode
,
4422 (basereg
+ cum
->words
4425 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
4428 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4432 /* If there is a prototype, then FP values go in a FR register when
4433 named, and in a GR register when unnamed. */
4434 else if (cum
->prototype
)
4437 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
4438 /* In big-endian mode, an anonymous SFmode value must be represented
4439 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4440 the value into the high half of the general register. */
4441 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
4442 return gen_rtx_PARALLEL (mode
,
4444 gen_rtx_EXPR_LIST (VOIDmode
,
4445 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
4448 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4450 /* If there is no prototype, then FP values go in both FR and GR
4454 /* See comment above. */
4455 enum machine_mode inner_mode
=
4456 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
4458 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4459 gen_rtx_REG (mode
, (FR_ARG_FIRST
4462 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4463 gen_rtx_REG (inner_mode
,
4464 (basereg
+ cum
->words
4468 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
4472 /* Return number of bytes, at the beginning of the argument, that must be
4473 put in registers. 0 is the argument is entirely in registers or entirely
4477 ia64_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4478 tree type
, bool named ATTRIBUTE_UNUSED
)
4480 int words
= ia64_function_arg_words (type
, mode
);
4481 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4483 /* If all argument slots are used, then it must go on the stack. */
4484 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4487 /* It doesn't matter whether the argument goes in FR or GR regs. If
4488 it fits within the 8 argument slots, then it goes entirely in
4489 registers. If it extends past the last argument slot, then the rest
4490 goes on the stack. */
4492 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
4495 return (MAX_ARGUMENT_SLOTS
- cum
->words
- offset
) * UNITS_PER_WORD
;
4498 /* Return ivms_arg_type based on machine_mode. */
4500 static enum ivms_arg_type
4501 ia64_arg_type (enum machine_mode mode
)
4514 /* Update CUM to point after this argument. This is patterned after
4515 ia64_function_arg. */
4518 ia64_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4519 tree type
, int named
)
4521 int words
= ia64_function_arg_words (type
, mode
);
4522 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4523 enum machine_mode hfa_mode
= VOIDmode
;
4525 /* If all arg slots are already full, then there is nothing to do. */
4526 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
4528 cum
->words
+= words
+ offset
;
4532 cum
->atypes
[cum
->words
] = ia64_arg_type (mode
);
4533 cum
->words
+= words
+ offset
;
4535 /* Check for and handle homogeneous FP aggregates. */
4537 hfa_mode
= hfa_element_mode (type
, 0);
4539 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4540 and unprototyped hfas are passed specially. */
4541 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4543 int fp_regs
= cum
->fp_regs
;
4544 /* This is the original value of cum->words + offset. */
4545 int int_regs
= cum
->words
- words
;
4546 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4550 /* If prototyped, pass it in FR regs then GR regs.
4551 If not prototyped, pass it in both FR and GR regs.
4553 If this is an SFmode aggregate, then it is possible to run out of
4554 FR regs while GR regs are still left. In that case, we pass the
4555 remaining part in the GR regs. */
4557 /* Fill the FP regs. We do this always. We stop if we reach the end
4558 of the argument, the last FP register, or the last argument slot. */
4560 byte_size
= ((mode
== BLKmode
)
4561 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4562 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4564 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4565 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
4568 args_byte_size
+= hfa_size
;
4572 cum
->fp_regs
= fp_regs
;
4575 /* On OpenVMS variable argument is either in Rn or Fn. */
4576 else if (TARGET_ABI_OPEN_VMS
&& named
== 0)
4578 cum
->int_regs
= cum
->words
;
4579 cum
->fp_regs
= cum
->words
;
4582 /* Integral and aggregates go in general registers. So do TFmode FP values.
4583 If we have run out of FR registers, then other FP values must also go in
4584 general registers. This can happen when we have a SFmode HFA. */
4585 else if (mode
== TFmode
|| mode
== TCmode
4586 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4587 cum
->int_regs
= cum
->words
;
4589 /* If there is a prototype, then FP values go in a FR register when
4590 named, and in a GR register when unnamed. */
4591 else if (cum
->prototype
)
4594 cum
->int_regs
= cum
->words
;
4596 /* ??? Complex types should not reach here. */
4597 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4599 /* If there is no prototype, then FP values go in both FR and GR
4603 /* ??? Complex types should not reach here. */
4604 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4605 cum
->int_regs
= cum
->words
;
4609 /* Arguments with alignment larger than 8 bytes start at the next even
4610 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4611 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4614 ia64_function_arg_boundary (enum machine_mode mode
, tree type
)
4617 if (mode
== TFmode
&& TARGET_HPUX
&& TARGET_ILP32
)
4618 return PARM_BOUNDARY
* 2;
4622 if (TYPE_ALIGN (type
) > PARM_BOUNDARY
)
4623 return PARM_BOUNDARY
* 2;
4625 return PARM_BOUNDARY
;
4628 if (GET_MODE_BITSIZE (mode
) > PARM_BOUNDARY
)
4629 return PARM_BOUNDARY
* 2;
4631 return PARM_BOUNDARY
;
4634 /* True if it is OK to do sibling call optimization for the specified
4635 call expression EXP. DECL will be the called function, or NULL if
4636 this is an indirect call. */
4638 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
4640 /* We can't perform a sibcall if the current function has the syscall_linkage
4642 if (lookup_attribute ("syscall_linkage",
4643 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
4646 /* We must always return with our current GP. This means we can
4647 only sibcall to functions defined in the current module unless
4648 TARGET_CONST_GP is set to true. */
4649 return (decl
&& (*targetm
.binds_local_p
) (decl
)) || TARGET_CONST_GP
;
4653 /* Implement va_arg. */
4656 ia64_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
4659 /* Variable sized types are passed by reference. */
4660 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
4662 tree ptrtype
= build_pointer_type (type
);
4663 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
4664 return build_va_arg_indirect_ref (addr
);
4667 /* Aggregate arguments with alignment larger than 8 bytes start at
4668 the next even boundary. Integer and floating point arguments
4669 do so if they are larger than 8 bytes, whether or not they are
4670 also aligned larger than 8 bytes. */
4671 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
4672 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
4674 tree t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4675 size_int (2 * UNITS_PER_WORD
- 1));
4676 t
= fold_convert (sizetype
, t
);
4677 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4678 size_int (-2 * UNITS_PER_WORD
));
4679 t
= fold_convert (TREE_TYPE (valist
), t
);
4680 gimplify_assign (unshare_expr (valist
), t
, pre_p
);
4683 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4686 /* Return 1 if function return value returned in memory. Return 0 if it is
4690 ia64_return_in_memory (const_tree valtype
, const_tree fntype ATTRIBUTE_UNUSED
)
4692 enum machine_mode mode
;
4693 enum machine_mode hfa_mode
;
4694 HOST_WIDE_INT byte_size
;
4696 mode
= TYPE_MODE (valtype
);
4697 byte_size
= GET_MODE_SIZE (mode
);
4698 if (mode
== BLKmode
)
4700 byte_size
= int_size_in_bytes (valtype
);
4705 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4707 hfa_mode
= hfa_element_mode (valtype
, 0);
4708 if (hfa_mode
!= VOIDmode
)
4710 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4712 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
4717 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
4723 /* Return rtx for register that holds the function return value. */
4726 ia64_function_value (const_tree valtype
,
4727 const_tree fn_decl_or_type
,
4728 bool outgoing ATTRIBUTE_UNUSED
)
4730 enum machine_mode mode
;
4731 enum machine_mode hfa_mode
;
4733 const_tree func
= fn_decl_or_type
;
4736 && !DECL_P (fn_decl_or_type
))
4739 mode
= TYPE_MODE (valtype
);
4740 hfa_mode
= hfa_element_mode (valtype
, 0);
4742 if (hfa_mode
!= VOIDmode
)
4750 hfa_size
= GET_MODE_SIZE (hfa_mode
);
4751 byte_size
= ((mode
== BLKmode
)
4752 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
4754 for (i
= 0; offset
< byte_size
; i
++)
4756 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4757 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
4761 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4763 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
4764 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
4767 bool need_parallel
= false;
4769 /* In big-endian mode, we need to manage the layout of aggregates
4770 in the registers so that we get the bits properly aligned in
4771 the highpart of the registers. */
4772 if (BYTES_BIG_ENDIAN
4773 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
4774 need_parallel
= true;
4776 /* Something like struct S { long double x; char a[0] } is not an
4777 HFA structure, and therefore doesn't go in fp registers. But
4778 the middle-end will give it XFmode anyway, and XFmode values
4779 don't normally fit in integer registers. So we need to smuggle
4780 the value inside a parallel. */
4781 else if (mode
== XFmode
|| mode
== XCmode
|| mode
== RFmode
)
4782 need_parallel
= true;
4792 bytesize
= int_size_in_bytes (valtype
);
4793 /* An empty PARALLEL is invalid here, but the return value
4794 doesn't matter for empty structs. */
4796 return gen_rtx_REG (mode
, GR_RET_FIRST
);
4797 for (i
= 0; offset
< bytesize
; i
++)
4799 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4800 gen_rtx_REG (DImode
,
4803 offset
+= UNITS_PER_WORD
;
4805 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4808 mode
= ia64_promote_function_mode (valtype
, mode
, &unsignedp
,
4809 func
? TREE_TYPE (func
) : NULL_TREE
,
4812 return gen_rtx_REG (mode
, GR_RET_FIRST
);
4816 /* Worker function for TARGET_LIBCALL_VALUE. */
4819 ia64_libcall_value (enum machine_mode mode
,
4820 const_rtx fun ATTRIBUTE_UNUSED
)
4822 return gen_rtx_REG (mode
,
4823 (((GET_MODE_CLASS (mode
) == MODE_FLOAT
4824 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4825 && (mode
) != TFmode
)
4826 ? FR_RET_FIRST
: GR_RET_FIRST
));
4829 /* Worker function for FUNCTION_VALUE_REGNO_P. */
4832 ia64_function_value_regno_p (const unsigned int regno
)
4834 return ((regno
>= GR_RET_FIRST
&& regno
<= GR_RET_LAST
)
4835 || (regno
>= FR_RET_FIRST
&& regno
<= FR_RET_LAST
));
4838 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4839 We need to emit DTP-relative relocations. */
4842 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4844 gcc_assert (size
== 4 || size
== 8);
4846 fputs ("\tdata4.ua\t@dtprel(", file
);
4848 fputs ("\tdata8.ua\t@dtprel(", file
);
4849 output_addr_const (file
, x
);
4853 /* Print a memory address as an operand to reference that memory location. */
4855 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4856 also call this from ia64_print_operand for memory addresses. */
4859 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
4860 rtx address ATTRIBUTE_UNUSED
)
4864 /* Print an operand to an assembler instruction.
4865 C Swap and print a comparison operator.
4866 D Print an FP comparison operator.
4867 E Print 32 - constant, for SImode shifts as extract.
4868 e Print 64 - constant, for DImode rotates.
4869 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4870 a floating point register emitted normally.
4871 G A floating point constant.
4872 I Invert a predicate register by adding 1.
4873 J Select the proper predicate register for a condition.
4874 j Select the inverse predicate register for a condition.
4875 O Append .acq for volatile load.
4876 P Postincrement of a MEM.
4877 Q Append .rel for volatile store.
4878 R Print .s .d or nothing for a single, double or no truncation.
4879 S Shift amount for shladd instruction.
4880 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4881 for Intel assembler.
4882 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4883 for Intel assembler.
4884 X A pair of floating point registers.
4885 r Print register name, or constant 0 as r0. HP compatibility for
4887 v Print vector constant value as an 8-byte integer value. */
4890 ia64_print_operand (FILE * file
, rtx x
, int code
)
4897 /* Handled below. */
4902 enum rtx_code c
= swap_condition (GET_CODE (x
));
4903 fputs (GET_RTX_NAME (c
), file
);
4908 switch (GET_CODE (x
))
4932 str
= GET_RTX_NAME (GET_CODE (x
));
4939 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
4943 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
4947 if (x
== CONST0_RTX (GET_MODE (x
)))
4948 str
= reg_names
[FR_REG (0)];
4949 else if (x
== CONST1_RTX (GET_MODE (x
)))
4950 str
= reg_names
[FR_REG (1)];
4953 gcc_assert (GET_CODE (x
) == REG
);
4954 str
= reg_names
[REGNO (x
)];
4963 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
4964 real_to_target (val
, &rv
, GET_MODE (x
));
4965 if (GET_MODE (x
) == SFmode
)
4966 fprintf (file
, "0x%08lx", val
[0] & 0xffffffff);
4967 else if (GET_MODE (x
) == DFmode
)
4968 fprintf (file
, "0x%08lx%08lx", (WORDS_BIG_ENDIAN
? val
[0] : val
[1])
4970 (WORDS_BIG_ENDIAN
? val
[1] : val
[0])
4973 output_operand_lossage ("invalid %%G mode");
4978 fputs (reg_names
[REGNO (x
) + 1], file
);
4984 unsigned int regno
= REGNO (XEXP (x
, 0));
4985 if (GET_CODE (x
) == EQ
)
4989 fputs (reg_names
[regno
], file
);
4994 if (MEM_VOLATILE_P (x
))
4995 fputs(".acq", file
);
5000 HOST_WIDE_INT value
;
5002 switch (GET_CODE (XEXP (x
, 0)))
5008 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5009 if (GET_CODE (x
) == CONST_INT
)
5013 gcc_assert (GET_CODE (x
) == REG
);
5014 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
5020 value
= GET_MODE_SIZE (GET_MODE (x
));
5024 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
5028 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
5033 if (MEM_VOLATILE_P (x
))
5034 fputs(".rel", file
);
5038 if (x
== CONST0_RTX (GET_MODE (x
)))
5040 else if (x
== CONST1_RTX (GET_MODE (x
)))
5042 else if (x
== CONST2_RTX (GET_MODE (x
)))
5045 output_operand_lossage ("invalid %%R value");
5049 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5053 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5055 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
5061 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5063 const char *prefix
= "0x";
5064 if (INTVAL (x
) & 0x80000000)
5066 fprintf (file
, "0xffffffff");
5069 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
5076 unsigned int regno
= REGNO (x
);
5077 fprintf (file
, "%s, %s", reg_names
[regno
], reg_names
[regno
+ 1]);
5082 /* If this operand is the constant zero, write it as register zero.
5083 Any register, zero, or CONST_INT value is OK here. */
5084 if (GET_CODE (x
) == REG
)
5085 fputs (reg_names
[REGNO (x
)], file
);
5086 else if (x
== CONST0_RTX (GET_MODE (x
)))
5088 else if (GET_CODE (x
) == CONST_INT
)
5089 output_addr_const (file
, x
);
5091 output_operand_lossage ("invalid %%r value");
5095 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
5096 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
5103 /* For conditional branches, returns or calls, substitute
5104 sptk, dptk, dpnt, or spnt for %s. */
5105 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
5108 int pred_val
= INTVAL (XEXP (x
, 0));
5110 /* Guess top and bottom 10% statically predicted. */
5111 if (pred_val
< REG_BR_PROB_BASE
/ 50
5112 && br_prob_note_reliable_p (x
))
5114 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
5116 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98
5117 || !br_prob_note_reliable_p (x
))
5122 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
5127 fputs (which
, file
);
5132 x
= current_insn_predicate
;
5135 unsigned int regno
= REGNO (XEXP (x
, 0));
5136 if (GET_CODE (x
) == EQ
)
5138 fprintf (file
, "(%s) ", reg_names
[regno
]);
5143 output_operand_lossage ("ia64_print_operand: unknown code");
5147 switch (GET_CODE (x
))
5149 /* This happens for the spill/restore instructions. */
5154 /* ... fall through ... */
5157 fputs (reg_names
[REGNO (x
)], file
);
5162 rtx addr
= XEXP (x
, 0);
5163 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
5164 addr
= XEXP (addr
, 0);
5165 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
5170 output_addr_const (file
, x
);
5177 /* Compute a (partial) cost for rtx X. Return true if the complete
5178 cost has been computed, and false if subexpressions should be
5179 scanned. In either case, *TOTAL contains the cost result. */
5180 /* ??? This is incomplete. */
5183 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
5184 bool speed ATTRIBUTE_UNUSED
)
5192 *total
= satisfies_constraint_J (x
) ? 0 : COSTS_N_INSNS (1);
5195 if (satisfies_constraint_I (x
))
5197 else if (satisfies_constraint_J (x
))
5200 *total
= COSTS_N_INSNS (1);
5203 if (satisfies_constraint_K (x
) || satisfies_constraint_L (x
))
5206 *total
= COSTS_N_INSNS (1);
5211 *total
= COSTS_N_INSNS (1);
5217 *total
= COSTS_N_INSNS (3);
5221 /* For multiplies wider than HImode, we have to go to the FPU,
5222 which normally involves copies. Plus there's the latency
5223 of the multiply itself, and the latency of the instructions to
5224 transfer integer regs to FP regs. */
5225 /* ??? Check for FP mode. */
5226 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
5227 *total
= COSTS_N_INSNS (10);
5229 *total
= COSTS_N_INSNS (2);
5237 *total
= COSTS_N_INSNS (1);
5244 /* We make divide expensive, so that divide-by-constant will be
5245 optimized to a multiply. */
5246 *total
= COSTS_N_INSNS (60);
5254 /* Calculate the cost of moving data from a register in class FROM to
5255 one in class TO, using MODE. */
5258 ia64_register_move_cost (enum machine_mode mode
, reg_class_t from_i
,
5261 enum reg_class from
= (enum reg_class
) from_i
;
5262 enum reg_class to
= (enum reg_class
) to_i
;
5264 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5265 if (to
== ADDL_REGS
)
5267 if (from
== ADDL_REGS
)
5270 /* All costs are symmetric, so reduce cases by putting the
5271 lower number class as the destination. */
5274 enum reg_class tmp
= to
;
5275 to
= from
, from
= tmp
;
5278 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5279 so that we get secondary memory reloads. Between FR_REGS,
5280 we have to make this at least as expensive as memory_move_cost
5281 to avoid spectacularly poor register class preferencing. */
5282 if (mode
== XFmode
|| mode
== RFmode
)
5284 if (to
!= GR_REGS
|| from
!= GR_REGS
)
5285 return memory_move_cost (mode
, to
, false);
5293 /* Moving between PR registers takes two insns. */
5294 if (from
== PR_REGS
)
5296 /* Moving between PR and anything but GR is impossible. */
5297 if (from
!= GR_REGS
)
5298 return memory_move_cost (mode
, to
, false);
5302 /* Moving between BR and anything but GR is impossible. */
5303 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
5304 return memory_move_cost (mode
, to
, false);
5309 /* Moving between AR and anything but GR is impossible. */
5310 if (from
!= GR_REGS
)
5311 return memory_move_cost (mode
, to
, false);
5317 case GR_AND_FR_REGS
:
5318 case GR_AND_BR_REGS
:
5329 /* Calculate the cost of moving data of MODE from a register to or from
5333 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
5335 bool in ATTRIBUTE_UNUSED
)
5337 if (rclass
== GENERAL_REGS
5338 || rclass
== FR_REGS
5339 || rclass
== FP_REGS
5340 || rclass
== GR_AND_FR_REGS
)
5346 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on RCLASS
5347 to use when copying X into that class. */
5350 ia64_preferred_reload_class (rtx x
, enum reg_class rclass
)
5356 /* Don't allow volatile mem reloads into floating point registers.
5357 This is defined to force reload to choose the r/m case instead
5358 of the f/f case when reloading (set (reg fX) (mem/v)). */
5359 if (MEM_P (x
) && MEM_VOLATILE_P (x
))
5362 /* Force all unrecognized constants into the constant pool. */
5380 /* This function returns the register class required for a secondary
5381 register when copying between one of the registers in RCLASS, and X,
5382 using MODE. A return value of NO_REGS means that no secondary register
5386 ia64_secondary_reload_class (enum reg_class rclass
,
5387 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
5391 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5392 regno
= true_regnum (x
);
5399 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5400 interaction. We end up with two pseudos with overlapping lifetimes
5401 both of which are equiv to the same constant, and both which need
5402 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5403 changes depending on the path length, which means the qty_first_reg
5404 check in make_regs_eqv can give different answers at different times.
5405 At some point I'll probably need a reload_indi pattern to handle
5408 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5409 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5410 non-general registers for good measure. */
5411 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
5414 /* This is needed if a pseudo used as a call_operand gets spilled to a
5416 if (GET_CODE (x
) == MEM
)
5422 /* Need to go through general registers to get to other class regs. */
5423 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
5426 /* This can happen when a paradoxical subreg is an operand to the
5428 /* ??? This shouldn't be necessary after instruction scheduling is
5429 enabled, because paradoxical subregs are not accepted by
5430 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5431 stop the paradoxical subreg stupidity in the *_operand functions
5433 if (GET_CODE (x
) == MEM
5434 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
5435 || GET_MODE (x
) == QImode
))
5438 /* This can happen because of the ior/and/etc patterns that accept FP
5439 registers as operands. If the third operand is a constant, then it
5440 needs to be reloaded into a FP register. */
5441 if (GET_CODE (x
) == CONST_INT
)
5444 /* This can happen because of register elimination in a muldi3 insn.
5445 E.g. `26107 * (unsigned long)&u'. */
5446 if (GET_CODE (x
) == PLUS
)
5451 /* ??? This happens if we cse/gcse a BImode value across a call,
5452 and the function has a nonlocal goto. This is because global
5453 does not allocate call crossing pseudos to hard registers when
5454 crtl->has_nonlocal_goto is true. This is relatively
5455 common for C++ programs that use exceptions. To reproduce,
5456 return NO_REGS and compile libstdc++. */
5457 if (GET_CODE (x
) == MEM
)
5460 /* This can happen when we take a BImode subreg of a DImode value,
5461 and that DImode value winds up in some non-GR register. */
5462 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
5474 /* Implement targetm.unspec_may_trap_p hook. */
5476 ia64_unspec_may_trap_p (const_rtx x
, unsigned flags
)
5478 if (GET_CODE (x
) == UNSPEC
)
5480 switch (XINT (x
, 1))
5486 case UNSPEC_CHKACLR
:
5488 /* These unspecs are just wrappers. */
5489 return may_trap_p_1 (XVECEXP (x
, 0, 0), flags
);
5493 return default_unspec_may_trap_p (x
, flags
);
5497 /* Parse the -mfixed-range= option string. */
5500 fix_range (const char *const_str
)
5503 char *str
, *dash
, *comma
;
5505 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5506 REG2 are either register names or register numbers. The effect
5507 of this option is to mark the registers in the range from REG1 to
5508 REG2 as ``fixed'' so they won't be used by the compiler. This is
5509 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5511 i
= strlen (const_str
);
5512 str
= (char *) alloca (i
+ 1);
5513 memcpy (str
, const_str
, i
+ 1);
5517 dash
= strchr (str
, '-');
5520 warning (0, "value of -mfixed-range must have form REG1-REG2");
5525 comma
= strchr (dash
+ 1, ',');
5529 first
= decode_reg_name (str
);
5532 warning (0, "unknown register name: %s", str
);
5536 last
= decode_reg_name (dash
+ 1);
5539 warning (0, "unknown register name: %s", dash
+ 1);
5547 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
5551 for (i
= first
; i
<= last
; ++i
)
5552 fixed_regs
[i
] = call_used_regs
[i
] = 1;
5562 /* Implement TARGET_HANDLE_OPTION. */
5565 ia64_handle_option (size_t code
, const char *arg
, int value
)
5569 case OPT_mfixed_range_
:
5573 case OPT_mtls_size_
:
5574 if (value
!= 14 && value
!= 22 && value
!= 64)
5575 error ("bad value %<%s%> for -mtls-size= switch", arg
);
5582 const char *name
; /* processor name or nickname. */
5583 enum processor_type processor
;
5585 const processor_alias_table
[] =
5587 {"itanium2", PROCESSOR_ITANIUM2
},
5588 {"mckinley", PROCESSOR_ITANIUM2
},
5590 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
5593 for (i
= 0; i
< pta_size
; i
++)
5594 if (!strcmp (arg
, processor_alias_table
[i
].name
))
5596 ia64_tune
= processor_alias_table
[i
].processor
;
5600 error ("bad value %<%s%> for -mtune= switch", arg
);
5609 /* Implement TARGET_OPTION_OVERRIDE. */
5612 ia64_option_override (void)
5614 if (TARGET_AUTO_PIC
)
5615 target_flags
|= MASK_CONST_GP
;
5617 /* Numerous experiment shows that IRA based loop pressure
5618 calculation works better for RTL loop invariant motion on targets
5619 with enough (>= 32) registers. It is an expensive optimization.
5620 So it is on only for peak performance. */
5622 flag_ira_loop_pressure
= 1;
5625 ia64_section_threshold
= (global_options_set
.x_g_switch_value
5627 : IA64_DEFAULT_GVALUE
);
5629 init_machine_status
= ia64_init_machine_status
;
5631 if (align_functions
<= 0)
5632 align_functions
= 64;
5633 if (align_loops
<= 0)
5635 if (TARGET_ABI_OPEN_VMS
)
5638 ia64_override_options_after_change();
5641 /* Implement targetm.override_options_after_change. */
5644 ia64_override_options_after_change (void)
5646 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
5647 flag_schedule_insns_after_reload
= 0;
5650 && !global_options_set
.x_flag_selective_scheduling
5651 && !global_options_set
.x_flag_selective_scheduling2
)
5653 flag_selective_scheduling2
= 1;
5654 flag_sel_sched_pipelining
= 1;
5656 if (mflag_sched_control_spec
== 2)
5658 /* Control speculation is on by default for the selective scheduler,
5659 but not for the Haifa scheduler. */
5660 mflag_sched_control_spec
= flag_selective_scheduling2
? 1 : 0;
5662 if (flag_sel_sched_pipelining
&& flag_auto_inc_dec
)
5664 /* FIXME: remove this when we'd implement breaking autoinsns as
5665 a transformation. */
5666 flag_auto_inc_dec
= 0;
5670 /* Initialize the record of emitted frame related registers. */
5672 void ia64_init_expanders (void)
5674 memset (&emitted_frame_related_regs
, 0, sizeof (emitted_frame_related_regs
));
5677 static struct machine_function
*
5678 ia64_init_machine_status (void)
5680 return ggc_alloc_cleared_machine_function ();
5683 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
5684 static enum attr_type
ia64_safe_type (rtx
);
5686 static enum attr_itanium_class
5687 ia64_safe_itanium_class (rtx insn
)
5689 if (recog_memoized (insn
) >= 0)
5690 return get_attr_itanium_class (insn
);
5691 else if (DEBUG_INSN_P (insn
))
5692 return ITANIUM_CLASS_IGNORE
;
5694 return ITANIUM_CLASS_UNKNOWN
;
5697 static enum attr_type
5698 ia64_safe_type (rtx insn
)
5700 if (recog_memoized (insn
) >= 0)
5701 return get_attr_type (insn
);
5703 return TYPE_UNKNOWN
;
5706 /* The following collection of routines emit instruction group stop bits as
5707 necessary to avoid dependencies. */
5709 /* Need to track some additional registers as far as serialization is
5710 concerned so we can properly handle br.call and br.ret. We could
5711 make these registers visible to gcc, but since these registers are
5712 never explicitly used in gcc generated code, it seems wasteful to
5713 do so (plus it would make the call and return patterns needlessly
5715 #define REG_RP (BR_REG (0))
5716 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5717 /* This is used for volatile asms which may require a stop bit immediately
5718 before and after them. */
5719 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5720 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5721 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5723 /* For each register, we keep track of how it has been written in the
5724 current instruction group.
5726 If a register is written unconditionally (no qualifying predicate),
5727 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5729 If a register is written if its qualifying predicate P is true, we
5730 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5731 may be written again by the complement of P (P^1) and when this happens,
5732 WRITE_COUNT gets set to 2.
5734 The result of this is that whenever an insn attempts to write a register
5735 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5737 If a predicate register is written by a floating-point insn, we set
5738 WRITTEN_BY_FP to true.
5740 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5741 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5743 #if GCC_VERSION >= 4000
5744 #define RWS_FIELD_TYPE __extension__ unsigned short
5746 #define RWS_FIELD_TYPE unsigned int
5748 struct reg_write_state
5750 RWS_FIELD_TYPE write_count
: 2;
5751 RWS_FIELD_TYPE first_pred
: 10;
5752 RWS_FIELD_TYPE written_by_fp
: 1;
5753 RWS_FIELD_TYPE written_by_and
: 1;
5754 RWS_FIELD_TYPE written_by_or
: 1;
5757 /* Cumulative info for the current instruction group. */
5758 struct reg_write_state rws_sum
[NUM_REGS
];
5759 #ifdef ENABLE_CHECKING
5760 /* Bitmap whether a register has been written in the current insn. */
5761 HARD_REG_ELT_TYPE rws_insn
[(NUM_REGS
+ HOST_BITS_PER_WIDEST_FAST_INT
- 1)
5762 / HOST_BITS_PER_WIDEST_FAST_INT
];
5765 rws_insn_set (int regno
)
5767 gcc_assert (!TEST_HARD_REG_BIT (rws_insn
, regno
));
5768 SET_HARD_REG_BIT (rws_insn
, regno
);
5772 rws_insn_test (int regno
)
5774 return TEST_HARD_REG_BIT (rws_insn
, regno
);
5777 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
5778 unsigned char rws_insn
[2];
5781 rws_insn_set (int regno
)
5783 if (regno
== REG_AR_CFM
)
5785 else if (regno
== REG_VOLATILE
)
5790 rws_insn_test (int regno
)
5792 if (regno
== REG_AR_CFM
)
5794 if (regno
== REG_VOLATILE
)
5800 /* Indicates whether this is the first instruction after a stop bit,
5801 in which case we don't need another stop bit. Without this,
5802 ia64_variable_issue will die when scheduling an alloc. */
5803 static int first_instruction
;
5805 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5806 RTL for one instruction. */
5809 unsigned int is_write
: 1; /* Is register being written? */
5810 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
5811 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
5812 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
5813 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
5814 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
5817 static void rws_update (int, struct reg_flags
, int);
5818 static int rws_access_regno (int, struct reg_flags
, int);
5819 static int rws_access_reg (rtx
, struct reg_flags
, int);
5820 static void update_set_flags (rtx
, struct reg_flags
*);
5821 static int set_src_needs_barrier (rtx
, struct reg_flags
, int);
5822 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
5823 static void init_insn_group_barriers (void);
5824 static int group_barrier_needed (rtx
);
5825 static int safe_group_barrier_needed (rtx
);
5826 static int in_safe_group_barrier
;
5828 /* Update *RWS for REGNO, which is being written by the current instruction,
5829 with predicate PRED, and associated register flags in FLAGS. */
5832 rws_update (int regno
, struct reg_flags flags
, int pred
)
5835 rws_sum
[regno
].write_count
++;
5837 rws_sum
[regno
].write_count
= 2;
5838 rws_sum
[regno
].written_by_fp
|= flags
.is_fp
;
5839 /* ??? Not tracking and/or across differing predicates. */
5840 rws_sum
[regno
].written_by_and
= flags
.is_and
;
5841 rws_sum
[regno
].written_by_or
= flags
.is_or
;
5842 rws_sum
[regno
].first_pred
= pred
;
5845 /* Handle an access to register REGNO of type FLAGS using predicate register
5846 PRED. Update rws_sum array. Return 1 if this access creates
5847 a dependency with an earlier instruction in the same group. */
5850 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
5852 int need_barrier
= 0;
5854 gcc_assert (regno
< NUM_REGS
);
5856 if (! PR_REGNO_P (regno
))
5857 flags
.is_and
= flags
.is_or
= 0;
5863 rws_insn_set (regno
);
5864 write_count
= rws_sum
[regno
].write_count
;
5866 switch (write_count
)
5869 /* The register has not been written yet. */
5870 if (!in_safe_group_barrier
)
5871 rws_update (regno
, flags
, pred
);
5875 /* The register has been written via a predicate. If this is
5876 not a complementary predicate, then we need a barrier. */
5877 /* ??? This assumes that P and P+1 are always complementary
5878 predicates for P even. */
5879 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5881 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5883 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5885 if (!in_safe_group_barrier
)
5886 rws_update (regno
, flags
, pred
);
5890 /* The register has been unconditionally written already. We
5892 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5894 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5898 if (!in_safe_group_barrier
)
5900 rws_sum
[regno
].written_by_and
= flags
.is_and
;
5901 rws_sum
[regno
].written_by_or
= flags
.is_or
;
5911 if (flags
.is_branch
)
5913 /* Branches have several RAW exceptions that allow to avoid
5916 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
5917 /* RAW dependencies on branch regs are permissible as long
5918 as the writer is a non-branch instruction. Since we
5919 never generate code that uses a branch register written
5920 by a branch instruction, handling this case is
5924 if (REGNO_REG_CLASS (regno
) == PR_REGS
5925 && ! rws_sum
[regno
].written_by_fp
)
5926 /* The predicates of a branch are available within the
5927 same insn group as long as the predicate was written by
5928 something other than a floating-point instruction. */
5932 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5934 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5937 switch (rws_sum
[regno
].write_count
)
5940 /* The register has not been written yet. */
5944 /* The register has been written via a predicate. If this is
5945 not a complementary predicate, then we need a barrier. */
5946 /* ??? This assumes that P and P+1 are always complementary
5947 predicates for P even. */
5948 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5953 /* The register has been unconditionally written already. We
5963 return need_barrier
;
5967 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
5969 int regno
= REGNO (reg
);
5970 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
5973 return rws_access_regno (regno
, flags
, pred
);
5976 int need_barrier
= 0;
5978 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
5979 return need_barrier
;
5983 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5984 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5987 update_set_flags (rtx x
, struct reg_flags
*pflags
)
5989 rtx src
= SET_SRC (x
);
5991 switch (GET_CODE (src
))
5997 /* There are four cases here:
5998 (1) The destination is (pc), in which case this is a branch,
5999 nothing here applies.
6000 (2) The destination is ar.lc, in which case this is a
6001 doloop_end_internal,
6002 (3) The destination is an fp register, in which case this is
6003 an fselect instruction.
6004 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6005 this is a check load.
6006 In all cases, nothing we do in this function applies. */
6010 if (COMPARISON_P (src
)
6011 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src
, 0))))
6012 /* Set pflags->is_fp to 1 so that we know we're dealing
6013 with a floating point comparison when processing the
6014 destination of the SET. */
6017 /* Discover if this is a parallel comparison. We only handle
6018 and.orcm and or.andcm at present, since we must retain a
6019 strict inverse on the predicate pair. */
6020 else if (GET_CODE (src
) == AND
)
6022 else if (GET_CODE (src
) == IOR
)
6029 /* Subroutine of rtx_needs_barrier; this function determines whether the
6030 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6031 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6035 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6037 int need_barrier
= 0;
6039 rtx src
= SET_SRC (x
);
6041 if (GET_CODE (src
) == CALL
)
6042 /* We don't need to worry about the result registers that
6043 get written by subroutine call. */
6044 return rtx_needs_barrier (src
, flags
, pred
);
6045 else if (SET_DEST (x
) == pc_rtx
)
6047 /* X is a conditional branch. */
6048 /* ??? This seems redundant, as the caller sets this bit for
6050 if (!ia64_spec_check_src_p (src
))
6051 flags
.is_branch
= 1;
6052 return rtx_needs_barrier (src
, flags
, pred
);
6055 if (ia64_spec_check_src_p (src
))
6056 /* Avoid checking one register twice (in condition
6057 and in 'then' section) for ldc pattern. */
6059 gcc_assert (REG_P (XEXP (src
, 2)));
6060 need_barrier
= rtx_needs_barrier (XEXP (src
, 2), flags
, pred
);
6062 /* We process MEM below. */
6063 src
= XEXP (src
, 1);
6066 need_barrier
|= rtx_needs_barrier (src
, flags
, pred
);
6069 if (GET_CODE (dst
) == ZERO_EXTRACT
)
6071 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
6072 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
6074 return need_barrier
;
6077 /* Handle an access to rtx X of type FLAGS using predicate register
6078 PRED. Return 1 if this access creates a dependency with an earlier
6079 instruction in the same group. */
6082 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6085 int is_complemented
= 0;
6086 int need_barrier
= 0;
6087 const char *format_ptr
;
6088 struct reg_flags new_flags
;
6096 switch (GET_CODE (x
))
6099 update_set_flags (x
, &new_flags
);
6100 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
);
6101 if (GET_CODE (SET_SRC (x
)) != CALL
)
6103 new_flags
.is_write
= 1;
6104 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
6109 new_flags
.is_write
= 0;
6110 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6112 /* Avoid multiple register writes, in case this is a pattern with
6113 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6114 if (! flags
.is_sibcall
&& ! rws_insn_test (REG_AR_CFM
))
6116 new_flags
.is_write
= 1;
6117 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
6118 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
6119 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6124 /* X is a predicated instruction. */
6126 cond
= COND_EXEC_TEST (x
);
6128 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
6130 if (GET_CODE (cond
) == EQ
)
6131 is_complemented
= 1;
6132 cond
= XEXP (cond
, 0);
6133 gcc_assert (GET_CODE (cond
) == REG
6134 && REGNO_REG_CLASS (REGNO (cond
)) == PR_REGS
);
6135 pred
= REGNO (cond
);
6136 if (is_complemented
)
6139 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
6140 return need_barrier
;
6144 /* Clobber & use are for earlier compiler-phases only. */
6149 /* We always emit stop bits for traditional asms. We emit stop bits
6150 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6151 if (GET_CODE (x
) != ASM_OPERANDS
6152 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
6154 /* Avoid writing the register multiple times if we have multiple
6155 asm outputs. This avoids a failure in rws_access_reg. */
6156 if (! rws_insn_test (REG_VOLATILE
))
6158 new_flags
.is_write
= 1;
6159 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
6164 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6165 We cannot just fall through here since then we would be confused
6166 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6167 traditional asms unlike their normal usage. */
6169 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
6170 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
6175 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6177 rtx pat
= XVECEXP (x
, 0, i
);
6178 switch (GET_CODE (pat
))
6181 update_set_flags (pat
, &new_flags
);
6182 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
);
6188 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6199 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6201 rtx pat
= XVECEXP (x
, 0, i
);
6202 if (GET_CODE (pat
) == SET
)
6204 if (GET_CODE (SET_SRC (pat
)) != CALL
)
6206 new_flags
.is_write
= 1;
6207 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
6211 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
6212 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6217 need_barrier
|= rtx_needs_barrier (SUBREG_REG (x
), flags
, pred
);
6220 if (REGNO (x
) == AR_UNAT_REGNUM
)
6222 for (i
= 0; i
< 64; ++i
)
6223 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
6226 need_barrier
= rws_access_reg (x
, flags
, pred
);
6230 /* Find the regs used in memory address computation. */
6231 new_flags
.is_write
= 0;
6232 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6235 case CONST_INT
: case CONST_DOUBLE
: case CONST_VECTOR
:
6236 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
6239 /* Operators with side-effects. */
6240 case POST_INC
: case POST_DEC
:
6241 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6243 new_flags
.is_write
= 0;
6244 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6245 new_flags
.is_write
= 1;
6246 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6250 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6252 new_flags
.is_write
= 0;
6253 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6254 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6255 new_flags
.is_write
= 1;
6256 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6259 /* Handle common unary and binary ops for efficiency. */
6260 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
6261 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
6262 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
6263 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
6264 case NE
: case EQ
: case GE
: case GT
: case LE
:
6265 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
6266 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6267 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6270 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
6271 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
6272 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
6273 case SQRT
: case FFS
: case POPCOUNT
:
6274 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6278 /* VEC_SELECT's second argument is a PARALLEL with integers that
6279 describe the elements selected. On ia64, those integers are
6280 always constants. Avoid walking the PARALLEL so that we don't
6281 get confused with "normal" parallels and then die. */
6282 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6286 switch (XINT (x
, 1))
6288 case UNSPEC_LTOFF_DTPMOD
:
6289 case UNSPEC_LTOFF_DTPREL
:
6291 case UNSPEC_LTOFF_TPREL
:
6293 case UNSPEC_PRED_REL_MUTEX
:
6294 case UNSPEC_PIC_CALL
:
6296 case UNSPEC_FETCHADD_ACQ
:
6297 case UNSPEC_BSP_VALUE
:
6298 case UNSPEC_FLUSHRS
:
6299 case UNSPEC_BUNDLE_SELECTOR
:
6302 case UNSPEC_GR_SPILL
:
6303 case UNSPEC_GR_RESTORE
:
6305 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
6306 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
6308 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6309 new_flags
.is_write
= (XINT (x
, 1) == UNSPEC_GR_SPILL
);
6310 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
6315 case UNSPEC_FR_SPILL
:
6316 case UNSPEC_FR_RESTORE
:
6317 case UNSPEC_GETF_EXP
:
6318 case UNSPEC_SETF_EXP
:
6320 case UNSPEC_FR_SQRT_RECIP_APPROX
:
6321 case UNSPEC_FR_SQRT_RECIP_APPROX_RES
:
6326 case UNSPEC_CHKACLR
:
6328 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6331 case UNSPEC_FR_RECIP_APPROX
:
6333 case UNSPEC_COPYSIGN
:
6334 case UNSPEC_FR_RECIP_APPROX_RES
:
6335 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6336 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6339 case UNSPEC_CMPXCHG_ACQ
:
6340 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6341 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
6349 case UNSPEC_VOLATILE
:
6350 switch (XINT (x
, 1))
6353 /* Alloc must always be the first instruction of a group.
6354 We force this by always returning true. */
6355 /* ??? We might get better scheduling if we explicitly check for
6356 input/local/output register dependencies, and modify the
6357 scheduler so that alloc is always reordered to the start of
6358 the current group. We could then eliminate all of the
6359 first_instruction code. */
6360 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6362 new_flags
.is_write
= 1;
6363 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6366 case UNSPECV_SET_BSP
:
6370 case UNSPECV_BLOCKAGE
:
6371 case UNSPECV_INSN_GROUP_BARRIER
:
6373 case UNSPECV_PSAC_ALL
:
6374 case UNSPECV_PSAC_NORMAL
:
6383 new_flags
.is_write
= 0;
6384 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
6385 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6387 new_flags
.is_write
= 1;
6388 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6389 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6393 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
6394 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6395 switch (format_ptr
[i
])
6397 case '0': /* unused field */
6398 case 'i': /* integer */
6399 case 'n': /* note */
6400 case 'w': /* wide integer */
6401 case 's': /* pointer to string */
6402 case 'S': /* optional pointer to string */
6406 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
6411 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
6412 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
6421 return need_barrier
;
6424 /* Clear out the state for group_barrier_needed at the start of a
6425 sequence of insns. */
6428 init_insn_group_barriers (void)
6430 memset (rws_sum
, 0, sizeof (rws_sum
));
6431 first_instruction
= 1;
6434 /* Given the current state, determine whether a group barrier (a stop bit) is
6435 necessary before INSN. Return nonzero if so. This modifies the state to
6436 include the effects of INSN as a side-effect. */
6439 group_barrier_needed (rtx insn
)
6442 int need_barrier
= 0;
6443 struct reg_flags flags
;
6445 memset (&flags
, 0, sizeof (flags
));
6446 switch (GET_CODE (insn
))
6453 /* A barrier doesn't imply an instruction group boundary. */
6457 memset (rws_insn
, 0, sizeof (rws_insn
));
6461 flags
.is_branch
= 1;
6462 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
6463 memset (rws_insn
, 0, sizeof (rws_insn
));
6465 /* Don't bundle a call following another call. */
6466 if ((pat
= prev_active_insn (insn
))
6467 && GET_CODE (pat
) == CALL_INSN
)
6473 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
6477 if (!ia64_spec_check_p (insn
))
6478 flags
.is_branch
= 1;
6480 /* Don't bundle a jump following a call. */
6481 if ((pat
= prev_active_insn (insn
))
6482 && GET_CODE (pat
) == CALL_INSN
)
6490 if (GET_CODE (PATTERN (insn
)) == USE
6491 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6492 /* Don't care about USE and CLOBBER "insns"---those are used to
6493 indicate to the optimizer that it shouldn't get rid of
6494 certain operations. */
6497 pat
= PATTERN (insn
);
6499 /* Ug. Hack hacks hacked elsewhere. */
6500 switch (recog_memoized (insn
))
6502 /* We play dependency tricks with the epilogue in order
6503 to get proper schedules. Undo this for dv analysis. */
6504 case CODE_FOR_epilogue_deallocate_stack
:
6505 case CODE_FOR_prologue_allocate_stack
:
6506 pat
= XVECEXP (pat
, 0, 0);
6509 /* The pattern we use for br.cloop confuses the code above.
6510 The second element of the vector is representative. */
6511 case CODE_FOR_doloop_end_internal
:
6512 pat
= XVECEXP (pat
, 0, 1);
6515 /* Doesn't generate code. */
6516 case CODE_FOR_pred_rel_mutex
:
6517 case CODE_FOR_prologue_use
:
6524 memset (rws_insn
, 0, sizeof (rws_insn
));
6525 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
6527 /* Check to see if the previous instruction was a volatile
6530 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
6538 if (first_instruction
&& INSN_P (insn
)
6539 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6540 && GET_CODE (PATTERN (insn
)) != USE
6541 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6544 first_instruction
= 0;
6547 return need_barrier
;
6550 /* Like group_barrier_needed, but do not clobber the current state. */
6553 safe_group_barrier_needed (rtx insn
)
6555 int saved_first_instruction
;
6558 saved_first_instruction
= first_instruction
;
6559 in_safe_group_barrier
= 1;
6561 t
= group_barrier_needed (insn
);
6563 first_instruction
= saved_first_instruction
;
6564 in_safe_group_barrier
= 0;
6569 /* Scan the current function and insert stop bits as necessary to
6570 eliminate dependencies. This function assumes that a final
6571 instruction scheduling pass has been run which has already
6572 inserted most of the necessary stop bits. This function only
6573 inserts new ones at basic block boundaries, since these are
6574 invisible to the scheduler. */
6577 emit_insn_group_barriers (FILE *dump
)
6581 int insns_since_last_label
= 0;
6583 init_insn_group_barriers ();
6585 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6587 if (GET_CODE (insn
) == CODE_LABEL
)
6589 if (insns_since_last_label
)
6591 insns_since_last_label
= 0;
6593 else if (GET_CODE (insn
) == NOTE
6594 && NOTE_KIND (insn
) == NOTE_INSN_BASIC_BLOCK
)
6596 if (insns_since_last_label
)
6598 insns_since_last_label
= 0;
6600 else if (GET_CODE (insn
) == INSN
6601 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
6602 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
6604 init_insn_group_barriers ();
6607 else if (NONDEBUG_INSN_P (insn
))
6609 insns_since_last_label
= 1;
6611 if (group_barrier_needed (insn
))
6616 fprintf (dump
, "Emitting stop before label %d\n",
6617 INSN_UID (last_label
));
6618 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
6621 init_insn_group_barriers ();
6629 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6630 This function has to emit all necessary group barriers. */
6633 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
6637 init_insn_group_barriers ();
6639 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6641 if (GET_CODE (insn
) == BARRIER
)
6643 rtx last
= prev_active_insn (insn
);
6647 if (GET_CODE (last
) == JUMP_INSN
6648 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
6649 last
= prev_active_insn (last
);
6650 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6651 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
6653 init_insn_group_barriers ();
6655 else if (NONDEBUG_INSN_P (insn
))
6657 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
6658 init_insn_group_barriers ();
6659 else if (group_barrier_needed (insn
))
6661 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
6662 init_insn_group_barriers ();
6663 group_barrier_needed (insn
);
6671 /* Instruction scheduling support. */
6673 #define NR_BUNDLES 10
6675 /* A list of names of all available bundles. */
6677 static const char *bundle_name
[NR_BUNDLES
] =
6683 #if NR_BUNDLES == 10
6693 /* Nonzero if we should insert stop bits into the schedule. */
6695 int ia64_final_schedule
= 0;
6697 /* Codes of the corresponding queried units: */
6699 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
6700 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
6702 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
6703 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
6705 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
6707 /* The following variable value is an insn group barrier. */
6709 static rtx dfa_stop_insn
;
6711 /* The following variable value is the last issued insn. */
6713 static rtx last_scheduled_insn
;
6715 /* The following variable value is pointer to a DFA state used as
6716 temporary variable. */
6718 static state_t temp_dfa_state
= NULL
;
6720 /* The following variable value is DFA state after issuing the last
6723 static state_t prev_cycle_state
= NULL
;
6725 /* The following array element values are TRUE if the corresponding
6726 insn requires to add stop bits before it. */
6728 static char *stops_p
= NULL
;
6730 /* The following variable is used to set up the mentioned above array. */
6732 static int stop_before_p
= 0;
6734 /* The following variable value is length of the arrays `clocks' and
6737 static int clocks_length
;
6739 /* The following variable value is number of data speculations in progress. */
6740 static int pending_data_specs
= 0;
6742 /* Number of memory references on current and three future processor cycles. */
6743 static char mem_ops_in_group
[4];
6745 /* Number of current processor cycle (from scheduler's point of view). */
6746 static int current_cycle
;
6748 static rtx
ia64_single_set (rtx
);
6749 static void ia64_emit_insn_before (rtx
, rtx
);
6751 /* Map a bundle number to its pseudo-op. */
6754 get_bundle_name (int b
)
6756 return bundle_name
[b
];
6760 /* Return the maximum number of instructions a cpu can issue. */
6763 ia64_issue_rate (void)
6768 /* Helper function - like single_set, but look inside COND_EXEC. */
6771 ia64_single_set (rtx insn
)
6773 rtx x
= PATTERN (insn
), ret
;
6774 if (GET_CODE (x
) == COND_EXEC
)
6775 x
= COND_EXEC_CODE (x
);
6776 if (GET_CODE (x
) == SET
)
6779 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6780 Although they are not classical single set, the second set is there just
6781 to protect it from moving past FP-relative stack accesses. */
6782 switch (recog_memoized (insn
))
6784 case CODE_FOR_prologue_allocate_stack
:
6785 case CODE_FOR_epilogue_deallocate_stack
:
6786 ret
= XVECEXP (x
, 0, 0);
6790 ret
= single_set_2 (insn
, x
);
6797 /* Adjust the cost of a scheduling dependency.
6798 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6799 COST is the current cost, DW is dependency weakness. */
6801 ia64_adjust_cost_2 (rtx insn
, int dep_type1
, rtx dep_insn
, int cost
, dw_t dw
)
6803 enum reg_note dep_type
= (enum reg_note
) dep_type1
;
6804 enum attr_itanium_class dep_class
;
6805 enum attr_itanium_class insn_class
;
6807 insn_class
= ia64_safe_itanium_class (insn
);
6808 dep_class
= ia64_safe_itanium_class (dep_insn
);
6810 /* Treat true memory dependencies separately. Ignore apparent true
6811 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
6812 if (dep_type
== REG_DEP_TRUE
6813 && (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
)
6814 && (insn_class
== ITANIUM_CLASS_BR
|| insn_class
== ITANIUM_CLASS_SCALL
))
6817 if (dw
== MIN_DEP_WEAK
)
6818 /* Store and load are likely to alias, use higher cost to avoid stall. */
6819 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST
);
6820 else if (dw
> MIN_DEP_WEAK
)
6822 /* Store and load are less likely to alias. */
6823 if (mflag_sched_fp_mem_deps_zero_cost
&& dep_class
== ITANIUM_CLASS_STF
)
6824 /* Assume there will be no cache conflict for floating-point data.
6825 For integer data, L1 conflict penalty is huge (17 cycles), so we
6826 never assume it will not cause a conflict. */
6832 if (dep_type
!= REG_DEP_OUTPUT
)
6835 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
6836 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
6842 /* Like emit_insn_before, but skip cycle_display notes.
6843 ??? When cycle display notes are implemented, update this. */
6846 ia64_emit_insn_before (rtx insn
, rtx before
)
6848 emit_insn_before (insn
, before
);
6851 /* The following function marks insns who produce addresses for load
6852 and store insns. Such insns will be placed into M slots because it
6853 decrease latency time for Itanium1 (see function
6854 `ia64_produce_address_p' and the DFA descriptions). */
6857 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
6859 rtx insn
, next
, next_tail
;
6861 /* Before reload, which_alternative is not set, which means that
6862 ia64_safe_itanium_class will produce wrong results for (at least)
6863 move instructions. */
6864 if (!reload_completed
)
6867 next_tail
= NEXT_INSN (tail
);
6868 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6871 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6873 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
6875 sd_iterator_def sd_it
;
6877 bool has_mem_op_consumer_p
= false;
6879 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
6881 enum attr_itanium_class c
;
6883 if (DEP_TYPE (dep
) != REG_DEP_TRUE
)
6886 next
= DEP_CON (dep
);
6887 c
= ia64_safe_itanium_class (next
);
6888 if ((c
== ITANIUM_CLASS_ST
6889 || c
== ITANIUM_CLASS_STF
)
6890 && ia64_st_address_bypass_p (insn
, next
))
6892 has_mem_op_consumer_p
= true;
6895 else if ((c
== ITANIUM_CLASS_LD
6896 || c
== ITANIUM_CLASS_FLD
6897 || c
== ITANIUM_CLASS_FLDP
)
6898 && ia64_ld_address_bypass_p (insn
, next
))
6900 has_mem_op_consumer_p
= true;
6905 insn
->call
= has_mem_op_consumer_p
;
6909 /* We're beginning a new block. Initialize data structures as necessary. */
6912 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
6913 int sched_verbose ATTRIBUTE_UNUSED
,
6914 int max_ready ATTRIBUTE_UNUSED
)
6916 #ifdef ENABLE_CHECKING
6919 if (!sel_sched_p () && reload_completed
)
6920 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
6921 insn
!= current_sched_info
->next_tail
;
6922 insn
= NEXT_INSN (insn
))
6923 gcc_assert (!SCHED_GROUP_P (insn
));
6925 last_scheduled_insn
= NULL_RTX
;
6926 init_insn_group_barriers ();
6929 memset (mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
6932 /* We're beginning a scheduling pass. Check assertion. */
6935 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED
,
6936 int sched_verbose ATTRIBUTE_UNUSED
,
6937 int max_ready ATTRIBUTE_UNUSED
)
6939 gcc_assert (pending_data_specs
== 0);
6942 /* Scheduling pass is now finished. Free/reset static variable. */
6944 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6945 int sched_verbose ATTRIBUTE_UNUSED
)
6947 gcc_assert (pending_data_specs
== 0);
6950 /* Return TRUE if INSN is a load (either normal or speculative, but not a
6951 speculation check), FALSE otherwise. */
6953 is_load_p (rtx insn
)
6955 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
6958 ((insn_class
== ITANIUM_CLASS_LD
|| insn_class
== ITANIUM_CLASS_FLD
)
6959 && get_attr_check_load (insn
) == CHECK_LOAD_NO
);
6962 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
6963 (taking account for 3-cycle cache reference postponing for stores: Intel
6964 Itanium 2 Reference Manual for Software Development and Optimization,
6967 record_memory_reference (rtx insn
)
6969 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
6971 switch (insn_class
) {
6972 case ITANIUM_CLASS_FLD
:
6973 case ITANIUM_CLASS_LD
:
6974 mem_ops_in_group
[current_cycle
% 4]++;
6976 case ITANIUM_CLASS_STF
:
6977 case ITANIUM_CLASS_ST
:
6978 mem_ops_in_group
[(current_cycle
+ 3) % 4]++;
6984 /* We are about to being issuing insns for this clock cycle.
6985 Override the default sort algorithm to better slot instructions. */
6988 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
6989 int *pn_ready
, int clock_var
,
6993 int n_ready
= *pn_ready
;
6994 rtx
*e_ready
= ready
+ n_ready
;
6998 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
7000 if (reorder_type
== 0)
7002 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7004 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7005 if (insnp
< e_ready
)
7008 enum attr_type t
= ia64_safe_type (insn
);
7009 if (t
== TYPE_UNKNOWN
)
7011 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
7012 || asm_noperands (PATTERN (insn
)) >= 0)
7014 rtx lowest
= ready
[n_asms
];
7015 ready
[n_asms
] = insn
;
7021 rtx highest
= ready
[n_ready
- 1];
7022 ready
[n_ready
- 1] = insn
;
7029 if (n_asms
< n_ready
)
7031 /* Some normal insns to process. Skip the asms. */
7035 else if (n_ready
> 0)
7039 if (ia64_final_schedule
)
7042 int nr_need_stop
= 0;
7044 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7045 if (safe_group_barrier_needed (*insnp
))
7048 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
7050 if (reorder_type
== 0)
7053 /* Move down everything that needs a stop bit, preserving
7055 while (insnp
-- > ready
+ deleted
)
7056 while (insnp
>= ready
+ deleted
)
7059 if (! safe_group_barrier_needed (insn
))
7061 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7069 current_cycle
= clock_var
;
7070 if (reload_completed
&& mem_ops_in_group
[clock_var
% 4] >= ia64_max_memory_insns
)
7075 /* Move down loads/stores, preserving relative order. */
7076 while (insnp
-- > ready
+ moved
)
7077 while (insnp
>= ready
+ moved
)
7080 if (! is_load_p (insn
))
7082 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7093 /* We are about to being issuing insns for this clock cycle. Override
7094 the default sort algorithm to better slot instructions. */
7097 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
7100 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
7101 pn_ready
, clock_var
, 0);
7104 /* Like ia64_sched_reorder, but called after issuing each insn.
7105 Override the default sort algorithm to better slot instructions. */
7108 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
7109 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
7110 int *pn_ready
, int clock_var
)
7112 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
7116 /* We are about to issue INSN. Return the number of insns left on the
7117 ready queue that can be issued this cycle. */
7120 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
7121 int sched_verbose ATTRIBUTE_UNUSED
,
7122 rtx insn ATTRIBUTE_UNUSED
,
7123 int can_issue_more ATTRIBUTE_UNUSED
)
7125 if (sched_deps_info
->generate_spec_deps
&& !sel_sched_p ())
7126 /* Modulo scheduling does not extend h_i_d when emitting
7127 new instructions. Don't use h_i_d, if we don't have to. */
7129 if (DONE_SPEC (insn
) & BEGIN_DATA
)
7130 pending_data_specs
++;
7131 if (CHECK_SPEC (insn
) & BEGIN_DATA
)
7132 pending_data_specs
--;
7135 if (DEBUG_INSN_P (insn
))
7138 last_scheduled_insn
= insn
;
7139 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
7140 if (reload_completed
)
7142 int needed
= group_barrier_needed (insn
);
7144 gcc_assert (!needed
);
7145 if (GET_CODE (insn
) == CALL_INSN
)
7146 init_insn_group_barriers ();
7147 stops_p
[INSN_UID (insn
)] = stop_before_p
;
7150 record_memory_reference (insn
);
7155 /* We are choosing insn from the ready queue. Return nonzero if INSN
7159 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
7161 gcc_assert (insn
&& INSN_P (insn
));
7162 return ((!reload_completed
7163 || !safe_group_barrier_needed (insn
))
7164 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn
)
7165 && (!mflag_sched_mem_insns_hard_limit
7166 || !is_load_p (insn
)
7167 || mem_ops_in_group
[current_cycle
% 4] < ia64_max_memory_insns
));
7170 /* We are choosing insn from the ready queue. Return nonzero if INSN
7174 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn
)
7176 gcc_assert (insn
&& INSN_P (insn
));
7177 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7178 we keep ALAT half-empty. */
7179 return (pending_data_specs
< 16
7180 || !(TODO_SPEC (insn
) & BEGIN_DATA
));
7183 /* The following variable value is pseudo-insn used by the DFA insn
7184 scheduler to change the DFA state when the simulated clock is
7187 static rtx dfa_pre_cycle_insn
;
7189 /* Returns 1 when a meaningful insn was scheduled between the last group
7190 barrier and LAST. */
7192 scheduled_good_insn (rtx last
)
7194 if (last
&& recog_memoized (last
) >= 0)
7198 last
!= NULL
&& !NOTE_INSN_BASIC_BLOCK_P (last
)
7199 && !stops_p
[INSN_UID (last
)];
7200 last
= PREV_INSN (last
))
7201 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7202 the ebb we're scheduling. */
7203 if (INSN_P (last
) && recog_memoized (last
) >= 0)
7209 /* We are about to being issuing INSN. Return nonzero if we cannot
7210 issue it on given cycle CLOCK and return zero if we should not sort
7211 the ready queue on the next clock start. */
7214 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
7215 int clock
, int *sort_p
)
7217 gcc_assert (insn
&& INSN_P (insn
));
7219 if (DEBUG_INSN_P (insn
))
7222 /* When a group barrier is needed for insn, last_scheduled_insn
7224 gcc_assert (!(reload_completed
&& safe_group_barrier_needed (insn
))
7225 || last_scheduled_insn
);
7227 if ((reload_completed
7228 && (safe_group_barrier_needed (insn
)
7229 || (mflag_sched_stop_bits_after_every_cycle
7230 && last_clock
!= clock
7231 && last_scheduled_insn
7232 && scheduled_good_insn (last_scheduled_insn
))))
7233 || (last_scheduled_insn
7234 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
7235 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
7236 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
7238 init_insn_group_barriers ();
7240 if (verbose
&& dump
)
7241 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
7242 last_clock
== clock
? " + cycle advance" : "");
7245 current_cycle
= clock
;
7246 mem_ops_in_group
[current_cycle
% 4] = 0;
7248 if (last_clock
== clock
)
7250 state_transition (curr_state
, dfa_stop_insn
);
7251 if (TARGET_EARLY_STOP_BITS
)
7252 *sort_p
= (last_scheduled_insn
== NULL_RTX
7253 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
7259 if (last_scheduled_insn
)
7261 if (GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
7262 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)
7263 state_reset (curr_state
);
7266 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
7267 state_transition (curr_state
, dfa_stop_insn
);
7268 state_transition (curr_state
, dfa_pre_cycle_insn
);
7269 state_transition (curr_state
, NULL
);
7276 /* Implement targetm.sched.h_i_d_extended hook.
7277 Extend internal data structures. */
7279 ia64_h_i_d_extended (void)
7281 if (stops_p
!= NULL
)
7283 int new_clocks_length
= get_max_uid () * 3 / 2;
7284 stops_p
= (char *) xrecalloc (stops_p
, new_clocks_length
, clocks_length
, 1);
7285 clocks_length
= new_clocks_length
;
7290 /* This structure describes the data used by the backend to guide scheduling.
7291 When the current scheduling point is switched, this data should be saved
7292 and restored later, if the scheduler returns to this point. */
7293 struct _ia64_sched_context
7295 state_t prev_cycle_state
;
7296 rtx last_scheduled_insn
;
7297 struct reg_write_state rws_sum
[NUM_REGS
];
7298 struct reg_write_state rws_insn
[NUM_REGS
];
7299 int first_instruction
;
7300 int pending_data_specs
;
7302 char mem_ops_in_group
[4];
7304 typedef struct _ia64_sched_context
*ia64_sched_context_t
;
7306 /* Allocates a scheduling context. */
7308 ia64_alloc_sched_context (void)
7310 return xmalloc (sizeof (struct _ia64_sched_context
));
7313 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7314 the global context otherwise. */
7316 ia64_init_sched_context (void *_sc
, bool clean_p
)
7318 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7320 sc
->prev_cycle_state
= xmalloc (dfa_state_size
);
7323 state_reset (sc
->prev_cycle_state
);
7324 sc
->last_scheduled_insn
= NULL_RTX
;
7325 memset (sc
->rws_sum
, 0, sizeof (rws_sum
));
7326 memset (sc
->rws_insn
, 0, sizeof (rws_insn
));
7327 sc
->first_instruction
= 1;
7328 sc
->pending_data_specs
= 0;
7329 sc
->current_cycle
= 0;
7330 memset (sc
->mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7334 memcpy (sc
->prev_cycle_state
, prev_cycle_state
, dfa_state_size
);
7335 sc
->last_scheduled_insn
= last_scheduled_insn
;
7336 memcpy (sc
->rws_sum
, rws_sum
, sizeof (rws_sum
));
7337 memcpy (sc
->rws_insn
, rws_insn
, sizeof (rws_insn
));
7338 sc
->first_instruction
= first_instruction
;
7339 sc
->pending_data_specs
= pending_data_specs
;
7340 sc
->current_cycle
= current_cycle
;
7341 memcpy (sc
->mem_ops_in_group
, mem_ops_in_group
, sizeof (mem_ops_in_group
));
7345 /* Sets the global scheduling context to the one pointed to by _SC. */
7347 ia64_set_sched_context (void *_sc
)
7349 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7351 gcc_assert (sc
!= NULL
);
7353 memcpy (prev_cycle_state
, sc
->prev_cycle_state
, dfa_state_size
);
7354 last_scheduled_insn
= sc
->last_scheduled_insn
;
7355 memcpy (rws_sum
, sc
->rws_sum
, sizeof (rws_sum
));
7356 memcpy (rws_insn
, sc
->rws_insn
, sizeof (rws_insn
));
7357 first_instruction
= sc
->first_instruction
;
7358 pending_data_specs
= sc
->pending_data_specs
;
7359 current_cycle
= sc
->current_cycle
;
7360 memcpy (mem_ops_in_group
, sc
->mem_ops_in_group
, sizeof (mem_ops_in_group
));
7363 /* Clears the data in the _SC scheduling context. */
7365 ia64_clear_sched_context (void *_sc
)
7367 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7369 free (sc
->prev_cycle_state
);
7370 sc
->prev_cycle_state
= NULL
;
7373 /* Frees the _SC scheduling context. */
7375 ia64_free_sched_context (void *_sc
)
7377 gcc_assert (_sc
!= NULL
);
7382 typedef rtx (* gen_func_t
) (rtx
, rtx
);
7384 /* Return a function that will generate a load of mode MODE_NO
7385 with speculation types TS. */
7387 get_spec_load_gen_function (ds_t ts
, int mode_no
)
7389 static gen_func_t gen_ld_
[] = {
7399 gen_zero_extendqidi2
,
7400 gen_zero_extendhidi2
,
7401 gen_zero_extendsidi2
,
7404 static gen_func_t gen_ld_a
[] = {
7414 gen_zero_extendqidi2_advanced
,
7415 gen_zero_extendhidi2_advanced
,
7416 gen_zero_extendsidi2_advanced
,
7418 static gen_func_t gen_ld_s
[] = {
7419 gen_movbi_speculative
,
7420 gen_movqi_speculative
,
7421 gen_movhi_speculative
,
7422 gen_movsi_speculative
,
7423 gen_movdi_speculative
,
7424 gen_movsf_speculative
,
7425 gen_movdf_speculative
,
7426 gen_movxf_speculative
,
7427 gen_movti_speculative
,
7428 gen_zero_extendqidi2_speculative
,
7429 gen_zero_extendhidi2_speculative
,
7430 gen_zero_extendsidi2_speculative
,
7432 static gen_func_t gen_ld_sa
[] = {
7433 gen_movbi_speculative_advanced
,
7434 gen_movqi_speculative_advanced
,
7435 gen_movhi_speculative_advanced
,
7436 gen_movsi_speculative_advanced
,
7437 gen_movdi_speculative_advanced
,
7438 gen_movsf_speculative_advanced
,
7439 gen_movdf_speculative_advanced
,
7440 gen_movxf_speculative_advanced
,
7441 gen_movti_speculative_advanced
,
7442 gen_zero_extendqidi2_speculative_advanced
,
7443 gen_zero_extendhidi2_speculative_advanced
,
7444 gen_zero_extendsidi2_speculative_advanced
,
7446 static gen_func_t gen_ld_s_a
[] = {
7447 gen_movbi_speculative_a
,
7448 gen_movqi_speculative_a
,
7449 gen_movhi_speculative_a
,
7450 gen_movsi_speculative_a
,
7451 gen_movdi_speculative_a
,
7452 gen_movsf_speculative_a
,
7453 gen_movdf_speculative_a
,
7454 gen_movxf_speculative_a
,
7455 gen_movti_speculative_a
,
7456 gen_zero_extendqidi2_speculative_a
,
7457 gen_zero_extendhidi2_speculative_a
,
7458 gen_zero_extendsidi2_speculative_a
,
7463 if (ts
& BEGIN_DATA
)
7465 if (ts
& BEGIN_CONTROL
)
7470 else if (ts
& BEGIN_CONTROL
)
7472 if ((spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
)
7473 || ia64_needs_block_p (ts
))
7476 gen_ld
= gen_ld_s_a
;
7483 return gen_ld
[mode_no
];
7486 /* Constants that help mapping 'enum machine_mode' to int. */
7489 SPEC_MODE_INVALID
= -1,
7490 SPEC_MODE_FIRST
= 0,
7491 SPEC_MODE_FOR_EXTEND_FIRST
= 1,
7492 SPEC_MODE_FOR_EXTEND_LAST
= 3,
7498 /* Offset to reach ZERO_EXTEND patterns. */
7499 SPEC_GEN_EXTEND_OFFSET
= SPEC_MODE_LAST
- SPEC_MODE_FOR_EXTEND_FIRST
+ 1
7502 /* Return index of the MODE. */
7504 ia64_mode_to_int (enum machine_mode mode
)
7508 case BImode
: return 0; /* SPEC_MODE_FIRST */
7509 case QImode
: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7510 case HImode
: return 2;
7511 case SImode
: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7512 case DImode
: return 4;
7513 case SFmode
: return 5;
7514 case DFmode
: return 6;
7515 case XFmode
: return 7;
7517 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7518 mentioned in itanium[12].md. Predicate fp_register_operand also
7519 needs to be defined. Bottom line: better disable for now. */
7520 return SPEC_MODE_INVALID
;
7521 default: return SPEC_MODE_INVALID
;
7525 /* Provide information about speculation capabilities. */
7527 ia64_set_sched_flags (spec_info_t spec_info
)
7529 unsigned int *flags
= &(current_sched_info
->flags
);
7531 if (*flags
& SCHED_RGN
7532 || *flags
& SCHED_EBB
7533 || *flags
& SEL_SCHED
)
7537 if ((mflag_sched_br_data_spec
&& !reload_completed
&& optimize
> 0)
7538 || (mflag_sched_ar_data_spec
&& reload_completed
))
7543 && ((mflag_sched_br_in_data_spec
&& !reload_completed
)
7544 || (mflag_sched_ar_in_data_spec
&& reload_completed
)))
7548 if (mflag_sched_control_spec
7550 || reload_completed
))
7552 mask
|= BEGIN_CONTROL
;
7554 if (!sel_sched_p () && mflag_sched_in_control_spec
)
7555 mask
|= BE_IN_CONTROL
;
7558 spec_info
->mask
= mask
;
7562 *flags
|= USE_DEPS_LIST
| DO_SPECULATION
;
7564 if (mask
& BE_IN_SPEC
)
7567 spec_info
->flags
= 0;
7569 if ((mask
& DATA_SPEC
) && mflag_sched_prefer_non_data_spec_insns
)
7570 spec_info
->flags
|= PREFER_NON_DATA_SPEC
;
7572 if (mask
& CONTROL_SPEC
)
7574 if (mflag_sched_prefer_non_control_spec_insns
)
7575 spec_info
->flags
|= PREFER_NON_CONTROL_SPEC
;
7577 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec
)
7578 spec_info
->flags
|= SEL_SCHED_SPEC_DONT_CHECK_CONTROL
;
7581 if (sched_verbose
>= 1)
7582 spec_info
->dump
= sched_dump
;
7584 spec_info
->dump
= 0;
7586 if (mflag_sched_count_spec_in_critical_path
)
7587 spec_info
->flags
|= COUNT_SPEC_IN_CRITICAL_PATH
;
7591 spec_info
->mask
= 0;
7594 /* If INSN is an appropriate load return its mode.
7595 Return -1 otherwise. */
7597 get_mode_no_for_insn (rtx insn
)
7599 rtx reg
, mem
, mode_rtx
;
7603 extract_insn_cached (insn
);
7605 /* We use WHICH_ALTERNATIVE only after reload. This will
7606 guarantee that reload won't touch a speculative insn. */
7608 if (recog_data
.n_operands
!= 2)
7611 reg
= recog_data
.operand
[0];
7612 mem
= recog_data
.operand
[1];
7614 /* We should use MEM's mode since REG's mode in presence of
7615 ZERO_EXTEND will always be DImode. */
7616 if (get_attr_speculable1 (insn
) == SPECULABLE1_YES
)
7617 /* Process non-speculative ld. */
7619 if (!reload_completed
)
7621 /* Do not speculate into regs like ar.lc. */
7622 if (!REG_P (reg
) || AR_REGNO_P (REGNO (reg
)))
7629 rtx mem_reg
= XEXP (mem
, 0);
7631 if (!REG_P (mem_reg
))
7637 else if (get_attr_speculable2 (insn
) == SPECULABLE2_YES
)
7639 gcc_assert (REG_P (reg
) && MEM_P (mem
));
7645 else if (get_attr_data_speculative (insn
) == DATA_SPECULATIVE_YES
7646 || get_attr_control_speculative (insn
) == CONTROL_SPECULATIVE_YES
7647 || get_attr_check_load (insn
) == CHECK_LOAD_YES
)
7648 /* Process speculative ld or ld.c. */
7650 gcc_assert (REG_P (reg
) && MEM_P (mem
));
7655 enum attr_itanium_class attr_class
= get_attr_itanium_class (insn
);
7657 if (attr_class
== ITANIUM_CLASS_CHK_A
7658 || attr_class
== ITANIUM_CLASS_CHK_S_I
7659 || attr_class
== ITANIUM_CLASS_CHK_S_F
)
7666 mode_no
= ia64_mode_to_int (GET_MODE (mode_rtx
));
7668 if (mode_no
== SPEC_MODE_INVALID
)
7671 extend_p
= (GET_MODE (reg
) != GET_MODE (mode_rtx
));
7675 if (!(SPEC_MODE_FOR_EXTEND_FIRST
<= mode_no
7676 && mode_no
<= SPEC_MODE_FOR_EXTEND_LAST
))
7679 mode_no
+= SPEC_GEN_EXTEND_OFFSET
;
7685 /* If X is an unspec part of a speculative load, return its code.
7686 Return -1 otherwise. */
7688 get_spec_unspec_code (const_rtx x
)
7690 if (GET_CODE (x
) != UNSPEC
)
7712 /* Implement skip_rtx_p hook. */
7714 ia64_skip_rtx_p (const_rtx x
)
7716 return get_spec_unspec_code (x
) != -1;
7719 /* If INSN is a speculative load, return its UNSPEC code.
7720 Return -1 otherwise. */
7722 get_insn_spec_code (const_rtx insn
)
7726 pat
= PATTERN (insn
);
7728 if (GET_CODE (pat
) == COND_EXEC
)
7729 pat
= COND_EXEC_CODE (pat
);
7731 if (GET_CODE (pat
) != SET
)
7734 reg
= SET_DEST (pat
);
7738 mem
= SET_SRC (pat
);
7739 if (GET_CODE (mem
) == ZERO_EXTEND
)
7740 mem
= XEXP (mem
, 0);
7742 return get_spec_unspec_code (mem
);
7745 /* If INSN is a speculative load, return a ds with the speculation types.
7746 Otherwise [if INSN is a normal instruction] return 0. */
7748 ia64_get_insn_spec_ds (rtx insn
)
7750 int code
= get_insn_spec_code (insn
);
7759 return BEGIN_CONTROL
;
7762 return BEGIN_DATA
| BEGIN_CONTROL
;
7769 /* If INSN is a speculative load return a ds with the speculation types that
7771 Otherwise [if INSN is a normal instruction] return 0. */
7773 ia64_get_insn_checked_ds (rtx insn
)
7775 int code
= get_insn_spec_code (insn
);
7780 return BEGIN_DATA
| BEGIN_CONTROL
;
7783 return BEGIN_CONTROL
;
7787 return BEGIN_DATA
| BEGIN_CONTROL
;
7794 /* If GEN_P is true, calculate the index of needed speculation check and return
7795 speculative pattern for INSN with speculative mode TS, machine mode
7796 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
7797 If GEN_P is false, just calculate the index of needed speculation check. */
7799 ia64_gen_spec_load (rtx insn
, ds_t ts
, int mode_no
)
7802 gen_func_t gen_load
;
7804 gen_load
= get_spec_load_gen_function (ts
, mode_no
);
7806 new_pat
= gen_load (copy_rtx (recog_data
.operand
[0]),
7807 copy_rtx (recog_data
.operand
[1]));
7809 pat
= PATTERN (insn
);
7810 if (GET_CODE (pat
) == COND_EXEC
)
7811 new_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
7818 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED
,
7819 ds_t ds ATTRIBUTE_UNUSED
)
7824 /* Implement targetm.sched.speculate_insn hook.
7825 Check if the INSN can be TS speculative.
7826 If 'no' - return -1.
7827 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
7828 If current pattern of the INSN already provides TS speculation,
7831 ia64_speculate_insn (rtx insn
, ds_t ts
, rtx
*new_pat
)
7836 gcc_assert (!(ts
& ~SPECULATIVE
));
7838 if (ia64_spec_check_p (insn
))
7841 if ((ts
& BE_IN_SPEC
)
7842 && !insn_can_be_in_speculative_p (insn
, ts
))
7845 mode_no
= get_mode_no_for_insn (insn
);
7847 if (mode_no
!= SPEC_MODE_INVALID
)
7849 if (ia64_get_insn_spec_ds (insn
) == ds_get_speculation_types (ts
))
7854 *new_pat
= ia64_gen_spec_load (insn
, ts
, mode_no
);
7863 /* Return a function that will generate a check for speculation TS with mode
7865 If simple check is needed, pass true for SIMPLE_CHECK_P.
7866 If clearing check is needed, pass true for CLEARING_CHECK_P. */
7868 get_spec_check_gen_function (ds_t ts
, int mode_no
,
7869 bool simple_check_p
, bool clearing_check_p
)
7871 static gen_func_t gen_ld_c_clr
[] = {
7881 gen_zero_extendqidi2_clr
,
7882 gen_zero_extendhidi2_clr
,
7883 gen_zero_extendsidi2_clr
,
7885 static gen_func_t gen_ld_c_nc
[] = {
7895 gen_zero_extendqidi2_nc
,
7896 gen_zero_extendhidi2_nc
,
7897 gen_zero_extendsidi2_nc
,
7899 static gen_func_t gen_chk_a_clr
[] = {
7900 gen_advanced_load_check_clr_bi
,
7901 gen_advanced_load_check_clr_qi
,
7902 gen_advanced_load_check_clr_hi
,
7903 gen_advanced_load_check_clr_si
,
7904 gen_advanced_load_check_clr_di
,
7905 gen_advanced_load_check_clr_sf
,
7906 gen_advanced_load_check_clr_df
,
7907 gen_advanced_load_check_clr_xf
,
7908 gen_advanced_load_check_clr_ti
,
7909 gen_advanced_load_check_clr_di
,
7910 gen_advanced_load_check_clr_di
,
7911 gen_advanced_load_check_clr_di
,
7913 static gen_func_t gen_chk_a_nc
[] = {
7914 gen_advanced_load_check_nc_bi
,
7915 gen_advanced_load_check_nc_qi
,
7916 gen_advanced_load_check_nc_hi
,
7917 gen_advanced_load_check_nc_si
,
7918 gen_advanced_load_check_nc_di
,
7919 gen_advanced_load_check_nc_sf
,
7920 gen_advanced_load_check_nc_df
,
7921 gen_advanced_load_check_nc_xf
,
7922 gen_advanced_load_check_nc_ti
,
7923 gen_advanced_load_check_nc_di
,
7924 gen_advanced_load_check_nc_di
,
7925 gen_advanced_load_check_nc_di
,
7927 static gen_func_t gen_chk_s
[] = {
7928 gen_speculation_check_bi
,
7929 gen_speculation_check_qi
,
7930 gen_speculation_check_hi
,
7931 gen_speculation_check_si
,
7932 gen_speculation_check_di
,
7933 gen_speculation_check_sf
,
7934 gen_speculation_check_df
,
7935 gen_speculation_check_xf
,
7936 gen_speculation_check_ti
,
7937 gen_speculation_check_di
,
7938 gen_speculation_check_di
,
7939 gen_speculation_check_di
,
7942 gen_func_t
*gen_check
;
7944 if (ts
& BEGIN_DATA
)
7946 /* We don't need recovery because even if this is ld.sa
7947 ALAT entry will be allocated only if NAT bit is set to zero.
7948 So it is enough to use ld.c here. */
7952 gcc_assert (mflag_sched_spec_ldc
);
7954 if (clearing_check_p
)
7955 gen_check
= gen_ld_c_clr
;
7957 gen_check
= gen_ld_c_nc
;
7961 if (clearing_check_p
)
7962 gen_check
= gen_chk_a_clr
;
7964 gen_check
= gen_chk_a_nc
;
7967 else if (ts
& BEGIN_CONTROL
)
7970 /* We might want to use ld.sa -> ld.c instead of
7973 gcc_assert (!ia64_needs_block_p (ts
));
7975 if (clearing_check_p
)
7976 gen_check
= gen_ld_c_clr
;
7978 gen_check
= gen_ld_c_nc
;
7982 gen_check
= gen_chk_s
;
7988 gcc_assert (mode_no
>= 0);
7989 return gen_check
[mode_no
];
7992 /* Return nonzero, if INSN needs branchy recovery check. */
7994 ia64_needs_block_p (ds_t ts
)
7996 if (ts
& BEGIN_DATA
)
7997 return !mflag_sched_spec_ldc
;
7999 gcc_assert ((ts
& BEGIN_CONTROL
) != 0);
8001 return !(mflag_sched_spec_control_ldc
&& mflag_sched_spec_ldc
);
8004 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
8005 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
8006 Otherwise, generate a simple check. */
8008 ia64_gen_spec_check (rtx insn
, rtx label
, ds_t ds
)
8010 rtx op1
, pat
, check_pat
;
8011 gen_func_t gen_check
;
8014 mode_no
= get_mode_no_for_insn (insn
);
8015 gcc_assert (mode_no
>= 0);
8021 gcc_assert (!ia64_needs_block_p (ds
));
8022 op1
= copy_rtx (recog_data
.operand
[1]);
8025 gen_check
= get_spec_check_gen_function (ds
, mode_no
, label
== NULL_RTX
,
8028 check_pat
= gen_check (copy_rtx (recog_data
.operand
[0]), op1
);
8030 pat
= PATTERN (insn
);
8031 if (GET_CODE (pat
) == COND_EXEC
)
8032 check_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8038 /* Return nonzero, if X is branchy recovery check. */
8040 ia64_spec_check_p (rtx x
)
8043 if (GET_CODE (x
) == COND_EXEC
)
8044 x
= COND_EXEC_CODE (x
);
8045 if (GET_CODE (x
) == SET
)
8046 return ia64_spec_check_src_p (SET_SRC (x
));
8050 /* Return nonzero, if SRC belongs to recovery check. */
8052 ia64_spec_check_src_p (rtx src
)
8054 if (GET_CODE (src
) == IF_THEN_ELSE
)
8059 if (GET_CODE (t
) == NE
)
8063 if (GET_CODE (t
) == UNSPEC
)
8069 if (code
== UNSPEC_LDCCLR
8070 || code
== UNSPEC_LDCNC
8071 || code
== UNSPEC_CHKACLR
8072 || code
== UNSPEC_CHKANC
8073 || code
== UNSPEC_CHKS
)
8075 gcc_assert (code
!= 0);
8085 /* The following page contains abstract data `bundle states' which are
8086 used for bundling insns (inserting nops and template generation). */
8088 /* The following describes state of insn bundling. */
8092 /* Unique bundle state number to identify them in the debugging
8095 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
8096 /* number nops before and after the insn */
8097 short before_nops_num
, after_nops_num
;
8098 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
8100 int cost
; /* cost of the state in cycles */
8101 int accumulated_insns_num
; /* number of all previous insns including
8102 nops. L is considered as 2 insns */
8103 int branch_deviation
; /* deviation of previous branches from 3rd slots */
8104 int middle_bundle_stops
; /* number of stop bits in the middle of bundles */
8105 struct bundle_state
*next
; /* next state with the same insn_num */
8106 struct bundle_state
*originator
; /* originator (previous insn state) */
8107 /* All bundle states are in the following chain. */
8108 struct bundle_state
*allocated_states_chain
;
8109 /* The DFA State after issuing the insn and the nops. */
8113 /* The following is map insn number to the corresponding bundle state. */
8115 static struct bundle_state
**index_to_bundle_states
;
8117 /* The unique number of next bundle state. */
8119 static int bundle_states_num
;
8121 /* All allocated bundle states are in the following chain. */
8123 static struct bundle_state
*allocated_bundle_states_chain
;
8125 /* All allocated but not used bundle states are in the following
8128 static struct bundle_state
*free_bundle_state_chain
;
8131 /* The following function returns a free bundle state. */
8133 static struct bundle_state
*
8134 get_free_bundle_state (void)
8136 struct bundle_state
*result
;
8138 if (free_bundle_state_chain
!= NULL
)
8140 result
= free_bundle_state_chain
;
8141 free_bundle_state_chain
= result
->next
;
8145 result
= XNEW (struct bundle_state
);
8146 result
->dfa_state
= xmalloc (dfa_state_size
);
8147 result
->allocated_states_chain
= allocated_bundle_states_chain
;
8148 allocated_bundle_states_chain
= result
;
8150 result
->unique_num
= bundle_states_num
++;
8155 /* The following function frees given bundle state. */
8158 free_bundle_state (struct bundle_state
*state
)
8160 state
->next
= free_bundle_state_chain
;
8161 free_bundle_state_chain
= state
;
8164 /* Start work with abstract data `bundle states'. */
8167 initiate_bundle_states (void)
8169 bundle_states_num
= 0;
8170 free_bundle_state_chain
= NULL
;
8171 allocated_bundle_states_chain
= NULL
;
8174 /* Finish work with abstract data `bundle states'. */
8177 finish_bundle_states (void)
8179 struct bundle_state
*curr_state
, *next_state
;
8181 for (curr_state
= allocated_bundle_states_chain
;
8183 curr_state
= next_state
)
8185 next_state
= curr_state
->allocated_states_chain
;
8186 free (curr_state
->dfa_state
);
8191 /* Hash table of the bundle states. The key is dfa_state and insn_num
8192 of the bundle states. */
8194 static htab_t bundle_state_table
;
8196 /* The function returns hash of BUNDLE_STATE. */
8199 bundle_state_hash (const void *bundle_state
)
8201 const struct bundle_state
*const state
8202 = (const struct bundle_state
*) bundle_state
;
8205 for (result
= i
= 0; i
< dfa_state_size
; i
++)
8206 result
+= (((unsigned char *) state
->dfa_state
) [i
]
8207 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
8208 return result
+ state
->insn_num
;
8211 /* The function returns nonzero if the bundle state keys are equal. */
8214 bundle_state_eq_p (const void *bundle_state_1
, const void *bundle_state_2
)
8216 const struct bundle_state
*const state1
8217 = (const struct bundle_state
*) bundle_state_1
;
8218 const struct bundle_state
*const state2
8219 = (const struct bundle_state
*) bundle_state_2
;
8221 return (state1
->insn_num
== state2
->insn_num
8222 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
8223 dfa_state_size
) == 0);
8226 /* The function inserts the BUNDLE_STATE into the hash table. The
8227 function returns nonzero if the bundle has been inserted into the
8228 table. The table contains the best bundle state with given key. */
8231 insert_bundle_state (struct bundle_state
*bundle_state
)
8235 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, INSERT
);
8236 if (*entry_ptr
== NULL
)
8238 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
8239 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
8240 *entry_ptr
= (void *) bundle_state
;
8243 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
8244 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
8245 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
8246 > bundle_state
->accumulated_insns_num
8247 || (((struct bundle_state
*)
8248 *entry_ptr
)->accumulated_insns_num
8249 == bundle_state
->accumulated_insns_num
8250 && (((struct bundle_state
*)
8251 *entry_ptr
)->branch_deviation
8252 > bundle_state
->branch_deviation
8253 || (((struct bundle_state
*)
8254 *entry_ptr
)->branch_deviation
8255 == bundle_state
->branch_deviation
8256 && ((struct bundle_state
*)
8257 *entry_ptr
)->middle_bundle_stops
8258 > bundle_state
->middle_bundle_stops
))))))
8261 struct bundle_state temp
;
8263 temp
= *(struct bundle_state
*) *entry_ptr
;
8264 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
8265 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
8266 *bundle_state
= temp
;
8271 /* Start work with the hash table. */
8274 initiate_bundle_state_table (void)
8276 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
8280 /* Finish work with the hash table. */
8283 finish_bundle_state_table (void)
8285 htab_delete (bundle_state_table
);
8290 /* The following variable is a insn `nop' used to check bundle states
8291 with different number of inserted nops. */
8293 static rtx ia64_nop
;
8295 /* The following function tries to issue NOPS_NUM nops for the current
8296 state without advancing processor cycle. If it failed, the
8297 function returns FALSE and frees the current state. */
8300 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
8304 for (i
= 0; i
< nops_num
; i
++)
8305 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
8307 free_bundle_state (curr_state
);
8313 /* The following function tries to issue INSN for the current
8314 state without advancing processor cycle. If it failed, the
8315 function returns FALSE and frees the current state. */
8318 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
8320 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
8322 free_bundle_state (curr_state
);
8328 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8329 starting with ORIGINATOR without advancing processor cycle. If
8330 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8331 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8332 If it was successful, the function creates new bundle state and
8333 insert into the hash table and into `index_to_bundle_states'. */
8336 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
8337 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
8339 struct bundle_state
*curr_state
;
8341 curr_state
= get_free_bundle_state ();
8342 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
8343 curr_state
->insn
= insn
;
8344 curr_state
->insn_num
= originator
->insn_num
+ 1;
8345 curr_state
->cost
= originator
->cost
;
8346 curr_state
->originator
= originator
;
8347 curr_state
->before_nops_num
= before_nops_num
;
8348 curr_state
->after_nops_num
= 0;
8349 curr_state
->accumulated_insns_num
8350 = originator
->accumulated_insns_num
+ before_nops_num
;
8351 curr_state
->branch_deviation
= originator
->branch_deviation
;
8352 curr_state
->middle_bundle_stops
= originator
->middle_bundle_stops
;
8354 if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
8356 gcc_assert (GET_MODE (insn
) != TImode
);
8357 if (!try_issue_nops (curr_state
, before_nops_num
))
8359 if (!try_issue_insn (curr_state
, insn
))
8361 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
8362 if (curr_state
->accumulated_insns_num
% 3 != 0)
8363 curr_state
->middle_bundle_stops
++;
8364 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
8365 && curr_state
->accumulated_insns_num
% 3 != 0)
8367 free_bundle_state (curr_state
);
8371 else if (GET_MODE (insn
) != TImode
)
8373 if (!try_issue_nops (curr_state
, before_nops_num
))
8375 if (!try_issue_insn (curr_state
, insn
))
8377 curr_state
->accumulated_insns_num
++;
8378 gcc_assert (GET_CODE (PATTERN (insn
)) != ASM_INPUT
8379 && asm_noperands (PATTERN (insn
)) < 0);
8381 if (ia64_safe_type (insn
) == TYPE_L
)
8382 curr_state
->accumulated_insns_num
++;
8386 /* If this is an insn that must be first in a group, then don't allow
8387 nops to be emitted before it. Currently, alloc is the only such
8388 supported instruction. */
8389 /* ??? The bundling automatons should handle this for us, but they do
8390 not yet have support for the first_insn attribute. */
8391 if (before_nops_num
> 0 && get_attr_first_insn (insn
) == FIRST_INSN_YES
)
8393 free_bundle_state (curr_state
);
8397 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
8398 state_transition (curr_state
->dfa_state
, NULL
);
8400 if (!try_issue_nops (curr_state
, before_nops_num
))
8402 if (!try_issue_insn (curr_state
, insn
))
8404 curr_state
->accumulated_insns_num
++;
8405 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
8406 || asm_noperands (PATTERN (insn
)) >= 0)
8408 /* Finish bundle containing asm insn. */
8409 curr_state
->after_nops_num
8410 = 3 - curr_state
->accumulated_insns_num
% 3;
8411 curr_state
->accumulated_insns_num
8412 += 3 - curr_state
->accumulated_insns_num
% 3;
8414 else if (ia64_safe_type (insn
) == TYPE_L
)
8415 curr_state
->accumulated_insns_num
++;
8417 if (ia64_safe_type (insn
) == TYPE_B
)
8418 curr_state
->branch_deviation
8419 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
8420 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
8422 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
8425 struct bundle_state
*curr_state1
;
8426 struct bundle_state
*allocated_states_chain
;
8428 curr_state1
= get_free_bundle_state ();
8429 dfa_state
= curr_state1
->dfa_state
;
8430 allocated_states_chain
= curr_state1
->allocated_states_chain
;
8431 *curr_state1
= *curr_state
;
8432 curr_state1
->dfa_state
= dfa_state
;
8433 curr_state1
->allocated_states_chain
= allocated_states_chain
;
8434 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
8436 curr_state
= curr_state1
;
8438 if (!try_issue_nops (curr_state
,
8439 3 - curr_state
->accumulated_insns_num
% 3))
8441 curr_state
->after_nops_num
8442 = 3 - curr_state
->accumulated_insns_num
% 3;
8443 curr_state
->accumulated_insns_num
8444 += 3 - curr_state
->accumulated_insns_num
% 3;
8446 if (!insert_bundle_state (curr_state
))
8447 free_bundle_state (curr_state
);
8451 /* The following function returns position in the two window bundle
8455 get_max_pos (state_t state
)
8457 if (cpu_unit_reservation_p (state
, pos_6
))
8459 else if (cpu_unit_reservation_p (state
, pos_5
))
8461 else if (cpu_unit_reservation_p (state
, pos_4
))
8463 else if (cpu_unit_reservation_p (state
, pos_3
))
8465 else if (cpu_unit_reservation_p (state
, pos_2
))
8467 else if (cpu_unit_reservation_p (state
, pos_1
))
8473 /* The function returns code of a possible template for given position
8474 and state. The function should be called only with 2 values of
8475 position equal to 3 or 6. We avoid generating F NOPs by putting
8476 templates containing F insns at the end of the template search
8477 because undocumented anomaly in McKinley derived cores which can
8478 cause stalls if an F-unit insn (including a NOP) is issued within a
8479 six-cycle window after reading certain application registers (such
8480 as ar.bsp). Furthermore, power-considerations also argue against
8481 the use of F-unit instructions unless they're really needed. */
8484 get_template (state_t state
, int pos
)
8489 if (cpu_unit_reservation_p (state
, _0mmi_
))
8491 else if (cpu_unit_reservation_p (state
, _0mii_
))
8493 else if (cpu_unit_reservation_p (state
, _0mmb_
))
8495 else if (cpu_unit_reservation_p (state
, _0mib_
))
8497 else if (cpu_unit_reservation_p (state
, _0mbb_
))
8499 else if (cpu_unit_reservation_p (state
, _0bbb_
))
8501 else if (cpu_unit_reservation_p (state
, _0mmf_
))
8503 else if (cpu_unit_reservation_p (state
, _0mfi_
))
8505 else if (cpu_unit_reservation_p (state
, _0mfb_
))
8507 else if (cpu_unit_reservation_p (state
, _0mlx_
))
8512 if (cpu_unit_reservation_p (state
, _1mmi_
))
8514 else if (cpu_unit_reservation_p (state
, _1mii_
))
8516 else if (cpu_unit_reservation_p (state
, _1mmb_
))
8518 else if (cpu_unit_reservation_p (state
, _1mib_
))
8520 else if (cpu_unit_reservation_p (state
, _1mbb_
))
8522 else if (cpu_unit_reservation_p (state
, _1bbb_
))
8524 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
8526 else if (cpu_unit_reservation_p (state
, _1mfi_
))
8528 else if (cpu_unit_reservation_p (state
, _1mfb_
))
8530 else if (cpu_unit_reservation_p (state
, _1mlx_
))
8539 /* True when INSN is important for bundling. */
8541 important_for_bundling_p (rtx insn
)
8543 return (INSN_P (insn
)
8544 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
8545 && GET_CODE (PATTERN (insn
)) != USE
8546 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8549 /* The following function returns an insn important for insn bundling
8550 followed by INSN and before TAIL. */
8553 get_next_important_insn (rtx insn
, rtx tail
)
8555 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
8556 if (important_for_bundling_p (insn
))
8561 /* Add a bundle selector TEMPLATE0 before INSN. */
8564 ia64_add_bundle_selector_before (int template0
, rtx insn
)
8566 rtx b
= gen_bundle_selector (GEN_INT (template0
));
8568 ia64_emit_insn_before (b
, insn
);
8569 #if NR_BUNDLES == 10
8570 if ((template0
== 4 || template0
== 5)
8571 && ia64_except_unwind_info () == UI_TARGET
)
8574 rtx note
= NULL_RTX
;
8576 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8577 first or second slot. If it is and has REG_EH_NOTE set, copy it
8578 to following nops, as br.call sets rp to the address of following
8579 bundle and therefore an EH region end must be on a bundle
8581 insn
= PREV_INSN (insn
);
8582 for (i
= 0; i
< 3; i
++)
8585 insn
= next_active_insn (insn
);
8586 while (GET_CODE (insn
) == INSN
8587 && get_attr_empty (insn
) == EMPTY_YES
);
8588 if (GET_CODE (insn
) == CALL_INSN
)
8589 note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8594 gcc_assert ((code
= recog_memoized (insn
)) == CODE_FOR_nop
8595 || code
== CODE_FOR_nop_b
);
8596 if (find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
8599 add_reg_note (insn
, REG_EH_REGION
, XEXP (note
, 0));
8606 /* The following function does insn bundling. Bundling means
8607 inserting templates and nop insns to fit insn groups into permitted
8608 templates. Instruction scheduling uses NDFA (non-deterministic
8609 finite automata) encoding informations about the templates and the
8610 inserted nops. Nondeterminism of the automata permits follows
8611 all possible insn sequences very fast.
8613 Unfortunately it is not possible to get information about inserting
8614 nop insns and used templates from the automata states. The
8615 automata only says that we can issue an insn possibly inserting
8616 some nops before it and using some template. Therefore insn
8617 bundling in this function is implemented by using DFA
8618 (deterministic finite automata). We follow all possible insn
8619 sequences by inserting 0-2 nops (that is what the NDFA describe for
8620 insn scheduling) before/after each insn being bundled. We know the
8621 start of simulated processor cycle from insn scheduling (insn
8622 starting a new cycle has TImode).
8624 Simple implementation of insn bundling would create enormous
8625 number of possible insn sequences satisfying information about new
8626 cycle ticks taken from the insn scheduling. To make the algorithm
8627 practical we use dynamic programming. Each decision (about
8628 inserting nops and implicitly about previous decisions) is described
8629 by structure bundle_state (see above). If we generate the same
8630 bundle state (key is automaton state after issuing the insns and
8631 nops for it), we reuse already generated one. As consequence we
8632 reject some decisions which cannot improve the solution and
8633 reduce memory for the algorithm.
8635 When we reach the end of EBB (extended basic block), we choose the
8636 best sequence and then, moving back in EBB, insert templates for
8637 the best alternative. The templates are taken from querying
8638 automaton state for each insn in chosen bundle states.
8640 So the algorithm makes two (forward and backward) passes through
8644 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
8646 struct bundle_state
*curr_state
, *next_state
, *best_state
;
8647 rtx insn
, next_insn
;
8649 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
8650 int pos
= 0, max_pos
, template0
, template1
;
8653 enum attr_type type
;
8656 /* Count insns in the EBB. */
8657 for (insn
= NEXT_INSN (prev_head_insn
);
8658 insn
&& insn
!= tail
;
8659 insn
= NEXT_INSN (insn
))
8665 dfa_clean_insn_cache ();
8666 initiate_bundle_state_table ();
8667 index_to_bundle_states
= XNEWVEC (struct bundle_state
*, insn_num
+ 2);
8668 /* First (forward) pass -- generation of bundle states. */
8669 curr_state
= get_free_bundle_state ();
8670 curr_state
->insn
= NULL
;
8671 curr_state
->before_nops_num
= 0;
8672 curr_state
->after_nops_num
= 0;
8673 curr_state
->insn_num
= 0;
8674 curr_state
->cost
= 0;
8675 curr_state
->accumulated_insns_num
= 0;
8676 curr_state
->branch_deviation
= 0;
8677 curr_state
->middle_bundle_stops
= 0;
8678 curr_state
->next
= NULL
;
8679 curr_state
->originator
= NULL
;
8680 state_reset (curr_state
->dfa_state
);
8681 index_to_bundle_states
[0] = curr_state
;
8683 /* Shift cycle mark if it is put on insn which could be ignored. */
8684 for (insn
= NEXT_INSN (prev_head_insn
);
8686 insn
= NEXT_INSN (insn
))
8688 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
8689 || GET_CODE (PATTERN (insn
)) == USE
8690 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
8691 && GET_MODE (insn
) == TImode
)
8693 PUT_MODE (insn
, VOIDmode
);
8694 for (next_insn
= NEXT_INSN (insn
);
8696 next_insn
= NEXT_INSN (next_insn
))
8697 if (INSN_P (next_insn
)
8698 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
8699 && GET_CODE (PATTERN (next_insn
)) != USE
8700 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
8701 && INSN_CODE (next_insn
) != CODE_FOR_insn_group_barrier
)
8703 PUT_MODE (next_insn
, TImode
);
8707 /* Forward pass: generation of bundle states. */
8708 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
8712 gcc_assert (INSN_P (insn
)
8713 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
8714 && GET_CODE (PATTERN (insn
)) != USE
8715 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8716 type
= ia64_safe_type (insn
);
8717 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
8719 index_to_bundle_states
[insn_num
] = NULL
;
8720 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
8722 curr_state
= next_state
)
8724 pos
= curr_state
->accumulated_insns_num
% 3;
8725 next_state
= curr_state
->next
;
8726 /* We must fill up the current bundle in order to start a
8727 subsequent asm insn in a new bundle. Asm insn is always
8728 placed in a separate bundle. */
8730 = (next_insn
!= NULL_RTX
8731 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
8732 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
8733 /* We may fill up the current bundle if it is the cycle end
8734 without a group barrier. */
8736 = (only_bundle_end_p
|| next_insn
== NULL_RTX
8737 || (GET_MODE (next_insn
) == TImode
8738 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
8739 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
8741 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
8743 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
8745 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
8748 gcc_assert (index_to_bundle_states
[insn_num
]);
8749 for (curr_state
= index_to_bundle_states
[insn_num
];
8751 curr_state
= curr_state
->next
)
8752 if (verbose
>= 2 && dump
)
8754 /* This structure is taken from generated code of the
8755 pipeline hazard recognizer (see file insn-attrtab.c).
8756 Please don't forget to change the structure if a new
8757 automaton is added to .md file. */
8760 unsigned short one_automaton_state
;
8761 unsigned short oneb_automaton_state
;
8762 unsigned short two_automaton_state
;
8763 unsigned short twob_automaton_state
;
8768 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
8769 curr_state
->unique_num
,
8770 (curr_state
->originator
== NULL
8771 ? -1 : curr_state
->originator
->unique_num
),
8773 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
8774 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
8775 curr_state
->middle_bundle_stops
,
8776 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
8781 /* We should find a solution because the 2nd insn scheduling has
8783 gcc_assert (index_to_bundle_states
[insn_num
]);
8784 /* Find a state corresponding to the best insn sequence. */
8786 for (curr_state
= index_to_bundle_states
[insn_num
];
8788 curr_state
= curr_state
->next
)
8789 /* We are just looking at the states with fully filled up last
8790 bundle. The first we prefer insn sequences with minimal cost
8791 then with minimal inserted nops and finally with branch insns
8792 placed in the 3rd slots. */
8793 if (curr_state
->accumulated_insns_num
% 3 == 0
8794 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
8795 || (best_state
->cost
== curr_state
->cost
8796 && (curr_state
->accumulated_insns_num
8797 < best_state
->accumulated_insns_num
8798 || (curr_state
->accumulated_insns_num
8799 == best_state
->accumulated_insns_num
8800 && (curr_state
->branch_deviation
8801 < best_state
->branch_deviation
8802 || (curr_state
->branch_deviation
8803 == best_state
->branch_deviation
8804 && curr_state
->middle_bundle_stops
8805 < best_state
->middle_bundle_stops
)))))))
8806 best_state
= curr_state
;
8807 /* Second (backward) pass: adding nops and templates. */
8808 gcc_assert (best_state
);
8809 insn_num
= best_state
->before_nops_num
;
8810 template0
= template1
= -1;
8811 for (curr_state
= best_state
;
8812 curr_state
->originator
!= NULL
;
8813 curr_state
= curr_state
->originator
)
8815 insn
= curr_state
->insn
;
8816 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
8817 || asm_noperands (PATTERN (insn
)) >= 0);
8819 if (verbose
>= 2 && dump
)
8823 unsigned short one_automaton_state
;
8824 unsigned short oneb_automaton_state
;
8825 unsigned short two_automaton_state
;
8826 unsigned short twob_automaton_state
;
8831 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
8832 curr_state
->unique_num
,
8833 (curr_state
->originator
== NULL
8834 ? -1 : curr_state
->originator
->unique_num
),
8836 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
8837 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
8838 curr_state
->middle_bundle_stops
,
8839 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
8842 /* Find the position in the current bundle window. The window can
8843 contain at most two bundles. Two bundle window means that
8844 the processor will make two bundle rotation. */
8845 max_pos
= get_max_pos (curr_state
->dfa_state
);
8847 /* The following (negative template number) means that the
8848 processor did one bundle rotation. */
8849 || (max_pos
== 3 && template0
< 0))
8851 /* We are at the end of the window -- find template(s) for
8855 template0
= get_template (curr_state
->dfa_state
, 3);
8858 template1
= get_template (curr_state
->dfa_state
, 3);
8859 template0
= get_template (curr_state
->dfa_state
, 6);
8862 if (max_pos
> 3 && template1
< 0)
8863 /* It may happen when we have the stop inside a bundle. */
8865 gcc_assert (pos
<= 3);
8866 template1
= get_template (curr_state
->dfa_state
, 3);
8870 /* Emit nops after the current insn. */
8871 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
8874 emit_insn_after (nop
, insn
);
8876 gcc_assert (pos
>= 0);
8879 /* We are at the start of a bundle: emit the template
8880 (it should be defined). */
8881 gcc_assert (template0
>= 0);
8882 ia64_add_bundle_selector_before (template0
, nop
);
8883 /* If we have two bundle window, we make one bundle
8884 rotation. Otherwise template0 will be undefined
8885 (negative value). */
8886 template0
= template1
;
8890 /* Move the position backward in the window. Group barrier has
8891 no slot. Asm insn takes all bundle. */
8892 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
8893 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
8894 && asm_noperands (PATTERN (insn
)) < 0)
8896 /* Long insn takes 2 slots. */
8897 if (ia64_safe_type (insn
) == TYPE_L
)
8899 gcc_assert (pos
>= 0);
8901 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
8902 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
8903 && asm_noperands (PATTERN (insn
)) < 0)
8905 /* The current insn is at the bundle start: emit the
8907 gcc_assert (template0
>= 0);
8908 ia64_add_bundle_selector_before (template0
, insn
);
8909 b
= PREV_INSN (insn
);
8911 /* See comment above in analogous place for emitting nops
8913 template0
= template1
;
8916 /* Emit nops after the current insn. */
8917 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
8920 ia64_emit_insn_before (nop
, insn
);
8921 nop
= PREV_INSN (insn
);
8924 gcc_assert (pos
>= 0);
8927 /* See comment above in analogous place for emitting nops
8929 gcc_assert (template0
>= 0);
8930 ia64_add_bundle_selector_before (template0
, insn
);
8931 b
= PREV_INSN (insn
);
8933 template0
= template1
;
8939 #ifdef ENABLE_CHECKING
8941 /* Assert right calculation of middle_bundle_stops. */
8942 int num
= best_state
->middle_bundle_stops
;
8943 bool start_bundle
= true, end_bundle
= false;
8945 for (insn
= NEXT_INSN (prev_head_insn
);
8946 insn
&& insn
!= tail
;
8947 insn
= NEXT_INSN (insn
))
8951 if (recog_memoized (insn
) == CODE_FOR_bundle_selector
)
8952 start_bundle
= true;
8957 for (next_insn
= NEXT_INSN (insn
);
8958 next_insn
&& next_insn
!= tail
;
8959 next_insn
= NEXT_INSN (next_insn
))
8960 if (INSN_P (next_insn
)
8961 && (ia64_safe_itanium_class (next_insn
)
8962 != ITANIUM_CLASS_IGNORE
8963 || recog_memoized (next_insn
)
8964 == CODE_FOR_bundle_selector
)
8965 && GET_CODE (PATTERN (next_insn
)) != USE
8966 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
8969 end_bundle
= next_insn
== NULL_RTX
8970 || next_insn
== tail
8971 || (INSN_P (next_insn
)
8972 && recog_memoized (next_insn
)
8973 == CODE_FOR_bundle_selector
);
8974 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
8975 && !start_bundle
&& !end_bundle
8977 && GET_CODE (PATTERN (next_insn
)) != ASM_INPUT
8978 && asm_noperands (PATTERN (next_insn
)) < 0)
8981 start_bundle
= false;
8985 gcc_assert (num
== 0);
8989 free (index_to_bundle_states
);
8990 finish_bundle_state_table ();
8992 dfa_clean_insn_cache ();
8995 /* The following function is called at the end of scheduling BB or
8996 EBB. After reload, it inserts stop bits and does insn bundling. */
8999 ia64_sched_finish (FILE *dump
, int sched_verbose
)
9002 fprintf (dump
, "// Finishing schedule.\n");
9003 if (!reload_completed
)
9005 if (reload_completed
)
9007 final_emit_insn_group_barriers (dump
);
9008 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
9009 current_sched_info
->next_tail
);
9010 if (sched_verbose
&& dump
)
9011 fprintf (dump
, "// finishing %d-%d\n",
9012 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
9013 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
9019 /* The following function inserts stop bits in scheduled BB or EBB. */
9022 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
9025 int need_barrier_p
= 0;
9026 int seen_good_insn
= 0;
9028 init_insn_group_barriers ();
9030 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
9031 insn
!= current_sched_info
->next_tail
;
9032 insn
= NEXT_INSN (insn
))
9034 if (GET_CODE (insn
) == BARRIER
)
9036 rtx last
= prev_active_insn (insn
);
9040 if (GET_CODE (last
) == JUMP_INSN
9041 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
9042 last
= prev_active_insn (last
);
9043 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9044 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
9046 init_insn_group_barriers ();
9050 else if (NONDEBUG_INSN_P (insn
))
9052 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
9054 init_insn_group_barriers ();
9058 else if (need_barrier_p
|| group_barrier_needed (insn
)
9059 || (mflag_sched_stop_bits_after_every_cycle
9060 && GET_MODE (insn
) == TImode
9063 if (TARGET_EARLY_STOP_BITS
)
9068 last
!= current_sched_info
->prev_head
;
9069 last
= PREV_INSN (last
))
9070 if (INSN_P (last
) && GET_MODE (last
) == TImode
9071 && stops_p
[INSN_UID (last
)])
9073 if (last
== current_sched_info
->prev_head
)
9075 last
= prev_active_insn (last
);
9077 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9078 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9080 init_insn_group_barriers ();
9081 for (last
= NEXT_INSN (last
);
9083 last
= NEXT_INSN (last
))
9086 group_barrier_needed (last
);
9087 if (recog_memoized (last
) >= 0
9088 && important_for_bundling_p (last
))
9094 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9096 init_insn_group_barriers ();
9099 group_barrier_needed (insn
);
9100 if (recog_memoized (insn
) >= 0
9101 && important_for_bundling_p (insn
))
9104 else if (recog_memoized (insn
) >= 0
9105 && important_for_bundling_p (insn
))
9107 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
9108 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
9109 || asm_noperands (PATTERN (insn
)) >= 0);
9116 /* If the following function returns TRUE, we will use the DFA
9120 ia64_first_cycle_multipass_dfa_lookahead (void)
9122 return (reload_completed
? 6 : 4);
9125 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9128 ia64_init_dfa_pre_cycle_insn (void)
9130 if (temp_dfa_state
== NULL
)
9132 dfa_state_size
= state_size ();
9133 temp_dfa_state
= xmalloc (dfa_state_size
);
9134 prev_cycle_state
= xmalloc (dfa_state_size
);
9136 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
9137 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
9138 recog_memoized (dfa_pre_cycle_insn
);
9139 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9140 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
9141 recog_memoized (dfa_stop_insn
);
9144 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9145 used by the DFA insn scheduler. */
9148 ia64_dfa_pre_cycle_insn (void)
9150 return dfa_pre_cycle_insn
;
9153 /* The following function returns TRUE if PRODUCER (of type ilog or
9154 ld) produces address for CONSUMER (of type st or stf). */
9157 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
9161 gcc_assert (producer
&& consumer
);
9162 dest
= ia64_single_set (producer
);
9164 reg
= SET_DEST (dest
);
9166 if (GET_CODE (reg
) == SUBREG
)
9167 reg
= SUBREG_REG (reg
);
9168 gcc_assert (GET_CODE (reg
) == REG
);
9170 dest
= ia64_single_set (consumer
);
9172 mem
= SET_DEST (dest
);
9173 gcc_assert (mem
&& GET_CODE (mem
) == MEM
);
9174 return reg_mentioned_p (reg
, mem
);
9177 /* The following function returns TRUE if PRODUCER (of type ilog or
9178 ld) produces address for CONSUMER (of type ld or fld). */
9181 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
9183 rtx dest
, src
, reg
, mem
;
9185 gcc_assert (producer
&& consumer
);
9186 dest
= ia64_single_set (producer
);
9188 reg
= SET_DEST (dest
);
9190 if (GET_CODE (reg
) == SUBREG
)
9191 reg
= SUBREG_REG (reg
);
9192 gcc_assert (GET_CODE (reg
) == REG
);
9194 src
= ia64_single_set (consumer
);
9196 mem
= SET_SRC (src
);
9199 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
9200 mem
= XVECEXP (mem
, 0, 0);
9201 else if (GET_CODE (mem
) == IF_THEN_ELSE
)
9202 /* ??? Is this bypass necessary for ld.c? */
9204 gcc_assert (XINT (XEXP (XEXP (mem
, 0), 0), 1) == UNSPEC_LDCCLR
);
9205 mem
= XEXP (mem
, 1);
9208 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
9209 mem
= XEXP (mem
, 0);
9211 if (GET_CODE (mem
) == UNSPEC
)
9213 int c
= XINT (mem
, 1);
9215 gcc_assert (c
== UNSPEC_LDA
|| c
== UNSPEC_LDS
|| c
== UNSPEC_LDS_A
9216 || c
== UNSPEC_LDSA
);
9217 mem
= XVECEXP (mem
, 0, 0);
9220 /* Note that LO_SUM is used for GOT loads. */
9221 gcc_assert (GET_CODE (mem
) == LO_SUM
|| GET_CODE (mem
) == MEM
);
9223 return reg_mentioned_p (reg
, mem
);
9226 /* The following function returns TRUE if INSN produces address for a
9227 load/store insn. We will place such insns into M slot because it
9228 decreases its latency time. */
9231 ia64_produce_address_p (rtx insn
)
9237 /* Emit pseudo-ops for the assembler to describe predicate relations.
9238 At present this assumes that we only consider predicate pairs to
9239 be mutex, and that the assembler can deduce proper values from
9240 straight-line code. */
9243 emit_predicate_relation_info (void)
9247 FOR_EACH_BB_REVERSE (bb
)
9250 rtx head
= BB_HEAD (bb
);
9252 /* We only need such notes at code labels. */
9253 if (GET_CODE (head
) != CODE_LABEL
)
9255 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head
)))
9256 head
= NEXT_INSN (head
);
9258 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9259 grabbing the entire block of predicate registers. */
9260 for (r
= PR_REG (2); r
< PR_REG (64); r
+= 2)
9261 if (REGNO_REG_SET_P (df_get_live_in (bb
), r
))
9263 rtx p
= gen_rtx_REG (BImode
, r
);
9264 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
9265 if (head
== BB_END (bb
))
9271 /* Look for conditional calls that do not return, and protect predicate
9272 relations around them. Otherwise the assembler will assume the call
9273 returns, and complain about uses of call-clobbered predicates after
9275 FOR_EACH_BB_REVERSE (bb
)
9277 rtx insn
= BB_HEAD (bb
);
9281 if (GET_CODE (insn
) == CALL_INSN
9282 && GET_CODE (PATTERN (insn
)) == COND_EXEC
9283 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
9285 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
9286 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
9287 if (BB_HEAD (bb
) == insn
)
9289 if (BB_END (bb
) == insn
)
9293 if (insn
== BB_END (bb
))
9295 insn
= NEXT_INSN (insn
);
9300 /* Perform machine dependent operations on the rtl chain INSNS. */
9305 /* We are freeing block_for_insn in the toplev to keep compatibility
9306 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9307 compute_bb_for_insn ();
9309 /* If optimizing, we'll have split before scheduling. */
9313 if (optimize
&& ia64_flag_schedule_insns2
9314 && dbg_cnt (ia64_sched2
))
9316 timevar_push (TV_SCHED2
);
9317 ia64_final_schedule
= 1;
9319 initiate_bundle_states ();
9320 ia64_nop
= make_insn_raw (gen_nop ());
9321 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
9322 recog_memoized (ia64_nop
);
9323 clocks_length
= get_max_uid () + 1;
9324 stops_p
= XCNEWVEC (char, clocks_length
);
9326 if (ia64_tune
== PROCESSOR_ITANIUM2
)
9328 pos_1
= get_cpu_unit_code ("2_1");
9329 pos_2
= get_cpu_unit_code ("2_2");
9330 pos_3
= get_cpu_unit_code ("2_3");
9331 pos_4
= get_cpu_unit_code ("2_4");
9332 pos_5
= get_cpu_unit_code ("2_5");
9333 pos_6
= get_cpu_unit_code ("2_6");
9334 _0mii_
= get_cpu_unit_code ("2b_0mii.");
9335 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
9336 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
9337 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
9338 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
9339 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
9340 _0mib_
= get_cpu_unit_code ("2b_0mib.");
9341 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
9342 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
9343 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
9344 _1mii_
= get_cpu_unit_code ("2b_1mii.");
9345 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
9346 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
9347 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
9348 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
9349 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
9350 _1mib_
= get_cpu_unit_code ("2b_1mib.");
9351 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
9352 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
9353 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
9357 pos_1
= get_cpu_unit_code ("1_1");
9358 pos_2
= get_cpu_unit_code ("1_2");
9359 pos_3
= get_cpu_unit_code ("1_3");
9360 pos_4
= get_cpu_unit_code ("1_4");
9361 pos_5
= get_cpu_unit_code ("1_5");
9362 pos_6
= get_cpu_unit_code ("1_6");
9363 _0mii_
= get_cpu_unit_code ("1b_0mii.");
9364 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
9365 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
9366 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
9367 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
9368 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
9369 _0mib_
= get_cpu_unit_code ("1b_0mib.");
9370 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
9371 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
9372 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
9373 _1mii_
= get_cpu_unit_code ("1b_1mii.");
9374 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
9375 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
9376 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
9377 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
9378 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
9379 _1mib_
= get_cpu_unit_code ("1b_1mib.");
9380 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
9381 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
9382 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
9385 if (flag_selective_scheduling2
9386 && !maybe_skip_selective_scheduling ())
9387 run_selective_scheduling ();
9391 /* Redo alignment computation, as it might gone wrong. */
9392 compute_alignments ();
9394 /* We cannot reuse this one because it has been corrupted by the
9396 finish_bundle_states ();
9399 emit_insn_group_barriers (dump_file
);
9401 ia64_final_schedule
= 0;
9402 timevar_pop (TV_SCHED2
);
9405 emit_all_insn_group_barriers (dump_file
);
9409 /* A call must not be the last instruction in a function, so that the
9410 return address is still within the function, so that unwinding works
9411 properly. Note that IA-64 differs from dwarf2 on this point. */
9412 if (ia64_except_unwind_info () == UI_TARGET
)
9417 insn
= get_last_insn ();
9418 if (! INSN_P (insn
))
9419 insn
= prev_active_insn (insn
);
9422 /* Skip over insns that expand to nothing. */
9423 while (GET_CODE (insn
) == INSN
9424 && get_attr_empty (insn
) == EMPTY_YES
)
9426 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
9427 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
9429 insn
= prev_active_insn (insn
);
9431 if (GET_CODE (insn
) == CALL_INSN
)
9434 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9435 emit_insn (gen_break_f ());
9436 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9441 emit_predicate_relation_info ();
9443 if (ia64_flag_var_tracking
)
9445 timevar_push (TV_VAR_TRACKING
);
9446 variable_tracking_main ();
9447 timevar_pop (TV_VAR_TRACKING
);
9449 df_finish_pass (false);
9452 /* Return true if REGNO is used by the epilogue. */
9455 ia64_epilogue_uses (int regno
)
9460 /* With a call to a function in another module, we will write a new
9461 value to "gp". After returning from such a call, we need to make
9462 sure the function restores the original gp-value, even if the
9463 function itself does not use the gp anymore. */
9464 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
9466 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9467 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9468 /* For functions defined with the syscall_linkage attribute, all
9469 input registers are marked as live at all function exits. This
9470 prevents the register allocator from using the input registers,
9471 which in turn makes it possible to restart a system call after
9472 an interrupt without having to save/restore the input registers.
9473 This also prevents kernel data from leaking to application code. */
9474 return lookup_attribute ("syscall_linkage",
9475 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
9478 /* Conditional return patterns can't represent the use of `b0' as
9479 the return address, so we force the value live this way. */
9483 /* Likewise for ar.pfs, which is used by br.ret. */
9491 /* Return true if REGNO is used by the frame unwinder. */
9494 ia64_eh_uses (int regno
)
9498 if (! reload_completed
)
9504 for (r
= reg_save_b0
; r
<= reg_save_ar_lc
; r
++)
9505 if (regno
== current_frame_info
.r
[r
]
9506 || regno
== emitted_frame_related_regs
[r
])
9512 /* Return true if this goes in small data/bss. */
9514 /* ??? We could also support own long data here. Generating movl/add/ld8
9515 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9516 code faster because there is one less load. This also includes incomplete
9517 types which can't go in sdata/sbss. */
9520 ia64_in_small_data_p (const_tree exp
)
9522 if (TARGET_NO_SDATA
)
9525 /* We want to merge strings, so we never consider them small data. */
9526 if (TREE_CODE (exp
) == STRING_CST
)
9529 /* Functions are never small data. */
9530 if (TREE_CODE (exp
) == FUNCTION_DECL
)
9533 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
9535 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
9537 if (strcmp (section
, ".sdata") == 0
9538 || strncmp (section
, ".sdata.", 7) == 0
9539 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
9540 || strcmp (section
, ".sbss") == 0
9541 || strncmp (section
, ".sbss.", 6) == 0
9542 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0)
9547 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
9549 /* If this is an incomplete type with size 0, then we can't put it
9550 in sdata because it might be too big when completed. */
9551 if (size
> 0 && size
<= ia64_section_threshold
)
9558 /* Output assembly directives for prologue regions. */
9560 /* The current basic block number. */
9562 static bool last_block
;
9564 /* True if we need a copy_state command at the start of the next block. */
9566 static bool need_copy_state
;
9568 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9569 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9572 /* Emit a debugging label after a call-frame-related insn. We'd
9573 rather output the label right away, but we'd have to output it
9574 after, not before, the instruction, and the instruction has not
9575 been output yet. So we emit the label after the insn, delete it to
9576 avoid introducing basic blocks, and mark it as preserved, such that
9577 it is still output, given that it is referenced in debug info. */
9580 ia64_emit_deleted_label_after_insn (rtx insn
)
9582 char label
[MAX_ARTIFICIAL_LABEL_BYTES
];
9583 rtx lb
= gen_label_rtx ();
9584 rtx label_insn
= emit_label_after (lb
, insn
);
9586 LABEL_PRESERVE_P (lb
) = 1;
9588 delete_insn (label_insn
);
9590 ASM_GENERATE_INTERNAL_LABEL (label
, "L", CODE_LABEL_NUMBER (label_insn
));
9592 return xstrdup (label
);
9595 /* Define the CFA after INSN with the steady-state definition. */
9598 ia64_dwarf2out_def_steady_cfa (rtx insn
, bool frame
)
9600 rtx fp
= frame_pointer_needed
9601 ? hard_frame_pointer_rtx
9602 : stack_pointer_rtx
;
9603 const char *label
= ia64_emit_deleted_label_after_insn (insn
);
9610 ia64_initial_elimination_offset
9611 (REGNO (arg_pointer_rtx
), REGNO (fp
))
9612 + ARG_POINTER_CFA_OFFSET (current_function_decl
));
9615 /* All we need to do here is avoid a crash in the generic dwarf2
9616 processing. The real CFA definition is set up above. */
9619 ia64_dwarf_handle_frame_unspec (const char * ARG_UNUSED (label
),
9620 rtx
ARG_UNUSED (pattern
),
9623 gcc_assert (index
== UNSPECV_ALLOC
);
9626 /* The generic dwarf2 frame debug info generator does not define a
9627 separate region for the very end of the epilogue, so refrain from
9628 doing so in the IA64-specific code as well. */
9630 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
9632 /* The function emits unwind directives for the start of an epilogue. */
9635 process_epilogue (FILE *asm_out_file
, rtx insn
, bool unwind
, bool frame
)
9637 /* If this isn't the last block of the function, then we need to label the
9638 current state, and copy it back in at the start of the next block. */
9643 fprintf (asm_out_file
, "\t.label_state %d\n",
9644 ++cfun
->machine
->state_num
);
9645 need_copy_state
= true;
9649 fprintf (asm_out_file
, "\t.restore sp\n");
9650 if (IA64_CHANGE_CFA_IN_EPILOGUE
&& frame
)
9651 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn
),
9652 STACK_POINTER_REGNUM
, INCOMING_FRAME_SP_OFFSET
);
9655 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9658 process_cfa_adjust_cfa (FILE *asm_out_file
, rtx pat
, rtx insn
,
9659 bool unwind
, bool frame
)
9661 rtx dest
= SET_DEST (pat
);
9662 rtx src
= SET_SRC (pat
);
9664 if (dest
== stack_pointer_rtx
)
9666 if (GET_CODE (src
) == PLUS
)
9668 rtx op0
= XEXP (src
, 0);
9669 rtx op1
= XEXP (src
, 1);
9671 gcc_assert (op0
== dest
&& GET_CODE (op1
) == CONST_INT
);
9673 if (INTVAL (op1
) < 0)
9675 gcc_assert (!frame_pointer_needed
);
9677 fprintf (asm_out_file
,
9678 "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
9680 ia64_dwarf2out_def_steady_cfa (insn
, frame
);
9683 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9687 gcc_assert (src
== hard_frame_pointer_rtx
);
9688 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9691 else if (dest
== hard_frame_pointer_rtx
)
9693 gcc_assert (src
== stack_pointer_rtx
);
9694 gcc_assert (frame_pointer_needed
);
9697 fprintf (asm_out_file
, "\t.vframe r%d\n",
9698 ia64_dbx_register_number (REGNO (dest
)));
9699 ia64_dwarf2out_def_steady_cfa (insn
, frame
);
9705 /* This function processes a SET pattern for REG_CFA_REGISTER. */
9708 process_cfa_register (FILE *asm_out_file
, rtx pat
, bool unwind
)
9710 rtx dest
= SET_DEST (pat
);
9711 rtx src
= SET_SRC (pat
);
9713 int dest_regno
= REGNO (dest
);
9714 int src_regno
= REGNO (src
);
9719 /* Saving return address pointer. */
9720 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_b0
]);
9722 fprintf (asm_out_file
, "\t.save rp, r%d\n",
9723 ia64_dbx_register_number (dest_regno
));
9727 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_pr
]);
9729 fprintf (asm_out_file
, "\t.save pr, r%d\n",
9730 ia64_dbx_register_number (dest_regno
));
9733 case AR_UNAT_REGNUM
:
9734 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_unat
]);
9736 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
9737 ia64_dbx_register_number (dest_regno
));
9741 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_lc
]);
9743 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
9744 ia64_dbx_register_number (dest_regno
));
9748 /* Everything else should indicate being stored to memory. */
9753 /* This function processes a SET pattern for REG_CFA_OFFSET. */
9756 process_cfa_offset (FILE *asm_out_file
, rtx pat
, bool unwind
)
9758 rtx dest
= SET_DEST (pat
);
9759 rtx src
= SET_SRC (pat
);
9760 int src_regno
= REGNO (src
);
9765 gcc_assert (MEM_P (dest
));
9766 if (GET_CODE (XEXP (dest
, 0)) == REG
)
9768 base
= XEXP (dest
, 0);
9773 gcc_assert (GET_CODE (XEXP (dest
, 0)) == PLUS
9774 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
);
9775 base
= XEXP (XEXP (dest
, 0), 0);
9776 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
9779 if (base
== hard_frame_pointer_rtx
)
9781 saveop
= ".savepsp";
9786 gcc_assert (base
== stack_pointer_rtx
);
9790 src_regno
= REGNO (src
);
9794 gcc_assert (!current_frame_info
.r
[reg_save_b0
]);
9796 fprintf (asm_out_file
, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC
"\n",
9801 gcc_assert (!current_frame_info
.r
[reg_save_pr
]);
9803 fprintf (asm_out_file
, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC
"\n",
9808 gcc_assert (!current_frame_info
.r
[reg_save_ar_lc
]);
9810 fprintf (asm_out_file
, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC
"\n",
9815 gcc_assert (!current_frame_info
.r
[reg_save_ar_pfs
]);
9817 fprintf (asm_out_file
, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC
"\n",
9821 case AR_UNAT_REGNUM
:
9822 gcc_assert (!current_frame_info
.r
[reg_save_ar_unat
]);
9824 fprintf (asm_out_file
, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC
"\n",
9833 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
9834 1 << (src_regno
- GR_REG (4)));
9843 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
9844 1 << (src_regno
- BR_REG (1)));
9852 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
9853 1 << (src_regno
- FR_REG (2)));
9856 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
9857 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
9858 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
9859 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
9861 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
9862 1 << (src_regno
- FR_REG (12)));
9866 /* ??? For some reason we mark other general registers, even those
9867 we can't represent in the unwind info. Ignore them. */
9872 /* This function looks at a single insn and emits any directives
9873 required to unwind this insn. */
9876 ia64_asm_unwind_emit (FILE *asm_out_file
, rtx insn
)
9878 bool unwind
= ia64_except_unwind_info () == UI_TARGET
;
9879 bool frame
= dwarf2out_do_frame ();
9883 if (!unwind
&& !frame
)
9886 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
9888 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
9890 /* Restore unwind state from immediately before the epilogue. */
9891 if (need_copy_state
)
9895 fprintf (asm_out_file
, "\t.body\n");
9896 fprintf (asm_out_file
, "\t.copy_state %d\n",
9897 cfun
->machine
->state_num
);
9899 if (IA64_CHANGE_CFA_IN_EPILOGUE
)
9900 ia64_dwarf2out_def_steady_cfa (insn
, frame
);
9901 need_copy_state
= false;
9905 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
9908 /* Look for the ALLOC insn. */
9909 if (INSN_CODE (insn
) == CODE_FOR_alloc
)
9911 rtx dest
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
9912 int dest_regno
= REGNO (dest
);
9914 /* If this is the final destination for ar.pfs, then this must
9915 be the alloc in the prologue. */
9916 if (dest_regno
== current_frame_info
.r
[reg_save_ar_pfs
])
9919 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
9920 ia64_dbx_register_number (dest_regno
));
9924 /* This must be an alloc before a sibcall. We must drop the
9925 old frame info. The easiest way to drop the old frame
9926 info is to ensure we had a ".restore sp" directive
9927 followed by a new prologue. If the procedure doesn't
9928 have a memory-stack frame, we'll issue a dummy ".restore
9930 if (current_frame_info
.total_size
== 0 && !frame_pointer_needed
)
9931 /* if haven't done process_epilogue() yet, do it now */
9932 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9934 fprintf (asm_out_file
, "\t.prologue\n");
9939 handled_one
= false;
9940 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9941 switch (REG_NOTE_KIND (note
))
9943 case REG_CFA_ADJUST_CFA
:
9944 pat
= XEXP (note
, 0);
9946 pat
= PATTERN (insn
);
9947 process_cfa_adjust_cfa (asm_out_file
, pat
, insn
, unwind
, frame
);
9951 case REG_CFA_OFFSET
:
9952 pat
= XEXP (note
, 0);
9954 pat
= PATTERN (insn
);
9955 process_cfa_offset (asm_out_file
, pat
, unwind
);
9959 case REG_CFA_REGISTER
:
9960 pat
= XEXP (note
, 0);
9962 pat
= PATTERN (insn
);
9963 process_cfa_register (asm_out_file
, pat
, unwind
);
9967 case REG_FRAME_RELATED_EXPR
:
9968 case REG_CFA_DEF_CFA
:
9969 case REG_CFA_EXPRESSION
:
9970 case REG_CFA_RESTORE
:
9971 case REG_CFA_SET_VDRAP
:
9972 /* Not used in the ia64 port. */
9976 /* Not a frame-related note. */
9980 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
9981 explicit action to take. No guessing required. */
9982 gcc_assert (handled_one
);
9985 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
9988 ia64_asm_emit_except_personality (rtx personality
)
9990 fputs ("\t.personality\t", asm_out_file
);
9991 output_addr_const (asm_out_file
, personality
);
9992 fputc ('\n', asm_out_file
);
9995 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
9998 ia64_asm_init_sections (void)
10000 exception_section
= get_unnamed_section (0, output_section_asm_op
,
10004 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10006 static enum unwind_info_type
10007 ia64_debug_unwind_info (void)
10012 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
10014 static enum unwind_info_type
10015 ia64_except_unwind_info (void)
10017 /* Honor the --enable-sjlj-exceptions configure switch. */
10018 #ifdef CONFIG_UNWIND_EXCEPTIONS
10019 if (CONFIG_UNWIND_EXCEPTIONS
)
10023 /* For simplicity elsewhere in this file, indicate that all unwind
10024 info is disabled if we're not emitting unwind tables. */
10025 if (!flag_exceptions
&& !flag_unwind_tables
)
10034 IA64_BUILTIN_COPYSIGNQ
,
10035 IA64_BUILTIN_FABSQ
,
10036 IA64_BUILTIN_FLUSHRS
,
10038 IA64_BUILTIN_HUGE_VALQ
,
10042 static GTY(()) tree ia64_builtins
[(int) IA64_BUILTIN_max
];
10045 ia64_init_builtins (void)
10051 /* The __fpreg type. */
10052 fpreg_type
= make_node (REAL_TYPE
);
10053 TYPE_PRECISION (fpreg_type
) = 82;
10054 layout_type (fpreg_type
);
10055 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
10057 /* The __float80 type. */
10058 float80_type
= make_node (REAL_TYPE
);
10059 TYPE_PRECISION (float80_type
) = 80;
10060 layout_type (float80_type
);
10061 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
10063 /* The __float128 type. */
10067 tree float128_type
= make_node (REAL_TYPE
);
10069 TYPE_PRECISION (float128_type
) = 128;
10070 layout_type (float128_type
);
10071 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
10073 /* TFmode support builtins. */
10074 ftype
= build_function_type (float128_type
, void_list_node
);
10075 decl
= add_builtin_function ("__builtin_infq", ftype
,
10076 IA64_BUILTIN_INFQ
, BUILT_IN_MD
,
10078 ia64_builtins
[IA64_BUILTIN_INFQ
] = decl
;
10080 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
10081 IA64_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
10083 ia64_builtins
[IA64_BUILTIN_HUGE_VALQ
] = decl
;
10085 ftype
= build_function_type_list (float128_type
,
10088 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
10089 IA64_BUILTIN_FABSQ
, BUILT_IN_MD
,
10090 "__fabstf2", NULL_TREE
);
10091 TREE_READONLY (decl
) = 1;
10092 ia64_builtins
[IA64_BUILTIN_FABSQ
] = decl
;
10094 ftype
= build_function_type_list (float128_type
,
10098 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
10099 IA64_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
10100 "__copysigntf3", NULL_TREE
);
10101 TREE_READONLY (decl
) = 1;
10102 ia64_builtins
[IA64_BUILTIN_COPYSIGNQ
] = decl
;
10105 /* Under HPUX, this is a synonym for "long double". */
10106 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
10109 /* Fwrite on VMS is non-standard. */
10110 if (TARGET_ABI_OPEN_VMS
)
10112 implicit_built_in_decls
[(int) BUILT_IN_FWRITE
] = NULL_TREE
;
10113 implicit_built_in_decls
[(int) BUILT_IN_FWRITE_UNLOCKED
] = NULL_TREE
;
10116 #define def_builtin(name, type, code) \
10117 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10120 decl
= def_builtin ("__builtin_ia64_bsp",
10121 build_function_type (ptr_type_node
, void_list_node
),
10123 ia64_builtins
[IA64_BUILTIN_BSP
] = decl
;
10125 decl
= def_builtin ("__builtin_ia64_flushrs",
10126 build_function_type (void_type_node
, void_list_node
),
10127 IA64_BUILTIN_FLUSHRS
);
10128 ia64_builtins
[IA64_BUILTIN_FLUSHRS
] = decl
;
10134 if (built_in_decls
[BUILT_IN_FINITE
])
10135 set_user_assembler_name (built_in_decls
[BUILT_IN_FINITE
],
10137 if (built_in_decls
[BUILT_IN_FINITEF
])
10138 set_user_assembler_name (built_in_decls
[BUILT_IN_FINITEF
],
10140 if (built_in_decls
[BUILT_IN_FINITEL
])
10141 set_user_assembler_name (built_in_decls
[BUILT_IN_FINITEL
],
10147 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10148 enum machine_mode mode ATTRIBUTE_UNUSED
,
10149 int ignore ATTRIBUTE_UNUSED
)
10151 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10152 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10156 case IA64_BUILTIN_BSP
:
10157 if (! target
|| ! register_operand (target
, DImode
))
10158 target
= gen_reg_rtx (DImode
);
10159 emit_insn (gen_bsp_value (target
));
10160 #ifdef POINTERS_EXTEND_UNSIGNED
10161 target
= convert_memory_address (ptr_mode
, target
);
10165 case IA64_BUILTIN_FLUSHRS
:
10166 emit_insn (gen_flushrs ());
10169 case IA64_BUILTIN_INFQ
:
10170 case IA64_BUILTIN_HUGE_VALQ
:
10172 REAL_VALUE_TYPE inf
;
10176 tmp
= CONST_DOUBLE_FROM_REAL_VALUE (inf
, mode
);
10178 tmp
= validize_mem (force_const_mem (mode
, tmp
));
10181 target
= gen_reg_rtx (mode
);
10183 emit_move_insn (target
, tmp
);
10187 case IA64_BUILTIN_FABSQ
:
10188 case IA64_BUILTIN_COPYSIGNQ
:
10189 return expand_call (exp
, target
, ignore
);
10192 gcc_unreachable ();
10198 /* Return the ia64 builtin for CODE. */
10201 ia64_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10203 if (code
>= IA64_BUILTIN_max
)
10204 return error_mark_node
;
10206 return ia64_builtins
[code
];
10209 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10210 most significant bits of the stack slot. */
10213 ia64_hpux_function_arg_padding (enum machine_mode mode
, const_tree type
)
10215 /* Exception to normal case for structures/unions/etc. */
10217 if (type
&& AGGREGATE_TYPE_P (type
)
10218 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
10221 /* Fall back to the default. */
10222 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
10225 /* Emit text to declare externally defined variables and functions, because
10226 the Intel assembler does not support undefined externals. */
10229 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
10231 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10232 set in order to avoid putting out names that are never really
10234 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
10236 /* maybe_assemble_visibility will return 1 if the assembler
10237 visibility directive is output. */
10238 int need_visibility
= ((*targetm
.binds_local_p
) (decl
)
10239 && maybe_assemble_visibility (decl
));
10241 #ifdef DO_CRTL_NAMES
10245 /* GNU as does not need anything here, but the HP linker does
10246 need something for external functions. */
10247 if ((TARGET_HPUX_LD
|| !TARGET_GNU_AS
)
10248 && TREE_CODE (decl
) == FUNCTION_DECL
)
10249 (*targetm
.asm_out
.globalize_decl_name
) (file
, decl
);
10250 else if (need_visibility
&& !TARGET_GNU_AS
)
10251 (*targetm
.asm_out
.globalize_label
) (file
, name
);
10255 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10256 modes of word_mode and larger. Rename the TFmode libfuncs using the
10257 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10258 backward compatibility. */
10261 ia64_init_libfuncs (void)
10263 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
10264 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
10265 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
10266 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
10268 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
10269 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
10270 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
10271 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
10272 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
10274 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
10275 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
10276 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
10277 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
10278 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
10279 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
10281 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
10282 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
10283 set_conv_libfunc (sfix_optab
, TImode
, TFmode
, "_U_Qfcnvfxt_quad_to_quad");
10284 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
10285 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
10287 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
10288 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
10289 set_conv_libfunc (sfloat_optab
, TFmode
, TImode
, "_U_Qfcnvxf_quad_to_quad");
10290 /* HP-UX 11.23 libc does not have a function for unsigned
10291 SImode-to-TFmode conversion. */
10292 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_U_Qfcnvxuf_dbl_to_quad");
10295 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10298 ia64_hpux_init_libfuncs (void)
10300 ia64_init_libfuncs ();
10302 /* The HP SI millicode division and mod functions expect DI arguments.
10303 By turning them off completely we avoid using both libgcc and the
10304 non-standard millicode routines and use the HP DI millicode routines
10307 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10308 set_optab_libfunc (udiv_optab
, SImode
, 0);
10309 set_optab_libfunc (smod_optab
, SImode
, 0);
10310 set_optab_libfunc (umod_optab
, SImode
, 0);
10312 set_optab_libfunc (sdiv_optab
, DImode
, "__milli_divI");
10313 set_optab_libfunc (udiv_optab
, DImode
, "__milli_divU");
10314 set_optab_libfunc (smod_optab
, DImode
, "__milli_remI");
10315 set_optab_libfunc (umod_optab
, DImode
, "__milli_remU");
10317 /* HP-UX libc has TF min/max/abs routines in it. */
10318 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
10319 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
10320 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
10322 /* ia64_expand_compare uses this. */
10323 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
10325 /* These should never be used. */
10326 set_optab_libfunc (eq_optab
, TFmode
, 0);
10327 set_optab_libfunc (ne_optab
, TFmode
, 0);
10328 set_optab_libfunc (gt_optab
, TFmode
, 0);
10329 set_optab_libfunc (ge_optab
, TFmode
, 0);
10330 set_optab_libfunc (lt_optab
, TFmode
, 0);
10331 set_optab_libfunc (le_optab
, TFmode
, 0);
10334 /* Rename the division and modulus functions in VMS. */
10337 ia64_vms_init_libfuncs (void)
10339 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10340 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10341 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10342 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10343 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10344 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10345 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10346 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10347 abort_libfunc
= init_one_libfunc ("decc$abort");
10348 memcmp_libfunc
= init_one_libfunc ("decc$memcmp");
10349 #ifdef MEM_LIBFUNCS_INIT
10354 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10355 the HPUX conventions. */
10358 ia64_sysv4_init_libfuncs (void)
10360 ia64_init_libfuncs ();
10362 /* These functions are not part of the HPUX TFmode interface. We
10363 use them instead of _U_Qfcmp, which doesn't work the way we
10365 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
10366 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
10367 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
10368 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
10369 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
10370 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
10372 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10373 glibc doesn't have them. */
10379 ia64_soft_fp_init_libfuncs (void)
10384 ia64_vms_valid_pointer_mode (enum machine_mode mode
)
10386 return (mode
== SImode
|| mode
== DImode
);
10389 /* For HPUX, it is illegal to have relocations in shared segments. */
10392 ia64_hpux_reloc_rw_mask (void)
10397 /* For others, relax this so that relocations to local data goes in
10398 read-only segments, but we still cannot allow global relocations
10399 in read-only segments. */
10402 ia64_reloc_rw_mask (void)
10404 return flag_pic
? 3 : 2;
10407 /* Return the section to use for X. The only special thing we do here
10408 is to honor small data. */
10411 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
10412 unsigned HOST_WIDE_INT align
)
10414 if (GET_MODE_SIZE (mode
) > 0
10415 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
10416 && !TARGET_NO_SDATA
)
10417 return sdata_section
;
10419 return default_elf_select_rtx_section (mode
, x
, align
);
10422 static unsigned int
10423 ia64_section_type_flags (tree decl
, const char *name
, int reloc
)
10425 unsigned int flags
= 0;
10427 if (strcmp (name
, ".sdata") == 0
10428 || strncmp (name
, ".sdata.", 7) == 0
10429 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
10430 || strncmp (name
, ".sdata2.", 8) == 0
10431 || strncmp (name
, ".gnu.linkonce.s2.", 17) == 0
10432 || strcmp (name
, ".sbss") == 0
10433 || strncmp (name
, ".sbss.", 6) == 0
10434 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
10435 flags
= SECTION_SMALL
;
10437 #if TARGET_ABI_OPEN_VMS
10438 if (decl
&& DECL_ATTRIBUTES (decl
)
10439 && lookup_attribute ("common_object", DECL_ATTRIBUTES (decl
)))
10440 flags
|= SECTION_VMS_OVERLAY
;
10443 flags
|= default_section_type_flags (decl
, name
, reloc
);
10447 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10448 structure type and that the address of that type should be passed
10449 in out0, rather than in r8. */
10452 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
10454 tree ret_type
= TREE_TYPE (fntype
);
10456 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10457 as the structure return address parameter, if the return value
10458 type has a non-trivial copy constructor or destructor. It is not
10459 clear if this same convention should be used for other
10460 programming languages. Until G++ 3.4, we incorrectly used r8 for
10461 these return values. */
10462 return (abi_version_at_least (2)
10464 && TYPE_MODE (ret_type
) == BLKmode
10465 && TREE_ADDRESSABLE (ret_type
)
10466 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
10469 /* Output the assembler code for a thunk function. THUNK_DECL is the
10470 declaration for the thunk function itself, FUNCTION is the decl for
10471 the target function. DELTA is an immediate constant offset to be
10472 added to THIS. If VCALL_OFFSET is nonzero, the word at
10473 *(*this + vcall_offset) should be added to THIS. */
10476 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
10477 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10480 rtx this_rtx
, insn
, funexp
;
10481 unsigned int this_parmno
;
10482 unsigned int this_regno
;
10485 reload_completed
= 1;
10486 epilogue_completed
= 1;
10488 /* Set things up as ia64_expand_prologue might. */
10489 last_scratch_gr_reg
= 15;
10491 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
10492 current_frame_info
.spill_cfa_off
= -16;
10493 current_frame_info
.n_input_regs
= 1;
10494 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
10496 /* Mark the end of the (empty) prologue. */
10497 emit_note (NOTE_INSN_PROLOGUE_END
);
10499 /* Figure out whether "this" will be the first parameter (the
10500 typical case) or the second parameter (as happens when the
10501 virtual function returns certain class objects). */
10503 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
10505 this_regno
= IN_REG (this_parmno
);
10506 if (!TARGET_REG_NAMES
)
10507 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
10509 this_rtx
= gen_rtx_REG (Pmode
, this_regno
);
10511 /* Apply the constant offset, if required. */
10512 delta_rtx
= GEN_INT (delta
);
10515 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
10516 REG_POINTER (tmp
) = 1;
10517 if (delta
&& satisfies_constraint_I (delta_rtx
))
10519 emit_insn (gen_ptr_extend_plus_imm (this_rtx
, tmp
, delta_rtx
));
10523 emit_insn (gen_ptr_extend (this_rtx
, tmp
));
10527 if (!satisfies_constraint_I (delta_rtx
))
10529 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10530 emit_move_insn (tmp
, delta_rtx
);
10533 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, delta_rtx
));
10536 /* Apply the offset from the vtable, if required. */
10539 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10540 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10544 rtx t
= gen_rtx_REG (ptr_mode
, 2);
10545 REG_POINTER (t
) = 1;
10546 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this_rtx
));
10547 if (satisfies_constraint_I (vcall_offset_rtx
))
10549 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
, vcall_offset_rtx
));
10553 emit_insn (gen_ptr_extend (tmp
, t
));
10556 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
10560 if (!satisfies_constraint_J (vcall_offset_rtx
))
10562 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
10563 emit_move_insn (tmp2
, vcall_offset_rtx
);
10564 vcall_offset_rtx
= tmp2
;
10566 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
10570 emit_insn (gen_zero_extendsidi2 (tmp
, gen_rtx_MEM (ptr_mode
, tmp
)));
10572 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
10574 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
10577 /* Generate a tail call to the target function. */
10578 if (! TREE_USED (function
))
10580 assemble_external (function
);
10581 TREE_USED (function
) = 1;
10583 funexp
= XEXP (DECL_RTL (function
), 0);
10584 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10585 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
10586 insn
= get_last_insn ();
10587 SIBLING_CALL_P (insn
) = 1;
10589 /* Code generation for calls relies on splitting. */
10590 reload_completed
= 1;
10591 epilogue_completed
= 1;
10592 try_split (PATTERN (insn
), insn
, 0);
10596 /* Run just enough of rest_of_compilation to get the insns emitted.
10597 There's not really enough bulk here to make other passes such as
10598 instruction scheduling worth while. Note that use_thunk calls
10599 assemble_start_function and assemble_end_function. */
10601 insn_locators_alloc ();
10602 emit_all_insn_group_barriers (NULL
);
10603 insn
= get_insns ();
10604 shorten_branches (insn
);
10605 final_start_function (insn
, file
, 1);
10606 final (insn
, file
, 1);
10607 final_end_function ();
10609 reload_completed
= 0;
10610 epilogue_completed
= 0;
10613 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10616 ia64_struct_value_rtx (tree fntype
,
10617 int incoming ATTRIBUTE_UNUSED
)
10619 if (TARGET_ABI_OPEN_VMS
||
10620 (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
)))
10622 return gen_rtx_REG (Pmode
, GR_REG (8));
10626 ia64_scalar_mode_supported_p (enum machine_mode mode
)
10652 ia64_vector_mode_supported_p (enum machine_mode mode
)
10669 /* Implement the FUNCTION_PROFILER macro. */
10672 ia64_output_function_profiler (FILE *file
, int labelno
)
10674 bool indirect_call
;
10676 /* If the function needs a static chain and the static chain
10677 register is r15, we use an indirect call so as to bypass
10678 the PLT stub in case the executable is dynamically linked,
10679 because the stub clobbers r15 as per 5.3.6 of the psABI.
10680 We don't need to do that in non canonical PIC mode. */
10682 if (cfun
->static_chain_decl
&& !TARGET_NO_PIC
&& !TARGET_AUTO_PIC
)
10684 gcc_assert (STATIC_CHAIN_REGNUM
== 15);
10685 indirect_call
= true;
10688 indirect_call
= false;
10691 fputs ("\t.prologue 4, r40\n", file
);
10693 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file
);
10694 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file
);
10696 if (NO_PROFILE_COUNTERS
)
10697 fputs ("\tmov out3 = r0\n", file
);
10701 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10703 if (TARGET_AUTO_PIC
)
10704 fputs ("\tmovl out3 = @gprel(", file
);
10706 fputs ("\taddl out3 = @ltoff(", file
);
10707 assemble_name (file
, buf
);
10708 if (TARGET_AUTO_PIC
)
10709 fputs (")\n", file
);
10711 fputs ("), r1\n", file
);
10715 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file
);
10716 fputs ("\t;;\n", file
);
10718 fputs ("\t.save rp, r42\n", file
);
10719 fputs ("\tmov out2 = b0\n", file
);
10721 fputs ("\tld8 r14 = [r14]\n\t;;\n", file
);
10722 fputs ("\t.body\n", file
);
10723 fputs ("\tmov out1 = r1\n", file
);
10726 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file
);
10727 fputs ("\tmov b6 = r16\n", file
);
10728 fputs ("\tld8 r1 = [r14]\n", file
);
10729 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file
);
10732 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file
);
10735 static GTY(()) rtx mcount_func_rtx
;
10737 gen_mcount_func_rtx (void)
10739 if (!mcount_func_rtx
)
10740 mcount_func_rtx
= init_one_libfunc ("_mcount");
10741 return mcount_func_rtx
;
10745 ia64_profile_hook (int labelno
)
10749 if (NO_PROFILE_COUNTERS
)
10750 label
= const0_rtx
;
10754 const char *label_name
;
10755 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10756 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
10757 label
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
10758 SYMBOL_REF_FLAGS (label
) = SYMBOL_FLAG_LOCAL
;
10760 ip
= gen_reg_rtx (Pmode
);
10761 emit_insn (gen_ip_value (ip
));
10762 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL
,
10764 gen_rtx_REG (Pmode
, BR_REG (0)), Pmode
,
10769 /* Return the mangling of TYPE if it is an extended fundamental type. */
10771 static const char *
10772 ia64_mangle_type (const_tree type
)
10774 type
= TYPE_MAIN_VARIANT (type
);
10776 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
10777 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
10780 /* On HP-UX, "long double" is mangled as "e" so __float128 is
10782 if (!TARGET_HPUX
&& TYPE_MODE (type
) == TFmode
)
10784 /* On HP-UX, "e" is not available as a mangling of __float80 so use
10785 an extended mangling. Elsewhere, "e" is available since long
10786 double is 80 bits. */
10787 if (TYPE_MODE (type
) == XFmode
)
10788 return TARGET_HPUX
? "u9__float80" : "e";
10789 if (TYPE_MODE (type
) == RFmode
)
10790 return "u7__fpreg";
10794 /* Return the diagnostic message string if conversion from FROMTYPE to
10795 TOTYPE is not allowed, NULL otherwise. */
10796 static const char *
10797 ia64_invalid_conversion (const_tree fromtype
, const_tree totype
)
10799 /* Reject nontrivial conversion to or from __fpreg. */
10800 if (TYPE_MODE (fromtype
) == RFmode
10801 && TYPE_MODE (totype
) != RFmode
10802 && TYPE_MODE (totype
) != VOIDmode
)
10803 return N_("invalid conversion from %<__fpreg%>");
10804 if (TYPE_MODE (totype
) == RFmode
10805 && TYPE_MODE (fromtype
) != RFmode
)
10806 return N_("invalid conversion to %<__fpreg%>");
10810 /* Return the diagnostic message string if the unary operation OP is
10811 not permitted on TYPE, NULL otherwise. */
10812 static const char *
10813 ia64_invalid_unary_op (int op
, const_tree type
)
10815 /* Reject operations on __fpreg other than unary + or &. */
10816 if (TYPE_MODE (type
) == RFmode
10817 && op
!= CONVERT_EXPR
10818 && op
!= ADDR_EXPR
)
10819 return N_("invalid operation on %<__fpreg%>");
10823 /* Return the diagnostic message string if the binary operation OP is
10824 not permitted on TYPE1 and TYPE2, NULL otherwise. */
10825 static const char *
10826 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
10828 /* Reject operations on __fpreg. */
10829 if (TYPE_MODE (type1
) == RFmode
|| TYPE_MODE (type2
) == RFmode
)
10830 return N_("invalid operation on %<__fpreg%>");
10834 /* Implement overriding of the optimization options. */
10836 ia64_option_optimization (int level ATTRIBUTE_UNUSED
,
10837 int size ATTRIBUTE_UNUSED
)
10839 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
10840 SUBTARGET_OPTIMIZATION_OPTIONS
;
10843 /* Let the scheduler form additional regions. */
10844 set_param_value ("max-sched-extend-regions-iters", 2);
10846 /* Set the default values for cache-related parameters. */
10847 set_param_value ("simultaneous-prefetches", 6);
10848 set_param_value ("l1-cache-line-size", 32);
10850 set_param_value("sched-mem-true-dep-cost", 4);
10853 /* HP-UX version_id attribute.
10854 For object foo, if the version_id is set to 1234 put out an alias
10855 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
10856 other than an alias statement because it is an illegal symbol name. */
10859 ia64_handle_version_id_attribute (tree
*node ATTRIBUTE_UNUSED
,
10860 tree name ATTRIBUTE_UNUSED
,
10862 int flags ATTRIBUTE_UNUSED
,
10863 bool *no_add_attrs
)
10865 tree arg
= TREE_VALUE (args
);
10867 if (TREE_CODE (arg
) != STRING_CST
)
10869 error("version attribute is not a string");
10870 *no_add_attrs
= true;
10876 /* Target hook for c_mode_for_suffix. */
10878 static enum machine_mode
10879 ia64_c_mode_for_suffix (char suffix
)
10889 static enum machine_mode
10890 ia64_promote_function_mode (const_tree type
,
10891 enum machine_mode mode
,
10893 const_tree funtype
,
10896 /* Special processing required for OpenVMS ... */
10898 if (!TARGET_ABI_OPEN_VMS
)
10899 return default_promote_function_mode(type
, mode
, punsignedp
, funtype
,
10902 /* HP OpenVMS Calling Standard dated June, 2004, that describes
10903 HP OpenVMS I64 Version 8.2EFT,
10904 chapter 4 "OpenVMS I64 Conventions"
10905 section 4.7 "Procedure Linkage"
10906 subsection 4.7.5.2, "Normal Register Parameters"
10908 "Unsigned integral (except unsigned 32-bit), set, and VAX floating-point
10909 values passed in registers are zero-filled; signed integral values as
10910 well as unsigned 32-bit integral values are sign-extended to 64 bits.
10911 For all other types passed in the general registers, unused bits are
10914 if (!AGGREGATE_TYPE_P (type
)
10915 && GET_MODE_CLASS (mode
) == MODE_INT
10916 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
10918 if (mode
== SImode
)
10923 return promote_mode (type
, mode
, punsignedp
);
10926 static GTY(()) rtx ia64_dconst_0_5_rtx
;
10929 ia64_dconst_0_5 (void)
10931 if (! ia64_dconst_0_5_rtx
)
10933 REAL_VALUE_TYPE rv
;
10934 real_from_string (&rv
, "0.5");
10935 ia64_dconst_0_5_rtx
= const_double_from_real_value (rv
, DFmode
);
10937 return ia64_dconst_0_5_rtx
;
10940 static GTY(()) rtx ia64_dconst_0_375_rtx
;
10943 ia64_dconst_0_375 (void)
10945 if (! ia64_dconst_0_375_rtx
)
10947 REAL_VALUE_TYPE rv
;
10948 real_from_string (&rv
, "0.375");
10949 ia64_dconst_0_375_rtx
= const_double_from_real_value (rv
, DFmode
);
10951 return ia64_dconst_0_375_rtx
;
10955 #include "gt-ia64.h"