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[gcc.git] / gcc / config / ia64 / ia64.c
1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
30 #include "calls.h"
31 #include "varasm.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "recog.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "except.h"
43 #include "function.h"
44 #include "ggc.h"
45 #include "basic-block.h"
46 #include "libfuncs.h"
47 #include "diagnostic-core.h"
48 #include "sched-int.h"
49 #include "timevar.h"
50 #include "target.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "tm_p.h"
54 #include "hash-table.h"
55 #include "langhooks.h"
56 #include "pointer-set.h"
57 #include "vec.h"
58 #include "basic-block.h"
59 #include "tree-ssa-alias.h"
60 #include "internal-fn.h"
61 #include "gimple-fold.h"
62 #include "tree-eh.h"
63 #include "gimple-expr.h"
64 #include "is-a.h"
65 #include "gimple.h"
66 #include "gimplify.h"
67 #include "intl.h"
68 #include "df.h"
69 #include "debug.h"
70 #include "params.h"
71 #include "dbgcnt.h"
72 #include "tm-constrs.h"
73 #include "sel-sched.h"
74 #include "reload.h"
75 #include "opts.h"
76 #include "dumpfile.h"
77
78 /* This is used for communication between ASM_OUTPUT_LABEL and
79 ASM_OUTPUT_LABELREF. */
80 int ia64_asm_output_label = 0;
81
82 /* Register names for ia64_expand_prologue. */
83 static const char * const ia64_reg_numbers[96] =
84 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
85 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
86 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
87 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
88 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
89 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
90 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
91 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
92 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
93 "r104","r105","r106","r107","r108","r109","r110","r111",
94 "r112","r113","r114","r115","r116","r117","r118","r119",
95 "r120","r121","r122","r123","r124","r125","r126","r127"};
96
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_input_reg_names[8] =
99 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
100
101 /* ??? These strings could be shared with REGISTER_NAMES. */
102 static const char * const ia64_local_reg_names[80] =
103 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
104 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
105 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
106 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
107 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
108 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
109 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
110 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
111 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
112 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
113
114 /* ??? These strings could be shared with REGISTER_NAMES. */
115 static const char * const ia64_output_reg_names[8] =
116 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
117
118 /* Variables which are this size or smaller are put in the sdata/sbss
119 sections. */
120
121 unsigned int ia64_section_threshold;
122
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
125 int bundling_p = 0;
126
127 enum ia64_frame_regs
128 {
129 reg_fp,
130 reg_save_b0,
131 reg_save_pr,
132 reg_save_ar_pfs,
133 reg_save_ar_unat,
134 reg_save_ar_lc,
135 reg_save_gp,
136 number_of_ia64_frame_regs
137 };
138
139 /* Structure to be filled in by ia64_compute_frame_size with register
140 save masks and offsets for the current function. */
141
142 struct ia64_frame_info
143 {
144 HOST_WIDE_INT total_size; /* size of the stack frame, not including
145 the caller's scratch area. */
146 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
147 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
148 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
149 HARD_REG_SET mask; /* mask of saved registers. */
150 unsigned int gr_used_mask; /* mask of registers in use as gr spill
151 registers or long-term scratches. */
152 int n_spilled; /* number of spilled registers. */
153 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
154 int n_input_regs; /* number of input registers used. */
155 int n_local_regs; /* number of local registers used. */
156 int n_output_regs; /* number of output registers used. */
157 int n_rotate_regs; /* number of rotating registers used. */
158
159 char need_regstk; /* true if a .regstk directive needed. */
160 char initialized; /* true if the data is finalized. */
161 };
162
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info;
165 /* The actual registers that are emitted. */
166 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
167 \f
168 static int ia64_first_cycle_multipass_dfa_lookahead (void);
169 static void ia64_dependencies_evaluation_hook (rtx, rtx);
170 static void ia64_init_dfa_pre_cycle_insn (void);
171 static rtx ia64_dfa_pre_cycle_insn (void);
172 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
173 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
174 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
175 static void ia64_h_i_d_extended (void);
176 static void * ia64_alloc_sched_context (void);
177 static void ia64_init_sched_context (void *, bool);
178 static void ia64_set_sched_context (void *);
179 static void ia64_clear_sched_context (void *);
180 static void ia64_free_sched_context (void *);
181 static int ia64_mode_to_int (enum machine_mode);
182 static void ia64_set_sched_flags (spec_info_t);
183 static ds_t ia64_get_insn_spec_ds (rtx);
184 static ds_t ia64_get_insn_checked_ds (rtx);
185 static bool ia64_skip_rtx_p (const_rtx);
186 static int ia64_speculate_insn (rtx, ds_t, rtx *);
187 static bool ia64_needs_block_p (ds_t);
188 static rtx ia64_gen_spec_check (rtx, rtx, ds_t);
189 static int ia64_spec_check_p (rtx);
190 static int ia64_spec_check_src_p (rtx);
191 static rtx gen_tls_get_addr (void);
192 static rtx gen_thread_pointer (void);
193 static int find_gr_spill (enum ia64_frame_regs, int);
194 static int next_scratch_gr_reg (void);
195 static void mark_reg_gr_used_mask (rtx, void *);
196 static void ia64_compute_frame_size (HOST_WIDE_INT);
197 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
198 static void finish_spill_pointers (void);
199 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
200 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
201 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
202 static rtx gen_movdi_x (rtx, rtx, rtx);
203 static rtx gen_fr_spill_x (rtx, rtx, rtx);
204 static rtx gen_fr_restore_x (rtx, rtx, rtx);
205
206 static void ia64_option_override (void);
207 static bool ia64_can_eliminate (const int, const int);
208 static enum machine_mode hfa_element_mode (const_tree, bool);
209 static void ia64_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
210 tree, int *, int);
211 static int ia64_arg_partial_bytes (cumulative_args_t, enum machine_mode,
212 tree, bool);
213 static rtx ia64_function_arg_1 (cumulative_args_t, enum machine_mode,
214 const_tree, bool, bool);
215 static rtx ia64_function_arg (cumulative_args_t, enum machine_mode,
216 const_tree, bool);
217 static rtx ia64_function_incoming_arg (cumulative_args_t,
218 enum machine_mode, const_tree, bool);
219 static void ia64_function_arg_advance (cumulative_args_t, enum machine_mode,
220 const_tree, bool);
221 static unsigned int ia64_function_arg_boundary (enum machine_mode,
222 const_tree);
223 static bool ia64_function_ok_for_sibcall (tree, tree);
224 static bool ia64_return_in_memory (const_tree, const_tree);
225 static rtx ia64_function_value (const_tree, const_tree, bool);
226 static rtx ia64_libcall_value (enum machine_mode, const_rtx);
227 static bool ia64_function_value_regno_p (const unsigned int);
228 static int ia64_register_move_cost (enum machine_mode, reg_class_t,
229 reg_class_t);
230 static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t,
231 bool);
232 static bool ia64_rtx_costs (rtx, int, int, int, int *, bool);
233 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
234 static void fix_range (const char *);
235 static struct machine_function * ia64_init_machine_status (void);
236 static void emit_insn_group_barriers (FILE *);
237 static void emit_all_insn_group_barriers (FILE *);
238 static void final_emit_insn_group_barriers (FILE *);
239 static void emit_predicate_relation_info (void);
240 static void ia64_reorg (void);
241 static bool ia64_in_small_data_p (const_tree);
242 static void process_epilogue (FILE *, rtx, bool, bool);
243
244 static bool ia64_assemble_integer (rtx, unsigned int, int);
245 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
246 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
247 static void ia64_output_function_end_prologue (FILE *);
248
249 static void ia64_print_operand (FILE *, rtx, int);
250 static void ia64_print_operand_address (FILE *, rtx);
251 static bool ia64_print_operand_punct_valid_p (unsigned char code);
252
253 static int ia64_issue_rate (void);
254 static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t);
255 static void ia64_sched_init (FILE *, int, int);
256 static void ia64_sched_init_global (FILE *, int, int);
257 static void ia64_sched_finish_global (FILE *, int);
258 static void ia64_sched_finish (FILE *, int);
259 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
260 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
261 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
262 static int ia64_variable_issue (FILE *, int, rtx, int);
263
264 static void ia64_asm_unwind_emit (FILE *, rtx);
265 static void ia64_asm_emit_except_personality (rtx);
266 static void ia64_asm_init_sections (void);
267
268 static enum unwind_info_type ia64_debug_unwind_info (void);
269
270 static struct bundle_state *get_free_bundle_state (void);
271 static void free_bundle_state (struct bundle_state *);
272 static void initiate_bundle_states (void);
273 static void finish_bundle_states (void);
274 static int insert_bundle_state (struct bundle_state *);
275 static void initiate_bundle_state_table (void);
276 static void finish_bundle_state_table (void);
277 static int try_issue_nops (struct bundle_state *, int);
278 static int try_issue_insn (struct bundle_state *, rtx);
279 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
280 static int get_max_pos (state_t);
281 static int get_template (state_t, int);
282
283 static rtx get_next_important_insn (rtx, rtx);
284 static bool important_for_bundling_p (rtx);
285 static bool unknown_for_bundling_p (rtx);
286 static void bundling (FILE *, int, rtx, rtx);
287
288 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
289 HOST_WIDE_INT, tree);
290 static void ia64_file_start (void);
291 static void ia64_globalize_decl_name (FILE *, tree);
292
293 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
294 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
295 static section *ia64_select_rtx_section (enum machine_mode, rtx,
296 unsigned HOST_WIDE_INT);
297 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
298 ATTRIBUTE_UNUSED;
299 static unsigned int ia64_section_type_flags (tree, const char *, int);
300 static void ia64_init_libfuncs (void)
301 ATTRIBUTE_UNUSED;
302 static void ia64_hpux_init_libfuncs (void)
303 ATTRIBUTE_UNUSED;
304 static void ia64_sysv4_init_libfuncs (void)
305 ATTRIBUTE_UNUSED;
306 static void ia64_vms_init_libfuncs (void)
307 ATTRIBUTE_UNUSED;
308 static void ia64_soft_fp_init_libfuncs (void)
309 ATTRIBUTE_UNUSED;
310 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
311 ATTRIBUTE_UNUSED;
312 static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
313 ATTRIBUTE_UNUSED;
314
315 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
316 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
317 static void ia64_encode_section_info (tree, rtx, int);
318 static rtx ia64_struct_value_rtx (tree, int);
319 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
320 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
321 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
322 static bool ia64_legitimate_constant_p (enum machine_mode, rtx);
323 static bool ia64_legitimate_address_p (enum machine_mode, rtx, bool);
324 static bool ia64_cannot_force_const_mem (enum machine_mode, rtx);
325 static const char *ia64_mangle_type (const_tree);
326 static const char *ia64_invalid_conversion (const_tree, const_tree);
327 static const char *ia64_invalid_unary_op (int, const_tree);
328 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
329 static enum machine_mode ia64_c_mode_for_suffix (char);
330 static void ia64_trampoline_init (rtx, tree, rtx);
331 static void ia64_override_options_after_change (void);
332 static bool ia64_member_type_forces_blk (const_tree, enum machine_mode);
333
334 static tree ia64_builtin_decl (unsigned, bool);
335
336 static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t);
337 static enum machine_mode ia64_get_reg_raw_mode (int regno);
338 static section * ia64_hpux_function_section (tree, enum node_frequency,
339 bool, bool);
340
341 static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
342 const unsigned char *sel);
343
344 #define MAX_VECT_LEN 8
345
346 struct expand_vec_perm_d
347 {
348 rtx target, op0, op1;
349 unsigned char perm[MAX_VECT_LEN];
350 enum machine_mode vmode;
351 unsigned char nelt;
352 bool one_operand_p;
353 bool testing_p;
354 };
355
356 static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d);
357
358 \f
359 /* Table of valid machine attributes. */
360 static const struct attribute_spec ia64_attribute_table[] =
361 {
362 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
363 affects_type_identity } */
364 { "syscall_linkage", 0, 0, false, true, true, NULL, false },
365 { "model", 1, 1, true, false, false, ia64_handle_model_attribute,
366 false },
367 #if TARGET_ABI_OPEN_VMS
368 { "common_object", 1, 1, true, false, false,
369 ia64_vms_common_object_attribute, false },
370 #endif
371 { "version_id", 1, 1, true, false, false,
372 ia64_handle_version_id_attribute, false },
373 { NULL, 0, 0, false, false, false, NULL, false }
374 };
375
376 /* Initialize the GCC target structure. */
377 #undef TARGET_ATTRIBUTE_TABLE
378 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
379
380 #undef TARGET_INIT_BUILTINS
381 #define TARGET_INIT_BUILTINS ia64_init_builtins
382
383 #undef TARGET_EXPAND_BUILTIN
384 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
385
386 #undef TARGET_BUILTIN_DECL
387 #define TARGET_BUILTIN_DECL ia64_builtin_decl
388
389 #undef TARGET_ASM_BYTE_OP
390 #define TARGET_ASM_BYTE_OP "\tdata1\t"
391 #undef TARGET_ASM_ALIGNED_HI_OP
392 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
393 #undef TARGET_ASM_ALIGNED_SI_OP
394 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
395 #undef TARGET_ASM_ALIGNED_DI_OP
396 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
397 #undef TARGET_ASM_UNALIGNED_HI_OP
398 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
399 #undef TARGET_ASM_UNALIGNED_SI_OP
400 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
401 #undef TARGET_ASM_UNALIGNED_DI_OP
402 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
403 #undef TARGET_ASM_INTEGER
404 #define TARGET_ASM_INTEGER ia64_assemble_integer
405
406 #undef TARGET_OPTION_OVERRIDE
407 #define TARGET_OPTION_OVERRIDE ia64_option_override
408
409 #undef TARGET_ASM_FUNCTION_PROLOGUE
410 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
411 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
412 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
413 #undef TARGET_ASM_FUNCTION_EPILOGUE
414 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
415
416 #undef TARGET_PRINT_OPERAND
417 #define TARGET_PRINT_OPERAND ia64_print_operand
418 #undef TARGET_PRINT_OPERAND_ADDRESS
419 #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address
420 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
421 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p
422
423 #undef TARGET_IN_SMALL_DATA_P
424 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
425
426 #undef TARGET_SCHED_ADJUST_COST_2
427 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
428 #undef TARGET_SCHED_ISSUE_RATE
429 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
430 #undef TARGET_SCHED_VARIABLE_ISSUE
431 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
432 #undef TARGET_SCHED_INIT
433 #define TARGET_SCHED_INIT ia64_sched_init
434 #undef TARGET_SCHED_FINISH
435 #define TARGET_SCHED_FINISH ia64_sched_finish
436 #undef TARGET_SCHED_INIT_GLOBAL
437 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
438 #undef TARGET_SCHED_FINISH_GLOBAL
439 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
440 #undef TARGET_SCHED_REORDER
441 #define TARGET_SCHED_REORDER ia64_sched_reorder
442 #undef TARGET_SCHED_REORDER2
443 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
444
445 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
446 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
447
448 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
449 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
450
451 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
452 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
453 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
454 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
455
456 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
457 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
458 ia64_first_cycle_multipass_dfa_lookahead_guard
459
460 #undef TARGET_SCHED_DFA_NEW_CYCLE
461 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
462
463 #undef TARGET_SCHED_H_I_D_EXTENDED
464 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
465
466 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
467 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
468
469 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
470 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
471
472 #undef TARGET_SCHED_SET_SCHED_CONTEXT
473 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
474
475 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
476 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
477
478 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
479 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
480
481 #undef TARGET_SCHED_SET_SCHED_FLAGS
482 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
483
484 #undef TARGET_SCHED_GET_INSN_SPEC_DS
485 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
486
487 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
488 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
489
490 #undef TARGET_SCHED_SPECULATE_INSN
491 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
492
493 #undef TARGET_SCHED_NEEDS_BLOCK_P
494 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
495
496 #undef TARGET_SCHED_GEN_SPEC_CHECK
497 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
498
499 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
500 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
501 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
502
503 #undef TARGET_SCHED_SKIP_RTX_P
504 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
505
506 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
507 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
508 #undef TARGET_ARG_PARTIAL_BYTES
509 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
510 #undef TARGET_FUNCTION_ARG
511 #define TARGET_FUNCTION_ARG ia64_function_arg
512 #undef TARGET_FUNCTION_INCOMING_ARG
513 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
514 #undef TARGET_FUNCTION_ARG_ADVANCE
515 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
516 #undef TARGET_FUNCTION_ARG_BOUNDARY
517 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
518
519 #undef TARGET_ASM_OUTPUT_MI_THUNK
520 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
521 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
522 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
523
524 #undef TARGET_ASM_FILE_START
525 #define TARGET_ASM_FILE_START ia64_file_start
526
527 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
528 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
529
530 #undef TARGET_REGISTER_MOVE_COST
531 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
532 #undef TARGET_MEMORY_MOVE_COST
533 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
534 #undef TARGET_RTX_COSTS
535 #define TARGET_RTX_COSTS ia64_rtx_costs
536 #undef TARGET_ADDRESS_COST
537 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
538
539 #undef TARGET_UNSPEC_MAY_TRAP_P
540 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
541
542 #undef TARGET_MACHINE_DEPENDENT_REORG
543 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
544
545 #undef TARGET_ENCODE_SECTION_INFO
546 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
547
548 #undef TARGET_SECTION_TYPE_FLAGS
549 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
550
551 #ifdef HAVE_AS_TLS
552 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
553 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
554 #endif
555
556 /* ??? Investigate. */
557 #if 0
558 #undef TARGET_PROMOTE_PROTOTYPES
559 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
560 #endif
561
562 #undef TARGET_FUNCTION_VALUE
563 #define TARGET_FUNCTION_VALUE ia64_function_value
564 #undef TARGET_LIBCALL_VALUE
565 #define TARGET_LIBCALL_VALUE ia64_libcall_value
566 #undef TARGET_FUNCTION_VALUE_REGNO_P
567 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
568
569 #undef TARGET_STRUCT_VALUE_RTX
570 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
571 #undef TARGET_RETURN_IN_MEMORY
572 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
573 #undef TARGET_SETUP_INCOMING_VARARGS
574 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
575 #undef TARGET_STRICT_ARGUMENT_NAMING
576 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
577 #undef TARGET_MUST_PASS_IN_STACK
578 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
579 #undef TARGET_GET_RAW_RESULT_MODE
580 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
581 #undef TARGET_GET_RAW_ARG_MODE
582 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
583
584 #undef TARGET_MEMBER_TYPE_FORCES_BLK
585 #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk
586
587 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
588 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
589
590 #undef TARGET_ASM_UNWIND_EMIT
591 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
592 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
593 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
594 #undef TARGET_ASM_INIT_SECTIONS
595 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
596
597 #undef TARGET_DEBUG_UNWIND_INFO
598 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
599
600 #undef TARGET_SCALAR_MODE_SUPPORTED_P
601 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
602 #undef TARGET_VECTOR_MODE_SUPPORTED_P
603 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
604
605 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
606 in an order different from the specified program order. */
607 #undef TARGET_RELAXED_ORDERING
608 #define TARGET_RELAXED_ORDERING true
609
610 #undef TARGET_LEGITIMATE_CONSTANT_P
611 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
612 #undef TARGET_LEGITIMATE_ADDRESS_P
613 #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p
614
615 #undef TARGET_CANNOT_FORCE_CONST_MEM
616 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
617
618 #undef TARGET_MANGLE_TYPE
619 #define TARGET_MANGLE_TYPE ia64_mangle_type
620
621 #undef TARGET_INVALID_CONVERSION
622 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
623 #undef TARGET_INVALID_UNARY_OP
624 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
625 #undef TARGET_INVALID_BINARY_OP
626 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
627
628 #undef TARGET_C_MODE_FOR_SUFFIX
629 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
630
631 #undef TARGET_CAN_ELIMINATE
632 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
633
634 #undef TARGET_TRAMPOLINE_INIT
635 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
636
637 #undef TARGET_CAN_USE_DOLOOP_P
638 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
639 #undef TARGET_INVALID_WITHIN_DOLOOP
640 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
641
642 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
643 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
644
645 #undef TARGET_PREFERRED_RELOAD_CLASS
646 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
647
648 #undef TARGET_DELAY_SCHED2
649 #define TARGET_DELAY_SCHED2 true
650
651 /* Variable tracking should be run after all optimizations which
652 change order of insns. It also needs a valid CFG. */
653 #undef TARGET_DELAY_VARTRACK
654 #define TARGET_DELAY_VARTRACK true
655
656 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
657 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok
658
659 struct gcc_target targetm = TARGET_INITIALIZER;
660 \f
661 typedef enum
662 {
663 ADDR_AREA_NORMAL, /* normal address area */
664 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
665 }
666 ia64_addr_area;
667
668 static GTY(()) tree small_ident1;
669 static GTY(()) tree small_ident2;
670
671 static void
672 init_idents (void)
673 {
674 if (small_ident1 == 0)
675 {
676 small_ident1 = get_identifier ("small");
677 small_ident2 = get_identifier ("__small__");
678 }
679 }
680
681 /* Retrieve the address area that has been chosen for the given decl. */
682
683 static ia64_addr_area
684 ia64_get_addr_area (tree decl)
685 {
686 tree model_attr;
687
688 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
689 if (model_attr)
690 {
691 tree id;
692
693 init_idents ();
694 id = TREE_VALUE (TREE_VALUE (model_attr));
695 if (id == small_ident1 || id == small_ident2)
696 return ADDR_AREA_SMALL;
697 }
698 return ADDR_AREA_NORMAL;
699 }
700
701 static tree
702 ia64_handle_model_attribute (tree *node, tree name, tree args,
703 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
704 {
705 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
706 ia64_addr_area area;
707 tree arg, decl = *node;
708
709 init_idents ();
710 arg = TREE_VALUE (args);
711 if (arg == small_ident1 || arg == small_ident2)
712 {
713 addr_area = ADDR_AREA_SMALL;
714 }
715 else
716 {
717 warning (OPT_Wattributes, "invalid argument of %qE attribute",
718 name);
719 *no_add_attrs = true;
720 }
721
722 switch (TREE_CODE (decl))
723 {
724 case VAR_DECL:
725 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
726 == FUNCTION_DECL)
727 && !TREE_STATIC (decl))
728 {
729 error_at (DECL_SOURCE_LOCATION (decl),
730 "an address area attribute cannot be specified for "
731 "local variables");
732 *no_add_attrs = true;
733 }
734 area = ia64_get_addr_area (decl);
735 if (area != ADDR_AREA_NORMAL && addr_area != area)
736 {
737 error ("address area of %q+D conflicts with previous "
738 "declaration", decl);
739 *no_add_attrs = true;
740 }
741 break;
742
743 case FUNCTION_DECL:
744 error_at (DECL_SOURCE_LOCATION (decl),
745 "address area attribute cannot be specified for "
746 "functions");
747 *no_add_attrs = true;
748 break;
749
750 default:
751 warning (OPT_Wattributes, "%qE attribute ignored",
752 name);
753 *no_add_attrs = true;
754 break;
755 }
756
757 return NULL_TREE;
758 }
759
760 /* Part of the low level implementation of DEC Ada pragma Common_Object which
761 enables the shared use of variables stored in overlaid linker areas
762 corresponding to the use of Fortran COMMON. */
763
764 static tree
765 ia64_vms_common_object_attribute (tree *node, tree name, tree args,
766 int flags ATTRIBUTE_UNUSED,
767 bool *no_add_attrs)
768 {
769 tree decl = *node;
770 tree id;
771
772 gcc_assert (DECL_P (decl));
773
774 DECL_COMMON (decl) = 1;
775 id = TREE_VALUE (args);
776 if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST)
777 {
778 error ("%qE attribute requires a string constant argument", name);
779 *no_add_attrs = true;
780 return NULL_TREE;
781 }
782 return NULL_TREE;
783 }
784
785 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
786
787 void
788 ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
789 unsigned HOST_WIDE_INT size,
790 unsigned int align)
791 {
792 tree attr = DECL_ATTRIBUTES (decl);
793
794 if (attr)
795 attr = lookup_attribute ("common_object", attr);
796 if (attr)
797 {
798 tree id = TREE_VALUE (TREE_VALUE (attr));
799 const char *name;
800
801 if (TREE_CODE (id) == IDENTIFIER_NODE)
802 name = IDENTIFIER_POINTER (id);
803 else if (TREE_CODE (id) == STRING_CST)
804 name = TREE_STRING_POINTER (id);
805 else
806 abort ();
807
808 fprintf (file, "\t.vms_common\t\"%s\",", name);
809 }
810 else
811 fprintf (file, "%s", COMMON_ASM_OP);
812
813 /* Code from elfos.h. */
814 assemble_name (file, name);
815 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u",
816 size, align / BITS_PER_UNIT);
817
818 fputc ('\n', file);
819 }
820
821 static void
822 ia64_encode_addr_area (tree decl, rtx symbol)
823 {
824 int flags;
825
826 flags = SYMBOL_REF_FLAGS (symbol);
827 switch (ia64_get_addr_area (decl))
828 {
829 case ADDR_AREA_NORMAL: break;
830 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
831 default: gcc_unreachable ();
832 }
833 SYMBOL_REF_FLAGS (symbol) = flags;
834 }
835
836 static void
837 ia64_encode_section_info (tree decl, rtx rtl, int first)
838 {
839 default_encode_section_info (decl, rtl, first);
840
841 /* Careful not to prod global register variables. */
842 if (TREE_CODE (decl) == VAR_DECL
843 && GET_CODE (DECL_RTL (decl)) == MEM
844 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
845 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
846 ia64_encode_addr_area (decl, XEXP (rtl, 0));
847 }
848 \f
849 /* Return 1 if the operands of a move are ok. */
850
851 int
852 ia64_move_ok (rtx dst, rtx src)
853 {
854 /* If we're under init_recog_no_volatile, we'll not be able to use
855 memory_operand. So check the code directly and don't worry about
856 the validity of the underlying address, which should have been
857 checked elsewhere anyway. */
858 if (GET_CODE (dst) != MEM)
859 return 1;
860 if (GET_CODE (src) == MEM)
861 return 0;
862 if (register_operand (src, VOIDmode))
863 return 1;
864
865 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
866 if (INTEGRAL_MODE_P (GET_MODE (dst)))
867 return src == const0_rtx;
868 else
869 return satisfies_constraint_G (src);
870 }
871
872 /* Return 1 if the operands are ok for a floating point load pair. */
873
874 int
875 ia64_load_pair_ok (rtx dst, rtx src)
876 {
877 /* ??? There is a thinko in the implementation of the "x" constraint and the
878 FP_REGS class. The constraint will also reject (reg f30:TI) so we must
879 also return false for it. */
880 if (GET_CODE (dst) != REG
881 || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
882 return 0;
883 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
884 return 0;
885 switch (GET_CODE (XEXP (src, 0)))
886 {
887 case REG:
888 case POST_INC:
889 break;
890 case POST_DEC:
891 return 0;
892 case POST_MODIFY:
893 {
894 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
895
896 if (GET_CODE (adjust) != CONST_INT
897 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
898 return 0;
899 }
900 break;
901 default:
902 abort ();
903 }
904 return 1;
905 }
906
907 int
908 addp4_optimize_ok (rtx op1, rtx op2)
909 {
910 return (basereg_operand (op1, GET_MODE(op1)) !=
911 basereg_operand (op2, GET_MODE(op2)));
912 }
913
914 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
915 Return the length of the field, or <= 0 on failure. */
916
917 int
918 ia64_depz_field_mask (rtx rop, rtx rshift)
919 {
920 unsigned HOST_WIDE_INT op = INTVAL (rop);
921 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
922
923 /* Get rid of the zero bits we're shifting in. */
924 op >>= shift;
925
926 /* We must now have a solid block of 1's at bit 0. */
927 return exact_log2 (op + 1);
928 }
929
930 /* Return the TLS model to use for ADDR. */
931
932 static enum tls_model
933 tls_symbolic_operand_type (rtx addr)
934 {
935 enum tls_model tls_kind = TLS_MODEL_NONE;
936
937 if (GET_CODE (addr) == CONST)
938 {
939 if (GET_CODE (XEXP (addr, 0)) == PLUS
940 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
941 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
942 }
943 else if (GET_CODE (addr) == SYMBOL_REF)
944 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
945
946 return tls_kind;
947 }
948
949 /* Returns true if REG (assumed to be a `reg' RTX) is valid for use
950 as a base register. */
951
952 static inline bool
953 ia64_reg_ok_for_base_p (const_rtx reg, bool strict)
954 {
955 if (strict
956 && REGNO_OK_FOR_BASE_P (REGNO (reg)))
957 return true;
958 else if (!strict
959 && (GENERAL_REGNO_P (REGNO (reg))
960 || !HARD_REGISTER_P (reg)))
961 return true;
962 else
963 return false;
964 }
965
966 static bool
967 ia64_legitimate_address_reg (const_rtx reg, bool strict)
968 {
969 if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict))
970 || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0))
971 && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict)))
972 return true;
973
974 return false;
975 }
976
977 static bool
978 ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict)
979 {
980 if (GET_CODE (disp) == PLUS
981 && rtx_equal_p (reg, XEXP (disp, 0))
982 && (ia64_legitimate_address_reg (XEXP (disp, 1), strict)
983 || (CONST_INT_P (XEXP (disp, 1))
984 && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255))))
985 return true;
986
987 return false;
988 }
989
990 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
991
992 static bool
993 ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
994 rtx x, bool strict)
995 {
996 if (ia64_legitimate_address_reg (x, strict))
997 return true;
998 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC)
999 && ia64_legitimate_address_reg (XEXP (x, 0), strict)
1000 && XEXP (x, 0) != arg_pointer_rtx)
1001 return true;
1002 else if (GET_CODE (x) == POST_MODIFY
1003 && ia64_legitimate_address_reg (XEXP (x, 0), strict)
1004 && XEXP (x, 0) != arg_pointer_rtx
1005 && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict))
1006 return true;
1007 else
1008 return false;
1009 }
1010
1011 /* Return true if X is a constant that is valid for some immediate
1012 field in an instruction. */
1013
1014 static bool
1015 ia64_legitimate_constant_p (enum machine_mode mode, rtx x)
1016 {
1017 switch (GET_CODE (x))
1018 {
1019 case CONST_INT:
1020 case LABEL_REF:
1021 return true;
1022
1023 case CONST_DOUBLE:
1024 if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode)
1025 return true;
1026 return satisfies_constraint_G (x);
1027
1028 case CONST:
1029 case SYMBOL_REF:
1030 /* ??? Short term workaround for PR 28490. We must make the code here
1031 match the code in ia64_expand_move and move_operand, even though they
1032 are both technically wrong. */
1033 if (tls_symbolic_operand_type (x) == 0)
1034 {
1035 HOST_WIDE_INT addend = 0;
1036 rtx op = x;
1037
1038 if (GET_CODE (op) == CONST
1039 && GET_CODE (XEXP (op, 0)) == PLUS
1040 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1041 {
1042 addend = INTVAL (XEXP (XEXP (op, 0), 1));
1043 op = XEXP (XEXP (op, 0), 0);
1044 }
1045
1046 if (any_offset_symbol_operand (op, mode)
1047 || function_operand (op, mode))
1048 return true;
1049 if (aligned_offset_symbol_operand (op, mode))
1050 return (addend & 0x3fff) == 0;
1051 return false;
1052 }
1053 return false;
1054
1055 case CONST_VECTOR:
1056 if (mode == V2SFmode)
1057 return satisfies_constraint_Y (x);
1058
1059 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
1060 && GET_MODE_SIZE (mode) <= 8);
1061
1062 default:
1063 return false;
1064 }
1065 }
1066
1067 /* Don't allow TLS addresses to get spilled to memory. */
1068
1069 static bool
1070 ia64_cannot_force_const_mem (enum machine_mode mode, rtx x)
1071 {
1072 if (mode == RFmode)
1073 return true;
1074 return tls_symbolic_operand_type (x) != 0;
1075 }
1076
1077 /* Expand a symbolic constant load. */
1078
1079 bool
1080 ia64_expand_load_address (rtx dest, rtx src)
1081 {
1082 gcc_assert (GET_CODE (dest) == REG);
1083
1084 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1085 having to pointer-extend the value afterward. Other forms of address
1086 computation below are also more natural to compute as 64-bit quantities.
1087 If we've been given an SImode destination register, change it. */
1088 if (GET_MODE (dest) != Pmode)
1089 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
1090 byte_lowpart_offset (Pmode, GET_MODE (dest)));
1091
1092 if (TARGET_NO_PIC)
1093 return false;
1094 if (small_addr_symbolic_operand (src, VOIDmode))
1095 return false;
1096
1097 if (TARGET_AUTO_PIC)
1098 emit_insn (gen_load_gprel64 (dest, src));
1099 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1100 emit_insn (gen_load_fptr (dest, src));
1101 else if (sdata_symbolic_operand (src, VOIDmode))
1102 emit_insn (gen_load_gprel (dest, src));
1103 else
1104 {
1105 HOST_WIDE_INT addend = 0;
1106 rtx tmp;
1107
1108 /* We did split constant offsets in ia64_expand_move, and we did try
1109 to keep them split in move_operand, but we also allowed reload to
1110 rematerialize arbitrary constants rather than spill the value to
1111 the stack and reload it. So we have to be prepared here to split
1112 them apart again. */
1113 if (GET_CODE (src) == CONST)
1114 {
1115 HOST_WIDE_INT hi, lo;
1116
1117 hi = INTVAL (XEXP (XEXP (src, 0), 1));
1118 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
1119 hi = hi - lo;
1120
1121 if (lo != 0)
1122 {
1123 addend = lo;
1124 src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi);
1125 }
1126 }
1127
1128 tmp = gen_rtx_HIGH (Pmode, src);
1129 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1130 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1131
1132 tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src);
1133 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1134
1135 if (addend)
1136 {
1137 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
1138 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1139 }
1140 }
1141
1142 return true;
1143 }
1144
1145 static GTY(()) rtx gen_tls_tga;
1146 static rtx
1147 gen_tls_get_addr (void)
1148 {
1149 if (!gen_tls_tga)
1150 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1151 return gen_tls_tga;
1152 }
1153
1154 static GTY(()) rtx thread_pointer_rtx;
1155 static rtx
1156 gen_thread_pointer (void)
1157 {
1158 if (!thread_pointer_rtx)
1159 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1160 return thread_pointer_rtx;
1161 }
1162
1163 static rtx
1164 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
1165 rtx orig_op1, HOST_WIDE_INT addend)
1166 {
1167 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1168 rtx orig_op0 = op0;
1169 HOST_WIDE_INT addend_lo, addend_hi;
1170
1171 switch (tls_kind)
1172 {
1173 case TLS_MODEL_GLOBAL_DYNAMIC:
1174 start_sequence ();
1175
1176 tga_op1 = gen_reg_rtx (Pmode);
1177 emit_insn (gen_load_dtpmod (tga_op1, op1));
1178
1179 tga_op2 = gen_reg_rtx (Pmode);
1180 emit_insn (gen_load_dtprel (tga_op2, op1));
1181
1182 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1183 LCT_CONST, Pmode, 2, tga_op1,
1184 Pmode, tga_op2, Pmode);
1185
1186 insns = get_insns ();
1187 end_sequence ();
1188
1189 if (GET_MODE (op0) != Pmode)
1190 op0 = tga_ret;
1191 emit_libcall_block (insns, op0, tga_ret, op1);
1192 break;
1193
1194 case TLS_MODEL_LOCAL_DYNAMIC:
1195 /* ??? This isn't the completely proper way to do local-dynamic
1196 If the call to __tls_get_addr is used only by a single symbol,
1197 then we should (somehow) move the dtprel to the second arg
1198 to avoid the extra add. */
1199 start_sequence ();
1200
1201 tga_op1 = gen_reg_rtx (Pmode);
1202 emit_insn (gen_load_dtpmod (tga_op1, op1));
1203
1204 tga_op2 = const0_rtx;
1205
1206 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1207 LCT_CONST, Pmode, 2, tga_op1,
1208 Pmode, tga_op2, Pmode);
1209
1210 insns = get_insns ();
1211 end_sequence ();
1212
1213 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1214 UNSPEC_LD_BASE);
1215 tmp = gen_reg_rtx (Pmode);
1216 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1217
1218 if (!register_operand (op0, Pmode))
1219 op0 = gen_reg_rtx (Pmode);
1220 if (TARGET_TLS64)
1221 {
1222 emit_insn (gen_load_dtprel (op0, op1));
1223 emit_insn (gen_adddi3 (op0, tmp, op0));
1224 }
1225 else
1226 emit_insn (gen_add_dtprel (op0, op1, tmp));
1227 break;
1228
1229 case TLS_MODEL_INITIAL_EXEC:
1230 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1231 addend_hi = addend - addend_lo;
1232
1233 op1 = plus_constant (Pmode, op1, addend_hi);
1234 addend = addend_lo;
1235
1236 tmp = gen_reg_rtx (Pmode);
1237 emit_insn (gen_load_tprel (tmp, op1));
1238
1239 if (!register_operand (op0, Pmode))
1240 op0 = gen_reg_rtx (Pmode);
1241 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1242 break;
1243
1244 case TLS_MODEL_LOCAL_EXEC:
1245 if (!register_operand (op0, Pmode))
1246 op0 = gen_reg_rtx (Pmode);
1247
1248 op1 = orig_op1;
1249 addend = 0;
1250 if (TARGET_TLS64)
1251 {
1252 emit_insn (gen_load_tprel (op0, op1));
1253 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1254 }
1255 else
1256 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1257 break;
1258
1259 default:
1260 gcc_unreachable ();
1261 }
1262
1263 if (addend)
1264 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1265 orig_op0, 1, OPTAB_DIRECT);
1266 if (orig_op0 == op0)
1267 return NULL_RTX;
1268 if (GET_MODE (orig_op0) == Pmode)
1269 return op0;
1270 return gen_lowpart (GET_MODE (orig_op0), op0);
1271 }
1272
1273 rtx
1274 ia64_expand_move (rtx op0, rtx op1)
1275 {
1276 enum machine_mode mode = GET_MODE (op0);
1277
1278 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1279 op1 = force_reg (mode, op1);
1280
1281 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1282 {
1283 HOST_WIDE_INT addend = 0;
1284 enum tls_model tls_kind;
1285 rtx sym = op1;
1286
1287 if (GET_CODE (op1) == CONST
1288 && GET_CODE (XEXP (op1, 0)) == PLUS
1289 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1290 {
1291 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1292 sym = XEXP (XEXP (op1, 0), 0);
1293 }
1294
1295 tls_kind = tls_symbolic_operand_type (sym);
1296 if (tls_kind)
1297 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1298
1299 if (any_offset_symbol_operand (sym, mode))
1300 addend = 0;
1301 else if (aligned_offset_symbol_operand (sym, mode))
1302 {
1303 HOST_WIDE_INT addend_lo, addend_hi;
1304
1305 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1306 addend_hi = addend - addend_lo;
1307
1308 if (addend_lo != 0)
1309 {
1310 op1 = plus_constant (mode, sym, addend_hi);
1311 addend = addend_lo;
1312 }
1313 else
1314 addend = 0;
1315 }
1316 else
1317 op1 = sym;
1318
1319 if (reload_completed)
1320 {
1321 /* We really should have taken care of this offset earlier. */
1322 gcc_assert (addend == 0);
1323 if (ia64_expand_load_address (op0, op1))
1324 return NULL_RTX;
1325 }
1326
1327 if (addend)
1328 {
1329 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1330
1331 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1332
1333 op1 = expand_simple_binop (mode, PLUS, subtarget,
1334 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1335 if (op0 == op1)
1336 return NULL_RTX;
1337 }
1338 }
1339
1340 return op1;
1341 }
1342
1343 /* Split a move from OP1 to OP0 conditional on COND. */
1344
1345 void
1346 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1347 {
1348 rtx insn, first = get_last_insn ();
1349
1350 emit_move_insn (op0, op1);
1351
1352 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1353 if (INSN_P (insn))
1354 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1355 PATTERN (insn));
1356 }
1357
1358 /* Split a post-reload TImode or TFmode reference into two DImode
1359 components. This is made extra difficult by the fact that we do
1360 not get any scratch registers to work with, because reload cannot
1361 be prevented from giving us a scratch that overlaps the register
1362 pair involved. So instead, when addressing memory, we tweak the
1363 pointer register up and back down with POST_INCs. Or up and not
1364 back down when we can get away with it.
1365
1366 REVERSED is true when the loads must be done in reversed order
1367 (high word first) for correctness. DEAD is true when the pointer
1368 dies with the second insn we generate and therefore the second
1369 address must not carry a postmodify.
1370
1371 May return an insn which is to be emitted after the moves. */
1372
1373 static rtx
1374 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1375 {
1376 rtx fixup = 0;
1377
1378 switch (GET_CODE (in))
1379 {
1380 case REG:
1381 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1382 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1383 break;
1384
1385 case CONST_INT:
1386 case CONST_DOUBLE:
1387 /* Cannot occur reversed. */
1388 gcc_assert (!reversed);
1389
1390 if (GET_MODE (in) != TFmode)
1391 split_double (in, &out[0], &out[1]);
1392 else
1393 /* split_double does not understand how to split a TFmode
1394 quantity into a pair of DImode constants. */
1395 {
1396 REAL_VALUE_TYPE r;
1397 unsigned HOST_WIDE_INT p[2];
1398 long l[4]; /* TFmode is 128 bits */
1399
1400 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1401 real_to_target (l, &r, TFmode);
1402
1403 if (FLOAT_WORDS_BIG_ENDIAN)
1404 {
1405 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1406 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1407 }
1408 else
1409 {
1410 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1411 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1412 }
1413 out[0] = GEN_INT (p[0]);
1414 out[1] = GEN_INT (p[1]);
1415 }
1416 break;
1417
1418 case MEM:
1419 {
1420 rtx base = XEXP (in, 0);
1421 rtx offset;
1422
1423 switch (GET_CODE (base))
1424 {
1425 case REG:
1426 if (!reversed)
1427 {
1428 out[0] = adjust_automodify_address
1429 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1430 out[1] = adjust_automodify_address
1431 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1432 }
1433 else
1434 {
1435 /* Reversal requires a pre-increment, which can only
1436 be done as a separate insn. */
1437 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1438 out[0] = adjust_automodify_address
1439 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1440 out[1] = adjust_address (in, DImode, 0);
1441 }
1442 break;
1443
1444 case POST_INC:
1445 gcc_assert (!reversed && !dead);
1446
1447 /* Just do the increment in two steps. */
1448 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1449 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1450 break;
1451
1452 case POST_DEC:
1453 gcc_assert (!reversed && !dead);
1454
1455 /* Add 8, subtract 24. */
1456 base = XEXP (base, 0);
1457 out[0] = adjust_automodify_address
1458 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1459 out[1] = adjust_automodify_address
1460 (in, DImode,
1461 gen_rtx_POST_MODIFY (Pmode, base,
1462 plus_constant (Pmode, base, -24)),
1463 8);
1464 break;
1465
1466 case POST_MODIFY:
1467 gcc_assert (!reversed && !dead);
1468
1469 /* Extract and adjust the modification. This case is
1470 trickier than the others, because we might have an
1471 index register, or we might have a combined offset that
1472 doesn't fit a signed 9-bit displacement field. We can
1473 assume the incoming expression is already legitimate. */
1474 offset = XEXP (base, 1);
1475 base = XEXP (base, 0);
1476
1477 out[0] = adjust_automodify_address
1478 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1479
1480 if (GET_CODE (XEXP (offset, 1)) == REG)
1481 {
1482 /* Can't adjust the postmodify to match. Emit the
1483 original, then a separate addition insn. */
1484 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1485 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1486 }
1487 else
1488 {
1489 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1490 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1491 {
1492 /* Again the postmodify cannot be made to match,
1493 but in this case it's more efficient to get rid
1494 of the postmodify entirely and fix up with an
1495 add insn. */
1496 out[1] = adjust_automodify_address (in, DImode, base, 8);
1497 fixup = gen_adddi3
1498 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1499 }
1500 else
1501 {
1502 /* Combined offset still fits in the displacement field.
1503 (We cannot overflow it at the high end.) */
1504 out[1] = adjust_automodify_address
1505 (in, DImode, gen_rtx_POST_MODIFY
1506 (Pmode, base, gen_rtx_PLUS
1507 (Pmode, base,
1508 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1509 8);
1510 }
1511 }
1512 break;
1513
1514 default:
1515 gcc_unreachable ();
1516 }
1517 break;
1518 }
1519
1520 default:
1521 gcc_unreachable ();
1522 }
1523
1524 return fixup;
1525 }
1526
1527 /* Split a TImode or TFmode move instruction after reload.
1528 This is used by *movtf_internal and *movti_internal. */
1529 void
1530 ia64_split_tmode_move (rtx operands[])
1531 {
1532 rtx in[2], out[2], insn;
1533 rtx fixup[2];
1534 bool dead = false;
1535 bool reversed = false;
1536
1537 /* It is possible for reload to decide to overwrite a pointer with
1538 the value it points to. In that case we have to do the loads in
1539 the appropriate order so that the pointer is not destroyed too
1540 early. Also we must not generate a postmodify for that second
1541 load, or rws_access_regno will die. And we must not generate a
1542 postmodify for the second load if the destination register
1543 overlaps with the base register. */
1544 if (GET_CODE (operands[1]) == MEM
1545 && reg_overlap_mentioned_p (operands[0], operands[1]))
1546 {
1547 rtx base = XEXP (operands[1], 0);
1548 while (GET_CODE (base) != REG)
1549 base = XEXP (base, 0);
1550
1551 if (REGNO (base) == REGNO (operands[0]))
1552 reversed = true;
1553
1554 if (refers_to_regno_p (REGNO (operands[0]),
1555 REGNO (operands[0])+2,
1556 base, 0))
1557 dead = true;
1558 }
1559 /* Another reason to do the moves in reversed order is if the first
1560 element of the target register pair is also the second element of
1561 the source register pair. */
1562 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1563 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1564 reversed = true;
1565
1566 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1567 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1568
1569 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1570 if (GET_CODE (EXP) == MEM \
1571 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1572 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1573 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1574 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1575
1576 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1577 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1578 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1579
1580 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1581 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1582 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1583
1584 if (fixup[0])
1585 emit_insn (fixup[0]);
1586 if (fixup[1])
1587 emit_insn (fixup[1]);
1588
1589 #undef MAYBE_ADD_REG_INC_NOTE
1590 }
1591
1592 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1593 through memory plus an extra GR scratch register. Except that you can
1594 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1595 SECONDARY_RELOAD_CLASS, but not both.
1596
1597 We got into problems in the first place by allowing a construct like
1598 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1599 This solution attempts to prevent this situation from occurring. When
1600 we see something like the above, we spill the inner register to memory. */
1601
1602 static rtx
1603 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1604 {
1605 if (GET_CODE (in) == SUBREG
1606 && GET_MODE (SUBREG_REG (in)) == TImode
1607 && GET_CODE (SUBREG_REG (in)) == REG)
1608 {
1609 rtx memt = assign_stack_temp (TImode, 16);
1610 emit_move_insn (memt, SUBREG_REG (in));
1611 return adjust_address (memt, mode, 0);
1612 }
1613 else if (force && GET_CODE (in) == REG)
1614 {
1615 rtx memx = assign_stack_temp (mode, 16);
1616 emit_move_insn (memx, in);
1617 return memx;
1618 }
1619 else
1620 return in;
1621 }
1622
1623 /* Expand the movxf or movrf pattern (MODE says which) with the given
1624 OPERANDS, returning true if the pattern should then invoke
1625 DONE. */
1626
1627 bool
1628 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1629 {
1630 rtx op0 = operands[0];
1631
1632 if (GET_CODE (op0) == SUBREG)
1633 op0 = SUBREG_REG (op0);
1634
1635 /* We must support XFmode loads into general registers for stdarg/vararg,
1636 unprototyped calls, and a rare case where a long double is passed as
1637 an argument after a float HFA fills the FP registers. We split them into
1638 DImode loads for convenience. We also need to support XFmode stores
1639 for the last case. This case does not happen for stdarg/vararg routines,
1640 because we do a block store to memory of unnamed arguments. */
1641
1642 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1643 {
1644 rtx out[2];
1645
1646 /* We're hoping to transform everything that deals with XFmode
1647 quantities and GR registers early in the compiler. */
1648 gcc_assert (can_create_pseudo_p ());
1649
1650 /* Struct to register can just use TImode instead. */
1651 if ((GET_CODE (operands[1]) == SUBREG
1652 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1653 || (GET_CODE (operands[1]) == REG
1654 && GR_REGNO_P (REGNO (operands[1]))))
1655 {
1656 rtx op1 = operands[1];
1657
1658 if (GET_CODE (op1) == SUBREG)
1659 op1 = SUBREG_REG (op1);
1660 else
1661 op1 = gen_rtx_REG (TImode, REGNO (op1));
1662
1663 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1664 return true;
1665 }
1666
1667 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1668 {
1669 /* Don't word-swap when reading in the constant. */
1670 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1671 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1672 0, mode));
1673 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1674 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1675 0, mode));
1676 return true;
1677 }
1678
1679 /* If the quantity is in a register not known to be GR, spill it. */
1680 if (register_operand (operands[1], mode))
1681 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1682
1683 gcc_assert (GET_CODE (operands[1]) == MEM);
1684
1685 /* Don't word-swap when reading in the value. */
1686 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1687 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1688
1689 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1690 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1691 return true;
1692 }
1693
1694 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1695 {
1696 /* We're hoping to transform everything that deals with XFmode
1697 quantities and GR registers early in the compiler. */
1698 gcc_assert (can_create_pseudo_p ());
1699
1700 /* Op0 can't be a GR_REG here, as that case is handled above.
1701 If op0 is a register, then we spill op1, so that we now have a
1702 MEM operand. This requires creating an XFmode subreg of a TImode reg
1703 to force the spill. */
1704 if (register_operand (operands[0], mode))
1705 {
1706 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1707 op1 = gen_rtx_SUBREG (mode, op1, 0);
1708 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1709 }
1710
1711 else
1712 {
1713 rtx in[2];
1714
1715 gcc_assert (GET_CODE (operands[0]) == MEM);
1716
1717 /* Don't word-swap when writing out the value. */
1718 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1719 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1720
1721 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1722 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1723 return true;
1724 }
1725 }
1726
1727 if (!reload_in_progress && !reload_completed)
1728 {
1729 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1730
1731 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1732 {
1733 rtx memt, memx, in = operands[1];
1734 if (CONSTANT_P (in))
1735 in = validize_mem (force_const_mem (mode, in));
1736 if (GET_CODE (in) == MEM)
1737 memt = adjust_address (in, TImode, 0);
1738 else
1739 {
1740 memt = assign_stack_temp (TImode, 16);
1741 memx = adjust_address (memt, mode, 0);
1742 emit_move_insn (memx, in);
1743 }
1744 emit_move_insn (op0, memt);
1745 return true;
1746 }
1747
1748 if (!ia64_move_ok (operands[0], operands[1]))
1749 operands[1] = force_reg (mode, operands[1]);
1750 }
1751
1752 return false;
1753 }
1754
1755 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1756 with the expression that holds the compare result (in VOIDmode). */
1757
1758 static GTY(()) rtx cmptf_libfunc;
1759
1760 void
1761 ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
1762 {
1763 enum rtx_code code = GET_CODE (*expr);
1764 rtx cmp;
1765
1766 /* If we have a BImode input, then we already have a compare result, and
1767 do not need to emit another comparison. */
1768 if (GET_MODE (*op0) == BImode)
1769 {
1770 gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
1771 cmp = *op0;
1772 }
1773 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1774 magic number as its third argument, that indicates what to do.
1775 The return value is an integer to be compared against zero. */
1776 else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
1777 {
1778 enum qfcmp_magic {
1779 QCMP_INV = 1, /* Raise FP_INVALID on NaNs as a side effect. */
1780 QCMP_UNORD = 2,
1781 QCMP_EQ = 4,
1782 QCMP_LT = 8,
1783 QCMP_GT = 16
1784 };
1785 int magic;
1786 enum rtx_code ncode;
1787 rtx ret, insns;
1788
1789 gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
1790 switch (code)
1791 {
1792 /* 1 = equal, 0 = not equal. Equality operators do
1793 not raise FP_INVALID when given a NaN operand. */
1794 case EQ: magic = QCMP_EQ; ncode = NE; break;
1795 case NE: magic = QCMP_EQ; ncode = EQ; break;
1796 /* isunordered() from C99. */
1797 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1798 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1799 /* Relational operators raise FP_INVALID when given
1800 a NaN operand. */
1801 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1802 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1803 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1804 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1805 /* Unordered relational operators do not raise FP_INVALID
1806 when given a NaN operand. */
1807 case UNLT: magic = QCMP_LT |QCMP_UNORD; ncode = NE; break;
1808 case UNLE: magic = QCMP_LT|QCMP_EQ|QCMP_UNORD; ncode = NE; break;
1809 case UNGT: magic = QCMP_GT |QCMP_UNORD; ncode = NE; break;
1810 case UNGE: magic = QCMP_GT|QCMP_EQ|QCMP_UNORD; ncode = NE; break;
1811 /* Not supported. */
1812 case UNEQ:
1813 case LTGT:
1814 default: gcc_unreachable ();
1815 }
1816
1817 start_sequence ();
1818
1819 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1820 *op0, TFmode, *op1, TFmode,
1821 GEN_INT (magic), DImode);
1822 cmp = gen_reg_rtx (BImode);
1823 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1824 gen_rtx_fmt_ee (ncode, BImode,
1825 ret, const0_rtx)));
1826
1827 insns = get_insns ();
1828 end_sequence ();
1829
1830 emit_libcall_block (insns, cmp, cmp,
1831 gen_rtx_fmt_ee (code, BImode, *op0, *op1));
1832 code = NE;
1833 }
1834 else
1835 {
1836 cmp = gen_reg_rtx (BImode);
1837 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1838 gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
1839 code = NE;
1840 }
1841
1842 *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
1843 *op0 = cmp;
1844 *op1 = const0_rtx;
1845 }
1846
1847 /* Generate an integral vector comparison. Return true if the condition has
1848 been reversed, and so the sense of the comparison should be inverted. */
1849
1850 static bool
1851 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1852 rtx dest, rtx op0, rtx op1)
1853 {
1854 bool negate = false;
1855 rtx x;
1856
1857 /* Canonicalize the comparison to EQ, GT, GTU. */
1858 switch (code)
1859 {
1860 case EQ:
1861 case GT:
1862 case GTU:
1863 break;
1864
1865 case NE:
1866 case LE:
1867 case LEU:
1868 code = reverse_condition (code);
1869 negate = true;
1870 break;
1871
1872 case GE:
1873 case GEU:
1874 code = reverse_condition (code);
1875 negate = true;
1876 /* FALLTHRU */
1877
1878 case LT:
1879 case LTU:
1880 code = swap_condition (code);
1881 x = op0, op0 = op1, op1 = x;
1882 break;
1883
1884 default:
1885 gcc_unreachable ();
1886 }
1887
1888 /* Unsigned parallel compare is not supported by the hardware. Play some
1889 tricks to turn this into a signed comparison against 0. */
1890 if (code == GTU)
1891 {
1892 switch (mode)
1893 {
1894 case V2SImode:
1895 {
1896 rtx t1, t2, mask;
1897
1898 /* Subtract (-(INT MAX) - 1) from both operands to make
1899 them signed. */
1900 mask = GEN_INT (0x80000000);
1901 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1902 mask = force_reg (mode, mask);
1903 t1 = gen_reg_rtx (mode);
1904 emit_insn (gen_subv2si3 (t1, op0, mask));
1905 t2 = gen_reg_rtx (mode);
1906 emit_insn (gen_subv2si3 (t2, op1, mask));
1907 op0 = t1;
1908 op1 = t2;
1909 code = GT;
1910 }
1911 break;
1912
1913 case V8QImode:
1914 case V4HImode:
1915 /* Perform a parallel unsigned saturating subtraction. */
1916 x = gen_reg_rtx (mode);
1917 emit_insn (gen_rtx_SET (VOIDmode, x,
1918 gen_rtx_US_MINUS (mode, op0, op1)));
1919
1920 code = EQ;
1921 op0 = x;
1922 op1 = CONST0_RTX (mode);
1923 negate = !negate;
1924 break;
1925
1926 default:
1927 gcc_unreachable ();
1928 }
1929 }
1930
1931 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1932 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1933
1934 return negate;
1935 }
1936
1937 /* Emit an integral vector conditional move. */
1938
1939 void
1940 ia64_expand_vecint_cmov (rtx operands[])
1941 {
1942 enum machine_mode mode = GET_MODE (operands[0]);
1943 enum rtx_code code = GET_CODE (operands[3]);
1944 bool negate;
1945 rtx cmp, x, ot, of;
1946
1947 cmp = gen_reg_rtx (mode);
1948 negate = ia64_expand_vecint_compare (code, mode, cmp,
1949 operands[4], operands[5]);
1950
1951 ot = operands[1+negate];
1952 of = operands[2-negate];
1953
1954 if (ot == CONST0_RTX (mode))
1955 {
1956 if (of == CONST0_RTX (mode))
1957 {
1958 emit_move_insn (operands[0], ot);
1959 return;
1960 }
1961
1962 x = gen_rtx_NOT (mode, cmp);
1963 x = gen_rtx_AND (mode, x, of);
1964 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1965 }
1966 else if (of == CONST0_RTX (mode))
1967 {
1968 x = gen_rtx_AND (mode, cmp, ot);
1969 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1970 }
1971 else
1972 {
1973 rtx t, f;
1974
1975 t = gen_reg_rtx (mode);
1976 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1977 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1978
1979 f = gen_reg_rtx (mode);
1980 x = gen_rtx_NOT (mode, cmp);
1981 x = gen_rtx_AND (mode, x, operands[2-negate]);
1982 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1983
1984 x = gen_rtx_IOR (mode, t, f);
1985 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1986 }
1987 }
1988
1989 /* Emit an integral vector min or max operation. Return true if all done. */
1990
1991 bool
1992 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1993 rtx operands[])
1994 {
1995 rtx xops[6];
1996
1997 /* These four combinations are supported directly. */
1998 if (mode == V8QImode && (code == UMIN || code == UMAX))
1999 return false;
2000 if (mode == V4HImode && (code == SMIN || code == SMAX))
2001 return false;
2002
2003 /* This combination can be implemented with only saturating subtraction. */
2004 if (mode == V4HImode && code == UMAX)
2005 {
2006 rtx x, tmp = gen_reg_rtx (mode);
2007
2008 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
2009 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
2010
2011 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
2012 return true;
2013 }
2014
2015 /* Everything else implemented via vector comparisons. */
2016 xops[0] = operands[0];
2017 xops[4] = xops[1] = operands[1];
2018 xops[5] = xops[2] = operands[2];
2019
2020 switch (code)
2021 {
2022 case UMIN:
2023 code = LTU;
2024 break;
2025 case UMAX:
2026 code = GTU;
2027 break;
2028 case SMIN:
2029 code = LT;
2030 break;
2031 case SMAX:
2032 code = GT;
2033 break;
2034 default:
2035 gcc_unreachable ();
2036 }
2037 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
2038
2039 ia64_expand_vecint_cmov (xops);
2040 return true;
2041 }
2042
2043 /* The vectors LO and HI each contain N halves of a double-wide vector.
2044 Reassemble either the first N/2 or the second N/2 elements. */
2045
2046 void
2047 ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp)
2048 {
2049 enum machine_mode vmode = GET_MODE (lo);
2050 unsigned int i, high, nelt = GET_MODE_NUNITS (vmode);
2051 struct expand_vec_perm_d d;
2052 bool ok;
2053
2054 d.target = gen_lowpart (vmode, out);
2055 d.op0 = (TARGET_BIG_ENDIAN ? hi : lo);
2056 d.op1 = (TARGET_BIG_ENDIAN ? lo : hi);
2057 d.vmode = vmode;
2058 d.nelt = nelt;
2059 d.one_operand_p = false;
2060 d.testing_p = false;
2061
2062 high = (highp ? nelt / 2 : 0);
2063 for (i = 0; i < nelt / 2; ++i)
2064 {
2065 d.perm[i * 2] = i + high;
2066 d.perm[i * 2 + 1] = i + high + nelt;
2067 }
2068
2069 ok = ia64_expand_vec_perm_const_1 (&d);
2070 gcc_assert (ok);
2071 }
2072
2073 /* Return a vector of the sign-extension of VEC. */
2074
2075 static rtx
2076 ia64_unpack_sign (rtx vec, bool unsignedp)
2077 {
2078 enum machine_mode mode = GET_MODE (vec);
2079 rtx zero = CONST0_RTX (mode);
2080
2081 if (unsignedp)
2082 return zero;
2083 else
2084 {
2085 rtx sign = gen_reg_rtx (mode);
2086 bool neg;
2087
2088 neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero);
2089 gcc_assert (!neg);
2090
2091 return sign;
2092 }
2093 }
2094
2095 /* Emit an integral vector unpack operation. */
2096
2097 void
2098 ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp)
2099 {
2100 rtx sign = ia64_unpack_sign (operands[1], unsignedp);
2101 ia64_unpack_assemble (operands[0], operands[1], sign, highp);
2102 }
2103
2104 /* Emit an integral vector widening sum operations. */
2105
2106 void
2107 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
2108 {
2109 enum machine_mode wmode;
2110 rtx l, h, t, sign;
2111
2112 sign = ia64_unpack_sign (operands[1], unsignedp);
2113
2114 wmode = GET_MODE (operands[0]);
2115 l = gen_reg_rtx (wmode);
2116 h = gen_reg_rtx (wmode);
2117
2118 ia64_unpack_assemble (l, operands[1], sign, false);
2119 ia64_unpack_assemble (h, operands[1], sign, true);
2120
2121 t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT);
2122 t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT);
2123 if (t != operands[0])
2124 emit_move_insn (operands[0], t);
2125 }
2126
2127 /* Emit the appropriate sequence for a call. */
2128
2129 void
2130 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
2131 int sibcall_p)
2132 {
2133 rtx insn, b0;
2134
2135 addr = XEXP (addr, 0);
2136 addr = convert_memory_address (DImode, addr);
2137 b0 = gen_rtx_REG (DImode, R_BR (0));
2138
2139 /* ??? Should do this for functions known to bind local too. */
2140 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2141 {
2142 if (sibcall_p)
2143 insn = gen_sibcall_nogp (addr);
2144 else if (! retval)
2145 insn = gen_call_nogp (addr, b0);
2146 else
2147 insn = gen_call_value_nogp (retval, addr, b0);
2148 insn = emit_call_insn (insn);
2149 }
2150 else
2151 {
2152 if (sibcall_p)
2153 insn = gen_sibcall_gp (addr);
2154 else if (! retval)
2155 insn = gen_call_gp (addr, b0);
2156 else
2157 insn = gen_call_value_gp (retval, addr, b0);
2158 insn = emit_call_insn (insn);
2159
2160 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2161 }
2162
2163 if (sibcall_p)
2164 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
2165
2166 if (TARGET_ABI_OPEN_VMS)
2167 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2168 gen_rtx_REG (DImode, GR_REG (25)));
2169 }
2170
2171 static void
2172 reg_emitted (enum ia64_frame_regs r)
2173 {
2174 if (emitted_frame_related_regs[r] == 0)
2175 emitted_frame_related_regs[r] = current_frame_info.r[r];
2176 else
2177 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
2178 }
2179
2180 static int
2181 get_reg (enum ia64_frame_regs r)
2182 {
2183 reg_emitted (r);
2184 return current_frame_info.r[r];
2185 }
2186
2187 static bool
2188 is_emitted (int regno)
2189 {
2190 unsigned int r;
2191
2192 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
2193 if (emitted_frame_related_regs[r] == regno)
2194 return true;
2195 return false;
2196 }
2197
2198 void
2199 ia64_reload_gp (void)
2200 {
2201 rtx tmp;
2202
2203 if (current_frame_info.r[reg_save_gp])
2204 {
2205 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2206 }
2207 else
2208 {
2209 HOST_WIDE_INT offset;
2210 rtx offset_r;
2211
2212 offset = (current_frame_info.spill_cfa_off
2213 + current_frame_info.spill_size);
2214 if (frame_pointer_needed)
2215 {
2216 tmp = hard_frame_pointer_rtx;
2217 offset = -offset;
2218 }
2219 else
2220 {
2221 tmp = stack_pointer_rtx;
2222 offset = current_frame_info.total_size - offset;
2223 }
2224
2225 offset_r = GEN_INT (offset);
2226 if (satisfies_constraint_I (offset_r))
2227 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
2228 else
2229 {
2230 emit_move_insn (pic_offset_table_rtx, offset_r);
2231 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2232 pic_offset_table_rtx, tmp));
2233 }
2234
2235 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2236 }
2237
2238 emit_move_insn (pic_offset_table_rtx, tmp);
2239 }
2240
2241 void
2242 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2243 rtx scratch_b, int noreturn_p, int sibcall_p)
2244 {
2245 rtx insn;
2246 bool is_desc = false;
2247
2248 /* If we find we're calling through a register, then we're actually
2249 calling through a descriptor, so load up the values. */
2250 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2251 {
2252 rtx tmp;
2253 bool addr_dead_p;
2254
2255 /* ??? We are currently constrained to *not* use peep2, because
2256 we can legitimately change the global lifetime of the GP
2257 (in the form of killing where previously live). This is
2258 because a call through a descriptor doesn't use the previous
2259 value of the GP, while a direct call does, and we do not
2260 commit to either form until the split here.
2261
2262 That said, this means that we lack precise life info for
2263 whether ADDR is dead after this call. This is not terribly
2264 important, since we can fix things up essentially for free
2265 with the POST_DEC below, but it's nice to not use it when we
2266 can immediately tell it's not necessary. */
2267 addr_dead_p = ((noreturn_p || sibcall_p
2268 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2269 REGNO (addr)))
2270 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2271
2272 /* Load the code address into scratch_b. */
2273 tmp = gen_rtx_POST_INC (Pmode, addr);
2274 tmp = gen_rtx_MEM (Pmode, tmp);
2275 emit_move_insn (scratch_r, tmp);
2276 emit_move_insn (scratch_b, scratch_r);
2277
2278 /* Load the GP address. If ADDR is not dead here, then we must
2279 revert the change made above via the POST_INCREMENT. */
2280 if (!addr_dead_p)
2281 tmp = gen_rtx_POST_DEC (Pmode, addr);
2282 else
2283 tmp = addr;
2284 tmp = gen_rtx_MEM (Pmode, tmp);
2285 emit_move_insn (pic_offset_table_rtx, tmp);
2286
2287 is_desc = true;
2288 addr = scratch_b;
2289 }
2290
2291 if (sibcall_p)
2292 insn = gen_sibcall_nogp (addr);
2293 else if (retval)
2294 insn = gen_call_value_nogp (retval, addr, retaddr);
2295 else
2296 insn = gen_call_nogp (addr, retaddr);
2297 emit_call_insn (insn);
2298
2299 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2300 ia64_reload_gp ();
2301 }
2302
2303 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2304
2305 This differs from the generic code in that we know about the zero-extending
2306 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2307 also know that ld.acq+cmpxchg.rel equals a full barrier.
2308
2309 The loop we want to generate looks like
2310
2311 cmp_reg = mem;
2312 label:
2313 old_reg = cmp_reg;
2314 new_reg = cmp_reg op val;
2315 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2316 if (cmp_reg != old_reg)
2317 goto label;
2318
2319 Note that we only do the plain load from memory once. Subsequent
2320 iterations use the value loaded by the compare-and-swap pattern. */
2321
2322 void
2323 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2324 rtx old_dst, rtx new_dst, enum memmodel model)
2325 {
2326 enum machine_mode mode = GET_MODE (mem);
2327 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2328 enum insn_code icode;
2329
2330 /* Special case for using fetchadd. */
2331 if ((mode == SImode || mode == DImode)
2332 && (code == PLUS || code == MINUS)
2333 && fetchadd_operand (val, mode))
2334 {
2335 if (code == MINUS)
2336 val = GEN_INT (-INTVAL (val));
2337
2338 if (!old_dst)
2339 old_dst = gen_reg_rtx (mode);
2340
2341 switch (model)
2342 {
2343 case MEMMODEL_ACQ_REL:
2344 case MEMMODEL_SEQ_CST:
2345 emit_insn (gen_memory_barrier ());
2346 /* FALLTHRU */
2347 case MEMMODEL_RELAXED:
2348 case MEMMODEL_ACQUIRE:
2349 case MEMMODEL_CONSUME:
2350 if (mode == SImode)
2351 icode = CODE_FOR_fetchadd_acq_si;
2352 else
2353 icode = CODE_FOR_fetchadd_acq_di;
2354 break;
2355 case MEMMODEL_RELEASE:
2356 if (mode == SImode)
2357 icode = CODE_FOR_fetchadd_rel_si;
2358 else
2359 icode = CODE_FOR_fetchadd_rel_di;
2360 break;
2361
2362 default:
2363 gcc_unreachable ();
2364 }
2365
2366 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2367
2368 if (new_dst)
2369 {
2370 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2371 true, OPTAB_WIDEN);
2372 if (new_reg != new_dst)
2373 emit_move_insn (new_dst, new_reg);
2374 }
2375 return;
2376 }
2377
2378 /* Because of the volatile mem read, we get an ld.acq, which is the
2379 front half of the full barrier. The end half is the cmpxchg.rel.
2380 For relaxed and release memory models, we don't need this. But we
2381 also don't bother trying to prevent it either. */
2382 gcc_assert (model == MEMMODEL_RELAXED
2383 || model == MEMMODEL_RELEASE
2384 || MEM_VOLATILE_P (mem));
2385
2386 old_reg = gen_reg_rtx (DImode);
2387 cmp_reg = gen_reg_rtx (DImode);
2388 label = gen_label_rtx ();
2389
2390 if (mode != DImode)
2391 {
2392 val = simplify_gen_subreg (DImode, val, mode, 0);
2393 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2394 }
2395 else
2396 emit_move_insn (cmp_reg, mem);
2397
2398 emit_label (label);
2399
2400 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2401 emit_move_insn (old_reg, cmp_reg);
2402 emit_move_insn (ar_ccv, cmp_reg);
2403
2404 if (old_dst)
2405 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2406
2407 new_reg = cmp_reg;
2408 if (code == NOT)
2409 {
2410 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2411 true, OPTAB_DIRECT);
2412 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2413 }
2414 else
2415 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2416 true, OPTAB_DIRECT);
2417
2418 if (mode != DImode)
2419 new_reg = gen_lowpart (mode, new_reg);
2420 if (new_dst)
2421 emit_move_insn (new_dst, new_reg);
2422
2423 switch (model)
2424 {
2425 case MEMMODEL_RELAXED:
2426 case MEMMODEL_ACQUIRE:
2427 case MEMMODEL_CONSUME:
2428 switch (mode)
2429 {
2430 case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break;
2431 case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break;
2432 case SImode: icode = CODE_FOR_cmpxchg_acq_si; break;
2433 case DImode: icode = CODE_FOR_cmpxchg_acq_di; break;
2434 default:
2435 gcc_unreachable ();
2436 }
2437 break;
2438
2439 case MEMMODEL_RELEASE:
2440 case MEMMODEL_ACQ_REL:
2441 case MEMMODEL_SEQ_CST:
2442 switch (mode)
2443 {
2444 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2445 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2446 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2447 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2448 default:
2449 gcc_unreachable ();
2450 }
2451 break;
2452
2453 default:
2454 gcc_unreachable ();
2455 }
2456
2457 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2458
2459 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2460 }
2461 \f
2462 /* Begin the assembly file. */
2463
2464 static void
2465 ia64_file_start (void)
2466 {
2467 default_file_start ();
2468 emit_safe_across_calls ();
2469 }
2470
2471 void
2472 emit_safe_across_calls (void)
2473 {
2474 unsigned int rs, re;
2475 int out_state;
2476
2477 rs = 1;
2478 out_state = 0;
2479 while (1)
2480 {
2481 while (rs < 64 && call_used_regs[PR_REG (rs)])
2482 rs++;
2483 if (rs >= 64)
2484 break;
2485 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2486 continue;
2487 if (out_state == 0)
2488 {
2489 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2490 out_state = 1;
2491 }
2492 else
2493 fputc (',', asm_out_file);
2494 if (re == rs + 1)
2495 fprintf (asm_out_file, "p%u", rs);
2496 else
2497 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2498 rs = re + 1;
2499 }
2500 if (out_state)
2501 fputc ('\n', asm_out_file);
2502 }
2503
2504 /* Globalize a declaration. */
2505
2506 static void
2507 ia64_globalize_decl_name (FILE * stream, tree decl)
2508 {
2509 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2510 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2511 if (version_attr)
2512 {
2513 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2514 const char *p = TREE_STRING_POINTER (v);
2515 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2516 }
2517 targetm.asm_out.globalize_label (stream, name);
2518 if (TREE_CODE (decl) == FUNCTION_DECL)
2519 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2520 }
2521
2522 /* Helper function for ia64_compute_frame_size: find an appropriate general
2523 register to spill some special register to. SPECIAL_SPILL_MASK contains
2524 bits in GR0 to GR31 that have already been allocated by this routine.
2525 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2526
2527 static int
2528 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2529 {
2530 int regno;
2531
2532 if (emitted_frame_related_regs[r] != 0)
2533 {
2534 regno = emitted_frame_related_regs[r];
2535 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2536 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2537 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2538 else if (crtl->is_leaf
2539 && regno >= GR_REG (1) && regno <= GR_REG (31))
2540 current_frame_info.gr_used_mask |= 1 << regno;
2541
2542 return regno;
2543 }
2544
2545 /* If this is a leaf function, first try an otherwise unused
2546 call-clobbered register. */
2547 if (crtl->is_leaf)
2548 {
2549 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2550 if (! df_regs_ever_live_p (regno)
2551 && call_used_regs[regno]
2552 && ! fixed_regs[regno]
2553 && ! global_regs[regno]
2554 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2555 && ! is_emitted (regno))
2556 {
2557 current_frame_info.gr_used_mask |= 1 << regno;
2558 return regno;
2559 }
2560 }
2561
2562 if (try_locals)
2563 {
2564 regno = current_frame_info.n_local_regs;
2565 /* If there is a frame pointer, then we can't use loc79, because
2566 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2567 reg_name switching code in ia64_expand_prologue. */
2568 while (regno < (80 - frame_pointer_needed))
2569 if (! is_emitted (LOC_REG (regno++)))
2570 {
2571 current_frame_info.n_local_regs = regno;
2572 return LOC_REG (regno - 1);
2573 }
2574 }
2575
2576 /* Failed to find a general register to spill to. Must use stack. */
2577 return 0;
2578 }
2579
2580 /* In order to make for nice schedules, we try to allocate every temporary
2581 to a different register. We must of course stay away from call-saved,
2582 fixed, and global registers. We must also stay away from registers
2583 allocated in current_frame_info.gr_used_mask, since those include regs
2584 used all through the prologue.
2585
2586 Any register allocated here must be used immediately. The idea is to
2587 aid scheduling, not to solve data flow problems. */
2588
2589 static int last_scratch_gr_reg;
2590
2591 static int
2592 next_scratch_gr_reg (void)
2593 {
2594 int i, regno;
2595
2596 for (i = 0; i < 32; ++i)
2597 {
2598 regno = (last_scratch_gr_reg + i + 1) & 31;
2599 if (call_used_regs[regno]
2600 && ! fixed_regs[regno]
2601 && ! global_regs[regno]
2602 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2603 {
2604 last_scratch_gr_reg = regno;
2605 return regno;
2606 }
2607 }
2608
2609 /* There must be _something_ available. */
2610 gcc_unreachable ();
2611 }
2612
2613 /* Helper function for ia64_compute_frame_size, called through
2614 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2615
2616 static void
2617 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2618 {
2619 unsigned int regno = REGNO (reg);
2620 if (regno < 32)
2621 {
2622 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2623 for (i = 0; i < n; ++i)
2624 current_frame_info.gr_used_mask |= 1 << (regno + i);
2625 }
2626 }
2627
2628
2629 /* Returns the number of bytes offset between the frame pointer and the stack
2630 pointer for the current function. SIZE is the number of bytes of space
2631 needed for local variables. */
2632
2633 static void
2634 ia64_compute_frame_size (HOST_WIDE_INT size)
2635 {
2636 HOST_WIDE_INT total_size;
2637 HOST_WIDE_INT spill_size = 0;
2638 HOST_WIDE_INT extra_spill_size = 0;
2639 HOST_WIDE_INT pretend_args_size;
2640 HARD_REG_SET mask;
2641 int n_spilled = 0;
2642 int spilled_gr_p = 0;
2643 int spilled_fr_p = 0;
2644 unsigned int regno;
2645 int min_regno;
2646 int max_regno;
2647 int i;
2648
2649 if (current_frame_info.initialized)
2650 return;
2651
2652 memset (&current_frame_info, 0, sizeof current_frame_info);
2653 CLEAR_HARD_REG_SET (mask);
2654
2655 /* Don't allocate scratches to the return register. */
2656 diddle_return_value (mark_reg_gr_used_mask, NULL);
2657
2658 /* Don't allocate scratches to the EH scratch registers. */
2659 if (cfun->machine->ia64_eh_epilogue_sp)
2660 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2661 if (cfun->machine->ia64_eh_epilogue_bsp)
2662 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2663
2664 /* Static stack checking uses r2 and r3. */
2665 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
2666 current_frame_info.gr_used_mask |= 0xc;
2667
2668 /* Find the size of the register stack frame. We have only 80 local
2669 registers, because we reserve 8 for the inputs and 8 for the
2670 outputs. */
2671
2672 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2673 since we'll be adjusting that down later. */
2674 regno = LOC_REG (78) + ! frame_pointer_needed;
2675 for (; regno >= LOC_REG (0); regno--)
2676 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2677 break;
2678 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2679
2680 /* For functions marked with the syscall_linkage attribute, we must mark
2681 all eight input registers as in use, so that locals aren't visible to
2682 the caller. */
2683
2684 if (cfun->machine->n_varargs > 0
2685 || lookup_attribute ("syscall_linkage",
2686 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2687 current_frame_info.n_input_regs = 8;
2688 else
2689 {
2690 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2691 if (df_regs_ever_live_p (regno))
2692 break;
2693 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2694 }
2695
2696 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2697 if (df_regs_ever_live_p (regno))
2698 break;
2699 i = regno - OUT_REG (0) + 1;
2700
2701 #ifndef PROFILE_HOOK
2702 /* When -p profiling, we need one output register for the mcount argument.
2703 Likewise for -a profiling for the bb_init_func argument. For -ax
2704 profiling, we need two output registers for the two bb_init_trace_func
2705 arguments. */
2706 if (crtl->profile)
2707 i = MAX (i, 1);
2708 #endif
2709 current_frame_info.n_output_regs = i;
2710
2711 /* ??? No rotating register support yet. */
2712 current_frame_info.n_rotate_regs = 0;
2713
2714 /* Discover which registers need spilling, and how much room that
2715 will take. Begin with floating point and general registers,
2716 which will always wind up on the stack. */
2717
2718 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2719 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2720 {
2721 SET_HARD_REG_BIT (mask, regno);
2722 spill_size += 16;
2723 n_spilled += 1;
2724 spilled_fr_p = 1;
2725 }
2726
2727 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2728 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2729 {
2730 SET_HARD_REG_BIT (mask, regno);
2731 spill_size += 8;
2732 n_spilled += 1;
2733 spilled_gr_p = 1;
2734 }
2735
2736 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2737 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2738 {
2739 SET_HARD_REG_BIT (mask, regno);
2740 spill_size += 8;
2741 n_spilled += 1;
2742 }
2743
2744 /* Now come all special registers that might get saved in other
2745 general registers. */
2746
2747 if (frame_pointer_needed)
2748 {
2749 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2750 /* If we did not get a register, then we take LOC79. This is guaranteed
2751 to be free, even if regs_ever_live is already set, because this is
2752 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2753 as we don't count loc79 above. */
2754 if (current_frame_info.r[reg_fp] == 0)
2755 {
2756 current_frame_info.r[reg_fp] = LOC_REG (79);
2757 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2758 }
2759 }
2760
2761 if (! crtl->is_leaf)
2762 {
2763 /* Emit a save of BR0 if we call other functions. Do this even
2764 if this function doesn't return, as EH depends on this to be
2765 able to unwind the stack. */
2766 SET_HARD_REG_BIT (mask, BR_REG (0));
2767
2768 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2769 if (current_frame_info.r[reg_save_b0] == 0)
2770 {
2771 extra_spill_size += 8;
2772 n_spilled += 1;
2773 }
2774
2775 /* Similarly for ar.pfs. */
2776 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2777 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2778 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2779 {
2780 extra_spill_size += 8;
2781 n_spilled += 1;
2782 }
2783
2784 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2785 registers are clobbered, so we fall back to the stack. */
2786 current_frame_info.r[reg_save_gp]
2787 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2788 if (current_frame_info.r[reg_save_gp] == 0)
2789 {
2790 SET_HARD_REG_BIT (mask, GR_REG (1));
2791 spill_size += 8;
2792 n_spilled += 1;
2793 }
2794 }
2795 else
2796 {
2797 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2798 {
2799 SET_HARD_REG_BIT (mask, BR_REG (0));
2800 extra_spill_size += 8;
2801 n_spilled += 1;
2802 }
2803
2804 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2805 {
2806 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2807 current_frame_info.r[reg_save_ar_pfs]
2808 = find_gr_spill (reg_save_ar_pfs, 1);
2809 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2810 {
2811 extra_spill_size += 8;
2812 n_spilled += 1;
2813 }
2814 }
2815 }
2816
2817 /* Unwind descriptor hackery: things are most efficient if we allocate
2818 consecutive GR save registers for RP, PFS, FP in that order. However,
2819 it is absolutely critical that FP get the only hard register that's
2820 guaranteed to be free, so we allocated it first. If all three did
2821 happen to be allocated hard regs, and are consecutive, rearrange them
2822 into the preferred order now.
2823
2824 If we have already emitted code for any of those registers,
2825 then it's already too late to change. */
2826 min_regno = MIN (current_frame_info.r[reg_fp],
2827 MIN (current_frame_info.r[reg_save_b0],
2828 current_frame_info.r[reg_save_ar_pfs]));
2829 max_regno = MAX (current_frame_info.r[reg_fp],
2830 MAX (current_frame_info.r[reg_save_b0],
2831 current_frame_info.r[reg_save_ar_pfs]));
2832 if (min_regno > 0
2833 && min_regno + 2 == max_regno
2834 && (current_frame_info.r[reg_fp] == min_regno + 1
2835 || current_frame_info.r[reg_save_b0] == min_regno + 1
2836 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2837 && (emitted_frame_related_regs[reg_save_b0] == 0
2838 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2839 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2840 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2841 && (emitted_frame_related_regs[reg_fp] == 0
2842 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2843 {
2844 current_frame_info.r[reg_save_b0] = min_regno;
2845 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2846 current_frame_info.r[reg_fp] = min_regno + 2;
2847 }
2848
2849 /* See if we need to store the predicate register block. */
2850 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2851 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2852 break;
2853 if (regno <= PR_REG (63))
2854 {
2855 SET_HARD_REG_BIT (mask, PR_REG (0));
2856 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2857 if (current_frame_info.r[reg_save_pr] == 0)
2858 {
2859 extra_spill_size += 8;
2860 n_spilled += 1;
2861 }
2862
2863 /* ??? Mark them all as used so that register renaming and such
2864 are free to use them. */
2865 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2866 df_set_regs_ever_live (regno, true);
2867 }
2868
2869 /* If we're forced to use st8.spill, we're forced to save and restore
2870 ar.unat as well. The check for existing liveness allows inline asm
2871 to touch ar.unat. */
2872 if (spilled_gr_p || cfun->machine->n_varargs
2873 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2874 {
2875 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2876 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2877 current_frame_info.r[reg_save_ar_unat]
2878 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2879 if (current_frame_info.r[reg_save_ar_unat] == 0)
2880 {
2881 extra_spill_size += 8;
2882 n_spilled += 1;
2883 }
2884 }
2885
2886 if (df_regs_ever_live_p (AR_LC_REGNUM))
2887 {
2888 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2889 current_frame_info.r[reg_save_ar_lc]
2890 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2891 if (current_frame_info.r[reg_save_ar_lc] == 0)
2892 {
2893 extra_spill_size += 8;
2894 n_spilled += 1;
2895 }
2896 }
2897
2898 /* If we have an odd number of words of pretend arguments written to
2899 the stack, then the FR save area will be unaligned. We round the
2900 size of this area up to keep things 16 byte aligned. */
2901 if (spilled_fr_p)
2902 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2903 else
2904 pretend_args_size = crtl->args.pretend_args_size;
2905
2906 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2907 + crtl->outgoing_args_size);
2908 total_size = IA64_STACK_ALIGN (total_size);
2909
2910 /* We always use the 16-byte scratch area provided by the caller, but
2911 if we are a leaf function, there's no one to which we need to provide
2912 a scratch area. However, if the function allocates dynamic stack space,
2913 the dynamic offset is computed early and contains STACK_POINTER_OFFSET,
2914 so we need to cope. */
2915 if (crtl->is_leaf && !cfun->calls_alloca)
2916 total_size = MAX (0, total_size - 16);
2917
2918 current_frame_info.total_size = total_size;
2919 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2920 current_frame_info.spill_size = spill_size;
2921 current_frame_info.extra_spill_size = extra_spill_size;
2922 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2923 current_frame_info.n_spilled = n_spilled;
2924 current_frame_info.initialized = reload_completed;
2925 }
2926
2927 /* Worker function for TARGET_CAN_ELIMINATE. */
2928
2929 bool
2930 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2931 {
2932 return (to == BR_REG (0) ? crtl->is_leaf : true);
2933 }
2934
2935 /* Compute the initial difference between the specified pair of registers. */
2936
2937 HOST_WIDE_INT
2938 ia64_initial_elimination_offset (int from, int to)
2939 {
2940 HOST_WIDE_INT offset;
2941
2942 ia64_compute_frame_size (get_frame_size ());
2943 switch (from)
2944 {
2945 case FRAME_POINTER_REGNUM:
2946 switch (to)
2947 {
2948 case HARD_FRAME_POINTER_REGNUM:
2949 offset = -current_frame_info.total_size;
2950 if (!crtl->is_leaf || cfun->calls_alloca)
2951 offset += 16 + crtl->outgoing_args_size;
2952 break;
2953
2954 case STACK_POINTER_REGNUM:
2955 offset = 0;
2956 if (!crtl->is_leaf || cfun->calls_alloca)
2957 offset += 16 + crtl->outgoing_args_size;
2958 break;
2959
2960 default:
2961 gcc_unreachable ();
2962 }
2963 break;
2964
2965 case ARG_POINTER_REGNUM:
2966 /* Arguments start above the 16 byte save area, unless stdarg
2967 in which case we store through the 16 byte save area. */
2968 switch (to)
2969 {
2970 case HARD_FRAME_POINTER_REGNUM:
2971 offset = 16 - crtl->args.pretend_args_size;
2972 break;
2973
2974 case STACK_POINTER_REGNUM:
2975 offset = (current_frame_info.total_size
2976 + 16 - crtl->args.pretend_args_size);
2977 break;
2978
2979 default:
2980 gcc_unreachable ();
2981 }
2982 break;
2983
2984 default:
2985 gcc_unreachable ();
2986 }
2987
2988 return offset;
2989 }
2990
2991 /* If there are more than a trivial number of register spills, we use
2992 two interleaved iterators so that we can get two memory references
2993 per insn group.
2994
2995 In order to simplify things in the prologue and epilogue expanders,
2996 we use helper functions to fix up the memory references after the
2997 fact with the appropriate offsets to a POST_MODIFY memory mode.
2998 The following data structure tracks the state of the two iterators
2999 while insns are being emitted. */
3000
3001 struct spill_fill_data
3002 {
3003 rtx init_after; /* point at which to emit initializations */
3004 rtx init_reg[2]; /* initial base register */
3005 rtx iter_reg[2]; /* the iterator registers */
3006 rtx *prev_addr[2]; /* address of last memory use */
3007 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
3008 HOST_WIDE_INT prev_off[2]; /* last offset */
3009 int n_iter; /* number of iterators in use */
3010 int next_iter; /* next iterator to use */
3011 unsigned int save_gr_used_mask;
3012 };
3013
3014 static struct spill_fill_data spill_fill_data;
3015
3016 static void
3017 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
3018 {
3019 int i;
3020
3021 spill_fill_data.init_after = get_last_insn ();
3022 spill_fill_data.init_reg[0] = init_reg;
3023 spill_fill_data.init_reg[1] = init_reg;
3024 spill_fill_data.prev_addr[0] = NULL;
3025 spill_fill_data.prev_addr[1] = NULL;
3026 spill_fill_data.prev_insn[0] = NULL;
3027 spill_fill_data.prev_insn[1] = NULL;
3028 spill_fill_data.prev_off[0] = cfa_off;
3029 spill_fill_data.prev_off[1] = cfa_off;
3030 spill_fill_data.next_iter = 0;
3031 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
3032
3033 spill_fill_data.n_iter = 1 + (n_spills > 2);
3034 for (i = 0; i < spill_fill_data.n_iter; ++i)
3035 {
3036 int regno = next_scratch_gr_reg ();
3037 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
3038 current_frame_info.gr_used_mask |= 1 << regno;
3039 }
3040 }
3041
3042 static void
3043 finish_spill_pointers (void)
3044 {
3045 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
3046 }
3047
3048 static rtx
3049 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
3050 {
3051 int iter = spill_fill_data.next_iter;
3052 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
3053 rtx disp_rtx = GEN_INT (disp);
3054 rtx mem;
3055
3056 if (spill_fill_data.prev_addr[iter])
3057 {
3058 if (satisfies_constraint_N (disp_rtx))
3059 {
3060 *spill_fill_data.prev_addr[iter]
3061 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
3062 gen_rtx_PLUS (DImode,
3063 spill_fill_data.iter_reg[iter],
3064 disp_rtx));
3065 add_reg_note (spill_fill_data.prev_insn[iter],
3066 REG_INC, spill_fill_data.iter_reg[iter]);
3067 }
3068 else
3069 {
3070 /* ??? Could use register post_modify for loads. */
3071 if (!satisfies_constraint_I (disp_rtx))
3072 {
3073 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3074 emit_move_insn (tmp, disp_rtx);
3075 disp_rtx = tmp;
3076 }
3077 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3078 spill_fill_data.iter_reg[iter], disp_rtx));
3079 }
3080 }
3081 /* Micro-optimization: if we've created a frame pointer, it's at
3082 CFA 0, which may allow the real iterator to be initialized lower,
3083 slightly increasing parallelism. Also, if there are few saves
3084 it may eliminate the iterator entirely. */
3085 else if (disp == 0
3086 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
3087 && frame_pointer_needed)
3088 {
3089 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
3090 set_mem_alias_set (mem, get_varargs_alias_set ());
3091 return mem;
3092 }
3093 else
3094 {
3095 rtx seq, insn;
3096
3097 if (disp == 0)
3098 seq = gen_movdi (spill_fill_data.iter_reg[iter],
3099 spill_fill_data.init_reg[iter]);
3100 else
3101 {
3102 start_sequence ();
3103
3104 if (!satisfies_constraint_I (disp_rtx))
3105 {
3106 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3107 emit_move_insn (tmp, disp_rtx);
3108 disp_rtx = tmp;
3109 }
3110
3111 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3112 spill_fill_data.init_reg[iter],
3113 disp_rtx));
3114
3115 seq = get_insns ();
3116 end_sequence ();
3117 }
3118
3119 /* Careful for being the first insn in a sequence. */
3120 if (spill_fill_data.init_after)
3121 insn = emit_insn_after (seq, spill_fill_data.init_after);
3122 else
3123 {
3124 rtx first = get_insns ();
3125 if (first)
3126 insn = emit_insn_before (seq, first);
3127 else
3128 insn = emit_insn (seq);
3129 }
3130 spill_fill_data.init_after = insn;
3131 }
3132
3133 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
3134
3135 /* ??? Not all of the spills are for varargs, but some of them are.
3136 The rest of the spills belong in an alias set of their own. But
3137 it doesn't actually hurt to include them here. */
3138 set_mem_alias_set (mem, get_varargs_alias_set ());
3139
3140 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
3141 spill_fill_data.prev_off[iter] = cfa_off;
3142
3143 if (++iter >= spill_fill_data.n_iter)
3144 iter = 0;
3145 spill_fill_data.next_iter = iter;
3146
3147 return mem;
3148 }
3149
3150 static void
3151 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
3152 rtx frame_reg)
3153 {
3154 int iter = spill_fill_data.next_iter;
3155 rtx mem, insn;
3156
3157 mem = spill_restore_mem (reg, cfa_off);
3158 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
3159 spill_fill_data.prev_insn[iter] = insn;
3160
3161 if (frame_reg)
3162 {
3163 rtx base;
3164 HOST_WIDE_INT off;
3165
3166 RTX_FRAME_RELATED_P (insn) = 1;
3167
3168 /* Don't even pretend that the unwind code can intuit its way
3169 through a pair of interleaved post_modify iterators. Just
3170 provide the correct answer. */
3171
3172 if (frame_pointer_needed)
3173 {
3174 base = hard_frame_pointer_rtx;
3175 off = - cfa_off;
3176 }
3177 else
3178 {
3179 base = stack_pointer_rtx;
3180 off = current_frame_info.total_size - cfa_off;
3181 }
3182
3183 add_reg_note (insn, REG_CFA_OFFSET,
3184 gen_rtx_SET (VOIDmode,
3185 gen_rtx_MEM (GET_MODE (reg),
3186 plus_constant (Pmode,
3187 base, off)),
3188 frame_reg));
3189 }
3190 }
3191
3192 static void
3193 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
3194 {
3195 int iter = spill_fill_data.next_iter;
3196 rtx insn;
3197
3198 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
3199 GEN_INT (cfa_off)));
3200 spill_fill_data.prev_insn[iter] = insn;
3201 }
3202
3203 /* Wrapper functions that discards the CONST_INT spill offset. These
3204 exist so that we can give gr_spill/gr_fill the offset they need and
3205 use a consistent function interface. */
3206
3207 static rtx
3208 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3209 {
3210 return gen_movdi (dest, src);
3211 }
3212
3213 static rtx
3214 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3215 {
3216 return gen_fr_spill (dest, src);
3217 }
3218
3219 static rtx
3220 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3221 {
3222 return gen_fr_restore (dest, src);
3223 }
3224
3225 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3226
3227 /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */
3228 #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0)
3229
3230 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
3231 inclusive. These are offsets from the current stack pointer. BS_SIZE
3232 is the size of the backing store. ??? This clobbers r2 and r3. */
3233
3234 static void
3235 ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size,
3236 int bs_size)
3237 {
3238 rtx r2 = gen_rtx_REG (Pmode, GR_REG (2));
3239 rtx r3 = gen_rtx_REG (Pmode, GR_REG (3));
3240 rtx p6 = gen_rtx_REG (BImode, PR_REG (6));
3241
3242 /* On the IA-64 there is a second stack in memory, namely the Backing Store
3243 of the Register Stack Engine. We also need to probe it after checking
3244 that the 2 stacks don't overlap. */
3245 emit_insn (gen_bsp_value (r3));
3246 emit_move_insn (r2, GEN_INT (-(first + size)));
3247
3248 /* Compare current value of BSP and SP registers. */
3249 emit_insn (gen_rtx_SET (VOIDmode, p6,
3250 gen_rtx_fmt_ee (LTU, BImode,
3251 r3, stack_pointer_rtx)));
3252
3253 /* Compute the address of the probe for the Backing Store (which grows
3254 towards higher addresses). We probe only at the first offset of
3255 the next page because some OS (eg Linux/ia64) only extend the
3256 backing store when this specific address is hit (but generate a SEGV
3257 on other address). Page size is the worst case (4KB). The reserve
3258 size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough.
3259 Also compute the address of the last probe for the memory stack
3260 (which grows towards lower addresses). */
3261 emit_insn (gen_rtx_SET (VOIDmode, r3, plus_constant (Pmode, r3, 4095)));
3262 emit_insn (gen_rtx_SET (VOIDmode, r2,
3263 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3264
3265 /* Compare them and raise SEGV if the former has topped the latter. */
3266 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
3267 gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx),
3268 gen_rtx_SET (VOIDmode, p6,
3269 gen_rtx_fmt_ee (GEU, BImode,
3270 r3, r2))));
3271 emit_insn (gen_rtx_SET (VOIDmode,
3272 gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12),
3273 const0_rtx),
3274 const0_rtx));
3275 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
3276 gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx),
3277 gen_rtx_TRAP_IF (VOIDmode, const1_rtx,
3278 GEN_INT (11))));
3279
3280 /* Probe the Backing Store if necessary. */
3281 if (bs_size > 0)
3282 emit_stack_probe (r3);
3283
3284 /* Probe the memory stack if necessary. */
3285 if (size == 0)
3286 ;
3287
3288 /* See if we have a constant small number of probes to generate. If so,
3289 that's the easy case. */
3290 else if (size <= PROBE_INTERVAL)
3291 emit_stack_probe (r2);
3292
3293 /* The run-time loop is made up of 8 insns in the generic case while this
3294 compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */
3295 else if (size <= 4 * PROBE_INTERVAL)
3296 {
3297 HOST_WIDE_INT i;
3298
3299 emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL)));
3300 emit_insn (gen_rtx_SET (VOIDmode, r2,
3301 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3302 emit_stack_probe (r2);
3303
3304 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3305 it exceeds SIZE. If only two probes are needed, this will not
3306 generate any code. Then probe at FIRST + SIZE. */
3307 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
3308 {
3309 emit_insn (gen_rtx_SET (VOIDmode, r2,
3310 plus_constant (Pmode, r2, -PROBE_INTERVAL)));
3311 emit_stack_probe (r2);
3312 }
3313
3314 emit_insn (gen_rtx_SET (VOIDmode, r2,
3315 plus_constant (Pmode, r2,
3316 (i - PROBE_INTERVAL) - size)));
3317 emit_stack_probe (r2);
3318 }
3319
3320 /* Otherwise, do the same as above, but in a loop. Note that we must be
3321 extra careful with variables wrapping around because we might be at
3322 the very top (or the very bottom) of the address space and we have
3323 to be able to handle this case properly; in particular, we use an
3324 equality test for the loop condition. */
3325 else
3326 {
3327 HOST_WIDE_INT rounded_size;
3328
3329 emit_move_insn (r2, GEN_INT (-first));
3330
3331
3332 /* Step 1: round SIZE to the previous multiple of the interval. */
3333
3334 rounded_size = size & -PROBE_INTERVAL;
3335
3336
3337 /* Step 2: compute initial and final value of the loop counter. */
3338
3339 /* TEST_ADDR = SP + FIRST. */
3340 emit_insn (gen_rtx_SET (VOIDmode, r2,
3341 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3342
3343 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3344 if (rounded_size > (1 << 21))
3345 {
3346 emit_move_insn (r3, GEN_INT (-rounded_size));
3347 emit_insn (gen_rtx_SET (VOIDmode, r3, gen_rtx_PLUS (Pmode, r2, r3)));
3348 }
3349 else
3350 emit_insn (gen_rtx_SET (VOIDmode, r3,
3351 gen_rtx_PLUS (Pmode, r2,
3352 GEN_INT (-rounded_size))));
3353
3354
3355 /* Step 3: the loop
3356
3357 while (TEST_ADDR != LAST_ADDR)
3358 {
3359 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3360 probe at TEST_ADDR
3361 }
3362
3363 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3364 until it is equal to ROUNDED_SIZE. */
3365
3366 emit_insn (gen_probe_stack_range (r2, r2, r3));
3367
3368
3369 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3370 that SIZE is equal to ROUNDED_SIZE. */
3371
3372 /* TEMP = SIZE - ROUNDED_SIZE. */
3373 if (size != rounded_size)
3374 {
3375 emit_insn (gen_rtx_SET (VOIDmode, r2,
3376 plus_constant (Pmode, r2,
3377 rounded_size - size)));
3378 emit_stack_probe (r2);
3379 }
3380 }
3381
3382 /* Make sure nothing is scheduled before we are done. */
3383 emit_insn (gen_blockage ());
3384 }
3385
3386 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3387 absolute addresses. */
3388
3389 const char *
3390 output_probe_stack_range (rtx reg1, rtx reg2)
3391 {
3392 static int labelno = 0;
3393 char loop_lab[32], end_lab[32];
3394 rtx xops[3];
3395
3396 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
3397 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
3398
3399 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
3400
3401 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
3402 xops[0] = reg1;
3403 xops[1] = reg2;
3404 xops[2] = gen_rtx_REG (BImode, PR_REG (6));
3405 output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops);
3406 fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [REGNO (xops[2])]);
3407 assemble_name_raw (asm_out_file, end_lab);
3408 fputc ('\n', asm_out_file);
3409
3410 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3411 xops[1] = GEN_INT (-PROBE_INTERVAL);
3412 output_asm_insn ("addl %0 = %1, %0", xops);
3413 fputs ("\t;;\n", asm_out_file);
3414
3415 /* Probe at TEST_ADDR and branch. */
3416 output_asm_insn ("probe.w.fault %0, 0", xops);
3417 fprintf (asm_out_file, "\tbr ");
3418 assemble_name_raw (asm_out_file, loop_lab);
3419 fputc ('\n', asm_out_file);
3420
3421 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
3422
3423 return "";
3424 }
3425
3426 /* Called after register allocation to add any instructions needed for the
3427 prologue. Using a prologue insn is favored compared to putting all of the
3428 instructions in output_function_prologue(), since it allows the scheduler
3429 to intermix instructions with the saves of the caller saved registers. In
3430 some cases, it might be necessary to emit a barrier instruction as the last
3431 insn to prevent such scheduling.
3432
3433 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3434 so that the debug info generation code can handle them properly.
3435
3436 The register save area is laid out like so:
3437 cfa+16
3438 [ varargs spill area ]
3439 [ fr register spill area ]
3440 [ br register spill area ]
3441 [ ar register spill area ]
3442 [ pr register spill area ]
3443 [ gr register spill area ] */
3444
3445 /* ??? Get inefficient code when the frame size is larger than can fit in an
3446 adds instruction. */
3447
3448 void
3449 ia64_expand_prologue (void)
3450 {
3451 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
3452 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
3453 rtx reg, alt_reg;
3454
3455 ia64_compute_frame_size (get_frame_size ());
3456 last_scratch_gr_reg = 15;
3457
3458 if (flag_stack_usage_info)
3459 current_function_static_stack_size = current_frame_info.total_size;
3460
3461 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
3462 {
3463 HOST_WIDE_INT size = current_frame_info.total_size;
3464 int bs_size = BACKING_STORE_SIZE (current_frame_info.n_input_regs
3465 + current_frame_info.n_local_regs);
3466
3467 if (crtl->is_leaf && !cfun->calls_alloca)
3468 {
3469 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
3470 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT,
3471 size - STACK_CHECK_PROTECT,
3472 bs_size);
3473 else if (size + bs_size > STACK_CHECK_PROTECT)
3474 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, 0, bs_size);
3475 }
3476 else if (size + bs_size > 0)
3477 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, size, bs_size);
3478 }
3479
3480 if (dump_file)
3481 {
3482 fprintf (dump_file, "ia64 frame related registers "
3483 "recorded in current_frame_info.r[]:\n");
3484 #define PRINTREG(a) if (current_frame_info.r[a]) \
3485 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3486 PRINTREG(reg_fp);
3487 PRINTREG(reg_save_b0);
3488 PRINTREG(reg_save_pr);
3489 PRINTREG(reg_save_ar_pfs);
3490 PRINTREG(reg_save_ar_unat);
3491 PRINTREG(reg_save_ar_lc);
3492 PRINTREG(reg_save_gp);
3493 #undef PRINTREG
3494 }
3495
3496 /* If there is no epilogue, then we don't need some prologue insns.
3497 We need to avoid emitting the dead prologue insns, because flow
3498 will complain about them. */
3499 if (optimize)
3500 {
3501 edge e;
3502 edge_iterator ei;
3503
3504 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds)
3505 if ((e->flags & EDGE_FAKE) == 0
3506 && (e->flags & EDGE_FALLTHRU) != 0)
3507 break;
3508 epilogue_p = (e != NULL);
3509 }
3510 else
3511 epilogue_p = 1;
3512
3513 /* Set the local, input, and output register names. We need to do this
3514 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3515 half. If we use in/loc/out register names, then we get assembler errors
3516 in crtn.S because there is no alloc insn or regstk directive in there. */
3517 if (! TARGET_REG_NAMES)
3518 {
3519 int inputs = current_frame_info.n_input_regs;
3520 int locals = current_frame_info.n_local_regs;
3521 int outputs = current_frame_info.n_output_regs;
3522
3523 for (i = 0; i < inputs; i++)
3524 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3525 for (i = 0; i < locals; i++)
3526 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3527 for (i = 0; i < outputs; i++)
3528 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3529 }
3530
3531 /* Set the frame pointer register name. The regnum is logically loc79,
3532 but of course we'll not have allocated that many locals. Rather than
3533 worrying about renumbering the existing rtxs, we adjust the name. */
3534 /* ??? This code means that we can never use one local register when
3535 there is a frame pointer. loc79 gets wasted in this case, as it is
3536 renamed to a register that will never be used. See also the try_locals
3537 code in find_gr_spill. */
3538 if (current_frame_info.r[reg_fp])
3539 {
3540 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3541 reg_names[HARD_FRAME_POINTER_REGNUM]
3542 = reg_names[current_frame_info.r[reg_fp]];
3543 reg_names[current_frame_info.r[reg_fp]] = tmp;
3544 }
3545
3546 /* We don't need an alloc instruction if we've used no outputs or locals. */
3547 if (current_frame_info.n_local_regs == 0
3548 && current_frame_info.n_output_regs == 0
3549 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3550 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3551 {
3552 /* If there is no alloc, but there are input registers used, then we
3553 need a .regstk directive. */
3554 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3555 ar_pfs_save_reg = NULL_RTX;
3556 }
3557 else
3558 {
3559 current_frame_info.need_regstk = 0;
3560
3561 if (current_frame_info.r[reg_save_ar_pfs])
3562 {
3563 regno = current_frame_info.r[reg_save_ar_pfs];
3564 reg_emitted (reg_save_ar_pfs);
3565 }
3566 else
3567 regno = next_scratch_gr_reg ();
3568 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3569
3570 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3571 GEN_INT (current_frame_info.n_input_regs),
3572 GEN_INT (current_frame_info.n_local_regs),
3573 GEN_INT (current_frame_info.n_output_regs),
3574 GEN_INT (current_frame_info.n_rotate_regs)));
3575 if (current_frame_info.r[reg_save_ar_pfs])
3576 {
3577 RTX_FRAME_RELATED_P (insn) = 1;
3578 add_reg_note (insn, REG_CFA_REGISTER,
3579 gen_rtx_SET (VOIDmode,
3580 ar_pfs_save_reg,
3581 gen_rtx_REG (DImode, AR_PFS_REGNUM)));
3582 }
3583 }
3584
3585 /* Set up frame pointer, stack pointer, and spill iterators. */
3586
3587 n_varargs = cfun->machine->n_varargs;
3588 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3589 stack_pointer_rtx, 0);
3590
3591 if (frame_pointer_needed)
3592 {
3593 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3594 RTX_FRAME_RELATED_P (insn) = 1;
3595
3596 /* Force the unwind info to recognize this as defining a new CFA,
3597 rather than some temp register setup. */
3598 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX);
3599 }
3600
3601 if (current_frame_info.total_size != 0)
3602 {
3603 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3604 rtx offset;
3605
3606 if (satisfies_constraint_I (frame_size_rtx))
3607 offset = frame_size_rtx;
3608 else
3609 {
3610 regno = next_scratch_gr_reg ();
3611 offset = gen_rtx_REG (DImode, regno);
3612 emit_move_insn (offset, frame_size_rtx);
3613 }
3614
3615 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3616 stack_pointer_rtx, offset));
3617
3618 if (! frame_pointer_needed)
3619 {
3620 RTX_FRAME_RELATED_P (insn) = 1;
3621 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3622 gen_rtx_SET (VOIDmode,
3623 stack_pointer_rtx,
3624 gen_rtx_PLUS (DImode,
3625 stack_pointer_rtx,
3626 frame_size_rtx)));
3627 }
3628
3629 /* ??? At this point we must generate a magic insn that appears to
3630 modify the stack pointer, the frame pointer, and all spill
3631 iterators. This would allow the most scheduling freedom. For
3632 now, just hard stop. */
3633 emit_insn (gen_blockage ());
3634 }
3635
3636 /* Must copy out ar.unat before doing any integer spills. */
3637 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3638 {
3639 if (current_frame_info.r[reg_save_ar_unat])
3640 {
3641 ar_unat_save_reg
3642 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3643 reg_emitted (reg_save_ar_unat);
3644 }
3645 else
3646 {
3647 alt_regno = next_scratch_gr_reg ();
3648 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3649 current_frame_info.gr_used_mask |= 1 << alt_regno;
3650 }
3651
3652 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3653 insn = emit_move_insn (ar_unat_save_reg, reg);
3654 if (current_frame_info.r[reg_save_ar_unat])
3655 {
3656 RTX_FRAME_RELATED_P (insn) = 1;
3657 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3658 }
3659
3660 /* Even if we're not going to generate an epilogue, we still
3661 need to save the register so that EH works. */
3662 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3663 emit_insn (gen_prologue_use (ar_unat_save_reg));
3664 }
3665 else
3666 ar_unat_save_reg = NULL_RTX;
3667
3668 /* Spill all varargs registers. Do this before spilling any GR registers,
3669 since we want the UNAT bits for the GR registers to override the UNAT
3670 bits from varargs, which we don't care about. */
3671
3672 cfa_off = -16;
3673 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3674 {
3675 reg = gen_rtx_REG (DImode, regno);
3676 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3677 }
3678
3679 /* Locate the bottom of the register save area. */
3680 cfa_off = (current_frame_info.spill_cfa_off
3681 + current_frame_info.spill_size
3682 + current_frame_info.extra_spill_size);
3683
3684 /* Save the predicate register block either in a register or in memory. */
3685 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3686 {
3687 reg = gen_rtx_REG (DImode, PR_REG (0));
3688 if (current_frame_info.r[reg_save_pr] != 0)
3689 {
3690 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3691 reg_emitted (reg_save_pr);
3692 insn = emit_move_insn (alt_reg, reg);
3693
3694 /* ??? Denote pr spill/fill by a DImode move that modifies all
3695 64 hard registers. */
3696 RTX_FRAME_RELATED_P (insn) = 1;
3697 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3698
3699 /* Even if we're not going to generate an epilogue, we still
3700 need to save the register so that EH works. */
3701 if (! epilogue_p)
3702 emit_insn (gen_prologue_use (alt_reg));
3703 }
3704 else
3705 {
3706 alt_regno = next_scratch_gr_reg ();
3707 alt_reg = gen_rtx_REG (DImode, alt_regno);
3708 insn = emit_move_insn (alt_reg, reg);
3709 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3710 cfa_off -= 8;
3711 }
3712 }
3713
3714 /* Handle AR regs in numerical order. All of them get special handling. */
3715 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3716 && current_frame_info.r[reg_save_ar_unat] == 0)
3717 {
3718 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3719 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3720 cfa_off -= 8;
3721 }
3722
3723 /* The alloc insn already copied ar.pfs into a general register. The
3724 only thing we have to do now is copy that register to a stack slot
3725 if we'd not allocated a local register for the job. */
3726 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3727 && current_frame_info.r[reg_save_ar_pfs] == 0)
3728 {
3729 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3730 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3731 cfa_off -= 8;
3732 }
3733
3734 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3735 {
3736 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3737 if (current_frame_info.r[reg_save_ar_lc] != 0)
3738 {
3739 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3740 reg_emitted (reg_save_ar_lc);
3741 insn = emit_move_insn (alt_reg, reg);
3742 RTX_FRAME_RELATED_P (insn) = 1;
3743 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3744
3745 /* Even if we're not going to generate an epilogue, we still
3746 need to save the register so that EH works. */
3747 if (! epilogue_p)
3748 emit_insn (gen_prologue_use (alt_reg));
3749 }
3750 else
3751 {
3752 alt_regno = next_scratch_gr_reg ();
3753 alt_reg = gen_rtx_REG (DImode, alt_regno);
3754 emit_move_insn (alt_reg, reg);
3755 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3756 cfa_off -= 8;
3757 }
3758 }
3759
3760 /* Save the return pointer. */
3761 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3762 {
3763 reg = gen_rtx_REG (DImode, BR_REG (0));
3764 if (current_frame_info.r[reg_save_b0] != 0)
3765 {
3766 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3767 reg_emitted (reg_save_b0);
3768 insn = emit_move_insn (alt_reg, reg);
3769 RTX_FRAME_RELATED_P (insn) = 1;
3770 add_reg_note (insn, REG_CFA_REGISTER,
3771 gen_rtx_SET (VOIDmode, alt_reg, pc_rtx));
3772
3773 /* Even if we're not going to generate an epilogue, we still
3774 need to save the register so that EH works. */
3775 if (! epilogue_p)
3776 emit_insn (gen_prologue_use (alt_reg));
3777 }
3778 else
3779 {
3780 alt_regno = next_scratch_gr_reg ();
3781 alt_reg = gen_rtx_REG (DImode, alt_regno);
3782 emit_move_insn (alt_reg, reg);
3783 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3784 cfa_off -= 8;
3785 }
3786 }
3787
3788 if (current_frame_info.r[reg_save_gp])
3789 {
3790 reg_emitted (reg_save_gp);
3791 insn = emit_move_insn (gen_rtx_REG (DImode,
3792 current_frame_info.r[reg_save_gp]),
3793 pic_offset_table_rtx);
3794 }
3795
3796 /* We should now be at the base of the gr/br/fr spill area. */
3797 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3798 + current_frame_info.spill_size));
3799
3800 /* Spill all general registers. */
3801 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3802 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3803 {
3804 reg = gen_rtx_REG (DImode, regno);
3805 do_spill (gen_gr_spill, reg, cfa_off, reg);
3806 cfa_off -= 8;
3807 }
3808
3809 /* Spill the rest of the BR registers. */
3810 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3811 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3812 {
3813 alt_regno = next_scratch_gr_reg ();
3814 alt_reg = gen_rtx_REG (DImode, alt_regno);
3815 reg = gen_rtx_REG (DImode, regno);
3816 emit_move_insn (alt_reg, reg);
3817 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3818 cfa_off -= 8;
3819 }
3820
3821 /* Align the frame and spill all FR registers. */
3822 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3823 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3824 {
3825 gcc_assert (!(cfa_off & 15));
3826 reg = gen_rtx_REG (XFmode, regno);
3827 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3828 cfa_off -= 16;
3829 }
3830
3831 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3832
3833 finish_spill_pointers ();
3834 }
3835
3836 /* Output the textual info surrounding the prologue. */
3837
3838 void
3839 ia64_start_function (FILE *file, const char *fnname,
3840 tree decl ATTRIBUTE_UNUSED)
3841 {
3842 #if TARGET_ABI_OPEN_VMS
3843 vms_start_function (fnname);
3844 #endif
3845
3846 fputs ("\t.proc ", file);
3847 assemble_name (file, fnname);
3848 fputc ('\n', file);
3849 ASM_OUTPUT_LABEL (file, fnname);
3850 }
3851
3852 /* Called after register allocation to add any instructions needed for the
3853 epilogue. Using an epilogue insn is favored compared to putting all of the
3854 instructions in output_function_prologue(), since it allows the scheduler
3855 to intermix instructions with the saves of the caller saved registers. In
3856 some cases, it might be necessary to emit a barrier instruction as the last
3857 insn to prevent such scheduling. */
3858
3859 void
3860 ia64_expand_epilogue (int sibcall_p)
3861 {
3862 rtx insn, reg, alt_reg, ar_unat_save_reg;
3863 int regno, alt_regno, cfa_off;
3864
3865 ia64_compute_frame_size (get_frame_size ());
3866
3867 /* If there is a frame pointer, then we use it instead of the stack
3868 pointer, so that the stack pointer does not need to be valid when
3869 the epilogue starts. See EXIT_IGNORE_STACK. */
3870 if (frame_pointer_needed)
3871 setup_spill_pointers (current_frame_info.n_spilled,
3872 hard_frame_pointer_rtx, 0);
3873 else
3874 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3875 current_frame_info.total_size);
3876
3877 if (current_frame_info.total_size != 0)
3878 {
3879 /* ??? At this point we must generate a magic insn that appears to
3880 modify the spill iterators and the frame pointer. This would
3881 allow the most scheduling freedom. For now, just hard stop. */
3882 emit_insn (gen_blockage ());
3883 }
3884
3885 /* Locate the bottom of the register save area. */
3886 cfa_off = (current_frame_info.spill_cfa_off
3887 + current_frame_info.spill_size
3888 + current_frame_info.extra_spill_size);
3889
3890 /* Restore the predicate registers. */
3891 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3892 {
3893 if (current_frame_info.r[reg_save_pr] != 0)
3894 {
3895 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3896 reg_emitted (reg_save_pr);
3897 }
3898 else
3899 {
3900 alt_regno = next_scratch_gr_reg ();
3901 alt_reg = gen_rtx_REG (DImode, alt_regno);
3902 do_restore (gen_movdi_x, alt_reg, cfa_off);
3903 cfa_off -= 8;
3904 }
3905 reg = gen_rtx_REG (DImode, PR_REG (0));
3906 emit_move_insn (reg, alt_reg);
3907 }
3908
3909 /* Restore the application registers. */
3910
3911 /* Load the saved unat from the stack, but do not restore it until
3912 after the GRs have been restored. */
3913 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3914 {
3915 if (current_frame_info.r[reg_save_ar_unat] != 0)
3916 {
3917 ar_unat_save_reg
3918 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3919 reg_emitted (reg_save_ar_unat);
3920 }
3921 else
3922 {
3923 alt_regno = next_scratch_gr_reg ();
3924 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3925 current_frame_info.gr_used_mask |= 1 << alt_regno;
3926 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3927 cfa_off -= 8;
3928 }
3929 }
3930 else
3931 ar_unat_save_reg = NULL_RTX;
3932
3933 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3934 {
3935 reg_emitted (reg_save_ar_pfs);
3936 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3937 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3938 emit_move_insn (reg, alt_reg);
3939 }
3940 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3941 {
3942 alt_regno = next_scratch_gr_reg ();
3943 alt_reg = gen_rtx_REG (DImode, alt_regno);
3944 do_restore (gen_movdi_x, alt_reg, cfa_off);
3945 cfa_off -= 8;
3946 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3947 emit_move_insn (reg, alt_reg);
3948 }
3949
3950 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3951 {
3952 if (current_frame_info.r[reg_save_ar_lc] != 0)
3953 {
3954 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3955 reg_emitted (reg_save_ar_lc);
3956 }
3957 else
3958 {
3959 alt_regno = next_scratch_gr_reg ();
3960 alt_reg = gen_rtx_REG (DImode, alt_regno);
3961 do_restore (gen_movdi_x, alt_reg, cfa_off);
3962 cfa_off -= 8;
3963 }
3964 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3965 emit_move_insn (reg, alt_reg);
3966 }
3967
3968 /* Restore the return pointer. */
3969 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3970 {
3971 if (current_frame_info.r[reg_save_b0] != 0)
3972 {
3973 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3974 reg_emitted (reg_save_b0);
3975 }
3976 else
3977 {
3978 alt_regno = next_scratch_gr_reg ();
3979 alt_reg = gen_rtx_REG (DImode, alt_regno);
3980 do_restore (gen_movdi_x, alt_reg, cfa_off);
3981 cfa_off -= 8;
3982 }
3983 reg = gen_rtx_REG (DImode, BR_REG (0));
3984 emit_move_insn (reg, alt_reg);
3985 }
3986
3987 /* We should now be at the base of the gr/br/fr spill area. */
3988 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3989 + current_frame_info.spill_size));
3990
3991 /* The GP may be stored on the stack in the prologue, but it's
3992 never restored in the epilogue. Skip the stack slot. */
3993 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3994 cfa_off -= 8;
3995
3996 /* Restore all general registers. */
3997 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3998 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3999 {
4000 reg = gen_rtx_REG (DImode, regno);
4001 do_restore (gen_gr_restore, reg, cfa_off);
4002 cfa_off -= 8;
4003 }
4004
4005 /* Restore the branch registers. */
4006 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
4007 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4008 {
4009 alt_regno = next_scratch_gr_reg ();
4010 alt_reg = gen_rtx_REG (DImode, alt_regno);
4011 do_restore (gen_movdi_x, alt_reg, cfa_off);
4012 cfa_off -= 8;
4013 reg = gen_rtx_REG (DImode, regno);
4014 emit_move_insn (reg, alt_reg);
4015 }
4016
4017 /* Restore floating point registers. */
4018 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
4019 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4020 {
4021 gcc_assert (!(cfa_off & 15));
4022 reg = gen_rtx_REG (XFmode, regno);
4023 do_restore (gen_fr_restore_x, reg, cfa_off);
4024 cfa_off -= 16;
4025 }
4026
4027 /* Restore ar.unat for real. */
4028 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
4029 {
4030 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
4031 emit_move_insn (reg, ar_unat_save_reg);
4032 }
4033
4034 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
4035
4036 finish_spill_pointers ();
4037
4038 if (current_frame_info.total_size
4039 || cfun->machine->ia64_eh_epilogue_sp
4040 || frame_pointer_needed)
4041 {
4042 /* ??? At this point we must generate a magic insn that appears to
4043 modify the spill iterators, the stack pointer, and the frame
4044 pointer. This would allow the most scheduling freedom. For now,
4045 just hard stop. */
4046 emit_insn (gen_blockage ());
4047 }
4048
4049 if (cfun->machine->ia64_eh_epilogue_sp)
4050 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
4051 else if (frame_pointer_needed)
4052 {
4053 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
4054 RTX_FRAME_RELATED_P (insn) = 1;
4055 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL);
4056 }
4057 else if (current_frame_info.total_size)
4058 {
4059 rtx offset, frame_size_rtx;
4060
4061 frame_size_rtx = GEN_INT (current_frame_info.total_size);
4062 if (satisfies_constraint_I (frame_size_rtx))
4063 offset = frame_size_rtx;
4064 else
4065 {
4066 regno = next_scratch_gr_reg ();
4067 offset = gen_rtx_REG (DImode, regno);
4068 emit_move_insn (offset, frame_size_rtx);
4069 }
4070
4071 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
4072 offset));
4073
4074 RTX_FRAME_RELATED_P (insn) = 1;
4075 add_reg_note (insn, REG_CFA_ADJUST_CFA,
4076 gen_rtx_SET (VOIDmode,
4077 stack_pointer_rtx,
4078 gen_rtx_PLUS (DImode,
4079 stack_pointer_rtx,
4080 frame_size_rtx)));
4081 }
4082
4083 if (cfun->machine->ia64_eh_epilogue_bsp)
4084 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
4085
4086 if (! sibcall_p)
4087 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
4088 else
4089 {
4090 int fp = GR_REG (2);
4091 /* We need a throw away register here, r0 and r1 are reserved,
4092 so r2 is the first available call clobbered register. If
4093 there was a frame_pointer register, we may have swapped the
4094 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
4095 sure we're using the string "r2" when emitting the register
4096 name for the assembler. */
4097 if (current_frame_info.r[reg_fp]
4098 && current_frame_info.r[reg_fp] == GR_REG (2))
4099 fp = HARD_FRAME_POINTER_REGNUM;
4100
4101 /* We must emit an alloc to force the input registers to become output
4102 registers. Otherwise, if the callee tries to pass its parameters
4103 through to another call without an intervening alloc, then these
4104 values get lost. */
4105 /* ??? We don't need to preserve all input registers. We only need to
4106 preserve those input registers used as arguments to the sibling call.
4107 It is unclear how to compute that number here. */
4108 if (current_frame_info.n_input_regs != 0)
4109 {
4110 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
4111
4112 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
4113 const0_rtx, const0_rtx,
4114 n_inputs, const0_rtx));
4115 RTX_FRAME_RELATED_P (insn) = 1;
4116
4117 /* ??? We need to mark the alloc as frame-related so that it gets
4118 passed into ia64_asm_unwind_emit for ia64-specific unwinding.
4119 But there's nothing dwarf2 related to be done wrt the register
4120 windows. If we do nothing, dwarf2out will abort on the UNSPEC;
4121 the empty parallel means dwarf2out will not see anything. */
4122 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4123 gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0)));
4124 }
4125 }
4126 }
4127
4128 /* Return 1 if br.ret can do all the work required to return from a
4129 function. */
4130
4131 int
4132 ia64_direct_return (void)
4133 {
4134 if (reload_completed && ! frame_pointer_needed)
4135 {
4136 ia64_compute_frame_size (get_frame_size ());
4137
4138 return (current_frame_info.total_size == 0
4139 && current_frame_info.n_spilled == 0
4140 && current_frame_info.r[reg_save_b0] == 0
4141 && current_frame_info.r[reg_save_pr] == 0
4142 && current_frame_info.r[reg_save_ar_pfs] == 0
4143 && current_frame_info.r[reg_save_ar_unat] == 0
4144 && current_frame_info.r[reg_save_ar_lc] == 0);
4145 }
4146 return 0;
4147 }
4148
4149 /* Return the magic cookie that we use to hold the return address
4150 during early compilation. */
4151
4152 rtx
4153 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
4154 {
4155 if (count != 0)
4156 return NULL;
4157 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
4158 }
4159
4160 /* Split this value after reload, now that we know where the return
4161 address is saved. */
4162
4163 void
4164 ia64_split_return_addr_rtx (rtx dest)
4165 {
4166 rtx src;
4167
4168 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
4169 {
4170 if (current_frame_info.r[reg_save_b0] != 0)
4171 {
4172 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4173 reg_emitted (reg_save_b0);
4174 }
4175 else
4176 {
4177 HOST_WIDE_INT off;
4178 unsigned int regno;
4179 rtx off_r;
4180
4181 /* Compute offset from CFA for BR0. */
4182 /* ??? Must be kept in sync with ia64_expand_prologue. */
4183 off = (current_frame_info.spill_cfa_off
4184 + current_frame_info.spill_size);
4185 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
4186 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4187 off -= 8;
4188
4189 /* Convert CFA offset to a register based offset. */
4190 if (frame_pointer_needed)
4191 src = hard_frame_pointer_rtx;
4192 else
4193 {
4194 src = stack_pointer_rtx;
4195 off += current_frame_info.total_size;
4196 }
4197
4198 /* Load address into scratch register. */
4199 off_r = GEN_INT (off);
4200 if (satisfies_constraint_I (off_r))
4201 emit_insn (gen_adddi3 (dest, src, off_r));
4202 else
4203 {
4204 emit_move_insn (dest, off_r);
4205 emit_insn (gen_adddi3 (dest, src, dest));
4206 }
4207
4208 src = gen_rtx_MEM (Pmode, dest);
4209 }
4210 }
4211 else
4212 src = gen_rtx_REG (DImode, BR_REG (0));
4213
4214 emit_move_insn (dest, src);
4215 }
4216
4217 int
4218 ia64_hard_regno_rename_ok (int from, int to)
4219 {
4220 /* Don't clobber any of the registers we reserved for the prologue. */
4221 unsigned int r;
4222
4223 for (r = reg_fp; r <= reg_save_ar_lc; r++)
4224 if (to == current_frame_info.r[r]
4225 || from == current_frame_info.r[r]
4226 || to == emitted_frame_related_regs[r]
4227 || from == emitted_frame_related_regs[r])
4228 return 0;
4229
4230 /* Don't use output registers outside the register frame. */
4231 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
4232 return 0;
4233
4234 /* Retain even/oddness on predicate register pairs. */
4235 if (PR_REGNO_P (from) && PR_REGNO_P (to))
4236 return (from & 1) == (to & 1);
4237
4238 return 1;
4239 }
4240
4241 /* Target hook for assembling integer objects. Handle word-sized
4242 aligned objects and detect the cases when @fptr is needed. */
4243
4244 static bool
4245 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
4246 {
4247 if (size == POINTER_SIZE / BITS_PER_UNIT
4248 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
4249 && GET_CODE (x) == SYMBOL_REF
4250 && SYMBOL_REF_FUNCTION_P (x))
4251 {
4252 static const char * const directive[2][2] = {
4253 /* 64-bit pointer */ /* 32-bit pointer */
4254 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
4255 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
4256 };
4257 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
4258 output_addr_const (asm_out_file, x);
4259 fputs (")\n", asm_out_file);
4260 return true;
4261 }
4262 return default_assemble_integer (x, size, aligned_p);
4263 }
4264
4265 /* Emit the function prologue. */
4266
4267 static void
4268 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4269 {
4270 int mask, grsave, grsave_prev;
4271
4272 if (current_frame_info.need_regstk)
4273 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
4274 current_frame_info.n_input_regs,
4275 current_frame_info.n_local_regs,
4276 current_frame_info.n_output_regs,
4277 current_frame_info.n_rotate_regs);
4278
4279 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4280 return;
4281
4282 /* Emit the .prologue directive. */
4283
4284 mask = 0;
4285 grsave = grsave_prev = 0;
4286 if (current_frame_info.r[reg_save_b0] != 0)
4287 {
4288 mask |= 8;
4289 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
4290 }
4291 if (current_frame_info.r[reg_save_ar_pfs] != 0
4292 && (grsave_prev == 0
4293 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
4294 {
4295 mask |= 4;
4296 if (grsave_prev == 0)
4297 grsave = current_frame_info.r[reg_save_ar_pfs];
4298 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
4299 }
4300 if (current_frame_info.r[reg_fp] != 0
4301 && (grsave_prev == 0
4302 || current_frame_info.r[reg_fp] == grsave_prev + 1))
4303 {
4304 mask |= 2;
4305 if (grsave_prev == 0)
4306 grsave = HARD_FRAME_POINTER_REGNUM;
4307 grsave_prev = current_frame_info.r[reg_fp];
4308 }
4309 if (current_frame_info.r[reg_save_pr] != 0
4310 && (grsave_prev == 0
4311 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
4312 {
4313 mask |= 1;
4314 if (grsave_prev == 0)
4315 grsave = current_frame_info.r[reg_save_pr];
4316 }
4317
4318 if (mask && TARGET_GNU_AS)
4319 fprintf (file, "\t.prologue %d, %d\n", mask,
4320 ia64_dbx_register_number (grsave));
4321 else
4322 fputs ("\t.prologue\n", file);
4323
4324 /* Emit a .spill directive, if necessary, to relocate the base of
4325 the register spill area. */
4326 if (current_frame_info.spill_cfa_off != -16)
4327 fprintf (file, "\t.spill %ld\n",
4328 (long) (current_frame_info.spill_cfa_off
4329 + current_frame_info.spill_size));
4330 }
4331
4332 /* Emit the .body directive at the scheduled end of the prologue. */
4333
4334 static void
4335 ia64_output_function_end_prologue (FILE *file)
4336 {
4337 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4338 return;
4339
4340 fputs ("\t.body\n", file);
4341 }
4342
4343 /* Emit the function epilogue. */
4344
4345 static void
4346 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
4347 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4348 {
4349 int i;
4350
4351 if (current_frame_info.r[reg_fp])
4352 {
4353 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
4354 reg_names[HARD_FRAME_POINTER_REGNUM]
4355 = reg_names[current_frame_info.r[reg_fp]];
4356 reg_names[current_frame_info.r[reg_fp]] = tmp;
4357 reg_emitted (reg_fp);
4358 }
4359 if (! TARGET_REG_NAMES)
4360 {
4361 for (i = 0; i < current_frame_info.n_input_regs; i++)
4362 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
4363 for (i = 0; i < current_frame_info.n_local_regs; i++)
4364 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
4365 for (i = 0; i < current_frame_info.n_output_regs; i++)
4366 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
4367 }
4368
4369 current_frame_info.initialized = 0;
4370 }
4371
4372 int
4373 ia64_dbx_register_number (int regno)
4374 {
4375 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4376 from its home at loc79 to something inside the register frame. We
4377 must perform the same renumbering here for the debug info. */
4378 if (current_frame_info.r[reg_fp])
4379 {
4380 if (regno == HARD_FRAME_POINTER_REGNUM)
4381 regno = current_frame_info.r[reg_fp];
4382 else if (regno == current_frame_info.r[reg_fp])
4383 regno = HARD_FRAME_POINTER_REGNUM;
4384 }
4385
4386 if (IN_REGNO_P (regno))
4387 return 32 + regno - IN_REG (0);
4388 else if (LOC_REGNO_P (regno))
4389 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
4390 else if (OUT_REGNO_P (regno))
4391 return (32 + current_frame_info.n_input_regs
4392 + current_frame_info.n_local_regs + regno - OUT_REG (0));
4393 else
4394 return regno;
4395 }
4396
4397 /* Implement TARGET_TRAMPOLINE_INIT.
4398
4399 The trampoline should set the static chain pointer to value placed
4400 into the trampoline and should branch to the specified routine.
4401 To make the normal indirect-subroutine calling convention work,
4402 the trampoline must look like a function descriptor; the first
4403 word being the target address and the second being the target's
4404 global pointer.
4405
4406 We abuse the concept of a global pointer by arranging for it
4407 to point to the data we need to load. The complete trampoline
4408 has the following form:
4409
4410 +-------------------+ \
4411 TRAMP: | __ia64_trampoline | |
4412 +-------------------+ > fake function descriptor
4413 | TRAMP+16 | |
4414 +-------------------+ /
4415 | target descriptor |
4416 +-------------------+
4417 | static link |
4418 +-------------------+
4419 */
4420
4421 static void
4422 ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
4423 {
4424 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4425 rtx addr, addr_reg, tramp, eight = GEN_INT (8);
4426
4427 /* The Intel assembler requires that the global __ia64_trampoline symbol
4428 be declared explicitly */
4429 if (!TARGET_GNU_AS)
4430 {
4431 static bool declared_ia64_trampoline = false;
4432
4433 if (!declared_ia64_trampoline)
4434 {
4435 declared_ia64_trampoline = true;
4436 (*targetm.asm_out.globalize_label) (asm_out_file,
4437 "__ia64_trampoline");
4438 }
4439 }
4440
4441 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4442 addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
4443 fnaddr = convert_memory_address (Pmode, fnaddr);
4444 static_chain = convert_memory_address (Pmode, static_chain);
4445
4446 /* Load up our iterator. */
4447 addr_reg = copy_to_reg (addr);
4448 m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
4449
4450 /* The first two words are the fake descriptor:
4451 __ia64_trampoline, ADDR+16. */
4452 tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
4453 if (TARGET_ABI_OPEN_VMS)
4454 {
4455 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4456 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4457 relocation against function symbols to make it identical to the
4458 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4459 strict ELF and dereference to get the bare code address. */
4460 rtx reg = gen_reg_rtx (Pmode);
4461 SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
4462 emit_move_insn (reg, tramp);
4463 emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
4464 tramp = reg;
4465 }
4466 emit_move_insn (m_tramp, tramp);
4467 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4468 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4469
4470 emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16)));
4471 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4472 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4473
4474 /* The third word is the target descriptor. */
4475 emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
4476 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4477 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4478
4479 /* The fourth word is the static chain. */
4480 emit_move_insn (m_tramp, static_chain);
4481 }
4482 \f
4483 /* Do any needed setup for a variadic function. CUM has not been updated
4484 for the last named argument which has type TYPE and mode MODE.
4485
4486 We generate the actual spill instructions during prologue generation. */
4487
4488 static void
4489 ia64_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
4490 tree type, int * pretend_size,
4491 int second_time ATTRIBUTE_UNUSED)
4492 {
4493 CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum);
4494
4495 /* Skip the current argument. */
4496 ia64_function_arg_advance (pack_cumulative_args (&next_cum), mode, type, 1);
4497
4498 if (next_cum.words < MAX_ARGUMENT_SLOTS)
4499 {
4500 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
4501 *pretend_size = n * UNITS_PER_WORD;
4502 cfun->machine->n_varargs = n;
4503 }
4504 }
4505
4506 /* Check whether TYPE is a homogeneous floating point aggregate. If
4507 it is, return the mode of the floating point type that appears
4508 in all leafs. If it is not, return VOIDmode.
4509
4510 An aggregate is a homogeneous floating point aggregate is if all
4511 fields/elements in it have the same floating point type (e.g,
4512 SFmode). 128-bit quad-precision floats are excluded.
4513
4514 Variable sized aggregates should never arrive here, since we should
4515 have already decided to pass them by reference. Top-level zero-sized
4516 aggregates are excluded because our parallels crash the middle-end. */
4517
4518 static enum machine_mode
4519 hfa_element_mode (const_tree type, bool nested)
4520 {
4521 enum machine_mode element_mode = VOIDmode;
4522 enum machine_mode mode;
4523 enum tree_code code = TREE_CODE (type);
4524 int know_element_mode = 0;
4525 tree t;
4526
4527 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
4528 return VOIDmode;
4529
4530 switch (code)
4531 {
4532 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
4533 case BOOLEAN_TYPE: case POINTER_TYPE:
4534 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
4535 case LANG_TYPE: case FUNCTION_TYPE:
4536 return VOIDmode;
4537
4538 /* Fortran complex types are supposed to be HFAs, so we need to handle
4539 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4540 types though. */
4541 case COMPLEX_TYPE:
4542 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
4543 && TYPE_MODE (type) != TCmode)
4544 return GET_MODE_INNER (TYPE_MODE (type));
4545 else
4546 return VOIDmode;
4547
4548 case REAL_TYPE:
4549 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4550 mode if this is contained within an aggregate. */
4551 if (nested && TYPE_MODE (type) != TFmode)
4552 return TYPE_MODE (type);
4553 else
4554 return VOIDmode;
4555
4556 case ARRAY_TYPE:
4557 return hfa_element_mode (TREE_TYPE (type), 1);
4558
4559 case RECORD_TYPE:
4560 case UNION_TYPE:
4561 case QUAL_UNION_TYPE:
4562 for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t))
4563 {
4564 if (TREE_CODE (t) != FIELD_DECL)
4565 continue;
4566
4567 mode = hfa_element_mode (TREE_TYPE (t), 1);
4568 if (know_element_mode)
4569 {
4570 if (mode != element_mode)
4571 return VOIDmode;
4572 }
4573 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
4574 return VOIDmode;
4575 else
4576 {
4577 know_element_mode = 1;
4578 element_mode = mode;
4579 }
4580 }
4581 return element_mode;
4582
4583 default:
4584 /* If we reach here, we probably have some front-end specific type
4585 that the backend doesn't know about. This can happen via the
4586 aggregate_value_p call in init_function_start. All we can do is
4587 ignore unknown tree types. */
4588 return VOIDmode;
4589 }
4590
4591 return VOIDmode;
4592 }
4593
4594 /* Return the number of words required to hold a quantity of TYPE and MODE
4595 when passed as an argument. */
4596 static int
4597 ia64_function_arg_words (const_tree type, enum machine_mode mode)
4598 {
4599 int words;
4600
4601 if (mode == BLKmode)
4602 words = int_size_in_bytes (type);
4603 else
4604 words = GET_MODE_SIZE (mode);
4605
4606 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4607 }
4608
4609 /* Return the number of registers that should be skipped so the current
4610 argument (described by TYPE and WORDS) will be properly aligned.
4611
4612 Integer and float arguments larger than 8 bytes start at the next
4613 even boundary. Aggregates larger than 8 bytes start at the next
4614 even boundary if the aggregate has 16 byte alignment. Note that
4615 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4616 but are still to be aligned in registers.
4617
4618 ??? The ABI does not specify how to handle aggregates with
4619 alignment from 9 to 15 bytes, or greater than 16. We handle them
4620 all as if they had 16 byte alignment. Such aggregates can occur
4621 only if gcc extensions are used. */
4622 static int
4623 ia64_function_arg_offset (const CUMULATIVE_ARGS *cum,
4624 const_tree type, int words)
4625 {
4626 /* No registers are skipped on VMS. */
4627 if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
4628 return 0;
4629
4630 if (type
4631 && TREE_CODE (type) != INTEGER_TYPE
4632 && TREE_CODE (type) != REAL_TYPE)
4633 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4634 else
4635 return words > 1;
4636 }
4637
4638 /* Return rtx for register where argument is passed, or zero if it is passed
4639 on the stack. */
4640 /* ??? 128-bit quad-precision floats are always passed in general
4641 registers. */
4642
4643 static rtx
4644 ia64_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
4645 const_tree type, bool named, bool incoming)
4646 {
4647 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4648
4649 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4650 int words = ia64_function_arg_words (type, mode);
4651 int offset = ia64_function_arg_offset (cum, type, words);
4652 enum machine_mode hfa_mode = VOIDmode;
4653
4654 /* For OPEN VMS, emit the instruction setting up the argument register here,
4655 when we know this will be together with the other arguments setup related
4656 insns. This is not the conceptually best place to do this, but this is
4657 the easiest as we have convenient access to cumulative args info. */
4658
4659 if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
4660 && named == 1)
4661 {
4662 unsigned HOST_WIDE_INT regval = cum->words;
4663 int i;
4664
4665 for (i = 0; i < 8; i++)
4666 regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
4667
4668 emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4669 GEN_INT (regval));
4670 }
4671
4672 /* If all argument slots are used, then it must go on the stack. */
4673 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4674 return 0;
4675
4676 /* On OpenVMS argument is either in Rn or Fn. */
4677 if (TARGET_ABI_OPEN_VMS)
4678 {
4679 if (FLOAT_MODE_P (mode))
4680 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
4681 else
4682 return gen_rtx_REG (mode, basereg + cum->words);
4683 }
4684
4685 /* Check for and handle homogeneous FP aggregates. */
4686 if (type)
4687 hfa_mode = hfa_element_mode (type, 0);
4688
4689 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4690 and unprototyped hfas are passed specially. */
4691 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4692 {
4693 rtx loc[16];
4694 int i = 0;
4695 int fp_regs = cum->fp_regs;
4696 int int_regs = cum->words + offset;
4697 int hfa_size = GET_MODE_SIZE (hfa_mode);
4698 int byte_size;
4699 int args_byte_size;
4700
4701 /* If prototyped, pass it in FR regs then GR regs.
4702 If not prototyped, pass it in both FR and GR regs.
4703
4704 If this is an SFmode aggregate, then it is possible to run out of
4705 FR regs while GR regs are still left. In that case, we pass the
4706 remaining part in the GR regs. */
4707
4708 /* Fill the FP regs. We do this always. We stop if we reach the end
4709 of the argument, the last FP register, or the last argument slot. */
4710
4711 byte_size = ((mode == BLKmode)
4712 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4713 args_byte_size = int_regs * UNITS_PER_WORD;
4714 offset = 0;
4715 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4716 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4717 {
4718 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4719 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4720 + fp_regs)),
4721 GEN_INT (offset));
4722 offset += hfa_size;
4723 args_byte_size += hfa_size;
4724 fp_regs++;
4725 }
4726
4727 /* If no prototype, then the whole thing must go in GR regs. */
4728 if (! cum->prototype)
4729 offset = 0;
4730 /* If this is an SFmode aggregate, then we might have some left over
4731 that needs to go in GR regs. */
4732 else if (byte_size != offset)
4733 int_regs += offset / UNITS_PER_WORD;
4734
4735 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4736
4737 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4738 {
4739 enum machine_mode gr_mode = DImode;
4740 unsigned int gr_size;
4741
4742 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4743 then this goes in a GR reg left adjusted/little endian, right
4744 adjusted/big endian. */
4745 /* ??? Currently this is handled wrong, because 4-byte hunks are
4746 always right adjusted/little endian. */
4747 if (offset & 0x4)
4748 gr_mode = SImode;
4749 /* If we have an even 4 byte hunk because the aggregate is a
4750 multiple of 4 bytes in size, then this goes in a GR reg right
4751 adjusted/little endian. */
4752 else if (byte_size - offset == 4)
4753 gr_mode = SImode;
4754
4755 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4756 gen_rtx_REG (gr_mode, (basereg
4757 + int_regs)),
4758 GEN_INT (offset));
4759
4760 gr_size = GET_MODE_SIZE (gr_mode);
4761 offset += gr_size;
4762 if (gr_size == UNITS_PER_WORD
4763 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4764 int_regs++;
4765 else if (gr_size > UNITS_PER_WORD)
4766 int_regs += gr_size / UNITS_PER_WORD;
4767 }
4768 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4769 }
4770
4771 /* Integral and aggregates go in general registers. If we have run out of
4772 FR registers, then FP values must also go in general registers. This can
4773 happen when we have a SFmode HFA. */
4774 else if (mode == TFmode || mode == TCmode
4775 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4776 {
4777 int byte_size = ((mode == BLKmode)
4778 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4779 if (BYTES_BIG_ENDIAN
4780 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4781 && byte_size < UNITS_PER_WORD
4782 && byte_size > 0)
4783 {
4784 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4785 gen_rtx_REG (DImode,
4786 (basereg + cum->words
4787 + offset)),
4788 const0_rtx);
4789 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4790 }
4791 else
4792 return gen_rtx_REG (mode, basereg + cum->words + offset);
4793
4794 }
4795
4796 /* If there is a prototype, then FP values go in a FR register when
4797 named, and in a GR register when unnamed. */
4798 else if (cum->prototype)
4799 {
4800 if (named)
4801 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4802 /* In big-endian mode, an anonymous SFmode value must be represented
4803 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4804 the value into the high half of the general register. */
4805 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4806 return gen_rtx_PARALLEL (mode,
4807 gen_rtvec (1,
4808 gen_rtx_EXPR_LIST (VOIDmode,
4809 gen_rtx_REG (DImode, basereg + cum->words + offset),
4810 const0_rtx)));
4811 else
4812 return gen_rtx_REG (mode, basereg + cum->words + offset);
4813 }
4814 /* If there is no prototype, then FP values go in both FR and GR
4815 registers. */
4816 else
4817 {
4818 /* See comment above. */
4819 enum machine_mode inner_mode =
4820 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4821
4822 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4823 gen_rtx_REG (mode, (FR_ARG_FIRST
4824 + cum->fp_regs)),
4825 const0_rtx);
4826 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4827 gen_rtx_REG (inner_mode,
4828 (basereg + cum->words
4829 + offset)),
4830 const0_rtx);
4831
4832 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4833 }
4834 }
4835
4836 /* Implement TARGET_FUNCION_ARG target hook. */
4837
4838 static rtx
4839 ia64_function_arg (cumulative_args_t cum, enum machine_mode mode,
4840 const_tree type, bool named)
4841 {
4842 return ia64_function_arg_1 (cum, mode, type, named, false);
4843 }
4844
4845 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4846
4847 static rtx
4848 ia64_function_incoming_arg (cumulative_args_t cum,
4849 enum machine_mode mode,
4850 const_tree type, bool named)
4851 {
4852 return ia64_function_arg_1 (cum, mode, type, named, true);
4853 }
4854
4855 /* Return number of bytes, at the beginning of the argument, that must be
4856 put in registers. 0 is the argument is entirely in registers or entirely
4857 in memory. */
4858
4859 static int
4860 ia64_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
4861 tree type, bool named ATTRIBUTE_UNUSED)
4862 {
4863 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4864
4865 int words = ia64_function_arg_words (type, mode);
4866 int offset = ia64_function_arg_offset (cum, type, words);
4867
4868 /* If all argument slots are used, then it must go on the stack. */
4869 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4870 return 0;
4871
4872 /* It doesn't matter whether the argument goes in FR or GR regs. If
4873 it fits within the 8 argument slots, then it goes entirely in
4874 registers. If it extends past the last argument slot, then the rest
4875 goes on the stack. */
4876
4877 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4878 return 0;
4879
4880 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4881 }
4882
4883 /* Return ivms_arg_type based on machine_mode. */
4884
4885 static enum ivms_arg_type
4886 ia64_arg_type (enum machine_mode mode)
4887 {
4888 switch (mode)
4889 {
4890 case SFmode:
4891 return FS;
4892 case DFmode:
4893 return FT;
4894 default:
4895 return I64;
4896 }
4897 }
4898
4899 /* Update CUM to point after this argument. This is patterned after
4900 ia64_function_arg. */
4901
4902 static void
4903 ia64_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4904 const_tree type, bool named)
4905 {
4906 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4907 int words = ia64_function_arg_words (type, mode);
4908 int offset = ia64_function_arg_offset (cum, type, words);
4909 enum machine_mode hfa_mode = VOIDmode;
4910
4911 /* If all arg slots are already full, then there is nothing to do. */
4912 if (cum->words >= MAX_ARGUMENT_SLOTS)
4913 {
4914 cum->words += words + offset;
4915 return;
4916 }
4917
4918 cum->atypes[cum->words] = ia64_arg_type (mode);
4919 cum->words += words + offset;
4920
4921 /* On OpenVMS argument is either in Rn or Fn. */
4922 if (TARGET_ABI_OPEN_VMS)
4923 {
4924 cum->int_regs = cum->words;
4925 cum->fp_regs = cum->words;
4926 return;
4927 }
4928
4929 /* Check for and handle homogeneous FP aggregates. */
4930 if (type)
4931 hfa_mode = hfa_element_mode (type, 0);
4932
4933 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4934 and unprototyped hfas are passed specially. */
4935 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4936 {
4937 int fp_regs = cum->fp_regs;
4938 /* This is the original value of cum->words + offset. */
4939 int int_regs = cum->words - words;
4940 int hfa_size = GET_MODE_SIZE (hfa_mode);
4941 int byte_size;
4942 int args_byte_size;
4943
4944 /* If prototyped, pass it in FR regs then GR regs.
4945 If not prototyped, pass it in both FR and GR regs.
4946
4947 If this is an SFmode aggregate, then it is possible to run out of
4948 FR regs while GR regs are still left. In that case, we pass the
4949 remaining part in the GR regs. */
4950
4951 /* Fill the FP regs. We do this always. We stop if we reach the end
4952 of the argument, the last FP register, or the last argument slot. */
4953
4954 byte_size = ((mode == BLKmode)
4955 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4956 args_byte_size = int_regs * UNITS_PER_WORD;
4957 offset = 0;
4958 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4959 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4960 {
4961 offset += hfa_size;
4962 args_byte_size += hfa_size;
4963 fp_regs++;
4964 }
4965
4966 cum->fp_regs = fp_regs;
4967 }
4968
4969 /* Integral and aggregates go in general registers. So do TFmode FP values.
4970 If we have run out of FR registers, then other FP values must also go in
4971 general registers. This can happen when we have a SFmode HFA. */
4972 else if (mode == TFmode || mode == TCmode
4973 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4974 cum->int_regs = cum->words;
4975
4976 /* If there is a prototype, then FP values go in a FR register when
4977 named, and in a GR register when unnamed. */
4978 else if (cum->prototype)
4979 {
4980 if (! named)
4981 cum->int_regs = cum->words;
4982 else
4983 /* ??? Complex types should not reach here. */
4984 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4985 }
4986 /* If there is no prototype, then FP values go in both FR and GR
4987 registers. */
4988 else
4989 {
4990 /* ??? Complex types should not reach here. */
4991 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4992 cum->int_regs = cum->words;
4993 }
4994 }
4995
4996 /* Arguments with alignment larger than 8 bytes start at the next even
4997 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4998 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4999
5000 static unsigned int
5001 ia64_function_arg_boundary (enum machine_mode mode, const_tree type)
5002 {
5003 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
5004 return PARM_BOUNDARY * 2;
5005
5006 if (type)
5007 {
5008 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
5009 return PARM_BOUNDARY * 2;
5010 else
5011 return PARM_BOUNDARY;
5012 }
5013
5014 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
5015 return PARM_BOUNDARY * 2;
5016 else
5017 return PARM_BOUNDARY;
5018 }
5019
5020 /* True if it is OK to do sibling call optimization for the specified
5021 call expression EXP. DECL will be the called function, or NULL if
5022 this is an indirect call. */
5023 static bool
5024 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5025 {
5026 /* We can't perform a sibcall if the current function has the syscall_linkage
5027 attribute. */
5028 if (lookup_attribute ("syscall_linkage",
5029 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
5030 return false;
5031
5032 /* We must always return with our current GP. This means we can
5033 only sibcall to functions defined in the current module unless
5034 TARGET_CONST_GP is set to true. */
5035 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
5036 }
5037 \f
5038
5039 /* Implement va_arg. */
5040
5041 static tree
5042 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
5043 gimple_seq *post_p)
5044 {
5045 /* Variable sized types are passed by reference. */
5046 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5047 {
5048 tree ptrtype = build_pointer_type (type);
5049 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
5050 return build_va_arg_indirect_ref (addr);
5051 }
5052
5053 /* Aggregate arguments with alignment larger than 8 bytes start at
5054 the next even boundary. Integer and floating point arguments
5055 do so if they are larger than 8 bytes, whether or not they are
5056 also aligned larger than 8 bytes. */
5057 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
5058 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
5059 {
5060 tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1);
5061 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5062 build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD));
5063 gimplify_assign (unshare_expr (valist), t, pre_p);
5064 }
5065
5066 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5067 }
5068 \f
5069 /* Return 1 if function return value returned in memory. Return 0 if it is
5070 in a register. */
5071
5072 static bool
5073 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
5074 {
5075 enum machine_mode mode;
5076 enum machine_mode hfa_mode;
5077 HOST_WIDE_INT byte_size;
5078
5079 mode = TYPE_MODE (valtype);
5080 byte_size = GET_MODE_SIZE (mode);
5081 if (mode == BLKmode)
5082 {
5083 byte_size = int_size_in_bytes (valtype);
5084 if (byte_size < 0)
5085 return true;
5086 }
5087
5088 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
5089
5090 hfa_mode = hfa_element_mode (valtype, 0);
5091 if (hfa_mode != VOIDmode)
5092 {
5093 int hfa_size = GET_MODE_SIZE (hfa_mode);
5094
5095 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
5096 return true;
5097 else
5098 return false;
5099 }
5100 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
5101 return true;
5102 else
5103 return false;
5104 }
5105
5106 /* Return rtx for register that holds the function return value. */
5107
5108 static rtx
5109 ia64_function_value (const_tree valtype,
5110 const_tree fn_decl_or_type,
5111 bool outgoing ATTRIBUTE_UNUSED)
5112 {
5113 enum machine_mode mode;
5114 enum machine_mode hfa_mode;
5115 int unsignedp;
5116 const_tree func = fn_decl_or_type;
5117
5118 if (fn_decl_or_type
5119 && !DECL_P (fn_decl_or_type))
5120 func = NULL;
5121
5122 mode = TYPE_MODE (valtype);
5123 hfa_mode = hfa_element_mode (valtype, 0);
5124
5125 if (hfa_mode != VOIDmode)
5126 {
5127 rtx loc[8];
5128 int i;
5129 int hfa_size;
5130 int byte_size;
5131 int offset;
5132
5133 hfa_size = GET_MODE_SIZE (hfa_mode);
5134 byte_size = ((mode == BLKmode)
5135 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
5136 offset = 0;
5137 for (i = 0; offset < byte_size; i++)
5138 {
5139 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
5140 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
5141 GEN_INT (offset));
5142 offset += hfa_size;
5143 }
5144 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
5145 }
5146 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
5147 return gen_rtx_REG (mode, FR_ARG_FIRST);
5148 else
5149 {
5150 bool need_parallel = false;
5151
5152 /* In big-endian mode, we need to manage the layout of aggregates
5153 in the registers so that we get the bits properly aligned in
5154 the highpart of the registers. */
5155 if (BYTES_BIG_ENDIAN
5156 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
5157 need_parallel = true;
5158
5159 /* Something like struct S { long double x; char a[0] } is not an
5160 HFA structure, and therefore doesn't go in fp registers. But
5161 the middle-end will give it XFmode anyway, and XFmode values
5162 don't normally fit in integer registers. So we need to smuggle
5163 the value inside a parallel. */
5164 else if (mode == XFmode || mode == XCmode || mode == RFmode)
5165 need_parallel = true;
5166
5167 if (need_parallel)
5168 {
5169 rtx loc[8];
5170 int offset;
5171 int bytesize;
5172 int i;
5173
5174 offset = 0;
5175 bytesize = int_size_in_bytes (valtype);
5176 /* An empty PARALLEL is invalid here, but the return value
5177 doesn't matter for empty structs. */
5178 if (bytesize == 0)
5179 return gen_rtx_REG (mode, GR_RET_FIRST);
5180 for (i = 0; offset < bytesize; i++)
5181 {
5182 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
5183 gen_rtx_REG (DImode,
5184 GR_RET_FIRST + i),
5185 GEN_INT (offset));
5186 offset += UNITS_PER_WORD;
5187 }
5188 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
5189 }
5190
5191 mode = promote_function_mode (valtype, mode, &unsignedp,
5192 func ? TREE_TYPE (func) : NULL_TREE,
5193 true);
5194
5195 return gen_rtx_REG (mode, GR_RET_FIRST);
5196 }
5197 }
5198
5199 /* Worker function for TARGET_LIBCALL_VALUE. */
5200
5201 static rtx
5202 ia64_libcall_value (enum machine_mode mode,
5203 const_rtx fun ATTRIBUTE_UNUSED)
5204 {
5205 return gen_rtx_REG (mode,
5206 (((GET_MODE_CLASS (mode) == MODE_FLOAT
5207 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5208 && (mode) != TFmode)
5209 ? FR_RET_FIRST : GR_RET_FIRST));
5210 }
5211
5212 /* Worker function for FUNCTION_VALUE_REGNO_P. */
5213
5214 static bool
5215 ia64_function_value_regno_p (const unsigned int regno)
5216 {
5217 return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST)
5218 || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST));
5219 }
5220
5221 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5222 We need to emit DTP-relative relocations. */
5223
5224 static void
5225 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
5226 {
5227 gcc_assert (size == 4 || size == 8);
5228 if (size == 4)
5229 fputs ("\tdata4.ua\t@dtprel(", file);
5230 else
5231 fputs ("\tdata8.ua\t@dtprel(", file);
5232 output_addr_const (file, x);
5233 fputs (")", file);
5234 }
5235
5236 /* Print a memory address as an operand to reference that memory location. */
5237
5238 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
5239 also call this from ia64_print_operand for memory addresses. */
5240
5241 static void
5242 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
5243 rtx address ATTRIBUTE_UNUSED)
5244 {
5245 }
5246
5247 /* Print an operand to an assembler instruction.
5248 C Swap and print a comparison operator.
5249 D Print an FP comparison operator.
5250 E Print 32 - constant, for SImode shifts as extract.
5251 e Print 64 - constant, for DImode rotates.
5252 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
5253 a floating point register emitted normally.
5254 G A floating point constant.
5255 I Invert a predicate register by adding 1.
5256 J Select the proper predicate register for a condition.
5257 j Select the inverse predicate register for a condition.
5258 O Append .acq for volatile load.
5259 P Postincrement of a MEM.
5260 Q Append .rel for volatile store.
5261 R Print .s .d or nothing for a single, double or no truncation.
5262 S Shift amount for shladd instruction.
5263 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
5264 for Intel assembler.
5265 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
5266 for Intel assembler.
5267 X A pair of floating point registers.
5268 r Print register name, or constant 0 as r0. HP compatibility for
5269 Linux kernel.
5270 v Print vector constant value as an 8-byte integer value. */
5271
5272 static void
5273 ia64_print_operand (FILE * file, rtx x, int code)
5274 {
5275 const char *str;
5276
5277 switch (code)
5278 {
5279 case 0:
5280 /* Handled below. */
5281 break;
5282
5283 case 'C':
5284 {
5285 enum rtx_code c = swap_condition (GET_CODE (x));
5286 fputs (GET_RTX_NAME (c), file);
5287 return;
5288 }
5289
5290 case 'D':
5291 switch (GET_CODE (x))
5292 {
5293 case NE:
5294 str = "neq";
5295 break;
5296 case UNORDERED:
5297 str = "unord";
5298 break;
5299 case ORDERED:
5300 str = "ord";
5301 break;
5302 case UNLT:
5303 str = "nge";
5304 break;
5305 case UNLE:
5306 str = "ngt";
5307 break;
5308 case UNGT:
5309 str = "nle";
5310 break;
5311 case UNGE:
5312 str = "nlt";
5313 break;
5314 case UNEQ:
5315 case LTGT:
5316 gcc_unreachable ();
5317 default:
5318 str = GET_RTX_NAME (GET_CODE (x));
5319 break;
5320 }
5321 fputs (str, file);
5322 return;
5323
5324 case 'E':
5325 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
5326 return;
5327
5328 case 'e':
5329 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
5330 return;
5331
5332 case 'F':
5333 if (x == CONST0_RTX (GET_MODE (x)))
5334 str = reg_names [FR_REG (0)];
5335 else if (x == CONST1_RTX (GET_MODE (x)))
5336 str = reg_names [FR_REG (1)];
5337 else
5338 {
5339 gcc_assert (GET_CODE (x) == REG);
5340 str = reg_names [REGNO (x)];
5341 }
5342 fputs (str, file);
5343 return;
5344
5345 case 'G':
5346 {
5347 long val[4];
5348 REAL_VALUE_TYPE rv;
5349 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
5350 real_to_target (val, &rv, GET_MODE (x));
5351 if (GET_MODE (x) == SFmode)
5352 fprintf (file, "0x%08lx", val[0] & 0xffffffff);
5353 else if (GET_MODE (x) == DFmode)
5354 fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
5355 & 0xffffffff,
5356 (WORDS_BIG_ENDIAN ? val[1] : val[0])
5357 & 0xffffffff);
5358 else
5359 output_operand_lossage ("invalid %%G mode");
5360 }
5361 return;
5362
5363 case 'I':
5364 fputs (reg_names [REGNO (x) + 1], file);
5365 return;
5366
5367 case 'J':
5368 case 'j':
5369 {
5370 unsigned int regno = REGNO (XEXP (x, 0));
5371 if (GET_CODE (x) == EQ)
5372 regno += 1;
5373 if (code == 'j')
5374 regno ^= 1;
5375 fputs (reg_names [regno], file);
5376 }
5377 return;
5378
5379 case 'O':
5380 if (MEM_VOLATILE_P (x))
5381 fputs(".acq", file);
5382 return;
5383
5384 case 'P':
5385 {
5386 HOST_WIDE_INT value;
5387
5388 switch (GET_CODE (XEXP (x, 0)))
5389 {
5390 default:
5391 return;
5392
5393 case POST_MODIFY:
5394 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
5395 if (GET_CODE (x) == CONST_INT)
5396 value = INTVAL (x);
5397 else
5398 {
5399 gcc_assert (GET_CODE (x) == REG);
5400 fprintf (file, ", %s", reg_names[REGNO (x)]);
5401 return;
5402 }
5403 break;
5404
5405 case POST_INC:
5406 value = GET_MODE_SIZE (GET_MODE (x));
5407 break;
5408
5409 case POST_DEC:
5410 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
5411 break;
5412 }
5413
5414 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
5415 return;
5416 }
5417
5418 case 'Q':
5419 if (MEM_VOLATILE_P (x))
5420 fputs(".rel", file);
5421 return;
5422
5423 case 'R':
5424 if (x == CONST0_RTX (GET_MODE (x)))
5425 fputs(".s", file);
5426 else if (x == CONST1_RTX (GET_MODE (x)))
5427 fputs(".d", file);
5428 else if (x == CONST2_RTX (GET_MODE (x)))
5429 ;
5430 else
5431 output_operand_lossage ("invalid %%R value");
5432 return;
5433
5434 case 'S':
5435 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5436 return;
5437
5438 case 'T':
5439 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5440 {
5441 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
5442 return;
5443 }
5444 break;
5445
5446 case 'U':
5447 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5448 {
5449 const char *prefix = "0x";
5450 if (INTVAL (x) & 0x80000000)
5451 {
5452 fprintf (file, "0xffffffff");
5453 prefix = "";
5454 }
5455 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
5456 return;
5457 }
5458 break;
5459
5460 case 'X':
5461 {
5462 unsigned int regno = REGNO (x);
5463 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
5464 }
5465 return;
5466
5467 case 'r':
5468 /* If this operand is the constant zero, write it as register zero.
5469 Any register, zero, or CONST_INT value is OK here. */
5470 if (GET_CODE (x) == REG)
5471 fputs (reg_names[REGNO (x)], file);
5472 else if (x == CONST0_RTX (GET_MODE (x)))
5473 fputs ("r0", file);
5474 else if (GET_CODE (x) == CONST_INT)
5475 output_addr_const (file, x);
5476 else
5477 output_operand_lossage ("invalid %%r value");
5478 return;
5479
5480 case 'v':
5481 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5482 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5483 break;
5484
5485 case '+':
5486 {
5487 const char *which;
5488
5489 /* For conditional branches, returns or calls, substitute
5490 sptk, dptk, dpnt, or spnt for %s. */
5491 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
5492 if (x)
5493 {
5494 int pred_val = XINT (x, 0);
5495
5496 /* Guess top and bottom 10% statically predicted. */
5497 if (pred_val < REG_BR_PROB_BASE / 50
5498 && br_prob_note_reliable_p (x))
5499 which = ".spnt";
5500 else if (pred_val < REG_BR_PROB_BASE / 2)
5501 which = ".dpnt";
5502 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
5503 || !br_prob_note_reliable_p (x))
5504 which = ".dptk";
5505 else
5506 which = ".sptk";
5507 }
5508 else if (CALL_P (current_output_insn))
5509 which = ".sptk";
5510 else
5511 which = ".dptk";
5512
5513 fputs (which, file);
5514 return;
5515 }
5516
5517 case ',':
5518 x = current_insn_predicate;
5519 if (x)
5520 {
5521 unsigned int regno = REGNO (XEXP (x, 0));
5522 if (GET_CODE (x) == EQ)
5523 regno += 1;
5524 fprintf (file, "(%s) ", reg_names [regno]);
5525 }
5526 return;
5527
5528 default:
5529 output_operand_lossage ("ia64_print_operand: unknown code");
5530 return;
5531 }
5532
5533 switch (GET_CODE (x))
5534 {
5535 /* This happens for the spill/restore instructions. */
5536 case POST_INC:
5537 case POST_DEC:
5538 case POST_MODIFY:
5539 x = XEXP (x, 0);
5540 /* ... fall through ... */
5541
5542 case REG:
5543 fputs (reg_names [REGNO (x)], file);
5544 break;
5545
5546 case MEM:
5547 {
5548 rtx addr = XEXP (x, 0);
5549 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
5550 addr = XEXP (addr, 0);
5551 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
5552 break;
5553 }
5554
5555 default:
5556 output_addr_const (file, x);
5557 break;
5558 }
5559
5560 return;
5561 }
5562
5563 /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
5564
5565 static bool
5566 ia64_print_operand_punct_valid_p (unsigned char code)
5567 {
5568 return (code == '+' || code == ',');
5569 }
5570 \f
5571 /* Compute a (partial) cost for rtx X. Return true if the complete
5572 cost has been computed, and false if subexpressions should be
5573 scanned. In either case, *TOTAL contains the cost result. */
5574 /* ??? This is incomplete. */
5575
5576 static bool
5577 ia64_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
5578 int *total, bool speed ATTRIBUTE_UNUSED)
5579 {
5580 switch (code)
5581 {
5582 case CONST_INT:
5583 switch (outer_code)
5584 {
5585 case SET:
5586 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
5587 return true;
5588 case PLUS:
5589 if (satisfies_constraint_I (x))
5590 *total = 0;
5591 else if (satisfies_constraint_J (x))
5592 *total = 1;
5593 else
5594 *total = COSTS_N_INSNS (1);
5595 return true;
5596 default:
5597 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
5598 *total = 0;
5599 else
5600 *total = COSTS_N_INSNS (1);
5601 return true;
5602 }
5603
5604 case CONST_DOUBLE:
5605 *total = COSTS_N_INSNS (1);
5606 return true;
5607
5608 case CONST:
5609 case SYMBOL_REF:
5610 case LABEL_REF:
5611 *total = COSTS_N_INSNS (3);
5612 return true;
5613
5614 case FMA:
5615 *total = COSTS_N_INSNS (4);
5616 return true;
5617
5618 case MULT:
5619 /* For multiplies wider than HImode, we have to go to the FPU,
5620 which normally involves copies. Plus there's the latency
5621 of the multiply itself, and the latency of the instructions to
5622 transfer integer regs to FP regs. */
5623 if (FLOAT_MODE_P (GET_MODE (x)))
5624 *total = COSTS_N_INSNS (4);
5625 else if (GET_MODE_SIZE (GET_MODE (x)) > 2)
5626 *total = COSTS_N_INSNS (10);
5627 else
5628 *total = COSTS_N_INSNS (2);
5629 return true;
5630
5631 case PLUS:
5632 case MINUS:
5633 if (FLOAT_MODE_P (GET_MODE (x)))
5634 {
5635 *total = COSTS_N_INSNS (4);
5636 return true;
5637 }
5638 /* FALLTHRU */
5639
5640 case ASHIFT:
5641 case ASHIFTRT:
5642 case LSHIFTRT:
5643 *total = COSTS_N_INSNS (1);
5644 return true;
5645
5646 case DIV:
5647 case UDIV:
5648 case MOD:
5649 case UMOD:
5650 /* We make divide expensive, so that divide-by-constant will be
5651 optimized to a multiply. */
5652 *total = COSTS_N_INSNS (60);
5653 return true;
5654
5655 default:
5656 return false;
5657 }
5658 }
5659
5660 /* Calculate the cost of moving data from a register in class FROM to
5661 one in class TO, using MODE. */
5662
5663 static int
5664 ia64_register_move_cost (enum machine_mode mode, reg_class_t from,
5665 reg_class_t to)
5666 {
5667 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5668 if (to == ADDL_REGS)
5669 to = GR_REGS;
5670 if (from == ADDL_REGS)
5671 from = GR_REGS;
5672
5673 /* All costs are symmetric, so reduce cases by putting the
5674 lower number class as the destination. */
5675 if (from < to)
5676 {
5677 reg_class_t tmp = to;
5678 to = from, from = tmp;
5679 }
5680
5681 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5682 so that we get secondary memory reloads. Between FR_REGS,
5683 we have to make this at least as expensive as memory_move_cost
5684 to avoid spectacularly poor register class preferencing. */
5685 if (mode == XFmode || mode == RFmode)
5686 {
5687 if (to != GR_REGS || from != GR_REGS)
5688 return memory_move_cost (mode, to, false);
5689 else
5690 return 3;
5691 }
5692
5693 switch (to)
5694 {
5695 case PR_REGS:
5696 /* Moving between PR registers takes two insns. */
5697 if (from == PR_REGS)
5698 return 3;
5699 /* Moving between PR and anything but GR is impossible. */
5700 if (from != GR_REGS)
5701 return memory_move_cost (mode, to, false);
5702 break;
5703
5704 case BR_REGS:
5705 /* Moving between BR and anything but GR is impossible. */
5706 if (from != GR_REGS && from != GR_AND_BR_REGS)
5707 return memory_move_cost (mode, to, false);
5708 break;
5709
5710 case AR_I_REGS:
5711 case AR_M_REGS:
5712 /* Moving between AR and anything but GR is impossible. */
5713 if (from != GR_REGS)
5714 return memory_move_cost (mode, to, false);
5715 break;
5716
5717 case GR_REGS:
5718 case FR_REGS:
5719 case FP_REGS:
5720 case GR_AND_FR_REGS:
5721 case GR_AND_BR_REGS:
5722 case ALL_REGS:
5723 break;
5724
5725 default:
5726 gcc_unreachable ();
5727 }
5728
5729 return 2;
5730 }
5731
5732 /* Calculate the cost of moving data of MODE from a register to or from
5733 memory. */
5734
5735 static int
5736 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
5737 reg_class_t rclass,
5738 bool in ATTRIBUTE_UNUSED)
5739 {
5740 if (rclass == GENERAL_REGS
5741 || rclass == FR_REGS
5742 || rclass == FP_REGS
5743 || rclass == GR_AND_FR_REGS)
5744 return 4;
5745 else
5746 return 10;
5747 }
5748
5749 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5750 on RCLASS to use when copying X into that class. */
5751
5752 static reg_class_t
5753 ia64_preferred_reload_class (rtx x, reg_class_t rclass)
5754 {
5755 switch (rclass)
5756 {
5757 case FR_REGS:
5758 case FP_REGS:
5759 /* Don't allow volatile mem reloads into floating point registers.
5760 This is defined to force reload to choose the r/m case instead
5761 of the f/f case when reloading (set (reg fX) (mem/v)). */
5762 if (MEM_P (x) && MEM_VOLATILE_P (x))
5763 return NO_REGS;
5764
5765 /* Force all unrecognized constants into the constant pool. */
5766 if (CONSTANT_P (x))
5767 return NO_REGS;
5768 break;
5769
5770 case AR_M_REGS:
5771 case AR_I_REGS:
5772 if (!OBJECT_P (x))
5773 return NO_REGS;
5774 break;
5775
5776 default:
5777 break;
5778 }
5779
5780 return rclass;
5781 }
5782
5783 /* This function returns the register class required for a secondary
5784 register when copying between one of the registers in RCLASS, and X,
5785 using MODE. A return value of NO_REGS means that no secondary register
5786 is required. */
5787
5788 enum reg_class
5789 ia64_secondary_reload_class (enum reg_class rclass,
5790 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5791 {
5792 int regno = -1;
5793
5794 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5795 regno = true_regnum (x);
5796
5797 switch (rclass)
5798 {
5799 case BR_REGS:
5800 case AR_M_REGS:
5801 case AR_I_REGS:
5802 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5803 interaction. We end up with two pseudos with overlapping lifetimes
5804 both of which are equiv to the same constant, and both which need
5805 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5806 changes depending on the path length, which means the qty_first_reg
5807 check in make_regs_eqv can give different answers at different times.
5808 At some point I'll probably need a reload_indi pattern to handle
5809 this.
5810
5811 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5812 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5813 non-general registers for good measure. */
5814 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5815 return GR_REGS;
5816
5817 /* This is needed if a pseudo used as a call_operand gets spilled to a
5818 stack slot. */
5819 if (GET_CODE (x) == MEM)
5820 return GR_REGS;
5821 break;
5822
5823 case FR_REGS:
5824 case FP_REGS:
5825 /* Need to go through general registers to get to other class regs. */
5826 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5827 return GR_REGS;
5828
5829 /* This can happen when a paradoxical subreg is an operand to the
5830 muldi3 pattern. */
5831 /* ??? This shouldn't be necessary after instruction scheduling is
5832 enabled, because paradoxical subregs are not accepted by
5833 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5834 stop the paradoxical subreg stupidity in the *_operand functions
5835 in recog.c. */
5836 if (GET_CODE (x) == MEM
5837 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5838 || GET_MODE (x) == QImode))
5839 return GR_REGS;
5840
5841 /* This can happen because of the ior/and/etc patterns that accept FP
5842 registers as operands. If the third operand is a constant, then it
5843 needs to be reloaded into a FP register. */
5844 if (GET_CODE (x) == CONST_INT)
5845 return GR_REGS;
5846
5847 /* This can happen because of register elimination in a muldi3 insn.
5848 E.g. `26107 * (unsigned long)&u'. */
5849 if (GET_CODE (x) == PLUS)
5850 return GR_REGS;
5851 break;
5852
5853 case PR_REGS:
5854 /* ??? This happens if we cse/gcse a BImode value across a call,
5855 and the function has a nonlocal goto. This is because global
5856 does not allocate call crossing pseudos to hard registers when
5857 crtl->has_nonlocal_goto is true. This is relatively
5858 common for C++ programs that use exceptions. To reproduce,
5859 return NO_REGS and compile libstdc++. */
5860 if (GET_CODE (x) == MEM)
5861 return GR_REGS;
5862
5863 /* This can happen when we take a BImode subreg of a DImode value,
5864 and that DImode value winds up in some non-GR register. */
5865 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5866 return GR_REGS;
5867 break;
5868
5869 default:
5870 break;
5871 }
5872
5873 return NO_REGS;
5874 }
5875
5876 \f
5877 /* Implement targetm.unspec_may_trap_p hook. */
5878 static int
5879 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5880 {
5881 switch (XINT (x, 1))
5882 {
5883 case UNSPEC_LDA:
5884 case UNSPEC_LDS:
5885 case UNSPEC_LDSA:
5886 case UNSPEC_LDCCLR:
5887 case UNSPEC_CHKACLR:
5888 case UNSPEC_CHKS:
5889 /* These unspecs are just wrappers. */
5890 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5891 }
5892
5893 return default_unspec_may_trap_p (x, flags);
5894 }
5895
5896 \f
5897 /* Parse the -mfixed-range= option string. */
5898
5899 static void
5900 fix_range (const char *const_str)
5901 {
5902 int i, first, last;
5903 char *str, *dash, *comma;
5904
5905 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5906 REG2 are either register names or register numbers. The effect
5907 of this option is to mark the registers in the range from REG1 to
5908 REG2 as ``fixed'' so they won't be used by the compiler. This is
5909 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5910
5911 i = strlen (const_str);
5912 str = (char *) alloca (i + 1);
5913 memcpy (str, const_str, i + 1);
5914
5915 while (1)
5916 {
5917 dash = strchr (str, '-');
5918 if (!dash)
5919 {
5920 warning (0, "value of -mfixed-range must have form REG1-REG2");
5921 return;
5922 }
5923 *dash = '\0';
5924
5925 comma = strchr (dash + 1, ',');
5926 if (comma)
5927 *comma = '\0';
5928
5929 first = decode_reg_name (str);
5930 if (first < 0)
5931 {
5932 warning (0, "unknown register name: %s", str);
5933 return;
5934 }
5935
5936 last = decode_reg_name (dash + 1);
5937 if (last < 0)
5938 {
5939 warning (0, "unknown register name: %s", dash + 1);
5940 return;
5941 }
5942
5943 *dash = '-';
5944
5945 if (first > last)
5946 {
5947 warning (0, "%s-%s is an empty range", str, dash + 1);
5948 return;
5949 }
5950
5951 for (i = first; i <= last; ++i)
5952 fixed_regs[i] = call_used_regs[i] = 1;
5953
5954 if (!comma)
5955 break;
5956
5957 *comma = ',';
5958 str = comma + 1;
5959 }
5960 }
5961
5962 /* Implement TARGET_OPTION_OVERRIDE. */
5963
5964 static void
5965 ia64_option_override (void)
5966 {
5967 unsigned int i;
5968 cl_deferred_option *opt;
5969 vec<cl_deferred_option> *v
5970 = (vec<cl_deferred_option> *) ia64_deferred_options;
5971
5972 if (v)
5973 FOR_EACH_VEC_ELT (*v, i, opt)
5974 {
5975 switch (opt->opt_index)
5976 {
5977 case OPT_mfixed_range_:
5978 fix_range (opt->arg);
5979 break;
5980
5981 default:
5982 gcc_unreachable ();
5983 }
5984 }
5985
5986 if (TARGET_AUTO_PIC)
5987 target_flags |= MASK_CONST_GP;
5988
5989 /* Numerous experiment shows that IRA based loop pressure
5990 calculation works better for RTL loop invariant motion on targets
5991 with enough (>= 32) registers. It is an expensive optimization.
5992 So it is on only for peak performance. */
5993 if (optimize >= 3)
5994 flag_ira_loop_pressure = 1;
5995
5996
5997 ia64_section_threshold = (global_options_set.x_g_switch_value
5998 ? g_switch_value
5999 : IA64_DEFAULT_GVALUE);
6000
6001 init_machine_status = ia64_init_machine_status;
6002
6003 if (align_functions <= 0)
6004 align_functions = 64;
6005 if (align_loops <= 0)
6006 align_loops = 32;
6007 if (TARGET_ABI_OPEN_VMS)
6008 flag_no_common = 1;
6009
6010 ia64_override_options_after_change();
6011 }
6012
6013 /* Implement targetm.override_options_after_change. */
6014
6015 static void
6016 ia64_override_options_after_change (void)
6017 {
6018 if (optimize >= 3
6019 && !global_options_set.x_flag_selective_scheduling
6020 && !global_options_set.x_flag_selective_scheduling2)
6021 {
6022 flag_selective_scheduling2 = 1;
6023 flag_sel_sched_pipelining = 1;
6024 }
6025 if (mflag_sched_control_spec == 2)
6026 {
6027 /* Control speculation is on by default for the selective scheduler,
6028 but not for the Haifa scheduler. */
6029 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
6030 }
6031 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
6032 {
6033 /* FIXME: remove this when we'd implement breaking autoinsns as
6034 a transformation. */
6035 flag_auto_inc_dec = 0;
6036 }
6037 }
6038
6039 /* Initialize the record of emitted frame related registers. */
6040
6041 void ia64_init_expanders (void)
6042 {
6043 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
6044 }
6045
6046 static struct machine_function *
6047 ia64_init_machine_status (void)
6048 {
6049 return ggc_alloc_cleared_machine_function ();
6050 }
6051 \f
6052 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
6053 static enum attr_type ia64_safe_type (rtx);
6054
6055 static enum attr_itanium_class
6056 ia64_safe_itanium_class (rtx insn)
6057 {
6058 if (recog_memoized (insn) >= 0)
6059 return get_attr_itanium_class (insn);
6060 else if (DEBUG_INSN_P (insn))
6061 return ITANIUM_CLASS_IGNORE;
6062 else
6063 return ITANIUM_CLASS_UNKNOWN;
6064 }
6065
6066 static enum attr_type
6067 ia64_safe_type (rtx insn)
6068 {
6069 if (recog_memoized (insn) >= 0)
6070 return get_attr_type (insn);
6071 else
6072 return TYPE_UNKNOWN;
6073 }
6074 \f
6075 /* The following collection of routines emit instruction group stop bits as
6076 necessary to avoid dependencies. */
6077
6078 /* Need to track some additional registers as far as serialization is
6079 concerned so we can properly handle br.call and br.ret. We could
6080 make these registers visible to gcc, but since these registers are
6081 never explicitly used in gcc generated code, it seems wasteful to
6082 do so (plus it would make the call and return patterns needlessly
6083 complex). */
6084 #define REG_RP (BR_REG (0))
6085 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
6086 /* This is used for volatile asms which may require a stop bit immediately
6087 before and after them. */
6088 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
6089 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
6090 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
6091
6092 /* For each register, we keep track of how it has been written in the
6093 current instruction group.
6094
6095 If a register is written unconditionally (no qualifying predicate),
6096 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
6097
6098 If a register is written if its qualifying predicate P is true, we
6099 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
6100 may be written again by the complement of P (P^1) and when this happens,
6101 WRITE_COUNT gets set to 2.
6102
6103 The result of this is that whenever an insn attempts to write a register
6104 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
6105
6106 If a predicate register is written by a floating-point insn, we set
6107 WRITTEN_BY_FP to true.
6108
6109 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
6110 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
6111
6112 #if GCC_VERSION >= 4000
6113 #define RWS_FIELD_TYPE __extension__ unsigned short
6114 #else
6115 #define RWS_FIELD_TYPE unsigned int
6116 #endif
6117 struct reg_write_state
6118 {
6119 RWS_FIELD_TYPE write_count : 2;
6120 RWS_FIELD_TYPE first_pred : 10;
6121 RWS_FIELD_TYPE written_by_fp : 1;
6122 RWS_FIELD_TYPE written_by_and : 1;
6123 RWS_FIELD_TYPE written_by_or : 1;
6124 };
6125
6126 /* Cumulative info for the current instruction group. */
6127 struct reg_write_state rws_sum[NUM_REGS];
6128 #ifdef ENABLE_CHECKING
6129 /* Bitmap whether a register has been written in the current insn. */
6130 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
6131 / HOST_BITS_PER_WIDEST_FAST_INT];
6132
6133 static inline void
6134 rws_insn_set (int regno)
6135 {
6136 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
6137 SET_HARD_REG_BIT (rws_insn, regno);
6138 }
6139
6140 static inline int
6141 rws_insn_test (int regno)
6142 {
6143 return TEST_HARD_REG_BIT (rws_insn, regno);
6144 }
6145 #else
6146 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
6147 unsigned char rws_insn[2];
6148
6149 static inline void
6150 rws_insn_set (int regno)
6151 {
6152 if (regno == REG_AR_CFM)
6153 rws_insn[0] = 1;
6154 else if (regno == REG_VOLATILE)
6155 rws_insn[1] = 1;
6156 }
6157
6158 static inline int
6159 rws_insn_test (int regno)
6160 {
6161 if (regno == REG_AR_CFM)
6162 return rws_insn[0];
6163 if (regno == REG_VOLATILE)
6164 return rws_insn[1];
6165 return 0;
6166 }
6167 #endif
6168
6169 /* Indicates whether this is the first instruction after a stop bit,
6170 in which case we don't need another stop bit. Without this,
6171 ia64_variable_issue will die when scheduling an alloc. */
6172 static int first_instruction;
6173
6174 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
6175 RTL for one instruction. */
6176 struct reg_flags
6177 {
6178 unsigned int is_write : 1; /* Is register being written? */
6179 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
6180 unsigned int is_branch : 1; /* Is register used as part of a branch? */
6181 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
6182 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
6183 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
6184 };
6185
6186 static void rws_update (int, struct reg_flags, int);
6187 static int rws_access_regno (int, struct reg_flags, int);
6188 static int rws_access_reg (rtx, struct reg_flags, int);
6189 static void update_set_flags (rtx, struct reg_flags *);
6190 static int set_src_needs_barrier (rtx, struct reg_flags, int);
6191 static int rtx_needs_barrier (rtx, struct reg_flags, int);
6192 static void init_insn_group_barriers (void);
6193 static int group_barrier_needed (rtx);
6194 static int safe_group_barrier_needed (rtx);
6195 static int in_safe_group_barrier;
6196
6197 /* Update *RWS for REGNO, which is being written by the current instruction,
6198 with predicate PRED, and associated register flags in FLAGS. */
6199
6200 static void
6201 rws_update (int regno, struct reg_flags flags, int pred)
6202 {
6203 if (pred)
6204 rws_sum[regno].write_count++;
6205 else
6206 rws_sum[regno].write_count = 2;
6207 rws_sum[regno].written_by_fp |= flags.is_fp;
6208 /* ??? Not tracking and/or across differing predicates. */
6209 rws_sum[regno].written_by_and = flags.is_and;
6210 rws_sum[regno].written_by_or = flags.is_or;
6211 rws_sum[regno].first_pred = pred;
6212 }
6213
6214 /* Handle an access to register REGNO of type FLAGS using predicate register
6215 PRED. Update rws_sum array. Return 1 if this access creates
6216 a dependency with an earlier instruction in the same group. */
6217
6218 static int
6219 rws_access_regno (int regno, struct reg_flags flags, int pred)
6220 {
6221 int need_barrier = 0;
6222
6223 gcc_assert (regno < NUM_REGS);
6224
6225 if (! PR_REGNO_P (regno))
6226 flags.is_and = flags.is_or = 0;
6227
6228 if (flags.is_write)
6229 {
6230 int write_count;
6231
6232 rws_insn_set (regno);
6233 write_count = rws_sum[regno].write_count;
6234
6235 switch (write_count)
6236 {
6237 case 0:
6238 /* The register has not been written yet. */
6239 if (!in_safe_group_barrier)
6240 rws_update (regno, flags, pred);
6241 break;
6242
6243 case 1:
6244 /* The register has been written via a predicate. Treat
6245 it like a unconditional write and do not try to check
6246 for complementary pred reg in earlier write. */
6247 if (flags.is_and && rws_sum[regno].written_by_and)
6248 ;
6249 else if (flags.is_or && rws_sum[regno].written_by_or)
6250 ;
6251 else
6252 need_barrier = 1;
6253 if (!in_safe_group_barrier)
6254 rws_update (regno, flags, pred);
6255 break;
6256
6257 case 2:
6258 /* The register has been unconditionally written already. We
6259 need a barrier. */
6260 if (flags.is_and && rws_sum[regno].written_by_and)
6261 ;
6262 else if (flags.is_or && rws_sum[regno].written_by_or)
6263 ;
6264 else
6265 need_barrier = 1;
6266 if (!in_safe_group_barrier)
6267 {
6268 rws_sum[regno].written_by_and = flags.is_and;
6269 rws_sum[regno].written_by_or = flags.is_or;
6270 }
6271 break;
6272
6273 default:
6274 gcc_unreachable ();
6275 }
6276 }
6277 else
6278 {
6279 if (flags.is_branch)
6280 {
6281 /* Branches have several RAW exceptions that allow to avoid
6282 barriers. */
6283
6284 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
6285 /* RAW dependencies on branch regs are permissible as long
6286 as the writer is a non-branch instruction. Since we
6287 never generate code that uses a branch register written
6288 by a branch instruction, handling this case is
6289 easy. */
6290 return 0;
6291
6292 if (REGNO_REG_CLASS (regno) == PR_REGS
6293 && ! rws_sum[regno].written_by_fp)
6294 /* The predicates of a branch are available within the
6295 same insn group as long as the predicate was written by
6296 something other than a floating-point instruction. */
6297 return 0;
6298 }
6299
6300 if (flags.is_and && rws_sum[regno].written_by_and)
6301 return 0;
6302 if (flags.is_or && rws_sum[regno].written_by_or)
6303 return 0;
6304
6305 switch (rws_sum[regno].write_count)
6306 {
6307 case 0:
6308 /* The register has not been written yet. */
6309 break;
6310
6311 case 1:
6312 /* The register has been written via a predicate, assume we
6313 need a barrier (don't check for complementary regs). */
6314 need_barrier = 1;
6315 break;
6316
6317 case 2:
6318 /* The register has been unconditionally written already. We
6319 need a barrier. */
6320 need_barrier = 1;
6321 break;
6322
6323 default:
6324 gcc_unreachable ();
6325 }
6326 }
6327
6328 return need_barrier;
6329 }
6330
6331 static int
6332 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
6333 {
6334 int regno = REGNO (reg);
6335 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
6336
6337 if (n == 1)
6338 return rws_access_regno (regno, flags, pred);
6339 else
6340 {
6341 int need_barrier = 0;
6342 while (--n >= 0)
6343 need_barrier |= rws_access_regno (regno + n, flags, pred);
6344 return need_barrier;
6345 }
6346 }
6347
6348 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6349 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6350
6351 static void
6352 update_set_flags (rtx x, struct reg_flags *pflags)
6353 {
6354 rtx src = SET_SRC (x);
6355
6356 switch (GET_CODE (src))
6357 {
6358 case CALL:
6359 return;
6360
6361 case IF_THEN_ELSE:
6362 /* There are four cases here:
6363 (1) The destination is (pc), in which case this is a branch,
6364 nothing here applies.
6365 (2) The destination is ar.lc, in which case this is a
6366 doloop_end_internal,
6367 (3) The destination is an fp register, in which case this is
6368 an fselect instruction.
6369 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6370 this is a check load.
6371 In all cases, nothing we do in this function applies. */
6372 return;
6373
6374 default:
6375 if (COMPARISON_P (src)
6376 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
6377 /* Set pflags->is_fp to 1 so that we know we're dealing
6378 with a floating point comparison when processing the
6379 destination of the SET. */
6380 pflags->is_fp = 1;
6381
6382 /* Discover if this is a parallel comparison. We only handle
6383 and.orcm and or.andcm at present, since we must retain a
6384 strict inverse on the predicate pair. */
6385 else if (GET_CODE (src) == AND)
6386 pflags->is_and = 1;
6387 else if (GET_CODE (src) == IOR)
6388 pflags->is_or = 1;
6389
6390 break;
6391 }
6392 }
6393
6394 /* Subroutine of rtx_needs_barrier; this function determines whether the
6395 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6396 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6397 for this insn. */
6398
6399 static int
6400 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
6401 {
6402 int need_barrier = 0;
6403 rtx dst;
6404 rtx src = SET_SRC (x);
6405
6406 if (GET_CODE (src) == CALL)
6407 /* We don't need to worry about the result registers that
6408 get written by subroutine call. */
6409 return rtx_needs_barrier (src, flags, pred);
6410 else if (SET_DEST (x) == pc_rtx)
6411 {
6412 /* X is a conditional branch. */
6413 /* ??? This seems redundant, as the caller sets this bit for
6414 all JUMP_INSNs. */
6415 if (!ia64_spec_check_src_p (src))
6416 flags.is_branch = 1;
6417 return rtx_needs_barrier (src, flags, pred);
6418 }
6419
6420 if (ia64_spec_check_src_p (src))
6421 /* Avoid checking one register twice (in condition
6422 and in 'then' section) for ldc pattern. */
6423 {
6424 gcc_assert (REG_P (XEXP (src, 2)));
6425 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
6426
6427 /* We process MEM below. */
6428 src = XEXP (src, 1);
6429 }
6430
6431 need_barrier |= rtx_needs_barrier (src, flags, pred);
6432
6433 dst = SET_DEST (x);
6434 if (GET_CODE (dst) == ZERO_EXTRACT)
6435 {
6436 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
6437 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
6438 }
6439 return need_barrier;
6440 }
6441
6442 /* Handle an access to rtx X of type FLAGS using predicate register
6443 PRED. Return 1 if this access creates a dependency with an earlier
6444 instruction in the same group. */
6445
6446 static int
6447 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
6448 {
6449 int i, j;
6450 int is_complemented = 0;
6451 int need_barrier = 0;
6452 const char *format_ptr;
6453 struct reg_flags new_flags;
6454 rtx cond;
6455
6456 if (! x)
6457 return 0;
6458
6459 new_flags = flags;
6460
6461 switch (GET_CODE (x))
6462 {
6463 case SET:
6464 update_set_flags (x, &new_flags);
6465 need_barrier = set_src_needs_barrier (x, new_flags, pred);
6466 if (GET_CODE (SET_SRC (x)) != CALL)
6467 {
6468 new_flags.is_write = 1;
6469 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
6470 }
6471 break;
6472
6473 case CALL:
6474 new_flags.is_write = 0;
6475 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6476
6477 /* Avoid multiple register writes, in case this is a pattern with
6478 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6479 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
6480 {
6481 new_flags.is_write = 1;
6482 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
6483 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
6484 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6485 }
6486 break;
6487
6488 case COND_EXEC:
6489 /* X is a predicated instruction. */
6490
6491 cond = COND_EXEC_TEST (x);
6492 gcc_assert (!pred);
6493 need_barrier = rtx_needs_barrier (cond, flags, 0);
6494
6495 if (GET_CODE (cond) == EQ)
6496 is_complemented = 1;
6497 cond = XEXP (cond, 0);
6498 gcc_assert (GET_CODE (cond) == REG
6499 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
6500 pred = REGNO (cond);
6501 if (is_complemented)
6502 ++pred;
6503
6504 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
6505 return need_barrier;
6506
6507 case CLOBBER:
6508 case USE:
6509 /* Clobber & use are for earlier compiler-phases only. */
6510 break;
6511
6512 case ASM_OPERANDS:
6513 case ASM_INPUT:
6514 /* We always emit stop bits for traditional asms. We emit stop bits
6515 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6516 if (GET_CODE (x) != ASM_OPERANDS
6517 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
6518 {
6519 /* Avoid writing the register multiple times if we have multiple
6520 asm outputs. This avoids a failure in rws_access_reg. */
6521 if (! rws_insn_test (REG_VOLATILE))
6522 {
6523 new_flags.is_write = 1;
6524 rws_access_regno (REG_VOLATILE, new_flags, pred);
6525 }
6526 return 1;
6527 }
6528
6529 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6530 We cannot just fall through here since then we would be confused
6531 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6532 traditional asms unlike their normal usage. */
6533
6534 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
6535 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
6536 need_barrier = 1;
6537 break;
6538
6539 case PARALLEL:
6540 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6541 {
6542 rtx pat = XVECEXP (x, 0, i);
6543 switch (GET_CODE (pat))
6544 {
6545 case SET:
6546 update_set_flags (pat, &new_flags);
6547 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
6548 break;
6549
6550 case USE:
6551 case CALL:
6552 case ASM_OPERANDS:
6553 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6554 break;
6555
6556 case CLOBBER:
6557 if (REG_P (XEXP (pat, 0))
6558 && extract_asm_operands (x) != NULL_RTX
6559 && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM)
6560 {
6561 new_flags.is_write = 1;
6562 need_barrier |= rtx_needs_barrier (XEXP (pat, 0),
6563 new_flags, pred);
6564 new_flags = flags;
6565 }
6566 break;
6567
6568 case RETURN:
6569 break;
6570
6571 default:
6572 gcc_unreachable ();
6573 }
6574 }
6575 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6576 {
6577 rtx pat = XVECEXP (x, 0, i);
6578 if (GET_CODE (pat) == SET)
6579 {
6580 if (GET_CODE (SET_SRC (pat)) != CALL)
6581 {
6582 new_flags.is_write = 1;
6583 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
6584 pred);
6585 }
6586 }
6587 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
6588 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6589 }
6590 break;
6591
6592 case SUBREG:
6593 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
6594 break;
6595 case REG:
6596 if (REGNO (x) == AR_UNAT_REGNUM)
6597 {
6598 for (i = 0; i < 64; ++i)
6599 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
6600 }
6601 else
6602 need_barrier = rws_access_reg (x, flags, pred);
6603 break;
6604
6605 case MEM:
6606 /* Find the regs used in memory address computation. */
6607 new_flags.is_write = 0;
6608 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6609 break;
6610
6611 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
6612 case SYMBOL_REF: case LABEL_REF: case CONST:
6613 break;
6614
6615 /* Operators with side-effects. */
6616 case POST_INC: case POST_DEC:
6617 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6618
6619 new_flags.is_write = 0;
6620 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6621 new_flags.is_write = 1;
6622 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6623 break;
6624
6625 case POST_MODIFY:
6626 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6627
6628 new_flags.is_write = 0;
6629 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6630 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6631 new_flags.is_write = 1;
6632 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6633 break;
6634
6635 /* Handle common unary and binary ops for efficiency. */
6636 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
6637 case MOD: case UDIV: case UMOD: case AND: case IOR:
6638 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
6639 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
6640 case NE: case EQ: case GE: case GT: case LE:
6641 case LT: case GEU: case GTU: case LEU: case LTU:
6642 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6643 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6644 break;
6645
6646 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
6647 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
6648 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
6649 case SQRT: case FFS: case POPCOUNT:
6650 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6651 break;
6652
6653 case VEC_SELECT:
6654 /* VEC_SELECT's second argument is a PARALLEL with integers that
6655 describe the elements selected. On ia64, those integers are
6656 always constants. Avoid walking the PARALLEL so that we don't
6657 get confused with "normal" parallels and then die. */
6658 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6659 break;
6660
6661 case UNSPEC:
6662 switch (XINT (x, 1))
6663 {
6664 case UNSPEC_LTOFF_DTPMOD:
6665 case UNSPEC_LTOFF_DTPREL:
6666 case UNSPEC_DTPREL:
6667 case UNSPEC_LTOFF_TPREL:
6668 case UNSPEC_TPREL:
6669 case UNSPEC_PRED_REL_MUTEX:
6670 case UNSPEC_PIC_CALL:
6671 case UNSPEC_MF:
6672 case UNSPEC_FETCHADD_ACQ:
6673 case UNSPEC_FETCHADD_REL:
6674 case UNSPEC_BSP_VALUE:
6675 case UNSPEC_FLUSHRS:
6676 case UNSPEC_BUNDLE_SELECTOR:
6677 break;
6678
6679 case UNSPEC_GR_SPILL:
6680 case UNSPEC_GR_RESTORE:
6681 {
6682 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
6683 HOST_WIDE_INT bit = (offset >> 3) & 63;
6684
6685 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6686 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
6687 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
6688 new_flags, pred);
6689 break;
6690 }
6691
6692 case UNSPEC_FR_SPILL:
6693 case UNSPEC_FR_RESTORE:
6694 case UNSPEC_GETF_EXP:
6695 case UNSPEC_SETF_EXP:
6696 case UNSPEC_ADDP4:
6697 case UNSPEC_FR_SQRT_RECIP_APPROX:
6698 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
6699 case UNSPEC_LDA:
6700 case UNSPEC_LDS:
6701 case UNSPEC_LDS_A:
6702 case UNSPEC_LDSA:
6703 case UNSPEC_CHKACLR:
6704 case UNSPEC_CHKS:
6705 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6706 break;
6707
6708 case UNSPEC_FR_RECIP_APPROX:
6709 case UNSPEC_SHRP:
6710 case UNSPEC_COPYSIGN:
6711 case UNSPEC_FR_RECIP_APPROX_RES:
6712 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6713 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6714 break;
6715
6716 case UNSPEC_CMPXCHG_ACQ:
6717 case UNSPEC_CMPXCHG_REL:
6718 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6719 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
6720 break;
6721
6722 default:
6723 gcc_unreachable ();
6724 }
6725 break;
6726
6727 case UNSPEC_VOLATILE:
6728 switch (XINT (x, 1))
6729 {
6730 case UNSPECV_ALLOC:
6731 /* Alloc must always be the first instruction of a group.
6732 We force this by always returning true. */
6733 /* ??? We might get better scheduling if we explicitly check for
6734 input/local/output register dependencies, and modify the
6735 scheduler so that alloc is always reordered to the start of
6736 the current group. We could then eliminate all of the
6737 first_instruction code. */
6738 rws_access_regno (AR_PFS_REGNUM, flags, pred);
6739
6740 new_flags.is_write = 1;
6741 rws_access_regno (REG_AR_CFM, new_flags, pred);
6742 return 1;
6743
6744 case UNSPECV_SET_BSP:
6745 case UNSPECV_PROBE_STACK_RANGE:
6746 need_barrier = 1;
6747 break;
6748
6749 case UNSPECV_BLOCKAGE:
6750 case UNSPECV_INSN_GROUP_BARRIER:
6751 case UNSPECV_BREAK:
6752 case UNSPECV_PSAC_ALL:
6753 case UNSPECV_PSAC_NORMAL:
6754 return 0;
6755
6756 case UNSPECV_PROBE_STACK_ADDRESS:
6757 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6758 break;
6759
6760 default:
6761 gcc_unreachable ();
6762 }
6763 break;
6764
6765 case RETURN:
6766 new_flags.is_write = 0;
6767 need_barrier = rws_access_regno (REG_RP, flags, pred);
6768 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6769
6770 new_flags.is_write = 1;
6771 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6772 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6773 break;
6774
6775 default:
6776 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6777 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6778 switch (format_ptr[i])
6779 {
6780 case '0': /* unused field */
6781 case 'i': /* integer */
6782 case 'n': /* note */
6783 case 'w': /* wide integer */
6784 case 's': /* pointer to string */
6785 case 'S': /* optional pointer to string */
6786 break;
6787
6788 case 'e':
6789 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6790 need_barrier = 1;
6791 break;
6792
6793 case 'E':
6794 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6795 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6796 need_barrier = 1;
6797 break;
6798
6799 default:
6800 gcc_unreachable ();
6801 }
6802 break;
6803 }
6804 return need_barrier;
6805 }
6806
6807 /* Clear out the state for group_barrier_needed at the start of a
6808 sequence of insns. */
6809
6810 static void
6811 init_insn_group_barriers (void)
6812 {
6813 memset (rws_sum, 0, sizeof (rws_sum));
6814 first_instruction = 1;
6815 }
6816
6817 /* Given the current state, determine whether a group barrier (a stop bit) is
6818 necessary before INSN. Return nonzero if so. This modifies the state to
6819 include the effects of INSN as a side-effect. */
6820
6821 static int
6822 group_barrier_needed (rtx insn)
6823 {
6824 rtx pat;
6825 int need_barrier = 0;
6826 struct reg_flags flags;
6827
6828 memset (&flags, 0, sizeof (flags));
6829 switch (GET_CODE (insn))
6830 {
6831 case NOTE:
6832 case DEBUG_INSN:
6833 break;
6834
6835 case BARRIER:
6836 /* A barrier doesn't imply an instruction group boundary. */
6837 break;
6838
6839 case CODE_LABEL:
6840 memset (rws_insn, 0, sizeof (rws_insn));
6841 return 1;
6842
6843 case CALL_INSN:
6844 flags.is_branch = 1;
6845 flags.is_sibcall = SIBLING_CALL_P (insn);
6846 memset (rws_insn, 0, sizeof (rws_insn));
6847
6848 /* Don't bundle a call following another call. */
6849 if ((pat = prev_active_insn (insn)) && CALL_P (pat))
6850 {
6851 need_barrier = 1;
6852 break;
6853 }
6854
6855 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6856 break;
6857
6858 case JUMP_INSN:
6859 if (!ia64_spec_check_p (insn))
6860 flags.is_branch = 1;
6861
6862 /* Don't bundle a jump following a call. */
6863 if ((pat = prev_active_insn (insn)) && CALL_P (pat))
6864 {
6865 need_barrier = 1;
6866 break;
6867 }
6868 /* FALLTHRU */
6869
6870 case INSN:
6871 if (GET_CODE (PATTERN (insn)) == USE
6872 || GET_CODE (PATTERN (insn)) == CLOBBER)
6873 /* Don't care about USE and CLOBBER "insns"---those are used to
6874 indicate to the optimizer that it shouldn't get rid of
6875 certain operations. */
6876 break;
6877
6878 pat = PATTERN (insn);
6879
6880 /* Ug. Hack hacks hacked elsewhere. */
6881 switch (recog_memoized (insn))
6882 {
6883 /* We play dependency tricks with the epilogue in order
6884 to get proper schedules. Undo this for dv analysis. */
6885 case CODE_FOR_epilogue_deallocate_stack:
6886 case CODE_FOR_prologue_allocate_stack:
6887 pat = XVECEXP (pat, 0, 0);
6888 break;
6889
6890 /* The pattern we use for br.cloop confuses the code above.
6891 The second element of the vector is representative. */
6892 case CODE_FOR_doloop_end_internal:
6893 pat = XVECEXP (pat, 0, 1);
6894 break;
6895
6896 /* Doesn't generate code. */
6897 case CODE_FOR_pred_rel_mutex:
6898 case CODE_FOR_prologue_use:
6899 return 0;
6900
6901 default:
6902 break;
6903 }
6904
6905 memset (rws_insn, 0, sizeof (rws_insn));
6906 need_barrier = rtx_needs_barrier (pat, flags, 0);
6907
6908 /* Check to see if the previous instruction was a volatile
6909 asm. */
6910 if (! need_barrier)
6911 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6912
6913 break;
6914
6915 default:
6916 gcc_unreachable ();
6917 }
6918
6919 if (first_instruction && important_for_bundling_p (insn))
6920 {
6921 need_barrier = 0;
6922 first_instruction = 0;
6923 }
6924
6925 return need_barrier;
6926 }
6927
6928 /* Like group_barrier_needed, but do not clobber the current state. */
6929
6930 static int
6931 safe_group_barrier_needed (rtx insn)
6932 {
6933 int saved_first_instruction;
6934 int t;
6935
6936 saved_first_instruction = first_instruction;
6937 in_safe_group_barrier = 1;
6938
6939 t = group_barrier_needed (insn);
6940
6941 first_instruction = saved_first_instruction;
6942 in_safe_group_barrier = 0;
6943
6944 return t;
6945 }
6946
6947 /* Scan the current function and insert stop bits as necessary to
6948 eliminate dependencies. This function assumes that a final
6949 instruction scheduling pass has been run which has already
6950 inserted most of the necessary stop bits. This function only
6951 inserts new ones at basic block boundaries, since these are
6952 invisible to the scheduler. */
6953
6954 static void
6955 emit_insn_group_barriers (FILE *dump)
6956 {
6957 rtx insn;
6958 rtx last_label = 0;
6959 int insns_since_last_label = 0;
6960
6961 init_insn_group_barriers ();
6962
6963 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6964 {
6965 if (LABEL_P (insn))
6966 {
6967 if (insns_since_last_label)
6968 last_label = insn;
6969 insns_since_last_label = 0;
6970 }
6971 else if (NOTE_P (insn)
6972 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6973 {
6974 if (insns_since_last_label)
6975 last_label = insn;
6976 insns_since_last_label = 0;
6977 }
6978 else if (NONJUMP_INSN_P (insn)
6979 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6980 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6981 {
6982 init_insn_group_barriers ();
6983 last_label = 0;
6984 }
6985 else if (NONDEBUG_INSN_P (insn))
6986 {
6987 insns_since_last_label = 1;
6988
6989 if (group_barrier_needed (insn))
6990 {
6991 if (last_label)
6992 {
6993 if (dump)
6994 fprintf (dump, "Emitting stop before label %d\n",
6995 INSN_UID (last_label));
6996 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6997 insn = last_label;
6998
6999 init_insn_group_barriers ();
7000 last_label = 0;
7001 }
7002 }
7003 }
7004 }
7005 }
7006
7007 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
7008 This function has to emit all necessary group barriers. */
7009
7010 static void
7011 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
7012 {
7013 rtx insn;
7014
7015 init_insn_group_barriers ();
7016
7017 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7018 {
7019 if (BARRIER_P (insn))
7020 {
7021 rtx last = prev_active_insn (insn);
7022
7023 if (! last)
7024 continue;
7025 if (JUMP_TABLE_DATA_P (last))
7026 last = prev_active_insn (last);
7027 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7028 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7029
7030 init_insn_group_barriers ();
7031 }
7032 else if (NONDEBUG_INSN_P (insn))
7033 {
7034 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7035 init_insn_group_barriers ();
7036 else if (group_barrier_needed (insn))
7037 {
7038 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
7039 init_insn_group_barriers ();
7040 group_barrier_needed (insn);
7041 }
7042 }
7043 }
7044 }
7045
7046 \f
7047
7048 /* Instruction scheduling support. */
7049
7050 #define NR_BUNDLES 10
7051
7052 /* A list of names of all available bundles. */
7053
7054 static const char *bundle_name [NR_BUNDLES] =
7055 {
7056 ".mii",
7057 ".mmi",
7058 ".mfi",
7059 ".mmf",
7060 #if NR_BUNDLES == 10
7061 ".bbb",
7062 ".mbb",
7063 #endif
7064 ".mib",
7065 ".mmb",
7066 ".mfb",
7067 ".mlx"
7068 };
7069
7070 /* Nonzero if we should insert stop bits into the schedule. */
7071
7072 int ia64_final_schedule = 0;
7073
7074 /* Codes of the corresponding queried units: */
7075
7076 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
7077 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
7078
7079 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
7080 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
7081
7082 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
7083
7084 /* The following variable value is an insn group barrier. */
7085
7086 static rtx dfa_stop_insn;
7087
7088 /* The following variable value is the last issued insn. */
7089
7090 static rtx last_scheduled_insn;
7091
7092 /* The following variable value is pointer to a DFA state used as
7093 temporary variable. */
7094
7095 static state_t temp_dfa_state = NULL;
7096
7097 /* The following variable value is DFA state after issuing the last
7098 insn. */
7099
7100 static state_t prev_cycle_state = NULL;
7101
7102 /* The following array element values are TRUE if the corresponding
7103 insn requires to add stop bits before it. */
7104
7105 static char *stops_p = NULL;
7106
7107 /* The following variable is used to set up the mentioned above array. */
7108
7109 static int stop_before_p = 0;
7110
7111 /* The following variable value is length of the arrays `clocks' and
7112 `add_cycles'. */
7113
7114 static int clocks_length;
7115
7116 /* The following variable value is number of data speculations in progress. */
7117 static int pending_data_specs = 0;
7118
7119 /* Number of memory references on current and three future processor cycles. */
7120 static char mem_ops_in_group[4];
7121
7122 /* Number of current processor cycle (from scheduler's point of view). */
7123 static int current_cycle;
7124
7125 static rtx ia64_single_set (rtx);
7126 static void ia64_emit_insn_before (rtx, rtx);
7127
7128 /* Map a bundle number to its pseudo-op. */
7129
7130 const char *
7131 get_bundle_name (int b)
7132 {
7133 return bundle_name[b];
7134 }
7135
7136
7137 /* Return the maximum number of instructions a cpu can issue. */
7138
7139 static int
7140 ia64_issue_rate (void)
7141 {
7142 return 6;
7143 }
7144
7145 /* Helper function - like single_set, but look inside COND_EXEC. */
7146
7147 static rtx
7148 ia64_single_set (rtx insn)
7149 {
7150 rtx x = PATTERN (insn), ret;
7151 if (GET_CODE (x) == COND_EXEC)
7152 x = COND_EXEC_CODE (x);
7153 if (GET_CODE (x) == SET)
7154 return x;
7155
7156 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
7157 Although they are not classical single set, the second set is there just
7158 to protect it from moving past FP-relative stack accesses. */
7159 switch (recog_memoized (insn))
7160 {
7161 case CODE_FOR_prologue_allocate_stack:
7162 case CODE_FOR_epilogue_deallocate_stack:
7163 ret = XVECEXP (x, 0, 0);
7164 break;
7165
7166 default:
7167 ret = single_set_2 (insn, x);
7168 break;
7169 }
7170
7171 return ret;
7172 }
7173
7174 /* Adjust the cost of a scheduling dependency.
7175 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
7176 COST is the current cost, DW is dependency weakness. */
7177 static int
7178 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw)
7179 {
7180 enum reg_note dep_type = (enum reg_note) dep_type1;
7181 enum attr_itanium_class dep_class;
7182 enum attr_itanium_class insn_class;
7183
7184 insn_class = ia64_safe_itanium_class (insn);
7185 dep_class = ia64_safe_itanium_class (dep_insn);
7186
7187 /* Treat true memory dependencies separately. Ignore apparent true
7188 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
7189 if (dep_type == REG_DEP_TRUE
7190 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
7191 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
7192 return 0;
7193
7194 if (dw == MIN_DEP_WEAK)
7195 /* Store and load are likely to alias, use higher cost to avoid stall. */
7196 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
7197 else if (dw > MIN_DEP_WEAK)
7198 {
7199 /* Store and load are less likely to alias. */
7200 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
7201 /* Assume there will be no cache conflict for floating-point data.
7202 For integer data, L1 conflict penalty is huge (17 cycles), so we
7203 never assume it will not cause a conflict. */
7204 return 0;
7205 else
7206 return cost;
7207 }
7208
7209 if (dep_type != REG_DEP_OUTPUT)
7210 return cost;
7211
7212 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
7213 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
7214 return 0;
7215
7216 return cost;
7217 }
7218
7219 /* Like emit_insn_before, but skip cycle_display notes.
7220 ??? When cycle display notes are implemented, update this. */
7221
7222 static void
7223 ia64_emit_insn_before (rtx insn, rtx before)
7224 {
7225 emit_insn_before (insn, before);
7226 }
7227
7228 /* The following function marks insns who produce addresses for load
7229 and store insns. Such insns will be placed into M slots because it
7230 decrease latency time for Itanium1 (see function
7231 `ia64_produce_address_p' and the DFA descriptions). */
7232
7233 static void
7234 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
7235 {
7236 rtx insn, next, next_tail;
7237
7238 /* Before reload, which_alternative is not set, which means that
7239 ia64_safe_itanium_class will produce wrong results for (at least)
7240 move instructions. */
7241 if (!reload_completed)
7242 return;
7243
7244 next_tail = NEXT_INSN (tail);
7245 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7246 if (INSN_P (insn))
7247 insn->call = 0;
7248 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7249 if (INSN_P (insn)
7250 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
7251 {
7252 sd_iterator_def sd_it;
7253 dep_t dep;
7254 bool has_mem_op_consumer_p = false;
7255
7256 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
7257 {
7258 enum attr_itanium_class c;
7259
7260 if (DEP_TYPE (dep) != REG_DEP_TRUE)
7261 continue;
7262
7263 next = DEP_CON (dep);
7264 c = ia64_safe_itanium_class (next);
7265 if ((c == ITANIUM_CLASS_ST
7266 || c == ITANIUM_CLASS_STF)
7267 && ia64_st_address_bypass_p (insn, next))
7268 {
7269 has_mem_op_consumer_p = true;
7270 break;
7271 }
7272 else if ((c == ITANIUM_CLASS_LD
7273 || c == ITANIUM_CLASS_FLD
7274 || c == ITANIUM_CLASS_FLDP)
7275 && ia64_ld_address_bypass_p (insn, next))
7276 {
7277 has_mem_op_consumer_p = true;
7278 break;
7279 }
7280 }
7281
7282 insn->call = has_mem_op_consumer_p;
7283 }
7284 }
7285
7286 /* We're beginning a new block. Initialize data structures as necessary. */
7287
7288 static void
7289 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7290 int sched_verbose ATTRIBUTE_UNUSED,
7291 int max_ready ATTRIBUTE_UNUSED)
7292 {
7293 #ifdef ENABLE_CHECKING
7294 rtx insn;
7295
7296 if (!sel_sched_p () && reload_completed)
7297 for (insn = NEXT_INSN (current_sched_info->prev_head);
7298 insn != current_sched_info->next_tail;
7299 insn = NEXT_INSN (insn))
7300 gcc_assert (!SCHED_GROUP_P (insn));
7301 #endif
7302 last_scheduled_insn = NULL_RTX;
7303 init_insn_group_barriers ();
7304
7305 current_cycle = 0;
7306 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7307 }
7308
7309 /* We're beginning a scheduling pass. Check assertion. */
7310
7311 static void
7312 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
7313 int sched_verbose ATTRIBUTE_UNUSED,
7314 int max_ready ATTRIBUTE_UNUSED)
7315 {
7316 gcc_assert (pending_data_specs == 0);
7317 }
7318
7319 /* Scheduling pass is now finished. Free/reset static variable. */
7320 static void
7321 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
7322 int sched_verbose ATTRIBUTE_UNUSED)
7323 {
7324 gcc_assert (pending_data_specs == 0);
7325 }
7326
7327 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7328 speculation check), FALSE otherwise. */
7329 static bool
7330 is_load_p (rtx insn)
7331 {
7332 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7333
7334 return
7335 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
7336 && get_attr_check_load (insn) == CHECK_LOAD_NO);
7337 }
7338
7339 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7340 (taking account for 3-cycle cache reference postponing for stores: Intel
7341 Itanium 2 Reference Manual for Software Development and Optimization,
7342 6.7.3.1). */
7343 static void
7344 record_memory_reference (rtx insn)
7345 {
7346 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7347
7348 switch (insn_class) {
7349 case ITANIUM_CLASS_FLD:
7350 case ITANIUM_CLASS_LD:
7351 mem_ops_in_group[current_cycle % 4]++;
7352 break;
7353 case ITANIUM_CLASS_STF:
7354 case ITANIUM_CLASS_ST:
7355 mem_ops_in_group[(current_cycle + 3) % 4]++;
7356 break;
7357 default:;
7358 }
7359 }
7360
7361 /* We are about to being issuing insns for this clock cycle.
7362 Override the default sort algorithm to better slot instructions. */
7363
7364 static int
7365 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
7366 int *pn_ready, int clock_var,
7367 int reorder_type)
7368 {
7369 int n_asms;
7370 int n_ready = *pn_ready;
7371 rtx *e_ready = ready + n_ready;
7372 rtx *insnp;
7373
7374 if (sched_verbose)
7375 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
7376
7377 if (reorder_type == 0)
7378 {
7379 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7380 n_asms = 0;
7381 for (insnp = ready; insnp < e_ready; insnp++)
7382 if (insnp < e_ready)
7383 {
7384 rtx insn = *insnp;
7385 enum attr_type t = ia64_safe_type (insn);
7386 if (t == TYPE_UNKNOWN)
7387 {
7388 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7389 || asm_noperands (PATTERN (insn)) >= 0)
7390 {
7391 rtx lowest = ready[n_asms];
7392 ready[n_asms] = insn;
7393 *insnp = lowest;
7394 n_asms++;
7395 }
7396 else
7397 {
7398 rtx highest = ready[n_ready - 1];
7399 ready[n_ready - 1] = insn;
7400 *insnp = highest;
7401 return 1;
7402 }
7403 }
7404 }
7405
7406 if (n_asms < n_ready)
7407 {
7408 /* Some normal insns to process. Skip the asms. */
7409 ready += n_asms;
7410 n_ready -= n_asms;
7411 }
7412 else if (n_ready > 0)
7413 return 1;
7414 }
7415
7416 if (ia64_final_schedule)
7417 {
7418 int deleted = 0;
7419 int nr_need_stop = 0;
7420
7421 for (insnp = ready; insnp < e_ready; insnp++)
7422 if (safe_group_barrier_needed (*insnp))
7423 nr_need_stop++;
7424
7425 if (reorder_type == 1 && n_ready == nr_need_stop)
7426 return 0;
7427 if (reorder_type == 0)
7428 return 1;
7429 insnp = e_ready;
7430 /* Move down everything that needs a stop bit, preserving
7431 relative order. */
7432 while (insnp-- > ready + deleted)
7433 while (insnp >= ready + deleted)
7434 {
7435 rtx insn = *insnp;
7436 if (! safe_group_barrier_needed (insn))
7437 break;
7438 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7439 *ready = insn;
7440 deleted++;
7441 }
7442 n_ready -= deleted;
7443 ready += deleted;
7444 }
7445
7446 current_cycle = clock_var;
7447 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
7448 {
7449 int moved = 0;
7450
7451 insnp = e_ready;
7452 /* Move down loads/stores, preserving relative order. */
7453 while (insnp-- > ready + moved)
7454 while (insnp >= ready + moved)
7455 {
7456 rtx insn = *insnp;
7457 if (! is_load_p (insn))
7458 break;
7459 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7460 *ready = insn;
7461 moved++;
7462 }
7463 n_ready -= moved;
7464 ready += moved;
7465 }
7466
7467 return 1;
7468 }
7469
7470 /* We are about to being issuing insns for this clock cycle. Override
7471 the default sort algorithm to better slot instructions. */
7472
7473 static int
7474 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
7475 int clock_var)
7476 {
7477 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
7478 pn_ready, clock_var, 0);
7479 }
7480
7481 /* Like ia64_sched_reorder, but called after issuing each insn.
7482 Override the default sort algorithm to better slot instructions. */
7483
7484 static int
7485 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
7486 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
7487 int *pn_ready, int clock_var)
7488 {
7489 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
7490 clock_var, 1);
7491 }
7492
7493 /* We are about to issue INSN. Return the number of insns left on the
7494 ready queue that can be issued this cycle. */
7495
7496 static int
7497 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
7498 int sched_verbose ATTRIBUTE_UNUSED,
7499 rtx insn ATTRIBUTE_UNUSED,
7500 int can_issue_more ATTRIBUTE_UNUSED)
7501 {
7502 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
7503 /* Modulo scheduling does not extend h_i_d when emitting
7504 new instructions. Don't use h_i_d, if we don't have to. */
7505 {
7506 if (DONE_SPEC (insn) & BEGIN_DATA)
7507 pending_data_specs++;
7508 if (CHECK_SPEC (insn) & BEGIN_DATA)
7509 pending_data_specs--;
7510 }
7511
7512 if (DEBUG_INSN_P (insn))
7513 return 1;
7514
7515 last_scheduled_insn = insn;
7516 memcpy (prev_cycle_state, curr_state, dfa_state_size);
7517 if (reload_completed)
7518 {
7519 int needed = group_barrier_needed (insn);
7520
7521 gcc_assert (!needed);
7522 if (CALL_P (insn))
7523 init_insn_group_barriers ();
7524 stops_p [INSN_UID (insn)] = stop_before_p;
7525 stop_before_p = 0;
7526
7527 record_memory_reference (insn);
7528 }
7529 return 1;
7530 }
7531
7532 /* We are choosing insn from the ready queue. Return nonzero if INSN
7533 can be chosen. */
7534
7535 static int
7536 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
7537 {
7538 gcc_assert (insn && INSN_P (insn));
7539 return ((!reload_completed
7540 || !safe_group_barrier_needed (insn))
7541 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
7542 && (!mflag_sched_mem_insns_hard_limit
7543 || !is_load_p (insn)
7544 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
7545 }
7546
7547 /* We are choosing insn from the ready queue. Return nonzero if INSN
7548 can be chosen. */
7549
7550 static bool
7551 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
7552 {
7553 gcc_assert (insn && INSN_P (insn));
7554 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7555 we keep ALAT half-empty. */
7556 return (pending_data_specs < 16
7557 || !(TODO_SPEC (insn) & BEGIN_DATA));
7558 }
7559
7560 /* The following variable value is pseudo-insn used by the DFA insn
7561 scheduler to change the DFA state when the simulated clock is
7562 increased. */
7563
7564 static rtx dfa_pre_cycle_insn;
7565
7566 /* Returns 1 when a meaningful insn was scheduled between the last group
7567 barrier and LAST. */
7568 static int
7569 scheduled_good_insn (rtx last)
7570 {
7571 if (last && recog_memoized (last) >= 0)
7572 return 1;
7573
7574 for ( ;
7575 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
7576 && !stops_p[INSN_UID (last)];
7577 last = PREV_INSN (last))
7578 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7579 the ebb we're scheduling. */
7580 if (INSN_P (last) && recog_memoized (last) >= 0)
7581 return 1;
7582
7583 return 0;
7584 }
7585
7586 /* We are about to being issuing INSN. Return nonzero if we cannot
7587 issue it on given cycle CLOCK and return zero if we should not sort
7588 the ready queue on the next clock start. */
7589
7590 static int
7591 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
7592 int clock, int *sort_p)
7593 {
7594 gcc_assert (insn && INSN_P (insn));
7595
7596 if (DEBUG_INSN_P (insn))
7597 return 0;
7598
7599 /* When a group barrier is needed for insn, last_scheduled_insn
7600 should be set. */
7601 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
7602 || last_scheduled_insn);
7603
7604 if ((reload_completed
7605 && (safe_group_barrier_needed (insn)
7606 || (mflag_sched_stop_bits_after_every_cycle
7607 && last_clock != clock
7608 && last_scheduled_insn
7609 && scheduled_good_insn (last_scheduled_insn))))
7610 || (last_scheduled_insn
7611 && (CALL_P (last_scheduled_insn)
7612 || unknown_for_bundling_p (last_scheduled_insn))))
7613 {
7614 init_insn_group_barriers ();
7615
7616 if (verbose && dump)
7617 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
7618 last_clock == clock ? " + cycle advance" : "");
7619
7620 stop_before_p = 1;
7621 current_cycle = clock;
7622 mem_ops_in_group[current_cycle % 4] = 0;
7623
7624 if (last_clock == clock)
7625 {
7626 state_transition (curr_state, dfa_stop_insn);
7627 if (TARGET_EARLY_STOP_BITS)
7628 *sort_p = (last_scheduled_insn == NULL_RTX
7629 || ! CALL_P (last_scheduled_insn));
7630 else
7631 *sort_p = 0;
7632 return 1;
7633 }
7634
7635 if (last_scheduled_insn)
7636 {
7637 if (unknown_for_bundling_p (last_scheduled_insn))
7638 state_reset (curr_state);
7639 else
7640 {
7641 memcpy (curr_state, prev_cycle_state, dfa_state_size);
7642 state_transition (curr_state, dfa_stop_insn);
7643 state_transition (curr_state, dfa_pre_cycle_insn);
7644 state_transition (curr_state, NULL);
7645 }
7646 }
7647 }
7648 return 0;
7649 }
7650
7651 /* Implement targetm.sched.h_i_d_extended hook.
7652 Extend internal data structures. */
7653 static void
7654 ia64_h_i_d_extended (void)
7655 {
7656 if (stops_p != NULL)
7657 {
7658 int new_clocks_length = get_max_uid () * 3 / 2;
7659 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
7660 clocks_length = new_clocks_length;
7661 }
7662 }
7663 \f
7664
7665 /* This structure describes the data used by the backend to guide scheduling.
7666 When the current scheduling point is switched, this data should be saved
7667 and restored later, if the scheduler returns to this point. */
7668 struct _ia64_sched_context
7669 {
7670 state_t prev_cycle_state;
7671 rtx last_scheduled_insn;
7672 struct reg_write_state rws_sum[NUM_REGS];
7673 struct reg_write_state rws_insn[NUM_REGS];
7674 int first_instruction;
7675 int pending_data_specs;
7676 int current_cycle;
7677 char mem_ops_in_group[4];
7678 };
7679 typedef struct _ia64_sched_context *ia64_sched_context_t;
7680
7681 /* Allocates a scheduling context. */
7682 static void *
7683 ia64_alloc_sched_context (void)
7684 {
7685 return xmalloc (sizeof (struct _ia64_sched_context));
7686 }
7687
7688 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7689 the global context otherwise. */
7690 static void
7691 ia64_init_sched_context (void *_sc, bool clean_p)
7692 {
7693 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7694
7695 sc->prev_cycle_state = xmalloc (dfa_state_size);
7696 if (clean_p)
7697 {
7698 state_reset (sc->prev_cycle_state);
7699 sc->last_scheduled_insn = NULL_RTX;
7700 memset (sc->rws_sum, 0, sizeof (rws_sum));
7701 memset (sc->rws_insn, 0, sizeof (rws_insn));
7702 sc->first_instruction = 1;
7703 sc->pending_data_specs = 0;
7704 sc->current_cycle = 0;
7705 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7706 }
7707 else
7708 {
7709 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7710 sc->last_scheduled_insn = last_scheduled_insn;
7711 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7712 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7713 sc->first_instruction = first_instruction;
7714 sc->pending_data_specs = pending_data_specs;
7715 sc->current_cycle = current_cycle;
7716 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7717 }
7718 }
7719
7720 /* Sets the global scheduling context to the one pointed to by _SC. */
7721 static void
7722 ia64_set_sched_context (void *_sc)
7723 {
7724 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7725
7726 gcc_assert (sc != NULL);
7727
7728 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7729 last_scheduled_insn = sc->last_scheduled_insn;
7730 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7731 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7732 first_instruction = sc->first_instruction;
7733 pending_data_specs = sc->pending_data_specs;
7734 current_cycle = sc->current_cycle;
7735 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7736 }
7737
7738 /* Clears the data in the _SC scheduling context. */
7739 static void
7740 ia64_clear_sched_context (void *_sc)
7741 {
7742 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7743
7744 free (sc->prev_cycle_state);
7745 sc->prev_cycle_state = NULL;
7746 }
7747
7748 /* Frees the _SC scheduling context. */
7749 static void
7750 ia64_free_sched_context (void *_sc)
7751 {
7752 gcc_assert (_sc != NULL);
7753
7754 free (_sc);
7755 }
7756
7757 typedef rtx (* gen_func_t) (rtx, rtx);
7758
7759 /* Return a function that will generate a load of mode MODE_NO
7760 with speculation types TS. */
7761 static gen_func_t
7762 get_spec_load_gen_function (ds_t ts, int mode_no)
7763 {
7764 static gen_func_t gen_ld_[] = {
7765 gen_movbi,
7766 gen_movqi_internal,
7767 gen_movhi_internal,
7768 gen_movsi_internal,
7769 gen_movdi_internal,
7770 gen_movsf_internal,
7771 gen_movdf_internal,
7772 gen_movxf_internal,
7773 gen_movti_internal,
7774 gen_zero_extendqidi2,
7775 gen_zero_extendhidi2,
7776 gen_zero_extendsidi2,
7777 };
7778
7779 static gen_func_t gen_ld_a[] = {
7780 gen_movbi_advanced,
7781 gen_movqi_advanced,
7782 gen_movhi_advanced,
7783 gen_movsi_advanced,
7784 gen_movdi_advanced,
7785 gen_movsf_advanced,
7786 gen_movdf_advanced,
7787 gen_movxf_advanced,
7788 gen_movti_advanced,
7789 gen_zero_extendqidi2_advanced,
7790 gen_zero_extendhidi2_advanced,
7791 gen_zero_extendsidi2_advanced,
7792 };
7793 static gen_func_t gen_ld_s[] = {
7794 gen_movbi_speculative,
7795 gen_movqi_speculative,
7796 gen_movhi_speculative,
7797 gen_movsi_speculative,
7798 gen_movdi_speculative,
7799 gen_movsf_speculative,
7800 gen_movdf_speculative,
7801 gen_movxf_speculative,
7802 gen_movti_speculative,
7803 gen_zero_extendqidi2_speculative,
7804 gen_zero_extendhidi2_speculative,
7805 gen_zero_extendsidi2_speculative,
7806 };
7807 static gen_func_t gen_ld_sa[] = {
7808 gen_movbi_speculative_advanced,
7809 gen_movqi_speculative_advanced,
7810 gen_movhi_speculative_advanced,
7811 gen_movsi_speculative_advanced,
7812 gen_movdi_speculative_advanced,
7813 gen_movsf_speculative_advanced,
7814 gen_movdf_speculative_advanced,
7815 gen_movxf_speculative_advanced,
7816 gen_movti_speculative_advanced,
7817 gen_zero_extendqidi2_speculative_advanced,
7818 gen_zero_extendhidi2_speculative_advanced,
7819 gen_zero_extendsidi2_speculative_advanced,
7820 };
7821 static gen_func_t gen_ld_s_a[] = {
7822 gen_movbi_speculative_a,
7823 gen_movqi_speculative_a,
7824 gen_movhi_speculative_a,
7825 gen_movsi_speculative_a,
7826 gen_movdi_speculative_a,
7827 gen_movsf_speculative_a,
7828 gen_movdf_speculative_a,
7829 gen_movxf_speculative_a,
7830 gen_movti_speculative_a,
7831 gen_zero_extendqidi2_speculative_a,
7832 gen_zero_extendhidi2_speculative_a,
7833 gen_zero_extendsidi2_speculative_a,
7834 };
7835
7836 gen_func_t *gen_ld;
7837
7838 if (ts & BEGIN_DATA)
7839 {
7840 if (ts & BEGIN_CONTROL)
7841 gen_ld = gen_ld_sa;
7842 else
7843 gen_ld = gen_ld_a;
7844 }
7845 else if (ts & BEGIN_CONTROL)
7846 {
7847 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7848 || ia64_needs_block_p (ts))
7849 gen_ld = gen_ld_s;
7850 else
7851 gen_ld = gen_ld_s_a;
7852 }
7853 else if (ts == 0)
7854 gen_ld = gen_ld_;
7855 else
7856 gcc_unreachable ();
7857
7858 return gen_ld[mode_no];
7859 }
7860
7861 /* Constants that help mapping 'enum machine_mode' to int. */
7862 enum SPEC_MODES
7863 {
7864 SPEC_MODE_INVALID = -1,
7865 SPEC_MODE_FIRST = 0,
7866 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7867 SPEC_MODE_FOR_EXTEND_LAST = 3,
7868 SPEC_MODE_LAST = 8
7869 };
7870
7871 enum
7872 {
7873 /* Offset to reach ZERO_EXTEND patterns. */
7874 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7875 };
7876
7877 /* Return index of the MODE. */
7878 static int
7879 ia64_mode_to_int (enum machine_mode mode)
7880 {
7881 switch (mode)
7882 {
7883 case BImode: return 0; /* SPEC_MODE_FIRST */
7884 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7885 case HImode: return 2;
7886 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7887 case DImode: return 4;
7888 case SFmode: return 5;
7889 case DFmode: return 6;
7890 case XFmode: return 7;
7891 case TImode:
7892 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7893 mentioned in itanium[12].md. Predicate fp_register_operand also
7894 needs to be defined. Bottom line: better disable for now. */
7895 return SPEC_MODE_INVALID;
7896 default: return SPEC_MODE_INVALID;
7897 }
7898 }
7899
7900 /* Provide information about speculation capabilities. */
7901 static void
7902 ia64_set_sched_flags (spec_info_t spec_info)
7903 {
7904 unsigned int *flags = &(current_sched_info->flags);
7905
7906 if (*flags & SCHED_RGN
7907 || *flags & SCHED_EBB
7908 || *flags & SEL_SCHED)
7909 {
7910 int mask = 0;
7911
7912 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7913 || (mflag_sched_ar_data_spec && reload_completed))
7914 {
7915 mask |= BEGIN_DATA;
7916
7917 if (!sel_sched_p ()
7918 && ((mflag_sched_br_in_data_spec && !reload_completed)
7919 || (mflag_sched_ar_in_data_spec && reload_completed)))
7920 mask |= BE_IN_DATA;
7921 }
7922
7923 if (mflag_sched_control_spec
7924 && (!sel_sched_p ()
7925 || reload_completed))
7926 {
7927 mask |= BEGIN_CONTROL;
7928
7929 if (!sel_sched_p () && mflag_sched_in_control_spec)
7930 mask |= BE_IN_CONTROL;
7931 }
7932
7933 spec_info->mask = mask;
7934
7935 if (mask)
7936 {
7937 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7938
7939 if (mask & BE_IN_SPEC)
7940 *flags |= NEW_BBS;
7941
7942 spec_info->flags = 0;
7943
7944 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
7945 spec_info->flags |= PREFER_NON_DATA_SPEC;
7946
7947 if (mask & CONTROL_SPEC)
7948 {
7949 if (mflag_sched_prefer_non_control_spec_insns)
7950 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
7951
7952 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7953 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7954 }
7955
7956 if (sched_verbose >= 1)
7957 spec_info->dump = sched_dump;
7958 else
7959 spec_info->dump = 0;
7960
7961 if (mflag_sched_count_spec_in_critical_path)
7962 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7963 }
7964 }
7965 else
7966 spec_info->mask = 0;
7967 }
7968
7969 /* If INSN is an appropriate load return its mode.
7970 Return -1 otherwise. */
7971 static int
7972 get_mode_no_for_insn (rtx insn)
7973 {
7974 rtx reg, mem, mode_rtx;
7975 int mode_no;
7976 bool extend_p;
7977
7978 extract_insn_cached (insn);
7979
7980 /* We use WHICH_ALTERNATIVE only after reload. This will
7981 guarantee that reload won't touch a speculative insn. */
7982
7983 if (recog_data.n_operands != 2)
7984 return -1;
7985
7986 reg = recog_data.operand[0];
7987 mem = recog_data.operand[1];
7988
7989 /* We should use MEM's mode since REG's mode in presence of
7990 ZERO_EXTEND will always be DImode. */
7991 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7992 /* Process non-speculative ld. */
7993 {
7994 if (!reload_completed)
7995 {
7996 /* Do not speculate into regs like ar.lc. */
7997 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7998 return -1;
7999
8000 if (!MEM_P (mem))
8001 return -1;
8002
8003 {
8004 rtx mem_reg = XEXP (mem, 0);
8005
8006 if (!REG_P (mem_reg))
8007 return -1;
8008 }
8009
8010 mode_rtx = mem;
8011 }
8012 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
8013 {
8014 gcc_assert (REG_P (reg) && MEM_P (mem));
8015 mode_rtx = mem;
8016 }
8017 else
8018 return -1;
8019 }
8020 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
8021 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
8022 || get_attr_check_load (insn) == CHECK_LOAD_YES)
8023 /* Process speculative ld or ld.c. */
8024 {
8025 gcc_assert (REG_P (reg) && MEM_P (mem));
8026 mode_rtx = mem;
8027 }
8028 else
8029 {
8030 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
8031
8032 if (attr_class == ITANIUM_CLASS_CHK_A
8033 || attr_class == ITANIUM_CLASS_CHK_S_I
8034 || attr_class == ITANIUM_CLASS_CHK_S_F)
8035 /* Process chk. */
8036 mode_rtx = reg;
8037 else
8038 return -1;
8039 }
8040
8041 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
8042
8043 if (mode_no == SPEC_MODE_INVALID)
8044 return -1;
8045
8046 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
8047
8048 if (extend_p)
8049 {
8050 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
8051 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
8052 return -1;
8053
8054 mode_no += SPEC_GEN_EXTEND_OFFSET;
8055 }
8056
8057 return mode_no;
8058 }
8059
8060 /* If X is an unspec part of a speculative load, return its code.
8061 Return -1 otherwise. */
8062 static int
8063 get_spec_unspec_code (const_rtx x)
8064 {
8065 if (GET_CODE (x) != UNSPEC)
8066 return -1;
8067
8068 {
8069 int code;
8070
8071 code = XINT (x, 1);
8072
8073 switch (code)
8074 {
8075 case UNSPEC_LDA:
8076 case UNSPEC_LDS:
8077 case UNSPEC_LDS_A:
8078 case UNSPEC_LDSA:
8079 return code;
8080
8081 default:
8082 return -1;
8083 }
8084 }
8085 }
8086
8087 /* Implement skip_rtx_p hook. */
8088 static bool
8089 ia64_skip_rtx_p (const_rtx x)
8090 {
8091 return get_spec_unspec_code (x) != -1;
8092 }
8093
8094 /* If INSN is a speculative load, return its UNSPEC code.
8095 Return -1 otherwise. */
8096 static int
8097 get_insn_spec_code (const_rtx insn)
8098 {
8099 rtx pat, reg, mem;
8100
8101 pat = PATTERN (insn);
8102
8103 if (GET_CODE (pat) == COND_EXEC)
8104 pat = COND_EXEC_CODE (pat);
8105
8106 if (GET_CODE (pat) != SET)
8107 return -1;
8108
8109 reg = SET_DEST (pat);
8110 if (!REG_P (reg))
8111 return -1;
8112
8113 mem = SET_SRC (pat);
8114 if (GET_CODE (mem) == ZERO_EXTEND)
8115 mem = XEXP (mem, 0);
8116
8117 return get_spec_unspec_code (mem);
8118 }
8119
8120 /* If INSN is a speculative load, return a ds with the speculation types.
8121 Otherwise [if INSN is a normal instruction] return 0. */
8122 static ds_t
8123 ia64_get_insn_spec_ds (rtx insn)
8124 {
8125 int code = get_insn_spec_code (insn);
8126
8127 switch (code)
8128 {
8129 case UNSPEC_LDA:
8130 return BEGIN_DATA;
8131
8132 case UNSPEC_LDS:
8133 case UNSPEC_LDS_A:
8134 return BEGIN_CONTROL;
8135
8136 case UNSPEC_LDSA:
8137 return BEGIN_DATA | BEGIN_CONTROL;
8138
8139 default:
8140 return 0;
8141 }
8142 }
8143
8144 /* If INSN is a speculative load return a ds with the speculation types that
8145 will be checked.
8146 Otherwise [if INSN is a normal instruction] return 0. */
8147 static ds_t
8148 ia64_get_insn_checked_ds (rtx insn)
8149 {
8150 int code = get_insn_spec_code (insn);
8151
8152 switch (code)
8153 {
8154 case UNSPEC_LDA:
8155 return BEGIN_DATA | BEGIN_CONTROL;
8156
8157 case UNSPEC_LDS:
8158 return BEGIN_CONTROL;
8159
8160 case UNSPEC_LDS_A:
8161 case UNSPEC_LDSA:
8162 return BEGIN_DATA | BEGIN_CONTROL;
8163
8164 default:
8165 return 0;
8166 }
8167 }
8168
8169 /* If GEN_P is true, calculate the index of needed speculation check and return
8170 speculative pattern for INSN with speculative mode TS, machine mode
8171 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
8172 If GEN_P is false, just calculate the index of needed speculation check. */
8173 static rtx
8174 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
8175 {
8176 rtx pat, new_pat;
8177 gen_func_t gen_load;
8178
8179 gen_load = get_spec_load_gen_function (ts, mode_no);
8180
8181 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
8182 copy_rtx (recog_data.operand[1]));
8183
8184 pat = PATTERN (insn);
8185 if (GET_CODE (pat) == COND_EXEC)
8186 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8187 new_pat);
8188
8189 return new_pat;
8190 }
8191
8192 static bool
8193 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
8194 ds_t ds ATTRIBUTE_UNUSED)
8195 {
8196 return false;
8197 }
8198
8199 /* Implement targetm.sched.speculate_insn hook.
8200 Check if the INSN can be TS speculative.
8201 If 'no' - return -1.
8202 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
8203 If current pattern of the INSN already provides TS speculation,
8204 return 0. */
8205 static int
8206 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
8207 {
8208 int mode_no;
8209 int res;
8210
8211 gcc_assert (!(ts & ~SPECULATIVE));
8212
8213 if (ia64_spec_check_p (insn))
8214 return -1;
8215
8216 if ((ts & BE_IN_SPEC)
8217 && !insn_can_be_in_speculative_p (insn, ts))
8218 return -1;
8219
8220 mode_no = get_mode_no_for_insn (insn);
8221
8222 if (mode_no != SPEC_MODE_INVALID)
8223 {
8224 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
8225 res = 0;
8226 else
8227 {
8228 res = 1;
8229 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
8230 }
8231 }
8232 else
8233 res = -1;
8234
8235 return res;
8236 }
8237
8238 /* Return a function that will generate a check for speculation TS with mode
8239 MODE_NO.
8240 If simple check is needed, pass true for SIMPLE_CHECK_P.
8241 If clearing check is needed, pass true for CLEARING_CHECK_P. */
8242 static gen_func_t
8243 get_spec_check_gen_function (ds_t ts, int mode_no,
8244 bool simple_check_p, bool clearing_check_p)
8245 {
8246 static gen_func_t gen_ld_c_clr[] = {
8247 gen_movbi_clr,
8248 gen_movqi_clr,
8249 gen_movhi_clr,
8250 gen_movsi_clr,
8251 gen_movdi_clr,
8252 gen_movsf_clr,
8253 gen_movdf_clr,
8254 gen_movxf_clr,
8255 gen_movti_clr,
8256 gen_zero_extendqidi2_clr,
8257 gen_zero_extendhidi2_clr,
8258 gen_zero_extendsidi2_clr,
8259 };
8260 static gen_func_t gen_ld_c_nc[] = {
8261 gen_movbi_nc,
8262 gen_movqi_nc,
8263 gen_movhi_nc,
8264 gen_movsi_nc,
8265 gen_movdi_nc,
8266 gen_movsf_nc,
8267 gen_movdf_nc,
8268 gen_movxf_nc,
8269 gen_movti_nc,
8270 gen_zero_extendqidi2_nc,
8271 gen_zero_extendhidi2_nc,
8272 gen_zero_extendsidi2_nc,
8273 };
8274 static gen_func_t gen_chk_a_clr[] = {
8275 gen_advanced_load_check_clr_bi,
8276 gen_advanced_load_check_clr_qi,
8277 gen_advanced_load_check_clr_hi,
8278 gen_advanced_load_check_clr_si,
8279 gen_advanced_load_check_clr_di,
8280 gen_advanced_load_check_clr_sf,
8281 gen_advanced_load_check_clr_df,
8282 gen_advanced_load_check_clr_xf,
8283 gen_advanced_load_check_clr_ti,
8284 gen_advanced_load_check_clr_di,
8285 gen_advanced_load_check_clr_di,
8286 gen_advanced_load_check_clr_di,
8287 };
8288 static gen_func_t gen_chk_a_nc[] = {
8289 gen_advanced_load_check_nc_bi,
8290 gen_advanced_load_check_nc_qi,
8291 gen_advanced_load_check_nc_hi,
8292 gen_advanced_load_check_nc_si,
8293 gen_advanced_load_check_nc_di,
8294 gen_advanced_load_check_nc_sf,
8295 gen_advanced_load_check_nc_df,
8296 gen_advanced_load_check_nc_xf,
8297 gen_advanced_load_check_nc_ti,
8298 gen_advanced_load_check_nc_di,
8299 gen_advanced_load_check_nc_di,
8300 gen_advanced_load_check_nc_di,
8301 };
8302 static gen_func_t gen_chk_s[] = {
8303 gen_speculation_check_bi,
8304 gen_speculation_check_qi,
8305 gen_speculation_check_hi,
8306 gen_speculation_check_si,
8307 gen_speculation_check_di,
8308 gen_speculation_check_sf,
8309 gen_speculation_check_df,
8310 gen_speculation_check_xf,
8311 gen_speculation_check_ti,
8312 gen_speculation_check_di,
8313 gen_speculation_check_di,
8314 gen_speculation_check_di,
8315 };
8316
8317 gen_func_t *gen_check;
8318
8319 if (ts & BEGIN_DATA)
8320 {
8321 /* We don't need recovery because even if this is ld.sa
8322 ALAT entry will be allocated only if NAT bit is set to zero.
8323 So it is enough to use ld.c here. */
8324
8325 if (simple_check_p)
8326 {
8327 gcc_assert (mflag_sched_spec_ldc);
8328
8329 if (clearing_check_p)
8330 gen_check = gen_ld_c_clr;
8331 else
8332 gen_check = gen_ld_c_nc;
8333 }
8334 else
8335 {
8336 if (clearing_check_p)
8337 gen_check = gen_chk_a_clr;
8338 else
8339 gen_check = gen_chk_a_nc;
8340 }
8341 }
8342 else if (ts & BEGIN_CONTROL)
8343 {
8344 if (simple_check_p)
8345 /* We might want to use ld.sa -> ld.c instead of
8346 ld.s -> chk.s. */
8347 {
8348 gcc_assert (!ia64_needs_block_p (ts));
8349
8350 if (clearing_check_p)
8351 gen_check = gen_ld_c_clr;
8352 else
8353 gen_check = gen_ld_c_nc;
8354 }
8355 else
8356 {
8357 gen_check = gen_chk_s;
8358 }
8359 }
8360 else
8361 gcc_unreachable ();
8362
8363 gcc_assert (mode_no >= 0);
8364 return gen_check[mode_no];
8365 }
8366
8367 /* Return nonzero, if INSN needs branchy recovery check. */
8368 static bool
8369 ia64_needs_block_p (ds_t ts)
8370 {
8371 if (ts & BEGIN_DATA)
8372 return !mflag_sched_spec_ldc;
8373
8374 gcc_assert ((ts & BEGIN_CONTROL) != 0);
8375
8376 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
8377 }
8378
8379 /* Generate (or regenerate) a recovery check for INSN. */
8380 static rtx
8381 ia64_gen_spec_check (rtx insn, rtx label, ds_t ds)
8382 {
8383 rtx op1, pat, check_pat;
8384 gen_func_t gen_check;
8385 int mode_no;
8386
8387 mode_no = get_mode_no_for_insn (insn);
8388 gcc_assert (mode_no >= 0);
8389
8390 if (label)
8391 op1 = label;
8392 else
8393 {
8394 gcc_assert (!ia64_needs_block_p (ds));
8395 op1 = copy_rtx (recog_data.operand[1]);
8396 }
8397
8398 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
8399 true);
8400
8401 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
8402
8403 pat = PATTERN (insn);
8404 if (GET_CODE (pat) == COND_EXEC)
8405 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8406 check_pat);
8407
8408 return check_pat;
8409 }
8410
8411 /* Return nonzero, if X is branchy recovery check. */
8412 static int
8413 ia64_spec_check_p (rtx x)
8414 {
8415 x = PATTERN (x);
8416 if (GET_CODE (x) == COND_EXEC)
8417 x = COND_EXEC_CODE (x);
8418 if (GET_CODE (x) == SET)
8419 return ia64_spec_check_src_p (SET_SRC (x));
8420 return 0;
8421 }
8422
8423 /* Return nonzero, if SRC belongs to recovery check. */
8424 static int
8425 ia64_spec_check_src_p (rtx src)
8426 {
8427 if (GET_CODE (src) == IF_THEN_ELSE)
8428 {
8429 rtx t;
8430
8431 t = XEXP (src, 0);
8432 if (GET_CODE (t) == NE)
8433 {
8434 t = XEXP (t, 0);
8435
8436 if (GET_CODE (t) == UNSPEC)
8437 {
8438 int code;
8439
8440 code = XINT (t, 1);
8441
8442 if (code == UNSPEC_LDCCLR
8443 || code == UNSPEC_LDCNC
8444 || code == UNSPEC_CHKACLR
8445 || code == UNSPEC_CHKANC
8446 || code == UNSPEC_CHKS)
8447 {
8448 gcc_assert (code != 0);
8449 return code;
8450 }
8451 }
8452 }
8453 }
8454 return 0;
8455 }
8456 \f
8457
8458 /* The following page contains abstract data `bundle states' which are
8459 used for bundling insns (inserting nops and template generation). */
8460
8461 /* The following describes state of insn bundling. */
8462
8463 struct bundle_state
8464 {
8465 /* Unique bundle state number to identify them in the debugging
8466 output */
8467 int unique_num;
8468 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
8469 /* number nops before and after the insn */
8470 short before_nops_num, after_nops_num;
8471 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
8472 insn */
8473 int cost; /* cost of the state in cycles */
8474 int accumulated_insns_num; /* number of all previous insns including
8475 nops. L is considered as 2 insns */
8476 int branch_deviation; /* deviation of previous branches from 3rd slots */
8477 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
8478 struct bundle_state *next; /* next state with the same insn_num */
8479 struct bundle_state *originator; /* originator (previous insn state) */
8480 /* All bundle states are in the following chain. */
8481 struct bundle_state *allocated_states_chain;
8482 /* The DFA State after issuing the insn and the nops. */
8483 state_t dfa_state;
8484 };
8485
8486 /* The following is map insn number to the corresponding bundle state. */
8487
8488 static struct bundle_state **index_to_bundle_states;
8489
8490 /* The unique number of next bundle state. */
8491
8492 static int bundle_states_num;
8493
8494 /* All allocated bundle states are in the following chain. */
8495
8496 static struct bundle_state *allocated_bundle_states_chain;
8497
8498 /* All allocated but not used bundle states are in the following
8499 chain. */
8500
8501 static struct bundle_state *free_bundle_state_chain;
8502
8503
8504 /* The following function returns a free bundle state. */
8505
8506 static struct bundle_state *
8507 get_free_bundle_state (void)
8508 {
8509 struct bundle_state *result;
8510
8511 if (free_bundle_state_chain != NULL)
8512 {
8513 result = free_bundle_state_chain;
8514 free_bundle_state_chain = result->next;
8515 }
8516 else
8517 {
8518 result = XNEW (struct bundle_state);
8519 result->dfa_state = xmalloc (dfa_state_size);
8520 result->allocated_states_chain = allocated_bundle_states_chain;
8521 allocated_bundle_states_chain = result;
8522 }
8523 result->unique_num = bundle_states_num++;
8524 return result;
8525
8526 }
8527
8528 /* The following function frees given bundle state. */
8529
8530 static void
8531 free_bundle_state (struct bundle_state *state)
8532 {
8533 state->next = free_bundle_state_chain;
8534 free_bundle_state_chain = state;
8535 }
8536
8537 /* Start work with abstract data `bundle states'. */
8538
8539 static void
8540 initiate_bundle_states (void)
8541 {
8542 bundle_states_num = 0;
8543 free_bundle_state_chain = NULL;
8544 allocated_bundle_states_chain = NULL;
8545 }
8546
8547 /* Finish work with abstract data `bundle states'. */
8548
8549 static void
8550 finish_bundle_states (void)
8551 {
8552 struct bundle_state *curr_state, *next_state;
8553
8554 for (curr_state = allocated_bundle_states_chain;
8555 curr_state != NULL;
8556 curr_state = next_state)
8557 {
8558 next_state = curr_state->allocated_states_chain;
8559 free (curr_state->dfa_state);
8560 free (curr_state);
8561 }
8562 }
8563
8564 /* Hashtable helpers. */
8565
8566 struct bundle_state_hasher : typed_noop_remove <bundle_state>
8567 {
8568 typedef bundle_state value_type;
8569 typedef bundle_state compare_type;
8570 static inline hashval_t hash (const value_type *);
8571 static inline bool equal (const value_type *, const compare_type *);
8572 };
8573
8574 /* The function returns hash of BUNDLE_STATE. */
8575
8576 inline hashval_t
8577 bundle_state_hasher::hash (const value_type *state)
8578 {
8579 unsigned result, i;
8580
8581 for (result = i = 0; i < dfa_state_size; i++)
8582 result += (((unsigned char *) state->dfa_state) [i]
8583 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
8584 return result + state->insn_num;
8585 }
8586
8587 /* The function returns nonzero if the bundle state keys are equal. */
8588
8589 inline bool
8590 bundle_state_hasher::equal (const value_type *state1,
8591 const compare_type *state2)
8592 {
8593 return (state1->insn_num == state2->insn_num
8594 && memcmp (state1->dfa_state, state2->dfa_state,
8595 dfa_state_size) == 0);
8596 }
8597
8598 /* Hash table of the bundle states. The key is dfa_state and insn_num
8599 of the bundle states. */
8600
8601 static hash_table <bundle_state_hasher> bundle_state_table;
8602
8603 /* The function inserts the BUNDLE_STATE into the hash table. The
8604 function returns nonzero if the bundle has been inserted into the
8605 table. The table contains the best bundle state with given key. */
8606
8607 static int
8608 insert_bundle_state (struct bundle_state *bundle_state)
8609 {
8610 struct bundle_state **entry_ptr;
8611
8612 entry_ptr = bundle_state_table.find_slot (bundle_state, INSERT);
8613 if (*entry_ptr == NULL)
8614 {
8615 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
8616 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
8617 *entry_ptr = bundle_state;
8618 return TRUE;
8619 }
8620 else if (bundle_state->cost < (*entry_ptr)->cost
8621 || (bundle_state->cost == (*entry_ptr)->cost
8622 && ((*entry_ptr)->accumulated_insns_num
8623 > bundle_state->accumulated_insns_num
8624 || ((*entry_ptr)->accumulated_insns_num
8625 == bundle_state->accumulated_insns_num
8626 && ((*entry_ptr)->branch_deviation
8627 > bundle_state->branch_deviation
8628 || ((*entry_ptr)->branch_deviation
8629 == bundle_state->branch_deviation
8630 && (*entry_ptr)->middle_bundle_stops
8631 > bundle_state->middle_bundle_stops))))))
8632
8633 {
8634 struct bundle_state temp;
8635
8636 temp = **entry_ptr;
8637 **entry_ptr = *bundle_state;
8638 (*entry_ptr)->next = temp.next;
8639 *bundle_state = temp;
8640 }
8641 return FALSE;
8642 }
8643
8644 /* Start work with the hash table. */
8645
8646 static void
8647 initiate_bundle_state_table (void)
8648 {
8649 bundle_state_table.create (50);
8650 }
8651
8652 /* Finish work with the hash table. */
8653
8654 static void
8655 finish_bundle_state_table (void)
8656 {
8657 bundle_state_table.dispose ();
8658 }
8659
8660 \f
8661
8662 /* The following variable is a insn `nop' used to check bundle states
8663 with different number of inserted nops. */
8664
8665 static rtx ia64_nop;
8666
8667 /* The following function tries to issue NOPS_NUM nops for the current
8668 state without advancing processor cycle. If it failed, the
8669 function returns FALSE and frees the current state. */
8670
8671 static int
8672 try_issue_nops (struct bundle_state *curr_state, int nops_num)
8673 {
8674 int i;
8675
8676 for (i = 0; i < nops_num; i++)
8677 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
8678 {
8679 free_bundle_state (curr_state);
8680 return FALSE;
8681 }
8682 return TRUE;
8683 }
8684
8685 /* The following function tries to issue INSN for the current
8686 state without advancing processor cycle. If it failed, the
8687 function returns FALSE and frees the current state. */
8688
8689 static int
8690 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8691 {
8692 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8693 {
8694 free_bundle_state (curr_state);
8695 return FALSE;
8696 }
8697 return TRUE;
8698 }
8699
8700 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8701 starting with ORIGINATOR without advancing processor cycle. If
8702 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8703 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8704 If it was successful, the function creates new bundle state and
8705 insert into the hash table and into `index_to_bundle_states'. */
8706
8707 static void
8708 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8709 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8710 {
8711 struct bundle_state *curr_state;
8712
8713 curr_state = get_free_bundle_state ();
8714 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8715 curr_state->insn = insn;
8716 curr_state->insn_num = originator->insn_num + 1;
8717 curr_state->cost = originator->cost;
8718 curr_state->originator = originator;
8719 curr_state->before_nops_num = before_nops_num;
8720 curr_state->after_nops_num = 0;
8721 curr_state->accumulated_insns_num
8722 = originator->accumulated_insns_num + before_nops_num;
8723 curr_state->branch_deviation = originator->branch_deviation;
8724 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8725 gcc_assert (insn);
8726 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8727 {
8728 gcc_assert (GET_MODE (insn) != TImode);
8729 if (!try_issue_nops (curr_state, before_nops_num))
8730 return;
8731 if (!try_issue_insn (curr_state, insn))
8732 return;
8733 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8734 if (curr_state->accumulated_insns_num % 3 != 0)
8735 curr_state->middle_bundle_stops++;
8736 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8737 && curr_state->accumulated_insns_num % 3 != 0)
8738 {
8739 free_bundle_state (curr_state);
8740 return;
8741 }
8742 }
8743 else if (GET_MODE (insn) != TImode)
8744 {
8745 if (!try_issue_nops (curr_state, before_nops_num))
8746 return;
8747 if (!try_issue_insn (curr_state, insn))
8748 return;
8749 curr_state->accumulated_insns_num++;
8750 gcc_assert (!unknown_for_bundling_p (insn));
8751
8752 if (ia64_safe_type (insn) == TYPE_L)
8753 curr_state->accumulated_insns_num++;
8754 }
8755 else
8756 {
8757 /* If this is an insn that must be first in a group, then don't allow
8758 nops to be emitted before it. Currently, alloc is the only such
8759 supported instruction. */
8760 /* ??? The bundling automatons should handle this for us, but they do
8761 not yet have support for the first_insn attribute. */
8762 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8763 {
8764 free_bundle_state (curr_state);
8765 return;
8766 }
8767
8768 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8769 state_transition (curr_state->dfa_state, NULL);
8770 curr_state->cost++;
8771 if (!try_issue_nops (curr_state, before_nops_num))
8772 return;
8773 if (!try_issue_insn (curr_state, insn))
8774 return;
8775 curr_state->accumulated_insns_num++;
8776 if (unknown_for_bundling_p (insn))
8777 {
8778 /* Finish bundle containing asm insn. */
8779 curr_state->after_nops_num
8780 = 3 - curr_state->accumulated_insns_num % 3;
8781 curr_state->accumulated_insns_num
8782 += 3 - curr_state->accumulated_insns_num % 3;
8783 }
8784 else if (ia64_safe_type (insn) == TYPE_L)
8785 curr_state->accumulated_insns_num++;
8786 }
8787 if (ia64_safe_type (insn) == TYPE_B)
8788 curr_state->branch_deviation
8789 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8790 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8791 {
8792 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8793 {
8794 state_t dfa_state;
8795 struct bundle_state *curr_state1;
8796 struct bundle_state *allocated_states_chain;
8797
8798 curr_state1 = get_free_bundle_state ();
8799 dfa_state = curr_state1->dfa_state;
8800 allocated_states_chain = curr_state1->allocated_states_chain;
8801 *curr_state1 = *curr_state;
8802 curr_state1->dfa_state = dfa_state;
8803 curr_state1->allocated_states_chain = allocated_states_chain;
8804 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8805 dfa_state_size);
8806 curr_state = curr_state1;
8807 }
8808 if (!try_issue_nops (curr_state,
8809 3 - curr_state->accumulated_insns_num % 3))
8810 return;
8811 curr_state->after_nops_num
8812 = 3 - curr_state->accumulated_insns_num % 3;
8813 curr_state->accumulated_insns_num
8814 += 3 - curr_state->accumulated_insns_num % 3;
8815 }
8816 if (!insert_bundle_state (curr_state))
8817 free_bundle_state (curr_state);
8818 return;
8819 }
8820
8821 /* The following function returns position in the two window bundle
8822 for given STATE. */
8823
8824 static int
8825 get_max_pos (state_t state)
8826 {
8827 if (cpu_unit_reservation_p (state, pos_6))
8828 return 6;
8829 else if (cpu_unit_reservation_p (state, pos_5))
8830 return 5;
8831 else if (cpu_unit_reservation_p (state, pos_4))
8832 return 4;
8833 else if (cpu_unit_reservation_p (state, pos_3))
8834 return 3;
8835 else if (cpu_unit_reservation_p (state, pos_2))
8836 return 2;
8837 else if (cpu_unit_reservation_p (state, pos_1))
8838 return 1;
8839 else
8840 return 0;
8841 }
8842
8843 /* The function returns code of a possible template for given position
8844 and state. The function should be called only with 2 values of
8845 position equal to 3 or 6. We avoid generating F NOPs by putting
8846 templates containing F insns at the end of the template search
8847 because undocumented anomaly in McKinley derived cores which can
8848 cause stalls if an F-unit insn (including a NOP) is issued within a
8849 six-cycle window after reading certain application registers (such
8850 as ar.bsp). Furthermore, power-considerations also argue against
8851 the use of F-unit instructions unless they're really needed. */
8852
8853 static int
8854 get_template (state_t state, int pos)
8855 {
8856 switch (pos)
8857 {
8858 case 3:
8859 if (cpu_unit_reservation_p (state, _0mmi_))
8860 return 1;
8861 else if (cpu_unit_reservation_p (state, _0mii_))
8862 return 0;
8863 else if (cpu_unit_reservation_p (state, _0mmb_))
8864 return 7;
8865 else if (cpu_unit_reservation_p (state, _0mib_))
8866 return 6;
8867 else if (cpu_unit_reservation_p (state, _0mbb_))
8868 return 5;
8869 else if (cpu_unit_reservation_p (state, _0bbb_))
8870 return 4;
8871 else if (cpu_unit_reservation_p (state, _0mmf_))
8872 return 3;
8873 else if (cpu_unit_reservation_p (state, _0mfi_))
8874 return 2;
8875 else if (cpu_unit_reservation_p (state, _0mfb_))
8876 return 8;
8877 else if (cpu_unit_reservation_p (state, _0mlx_))
8878 return 9;
8879 else
8880 gcc_unreachable ();
8881 case 6:
8882 if (cpu_unit_reservation_p (state, _1mmi_))
8883 return 1;
8884 else if (cpu_unit_reservation_p (state, _1mii_))
8885 return 0;
8886 else if (cpu_unit_reservation_p (state, _1mmb_))
8887 return 7;
8888 else if (cpu_unit_reservation_p (state, _1mib_))
8889 return 6;
8890 else if (cpu_unit_reservation_p (state, _1mbb_))
8891 return 5;
8892 else if (cpu_unit_reservation_p (state, _1bbb_))
8893 return 4;
8894 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8895 return 3;
8896 else if (cpu_unit_reservation_p (state, _1mfi_))
8897 return 2;
8898 else if (cpu_unit_reservation_p (state, _1mfb_))
8899 return 8;
8900 else if (cpu_unit_reservation_p (state, _1mlx_))
8901 return 9;
8902 else
8903 gcc_unreachable ();
8904 default:
8905 gcc_unreachable ();
8906 }
8907 }
8908
8909 /* True when INSN is important for bundling. */
8910
8911 static bool
8912 important_for_bundling_p (rtx insn)
8913 {
8914 return (INSN_P (insn)
8915 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8916 && GET_CODE (PATTERN (insn)) != USE
8917 && GET_CODE (PATTERN (insn)) != CLOBBER);
8918 }
8919
8920 /* The following function returns an insn important for insn bundling
8921 followed by INSN and before TAIL. */
8922
8923 static rtx
8924 get_next_important_insn (rtx insn, rtx tail)
8925 {
8926 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8927 if (important_for_bundling_p (insn))
8928 return insn;
8929 return NULL_RTX;
8930 }
8931
8932 /* True when INSN is unknown, but important, for bundling. */
8933
8934 static bool
8935 unknown_for_bundling_p (rtx insn)
8936 {
8937 return (INSN_P (insn)
8938 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN
8939 && GET_CODE (PATTERN (insn)) != USE
8940 && GET_CODE (PATTERN (insn)) != CLOBBER);
8941 }
8942
8943 /* Add a bundle selector TEMPLATE0 before INSN. */
8944
8945 static void
8946 ia64_add_bundle_selector_before (int template0, rtx insn)
8947 {
8948 rtx b = gen_bundle_selector (GEN_INT (template0));
8949
8950 ia64_emit_insn_before (b, insn);
8951 #if NR_BUNDLES == 10
8952 if ((template0 == 4 || template0 == 5)
8953 && ia64_except_unwind_info (&global_options) == UI_TARGET)
8954 {
8955 int i;
8956 rtx note = NULL_RTX;
8957
8958 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8959 first or second slot. If it is and has REG_EH_NOTE set, copy it
8960 to following nops, as br.call sets rp to the address of following
8961 bundle and therefore an EH region end must be on a bundle
8962 boundary. */
8963 insn = PREV_INSN (insn);
8964 for (i = 0; i < 3; i++)
8965 {
8966 do
8967 insn = next_active_insn (insn);
8968 while (NONJUMP_INSN_P (insn)
8969 && get_attr_empty (insn) == EMPTY_YES);
8970 if (CALL_P (insn))
8971 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8972 else if (note)
8973 {
8974 int code;
8975
8976 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8977 || code == CODE_FOR_nop_b);
8978 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8979 note = NULL_RTX;
8980 else
8981 add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
8982 }
8983 }
8984 }
8985 #endif
8986 }
8987
8988 /* The following function does insn bundling. Bundling means
8989 inserting templates and nop insns to fit insn groups into permitted
8990 templates. Instruction scheduling uses NDFA (non-deterministic
8991 finite automata) encoding informations about the templates and the
8992 inserted nops. Nondeterminism of the automata permits follows
8993 all possible insn sequences very fast.
8994
8995 Unfortunately it is not possible to get information about inserting
8996 nop insns and used templates from the automata states. The
8997 automata only says that we can issue an insn possibly inserting
8998 some nops before it and using some template. Therefore insn
8999 bundling in this function is implemented by using DFA
9000 (deterministic finite automata). We follow all possible insn
9001 sequences by inserting 0-2 nops (that is what the NDFA describe for
9002 insn scheduling) before/after each insn being bundled. We know the
9003 start of simulated processor cycle from insn scheduling (insn
9004 starting a new cycle has TImode).
9005
9006 Simple implementation of insn bundling would create enormous
9007 number of possible insn sequences satisfying information about new
9008 cycle ticks taken from the insn scheduling. To make the algorithm
9009 practical we use dynamic programming. Each decision (about
9010 inserting nops and implicitly about previous decisions) is described
9011 by structure bundle_state (see above). If we generate the same
9012 bundle state (key is automaton state after issuing the insns and
9013 nops for it), we reuse already generated one. As consequence we
9014 reject some decisions which cannot improve the solution and
9015 reduce memory for the algorithm.
9016
9017 When we reach the end of EBB (extended basic block), we choose the
9018 best sequence and then, moving back in EBB, insert templates for
9019 the best alternative. The templates are taken from querying
9020 automaton state for each insn in chosen bundle states.
9021
9022 So the algorithm makes two (forward and backward) passes through
9023 EBB. */
9024
9025 static void
9026 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
9027 {
9028 struct bundle_state *curr_state, *next_state, *best_state;
9029 rtx insn, next_insn;
9030 int insn_num;
9031 int i, bundle_end_p, only_bundle_end_p, asm_p;
9032 int pos = 0, max_pos, template0, template1;
9033 rtx b;
9034 rtx nop;
9035 enum attr_type type;
9036
9037 insn_num = 0;
9038 /* Count insns in the EBB. */
9039 for (insn = NEXT_INSN (prev_head_insn);
9040 insn && insn != tail;
9041 insn = NEXT_INSN (insn))
9042 if (INSN_P (insn))
9043 insn_num++;
9044 if (insn_num == 0)
9045 return;
9046 bundling_p = 1;
9047 dfa_clean_insn_cache ();
9048 initiate_bundle_state_table ();
9049 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
9050 /* First (forward) pass -- generation of bundle states. */
9051 curr_state = get_free_bundle_state ();
9052 curr_state->insn = NULL;
9053 curr_state->before_nops_num = 0;
9054 curr_state->after_nops_num = 0;
9055 curr_state->insn_num = 0;
9056 curr_state->cost = 0;
9057 curr_state->accumulated_insns_num = 0;
9058 curr_state->branch_deviation = 0;
9059 curr_state->middle_bundle_stops = 0;
9060 curr_state->next = NULL;
9061 curr_state->originator = NULL;
9062 state_reset (curr_state->dfa_state);
9063 index_to_bundle_states [0] = curr_state;
9064 insn_num = 0;
9065 /* Shift cycle mark if it is put on insn which could be ignored. */
9066 for (insn = NEXT_INSN (prev_head_insn);
9067 insn != tail;
9068 insn = NEXT_INSN (insn))
9069 if (INSN_P (insn)
9070 && !important_for_bundling_p (insn)
9071 && GET_MODE (insn) == TImode)
9072 {
9073 PUT_MODE (insn, VOIDmode);
9074 for (next_insn = NEXT_INSN (insn);
9075 next_insn != tail;
9076 next_insn = NEXT_INSN (next_insn))
9077 if (important_for_bundling_p (next_insn)
9078 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
9079 {
9080 PUT_MODE (next_insn, TImode);
9081 break;
9082 }
9083 }
9084 /* Forward pass: generation of bundle states. */
9085 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
9086 insn != NULL_RTX;
9087 insn = next_insn)
9088 {
9089 gcc_assert (important_for_bundling_p (insn));
9090 type = ia64_safe_type (insn);
9091 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
9092 insn_num++;
9093 index_to_bundle_states [insn_num] = NULL;
9094 for (curr_state = index_to_bundle_states [insn_num - 1];
9095 curr_state != NULL;
9096 curr_state = next_state)
9097 {
9098 pos = curr_state->accumulated_insns_num % 3;
9099 next_state = curr_state->next;
9100 /* We must fill up the current bundle in order to start a
9101 subsequent asm insn in a new bundle. Asm insn is always
9102 placed in a separate bundle. */
9103 only_bundle_end_p
9104 = (next_insn != NULL_RTX
9105 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
9106 && unknown_for_bundling_p (next_insn));
9107 /* We may fill up the current bundle if it is the cycle end
9108 without a group barrier. */
9109 bundle_end_p
9110 = (only_bundle_end_p || next_insn == NULL_RTX
9111 || (GET_MODE (next_insn) == TImode
9112 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
9113 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
9114 || type == TYPE_S)
9115 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
9116 only_bundle_end_p);
9117 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
9118 only_bundle_end_p);
9119 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
9120 only_bundle_end_p);
9121 }
9122 gcc_assert (index_to_bundle_states [insn_num]);
9123 for (curr_state = index_to_bundle_states [insn_num];
9124 curr_state != NULL;
9125 curr_state = curr_state->next)
9126 if (verbose >= 2 && dump)
9127 {
9128 /* This structure is taken from generated code of the
9129 pipeline hazard recognizer (see file insn-attrtab.c).
9130 Please don't forget to change the structure if a new
9131 automaton is added to .md file. */
9132 struct DFA_chip
9133 {
9134 unsigned short one_automaton_state;
9135 unsigned short oneb_automaton_state;
9136 unsigned short two_automaton_state;
9137 unsigned short twob_automaton_state;
9138 };
9139
9140 fprintf
9141 (dump,
9142 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
9143 curr_state->unique_num,
9144 (curr_state->originator == NULL
9145 ? -1 : curr_state->originator->unique_num),
9146 curr_state->cost,
9147 curr_state->before_nops_num, curr_state->after_nops_num,
9148 curr_state->accumulated_insns_num, curr_state->branch_deviation,
9149 curr_state->middle_bundle_stops,
9150 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
9151 INSN_UID (insn));
9152 }
9153 }
9154
9155 /* We should find a solution because the 2nd insn scheduling has
9156 found one. */
9157 gcc_assert (index_to_bundle_states [insn_num]);
9158 /* Find a state corresponding to the best insn sequence. */
9159 best_state = NULL;
9160 for (curr_state = index_to_bundle_states [insn_num];
9161 curr_state != NULL;
9162 curr_state = curr_state->next)
9163 /* We are just looking at the states with fully filled up last
9164 bundle. The first we prefer insn sequences with minimal cost
9165 then with minimal inserted nops and finally with branch insns
9166 placed in the 3rd slots. */
9167 if (curr_state->accumulated_insns_num % 3 == 0
9168 && (best_state == NULL || best_state->cost > curr_state->cost
9169 || (best_state->cost == curr_state->cost
9170 && (curr_state->accumulated_insns_num
9171 < best_state->accumulated_insns_num
9172 || (curr_state->accumulated_insns_num
9173 == best_state->accumulated_insns_num
9174 && (curr_state->branch_deviation
9175 < best_state->branch_deviation
9176 || (curr_state->branch_deviation
9177 == best_state->branch_deviation
9178 && curr_state->middle_bundle_stops
9179 < best_state->middle_bundle_stops)))))))
9180 best_state = curr_state;
9181 /* Second (backward) pass: adding nops and templates. */
9182 gcc_assert (best_state);
9183 insn_num = best_state->before_nops_num;
9184 template0 = template1 = -1;
9185 for (curr_state = best_state;
9186 curr_state->originator != NULL;
9187 curr_state = curr_state->originator)
9188 {
9189 insn = curr_state->insn;
9190 asm_p = unknown_for_bundling_p (insn);
9191 insn_num++;
9192 if (verbose >= 2 && dump)
9193 {
9194 struct DFA_chip
9195 {
9196 unsigned short one_automaton_state;
9197 unsigned short oneb_automaton_state;
9198 unsigned short two_automaton_state;
9199 unsigned short twob_automaton_state;
9200 };
9201
9202 fprintf
9203 (dump,
9204 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
9205 curr_state->unique_num,
9206 (curr_state->originator == NULL
9207 ? -1 : curr_state->originator->unique_num),
9208 curr_state->cost,
9209 curr_state->before_nops_num, curr_state->after_nops_num,
9210 curr_state->accumulated_insns_num, curr_state->branch_deviation,
9211 curr_state->middle_bundle_stops,
9212 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
9213 INSN_UID (insn));
9214 }
9215 /* Find the position in the current bundle window. The window can
9216 contain at most two bundles. Two bundle window means that
9217 the processor will make two bundle rotation. */
9218 max_pos = get_max_pos (curr_state->dfa_state);
9219 if (max_pos == 6
9220 /* The following (negative template number) means that the
9221 processor did one bundle rotation. */
9222 || (max_pos == 3 && template0 < 0))
9223 {
9224 /* We are at the end of the window -- find template(s) for
9225 its bundle(s). */
9226 pos = max_pos;
9227 if (max_pos == 3)
9228 template0 = get_template (curr_state->dfa_state, 3);
9229 else
9230 {
9231 template1 = get_template (curr_state->dfa_state, 3);
9232 template0 = get_template (curr_state->dfa_state, 6);
9233 }
9234 }
9235 if (max_pos > 3 && template1 < 0)
9236 /* It may happen when we have the stop inside a bundle. */
9237 {
9238 gcc_assert (pos <= 3);
9239 template1 = get_template (curr_state->dfa_state, 3);
9240 pos += 3;
9241 }
9242 if (!asm_p)
9243 /* Emit nops after the current insn. */
9244 for (i = 0; i < curr_state->after_nops_num; i++)
9245 {
9246 nop = gen_nop ();
9247 emit_insn_after (nop, insn);
9248 pos--;
9249 gcc_assert (pos >= 0);
9250 if (pos % 3 == 0)
9251 {
9252 /* We are at the start of a bundle: emit the template
9253 (it should be defined). */
9254 gcc_assert (template0 >= 0);
9255 ia64_add_bundle_selector_before (template0, nop);
9256 /* If we have two bundle window, we make one bundle
9257 rotation. Otherwise template0 will be undefined
9258 (negative value). */
9259 template0 = template1;
9260 template1 = -1;
9261 }
9262 }
9263 /* Move the position backward in the window. Group barrier has
9264 no slot. Asm insn takes all bundle. */
9265 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
9266 && !unknown_for_bundling_p (insn))
9267 pos--;
9268 /* Long insn takes 2 slots. */
9269 if (ia64_safe_type (insn) == TYPE_L)
9270 pos--;
9271 gcc_assert (pos >= 0);
9272 if (pos % 3 == 0
9273 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
9274 && !unknown_for_bundling_p (insn))
9275 {
9276 /* The current insn is at the bundle start: emit the
9277 template. */
9278 gcc_assert (template0 >= 0);
9279 ia64_add_bundle_selector_before (template0, insn);
9280 b = PREV_INSN (insn);
9281 insn = b;
9282 /* See comment above in analogous place for emitting nops
9283 after the insn. */
9284 template0 = template1;
9285 template1 = -1;
9286 }
9287 /* Emit nops after the current insn. */
9288 for (i = 0; i < curr_state->before_nops_num; i++)
9289 {
9290 nop = gen_nop ();
9291 ia64_emit_insn_before (nop, insn);
9292 nop = PREV_INSN (insn);
9293 insn = nop;
9294 pos--;
9295 gcc_assert (pos >= 0);
9296 if (pos % 3 == 0)
9297 {
9298 /* See comment above in analogous place for emitting nops
9299 after the insn. */
9300 gcc_assert (template0 >= 0);
9301 ia64_add_bundle_selector_before (template0, insn);
9302 b = PREV_INSN (insn);
9303 insn = b;
9304 template0 = template1;
9305 template1 = -1;
9306 }
9307 }
9308 }
9309
9310 #ifdef ENABLE_CHECKING
9311 {
9312 /* Assert right calculation of middle_bundle_stops. */
9313 int num = best_state->middle_bundle_stops;
9314 bool start_bundle = true, end_bundle = false;
9315
9316 for (insn = NEXT_INSN (prev_head_insn);
9317 insn && insn != tail;
9318 insn = NEXT_INSN (insn))
9319 {
9320 if (!INSN_P (insn))
9321 continue;
9322 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
9323 start_bundle = true;
9324 else
9325 {
9326 rtx next_insn;
9327
9328 for (next_insn = NEXT_INSN (insn);
9329 next_insn && next_insn != tail;
9330 next_insn = NEXT_INSN (next_insn))
9331 if (INSN_P (next_insn)
9332 && (ia64_safe_itanium_class (next_insn)
9333 != ITANIUM_CLASS_IGNORE
9334 || recog_memoized (next_insn)
9335 == CODE_FOR_bundle_selector)
9336 && GET_CODE (PATTERN (next_insn)) != USE
9337 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
9338 break;
9339
9340 end_bundle = next_insn == NULL_RTX
9341 || next_insn == tail
9342 || (INSN_P (next_insn)
9343 && recog_memoized (next_insn)
9344 == CODE_FOR_bundle_selector);
9345 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
9346 && !start_bundle && !end_bundle
9347 && next_insn
9348 && !unknown_for_bundling_p (next_insn))
9349 num--;
9350
9351 start_bundle = false;
9352 }
9353 }
9354
9355 gcc_assert (num == 0);
9356 }
9357 #endif
9358
9359 free (index_to_bundle_states);
9360 finish_bundle_state_table ();
9361 bundling_p = 0;
9362 dfa_clean_insn_cache ();
9363 }
9364
9365 /* The following function is called at the end of scheduling BB or
9366 EBB. After reload, it inserts stop bits and does insn bundling. */
9367
9368 static void
9369 ia64_sched_finish (FILE *dump, int sched_verbose)
9370 {
9371 if (sched_verbose)
9372 fprintf (dump, "// Finishing schedule.\n");
9373 if (!reload_completed)
9374 return;
9375 if (reload_completed)
9376 {
9377 final_emit_insn_group_barriers (dump);
9378 bundling (dump, sched_verbose, current_sched_info->prev_head,
9379 current_sched_info->next_tail);
9380 if (sched_verbose && dump)
9381 fprintf (dump, "// finishing %d-%d\n",
9382 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
9383 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
9384
9385 return;
9386 }
9387 }
9388
9389 /* The following function inserts stop bits in scheduled BB or EBB. */
9390
9391 static void
9392 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
9393 {
9394 rtx insn;
9395 int need_barrier_p = 0;
9396 int seen_good_insn = 0;
9397
9398 init_insn_group_barriers ();
9399
9400 for (insn = NEXT_INSN (current_sched_info->prev_head);
9401 insn != current_sched_info->next_tail;
9402 insn = NEXT_INSN (insn))
9403 {
9404 if (BARRIER_P (insn))
9405 {
9406 rtx last = prev_active_insn (insn);
9407
9408 if (! last)
9409 continue;
9410 if (JUMP_TABLE_DATA_P (last))
9411 last = prev_active_insn (last);
9412 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
9413 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
9414
9415 init_insn_group_barriers ();
9416 seen_good_insn = 0;
9417 need_barrier_p = 0;
9418 }
9419 else if (NONDEBUG_INSN_P (insn))
9420 {
9421 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
9422 {
9423 init_insn_group_barriers ();
9424 seen_good_insn = 0;
9425 need_barrier_p = 0;
9426 }
9427 else if (need_barrier_p || group_barrier_needed (insn)
9428 || (mflag_sched_stop_bits_after_every_cycle
9429 && GET_MODE (insn) == TImode
9430 && seen_good_insn))
9431 {
9432 if (TARGET_EARLY_STOP_BITS)
9433 {
9434 rtx last;
9435
9436 for (last = insn;
9437 last != current_sched_info->prev_head;
9438 last = PREV_INSN (last))
9439 if (INSN_P (last) && GET_MODE (last) == TImode
9440 && stops_p [INSN_UID (last)])
9441 break;
9442 if (last == current_sched_info->prev_head)
9443 last = insn;
9444 last = prev_active_insn (last);
9445 if (last
9446 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
9447 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9448 last);
9449 init_insn_group_barriers ();
9450 for (last = NEXT_INSN (last);
9451 last != insn;
9452 last = NEXT_INSN (last))
9453 if (INSN_P (last))
9454 {
9455 group_barrier_needed (last);
9456 if (recog_memoized (last) >= 0
9457 && important_for_bundling_p (last))
9458 seen_good_insn = 1;
9459 }
9460 }
9461 else
9462 {
9463 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9464 insn);
9465 init_insn_group_barriers ();
9466 seen_good_insn = 0;
9467 }
9468 group_barrier_needed (insn);
9469 if (recog_memoized (insn) >= 0
9470 && important_for_bundling_p (insn))
9471 seen_good_insn = 1;
9472 }
9473 else if (recog_memoized (insn) >= 0
9474 && important_for_bundling_p (insn))
9475 seen_good_insn = 1;
9476 need_barrier_p = (CALL_P (insn) || unknown_for_bundling_p (insn));
9477 }
9478 }
9479 }
9480
9481 \f
9482
9483 /* If the following function returns TRUE, we will use the DFA
9484 insn scheduler. */
9485
9486 static int
9487 ia64_first_cycle_multipass_dfa_lookahead (void)
9488 {
9489 return (reload_completed ? 6 : 4);
9490 }
9491
9492 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9493
9494 static void
9495 ia64_init_dfa_pre_cycle_insn (void)
9496 {
9497 if (temp_dfa_state == NULL)
9498 {
9499 dfa_state_size = state_size ();
9500 temp_dfa_state = xmalloc (dfa_state_size);
9501 prev_cycle_state = xmalloc (dfa_state_size);
9502 }
9503 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
9504 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
9505 recog_memoized (dfa_pre_cycle_insn);
9506 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9507 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
9508 recog_memoized (dfa_stop_insn);
9509 }
9510
9511 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9512 used by the DFA insn scheduler. */
9513
9514 static rtx
9515 ia64_dfa_pre_cycle_insn (void)
9516 {
9517 return dfa_pre_cycle_insn;
9518 }
9519
9520 /* The following function returns TRUE if PRODUCER (of type ilog or
9521 ld) produces address for CONSUMER (of type st or stf). */
9522
9523 int
9524 ia64_st_address_bypass_p (rtx producer, rtx consumer)
9525 {
9526 rtx dest, reg, mem;
9527
9528 gcc_assert (producer && consumer);
9529 dest = ia64_single_set (producer);
9530 gcc_assert (dest);
9531 reg = SET_DEST (dest);
9532 gcc_assert (reg);
9533 if (GET_CODE (reg) == SUBREG)
9534 reg = SUBREG_REG (reg);
9535 gcc_assert (GET_CODE (reg) == REG);
9536
9537 dest = ia64_single_set (consumer);
9538 gcc_assert (dest);
9539 mem = SET_DEST (dest);
9540 gcc_assert (mem && GET_CODE (mem) == MEM);
9541 return reg_mentioned_p (reg, mem);
9542 }
9543
9544 /* The following function returns TRUE if PRODUCER (of type ilog or
9545 ld) produces address for CONSUMER (of type ld or fld). */
9546
9547 int
9548 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
9549 {
9550 rtx dest, src, reg, mem;
9551
9552 gcc_assert (producer && consumer);
9553 dest = ia64_single_set (producer);
9554 gcc_assert (dest);
9555 reg = SET_DEST (dest);
9556 gcc_assert (reg);
9557 if (GET_CODE (reg) == SUBREG)
9558 reg = SUBREG_REG (reg);
9559 gcc_assert (GET_CODE (reg) == REG);
9560
9561 src = ia64_single_set (consumer);
9562 gcc_assert (src);
9563 mem = SET_SRC (src);
9564 gcc_assert (mem);
9565
9566 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9567 mem = XVECEXP (mem, 0, 0);
9568 else if (GET_CODE (mem) == IF_THEN_ELSE)
9569 /* ??? Is this bypass necessary for ld.c? */
9570 {
9571 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9572 mem = XEXP (mem, 1);
9573 }
9574
9575 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9576 mem = XEXP (mem, 0);
9577
9578 if (GET_CODE (mem) == UNSPEC)
9579 {
9580 int c = XINT (mem, 1);
9581
9582 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9583 || c == UNSPEC_LDSA);
9584 mem = XVECEXP (mem, 0, 0);
9585 }
9586
9587 /* Note that LO_SUM is used for GOT loads. */
9588 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9589
9590 return reg_mentioned_p (reg, mem);
9591 }
9592
9593 /* The following function returns TRUE if INSN produces address for a
9594 load/store insn. We will place such insns into M slot because it
9595 decreases its latency time. */
9596
9597 int
9598 ia64_produce_address_p (rtx insn)
9599 {
9600 return insn->call;
9601 }
9602
9603 \f
9604 /* Emit pseudo-ops for the assembler to describe predicate relations.
9605 At present this assumes that we only consider predicate pairs to
9606 be mutex, and that the assembler can deduce proper values from
9607 straight-line code. */
9608
9609 static void
9610 emit_predicate_relation_info (void)
9611 {
9612 basic_block bb;
9613
9614 FOR_EACH_BB_REVERSE (bb)
9615 {
9616 int r;
9617 rtx head = BB_HEAD (bb);
9618
9619 /* We only need such notes at code labels. */
9620 if (! LABEL_P (head))
9621 continue;
9622 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9623 head = NEXT_INSN (head);
9624
9625 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9626 grabbing the entire block of predicate registers. */
9627 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9628 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9629 {
9630 rtx p = gen_rtx_REG (BImode, r);
9631 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
9632 if (head == BB_END (bb))
9633 BB_END (bb) = n;
9634 head = n;
9635 }
9636 }
9637
9638 /* Look for conditional calls that do not return, and protect predicate
9639 relations around them. Otherwise the assembler will assume the call
9640 returns, and complain about uses of call-clobbered predicates after
9641 the call. */
9642 FOR_EACH_BB_REVERSE (bb)
9643 {
9644 rtx insn = BB_HEAD (bb);
9645
9646 while (1)
9647 {
9648 if (CALL_P (insn)
9649 && GET_CODE (PATTERN (insn)) == COND_EXEC
9650 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9651 {
9652 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
9653 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9654 if (BB_HEAD (bb) == insn)
9655 BB_HEAD (bb) = b;
9656 if (BB_END (bb) == insn)
9657 BB_END (bb) = a;
9658 }
9659
9660 if (insn == BB_END (bb))
9661 break;
9662 insn = NEXT_INSN (insn);
9663 }
9664 }
9665 }
9666
9667 /* Perform machine dependent operations on the rtl chain INSNS. */
9668
9669 static void
9670 ia64_reorg (void)
9671 {
9672 /* We are freeing block_for_insn in the toplev to keep compatibility
9673 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9674 compute_bb_for_insn ();
9675
9676 /* If optimizing, we'll have split before scheduling. */
9677 if (optimize == 0)
9678 split_all_insns ();
9679
9680 if (optimize && flag_schedule_insns_after_reload
9681 && dbg_cnt (ia64_sched2))
9682 {
9683 basic_block bb;
9684 timevar_push (TV_SCHED2);
9685 ia64_final_schedule = 1;
9686
9687 /* We can't let modulo-sched prevent us from scheduling any bbs,
9688 since we need the final schedule to produce bundle information. */
9689 FOR_EACH_BB (bb)
9690 bb->flags &= ~BB_DISABLE_SCHEDULE;
9691
9692 initiate_bundle_states ();
9693 ia64_nop = make_insn_raw (gen_nop ());
9694 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
9695 recog_memoized (ia64_nop);
9696 clocks_length = get_max_uid () + 1;
9697 stops_p = XCNEWVEC (char, clocks_length);
9698
9699 if (ia64_tune == PROCESSOR_ITANIUM2)
9700 {
9701 pos_1 = get_cpu_unit_code ("2_1");
9702 pos_2 = get_cpu_unit_code ("2_2");
9703 pos_3 = get_cpu_unit_code ("2_3");
9704 pos_4 = get_cpu_unit_code ("2_4");
9705 pos_5 = get_cpu_unit_code ("2_5");
9706 pos_6 = get_cpu_unit_code ("2_6");
9707 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9708 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9709 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9710 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9711 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9712 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9713 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9714 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9715 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9716 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9717 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9718 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9719 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9720 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9721 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9722 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9723 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9724 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9725 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9726 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9727 }
9728 else
9729 {
9730 pos_1 = get_cpu_unit_code ("1_1");
9731 pos_2 = get_cpu_unit_code ("1_2");
9732 pos_3 = get_cpu_unit_code ("1_3");
9733 pos_4 = get_cpu_unit_code ("1_4");
9734 pos_5 = get_cpu_unit_code ("1_5");
9735 pos_6 = get_cpu_unit_code ("1_6");
9736 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9737 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9738 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9739 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9740 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9741 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9742 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9743 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9744 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9745 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9746 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9747 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9748 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9749 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9750 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9751 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9752 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9753 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9754 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9755 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9756 }
9757
9758 if (flag_selective_scheduling2
9759 && !maybe_skip_selective_scheduling ())
9760 run_selective_scheduling ();
9761 else
9762 schedule_ebbs ();
9763
9764 /* Redo alignment computation, as it might gone wrong. */
9765 compute_alignments ();
9766
9767 /* We cannot reuse this one because it has been corrupted by the
9768 evil glat. */
9769 finish_bundle_states ();
9770 free (stops_p);
9771 stops_p = NULL;
9772 emit_insn_group_barriers (dump_file);
9773
9774 ia64_final_schedule = 0;
9775 timevar_pop (TV_SCHED2);
9776 }
9777 else
9778 emit_all_insn_group_barriers (dump_file);
9779
9780 df_analyze ();
9781
9782 /* A call must not be the last instruction in a function, so that the
9783 return address is still within the function, so that unwinding works
9784 properly. Note that IA-64 differs from dwarf2 on this point. */
9785 if (ia64_except_unwind_info (&global_options) == UI_TARGET)
9786 {
9787 rtx insn;
9788 int saw_stop = 0;
9789
9790 insn = get_last_insn ();
9791 if (! INSN_P (insn))
9792 insn = prev_active_insn (insn);
9793 if (insn)
9794 {
9795 /* Skip over insns that expand to nothing. */
9796 while (NONJUMP_INSN_P (insn)
9797 && get_attr_empty (insn) == EMPTY_YES)
9798 {
9799 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9800 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9801 saw_stop = 1;
9802 insn = prev_active_insn (insn);
9803 }
9804 if (CALL_P (insn))
9805 {
9806 if (! saw_stop)
9807 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9808 emit_insn (gen_break_f ());
9809 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9810 }
9811 }
9812 }
9813
9814 emit_predicate_relation_info ();
9815
9816 if (flag_var_tracking)
9817 {
9818 timevar_push (TV_VAR_TRACKING);
9819 variable_tracking_main ();
9820 timevar_pop (TV_VAR_TRACKING);
9821 }
9822 df_finish_pass (false);
9823 }
9824 \f
9825 /* Return true if REGNO is used by the epilogue. */
9826
9827 int
9828 ia64_epilogue_uses (int regno)
9829 {
9830 switch (regno)
9831 {
9832 case R_GR (1):
9833 /* With a call to a function in another module, we will write a new
9834 value to "gp". After returning from such a call, we need to make
9835 sure the function restores the original gp-value, even if the
9836 function itself does not use the gp anymore. */
9837 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9838
9839 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9840 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9841 /* For functions defined with the syscall_linkage attribute, all
9842 input registers are marked as live at all function exits. This
9843 prevents the register allocator from using the input registers,
9844 which in turn makes it possible to restart a system call after
9845 an interrupt without having to save/restore the input registers.
9846 This also prevents kernel data from leaking to application code. */
9847 return lookup_attribute ("syscall_linkage",
9848 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9849
9850 case R_BR (0):
9851 /* Conditional return patterns can't represent the use of `b0' as
9852 the return address, so we force the value live this way. */
9853 return 1;
9854
9855 case AR_PFS_REGNUM:
9856 /* Likewise for ar.pfs, which is used by br.ret. */
9857 return 1;
9858
9859 default:
9860 return 0;
9861 }
9862 }
9863
9864 /* Return true if REGNO is used by the frame unwinder. */
9865
9866 int
9867 ia64_eh_uses (int regno)
9868 {
9869 unsigned int r;
9870
9871 if (! reload_completed)
9872 return 0;
9873
9874 if (regno == 0)
9875 return 0;
9876
9877 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9878 if (regno == current_frame_info.r[r]
9879 || regno == emitted_frame_related_regs[r])
9880 return 1;
9881
9882 return 0;
9883 }
9884 \f
9885 /* Return true if this goes in small data/bss. */
9886
9887 /* ??? We could also support own long data here. Generating movl/add/ld8
9888 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9889 code faster because there is one less load. This also includes incomplete
9890 types which can't go in sdata/sbss. */
9891
9892 static bool
9893 ia64_in_small_data_p (const_tree exp)
9894 {
9895 if (TARGET_NO_SDATA)
9896 return false;
9897
9898 /* We want to merge strings, so we never consider them small data. */
9899 if (TREE_CODE (exp) == STRING_CST)
9900 return false;
9901
9902 /* Functions are never small data. */
9903 if (TREE_CODE (exp) == FUNCTION_DECL)
9904 return false;
9905
9906 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9907 {
9908 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
9909
9910 if (strcmp (section, ".sdata") == 0
9911 || strncmp (section, ".sdata.", 7) == 0
9912 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9913 || strcmp (section, ".sbss") == 0
9914 || strncmp (section, ".sbss.", 6) == 0
9915 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9916 return true;
9917 }
9918 else
9919 {
9920 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9921
9922 /* If this is an incomplete type with size 0, then we can't put it
9923 in sdata because it might be too big when completed. */
9924 if (size > 0 && size <= ia64_section_threshold)
9925 return true;
9926 }
9927
9928 return false;
9929 }
9930 \f
9931 /* Output assembly directives for prologue regions. */
9932
9933 /* The current basic block number. */
9934
9935 static bool last_block;
9936
9937 /* True if we need a copy_state command at the start of the next block. */
9938
9939 static bool need_copy_state;
9940
9941 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9942 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9943 #endif
9944
9945 /* The function emits unwind directives for the start of an epilogue. */
9946
9947 static void
9948 process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED,
9949 bool unwind, bool frame ATTRIBUTE_UNUSED)
9950 {
9951 /* If this isn't the last block of the function, then we need to label the
9952 current state, and copy it back in at the start of the next block. */
9953
9954 if (!last_block)
9955 {
9956 if (unwind)
9957 fprintf (asm_out_file, "\t.label_state %d\n",
9958 ++cfun->machine->state_num);
9959 need_copy_state = true;
9960 }
9961
9962 if (unwind)
9963 fprintf (asm_out_file, "\t.restore sp\n");
9964 }
9965
9966 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9967
9968 static void
9969 process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
9970 bool unwind, bool frame)
9971 {
9972 rtx dest = SET_DEST (pat);
9973 rtx src = SET_SRC (pat);
9974
9975 if (dest == stack_pointer_rtx)
9976 {
9977 if (GET_CODE (src) == PLUS)
9978 {
9979 rtx op0 = XEXP (src, 0);
9980 rtx op1 = XEXP (src, 1);
9981
9982 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9983
9984 if (INTVAL (op1) < 0)
9985 {
9986 gcc_assert (!frame_pointer_needed);
9987 if (unwind)
9988 fprintf (asm_out_file,
9989 "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9990 -INTVAL (op1));
9991 }
9992 else
9993 process_epilogue (asm_out_file, insn, unwind, frame);
9994 }
9995 else
9996 {
9997 gcc_assert (src == hard_frame_pointer_rtx);
9998 process_epilogue (asm_out_file, insn, unwind, frame);
9999 }
10000 }
10001 else if (dest == hard_frame_pointer_rtx)
10002 {
10003 gcc_assert (src == stack_pointer_rtx);
10004 gcc_assert (frame_pointer_needed);
10005
10006 if (unwind)
10007 fprintf (asm_out_file, "\t.vframe r%d\n",
10008 ia64_dbx_register_number (REGNO (dest)));
10009 }
10010 else
10011 gcc_unreachable ();
10012 }
10013
10014 /* This function processes a SET pattern for REG_CFA_REGISTER. */
10015
10016 static void
10017 process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind)
10018 {
10019 rtx dest = SET_DEST (pat);
10020 rtx src = SET_SRC (pat);
10021 int dest_regno = REGNO (dest);
10022 int src_regno;
10023
10024 if (src == pc_rtx)
10025 {
10026 /* Saving return address pointer. */
10027 if (unwind)
10028 fprintf (asm_out_file, "\t.save rp, r%d\n",
10029 ia64_dbx_register_number (dest_regno));
10030 return;
10031 }
10032
10033 src_regno = REGNO (src);
10034
10035 switch (src_regno)
10036 {
10037 case PR_REG (0):
10038 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
10039 if (unwind)
10040 fprintf (asm_out_file, "\t.save pr, r%d\n",
10041 ia64_dbx_register_number (dest_regno));
10042 break;
10043
10044 case AR_UNAT_REGNUM:
10045 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
10046 if (unwind)
10047 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
10048 ia64_dbx_register_number (dest_regno));
10049 break;
10050
10051 case AR_LC_REGNUM:
10052 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
10053 if (unwind)
10054 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
10055 ia64_dbx_register_number (dest_regno));
10056 break;
10057
10058 default:
10059 /* Everything else should indicate being stored to memory. */
10060 gcc_unreachable ();
10061 }
10062 }
10063
10064 /* This function processes a SET pattern for REG_CFA_OFFSET. */
10065
10066 static void
10067 process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
10068 {
10069 rtx dest = SET_DEST (pat);
10070 rtx src = SET_SRC (pat);
10071 int src_regno = REGNO (src);
10072 const char *saveop;
10073 HOST_WIDE_INT off;
10074 rtx base;
10075
10076 gcc_assert (MEM_P (dest));
10077 if (GET_CODE (XEXP (dest, 0)) == REG)
10078 {
10079 base = XEXP (dest, 0);
10080 off = 0;
10081 }
10082 else
10083 {
10084 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
10085 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
10086 base = XEXP (XEXP (dest, 0), 0);
10087 off = INTVAL (XEXP (XEXP (dest, 0), 1));
10088 }
10089
10090 if (base == hard_frame_pointer_rtx)
10091 {
10092 saveop = ".savepsp";
10093 off = - off;
10094 }
10095 else
10096 {
10097 gcc_assert (base == stack_pointer_rtx);
10098 saveop = ".savesp";
10099 }
10100
10101 src_regno = REGNO (src);
10102 switch (src_regno)
10103 {
10104 case BR_REG (0):
10105 gcc_assert (!current_frame_info.r[reg_save_b0]);
10106 if (unwind)
10107 fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n",
10108 saveop, off);
10109 break;
10110
10111 case PR_REG (0):
10112 gcc_assert (!current_frame_info.r[reg_save_pr]);
10113 if (unwind)
10114 fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n",
10115 saveop, off);
10116 break;
10117
10118 case AR_LC_REGNUM:
10119 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
10120 if (unwind)
10121 fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n",
10122 saveop, off);
10123 break;
10124
10125 case AR_PFS_REGNUM:
10126 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
10127 if (unwind)
10128 fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n",
10129 saveop, off);
10130 break;
10131
10132 case AR_UNAT_REGNUM:
10133 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
10134 if (unwind)
10135 fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n",
10136 saveop, off);
10137 break;
10138
10139 case GR_REG (4):
10140 case GR_REG (5):
10141 case GR_REG (6):
10142 case GR_REG (7):
10143 if (unwind)
10144 fprintf (asm_out_file, "\t.save.g 0x%x\n",
10145 1 << (src_regno - GR_REG (4)));
10146 break;
10147
10148 case BR_REG (1):
10149 case BR_REG (2):
10150 case BR_REG (3):
10151 case BR_REG (4):
10152 case BR_REG (5):
10153 if (unwind)
10154 fprintf (asm_out_file, "\t.save.b 0x%x\n",
10155 1 << (src_regno - BR_REG (1)));
10156 break;
10157
10158 case FR_REG (2):
10159 case FR_REG (3):
10160 case FR_REG (4):
10161 case FR_REG (5):
10162 if (unwind)
10163 fprintf (asm_out_file, "\t.save.f 0x%x\n",
10164 1 << (src_regno - FR_REG (2)));
10165 break;
10166
10167 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
10168 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
10169 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
10170 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
10171 if (unwind)
10172 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
10173 1 << (src_regno - FR_REG (12)));
10174 break;
10175
10176 default:
10177 /* ??? For some reason we mark other general registers, even those
10178 we can't represent in the unwind info. Ignore them. */
10179 break;
10180 }
10181 }
10182
10183 /* This function looks at a single insn and emits any directives
10184 required to unwind this insn. */
10185
10186 static void
10187 ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn)
10188 {
10189 bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET;
10190 bool frame = dwarf2out_do_frame ();
10191 rtx note, pat;
10192 bool handled_one;
10193
10194 if (!unwind && !frame)
10195 return;
10196
10197 if (NOTE_INSN_BASIC_BLOCK_P (insn))
10198 {
10199 last_block = NOTE_BASIC_BLOCK (insn)->next_bb
10200 == EXIT_BLOCK_PTR_FOR_FN (cfun);
10201
10202 /* Restore unwind state from immediately before the epilogue. */
10203 if (need_copy_state)
10204 {
10205 if (unwind)
10206 {
10207 fprintf (asm_out_file, "\t.body\n");
10208 fprintf (asm_out_file, "\t.copy_state %d\n",
10209 cfun->machine->state_num);
10210 }
10211 need_copy_state = false;
10212 }
10213 }
10214
10215 if (NOTE_P (insn) || ! RTX_FRAME_RELATED_P (insn))
10216 return;
10217
10218 /* Look for the ALLOC insn. */
10219 if (INSN_CODE (insn) == CODE_FOR_alloc)
10220 {
10221 rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
10222 int dest_regno = REGNO (dest);
10223
10224 /* If this is the final destination for ar.pfs, then this must
10225 be the alloc in the prologue. */
10226 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
10227 {
10228 if (unwind)
10229 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
10230 ia64_dbx_register_number (dest_regno));
10231 }
10232 else
10233 {
10234 /* This must be an alloc before a sibcall. We must drop the
10235 old frame info. The easiest way to drop the old frame
10236 info is to ensure we had a ".restore sp" directive
10237 followed by a new prologue. If the procedure doesn't
10238 have a memory-stack frame, we'll issue a dummy ".restore
10239 sp" now. */
10240 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
10241 /* if haven't done process_epilogue() yet, do it now */
10242 process_epilogue (asm_out_file, insn, unwind, frame);
10243 if (unwind)
10244 fprintf (asm_out_file, "\t.prologue\n");
10245 }
10246 return;
10247 }
10248
10249 handled_one = false;
10250 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10251 switch (REG_NOTE_KIND (note))
10252 {
10253 case REG_CFA_ADJUST_CFA:
10254 pat = XEXP (note, 0);
10255 if (pat == NULL)
10256 pat = PATTERN (insn);
10257 process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame);
10258 handled_one = true;
10259 break;
10260
10261 case REG_CFA_OFFSET:
10262 pat = XEXP (note, 0);
10263 if (pat == NULL)
10264 pat = PATTERN (insn);
10265 process_cfa_offset (asm_out_file, pat, unwind);
10266 handled_one = true;
10267 break;
10268
10269 case REG_CFA_REGISTER:
10270 pat = XEXP (note, 0);
10271 if (pat == NULL)
10272 pat = PATTERN (insn);
10273 process_cfa_register (asm_out_file, pat, unwind);
10274 handled_one = true;
10275 break;
10276
10277 case REG_FRAME_RELATED_EXPR:
10278 case REG_CFA_DEF_CFA:
10279 case REG_CFA_EXPRESSION:
10280 case REG_CFA_RESTORE:
10281 case REG_CFA_SET_VDRAP:
10282 /* Not used in the ia64 port. */
10283 gcc_unreachable ();
10284
10285 default:
10286 /* Not a frame-related note. */
10287 break;
10288 }
10289
10290 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10291 explicit action to take. No guessing required. */
10292 gcc_assert (handled_one);
10293 }
10294
10295 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10296
10297 static void
10298 ia64_asm_emit_except_personality (rtx personality)
10299 {
10300 fputs ("\t.personality\t", asm_out_file);
10301 output_addr_const (asm_out_file, personality);
10302 fputc ('\n', asm_out_file);
10303 }
10304
10305 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10306
10307 static void
10308 ia64_asm_init_sections (void)
10309 {
10310 exception_section = get_unnamed_section (0, output_section_asm_op,
10311 "\t.handlerdata");
10312 }
10313
10314 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10315
10316 static enum unwind_info_type
10317 ia64_debug_unwind_info (void)
10318 {
10319 return UI_TARGET;
10320 }
10321 \f
10322 enum ia64_builtins
10323 {
10324 IA64_BUILTIN_BSP,
10325 IA64_BUILTIN_COPYSIGNQ,
10326 IA64_BUILTIN_FABSQ,
10327 IA64_BUILTIN_FLUSHRS,
10328 IA64_BUILTIN_INFQ,
10329 IA64_BUILTIN_HUGE_VALQ,
10330 IA64_BUILTIN_max
10331 };
10332
10333 static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max];
10334
10335 void
10336 ia64_init_builtins (void)
10337 {
10338 tree fpreg_type;
10339 tree float80_type;
10340 tree decl;
10341
10342 /* The __fpreg type. */
10343 fpreg_type = make_node (REAL_TYPE);
10344 TYPE_PRECISION (fpreg_type) = 82;
10345 layout_type (fpreg_type);
10346 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
10347
10348 /* The __float80 type. */
10349 float80_type = make_node (REAL_TYPE);
10350 TYPE_PRECISION (float80_type) = 80;
10351 layout_type (float80_type);
10352 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
10353
10354 /* The __float128 type. */
10355 if (!TARGET_HPUX)
10356 {
10357 tree ftype;
10358 tree float128_type = make_node (REAL_TYPE);
10359
10360 TYPE_PRECISION (float128_type) = 128;
10361 layout_type (float128_type);
10362 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
10363
10364 /* TFmode support builtins. */
10365 ftype = build_function_type_list (float128_type, NULL_TREE);
10366 decl = add_builtin_function ("__builtin_infq", ftype,
10367 IA64_BUILTIN_INFQ, BUILT_IN_MD,
10368 NULL, NULL_TREE);
10369 ia64_builtins[IA64_BUILTIN_INFQ] = decl;
10370
10371 decl = add_builtin_function ("__builtin_huge_valq", ftype,
10372 IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
10373 NULL, NULL_TREE);
10374 ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl;
10375
10376 ftype = build_function_type_list (float128_type,
10377 float128_type,
10378 NULL_TREE);
10379 decl = add_builtin_function ("__builtin_fabsq", ftype,
10380 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
10381 "__fabstf2", NULL_TREE);
10382 TREE_READONLY (decl) = 1;
10383 ia64_builtins[IA64_BUILTIN_FABSQ] = decl;
10384
10385 ftype = build_function_type_list (float128_type,
10386 float128_type,
10387 float128_type,
10388 NULL_TREE);
10389 decl = add_builtin_function ("__builtin_copysignq", ftype,
10390 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
10391 "__copysigntf3", NULL_TREE);
10392 TREE_READONLY (decl) = 1;
10393 ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl;
10394 }
10395 else
10396 /* Under HPUX, this is a synonym for "long double". */
10397 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
10398 "__float128");
10399
10400 /* Fwrite on VMS is non-standard. */
10401 #if TARGET_ABI_OPEN_VMS
10402 vms_patch_builtins ();
10403 #endif
10404
10405 #define def_builtin(name, type, code) \
10406 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10407 NULL, NULL_TREE)
10408
10409 decl = def_builtin ("__builtin_ia64_bsp",
10410 build_function_type_list (ptr_type_node, NULL_TREE),
10411 IA64_BUILTIN_BSP);
10412 ia64_builtins[IA64_BUILTIN_BSP] = decl;
10413
10414 decl = def_builtin ("__builtin_ia64_flushrs",
10415 build_function_type_list (void_type_node, NULL_TREE),
10416 IA64_BUILTIN_FLUSHRS);
10417 ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl;
10418
10419 #undef def_builtin
10420
10421 if (TARGET_HPUX)
10422 {
10423 if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE)
10424 set_user_assembler_name (decl, "_Isfinite");
10425 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE)
10426 set_user_assembler_name (decl, "_Isfinitef");
10427 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE)
10428 set_user_assembler_name (decl, "_Isfinitef128");
10429 }
10430 }
10431
10432 rtx
10433 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10434 enum machine_mode mode ATTRIBUTE_UNUSED,
10435 int ignore ATTRIBUTE_UNUSED)
10436 {
10437 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10438 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10439
10440 switch (fcode)
10441 {
10442 case IA64_BUILTIN_BSP:
10443 if (! target || ! register_operand (target, DImode))
10444 target = gen_reg_rtx (DImode);
10445 emit_insn (gen_bsp_value (target));
10446 #ifdef POINTERS_EXTEND_UNSIGNED
10447 target = convert_memory_address (ptr_mode, target);
10448 #endif
10449 return target;
10450
10451 case IA64_BUILTIN_FLUSHRS:
10452 emit_insn (gen_flushrs ());
10453 return const0_rtx;
10454
10455 case IA64_BUILTIN_INFQ:
10456 case IA64_BUILTIN_HUGE_VALQ:
10457 {
10458 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
10459 REAL_VALUE_TYPE inf;
10460 rtx tmp;
10461
10462 real_inf (&inf);
10463 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
10464
10465 tmp = validize_mem (force_const_mem (target_mode, tmp));
10466
10467 if (target == 0)
10468 target = gen_reg_rtx (target_mode);
10469
10470 emit_move_insn (target, tmp);
10471 return target;
10472 }
10473
10474 case IA64_BUILTIN_FABSQ:
10475 case IA64_BUILTIN_COPYSIGNQ:
10476 return expand_call (exp, target, ignore);
10477
10478 default:
10479 gcc_unreachable ();
10480 }
10481
10482 return NULL_RTX;
10483 }
10484
10485 /* Return the ia64 builtin for CODE. */
10486
10487 static tree
10488 ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10489 {
10490 if (code >= IA64_BUILTIN_max)
10491 return error_mark_node;
10492
10493 return ia64_builtins[code];
10494 }
10495
10496 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10497 most significant bits of the stack slot. */
10498
10499 enum direction
10500 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
10501 {
10502 /* Exception to normal case for structures/unions/etc. */
10503
10504 if (type && AGGREGATE_TYPE_P (type)
10505 && int_size_in_bytes (type) < UNITS_PER_WORD)
10506 return upward;
10507
10508 /* Fall back to the default. */
10509 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
10510 }
10511
10512 /* Emit text to declare externally defined variables and functions, because
10513 the Intel assembler does not support undefined externals. */
10514
10515 void
10516 ia64_asm_output_external (FILE *file, tree decl, const char *name)
10517 {
10518 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10519 set in order to avoid putting out names that are never really
10520 used. */
10521 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
10522 {
10523 /* maybe_assemble_visibility will return 1 if the assembler
10524 visibility directive is output. */
10525 int need_visibility = ((*targetm.binds_local_p) (decl)
10526 && maybe_assemble_visibility (decl));
10527
10528 /* GNU as does not need anything here, but the HP linker does
10529 need something for external functions. */
10530 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
10531 && TREE_CODE (decl) == FUNCTION_DECL)
10532 (*targetm.asm_out.globalize_decl_name) (file, decl);
10533 else if (need_visibility && !TARGET_GNU_AS)
10534 (*targetm.asm_out.globalize_label) (file, name);
10535 }
10536 }
10537
10538 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10539 modes of word_mode and larger. Rename the TFmode libfuncs using the
10540 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10541 backward compatibility. */
10542
10543 static void
10544 ia64_init_libfuncs (void)
10545 {
10546 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
10547 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
10548 set_optab_libfunc (smod_optab, SImode, "__modsi3");
10549 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
10550
10551 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
10552 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
10553 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
10554 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
10555 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
10556
10557 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
10558 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
10559 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
10560 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
10561 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
10562 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
10563
10564 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
10565 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10566 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
10567 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
10568 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10569
10570 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
10571 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10572 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
10573 /* HP-UX 11.23 libc does not have a function for unsigned
10574 SImode-to-TFmode conversion. */
10575 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10576 }
10577
10578 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10579
10580 static void
10581 ia64_hpux_init_libfuncs (void)
10582 {
10583 ia64_init_libfuncs ();
10584
10585 /* The HP SI millicode division and mod functions expect DI arguments.
10586 By turning them off completely we avoid using both libgcc and the
10587 non-standard millicode routines and use the HP DI millicode routines
10588 instead. */
10589
10590 set_optab_libfunc (sdiv_optab, SImode, 0);
10591 set_optab_libfunc (udiv_optab, SImode, 0);
10592 set_optab_libfunc (smod_optab, SImode, 0);
10593 set_optab_libfunc (umod_optab, SImode, 0);
10594
10595 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10596 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10597 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10598 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10599
10600 /* HP-UX libc has TF min/max/abs routines in it. */
10601 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10602 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10603 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10604
10605 /* ia64_expand_compare uses this. */
10606 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10607
10608 /* These should never be used. */
10609 set_optab_libfunc (eq_optab, TFmode, 0);
10610 set_optab_libfunc (ne_optab, TFmode, 0);
10611 set_optab_libfunc (gt_optab, TFmode, 0);
10612 set_optab_libfunc (ge_optab, TFmode, 0);
10613 set_optab_libfunc (lt_optab, TFmode, 0);
10614 set_optab_libfunc (le_optab, TFmode, 0);
10615 }
10616
10617 /* Rename the division and modulus functions in VMS. */
10618
10619 static void
10620 ia64_vms_init_libfuncs (void)
10621 {
10622 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10623 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10624 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10625 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10626 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10627 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10628 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10629 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10630 abort_libfunc = init_one_libfunc ("decc$abort");
10631 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10632 #ifdef MEM_LIBFUNCS_INIT
10633 MEM_LIBFUNCS_INIT;
10634 #endif
10635 }
10636
10637 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10638 the HPUX conventions. */
10639
10640 static void
10641 ia64_sysv4_init_libfuncs (void)
10642 {
10643 ia64_init_libfuncs ();
10644
10645 /* These functions are not part of the HPUX TFmode interface. We
10646 use them instead of _U_Qfcmp, which doesn't work the way we
10647 expect. */
10648 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10649 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10650 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10651 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10652 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10653 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10654
10655 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10656 glibc doesn't have them. */
10657 }
10658
10659 /* Use soft-fp. */
10660
10661 static void
10662 ia64_soft_fp_init_libfuncs (void)
10663 {
10664 }
10665
10666 static bool
10667 ia64_vms_valid_pointer_mode (enum machine_mode mode)
10668 {
10669 return (mode == SImode || mode == DImode);
10670 }
10671 \f
10672 /* For HPUX, it is illegal to have relocations in shared segments. */
10673
10674 static int
10675 ia64_hpux_reloc_rw_mask (void)
10676 {
10677 return 3;
10678 }
10679
10680 /* For others, relax this so that relocations to local data goes in
10681 read-only segments, but we still cannot allow global relocations
10682 in read-only segments. */
10683
10684 static int
10685 ia64_reloc_rw_mask (void)
10686 {
10687 return flag_pic ? 3 : 2;
10688 }
10689
10690 /* Return the section to use for X. The only special thing we do here
10691 is to honor small data. */
10692
10693 static section *
10694 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10695 unsigned HOST_WIDE_INT align)
10696 {
10697 if (GET_MODE_SIZE (mode) > 0
10698 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10699 && !TARGET_NO_SDATA)
10700 return sdata_section;
10701 else
10702 return default_elf_select_rtx_section (mode, x, align);
10703 }
10704
10705 static unsigned int
10706 ia64_section_type_flags (tree decl, const char *name, int reloc)
10707 {
10708 unsigned int flags = 0;
10709
10710 if (strcmp (name, ".sdata") == 0
10711 || strncmp (name, ".sdata.", 7) == 0
10712 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10713 || strncmp (name, ".sdata2.", 8) == 0
10714 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10715 || strcmp (name, ".sbss") == 0
10716 || strncmp (name, ".sbss.", 6) == 0
10717 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10718 flags = SECTION_SMALL;
10719
10720 flags |= default_section_type_flags (decl, name, reloc);
10721 return flags;
10722 }
10723
10724 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10725 structure type and that the address of that type should be passed
10726 in out0, rather than in r8. */
10727
10728 static bool
10729 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10730 {
10731 tree ret_type = TREE_TYPE (fntype);
10732
10733 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10734 as the structure return address parameter, if the return value
10735 type has a non-trivial copy constructor or destructor. It is not
10736 clear if this same convention should be used for other
10737 programming languages. Until G++ 3.4, we incorrectly used r8 for
10738 these return values. */
10739 return (abi_version_at_least (2)
10740 && ret_type
10741 && TYPE_MODE (ret_type) == BLKmode
10742 && TREE_ADDRESSABLE (ret_type)
10743 && strcmp (lang_hooks.name, "GNU C++") == 0);
10744 }
10745
10746 /* Output the assembler code for a thunk function. THUNK_DECL is the
10747 declaration for the thunk function itself, FUNCTION is the decl for
10748 the target function. DELTA is an immediate constant offset to be
10749 added to THIS. If VCALL_OFFSET is nonzero, the word at
10750 *(*this + vcall_offset) should be added to THIS. */
10751
10752 static void
10753 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10754 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10755 tree function)
10756 {
10757 rtx this_rtx, insn, funexp;
10758 unsigned int this_parmno;
10759 unsigned int this_regno;
10760 rtx delta_rtx;
10761
10762 reload_completed = 1;
10763 epilogue_completed = 1;
10764
10765 /* Set things up as ia64_expand_prologue might. */
10766 last_scratch_gr_reg = 15;
10767
10768 memset (&current_frame_info, 0, sizeof (current_frame_info));
10769 current_frame_info.spill_cfa_off = -16;
10770 current_frame_info.n_input_regs = 1;
10771 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10772
10773 /* Mark the end of the (empty) prologue. */
10774 emit_note (NOTE_INSN_PROLOGUE_END);
10775
10776 /* Figure out whether "this" will be the first parameter (the
10777 typical case) or the second parameter (as happens when the
10778 virtual function returns certain class objects). */
10779 this_parmno
10780 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10781 ? 1 : 0);
10782 this_regno = IN_REG (this_parmno);
10783 if (!TARGET_REG_NAMES)
10784 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10785
10786 this_rtx = gen_rtx_REG (Pmode, this_regno);
10787
10788 /* Apply the constant offset, if required. */
10789 delta_rtx = GEN_INT (delta);
10790 if (TARGET_ILP32)
10791 {
10792 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10793 REG_POINTER (tmp) = 1;
10794 if (delta && satisfies_constraint_I (delta_rtx))
10795 {
10796 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10797 delta = 0;
10798 }
10799 else
10800 emit_insn (gen_ptr_extend (this_rtx, tmp));
10801 }
10802 if (delta)
10803 {
10804 if (!satisfies_constraint_I (delta_rtx))
10805 {
10806 rtx tmp = gen_rtx_REG (Pmode, 2);
10807 emit_move_insn (tmp, delta_rtx);
10808 delta_rtx = tmp;
10809 }
10810 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10811 }
10812
10813 /* Apply the offset from the vtable, if required. */
10814 if (vcall_offset)
10815 {
10816 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10817 rtx tmp = gen_rtx_REG (Pmode, 2);
10818
10819 if (TARGET_ILP32)
10820 {
10821 rtx t = gen_rtx_REG (ptr_mode, 2);
10822 REG_POINTER (t) = 1;
10823 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10824 if (satisfies_constraint_I (vcall_offset_rtx))
10825 {
10826 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10827 vcall_offset = 0;
10828 }
10829 else
10830 emit_insn (gen_ptr_extend (tmp, t));
10831 }
10832 else
10833 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10834
10835 if (vcall_offset)
10836 {
10837 if (!satisfies_constraint_J (vcall_offset_rtx))
10838 {
10839 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10840 emit_move_insn (tmp2, vcall_offset_rtx);
10841 vcall_offset_rtx = tmp2;
10842 }
10843 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10844 }
10845
10846 if (TARGET_ILP32)
10847 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10848 else
10849 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10850
10851 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10852 }
10853
10854 /* Generate a tail call to the target function. */
10855 if (! TREE_USED (function))
10856 {
10857 assemble_external (function);
10858 TREE_USED (function) = 1;
10859 }
10860 funexp = XEXP (DECL_RTL (function), 0);
10861 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10862 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10863 insn = get_last_insn ();
10864 SIBLING_CALL_P (insn) = 1;
10865
10866 /* Code generation for calls relies on splitting. */
10867 reload_completed = 1;
10868 epilogue_completed = 1;
10869 try_split (PATTERN (insn), insn, 0);
10870
10871 emit_barrier ();
10872
10873 /* Run just enough of rest_of_compilation to get the insns emitted.
10874 There's not really enough bulk here to make other passes such as
10875 instruction scheduling worth while. Note that use_thunk calls
10876 assemble_start_function and assemble_end_function. */
10877
10878 emit_all_insn_group_barriers (NULL);
10879 insn = get_insns ();
10880 shorten_branches (insn);
10881 final_start_function (insn, file, 1);
10882 final (insn, file, 1);
10883 final_end_function ();
10884
10885 reload_completed = 0;
10886 epilogue_completed = 0;
10887 }
10888
10889 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10890
10891 static rtx
10892 ia64_struct_value_rtx (tree fntype,
10893 int incoming ATTRIBUTE_UNUSED)
10894 {
10895 if (TARGET_ABI_OPEN_VMS ||
10896 (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
10897 return NULL_RTX;
10898 return gen_rtx_REG (Pmode, GR_REG (8));
10899 }
10900
10901 static bool
10902 ia64_scalar_mode_supported_p (enum machine_mode mode)
10903 {
10904 switch (mode)
10905 {
10906 case QImode:
10907 case HImode:
10908 case SImode:
10909 case DImode:
10910 case TImode:
10911 return true;
10912
10913 case SFmode:
10914 case DFmode:
10915 case XFmode:
10916 case RFmode:
10917 return true;
10918
10919 case TFmode:
10920 return true;
10921
10922 default:
10923 return false;
10924 }
10925 }
10926
10927 static bool
10928 ia64_vector_mode_supported_p (enum machine_mode mode)
10929 {
10930 switch (mode)
10931 {
10932 case V8QImode:
10933 case V4HImode:
10934 case V2SImode:
10935 return true;
10936
10937 case V2SFmode:
10938 return true;
10939
10940 default:
10941 return false;
10942 }
10943 }
10944
10945 /* Implement the FUNCTION_PROFILER macro. */
10946
10947 void
10948 ia64_output_function_profiler (FILE *file, int labelno)
10949 {
10950 bool indirect_call;
10951
10952 /* If the function needs a static chain and the static chain
10953 register is r15, we use an indirect call so as to bypass
10954 the PLT stub in case the executable is dynamically linked,
10955 because the stub clobbers r15 as per 5.3.6 of the psABI.
10956 We don't need to do that in non canonical PIC mode. */
10957
10958 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10959 {
10960 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10961 indirect_call = true;
10962 }
10963 else
10964 indirect_call = false;
10965
10966 if (TARGET_GNU_AS)
10967 fputs ("\t.prologue 4, r40\n", file);
10968 else
10969 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10970 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10971
10972 if (NO_PROFILE_COUNTERS)
10973 fputs ("\tmov out3 = r0\n", file);
10974 else
10975 {
10976 char buf[20];
10977 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10978
10979 if (TARGET_AUTO_PIC)
10980 fputs ("\tmovl out3 = @gprel(", file);
10981 else
10982 fputs ("\taddl out3 = @ltoff(", file);
10983 assemble_name (file, buf);
10984 if (TARGET_AUTO_PIC)
10985 fputs (")\n", file);
10986 else
10987 fputs ("), r1\n", file);
10988 }
10989
10990 if (indirect_call)
10991 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10992 fputs ("\t;;\n", file);
10993
10994 fputs ("\t.save rp, r42\n", file);
10995 fputs ("\tmov out2 = b0\n", file);
10996 if (indirect_call)
10997 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10998 fputs ("\t.body\n", file);
10999 fputs ("\tmov out1 = r1\n", file);
11000 if (indirect_call)
11001 {
11002 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
11003 fputs ("\tmov b6 = r16\n", file);
11004 fputs ("\tld8 r1 = [r14]\n", file);
11005 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
11006 }
11007 else
11008 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
11009 }
11010
11011 static GTY(()) rtx mcount_func_rtx;
11012 static rtx
11013 gen_mcount_func_rtx (void)
11014 {
11015 if (!mcount_func_rtx)
11016 mcount_func_rtx = init_one_libfunc ("_mcount");
11017 return mcount_func_rtx;
11018 }
11019
11020 void
11021 ia64_profile_hook (int labelno)
11022 {
11023 rtx label, ip;
11024
11025 if (NO_PROFILE_COUNTERS)
11026 label = const0_rtx;
11027 else
11028 {
11029 char buf[30];
11030 const char *label_name;
11031 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
11032 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
11033 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
11034 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
11035 }
11036 ip = gen_reg_rtx (Pmode);
11037 emit_insn (gen_ip_value (ip));
11038 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
11039 VOIDmode, 3,
11040 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
11041 ip, Pmode,
11042 label, Pmode);
11043 }
11044
11045 /* Return the mangling of TYPE if it is an extended fundamental type. */
11046
11047 static const char *
11048 ia64_mangle_type (const_tree type)
11049 {
11050 type = TYPE_MAIN_VARIANT (type);
11051
11052 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
11053 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
11054 return NULL;
11055
11056 /* On HP-UX, "long double" is mangled as "e" so __float128 is
11057 mangled as "e". */
11058 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
11059 return "g";
11060 /* On HP-UX, "e" is not available as a mangling of __float80 so use
11061 an extended mangling. Elsewhere, "e" is available since long
11062 double is 80 bits. */
11063 if (TYPE_MODE (type) == XFmode)
11064 return TARGET_HPUX ? "u9__float80" : "e";
11065 if (TYPE_MODE (type) == RFmode)
11066 return "u7__fpreg";
11067 return NULL;
11068 }
11069
11070 /* Return the diagnostic message string if conversion from FROMTYPE to
11071 TOTYPE is not allowed, NULL otherwise. */
11072 static const char *
11073 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
11074 {
11075 /* Reject nontrivial conversion to or from __fpreg. */
11076 if (TYPE_MODE (fromtype) == RFmode
11077 && TYPE_MODE (totype) != RFmode
11078 && TYPE_MODE (totype) != VOIDmode)
11079 return N_("invalid conversion from %<__fpreg%>");
11080 if (TYPE_MODE (totype) == RFmode
11081 && TYPE_MODE (fromtype) != RFmode)
11082 return N_("invalid conversion to %<__fpreg%>");
11083 return NULL;
11084 }
11085
11086 /* Return the diagnostic message string if the unary operation OP is
11087 not permitted on TYPE, NULL otherwise. */
11088 static const char *
11089 ia64_invalid_unary_op (int op, const_tree type)
11090 {
11091 /* Reject operations on __fpreg other than unary + or &. */
11092 if (TYPE_MODE (type) == RFmode
11093 && op != CONVERT_EXPR
11094 && op != ADDR_EXPR)
11095 return N_("invalid operation on %<__fpreg%>");
11096 return NULL;
11097 }
11098
11099 /* Return the diagnostic message string if the binary operation OP is
11100 not permitted on TYPE1 and TYPE2, NULL otherwise. */
11101 static const char *
11102 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
11103 {
11104 /* Reject operations on __fpreg. */
11105 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
11106 return N_("invalid operation on %<__fpreg%>");
11107 return NULL;
11108 }
11109
11110 /* HP-UX version_id attribute.
11111 For object foo, if the version_id is set to 1234 put out an alias
11112 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
11113 other than an alias statement because it is an illegal symbol name. */
11114
11115 static tree
11116 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
11117 tree name ATTRIBUTE_UNUSED,
11118 tree args,
11119 int flags ATTRIBUTE_UNUSED,
11120 bool *no_add_attrs)
11121 {
11122 tree arg = TREE_VALUE (args);
11123
11124 if (TREE_CODE (arg) != STRING_CST)
11125 {
11126 error("version attribute is not a string");
11127 *no_add_attrs = true;
11128 return NULL_TREE;
11129 }
11130 return NULL_TREE;
11131 }
11132
11133 /* Target hook for c_mode_for_suffix. */
11134
11135 static enum machine_mode
11136 ia64_c_mode_for_suffix (char suffix)
11137 {
11138 if (suffix == 'q')
11139 return TFmode;
11140 if (suffix == 'w')
11141 return XFmode;
11142
11143 return VOIDmode;
11144 }
11145
11146 static GTY(()) rtx ia64_dconst_0_5_rtx;
11147
11148 rtx
11149 ia64_dconst_0_5 (void)
11150 {
11151 if (! ia64_dconst_0_5_rtx)
11152 {
11153 REAL_VALUE_TYPE rv;
11154 real_from_string (&rv, "0.5");
11155 ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
11156 }
11157 return ia64_dconst_0_5_rtx;
11158 }
11159
11160 static GTY(()) rtx ia64_dconst_0_375_rtx;
11161
11162 rtx
11163 ia64_dconst_0_375 (void)
11164 {
11165 if (! ia64_dconst_0_375_rtx)
11166 {
11167 REAL_VALUE_TYPE rv;
11168 real_from_string (&rv, "0.375");
11169 ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
11170 }
11171 return ia64_dconst_0_375_rtx;
11172 }
11173
11174 static enum machine_mode
11175 ia64_get_reg_raw_mode (int regno)
11176 {
11177 if (FR_REGNO_P (regno))
11178 return XFmode;
11179 return default_get_reg_raw_mode(regno);
11180 }
11181
11182 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed
11183 anymore. */
11184
11185 bool
11186 ia64_member_type_forces_blk (const_tree, enum machine_mode mode)
11187 {
11188 return TARGET_HPUX && mode == TFmode;
11189 }
11190
11191 /* Always default to .text section until HP-UX linker is fixed. */
11192
11193 ATTRIBUTE_UNUSED static section *
11194 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED,
11195 enum node_frequency freq ATTRIBUTE_UNUSED,
11196 bool startup ATTRIBUTE_UNUSED,
11197 bool exit ATTRIBUTE_UNUSED)
11198 {
11199 return NULL;
11200 }
11201 \f
11202 /* Construct (set target (vec_select op0 (parallel perm))) and
11203 return true if that's a valid instruction in the active ISA. */
11204
11205 static bool
11206 expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt)
11207 {
11208 rtx rperm[MAX_VECT_LEN], x;
11209 unsigned i;
11210
11211 for (i = 0; i < nelt; ++i)
11212 rperm[i] = GEN_INT (perm[i]);
11213
11214 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
11215 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
11216 x = gen_rtx_SET (VOIDmode, target, x);
11217
11218 x = emit_insn (x);
11219 if (recog_memoized (x) < 0)
11220 {
11221 remove_insn (x);
11222 return false;
11223 }
11224 return true;
11225 }
11226
11227 /* Similar, but generate a vec_concat from op0 and op1 as well. */
11228
11229 static bool
11230 expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
11231 const unsigned char *perm, unsigned nelt)
11232 {
11233 enum machine_mode v2mode;
11234 rtx x;
11235
11236 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
11237 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
11238 return expand_vselect (target, x, perm, nelt);
11239 }
11240
11241 /* Try to expand a no-op permutation. */
11242
11243 static bool
11244 expand_vec_perm_identity (struct expand_vec_perm_d *d)
11245 {
11246 unsigned i, nelt = d->nelt;
11247
11248 for (i = 0; i < nelt; ++i)
11249 if (d->perm[i] != i)
11250 return false;
11251
11252 if (!d->testing_p)
11253 emit_move_insn (d->target, d->op0);
11254
11255 return true;
11256 }
11257
11258 /* Try to expand D via a shrp instruction. */
11259
11260 static bool
11261 expand_vec_perm_shrp (struct expand_vec_perm_d *d)
11262 {
11263 unsigned i, nelt = d->nelt, shift, mask;
11264 rtx tmp, hi, lo;
11265
11266 /* ??? Don't force V2SFmode into the integer registers. */
11267 if (d->vmode == V2SFmode)
11268 return false;
11269
11270 mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1);
11271
11272 shift = d->perm[0];
11273 if (BYTES_BIG_ENDIAN && shift > nelt)
11274 return false;
11275
11276 for (i = 1; i < nelt; ++i)
11277 if (d->perm[i] != ((shift + i) & mask))
11278 return false;
11279
11280 if (d->testing_p)
11281 return true;
11282
11283 hi = shift < nelt ? d->op1 : d->op0;
11284 lo = shift < nelt ? d->op0 : d->op1;
11285
11286 shift %= nelt;
11287
11288 shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT;
11289
11290 /* We've eliminated the shift 0 case via expand_vec_perm_identity. */
11291 gcc_assert (IN_RANGE (shift, 1, 63));
11292
11293 /* Recall that big-endian elements are numbered starting at the top of
11294 the register. Ideally we'd have a shift-left-pair. But since we
11295 don't, convert to a shift the other direction. */
11296 if (BYTES_BIG_ENDIAN)
11297 shift = 64 - shift;
11298
11299 tmp = gen_reg_rtx (DImode);
11300 hi = gen_lowpart (DImode, hi);
11301 lo = gen_lowpart (DImode, lo);
11302 emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift)));
11303
11304 emit_move_insn (d->target, gen_lowpart (d->vmode, tmp));
11305 return true;
11306 }
11307
11308 /* Try to instantiate D in a single instruction. */
11309
11310 static bool
11311 expand_vec_perm_1 (struct expand_vec_perm_d *d)
11312 {
11313 unsigned i, nelt = d->nelt;
11314 unsigned char perm2[MAX_VECT_LEN];
11315
11316 /* Try single-operand selections. */
11317 if (d->one_operand_p)
11318 {
11319 if (expand_vec_perm_identity (d))
11320 return true;
11321 if (expand_vselect (d->target, d->op0, d->perm, nelt))
11322 return true;
11323 }
11324
11325 /* Try two operand selections. */
11326 if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt))
11327 return true;
11328
11329 /* Recognize interleave style patterns with reversed operands. */
11330 if (!d->one_operand_p)
11331 {
11332 for (i = 0; i < nelt; ++i)
11333 {
11334 unsigned e = d->perm[i];
11335 if (e >= nelt)
11336 e -= nelt;
11337 else
11338 e += nelt;
11339 perm2[i] = e;
11340 }
11341
11342 if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
11343 return true;
11344 }
11345
11346 if (expand_vec_perm_shrp (d))
11347 return true;
11348
11349 /* ??? Look for deposit-like permutations where most of the result
11350 comes from one vector unchanged and the rest comes from a
11351 sequential hunk of the other vector. */
11352
11353 return false;
11354 }
11355
11356 /* Pattern match broadcast permutations. */
11357
11358 static bool
11359 expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
11360 {
11361 unsigned i, elt, nelt = d->nelt;
11362 unsigned char perm2[2];
11363 rtx temp;
11364 bool ok;
11365
11366 if (!d->one_operand_p)
11367 return false;
11368
11369 elt = d->perm[0];
11370 for (i = 1; i < nelt; ++i)
11371 if (d->perm[i] != elt)
11372 return false;
11373
11374 switch (d->vmode)
11375 {
11376 case V2SImode:
11377 case V2SFmode:
11378 /* Implementable by interleave. */
11379 perm2[0] = elt;
11380 perm2[1] = elt + 2;
11381 ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2);
11382 gcc_assert (ok);
11383 break;
11384
11385 case V8QImode:
11386 /* Implementable by extract + broadcast. */
11387 if (BYTES_BIG_ENDIAN)
11388 elt = 7 - elt;
11389 elt *= BITS_PER_UNIT;
11390 temp = gen_reg_rtx (DImode);
11391 emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0),
11392 GEN_INT (8), GEN_INT (elt)));
11393 emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp)));
11394 break;
11395
11396 case V4HImode:
11397 /* Should have been matched directly by vec_select. */
11398 default:
11399 gcc_unreachable ();
11400 }
11401
11402 return true;
11403 }
11404
11405 /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a
11406 two vector permutation into a single vector permutation by using
11407 an interleave operation to merge the vectors. */
11408
11409 static bool
11410 expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d)
11411 {
11412 struct expand_vec_perm_d dremap, dfinal;
11413 unsigned char remap[2 * MAX_VECT_LEN];
11414 unsigned contents, i, nelt, nelt2;
11415 unsigned h0, h1, h2, h3;
11416 rtx seq;
11417 bool ok;
11418
11419 if (d->one_operand_p)
11420 return false;
11421
11422 nelt = d->nelt;
11423 nelt2 = nelt / 2;
11424
11425 /* Examine from whence the elements come. */
11426 contents = 0;
11427 for (i = 0; i < nelt; ++i)
11428 contents |= 1u << d->perm[i];
11429
11430 memset (remap, 0xff, sizeof (remap));
11431 dremap = *d;
11432
11433 h0 = (1u << nelt2) - 1;
11434 h1 = h0 << nelt2;
11435 h2 = h0 << nelt;
11436 h3 = h0 << (nelt + nelt2);
11437
11438 if ((contents & (h0 | h2)) == contents) /* punpck even halves */
11439 {
11440 for (i = 0; i < nelt; ++i)
11441 {
11442 unsigned which = i / 2 + (i & 1 ? nelt : 0);
11443 remap[which] = i;
11444 dremap.perm[i] = which;
11445 }
11446 }
11447 else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */
11448 {
11449 for (i = 0; i < nelt; ++i)
11450 {
11451 unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0);
11452 remap[which] = i;
11453 dremap.perm[i] = which;
11454 }
11455 }
11456 else if ((contents & 0x5555) == contents) /* mix even elements */
11457 {
11458 for (i = 0; i < nelt; ++i)
11459 {
11460 unsigned which = (i & ~1) + (i & 1 ? nelt : 0);
11461 remap[which] = i;
11462 dremap.perm[i] = which;
11463 }
11464 }
11465 else if ((contents & 0xaaaa) == contents) /* mix odd elements */
11466 {
11467 for (i = 0; i < nelt; ++i)
11468 {
11469 unsigned which = (i | 1) + (i & 1 ? nelt : 0);
11470 remap[which] = i;
11471 dremap.perm[i] = which;
11472 }
11473 }
11474 else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */
11475 {
11476 unsigned shift = ctz_hwi (contents);
11477 for (i = 0; i < nelt; ++i)
11478 {
11479 unsigned which = (i + shift) & (2 * nelt - 1);
11480 remap[which] = i;
11481 dremap.perm[i] = which;
11482 }
11483 }
11484 else
11485 return false;
11486
11487 /* Use the remapping array set up above to move the elements from their
11488 swizzled locations into their final destinations. */
11489 dfinal = *d;
11490 for (i = 0; i < nelt; ++i)
11491 {
11492 unsigned e = remap[d->perm[i]];
11493 gcc_assert (e < nelt);
11494 dfinal.perm[i] = e;
11495 }
11496 dfinal.op0 = gen_reg_rtx (dfinal.vmode);
11497 dfinal.op1 = dfinal.op0;
11498 dfinal.one_operand_p = true;
11499 dremap.target = dfinal.op0;
11500
11501 /* Test if the final remap can be done with a single insn. For V4HImode
11502 this *will* succeed. For V8QImode or V2SImode it may not. */
11503 start_sequence ();
11504 ok = expand_vec_perm_1 (&dfinal);
11505 seq = get_insns ();
11506 end_sequence ();
11507 if (!ok)
11508 return false;
11509 if (d->testing_p)
11510 return true;
11511
11512 ok = expand_vec_perm_1 (&dremap);
11513 gcc_assert (ok);
11514
11515 emit_insn (seq);
11516 return true;
11517 }
11518
11519 /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode
11520 constant permutation via two mux2 and a merge. */
11521
11522 static bool
11523 expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d)
11524 {
11525 unsigned char perm2[4];
11526 rtx rmask[4];
11527 unsigned i;
11528 rtx t0, t1, mask, x;
11529 bool ok;
11530
11531 if (d->vmode != V4HImode || d->one_operand_p)
11532 return false;
11533 if (d->testing_p)
11534 return true;
11535
11536 for (i = 0; i < 4; ++i)
11537 {
11538 perm2[i] = d->perm[i] & 3;
11539 rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx);
11540 }
11541 mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask));
11542 mask = force_reg (V4HImode, mask);
11543
11544 t0 = gen_reg_rtx (V4HImode);
11545 t1 = gen_reg_rtx (V4HImode);
11546
11547 ok = expand_vselect (t0, d->op0, perm2, 4);
11548 gcc_assert (ok);
11549 ok = expand_vselect (t1, d->op1, perm2, 4);
11550 gcc_assert (ok);
11551
11552 x = gen_rtx_AND (V4HImode, mask, t0);
11553 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
11554
11555 x = gen_rtx_NOT (V4HImode, mask);
11556 x = gen_rtx_AND (V4HImode, x, t1);
11557 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
11558
11559 x = gen_rtx_IOR (V4HImode, t0, t1);
11560 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
11561
11562 return true;
11563 }
11564
11565 /* The guts of ia64_expand_vec_perm_const, also used by the ok hook.
11566 With all of the interface bits taken care of, perform the expansion
11567 in D and return true on success. */
11568
11569 static bool
11570 ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
11571 {
11572 if (expand_vec_perm_1 (d))
11573 return true;
11574 if (expand_vec_perm_broadcast (d))
11575 return true;
11576 if (expand_vec_perm_interleave_2 (d))
11577 return true;
11578 if (expand_vec_perm_v4hi_5 (d))
11579 return true;
11580 return false;
11581 }
11582
11583 bool
11584 ia64_expand_vec_perm_const (rtx operands[4])
11585 {
11586 struct expand_vec_perm_d d;
11587 unsigned char perm[MAX_VECT_LEN];
11588 int i, nelt, which;
11589 rtx sel;
11590
11591 d.target = operands[0];
11592 d.op0 = operands[1];
11593 d.op1 = operands[2];
11594 sel = operands[3];
11595
11596 d.vmode = GET_MODE (d.target);
11597 gcc_assert (VECTOR_MODE_P (d.vmode));
11598 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
11599 d.testing_p = false;
11600
11601 gcc_assert (GET_CODE (sel) == CONST_VECTOR);
11602 gcc_assert (XVECLEN (sel, 0) == nelt);
11603 gcc_checking_assert (sizeof (d.perm) == sizeof (perm));
11604
11605 for (i = which = 0; i < nelt; ++i)
11606 {
11607 rtx e = XVECEXP (sel, 0, i);
11608 int ei = INTVAL (e) & (2 * nelt - 1);
11609
11610 which |= (ei < nelt ? 1 : 2);
11611 d.perm[i] = ei;
11612 perm[i] = ei;
11613 }
11614
11615 switch (which)
11616 {
11617 default:
11618 gcc_unreachable();
11619
11620 case 3:
11621 if (!rtx_equal_p (d.op0, d.op1))
11622 {
11623 d.one_operand_p = false;
11624 break;
11625 }
11626
11627 /* The elements of PERM do not suggest that only the first operand
11628 is used, but both operands are identical. Allow easier matching
11629 of the permutation by folding the permutation into the single
11630 input vector. */
11631 for (i = 0; i < nelt; ++i)
11632 if (d.perm[i] >= nelt)
11633 d.perm[i] -= nelt;
11634 /* FALLTHRU */
11635
11636 case 1:
11637 d.op1 = d.op0;
11638 d.one_operand_p = true;
11639 break;
11640
11641 case 2:
11642 for (i = 0; i < nelt; ++i)
11643 d.perm[i] -= nelt;
11644 d.op0 = d.op1;
11645 d.one_operand_p = true;
11646 break;
11647 }
11648
11649 if (ia64_expand_vec_perm_const_1 (&d))
11650 return true;
11651
11652 /* If the mask says both arguments are needed, but they are the same,
11653 the above tried to expand with one_operand_p true. If that didn't
11654 work, retry with one_operand_p false, as that's what we used in _ok. */
11655 if (which == 3 && d.one_operand_p)
11656 {
11657 memcpy (d.perm, perm, sizeof (perm));
11658 d.one_operand_p = false;
11659 return ia64_expand_vec_perm_const_1 (&d);
11660 }
11661
11662 return false;
11663 }
11664
11665 /* Implement targetm.vectorize.vec_perm_const_ok. */
11666
11667 static bool
11668 ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
11669 const unsigned char *sel)
11670 {
11671 struct expand_vec_perm_d d;
11672 unsigned int i, nelt, which;
11673 bool ret;
11674
11675 d.vmode = vmode;
11676 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
11677 d.testing_p = true;
11678
11679 /* Extract the values from the vector CST into the permutation
11680 array in D. */
11681 memcpy (d.perm, sel, nelt);
11682 for (i = which = 0; i < nelt; ++i)
11683 {
11684 unsigned char e = d.perm[i];
11685 gcc_assert (e < 2 * nelt);
11686 which |= (e < nelt ? 1 : 2);
11687 }
11688
11689 /* For all elements from second vector, fold the elements to first. */
11690 if (which == 2)
11691 for (i = 0; i < nelt; ++i)
11692 d.perm[i] -= nelt;
11693
11694 /* Check whether the mask can be applied to the vector type. */
11695 d.one_operand_p = (which != 3);
11696
11697 /* Otherwise we have to go through the motions and see if we can
11698 figure out how to generate the requested permutation. */
11699 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
11700 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
11701 if (!d.one_operand_p)
11702 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
11703
11704 start_sequence ();
11705 ret = ia64_expand_vec_perm_const_1 (&d);
11706 end_sequence ();
11707
11708 return ret;
11709 }
11710
11711 void
11712 ia64_expand_vec_setv2sf (rtx operands[3])
11713 {
11714 struct expand_vec_perm_d d;
11715 unsigned int which;
11716 bool ok;
11717
11718 d.target = operands[0];
11719 d.op0 = operands[0];
11720 d.op1 = gen_reg_rtx (V2SFmode);
11721 d.vmode = V2SFmode;
11722 d.nelt = 2;
11723 d.one_operand_p = false;
11724 d.testing_p = false;
11725
11726 which = INTVAL (operands[2]);
11727 gcc_assert (which <= 1);
11728 d.perm[0] = 1 - which;
11729 d.perm[1] = which + 2;
11730
11731 emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode)));
11732
11733 ok = ia64_expand_vec_perm_const_1 (&d);
11734 gcc_assert (ok);
11735 }
11736
11737 void
11738 ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd)
11739 {
11740 struct expand_vec_perm_d d;
11741 enum machine_mode vmode = GET_MODE (target);
11742 unsigned int i, nelt = GET_MODE_NUNITS (vmode);
11743 bool ok;
11744
11745 d.target = target;
11746 d.op0 = op0;
11747 d.op1 = op1;
11748 d.vmode = vmode;
11749 d.nelt = nelt;
11750 d.one_operand_p = false;
11751 d.testing_p = false;
11752
11753 for (i = 0; i < nelt; ++i)
11754 d.perm[i] = i * 2 + odd;
11755
11756 ok = ia64_expand_vec_perm_const_1 (&d);
11757 gcc_assert (ok);
11758 }
11759
11760 #include "gt-ia64.h"