1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26 ;; reload. This will be fixed once scheduling support is turned on.
28 ;; ??? Optimize for post-increment addressing modes.
30 ;; ??? fselect is not supported, because there is no integer register
33 ;; ??? fp abs/min/max instructions may also work for integer values.
35 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36 ;; it assumes the operand is a register and takes REGNO of it without checking.
38 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39 ;; it assumes the operand is a register and takes REGNO of it without checking.
41 ;; ??? Go through list of documented named patterns and look for more to
44 ;; ??? Go through instruction manual and look for more instructions that
47 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
49 ;; ??? Need a better way to describe alternate fp status registers.
53 (UNSPEC_LTOFF_DTPMOD 0)
54 (UNSPEC_LTOFF_DTPREL 1)
56 (UNSPEC_LTOFF_TPREL 3)
61 (UNSPEC_GR_RESTORE 11)
63 (UNSPEC_FR_RESTORE 13)
64 (UNSPEC_FR_RECIP_APPROX 14)
65 (UNSPEC_PRED_REL_MUTEX 15)
69 (UNSPEC_CMPXCHG_ACQ 19)
70 (UNSPEC_FETCHADD_ACQ 20)
73 (UNSPEC_BUNDLE_SELECTOR 23)
75 (UNSPEC_PROLOGUE_USE 25)
82 (UNSPECV_INSN_GROUP_BARRIER 2)
85 (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls
86 (UNSPECV_PSAC_NORMAL 6)
87 (UNSPECV_SETJMP_RECEIVER 7)
90 ;; ::::::::::::::::::::
94 ;; ::::::::::::::::::::
96 ;; Processor type. This attribute must exactly match the processor_type
97 ;; enumeration in ia64.h.
98 (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune")))
100 ;; Instruction type. This primarily determines how instructions can be
101 ;; packed in bundles, and secondarily affects scheduling to function units.
103 ;; A alu, can go in I or M syllable of a bundle
108 ;; L long immediate, takes two syllables
111 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
112 ;; check this in md_reorg? Currently use unknown for patterns which emit
113 ;; multiple instructions, patterns which emit 0 instructions, and patterns
114 ;; which emit instruction that can go in any slot (e.g. nop).
116 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
117 fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
118 chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
119 syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
120 nop_i,nop_m,nop_x,lfetch,pre_cycle"
121 (const_string "unknown"))
123 ;; chk_s has an I and an M form; use type A for convenience.
124 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
125 (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
126 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
127 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
128 (eq_attr "itanium_class" "lfetch") (const_string "M")
129 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
130 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
131 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
132 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
133 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
134 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
135 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
136 (eq_attr "itanium_class" "stop_bit") (const_string "S")
137 (eq_attr "itanium_class" "nop_x") (const_string "X")
138 (eq_attr "itanium_class" "long_i") (const_string "L")]
139 (const_string "unknown")))
141 (define_attr "itanium_requires_unit0" "no,yes"
142 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
143 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
144 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
145 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
146 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
147 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
148 (const_string "no")))
150 ;; Predication. True iff this instruction can be predicated.
152 (define_attr "predicable" "no,yes" (const_string "yes"))
156 ;; DFA descriptions of ia64 processors used for insn scheduling and
159 (automata_option "ndfa")
161 ;; Uncomment the following line to output automata for debugging.
162 ;; (automata_option "v")
164 (automata_option "w")
166 ;;(automata_option "no-minimization")
169 (include "itanium1.md")
170 (include "itanium2.md")
173 ;; ::::::::::::::::::::
177 ;; ::::::::::::::::::::
179 ;; Set of a single predicate register. This is only used to implement
180 ;; pr-to-pr move and complement.
182 (define_insn "*movcci"
183 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
184 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
187 cmp.ne %0, p0 = r0, r0
188 cmp.eq %0, p0 = r0, r0
189 (%1) cmp.eq.unc %0, p0 = r0, r0"
190 [(set_attr "itanium_class" "icmp")
191 (set_attr "predicable" "no")])
194 [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
195 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
198 cmp.ne %0, %I0 = r0, r0
199 cmp.eq %0, %I0 = r0, r0
202 tbit.nz %0, %I0 = %1, 0
207 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
210 [(set (match_operand:BI 0 "register_operand" "")
211 (match_operand:BI 1 "register_operand" ""))]
213 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
214 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
215 [(cond_exec (ne (match_dup 1) (const_int 0))
216 (set (match_dup 0) (const_int 1)))
217 (cond_exec (eq (match_dup 1) (const_int 0))
218 (set (match_dup 0) (const_int 0)))]
222 [(set (match_operand:BI 0 "register_operand" "")
223 (match_operand:BI 1 "register_operand" ""))]
225 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
226 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
227 [(set (match_dup 2) (match_dup 4))
228 (set (match_dup 3) (match_dup 5))
229 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
230 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
231 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
232 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
233 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
235 (define_expand "movqi"
236 [(set (match_operand:QI 0 "general_operand" "")
237 (match_operand:QI 1 "general_operand" ""))]
240 rtx op1 = ia64_expand_move (operands[0], operands[1]);
246 (define_insn "*movqi_internal"
247 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
248 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
249 "ia64_move_ok (operands[0], operands[1])"
258 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
260 (define_expand "movhi"
261 [(set (match_operand:HI 0 "general_operand" "")
262 (match_operand:HI 1 "general_operand" ""))]
265 rtx op1 = ia64_expand_move (operands[0], operands[1]);
271 (define_insn "*movhi_internal"
272 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
273 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
274 "ia64_move_ok (operands[0], operands[1])"
283 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
285 (define_expand "movsi"
286 [(set (match_operand:SI 0 "general_operand" "")
287 (match_operand:SI 1 "general_operand" ""))]
290 rtx op1 = ia64_expand_move (operands[0], operands[1]);
296 (define_insn "*movsi_internal"
297 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
298 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
299 "ia64_move_ok (operands[0], operands[1])"
311 ;; frar_m, toar_m ??? why not frar_i and toar_i
312 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
314 (define_expand "movdi"
315 [(set (match_operand:DI 0 "general_operand" "")
316 (match_operand:DI 1 "general_operand" ""))]
319 rtx op1 = ia64_expand_move (operands[0], operands[1]);
325 (define_insn "*movdi_internal"
326 [(set (match_operand:DI 0 "destination_operand"
327 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
328 (match_operand:DI 1 "move_operand"
329 "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
330 "ia64_move_ok (operands[0], operands[1])"
332 static const char * const alt[] = {
334 "%,addl %0 = %1, r0",
336 "%,ld8%O1 %0 = %1%P1",
337 "%,st8%Q0 %0 = %r1%P0",
338 "%,getf.sig %0 = %1",
339 "%,setf.sig %0 = %r1",
353 if (which_alternative == 2 && ! TARGET_NO_PIC
354 && symbolic_operand (operands[1], VOIDmode))
357 return alt[which_alternative];
359 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
362 [(set (match_operand 0 "register_operand" "")
363 (match_operand 1 "symbolic_operand" ""))]
364 "reload_completed && ! TARGET_NO_PIC"
367 ia64_expand_load_address (operands[0], operands[1]);
371 (define_expand "load_fptr"
373 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "")))
374 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
377 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
378 operands[3] = gen_rtx_MEM (DImode, operands[2]);
379 RTX_UNCHANGING_P (operands[3]) = 1;
382 (define_insn "*load_fptr_internal1"
383 [(set (match_operand:DI 0 "register_operand" "=r")
384 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
386 "addl %0 = @ltoff(@fptr(%1)), gp"
387 [(set_attr "itanium_class" "ialu")])
389 (define_insn "load_gprel"
390 [(set (match_operand:DI 0 "register_operand" "=r")
391 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
393 "addl %0 = @gprel(%1), gp"
394 [(set_attr "itanium_class" "ialu")])
396 (define_insn "gprel64_offset"
397 [(set (match_operand:DI 0 "register_operand" "=r")
398 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
400 "movl %0 = @gprel(%1)"
401 [(set_attr "itanium_class" "long_i")])
403 (define_expand "load_gprel64"
405 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3)))
406 (set (match_operand:DI 0 "register_operand" "")
407 (plus:DI (match_dup 3) (match_dup 2)))]
410 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
411 operands[3] = pic_offset_table_rtx;
414 ;; This is used as a placeholder for the return address during early
415 ;; compilation. We won't know where we've placed this until during
416 ;; reload, at which point it can wind up in b0, a general register,
417 ;; or memory. The only safe destination under these conditions is a
420 (define_insn_and_split "*movdi_ret_addr"
421 [(set (match_operand:DI 0 "register_operand" "=r")
422 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
428 ia64_split_return_addr_rtx (operands[0]);
431 [(set_attr "itanium_class" "ialu")])
433 (define_insn "*load_symptr_high"
434 [(set (match_operand:DI 0 "register_operand" "=r")
435 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
436 (match_operand:DI 2 "register_operand" "a")))]
439 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
440 return "%,addl %0 = @ltoffx(%1), %2";
442 return "%,addl %0 = @ltoff(%1), %2";
444 [(set_attr "itanium_class" "ialu")])
446 (define_insn "*load_symptr_low"
447 [(set (match_operand:DI 0 "register_operand" "=r")
448 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
449 (match_operand 2 "got_symbolic_operand" "s")))]
452 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
453 return "%,ld8.mov %0 = [%1], %2";
455 return "%,ld8 %0 = [%1]";
457 [(set_attr "itanium_class" "ld")])
459 (define_insn "load_ltoff_dtpmod"
460 [(set (match_operand:DI 0 "register_operand" "=r")
462 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
463 UNSPEC_LTOFF_DTPMOD)))]
465 "addl %0 = @ltoff(@dtpmod(%1)), gp"
466 [(set_attr "itanium_class" "ialu")])
468 (define_insn "load_ltoff_dtprel"
469 [(set (match_operand:DI 0 "register_operand" "=r")
471 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
472 UNSPEC_LTOFF_DTPREL)))]
474 "addl %0 = @ltoff(@dtprel(%1)), gp"
475 [(set_attr "itanium_class" "ialu")])
477 (define_expand "load_dtprel"
478 [(set (match_operand:DI 0 "register_operand" "")
479 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
484 (define_insn "*load_dtprel64"
485 [(set (match_operand:DI 0 "register_operand" "=r")
486 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
489 "movl %0 = @dtprel(%1)"
490 [(set_attr "itanium_class" "long_i")])
492 (define_insn "*load_dtprel22"
493 [(set (match_operand:DI 0 "register_operand" "=r")
494 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
497 "addl %0 = @dtprel(%1), r0"
498 [(set_attr "itanium_class" "ialu")])
500 (define_expand "add_dtprel"
501 [(set (match_operand:DI 0 "register_operand" "")
502 (plus:DI (match_operand:DI 1 "register_operand" "")
503 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
508 (define_insn "*add_dtprel14"
509 [(set (match_operand:DI 0 "register_operand" "=r")
510 (plus:DI (match_operand:DI 1 "register_operand" "r")
511 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
514 "adds %0 = @dtprel(%2), %1"
515 [(set_attr "itanium_class" "ialu")])
517 (define_insn "*add_dtprel22"
518 [(set (match_operand:DI 0 "register_operand" "=r")
519 (plus:DI (match_operand:DI 1 "register_operand" "a")
520 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
523 "addl %0 = @dtprel(%2), %1"
524 [(set_attr "itanium_class" "ialu")])
526 (define_insn "load_ltoff_tprel"
527 [(set (match_operand:DI 0 "register_operand" "=r")
529 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
530 UNSPEC_LTOFF_TPREL)))]
532 "addl %0 = @ltoff(@tprel(%1)), gp"
533 [(set_attr "itanium_class" "ialu")])
535 (define_expand "load_tprel"
536 [(set (match_operand:DI 0 "register_operand" "")
537 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
542 (define_insn "*load_tprel64"
543 [(set (match_operand:DI 0 "register_operand" "=r")
544 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
547 "movl %0 = @tprel(%1)"
548 [(set_attr "itanium_class" "long_i")])
550 (define_insn "*load_tprel22"
551 [(set (match_operand:DI 0 "register_operand" "=r")
552 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
555 "addl %0 = @tprel(%1), r0"
556 [(set_attr "itanium_class" "ialu")])
558 (define_expand "add_tprel"
559 [(set (match_operand:DI 0 "register_operand" "")
560 (plus:DI (match_operand:DI 1 "register_operand" "")
561 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
566 (define_insn "*add_tprel14"
567 [(set (match_operand:DI 0 "register_operand" "=r")
568 (plus:DI (match_operand:DI 1 "register_operand" "r")
569 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
572 "adds %0 = @tprel(%2), %1"
573 [(set_attr "itanium_class" "ialu")])
575 (define_insn "*add_tprel22"
576 [(set (match_operand:DI 0 "register_operand" "=r")
577 (plus:DI (match_operand:DI 1 "register_operand" "a")
578 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
581 "addl %0 = @tprel(%2), %1"
582 [(set_attr "itanium_class" "ialu")])
584 ;; With no offsettable memory references, we've got to have a scratch
585 ;; around to play with the second word.
586 (define_expand "movti"
587 [(parallel [(set (match_operand:TI 0 "general_operand" "")
588 (match_operand:TI 1 "general_operand" ""))
589 (clobber (match_scratch:DI 2 ""))])]
592 rtx op1 = ia64_expand_move (operands[0], operands[1]);
598 (define_insn_and_split "*movti_internal"
599 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
600 (match_operand:TI 1 "general_operand" "ri,m,r"))
601 (clobber (match_scratch:DI 2 "=X,&r,&r"))]
602 "ia64_move_ok (operands[0], operands[1])"
607 rtx adj1, adj2, in[2], out[2], insn;
610 adj1 = ia64_split_timode (in, operands[1], operands[2]);
611 adj2 = ia64_split_timode (out, operands[0], operands[2]);
614 if (reg_overlap_mentioned_p (out[0], in[1]))
616 if (reg_overlap_mentioned_p (out[1], in[0]))
627 insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
628 if (GET_CODE (out[first]) == MEM
629 && GET_CODE (XEXP (out[first], 0)) == POST_MODIFY)
630 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
631 XEXP (XEXP (out[first], 0), 0),
633 insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
634 if (GET_CODE (out[!first]) == MEM
635 && GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY)
636 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
637 XEXP (XEXP (out[!first], 0), 0),
641 [(set_attr "itanium_class" "unknown")
642 (set_attr "predicable" "no")])
644 ;; ??? SSA creates these. Can't allow memories since we don't have
645 ;; the scratch register. Fortunately combine will know how to add
646 ;; the clobber and scratch.
647 (define_insn_and_split "*movti_internal_reg"
648 [(set (match_operand:TI 0 "register_operand" "=r")
649 (match_operand:TI 1 "nonmemory_operand" "ri"))]
658 ia64_split_timode (in, operands[1], NULL_RTX);
659 ia64_split_timode (out, operands[0], NULL_RTX);
662 if (reg_overlap_mentioned_p (out[0], in[1]))
664 if (reg_overlap_mentioned_p (out[1], in[0]))
669 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
670 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
673 [(set_attr "itanium_class" "unknown")
674 (set_attr "predicable" "no")])
676 (define_expand "reload_inti"
677 [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
678 (match_operand:TI 1 "" "m"))
679 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
682 unsigned int s_regno = REGNO (operands[2]);
683 if (s_regno == REGNO (operands[0]))
685 operands[2] = gen_rtx_REG (DImode, s_regno);
688 (define_expand "reload_outti"
689 [(parallel [(set (match_operand:TI 0 "" "=m")
690 (match_operand:TI 1 "register_operand" "r"))
691 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
694 unsigned int s_regno = REGNO (operands[2]);
695 if (s_regno == REGNO (operands[1]))
697 operands[2] = gen_rtx_REG (DImode, s_regno);
700 ;; Floating Point Moves
702 ;; Note - Patterns for SF mode moves are compulsory, but
703 ;; patterns for DF are optional, as GCC can synthesize them.
705 (define_expand "movsf"
706 [(set (match_operand:SF 0 "general_operand" "")
707 (match_operand:SF 1 "general_operand" ""))]
710 rtx op1 = ia64_expand_move (operands[0], operands[1]);
716 (define_insn "*movsf_internal"
717 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
718 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
719 "ia64_move_ok (operands[0], operands[1])"
729 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
731 (define_expand "movdf"
732 [(set (match_operand:DF 0 "general_operand" "")
733 (match_operand:DF 1 "general_operand" ""))]
736 rtx op1 = ia64_expand_move (operands[0], operands[1]);
742 (define_insn "*movdf_internal"
743 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
744 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
745 "ia64_move_ok (operands[0], operands[1])"
755 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
757 ;; With no offsettable memory references, we've got to have a scratch
758 ;; around to play with the second word if the variable winds up in GRs.
759 (define_expand "movtf"
760 [(set (match_operand:TF 0 "general_operand" "")
761 (match_operand:TF 1 "general_operand" ""))]
762 "INTEL_EXTENDED_IEEE_FORMAT"
764 /* We must support TFmode loads into general registers for stdarg/vararg
765 and unprototyped calls. We split them into DImode loads for convenience.
766 We don't need TFmode stores from general regs, because a stdarg/vararg
767 routine does a block store to memory of unnamed arguments. */
768 if (GET_CODE (operands[0]) == REG
769 && GR_REGNO_P (REGNO (operands[0])))
771 /* We're hoping to transform everything that deals with TFmode
772 quantities and GR registers early in the compiler. */
776 /* Struct to register can just use TImode instead. */
777 if ((GET_CODE (operands[1]) == SUBREG
778 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
779 || (GET_CODE (operands[1]) == REG
780 && GR_REGNO_P (REGNO (operands[1]))))
782 emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])),
783 SUBREG_REG (operands[1]));
787 if (GET_CODE (operands[1]) == CONST_DOUBLE)
789 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
790 operand_subword (operands[1], 0, 0, TFmode));
791 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
792 operand_subword (operands[1], 1, 0, TFmode));
796 /* If the quantity is in a register not known to be GR, spill it. */
797 if (register_operand (operands[1], TFmode))
798 operands[1] = spill_tfmode_operand (operands[1], 1);
800 if (GET_CODE (operands[1]) == MEM)
804 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0]));
805 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1);
807 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
808 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
815 if (! reload_in_progress && ! reload_completed)
817 operands[0] = spill_tfmode_operand (operands[0], 0);
818 operands[1] = spill_tfmode_operand (operands[1], 0);
820 if (! ia64_move_ok (operands[0], operands[1]))
821 operands[1] = force_reg (TFmode, operands[1]);
825 ;; ??? There's no easy way to mind volatile acquire/release semantics.
827 (define_insn "*movtf_internal"
828 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
829 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
830 "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
835 [(set_attr "itanium_class" "fmisc,fld,stf")])
837 ;; ::::::::::::::::::::
841 ;; ::::::::::::::::::::
843 ;; Signed conversions from a smaller integer to a larger integer
845 (define_insn "extendqidi2"
846 [(set (match_operand:DI 0 "gr_register_operand" "=r")
847 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
850 [(set_attr "itanium_class" "xtd")])
852 (define_insn "extendhidi2"
853 [(set (match_operand:DI 0 "gr_register_operand" "=r")
854 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
857 [(set_attr "itanium_class" "xtd")])
859 (define_insn "extendsidi2"
860 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
861 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
866 [(set_attr "itanium_class" "xtd,fmisc")])
868 ;; Unsigned conversions from a smaller integer to a larger integer
870 (define_insn "zero_extendqidi2"
871 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
872 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
877 [(set_attr "itanium_class" "xtd,ld")])
879 (define_insn "zero_extendhidi2"
880 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
881 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
886 [(set_attr "itanium_class" "xtd,ld")])
888 (define_insn "zero_extendsidi2"
889 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
891 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
897 [(set_attr "itanium_class" "xtd,ld,fmisc")])
899 ;; Convert between floating point types of different sizes.
901 ;; At first glance, it would appear that emitting fnorm for an extending
902 ;; conversion is unnecessary. However, the stf and getf instructions work
903 ;; correctly only if the input is properly rounded for its type. In
904 ;; particular, we get the wrong result for getf.d/stfd if the input is a
905 ;; denorm single. Since we don't know what the next instruction will be, we
906 ;; have to emit an fnorm.
908 ;; ??? Optimization opportunity here. Get rid of the insn altogether
909 ;; when we can. Should probably use a scheme like has been proposed
910 ;; for ia32 in dealing with operands that match unary operators. This
911 ;; would let combine merge the thing into adjacent insns. See also how the
912 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
913 ;; se_register_operand.
915 (define_insn "extendsfdf2"
916 [(set (match_operand:DF 0 "fr_register_operand" "=f")
917 (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
920 [(set_attr "itanium_class" "fmac")])
922 (define_insn "extendsftf2"
923 [(set (match_operand:TF 0 "fr_register_operand" "=f")
924 (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))]
925 "INTEL_EXTENDED_IEEE_FORMAT"
927 [(set_attr "itanium_class" "fmac")])
929 (define_insn "extenddftf2"
930 [(set (match_operand:TF 0 "fr_register_operand" "=f")
931 (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))]
932 "INTEL_EXTENDED_IEEE_FORMAT"
934 [(set_attr "itanium_class" "fmac")])
936 (define_insn "truncdfsf2"
937 [(set (match_operand:SF 0 "fr_register_operand" "=f")
938 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
941 [(set_attr "itanium_class" "fmac")])
943 (define_insn "trunctfsf2"
944 [(set (match_operand:SF 0 "fr_register_operand" "=f")
945 (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
946 "INTEL_EXTENDED_IEEE_FORMAT"
948 [(set_attr "itanium_class" "fmac")])
950 (define_insn "trunctfdf2"
951 [(set (match_operand:DF 0 "fr_register_operand" "=f")
952 (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
953 "INTEL_EXTENDED_IEEE_FORMAT"
955 [(set_attr "itanium_class" "fmac")])
957 ;; Convert between signed integer types and floating point.
959 (define_insn "floatditf2"
960 [(set (match_operand:TF 0 "fr_register_operand" "=f")
961 (float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
962 "INTEL_EXTENDED_IEEE_FORMAT"
964 [(set_attr "itanium_class" "fcvtfx")])
966 ;; ??? Suboptimal. This should be split somehow.
967 (define_insn "floatdidf2"
968 [(set (match_operand:DF 0 "register_operand" "=f")
969 (float:DF (match_operand:DI 1 "register_operand" "f")))]
970 "!INTEL_EXTENDED_IEEE_FORMAT"
971 "fcvt.xf %0 = %1\;;;\;%,fnorm.d %0 = %0"
972 [(set_attr "itanium_class" "fcvtfx")])
974 ;; ??? Suboptimal. This should be split somehow.
975 (define_insn "floatdisf2"
976 [(set (match_operand:SF 0 "register_operand" "=f")
977 (float:SF (match_operand:DI 1 "register_operand" "f")))]
978 "!INTEL_EXTENDED_IEEE_FORMAT"
979 "fcvt.xf %0 = %1\;;;\;%,fnorm.s %0 = %0"
980 [(set_attr "itanium_class" "fcvtfx")])
982 (define_insn "fix_truncsfdi2"
983 [(set (match_operand:DI 0 "fr_register_operand" "=f")
984 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
986 "fcvt.fx.trunc %0 = %1"
987 [(set_attr "itanium_class" "fcvtfx")])
989 (define_insn "fix_truncdfdi2"
990 [(set (match_operand:DI 0 "fr_register_operand" "=f")
991 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
993 "fcvt.fx.trunc %0 = %1"
994 [(set_attr "itanium_class" "fcvtfx")])
996 (define_insn "fix_trunctfdi2"
997 [(set (match_operand:DI 0 "fr_register_operand" "=f")
998 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
999 "INTEL_EXTENDED_IEEE_FORMAT"
1000 "fcvt.fx.trunc %0 = %1"
1001 [(set_attr "itanium_class" "fcvtfx")])
1003 (define_insn "fix_trunctfdi2_alts"
1004 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1005 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1006 (use (match_operand:SI 2 "const_int_operand" ""))]
1007 "INTEL_EXTENDED_IEEE_FORMAT"
1008 "fcvt.fx.trunc.s%2 %0 = %1"
1009 [(set_attr "itanium_class" "fcvtfx")])
1011 ;; Convert between unsigned integer types and floating point.
1013 (define_insn "floatunsdisf2"
1014 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1015 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
1017 "fcvt.xuf.s %0 = %1"
1018 [(set_attr "itanium_class" "fcvtfx")])
1020 (define_insn "floatunsdidf2"
1021 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1022 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
1024 "fcvt.xuf.d %0 = %1"
1025 [(set_attr "itanium_class" "fcvtfx")])
1027 (define_insn "floatunsditf2"
1028 [(set (match_operand:TF 0 "fr_register_operand" "=f")
1029 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
1030 "INTEL_EXTENDED_IEEE_FORMAT"
1032 [(set_attr "itanium_class" "fcvtfx")])
1034 (define_insn "fixuns_truncsfdi2"
1035 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1036 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1038 "fcvt.fxu.trunc %0 = %1"
1039 [(set_attr "itanium_class" "fcvtfx")])
1041 (define_insn "fixuns_truncdfdi2"
1042 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1043 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1045 "fcvt.fxu.trunc %0 = %1"
1046 [(set_attr "itanium_class" "fcvtfx")])
1048 (define_insn "fixuns_trunctfdi2"
1049 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1050 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1051 "INTEL_EXTENDED_IEEE_FORMAT"
1052 "fcvt.fxu.trunc %0 = %1"
1053 [(set_attr "itanium_class" "fcvtfx")])
1055 (define_insn "fixuns_trunctfdi2_alts"
1056 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1057 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1058 (use (match_operand:SI 2 "const_int_operand" ""))]
1059 "INTEL_EXTENDED_IEEE_FORMAT"
1060 "fcvt.fxu.trunc.s%2 %0 = %1"
1061 [(set_attr "itanium_class" "fcvtfx")])
1063 ;; ::::::::::::::::::::
1065 ;; :: Bit field extraction
1067 ;; ::::::::::::::::::::
1070 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1071 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1072 (match_operand:DI 2 "const_int_operand" "n")
1073 (match_operand:DI 3 "const_int_operand" "n")))]
1075 "extr %0 = %1, %3, %2"
1076 [(set_attr "itanium_class" "ishf")])
1078 (define_insn "extzv"
1079 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1080 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1081 (match_operand:DI 2 "const_int_operand" "n")
1082 (match_operand:DI 3 "const_int_operand" "n")))]
1084 "extr.u %0 = %1, %3, %2"
1085 [(set_attr "itanium_class" "ishf")])
1087 ;; Insert a bit field.
1088 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1089 ;; Source1 can be 0 or -1.
1090 ;; Source2 can be 0.
1092 ;; ??? Actual dep instruction is more powerful than what these insv
1093 ;; patterns support. Unfortunately, combine is unable to create patterns
1094 ;; where source2 != dest.
1096 (define_expand "insv"
1097 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1098 (match_operand:DI 1 "const_int_operand" "")
1099 (match_operand:DI 2 "const_int_operand" ""))
1100 (match_operand:DI 3 "nonmemory_operand" ""))]
1103 int width = INTVAL (operands[1]);
1104 int shift = INTVAL (operands[2]);
1106 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1108 if (! register_operand (operands[3], DImode)
1109 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1110 operands[3] = force_reg (DImode, operands[3]);
1112 /* If this is a single dep instruction, we have nothing to do. */
1113 if (! ((register_operand (operands[3], DImode) && width <= 16)
1114 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1116 /* Check for cases that can be implemented with a mix instruction. */
1117 if (width == 32 && shift == 0)
1119 /* Directly generating the mix4left instruction confuses
1120 optimize_bit_field in function.c. Since this is performing
1121 a useful optimization, we defer generation of the complicated
1122 mix4left RTL to the first splitting phase. */
1123 rtx tmp = gen_reg_rtx (DImode);
1124 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1127 else if (width == 32 && shift == 32)
1129 emit_insn (gen_mix4right (operands[0], operands[3]));
1133 /* We could handle remaining cases by emitting multiple dep
1136 If we need more than two dep instructions then we lose. A 6
1137 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1138 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1139 the latter is 6 cycles on an Itanium (TM) processor, because there is
1140 only one function unit that can execute dep and shr immed.
1142 If we only need two dep instruction, then we still lose.
1143 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1144 the unnecessary mov, this is still undesirable because it will be
1145 hard to optimize, and it creates unnecessary pressure on the I0
1151 /* This code may be useful for other IA-64 processors, so we leave it in
1157 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1161 tmp = gen_reg_rtx (DImode);
1162 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1165 operands[1] = GEN_INT (width);
1166 operands[2] = GEN_INT (shift);
1171 (define_insn "*insv_internal"
1172 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1173 (match_operand:DI 1 "const_int_operand" "n")
1174 (match_operand:DI 2 "const_int_operand" "n"))
1175 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1176 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1177 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1178 "dep %0 = %3, %0, %2, %1"
1179 [(set_attr "itanium_class" "ishf")])
1181 ;; Combine doesn't like to create bit-field insertions into zero.
1182 (define_insn "*depz_internal"
1183 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1184 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1185 (match_operand:DI 2 "const_int_operand" "n"))
1186 (match_operand:DI 3 "const_int_operand" "n")))]
1187 "CONST_OK_FOR_M (INTVAL (operands[2]))
1188 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1190 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1191 return "%,dep.z %0 = %1, %2, %3";
1193 [(set_attr "itanium_class" "ishf")])
1195 (define_insn "shift_mix4left"
1196 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1197 (const_int 32) (const_int 0))
1198 (match_operand:DI 1 "gr_register_operand" "r"))
1199 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1202 [(set_attr "itanium_class" "unknown")])
1205 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1206 (const_int 32) (const_int 0))
1207 (match_operand:DI 1 "register_operand" ""))
1208 (clobber (match_operand:DI 2 "register_operand" ""))]
1210 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1211 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1212 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1213 "operands[3] = operands[2];")
1216 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1217 (const_int 32) (const_int 0))
1218 (match_operand:DI 1 "register_operand" ""))
1219 (clobber (match_operand:DI 2 "register_operand" ""))]
1220 "! reload_completed"
1221 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1222 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1223 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1224 "operands[3] = operands[2];")
1226 (define_insn "*mix4left"
1227 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1228 (const_int 32) (const_int 0))
1229 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1232 "mix4.l %0 = %0, %r1"
1233 [(set_attr "itanium_class" "mmshf")])
1235 (define_insn "mix4right"
1236 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1237 (const_int 32) (const_int 32))
1238 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1240 "mix4.r %0 = %r1, %0"
1241 [(set_attr "itanium_class" "mmshf")])
1243 ;; This is used by the rotrsi3 pattern.
1245 (define_insn "*mix4right_3op"
1246 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1247 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1248 (ashift:DI (zero_extend:DI
1249 (match_operand:SI 2 "gr_register_operand" "r"))
1252 "mix4.r %0 = %2, %1"
1253 [(set_attr "itanium_class" "mmshf")])
1256 ;; ::::::::::::::::::::
1258 ;; :: 1 bit Integer arithmetic
1260 ;; ::::::::::::::::::::
1262 (define_insn_and_split "andbi3"
1263 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1264 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1265 (match_operand:BI 2 "register_operand" "c,r,r")))]
1269 tbit.nz.and.orcm %0, %I0 = %2, 0
1272 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1273 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1274 [(cond_exec (eq (match_dup 2) (const_int 0))
1275 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1278 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1280 (define_insn_and_split "*andcmbi3"
1281 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1282 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1283 (match_operand:BI 2 "register_operand" "0,0,r")))]
1287 tbit.z.and.orcm %0, %I0 = %1, 0
1290 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1291 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1292 [(cond_exec (ne (match_dup 1) (const_int 0))
1293 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1296 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1298 (define_insn_and_split "iorbi3"
1299 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1300 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1301 (match_operand:BI 2 "register_operand" "c,r,r")))]
1305 tbit.nz.or.andcm %0, %I0 = %2, 0
1308 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1309 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1310 [(cond_exec (ne (match_dup 2) (const_int 0))
1311 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1314 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1316 (define_insn_and_split "*iorcmbi3"
1317 [(set (match_operand:BI 0 "register_operand" "=c,c")
1318 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1319 (match_operand:BI 2 "register_operand" "0,0")))]
1323 tbit.z.or.andcm %0, %I0 = %1, 0"
1325 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1326 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1327 [(cond_exec (eq (match_dup 1) (const_int 0))
1328 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1331 [(set_attr "itanium_class" "unknown,tbit")])
1333 (define_insn "one_cmplbi2"
1334 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1335 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1336 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1339 tbit.z %0, %I0 = %1, 0
1343 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1346 [(set (match_operand:BI 0 "register_operand" "")
1347 (not:BI (match_operand:BI 1 "register_operand" "")))
1348 (clobber (match_scratch:BI 2 ""))]
1350 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1351 && rtx_equal_p (operands[0], operands[1])"
1352 [(set (match_dup 4) (match_dup 3))
1353 (set (match_dup 0) (const_int 1))
1354 (cond_exec (ne (match_dup 2) (const_int 0))
1355 (set (match_dup 0) (const_int 0)))
1356 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1357 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1358 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1361 [(set (match_operand:BI 0 "register_operand" "")
1362 (not:BI (match_operand:BI 1 "register_operand" "")))
1363 (clobber (match_scratch:BI 2 ""))]
1365 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1366 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1367 && ! rtx_equal_p (operands[0], operands[1])"
1368 [(cond_exec (ne (match_dup 1) (const_int 0))
1369 (set (match_dup 0) (const_int 0)))
1370 (cond_exec (eq (match_dup 1) (const_int 0))
1371 (set (match_dup 0) (const_int 1)))
1372 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1375 (define_insn "*cmpsi_and_0"
1376 [(set (match_operand:BI 0 "register_operand" "=c")
1377 (and:BI (match_operator:BI 4 "predicate_operator"
1378 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1379 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1380 (match_operand:BI 1 "register_operand" "0")))]
1382 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1383 [(set_attr "itanium_class" "icmp")])
1385 (define_insn "*cmpsi_and_1"
1386 [(set (match_operand:BI 0 "register_operand" "=c")
1387 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1388 [(match_operand:SI 2 "gr_register_operand" "r")
1390 (match_operand:BI 1 "register_operand" "0")))]
1392 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1393 [(set_attr "itanium_class" "icmp")])
1395 (define_insn "*cmpsi_andnot_0"
1396 [(set (match_operand:BI 0 "register_operand" "=c")
1397 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1398 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1399 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1400 (match_operand:BI 1 "register_operand" "0")))]
1402 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1403 [(set_attr "itanium_class" "icmp")])
1405 (define_insn "*cmpsi_andnot_1"
1406 [(set (match_operand:BI 0 "register_operand" "=c")
1407 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1408 [(match_operand:SI 2 "gr_register_operand" "r")
1410 (match_operand:BI 1 "register_operand" "0")))]
1412 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1413 [(set_attr "itanium_class" "icmp")])
1415 (define_insn "*cmpdi_and_0"
1416 [(set (match_operand:BI 0 "register_operand" "=c")
1417 (and:BI (match_operator:BI 4 "predicate_operator"
1418 [(match_operand:DI 2 "gr_register_operand" "r")
1419 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1420 (match_operand:BI 1 "register_operand" "0")))]
1422 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1423 [(set_attr "itanium_class" "icmp")])
1425 (define_insn "*cmpdi_and_1"
1426 [(set (match_operand:BI 0 "register_operand" "=c")
1427 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1428 [(match_operand:DI 2 "gr_register_operand" "r")
1430 (match_operand:BI 1 "register_operand" "0")))]
1432 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1433 [(set_attr "itanium_class" "icmp")])
1435 (define_insn "*cmpdi_andnot_0"
1436 [(set (match_operand:BI 0 "register_operand" "=c")
1437 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1438 [(match_operand:DI 2 "gr_register_operand" "r")
1439 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1440 (match_operand:BI 1 "register_operand" "0")))]
1442 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1443 [(set_attr "itanium_class" "icmp")])
1445 (define_insn "*cmpdi_andnot_1"
1446 [(set (match_operand:BI 0 "register_operand" "=c")
1447 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1448 [(match_operand:DI 2 "gr_register_operand" "r")
1450 (match_operand:BI 1 "register_operand" "0")))]
1452 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1453 [(set_attr "itanium_class" "icmp")])
1455 (define_insn "*tbit_and_0"
1456 [(set (match_operand:BI 0 "register_operand" "=c")
1457 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1460 (match_operand:BI 2 "register_operand" "0")))]
1462 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1463 [(set_attr "itanium_class" "tbit")])
1465 (define_insn "*tbit_and_1"
1466 [(set (match_operand:BI 0 "register_operand" "=c")
1467 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1470 (match_operand:BI 2 "register_operand" "0")))]
1472 "tbit.z.and.orcm %0, %I0 = %1, 0"
1473 [(set_attr "itanium_class" "tbit")])
1475 (define_insn "*tbit_and_2"
1476 [(set (match_operand:BI 0 "register_operand" "=c")
1477 (and:BI (ne:BI (zero_extract:DI
1478 (match_operand:DI 1 "gr_register_operand" "r")
1480 (match_operand:DI 2 "const_int_operand" "n"))
1482 (match_operand:BI 3 "register_operand" "0")))]
1484 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1485 [(set_attr "itanium_class" "tbit")])
1487 (define_insn "*tbit_and_3"
1488 [(set (match_operand:BI 0 "register_operand" "=c")
1489 (and:BI (eq:BI (zero_extract:DI
1490 (match_operand:DI 1 "gr_register_operand" "r")
1492 (match_operand:DI 2 "const_int_operand" "n"))
1494 (match_operand:BI 3 "register_operand" "0")))]
1496 "tbit.z.and.orcm %0, %I0 = %1, %2"
1497 [(set_attr "itanium_class" "tbit")])
1499 (define_insn "*cmpsi_or_0"
1500 [(set (match_operand:BI 0 "register_operand" "=c")
1501 (ior:BI (match_operator:BI 4 "predicate_operator"
1502 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1503 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1504 (match_operand:BI 1 "register_operand" "0")))]
1506 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1507 [(set_attr "itanium_class" "icmp")])
1509 (define_insn "*cmpsi_or_1"
1510 [(set (match_operand:BI 0 "register_operand" "=c")
1511 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1512 [(match_operand:SI 2 "gr_register_operand" "r")
1514 (match_operand:BI 1 "register_operand" "0")))]
1516 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1517 [(set_attr "itanium_class" "icmp")])
1519 (define_insn "*cmpsi_orcm_0"
1520 [(set (match_operand:BI 0 "register_operand" "=c")
1521 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1522 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1523 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1524 (match_operand:BI 1 "register_operand" "0")))]
1526 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1527 [(set_attr "itanium_class" "icmp")])
1529 (define_insn "*cmpsi_orcm_1"
1530 [(set (match_operand:BI 0 "register_operand" "=c")
1531 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1532 [(match_operand:SI 2 "gr_register_operand" "r")
1534 (match_operand:BI 1 "register_operand" "0")))]
1536 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1537 [(set_attr "itanium_class" "icmp")])
1539 (define_insn "*cmpdi_or_0"
1540 [(set (match_operand:BI 0 "register_operand" "=c")
1541 (ior:BI (match_operator:BI 4 "predicate_operator"
1542 [(match_operand:DI 2 "gr_register_operand" "r")
1543 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1544 (match_operand:BI 1 "register_operand" "0")))]
1546 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1547 [(set_attr "itanium_class" "icmp")])
1549 (define_insn "*cmpdi_or_1"
1550 [(set (match_operand:BI 0 "register_operand" "=c")
1551 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1552 [(match_operand:DI 2 "gr_register_operand" "r")
1554 (match_operand:BI 1 "register_operand" "0")))]
1556 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1557 [(set_attr "itanium_class" "icmp")])
1559 (define_insn "*cmpdi_orcm_0"
1560 [(set (match_operand:BI 0 "register_operand" "=c")
1561 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1562 [(match_operand:DI 2 "gr_register_operand" "r")
1563 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1564 (match_operand:BI 1 "register_operand" "0")))]
1566 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1567 [(set_attr "itanium_class" "icmp")])
1569 (define_insn "*cmpdi_orcm_1"
1570 [(set (match_operand:BI 0 "register_operand" "=c")
1571 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1572 [(match_operand:DI 2 "gr_register_operand" "r")
1574 (match_operand:BI 1 "register_operand" "0")))]
1576 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1577 [(set_attr "itanium_class" "icmp")])
1579 (define_insn "*tbit_or_0"
1580 [(set (match_operand:BI 0 "register_operand" "=c")
1581 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1584 (match_operand:BI 2 "register_operand" "0")))]
1586 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1587 [(set_attr "itanium_class" "tbit")])
1589 (define_insn "*tbit_or_1"
1590 [(set (match_operand:BI 0 "register_operand" "=c")
1591 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1594 (match_operand:BI 2 "register_operand" "0")))]
1596 "tbit.z.or.andcm %0, %I0 = %1, 0"
1597 [(set_attr "itanium_class" "tbit")])
1599 (define_insn "*tbit_or_2"
1600 [(set (match_operand:BI 0 "register_operand" "=c")
1601 (ior:BI (ne:BI (zero_extract:DI
1602 (match_operand:DI 1 "gr_register_operand" "r")
1604 (match_operand:DI 2 "const_int_operand" "n"))
1606 (match_operand:BI 3 "register_operand" "0")))]
1608 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1609 [(set_attr "itanium_class" "tbit")])
1611 (define_insn "*tbit_or_3"
1612 [(set (match_operand:BI 0 "register_operand" "=c")
1613 (ior:BI (eq:BI (zero_extract:DI
1614 (match_operand:DI 1 "gr_register_operand" "r")
1616 (match_operand:DI 2 "const_int_operand" "n"))
1618 (match_operand:BI 3 "register_operand" "0")))]
1620 "tbit.z.or.andcm %0, %I0 = %1, %2"
1621 [(set_attr "itanium_class" "tbit")])
1623 ;; Transform test of and/or of setcc into parallel comparisons.
1626 [(set (match_operand:BI 0 "register_operand" "")
1627 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1629 (match_operand:DI 3 "register_operand" ""))
1633 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1638 [(set (match_operand:BI 0 "register_operand" "")
1639 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1641 (match_operand:DI 3 "register_operand" ""))
1645 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1647 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1648 (clobber (scratch))])]
1652 [(set (match_operand:BI 0 "register_operand" "")
1653 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1655 (match_operand:DI 3 "register_operand" ""))
1659 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1664 [(set (match_operand:BI 0 "register_operand" "")
1665 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1667 (match_operand:DI 3 "register_operand" ""))
1671 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1673 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1674 (clobber (scratch))])]
1677 ;; ??? Incredibly hackish. Either need four proper patterns with all
1678 ;; the alternatives, or rely on sched1 to split the insn and hope that
1679 ;; nothing bad happens to the comparisons in the meantime.
1681 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1682 ;; that we're doing height reduction.
1684 ;(define_insn_and_split ""
1685 ; [(set (match_operand:BI 0 "register_operand" "=c")
1686 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1687 ; [(match_operand 2 "" "")
1688 ; (match_operand 3 "" "")])
1689 ; (match_operator:BI 4 "comparison_operator"
1690 ; [(match_operand 5 "" "")
1691 ; (match_operand 6 "" "")]))
1693 ; "flag_schedule_insns"
1696 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1697 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1700 ;(define_insn_and_split ""
1701 ; [(set (match_operand:BI 0 "register_operand" "=c")
1702 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1703 ; [(match_operand 2 "" "")
1704 ; (match_operand 3 "" "")])
1705 ; (match_operator:BI 4 "comparison_operator"
1706 ; [(match_operand 5 "" "")
1707 ; (match_operand 6 "" "")]))
1709 ; "flag_schedule_insns"
1712 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1713 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1717 ; [(set (match_operand:BI 0 "register_operand" "")
1718 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1719 ; [(match_operand 2 "" "")
1720 ; (match_operand 3 "" "")])
1721 ; (match_operand:BI 7 "register_operand" ""))
1722 ; (and:BI (match_operator:BI 4 "comparison_operator"
1723 ; [(match_operand 5 "" "")
1724 ; (match_operand 6 "" "")])
1725 ; (match_operand:BI 8 "register_operand" ""))))]
1727 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1728 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1733 ; [(set (match_operand:BI 0 "register_operand" "")
1734 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1735 ; [(match_operand 2 "" "")
1736 ; (match_operand 3 "" "")])
1737 ; (match_operand:BI 7 "register_operand" ""))
1738 ; (ior:BI (match_operator:BI 4 "comparison_operator"
1739 ; [(match_operand 5 "" "")
1740 ; (match_operand 6 "" "")])
1741 ; (match_operand:BI 8 "register_operand" ""))))]
1743 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1744 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1748 ;; Try harder to avoid predicate copies by duplicating compares.
1749 ;; Note that we'll have already split the predicate copy, which
1750 ;; is kind of a pain, but oh well.
1753 [(set (match_operand:BI 0 "register_operand" "")
1754 (match_operand:BI 1 "comparison_operator" ""))
1755 (set (match_operand:CCI 2 "register_operand" "")
1756 (match_operand:CCI 3 "register_operand" ""))
1757 (set (match_operand:CCI 4 "register_operand" "")
1758 (match_operand:CCI 5 "register_operand" ""))
1759 (set (match_operand:BI 6 "register_operand" "")
1760 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
1761 "REGNO (operands[3]) == REGNO (operands[0])
1762 && REGNO (operands[4]) == REGNO (operands[0]) + 1
1763 && REGNO (operands[4]) == REGNO (operands[2]) + 1
1764 && REGNO (operands[6]) == REGNO (operands[2])"
1765 [(set (match_dup 0) (match_dup 1))
1766 (set (match_dup 6) (match_dup 7))]
1767 "operands[7] = copy_rtx (operands[1]);")
1769 ;; ::::::::::::::::::::
1771 ;; :: 16 bit Integer arithmetic
1773 ;; ::::::::::::::::::::
1775 (define_insn "mulhi3"
1776 [(set (match_operand:HI 0 "gr_register_operand" "=r")
1777 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
1778 (match_operand:HI 2 "gr_register_operand" "r")))]
1780 "pmpy2.r %0 = %1, %2"
1781 [(set_attr "itanium_class" "mmmul")])
1784 ;; ::::::::::::::::::::
1786 ;; :: 32 bit Integer arithmetic
1788 ;; ::::::::::::::::::::
1790 (define_insn "addsi3"
1791 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
1792 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
1793 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
1799 [(set_attr "itanium_class" "ialu")])
1801 (define_insn "*addsi3_plus1"
1802 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1803 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
1804 (match_operand:SI 2 "gr_register_operand" "r"))
1807 "add %0 = %1, %2, 1"
1808 [(set_attr "itanium_class" "ialu")])
1810 (define_insn "*addsi3_plus1_alt"
1811 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1812 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1816 "add %0 = %1, %1, 1"
1817 [(set_attr "itanium_class" "ialu")])
1819 (define_insn "*addsi3_shladd"
1820 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1821 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1822 (match_operand:SI 2 "shladd_operand" "n"))
1823 (match_operand:SI 3 "gr_register_operand" "r")))]
1825 "shladd %0 = %1, %S2, %3"
1826 [(set_attr "itanium_class" "ialu")])
1828 (define_insn "subsi3"
1829 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1830 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
1831 (match_operand:SI 2 "gr_register_operand" "r")))]
1834 [(set_attr "itanium_class" "ialu")])
1836 (define_insn "*subsi3_minus1"
1837 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1838 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
1839 (match_operand:SI 2 "gr_register_operand" "r")))]
1841 "sub %0 = %2, %1, 1"
1842 [(set_attr "itanium_class" "ialu")])
1844 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
1846 (define_insn "mulsi3"
1847 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1848 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1849 (match_operand:SI 2 "grfr_register_operand" "f")))]
1851 "xmpy.l %0 = %1, %2"
1852 [(set_attr "itanium_class" "xmpy")])
1854 (define_insn "maddsi4"
1855 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1856 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1857 (match_operand:SI 2 "grfr_register_operand" "f"))
1858 (match_operand:SI 3 "grfr_register_operand" "f")))]
1860 "xma.l %0 = %1, %2, %3"
1861 [(set_attr "itanium_class" "xmpy")])
1863 (define_insn "negsi2"
1864 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1865 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
1868 [(set_attr "itanium_class" "ialu")])
1870 (define_expand "abssi2"
1872 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
1873 (set (match_operand:SI 0 "gr_register_operand" "")
1874 (if_then_else:SI (eq (match_dup 2) (const_int 0))
1875 (neg:SI (match_dup 1))
1878 { operands[2] = gen_reg_rtx (BImode); })
1880 (define_expand "sminsi3"
1882 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
1883 (match_operand:SI 2 "gr_register_operand" "")))
1884 (set (match_operand:SI 0 "gr_register_operand" "")
1885 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1886 (match_dup 2) (match_dup 1)))]
1888 { operands[3] = gen_reg_rtx (BImode); })
1890 (define_expand "smaxsi3"
1892 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
1893 (match_operand:SI 2 "gr_register_operand" "")))
1894 (set (match_operand:SI 0 "gr_register_operand" "")
1895 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1896 (match_dup 1) (match_dup 2)))]
1898 { operands[3] = gen_reg_rtx (BImode); })
1900 (define_expand "uminsi3"
1902 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
1903 (match_operand:SI 2 "gr_register_operand" "")))
1904 (set (match_operand:SI 0 "gr_register_operand" "")
1905 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1906 (match_dup 2) (match_dup 1)))]
1908 { operands[3] = gen_reg_rtx (BImode); })
1910 (define_expand "umaxsi3"
1912 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
1913 (match_operand:SI 2 "gr_register_operand" "")))
1914 (set (match_operand:SI 0 "gr_register_operand" "")
1915 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1916 (match_dup 1) (match_dup 2)))]
1918 { operands[3] = gen_reg_rtx (BImode); })
1920 (define_expand "divsi3"
1921 [(set (match_operand:SI 0 "register_operand" "")
1922 (div:SI (match_operand:SI 1 "general_operand" "")
1923 (match_operand:SI 2 "general_operand" "")))]
1924 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
1926 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
1927 REAL_VALUE_TYPE twon34_r;
1929 op0_tf = gen_reg_rtx (TFmode);
1930 op0_di = gen_reg_rtx (DImode);
1932 if (CONSTANT_P (operands[1]))
1933 operands[1] = force_reg (SImode, operands[1]);
1934 op1_tf = gen_reg_rtx (TFmode);
1935 expand_float (op1_tf, operands[1], 0);
1937 if (CONSTANT_P (operands[2]))
1938 operands[2] = force_reg (SImode, operands[2]);
1939 op2_tf = gen_reg_rtx (TFmode);
1940 expand_float (op2_tf, operands[2], 0);
1943 real_2expN (&twon34_r, -34);
1944 twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
1945 twon34 = force_reg (TFmode, twon34);
1947 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
1949 emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
1950 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
1954 (define_expand "modsi3"
1955 [(set (match_operand:SI 0 "register_operand" "")
1956 (mod:SI (match_operand:SI 1 "general_operand" "")
1957 (match_operand:SI 2 "general_operand" "")))]
1958 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
1960 rtx op2_neg, op1_di, div;
1962 div = gen_reg_rtx (SImode);
1963 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
1965 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
1967 /* This is a trick to get us to reuse the value that we're sure to
1968 have already copied to the FP regs. */
1969 op1_di = gen_reg_rtx (DImode);
1970 convert_move (op1_di, operands[1], 0);
1972 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
1973 gen_lowpart (SImode, op1_di)));
1977 (define_expand "udivsi3"
1978 [(set (match_operand:SI 0 "register_operand" "")
1979 (udiv:SI (match_operand:SI 1 "general_operand" "")
1980 (match_operand:SI 2 "general_operand" "")))]
1981 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
1983 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
1984 REAL_VALUE_TYPE twon34_r;
1986 op0_tf = gen_reg_rtx (TFmode);
1987 op0_di = gen_reg_rtx (DImode);
1989 if (CONSTANT_P (operands[1]))
1990 operands[1] = force_reg (SImode, operands[1]);
1991 op1_tf = gen_reg_rtx (TFmode);
1992 expand_float (op1_tf, operands[1], 1);
1994 if (CONSTANT_P (operands[2]))
1995 operands[2] = force_reg (SImode, operands[2]);
1996 op2_tf = gen_reg_rtx (TFmode);
1997 expand_float (op2_tf, operands[2], 1);
2000 real_2expN (&twon34_r, -34);
2001 twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
2002 twon34 = force_reg (TFmode, twon34);
2004 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
2006 emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
2007 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2011 (define_expand "umodsi3"
2012 [(set (match_operand:SI 0 "register_operand" "")
2013 (umod:SI (match_operand:SI 1 "general_operand" "")
2014 (match_operand:SI 2 "general_operand" "")))]
2015 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2017 rtx op2_neg, op1_di, div;
2019 div = gen_reg_rtx (SImode);
2020 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
2022 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2024 /* This is a trick to get us to reuse the value that we're sure to
2025 have already copied to the FP regs. */
2026 op1_di = gen_reg_rtx (DImode);
2027 convert_move (op1_di, operands[1], 1);
2029 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2030 gen_lowpart (SImode, op1_di)));
2034 (define_insn_and_split "divsi3_internal"
2035 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2036 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2037 (match_operand:TF 2 "fr_register_operand" "f"))))
2038 (clobber (match_scratch:TF 4 "=&f"))
2039 (clobber (match_scratch:TF 5 "=&f"))
2040 (clobber (match_scratch:BI 6 "=c"))
2041 (use (match_operand:TF 3 "fr_register_operand" "f"))]
2042 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2044 "&& reload_completed"
2045 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2046 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2047 UNSPEC_FR_RECIP_APPROX))
2048 (use (const_int 1))])
2049 (cond_exec (ne (match_dup 6) (const_int 0))
2050 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2051 (use (const_int 1))]))
2052 (cond_exec (ne (match_dup 6) (const_int 0))
2053 (parallel [(set (match_dup 5)
2054 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2056 (use (const_int 1))]))
2057 (cond_exec (ne (match_dup 6) (const_int 0))
2058 (parallel [(set (match_dup 4)
2059 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2061 (use (const_int 1))]))
2062 (cond_exec (ne (match_dup 6) (const_int 0))
2063 (parallel [(set (match_dup 5)
2064 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
2066 (use (const_int 1))]))
2067 (cond_exec (ne (match_dup 6) (const_int 0))
2068 (parallel [(set (match_dup 0)
2069 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2071 (use (const_int 1))]))
2073 "operands[7] = CONST1_RTX (TFmode);"
2074 [(set_attr "predicable" "no")])
2076 ;; ::::::::::::::::::::
2078 ;; :: 64 bit Integer arithmetic
2080 ;; ::::::::::::::::::::
2082 (define_insn "adddi3"
2083 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2084 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2085 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2091 [(set_attr "itanium_class" "ialu")])
2093 (define_insn "*adddi3_plus1"
2094 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2095 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2096 (match_operand:DI 2 "gr_register_operand" "r"))
2099 "add %0 = %1, %2, 1"
2100 [(set_attr "itanium_class" "ialu")])
2102 ;; This has some of the same problems as shladd. We let the shladd
2103 ;; eliminator hack handle it, which results in the 1 being forced into
2104 ;; a register, but not more ugliness here.
2105 (define_insn "*adddi3_plus1_alt"
2106 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2107 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2111 "add %0 = %1, %1, 1"
2112 [(set_attr "itanium_class" "ialu")])
2114 (define_insn "subdi3"
2115 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2116 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2117 (match_operand:DI 2 "gr_register_operand" "r")))]
2120 [(set_attr "itanium_class" "ialu")])
2122 (define_insn "*subdi3_minus1"
2123 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2124 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2125 (match_operand:DI 2 "gr_register_operand" "r")))]
2127 "sub %0 = %2, %1, 1"
2128 [(set_attr "itanium_class" "ialu")])
2130 ;; ??? Use grfr instead of fr because of virtual register elimination
2131 ;; and silly test cases multiplying by the frame pointer.
2132 (define_insn "muldi3"
2133 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2134 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2135 (match_operand:DI 2 "grfr_register_operand" "f")))]
2137 "xmpy.l %0 = %1, %2"
2138 [(set_attr "itanium_class" "xmpy")])
2140 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2141 ;; same problem that we have with shladd below. Unfortunately, this case is
2142 ;; much harder to fix because the multiply puts the result in an FP register,
2143 ;; but the add needs inputs from a general register. We add a spurious clobber
2144 ;; here so that it will be present just in case register elimination gives us
2145 ;; the funny result.
2147 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2149 ;; ??? Maybe we should change how adds are canonicalized.
2151 (define_insn "madddi4"
2152 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2153 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2154 (match_operand:DI 2 "grfr_register_operand" "f"))
2155 (match_operand:DI 3 "grfr_register_operand" "f")))
2156 (clobber (match_scratch:DI 4 "=X"))]
2158 "xma.l %0 = %1, %2, %3"
2159 [(set_attr "itanium_class" "xmpy")])
2161 ;; This can be created by register elimination if operand3 of shladd is an
2162 ;; eliminable register or has reg_equiv_constant set.
2164 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2165 ;; validate_changes call inside eliminate_regs will always succeed. If it
2166 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2169 (define_insn "*madddi4_elim"
2170 [(set (match_operand:DI 0 "register_operand" "=&r")
2171 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2172 (match_operand:DI 2 "register_operand" "f"))
2173 (match_operand:DI 3 "register_operand" "f"))
2174 (match_operand:DI 4 "nonmemory_operand" "rI")))
2175 (clobber (match_scratch:DI 5 "=f"))]
2176 "reload_in_progress"
2178 [(set_attr "itanium_class" "unknown")])
2181 [(set (match_operand:DI 0 "register_operand" "")
2182 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2183 (match_operand:DI 2 "register_operand" ""))
2184 (match_operand:DI 3 "register_operand" ""))
2185 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2186 (clobber (match_scratch:DI 5 ""))]
2188 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2190 (clobber (match_dup 0))])
2191 (set (match_dup 0) (match_dup 5))
2192 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2195 ;; ??? There are highpart multiply and add instructions, but we have no way
2196 ;; to generate them.
2198 (define_insn "smuldi3_highpart"
2199 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2202 (mult:TI (sign_extend:TI
2203 (match_operand:DI 1 "fr_register_operand" "f"))
2205 (match_operand:DI 2 "fr_register_operand" "f")))
2208 "xmpy.h %0 = %1, %2"
2209 [(set_attr "itanium_class" "xmpy")])
2211 (define_insn "umuldi3_highpart"
2212 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2215 (mult:TI (zero_extend:TI
2216 (match_operand:DI 1 "fr_register_operand" "f"))
2218 (match_operand:DI 2 "fr_register_operand" "f")))
2221 "xmpy.hu %0 = %1, %2"
2222 [(set_attr "itanium_class" "xmpy")])
2224 (define_insn "negdi2"
2225 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2226 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2229 [(set_attr "itanium_class" "ialu")])
2231 (define_expand "absdi2"
2233 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2234 (set (match_operand:DI 0 "gr_register_operand" "")
2235 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2236 (neg:DI (match_dup 1))
2239 { operands[2] = gen_reg_rtx (BImode); })
2241 (define_expand "smindi3"
2243 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2244 (match_operand:DI 2 "gr_register_operand" "")))
2245 (set (match_operand:DI 0 "gr_register_operand" "")
2246 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2247 (match_dup 2) (match_dup 1)))]
2249 { operands[3] = gen_reg_rtx (BImode); })
2251 (define_expand "smaxdi3"
2253 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2254 (match_operand:DI 2 "gr_register_operand" "")))
2255 (set (match_operand:DI 0 "gr_register_operand" "")
2256 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2257 (match_dup 1) (match_dup 2)))]
2259 { operands[3] = gen_reg_rtx (BImode); })
2261 (define_expand "umindi3"
2263 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2264 (match_operand:DI 2 "gr_register_operand" "")))
2265 (set (match_operand:DI 0 "gr_register_operand" "")
2266 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2267 (match_dup 2) (match_dup 1)))]
2269 { operands[3] = gen_reg_rtx (BImode); })
2271 (define_expand "umaxdi3"
2273 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2274 (match_operand:DI 2 "gr_register_operand" "")))
2275 (set (match_operand:DI 0 "gr_register_operand" "")
2276 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2277 (match_dup 1) (match_dup 2)))]
2279 { operands[3] = gen_reg_rtx (BImode); })
2281 (define_expand "ffsdi2"
2283 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2284 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2285 (set (match_dup 5) (const_int 0))
2286 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2287 (set (match_dup 4) (popcount:DI (match_dup 3)))
2288 (set (match_operand:DI 0 "gr_register_operand" "")
2289 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2290 (match_dup 5) (match_dup 4)))]
2293 operands[2] = gen_reg_rtx (DImode);
2294 operands[3] = gen_reg_rtx (DImode);
2295 operands[4] = gen_reg_rtx (DImode);
2296 operands[5] = gen_reg_rtx (DImode);
2297 operands[6] = gen_reg_rtx (BImode);
2300 (define_expand "ctzdi2"
2301 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2303 (set (match_dup 3) (not:DI (match_dup 1)))
2304 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2305 (set (match_operand:DI 0 "gr_register_operand" "")
2306 (popcount:DI (match_dup 4)))]
2309 operands[2] = gen_reg_rtx (DImode);
2310 operands[3] = gen_reg_rtx (DImode);
2311 operands[4] = gen_reg_rtx (DImode);
2314 ;; ??? Ought to invent some unspecs for !INTEL_EXTENDED_IEEE_FORMAT.
2315 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2316 (define_expand "clzdi2"
2318 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "")))
2320 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2321 (set (match_dup 4) (const_int 65598))
2322 (set (match_operand:DI 0 "gr_register_operand" "")
2323 (minus:DI (match_dup 4) (match_dup 3)))]
2324 "INTEL_EXTENDED_IEEE_FORMAT"
2326 operands[2] = gen_reg_rtx (TFmode);
2327 operands[3] = gen_reg_rtx (DImode);
2328 operands[4] = gen_reg_rtx (DImode);
2331 (define_insn "popcountdi2"
2332 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2333 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2336 [(set_attr "itanium_class" "mmmul")])
2338 (define_insn "*getf_exp_tf"
2339 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2340 (unspec:DI [(match_operand:TF 1 "fr_register_operand" "f")]
2342 "INTEL_EXTENDED_IEEE_FORMAT"
2344 [(set_attr "itanium_class" "frfr")])
2346 (define_expand "divdi3"
2347 [(set (match_operand:DI 0 "register_operand" "")
2348 (div:DI (match_operand:DI 1 "general_operand" "")
2349 (match_operand:DI 2 "general_operand" "")))]
2350 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2352 rtx op1_tf, op2_tf, op0_tf;
2354 op0_tf = gen_reg_rtx (TFmode);
2356 if (CONSTANT_P (operands[1]))
2357 operands[1] = force_reg (DImode, operands[1]);
2358 op1_tf = gen_reg_rtx (TFmode);
2359 expand_float (op1_tf, operands[1], 0);
2361 if (CONSTANT_P (operands[2]))
2362 operands[2] = force_reg (DImode, operands[2]);
2363 op2_tf = gen_reg_rtx (TFmode);
2364 expand_float (op2_tf, operands[2], 0);
2366 if (TARGET_INLINE_INT_DIV_LAT)
2367 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2369 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2371 emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2375 (define_expand "moddi3"
2376 [(set (match_operand:DI 0 "register_operand" "")
2377 (mod:SI (match_operand:DI 1 "general_operand" "")
2378 (match_operand:DI 2 "general_operand" "")))]
2379 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2383 div = gen_reg_rtx (DImode);
2384 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2386 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2388 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2392 (define_expand "udivdi3"
2393 [(set (match_operand:DI 0 "register_operand" "")
2394 (udiv:DI (match_operand:DI 1 "general_operand" "")
2395 (match_operand:DI 2 "general_operand" "")))]
2396 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2398 rtx op1_tf, op2_tf, op0_tf;
2400 op0_tf = gen_reg_rtx (TFmode);
2402 if (CONSTANT_P (operands[1]))
2403 operands[1] = force_reg (DImode, operands[1]);
2404 op1_tf = gen_reg_rtx (TFmode);
2405 expand_float (op1_tf, operands[1], 1);
2407 if (CONSTANT_P (operands[2]))
2408 operands[2] = force_reg (DImode, operands[2]);
2409 op2_tf = gen_reg_rtx (TFmode);
2410 expand_float (op2_tf, operands[2], 1);
2412 if (TARGET_INLINE_INT_DIV_LAT)
2413 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2415 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2417 emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2421 (define_expand "umoddi3"
2422 [(set (match_operand:DI 0 "register_operand" "")
2423 (umod:DI (match_operand:DI 1 "general_operand" "")
2424 (match_operand:DI 2 "general_operand" "")))]
2425 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2429 div = gen_reg_rtx (DImode);
2430 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2432 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2434 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2438 (define_insn_and_split "divdi3_internal_lat"
2439 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2440 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2441 (match_operand:TF 2 "fr_register_operand" "f"))))
2442 (clobber (match_scratch:TF 3 "=&f"))
2443 (clobber (match_scratch:TF 4 "=&f"))
2444 (clobber (match_scratch:TF 5 "=&f"))
2445 (clobber (match_scratch:BI 6 "=c"))]
2446 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
2448 "&& reload_completed"
2449 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2450 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2451 UNSPEC_FR_RECIP_APPROX))
2452 (use (const_int 1))])
2453 (cond_exec (ne (match_dup 6) (const_int 0))
2454 (parallel [(set (match_dup 3)
2455 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2457 (use (const_int 1))]))
2458 (cond_exec (ne (match_dup 6) (const_int 0))
2459 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2460 (use (const_int 1))]))
2461 (cond_exec (ne (match_dup 6) (const_int 0))
2462 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
2463 (use (const_int 1))]))
2464 (cond_exec (ne (match_dup 6) (const_int 0))
2465 (parallel [(set (match_dup 4)
2466 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
2468 (use (const_int 1))]))
2469 (cond_exec (ne (match_dup 6) (const_int 0))
2470 (parallel [(set (match_dup 0)
2471 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2473 (use (const_int 1))]))
2474 (cond_exec (ne (match_dup 6) (const_int 0))
2475 (parallel [(set (match_dup 3)
2476 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2478 (use (const_int 1))]))
2479 (cond_exec (ne (match_dup 6) (const_int 0))
2480 (parallel [(set (match_dup 0)
2481 (plus:TF (mult:TF (match_dup 5) (match_dup 0))
2483 (use (const_int 1))]))
2484 (cond_exec (ne (match_dup 6) (const_int 0))
2485 (parallel [(set (match_dup 4)
2486 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2488 (use (const_int 1))]))
2489 (cond_exec (ne (match_dup 6) (const_int 0))
2490 (parallel [(set (match_dup 0)
2491 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2493 (use (const_int 1))]))
2495 "operands[7] = CONST1_RTX (TFmode);"
2496 [(set_attr "predicable" "no")])
2498 (define_insn_and_split "divdi3_internal_thr"
2499 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2500 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2501 (match_operand:TF 2 "fr_register_operand" "f"))))
2502 (clobber (match_scratch:TF 3 "=&f"))
2503 (clobber (match_scratch:TF 4 "=f"))
2504 (clobber (match_scratch:BI 5 "=c"))]
2505 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
2507 "&& reload_completed"
2508 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2509 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
2510 UNSPEC_FR_RECIP_APPROX))
2511 (use (const_int 1))])
2512 (cond_exec (ne (match_dup 5) (const_int 0))
2513 (parallel [(set (match_dup 3)
2514 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2516 (use (const_int 1))]))
2517 (cond_exec (ne (match_dup 5) (const_int 0))
2518 (parallel [(set (match_dup 0)
2519 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2521 (use (const_int 1))]))
2522 (cond_exec (ne (match_dup 5) (const_int 0))
2523 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
2524 (use (const_int 1))]))
2525 (cond_exec (ne (match_dup 5) (const_int 0))
2526 (parallel [(set (match_dup 0)
2527 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2529 (use (const_int 1))]))
2530 (cond_exec (ne (match_dup 5) (const_int 0))
2531 (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1)))
2532 (use (const_int 1))]))
2533 (cond_exec (ne (match_dup 5) (const_int 0))
2534 (parallel [(set (match_dup 4)
2535 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2537 (use (const_int 1))]))
2538 (cond_exec (ne (match_dup 5) (const_int 0))
2539 (parallel [(set (match_dup 0)
2540 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2542 (use (const_int 1))]))
2544 "operands[6] = CONST1_RTX (TFmode);"
2545 [(set_attr "predicable" "no")])
2547 ;; ::::::::::::::::::::
2549 ;; :: 32 bit floating point arithmetic
2551 ;; ::::::::::::::::::::
2553 (define_insn "addsf3"
2554 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2555 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2556 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2558 "fadd.s %0 = %1, %F2"
2559 [(set_attr "itanium_class" "fmac")])
2561 (define_insn "subsf3"
2562 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2563 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2564 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2566 "fsub.s %0 = %F1, %F2"
2567 [(set_attr "itanium_class" "fmac")])
2569 (define_insn "mulsf3"
2570 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2571 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2572 (match_operand:SF 2 "fr_register_operand" "f")))]
2574 "fmpy.s %0 = %1, %2"
2575 [(set_attr "itanium_class" "fmac")])
2577 (define_insn "abssf2"
2578 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2579 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2582 [(set_attr "itanium_class" "fmisc")])
2584 (define_insn "negsf2"
2585 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2586 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2589 [(set_attr "itanium_class" "fmisc")])
2591 (define_insn "*nabssf2"
2592 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2593 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2596 [(set_attr "itanium_class" "fmisc")])
2598 (define_insn "minsf3"
2599 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2600 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2601 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2604 [(set_attr "itanium_class" "fmisc")])
2606 (define_insn "maxsf3"
2607 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2608 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2609 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2612 [(set_attr "itanium_class" "fmisc")])
2614 (define_insn "*maddsf4"
2615 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2616 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2617 (match_operand:SF 2 "fr_register_operand" "f"))
2618 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2620 "fma.s %0 = %1, %2, %F3"
2621 [(set_attr "itanium_class" "fmac")])
2623 (define_insn "*msubsf4"
2624 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2625 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2626 (match_operand:SF 2 "fr_register_operand" "f"))
2627 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2629 "fms.s %0 = %1, %2, %F3"
2630 [(set_attr "itanium_class" "fmac")])
2632 (define_insn "*nmulsf3"
2633 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2634 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2635 (match_operand:SF 2 "fr_register_operand" "f"))))]
2637 "fnmpy.s %0 = %1, %2"
2638 [(set_attr "itanium_class" "fmac")])
2640 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2642 (define_insn "*nmaddsf4"
2643 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2644 (plus:SF (neg:SF (mult:SF
2645 (match_operand:SF 1 "fr_register_operand" "f")
2646 (match_operand:SF 2 "fr_register_operand" "f")))
2647 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2649 "fnma.s %0 = %1, %2, %F3"
2650 [(set_attr "itanium_class" "fmac")])
2652 (define_expand "divsf3"
2653 [(set (match_operand:SF 0 "fr_register_operand" "")
2654 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2655 (match_operand:SF 2 "fr_register_operand" "")))]
2656 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
2659 if (TARGET_INLINE_FLOAT_DIV_LAT)
2660 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2662 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2667 (define_insn_and_split "divsf3_internal_lat"
2668 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2669 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2670 (match_operand:SF 2 "fr_register_operand" "f")))
2671 (clobber (match_scratch:TF 3 "=&f"))
2672 (clobber (match_scratch:TF 4 "=f"))
2673 (clobber (match_scratch:BI 5 "=c"))]
2674 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
2676 "&& reload_completed"
2677 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2678 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2679 UNSPEC_FR_RECIP_APPROX))
2680 (use (const_int 1))])
2681 (cond_exec (ne (match_dup 5) (const_int 0))
2682 (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
2683 (use (const_int 1))]))
2684 (cond_exec (ne (match_dup 5) (const_int 0))
2685 (parallel [(set (match_dup 4)
2686 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2688 (use (const_int 1))]))
2689 (cond_exec (ne (match_dup 5) (const_int 0))
2690 (parallel [(set (match_dup 3)
2691 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2693 (use (const_int 1))]))
2694 (cond_exec (ne (match_dup 5) (const_int 0))
2695 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2696 (use (const_int 1))]))
2697 (cond_exec (ne (match_dup 5) (const_int 0))
2698 (parallel [(set (match_dup 3)
2699 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2701 (use (const_int 1))]))
2702 (cond_exec (ne (match_dup 5) (const_int 0))
2703 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2704 (use (const_int 1))]))
2705 (cond_exec (ne (match_dup 5) (const_int 0))
2706 (parallel [(set (match_dup 9)
2708 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2710 (use (const_int 1))]))
2711 (cond_exec (ne (match_dup 5) (const_int 0))
2713 (float_truncate:SF (match_dup 6))))
2716 operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2717 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2718 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2719 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
2720 operands[10] = CONST1_RTX (TFmode);
2722 [(set_attr "predicable" "no")])
2724 (define_insn_and_split "divsf3_internal_thr"
2725 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2726 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2727 (match_operand:SF 2 "fr_register_operand" "f")))
2728 (clobber (match_scratch:TF 3 "=&f"))
2729 (clobber (match_scratch:TF 4 "=f"))
2730 (clobber (match_scratch:BI 5 "=c"))]
2731 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
2733 "&& reload_completed"
2734 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2735 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2736 UNSPEC_FR_RECIP_APPROX))
2737 (use (const_int 1))])
2738 (cond_exec (ne (match_dup 5) (const_int 0))
2739 (parallel [(set (match_dup 3)
2740 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2742 (use (const_int 1))]))
2743 (cond_exec (ne (match_dup 5) (const_int 0))
2744 (parallel [(set (match_dup 3)
2745 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
2747 (use (const_int 1))]))
2748 (cond_exec (ne (match_dup 5) (const_int 0))
2749 (parallel [(set (match_dup 6)
2750 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
2752 (use (const_int 1))]))
2753 (cond_exec (ne (match_dup 5) (const_int 0))
2754 (parallel [(set (match_dup 9)
2756 (mult:TF (match_dup 7) (match_dup 6))))
2757 (use (const_int 1))]))
2758 (cond_exec (ne (match_dup 5) (const_int 0))
2759 (parallel [(set (match_dup 4)
2760 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3)))
2762 (use (const_int 1))]))
2763 (cond_exec (ne (match_dup 5) (const_int 0))
2766 (plus:TF (mult:TF (match_dup 4) (match_dup 6))
2770 operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2771 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2772 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2773 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
2774 operands[10] = CONST1_RTX (TFmode);
2776 [(set_attr "predicable" "no")])
2778 ;; ::::::::::::::::::::
2780 ;; :: 64 bit floating point arithmetic
2782 ;; ::::::::::::::::::::
2784 (define_insn "adddf3"
2785 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2786 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2787 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2789 "fadd.d %0 = %1, %F2"
2790 [(set_attr "itanium_class" "fmac")])
2792 (define_insn "*adddf3_trunc"
2793 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2795 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2796 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2798 "fadd.s %0 = %1, %F2"
2799 [(set_attr "itanium_class" "fmac")])
2801 (define_insn "subdf3"
2802 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2803 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2804 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2806 "fsub.d %0 = %F1, %F2"
2807 [(set_attr "itanium_class" "fmac")])
2809 (define_insn "*subdf3_trunc"
2810 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2812 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2813 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2815 "fsub.s %0 = %F1, %F2"
2816 [(set_attr "itanium_class" "fmac")])
2818 (define_insn "muldf3"
2819 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2820 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2821 (match_operand:DF 2 "fr_register_operand" "f")))]
2823 "fmpy.d %0 = %1, %2"
2824 [(set_attr "itanium_class" "fmac")])
2826 (define_insn "*muldf3_trunc"
2827 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2829 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2830 (match_operand:DF 2 "fr_register_operand" "f"))))]
2832 "fmpy.s %0 = %1, %2"
2833 [(set_attr "itanium_class" "fmac")])
2835 (define_insn "absdf2"
2836 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2837 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
2840 [(set_attr "itanium_class" "fmisc")])
2842 (define_insn "negdf2"
2843 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2844 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
2847 [(set_attr "itanium_class" "fmisc")])
2849 (define_insn "*nabsdf2"
2850 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2851 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
2854 [(set_attr "itanium_class" "fmisc")])
2856 (define_insn "mindf3"
2857 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2858 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
2859 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2862 [(set_attr "itanium_class" "fmisc")])
2864 (define_insn "maxdf3"
2865 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2866 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
2867 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2870 [(set_attr "itanium_class" "fmisc")])
2872 (define_insn "*madddf4"
2873 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2874 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2875 (match_operand:DF 2 "fr_register_operand" "f"))
2876 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2878 "fma.d %0 = %1, %2, %F3"
2879 [(set_attr "itanium_class" "fmac")])
2881 (define_insn "*madddf4_trunc"
2882 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2884 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2885 (match_operand:DF 2 "fr_register_operand" "f"))
2886 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2888 "fma.s %0 = %1, %2, %F3"
2889 [(set_attr "itanium_class" "fmac")])
2891 (define_insn "*msubdf4"
2892 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2893 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2894 (match_operand:DF 2 "fr_register_operand" "f"))
2895 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2897 "fms.d %0 = %1, %2, %F3"
2898 [(set_attr "itanium_class" "fmac")])
2900 (define_insn "*msubdf4_trunc"
2901 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2903 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2904 (match_operand:DF 2 "fr_register_operand" "f"))
2905 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2907 "fms.s %0 = %1, %2, %F3"
2908 [(set_attr "itanium_class" "fmac")])
2910 (define_insn "*nmuldf3"
2911 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2912 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2913 (match_operand:DF 2 "fr_register_operand" "f"))))]
2915 "fnmpy.d %0 = %1, %2"
2916 [(set_attr "itanium_class" "fmac")])
2918 (define_insn "*nmuldf3_trunc"
2919 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2921 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2922 (match_operand:DF 2 "fr_register_operand" "f")))))]
2924 "fnmpy.s %0 = %1, %2"
2925 [(set_attr "itanium_class" "fmac")])
2927 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2929 (define_insn "*nmadddf4"
2930 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2931 (plus:DF (neg:DF (mult:DF
2932 (match_operand:DF 1 "fr_register_operand" "f")
2933 (match_operand:DF 2 "fr_register_operand" "f")))
2934 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2936 "fnma.d %0 = %1, %2, %F3"
2937 [(set_attr "itanium_class" "fmac")])
2939 (define_insn "*nmadddf4_alts"
2940 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2941 (plus:DF (neg:DF (mult:DF
2942 (match_operand:DF 1 "fr_register_operand" "f")
2943 (match_operand:DF 2 "fr_register_operand" "f")))
2944 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))
2945 (use (match_operand:SI 4 "const_int_operand" ""))]
2947 "fnma.d.s%4 %0 = %1, %2, %F3"
2948 [(set_attr "itanium_class" "fmac")])
2950 (define_insn "*nmadddf4_trunc"
2951 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2953 (plus:DF (neg:DF (mult:DF
2954 (match_operand:DF 1 "fr_register_operand" "f")
2955 (match_operand:DF 2 "fr_register_operand" "f")))
2956 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2958 "fnma.s %0 = %1, %2, %F3"
2959 [(set_attr "itanium_class" "fmac")])
2961 (define_expand "divdf3"
2962 [(set (match_operand:DF 0 "fr_register_operand" "")
2963 (div:DF (match_operand:DF 1 "fr_register_operand" "")
2964 (match_operand:DF 2 "fr_register_operand" "")))]
2965 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
2968 if (TARGET_INLINE_FLOAT_DIV_LAT)
2969 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
2971 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
2976 (define_insn_and_split "divdf3_internal_lat"
2977 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
2978 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
2979 (match_operand:DF 2 "fr_register_operand" "f")))
2980 (clobber (match_scratch:TF 3 "=&f"))
2981 (clobber (match_scratch:TF 4 "=&f"))
2982 (clobber (match_scratch:TF 5 "=&f"))
2983 (clobber (match_scratch:BI 6 "=c"))]
2984 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
2986 "&& reload_completed"
2987 [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
2988 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
2989 UNSPEC_FR_RECIP_APPROX))
2990 (use (const_int 1))])
2991 (cond_exec (ne (match_dup 6) (const_int 0))
2992 (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
2993 (use (const_int 1))]))
2994 (cond_exec (ne (match_dup 6) (const_int 0))
2995 (parallel [(set (match_dup 4)
2996 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7)))
2998 (use (const_int 1))]))
2999 (cond_exec (ne (match_dup 6) (const_int 0))
3000 (parallel [(set (match_dup 3)
3001 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3003 (use (const_int 1))]))
3004 (cond_exec (ne (match_dup 6) (const_int 0))
3005 (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4)))
3006 (use (const_int 1))]))
3007 (cond_exec (ne (match_dup 6) (const_int 0))
3008 (parallel [(set (match_dup 7)
3009 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3011 (use (const_int 1))]))
3012 (cond_exec (ne (match_dup 6) (const_int 0))
3013 (parallel [(set (match_dup 3)
3014 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3016 (use (const_int 1))]))
3017 (cond_exec (ne (match_dup 6) (const_int 0))
3018 (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5)))
3019 (use (const_int 1))]))
3020 (cond_exec (ne (match_dup 6) (const_int 0))
3021 (parallel [(set (match_dup 7)
3022 (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3024 (use (const_int 1))]))
3025 (cond_exec (ne (match_dup 6) (const_int 0))
3026 (parallel [(set (match_dup 10)
3028 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3030 (use (const_int 1))]))
3031 (cond_exec (ne (match_dup 6) (const_int 0))
3032 (parallel [(set (match_dup 7)
3033 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3035 (use (const_int 1))]))
3036 (cond_exec (ne (match_dup 6) (const_int 0))
3037 (parallel [(set (match_dup 11)
3039 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3)))
3041 (use (const_int 1))]))
3042 (cond_exec (ne (match_dup 6) (const_int 0))
3044 (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3048 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3049 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3050 operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3051 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3052 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3053 operands[12] = CONST1_RTX (TFmode);
3055 [(set_attr "predicable" "no")])
3057 (define_insn_and_split "divdf3_internal_thr"
3058 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3059 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3060 (match_operand:DF 2 "fr_register_operand" "f")))
3061 (clobber (match_scratch:TF 3 "=&f"))
3062 (clobber (match_scratch:DF 4 "=f"))
3063 (clobber (match_scratch:BI 5 "=c"))]
3064 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
3066 "&& reload_completed"
3067 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
3068 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3069 UNSPEC_FR_RECIP_APPROX))
3070 (use (const_int 1))])
3071 (cond_exec (ne (match_dup 5) (const_int 0))
3072 (parallel [(set (match_dup 3)
3073 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
3075 (use (const_int 1))]))
3076 (cond_exec (ne (match_dup 5) (const_int 0))
3077 (parallel [(set (match_dup 6)
3078 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3080 (use (const_int 1))]))
3081 (cond_exec (ne (match_dup 5) (const_int 0))
3082 (parallel [(set (match_dup 3)
3083 (mult:TF (match_dup 3) (match_dup 3)))
3084 (use (const_int 1))]))
3085 (cond_exec (ne (match_dup 5) (const_int 0))
3086 (parallel [(set (match_dup 6)
3087 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3089 (use (const_int 1))]))
3090 (cond_exec (ne (match_dup 5) (const_int 0))
3091 (parallel [(set (match_dup 3)
3092 (mult:TF (match_dup 3) (match_dup 3)))
3093 (use (const_int 1))]))
3094 (cond_exec (ne (match_dup 5) (const_int 0))
3095 (parallel [(set (match_dup 6)
3096 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3098 (use (const_int 1))]))
3099 (cond_exec (ne (match_dup 5) (const_int 0))
3100 (parallel [(set (match_dup 9)
3102 (mult:TF (match_dup 7) (match_dup 3))))
3103 (use (const_int 1))]))
3104 (cond_exec (ne (match_dup 5) (const_int 0))
3105 (parallel [(set (match_dup 4)
3106 (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9)))
3108 (use (const_int 1))]))
3109 (cond_exec (ne (match_dup 5) (const_int 0))
3111 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3115 operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3116 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3117 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3118 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3119 operands[10] = CONST1_RTX (TFmode);
3121 [(set_attr "predicable" "no")])
3123 ;; ::::::::::::::::::::
3125 ;; :: 80 bit floating point arithmetic
3127 ;; ::::::::::::::::::::
3129 (define_insn "addtf3"
3130 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3131 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3132 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3133 "INTEL_EXTENDED_IEEE_FORMAT"
3134 "fadd %0 = %F1, %F2"
3135 [(set_attr "itanium_class" "fmac")])
3137 (define_insn "*addtf3_truncsf"
3138 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3140 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3141 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3142 "INTEL_EXTENDED_IEEE_FORMAT"
3143 "fadd.s %0 = %F1, %F2"
3144 [(set_attr "itanium_class" "fmac")])
3146 (define_insn "*addtf3_truncdf"
3147 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3149 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3150 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3151 "INTEL_EXTENDED_IEEE_FORMAT"
3152 "fadd.d %0 = %F1, %F2"
3153 [(set_attr "itanium_class" "fmac")])
3155 (define_insn "subtf3"
3156 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3157 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3158 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3159 "INTEL_EXTENDED_IEEE_FORMAT"
3160 "fsub %0 = %F1, %F2"
3161 [(set_attr "itanium_class" "fmac")])
3163 (define_insn "*subtf3_truncsf"
3164 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3166 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3167 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3168 "INTEL_EXTENDED_IEEE_FORMAT"
3169 "fsub.s %0 = %F1, %F2"
3170 [(set_attr "itanium_class" "fmac")])
3172 (define_insn "*subtf3_truncdf"
3173 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3175 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3176 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3177 "INTEL_EXTENDED_IEEE_FORMAT"
3178 "fsub.d %0 = %F1, %F2"
3179 [(set_attr "itanium_class" "fmac")])
3181 (define_insn "multf3"
3182 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3183 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3184 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3185 "INTEL_EXTENDED_IEEE_FORMAT"
3186 "fmpy %0 = %F1, %F2"
3187 [(set_attr "itanium_class" "fmac")])
3189 (define_insn "*multf3_truncsf"
3190 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3192 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3193 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3194 "INTEL_EXTENDED_IEEE_FORMAT"
3195 "fmpy.s %0 = %F1, %F2"
3196 [(set_attr "itanium_class" "fmac")])
3198 (define_insn "*multf3_truncdf"
3199 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3201 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3202 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3203 "INTEL_EXTENDED_IEEE_FORMAT"
3204 "fmpy.d %0 = %F1, %F2"
3205 [(set_attr "itanium_class" "fmac")])
3207 (define_insn "*multf3_alts"
3208 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3209 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3210 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3211 (use (match_operand:SI 3 "const_int_operand" ""))]
3212 "INTEL_EXTENDED_IEEE_FORMAT"
3213 "fmpy.s%3 %0 = %F1, %F2"
3214 [(set_attr "itanium_class" "fmac")])
3216 (define_insn "*multf3_truncsf_alts"
3217 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3219 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3220 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3221 (use (match_operand:SI 3 "const_int_operand" ""))]
3222 "INTEL_EXTENDED_IEEE_FORMAT"
3223 "fmpy.s.s%3 %0 = %F1, %F2"
3224 [(set_attr "itanium_class" "fmac")])
3226 (define_insn "*multf3_truncdf_alts"
3227 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3229 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3230 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3231 (use (match_operand:SI 3 "const_int_operand" ""))]
3232 "INTEL_EXTENDED_IEEE_FORMAT"
3233 "fmpy.d.s%3 %0 = %F1, %F2"
3234 [(set_attr "itanium_class" "fmac")])
3236 (define_insn "abstf2"
3237 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3238 (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3239 "INTEL_EXTENDED_IEEE_FORMAT"
3241 [(set_attr "itanium_class" "fmisc")])
3243 (define_insn "negtf2"
3244 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3245 (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3246 "INTEL_EXTENDED_IEEE_FORMAT"
3248 [(set_attr "itanium_class" "fmisc")])
3250 (define_insn "*nabstf2"
3251 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3252 (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
3253 "INTEL_EXTENDED_IEEE_FORMAT"
3255 [(set_attr "itanium_class" "fmisc")])
3257 (define_insn "mintf3"
3258 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3259 (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3260 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3261 "INTEL_EXTENDED_IEEE_FORMAT"
3262 "fmin %0 = %F1, %F2"
3263 [(set_attr "itanium_class" "fmisc")])
3265 (define_insn "maxtf3"
3266 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3267 (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3268 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3269 "INTEL_EXTENDED_IEEE_FORMAT"
3270 "fmax %0 = %F1, %F2"
3271 [(set_attr "itanium_class" "fmisc")])
3273 (define_insn "*maddtf4"
3274 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3275 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3276 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3277 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3278 "INTEL_EXTENDED_IEEE_FORMAT"
3279 "fma %0 = %F1, %F2, %F3"
3280 [(set_attr "itanium_class" "fmac")])
3282 (define_insn "*maddtf4_truncsf"
3283 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3285 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3286 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3287 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3288 "INTEL_EXTENDED_IEEE_FORMAT"
3289 "fma.s %0 = %F1, %F2, %F3"
3290 [(set_attr "itanium_class" "fmac")])
3292 (define_insn "*maddtf4_truncdf"
3293 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3295 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3296 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3297 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3298 "INTEL_EXTENDED_IEEE_FORMAT"
3299 "fma.d %0 = %F1, %F2, %F3"
3300 [(set_attr "itanium_class" "fmac")])
3302 (define_insn "*maddtf4_alts"
3303 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3304 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3305 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3306 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3307 (use (match_operand:SI 4 "const_int_operand" ""))]
3308 "INTEL_EXTENDED_IEEE_FORMAT"
3309 "fma.s%4 %0 = %F1, %F2, %F3"
3310 [(set_attr "itanium_class" "fmac")])
3312 (define_insn "*maddtf4_alts_truncdf"
3313 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3315 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3316 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3317 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3318 (use (match_operand:SI 4 "const_int_operand" ""))]
3319 "INTEL_EXTENDED_IEEE_FORMAT"
3320 "fma.d.s%4 %0 = %F1, %F2, %F3"
3321 [(set_attr "itanium_class" "fmac")])
3323 (define_insn "*msubtf4"
3324 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3325 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3326 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3327 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3328 "INTEL_EXTENDED_IEEE_FORMAT"
3329 "fms %0 = %F1, %F2, %F3"
3330 [(set_attr "itanium_class" "fmac")])
3332 (define_insn "*msubtf4_truncsf"
3333 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3335 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3336 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3337 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3338 "INTEL_EXTENDED_IEEE_FORMAT"
3339 "fms.s %0 = %F1, %F2, %F3"
3340 [(set_attr "itanium_class" "fmac")])
3342 (define_insn "*msubtf4_truncdf"
3343 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3345 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3346 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3347 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3348 "INTEL_EXTENDED_IEEE_FORMAT"
3349 "fms.d %0 = %F1, %F2, %F3"
3350 [(set_attr "itanium_class" "fmac")])
3352 (define_insn "*nmultf3"
3353 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3354 (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3355 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3356 "INTEL_EXTENDED_IEEE_FORMAT"
3357 "fnmpy %0 = %F1, %F2"
3358 [(set_attr "itanium_class" "fmac")])
3360 (define_insn "*nmultf3_truncsf"
3361 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3364 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3365 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3366 "INTEL_EXTENDED_IEEE_FORMAT"
3367 "fnmpy.s %0 = %F1, %F2"
3368 [(set_attr "itanium_class" "fmac")])
3370 (define_insn "*nmultf3_truncdf"
3371 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3374 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3375 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3376 "INTEL_EXTENDED_IEEE_FORMAT"
3377 "fnmpy.d %0 = %F1, %F2"
3378 [(set_attr "itanium_class" "fmac")])
3380 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3382 (define_insn "*nmaddtf4"
3383 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3384 (plus:TF (neg:TF (mult:TF
3385 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3386 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3387 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3388 "INTEL_EXTENDED_IEEE_FORMAT"
3389 "fnma %0 = %F1, %F2, %F3"
3390 [(set_attr "itanium_class" "fmac")])
3392 (define_insn "*nmaddtf4_truncsf"
3393 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3395 (plus:TF (neg:TF (mult:TF
3396 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3397 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3398 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3399 "INTEL_EXTENDED_IEEE_FORMAT"
3400 "fnma.s %0 = %F1, %F2, %F3"
3401 [(set_attr "itanium_class" "fmac")])
3403 (define_insn "*nmaddtf4_truncdf"
3404 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3406 (plus:TF (neg:TF (mult:TF
3407 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3408 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3409 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3410 "INTEL_EXTENDED_IEEE_FORMAT"
3411 "fnma.d %0 = %F1, %F2, %F3"
3412 [(set_attr "itanium_class" "fmac")])
3414 (define_insn "*nmaddtf4_alts"
3415 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3416 (plus:TF (neg:TF (mult:TF
3417 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3418 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3419 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3420 (use (match_operand:SI 4 "const_int_operand" ""))]
3421 "INTEL_EXTENDED_IEEE_FORMAT"
3422 "fnma.s%4 %0 = %F1, %F2, %F3"
3423 [(set_attr "itanium_class" "fmac")])
3425 (define_insn "*nmaddtf4_truncdf_alts"
3426 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3430 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3431 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3432 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3433 (use (match_operand:SI 4 "const_int_operand" ""))]
3434 "INTEL_EXTENDED_IEEE_FORMAT"
3435 "fnma.d.s%4 %0 = %F1, %F2, %F3"
3436 [(set_attr "itanium_class" "fmac")])
3438 (define_expand "divtf3"
3439 [(set (match_operand:TF 0 "fr_register_operand" "")
3440 (div:TF (match_operand:TF 1 "fr_register_operand" "")
3441 (match_operand:TF 2 "fr_register_operand" "")))]
3442 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
3445 if (TARGET_INLINE_FLOAT_DIV_LAT)
3446 insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
3448 insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
3453 (define_insn_and_split "divtf3_internal_lat"
3454 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3455 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3456 (match_operand:TF 2 "fr_register_operand" "f")))
3457 (clobber (match_scratch:TF 3 "=&f"))
3458 (clobber (match_scratch:TF 4 "=&f"))
3459 (clobber (match_scratch:TF 5 "=&f"))
3460 (clobber (match_scratch:TF 6 "=&f"))
3461 (clobber (match_scratch:BI 7 "=c"))]
3462 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
3464 "&& reload_completed"
3465 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3466 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
3467 UNSPEC_FR_RECIP_APPROX))
3468 (use (const_int 1))])
3469 (cond_exec (ne (match_dup 7) (const_int 0))
3470 (parallel [(set (match_dup 3)
3471 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3473 (use (const_int 1))]))
3474 (cond_exec (ne (match_dup 7) (const_int 0))
3475 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3476 (use (const_int 1))]))
3477 (cond_exec (ne (match_dup 7) (const_int 0))
3478 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
3479 (use (const_int 1))]))
3480 (cond_exec (ne (match_dup 7) (const_int 0))
3481 (parallel [(set (match_dup 6)
3482 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
3484 (use (const_int 1))]))
3485 (cond_exec (ne (match_dup 7) (const_int 0))
3486 (parallel [(set (match_dup 3)
3487 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
3489 (use (const_int 1))]))
3490 (cond_exec (ne (match_dup 7) (const_int 0))
3491 (parallel [(set (match_dup 5)
3492 (plus:TF (mult:TF (match_dup 6) (match_dup 0))
3494 (use (const_int 1))]))
3495 (cond_exec (ne (match_dup 7) (const_int 0))
3496 (parallel [(set (match_dup 0)
3497 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3499 (use (const_int 1))]))
3500 (cond_exec (ne (match_dup 7) (const_int 0))
3501 (parallel [(set (match_dup 4)
3502 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3504 (use (const_int 1))]))
3505 (cond_exec (ne (match_dup 7) (const_int 0))
3506 (parallel [(set (match_dup 3)
3507 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3509 (use (const_int 1))]))
3510 (cond_exec (ne (match_dup 7) (const_int 0))
3511 (parallel [(set (match_dup 5)
3512 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3514 (use (const_int 1))]))
3515 (cond_exec (ne (match_dup 7) (const_int 0))
3516 (parallel [(set (match_dup 0)
3517 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3519 (use (const_int 1))]))
3520 (cond_exec (ne (match_dup 7) (const_int 0))
3521 (parallel [(set (match_dup 4)
3522 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3524 (use (const_int 1))]))
3525 (cond_exec (ne (match_dup 7) (const_int 0))
3527 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3530 "operands[8] = CONST1_RTX (TFmode);"
3531 [(set_attr "predicable" "no")])
3533 (define_insn_and_split "divtf3_internal_thr"
3534 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3535 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3536 (match_operand:TF 2 "fr_register_operand" "f")))
3537 (clobber (match_scratch:TF 3 "=&f"))
3538 (clobber (match_scratch:TF 4 "=&f"))
3539 (clobber (match_scratch:BI 5 "=c"))]
3540 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
3542 "&& reload_completed"
3543 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3544 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
3545 UNSPEC_FR_RECIP_APPROX))
3546 (use (const_int 1))])
3547 (cond_exec (ne (match_dup 5) (const_int 0))
3548 (parallel [(set (match_dup 3)
3549 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3551 (use (const_int 1))]))
3552 (cond_exec (ne (match_dup 5) (const_int 0))
3553 (parallel [(set (match_dup 4)
3554 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3556 (use (const_int 1))]))
3557 (cond_exec (ne (match_dup 5) (const_int 0))
3558 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
3559 (use (const_int 1))]))
3560 (cond_exec (ne (match_dup 5) (const_int 0))
3561 (parallel [(set (match_dup 3)
3562 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
3564 (use (const_int 1))]))
3565 (cond_exec (ne (match_dup 5) (const_int 0))
3566 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3567 (use (const_int 1))]))
3568 (cond_exec (ne (match_dup 5) (const_int 0))
3569 (parallel [(set (match_dup 0)
3570 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3572 (use (const_int 1))]))
3573 (cond_exec (ne (match_dup 5) (const_int 0))
3574 (parallel [(set (match_dup 0)
3575 (plus:TF (mult:TF (match_dup 0) (match_dup 3))
3577 (use (const_int 1))]))
3578 (cond_exec (ne (match_dup 5) (const_int 0))
3579 (parallel [(set (match_dup 3)
3580 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3582 (use (const_int 1))]))
3583 (cond_exec (ne (match_dup 5) (const_int 0))
3584 (parallel [(set (match_dup 3)
3585 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3587 (use (const_int 1))]))
3588 (cond_exec (ne (match_dup 5) (const_int 0))
3589 (parallel [(set (match_dup 4)
3590 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3592 (use (const_int 1))]))
3593 (cond_exec (ne (match_dup 5) (const_int 0))
3594 (parallel [(set (match_dup 0)
3595 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3597 (use (const_int 1))]))
3598 (cond_exec (ne (match_dup 5) (const_int 0))
3599 (parallel [(set (match_dup 4)
3600 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3602 (use (const_int 1))]))
3603 (cond_exec (ne (match_dup 5) (const_int 0))
3605 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3608 "operands[6] = CONST1_RTX (TFmode);"
3609 [(set_attr "predicable" "no")])
3611 ;; ??? frcpa works like cmp.foo.unc.
3613 (define_insn "*recip_approx"
3614 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3615 (div:TF (const_int 1)
3616 (match_operand:TF 3 "fr_register_operand" "f")))
3617 (set (match_operand:BI 1 "register_operand" "=c")
3618 (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
3619 (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
3620 (use (match_operand:SI 4 "const_int_operand" ""))]
3621 "INTEL_EXTENDED_IEEE_FORMAT"
3622 "frcpa.s%4 %0, %1 = %2, %3"
3623 [(set_attr "itanium_class" "fmisc")
3624 (set_attr "predicable" "no")])
3626 ;; ::::::::::::::::::::
3628 ;; :: 32 bit Integer Shifts and Rotates
3630 ;; ::::::::::::::::::::
3632 (define_expand "ashlsi3"
3633 [(set (match_operand:SI 0 "gr_register_operand" "")
3634 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3635 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3638 if (GET_CODE (operands[2]) != CONST_INT)
3640 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3641 we've got to get rid of stray bits outside the SImode register. */
3642 rtx subshift = gen_reg_rtx (DImode);
3643 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3644 operands[2] = subshift;
3648 (define_insn "*ashlsi3_internal"
3649 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3650 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3651 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
3654 shladd %0 = %1, %2, r0
3655 dep.z %0 = %1, %2, %E2
3657 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
3659 (define_expand "ashrsi3"
3660 [(set (match_operand:SI 0 "gr_register_operand" "")
3661 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3662 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3665 rtx subtarget = gen_reg_rtx (DImode);
3666 if (GET_CODE (operands[2]) == CONST_INT)
3667 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3668 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3671 rtx subshift = gen_reg_rtx (DImode);
3672 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
3673 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3674 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
3676 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3680 (define_expand "lshrsi3"
3681 [(set (match_operand:SI 0 "gr_register_operand" "")
3682 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3683 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3686 rtx subtarget = gen_reg_rtx (DImode);
3687 if (GET_CODE (operands[2]) == CONST_INT)
3688 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3689 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3692 rtx subshift = gen_reg_rtx (DImode);
3693 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
3694 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3695 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
3697 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3701 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
3702 ;; here, instead of 64 like the patterns above. Keep the pattern together
3703 ;; until after combine; otherwise it won't get matched often.
3705 (define_expand "rotrsi3"
3706 [(set (match_operand:SI 0 "gr_register_operand" "")
3707 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3708 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3711 if (GET_MODE (operands[2]) != VOIDmode)
3713 rtx tmp = gen_reg_rtx (DImode);
3714 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3719 (define_insn_and_split "*rotrsi3_internal"
3720 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3721 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3722 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3727 (ior:DI (zero_extend:DI (match_dup 1))
3728 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3730 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3731 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3733 (define_expand "rotlsi3"
3734 [(set (match_operand:SI 0 "gr_register_operand" "")
3735 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3736 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3739 if (! shift_32bit_count_operand (operands[2], SImode))
3741 rtx tmp = gen_reg_rtx (SImode);
3742 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3743 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3748 (define_insn_and_split "*rotlsi3_internal"
3749 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3750 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3751 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3756 (ior:DI (zero_extend:DI (match_dup 1))
3757 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3759 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3761 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
3762 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
3765 ;; ::::::::::::::::::::
3767 ;; :: 64 bit Integer Shifts and Rotates
3769 ;; ::::::::::::::::::::
3771 (define_insn "ashldi3"
3772 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
3773 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
3774 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
3777 shladd %0 = %1, %2, r0
3780 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
3782 ;; ??? Maybe combine this with the multiply and add instruction?
3784 (define_insn "*shladd"
3785 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3786 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3787 (match_operand:DI 2 "shladd_operand" "n"))
3788 (match_operand:DI 3 "gr_register_operand" "r")))]
3790 "shladd %0 = %1, %S2, %3"
3791 [(set_attr "itanium_class" "ialu")])
3793 ;; This can be created by register elimination if operand3 of shladd is an
3794 ;; eliminable register or has reg_equiv_constant set.
3796 ;; We have to use nonmemory_operand for operand 4, to ensure that the
3797 ;; validate_changes call inside eliminate_regs will always succeed. If it
3798 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3801 (define_insn_and_split "*shladd_elim"
3802 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3803 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3804 (match_operand:DI 2 "shladd_operand" "n"))
3805 (match_operand:DI 3 "nonmemory_operand" "r"))
3806 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3807 "reload_in_progress"
3810 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3812 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
3814 [(set_attr "itanium_class" "unknown")])
3816 (define_insn "ashrdi3"
3817 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3818 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3819 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3824 [(set_attr "itanium_class" "mmshf,mmshfi")])
3826 (define_insn "lshrdi3"
3827 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3828 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3829 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3834 [(set_attr "itanium_class" "mmshf,mmshfi")])
3836 ;; Using a predicate that accepts only constants doesn't work, because optabs
3837 ;; will load the operand into a register and call the pattern if the predicate
3838 ;; did not accept it on the first try. So we use nonmemory_operand and then
3839 ;; verify that we have an appropriate constant in the expander.
3841 (define_expand "rotrdi3"
3842 [(set (match_operand:DI 0 "gr_register_operand" "")
3843 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
3844 (match_operand:DI 2 "nonmemory_operand" "")))]
3847 if (! shift_count_operand (operands[2], DImode))
3851 (define_insn "*rotrdi3_internal"
3852 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3853 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
3854 (match_operand:DI 2 "shift_count_operand" "M")))]
3856 "shrp %0 = %1, %1, %2"
3857 [(set_attr "itanium_class" "ishf")])
3859 (define_expand "rotldi3"
3860 [(set (match_operand:DI 0 "gr_register_operand" "")
3861 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
3862 (match_operand:DI 2 "nonmemory_operand" "")))]
3865 if (! shift_count_operand (operands[2], DImode))
3869 (define_insn "*rotldi3_internal"
3870 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3871 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
3872 (match_operand:DI 2 "shift_count_operand" "M")))]
3874 "shrp %0 = %1, %1, %e2"
3875 [(set_attr "itanium_class" "ishf")])
3877 ;; ::::::::::::::::::::
3879 ;; :: 32 bit Integer Logical operations
3881 ;; ::::::::::::::::::::
3883 ;; We don't seem to need any other 32-bit logical operations, because gcc
3884 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3885 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3886 ;; This doesn't work for unary logical operations, because we don't call
3887 ;; apply_distributive_law for them.
3889 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3890 ;; apply_distributive_law. We get inefficient code for
3891 ;; int sub4 (int i, int j) { return i & ~j; }
3892 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3893 ;; (zero_extend (and (not A) B)) in combine.
3894 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3895 ;; one_cmplsi2 pattern.
3897 (define_insn "one_cmplsi2"
3898 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3899 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
3902 [(set_attr "itanium_class" "ilog")])
3904 ;; ::::::::::::::::::::
3906 ;; :: 64 bit Integer Logical operations
3908 ;; ::::::::::::::::::::
3910 (define_insn "anddi3"
3911 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3912 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3913 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3918 [(set_attr "itanium_class" "ilog,fmisc")])
3920 (define_insn "*andnot"
3921 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3922 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
3923 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3928 [(set_attr "itanium_class" "ilog,fmisc")])
3930 (define_insn "iordi3"
3931 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3932 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3933 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3938 [(set_attr "itanium_class" "ilog,fmisc")])
3940 (define_insn "xordi3"
3941 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3942 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3943 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3948 [(set_attr "itanium_class" "ilog,fmisc")])
3950 (define_insn "one_cmpldi2"
3951 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3952 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
3955 [(set_attr "itanium_class" "ilog")])
3957 ;; ::::::::::::::::::::
3961 ;; ::::::::::::::::::::
3963 (define_expand "cmpbi"
3965 (compare (match_operand:BI 0 "register_operand" "")
3966 (match_operand:BI 1 "const_int_operand" "")))]
3969 ia64_compare_op0 = operands[0];
3970 ia64_compare_op1 = operands[1];
3974 (define_expand "cmpsi"
3976 (compare (match_operand:SI 0 "gr_register_operand" "")
3977 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
3980 ia64_compare_op0 = operands[0];
3981 ia64_compare_op1 = operands[1];
3985 (define_expand "cmpdi"
3987 (compare (match_operand:DI 0 "gr_register_operand" "")
3988 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
3991 ia64_compare_op0 = operands[0];
3992 ia64_compare_op1 = operands[1];
3996 (define_expand "cmpsf"
3998 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
3999 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
4002 ia64_compare_op0 = operands[0];
4003 ia64_compare_op1 = operands[1];
4007 (define_expand "cmpdf"
4009 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
4010 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
4013 ia64_compare_op0 = operands[0];
4014 ia64_compare_op1 = operands[1];
4018 (define_expand "cmptf"
4020 (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
4021 (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
4022 "INTEL_EXTENDED_IEEE_FORMAT"
4024 ia64_compare_op0 = operands[0];
4025 ia64_compare_op1 = operands[1];
4029 (define_insn "*cmpsi_normal"
4030 [(set (match_operand:BI 0 "register_operand" "=c")
4031 (match_operator:BI 1 "normal_comparison_operator"
4032 [(match_operand:SI 2 "gr_register_operand" "r")
4033 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
4035 "cmp4.%C1 %0, %I0 = %3, %2"
4036 [(set_attr "itanium_class" "icmp")])
4038 ;; We use %r3 because it is possible for us to match a 0, and two of the
4039 ;; unsigned comparisons don't accept immediate operands of zero.
4041 (define_insn "*cmpsi_adjusted"
4042 [(set (match_operand:BI 0 "register_operand" "=c")
4043 (match_operator:BI 1 "adjusted_comparison_operator"
4044 [(match_operand:SI 2 "gr_register_operand" "r")
4045 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4047 "cmp4.%C1 %0, %I0 = %r3, %2"
4048 [(set_attr "itanium_class" "icmp")])
4050 (define_insn "*cmpdi_normal"
4051 [(set (match_operand:BI 0 "register_operand" "=c")
4052 (match_operator:BI 1 "normal_comparison_operator"
4053 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
4054 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
4056 "cmp.%C1 %0, %I0 = %3, %r2"
4057 [(set_attr "itanium_class" "icmp")])
4059 ;; We use %r3 because it is possible for us to match a 0, and two of the
4060 ;; unsigned comparisons don't accept immediate operands of zero.
4062 (define_insn "*cmpdi_adjusted"
4063 [(set (match_operand:BI 0 "register_operand" "=c")
4064 (match_operator:BI 1 "adjusted_comparison_operator"
4065 [(match_operand:DI 2 "gr_register_operand" "r")
4066 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4068 "cmp.%C1 %0, %I0 = %r3, %2"
4069 [(set_attr "itanium_class" "icmp")])
4071 (define_insn "*cmpsf_internal"
4072 [(set (match_operand:BI 0 "register_operand" "=c")
4073 (match_operator:BI 1 "comparison_operator"
4074 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4075 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
4077 "fcmp.%D1 %0, %I0 = %F2, %F3"
4078 [(set_attr "itanium_class" "fcmp")])
4080 (define_insn "*cmpdf_internal"
4081 [(set (match_operand:BI 0 "register_operand" "=c")
4082 (match_operator:BI 1 "comparison_operator"
4083 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4084 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
4086 "fcmp.%D1 %0, %I0 = %F2, %F3"
4087 [(set_attr "itanium_class" "fcmp")])
4089 (define_insn "*cmptf_internal"
4090 [(set (match_operand:BI 0 "register_operand" "=c")
4091 (match_operator:BI 1 "comparison_operator"
4092 [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
4093 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
4094 "INTEL_EXTENDED_IEEE_FORMAT"
4095 "fcmp.%D1 %0, %I0 = %F2, %F3"
4096 [(set_attr "itanium_class" "fcmp")])
4098 ;; ??? Can this pattern be generated?
4100 (define_insn "*bit_zero"
4101 [(set (match_operand:BI 0 "register_operand" "=c")
4102 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4104 (match_operand:DI 2 "immediate_operand" "n"))
4107 "tbit.z %0, %I0 = %1, %2"
4108 [(set_attr "itanium_class" "tbit")])
4110 (define_insn "*bit_one"
4111 [(set (match_operand:BI 0 "register_operand" "=c")
4112 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4114 (match_operand:DI 2 "immediate_operand" "n"))
4117 "tbit.nz %0, %I0 = %1, %2"
4118 [(set_attr "itanium_class" "tbit")])
4120 ;; ::::::::::::::::::::
4124 ;; ::::::::::::::::::::
4126 (define_expand "beq"
4128 (if_then_else (match_dup 1)
4129 (label_ref (match_operand 0 "" ""))
4132 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
4134 (define_expand "bne"
4136 (if_then_else (match_dup 1)
4137 (label_ref (match_operand 0 "" ""))
4140 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
4142 (define_expand "blt"
4144 (if_then_else (match_dup 1)
4145 (label_ref (match_operand 0 "" ""))
4148 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
4150 (define_expand "ble"
4152 (if_then_else (match_dup 1)
4153 (label_ref (match_operand 0 "" ""))
4156 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
4158 (define_expand "bgt"
4160 (if_then_else (match_dup 1)
4161 (label_ref (match_operand 0 "" ""))
4164 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
4166 (define_expand "bge"
4168 (if_then_else (match_dup 1)
4169 (label_ref (match_operand 0 "" ""))
4172 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
4174 (define_expand "bltu"
4176 (if_then_else (match_dup 1)
4177 (label_ref (match_operand 0 "" ""))
4180 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
4182 (define_expand "bleu"
4184 (if_then_else (match_dup 1)
4185 (label_ref (match_operand 0 "" ""))
4188 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
4190 (define_expand "bgtu"
4192 (if_then_else (match_dup 1)
4193 (label_ref (match_operand 0 "" ""))
4196 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
4198 (define_expand "bgeu"
4200 (if_then_else (match_dup 1)
4201 (label_ref (match_operand 0 "" ""))
4204 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
4206 (define_expand "bunordered"
4208 (if_then_else (match_dup 1)
4209 (label_ref (match_operand 0 "" ""))
4212 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
4214 (define_expand "bordered"
4216 (if_then_else (match_dup 1)
4217 (label_ref (match_operand 0 "" ""))
4220 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
4222 (define_insn "*br_true"
4224 (if_then_else (match_operator 0 "predicate_operator"
4225 [(match_operand:BI 1 "register_operand" "c")
4227 (label_ref (match_operand 2 "" ""))
4230 "(%J0) br.cond%+ %l2"
4231 [(set_attr "itanium_class" "br")
4232 (set_attr "predicable" "no")])
4234 (define_insn "*br_false"
4236 (if_then_else (match_operator 0 "predicate_operator"
4237 [(match_operand:BI 1 "register_operand" "c")
4240 (label_ref (match_operand 2 "" ""))))]
4242 "(%j0) br.cond%+ %l2"
4243 [(set_attr "itanium_class" "br")
4244 (set_attr "predicable" "no")])
4246 ;; ::::::::::::::::::::
4248 ;; :: Counted loop operations
4250 ;; ::::::::::::::::::::
4252 (define_expand "doloop_end"
4253 [(use (match_operand 0 "" "")) ; loop pseudo
4254 (use (match_operand 1 "" "")) ; iterations; zero if unknown
4255 (use (match_operand 2 "" "")) ; max iterations
4256 (use (match_operand 3 "" "")) ; loop level
4257 (use (match_operand 4 "" ""))] ; label
4260 /* Only use cloop on innermost loops. */
4261 if (INTVAL (operands[3]) > 1)
4263 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
4268 (define_insn "doloop_end_internal"
4269 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
4271 (label_ref (match_operand 1 "" ""))
4273 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
4274 (plus:DI (match_dup 0) (const_int -1))
4277 "br.cloop.sptk.few %l1"
4278 [(set_attr "itanium_class" "br")
4279 (set_attr "predicable" "no")])
4281 ;; ::::::::::::::::::::
4283 ;; :: Set flag operations
4285 ;; ::::::::::::::::::::
4287 (define_expand "seq"
4288 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4290 "operands[1] = ia64_expand_compare (EQ, DImode);")
4292 (define_expand "sne"
4293 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4295 "operands[1] = ia64_expand_compare (NE, DImode);")
4297 (define_expand "slt"
4298 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4300 "operands[1] = ia64_expand_compare (LT, DImode);")
4302 (define_expand "sle"
4303 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4305 "operands[1] = ia64_expand_compare (LE, DImode);")
4307 (define_expand "sgt"
4308 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4310 "operands[1] = ia64_expand_compare (GT, DImode);")
4312 (define_expand "sge"
4313 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4315 "operands[1] = ia64_expand_compare (GE, DImode);")
4317 (define_expand "sltu"
4318 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4320 "operands[1] = ia64_expand_compare (LTU, DImode);")
4322 (define_expand "sleu"
4323 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4325 "operands[1] = ia64_expand_compare (LEU, DImode);")
4327 (define_expand "sgtu"
4328 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4330 "operands[1] = ia64_expand_compare (GTU, DImode);")
4332 (define_expand "sgeu"
4333 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4335 "operands[1] = ia64_expand_compare (GEU, DImode);")
4337 (define_expand "sunordered"
4338 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4340 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
4342 (define_expand "sordered"
4343 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4345 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
4347 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4348 ;; efficient than mov/mov/cst/cst.
4350 (define_insn_and_split "*sne_internal"
4351 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4352 (ne:DI (match_operand:BI 1 "register_operand" "c")
4357 [(cond_exec (ne (match_dup 1) (const_int 0))
4358 (set (match_dup 0) (const_int 1)))
4359 (cond_exec (eq (match_dup 1) (const_int 0))
4360 (set (match_dup 0) (const_int 0)))]
4362 [(set_attr "itanium_class" "unknown")])
4364 (define_insn_and_split "*seq_internal"
4365 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4366 (eq:DI (match_operand:BI 1 "register_operand" "c")
4371 [(cond_exec (ne (match_dup 1) (const_int 0))
4372 (set (match_dup 0) (const_int 0)))
4373 (cond_exec (eq (match_dup 1) (const_int 0))
4374 (set (match_dup 0) (const_int 1)))]
4376 [(set_attr "itanium_class" "unknown")])
4378 ;; ::::::::::::::::::::
4380 ;; :: Conditional move instructions.
4382 ;; ::::::::::::::::::::
4384 ;; ??? Add movXXcc patterns?
4387 ;; DImode if_then_else patterns.
4390 (define_insn "*cmovdi_internal"
4391 [(set (match_operand:DI 0 "destination_operand"
4392 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
4394 (match_operator 4 "predicate_operator"
4395 [(match_operand:BI 1 "register_operand"
4396 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4398 (match_operand:DI 2 "move_operand"
4399 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
4400 (match_operand:DI 3 "move_operand"
4401 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
4402 "ia64_move_ok (operands[0], operands[2])
4403 && ia64_move_ok (operands[0], operands[3])"
4405 [(set_attr "predicable" "no")])
4408 [(set (match_operand 0 "destination_operand" "")
4410 (match_operator 4 "predicate_operator"
4411 [(match_operand:BI 1 "register_operand" "")
4413 (match_operand 2 "move_operand" "")
4414 (match_operand 3 "move_operand" "")))]
4418 bool emitted_something = false;
4419 rtx dest = operands[0];
4420 rtx srct = operands[2];
4421 rtx srcf = operands[3];
4422 rtx cond = operands[4];
4424 if (! rtx_equal_p (dest, srct))
4426 ia64_emit_cond_move (dest, srct, cond);
4427 emitted_something = true;
4429 if (! rtx_equal_p (dest, srcf))
4431 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
4432 VOIDmode, operands[1], const0_rtx);
4433 ia64_emit_cond_move (dest, srcf, cond);
4434 emitted_something = true;
4436 if (! emitted_something)
4437 emit_note (NOTE_INSN_DELETED);
4441 ;; Absolute value pattern.
4443 (define_insn "*absdi2_internal"
4444 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4446 (match_operator 4 "predicate_operator"
4447 [(match_operand:BI 1 "register_operand" "c,c")
4449 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4450 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
4453 [(set_attr "itanium_class" "ialu,unknown")
4454 (set_attr "predicable" "no")])
4457 [(set (match_operand:DI 0 "register_operand" "")
4459 (match_operator 4 "predicate_operator"
4460 [(match_operand:BI 1 "register_operand" "c,c")
4462 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4463 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4464 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4468 (neg:DI (match_dup 2))))]
4472 [(set (match_operand:DI 0 "register_operand" "")
4474 (match_operator 4 "predicate_operator"
4475 [(match_operand:BI 1 "register_operand" "c,c")
4477 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4478 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4482 (set (match_dup 0) (neg:DI (match_dup 2))))
4485 (set (match_dup 0) (match_dup 3)))]
4487 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4488 VOIDmode, operands[1], const0_rtx);
4492 ;; SImode if_then_else patterns.
4495 (define_insn "*cmovsi_internal"
4496 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
4498 (match_operator 4 "predicate_operator"
4499 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
4501 (match_operand:SI 2 "move_operand"
4502 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
4503 (match_operand:SI 3 "move_operand"
4504 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
4505 "ia64_move_ok (operands[0], operands[2])
4506 && ia64_move_ok (operands[0], operands[3])"
4508 [(set_attr "predicable" "no")])
4510 (define_insn "*abssi2_internal"
4511 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
4513 (match_operator 4 "predicate_operator"
4514 [(match_operand:BI 1 "register_operand" "c,c")
4516 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4517 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
4520 [(set_attr "itanium_class" "ialu,unknown")
4521 (set_attr "predicable" "no")])
4524 [(set (match_operand:SI 0 "register_operand" "")
4526 (match_operator 4 "predicate_operator"
4527 [(match_operand:BI 1 "register_operand" "c,c")
4529 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4530 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4531 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4535 (neg:SI (match_dup 2))))]
4539 [(set (match_operand:SI 0 "register_operand" "")
4541 (match_operator 4 "predicate_operator"
4542 [(match_operand:BI 1 "register_operand" "c,c")
4544 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4545 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4549 (set (match_dup 0) (neg:SI (match_dup 2))))
4552 (set (match_dup 0) (match_dup 3)))]
4554 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4555 VOIDmode, operands[1], const0_rtx);
4558 (define_insn_and_split "*cond_opsi2_internal"
4559 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4560 (match_operator:SI 5 "condop_operator"
4562 (match_operator 6 "predicate_operator"
4563 [(match_operand:BI 1 "register_operand" "c")
4565 (match_operand:SI 2 "gr_register_operand" "r")
4566 (match_operand:SI 3 "gr_register_operand" "r"))
4567 (match_operand:SI 4 "gr_register_operand" "r")]))]
4573 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
4576 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
4578 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4579 VOIDmode, operands[1], const0_rtx);
4581 [(set_attr "itanium_class" "ialu")
4582 (set_attr "predicable" "no")])
4585 (define_insn_and_split "*cond_opsi2_internal_b"
4586 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4587 (match_operator:SI 5 "condop_operator"
4588 [(match_operand:SI 4 "gr_register_operand" "r")
4590 (match_operator 6 "predicate_operator"
4591 [(match_operand:BI 1 "register_operand" "c")
4593 (match_operand:SI 2 "gr_register_operand" "r")
4594 (match_operand:SI 3 "gr_register_operand" "r"))]))]
4600 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
4603 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
4605 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4606 VOIDmode, operands[1], const0_rtx);
4608 [(set_attr "itanium_class" "ialu")
4609 (set_attr "predicable" "no")])
4612 ;; ::::::::::::::::::::
4614 ;; :: Call and branch instructions
4616 ;; ::::::::::::::::::::
4618 ;; Subroutine call instruction returning no value. Operand 0 is the function
4619 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4620 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4621 ;; registers used as operands.
4623 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4624 ;; is supplied for the sake of some RISC machines which need to put this
4625 ;; information into the assembler code; they can put it in the RTL instead of
4628 (define_expand "call"
4629 [(use (match_operand:DI 0 "" ""))
4630 (use (match_operand 1 "" ""))
4631 (use (match_operand 2 "" ""))
4632 (use (match_operand 3 "" ""))]
4635 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
4639 (define_expand "sibcall"
4640 [(use (match_operand:DI 0 "" ""))
4641 (use (match_operand 1 "" ""))
4642 (use (match_operand 2 "" ""))
4643 (use (match_operand 3 "" ""))]
4646 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
4650 ;; Subroutine call instruction returning a value. Operand 0 is the hard
4651 ;; register in which the value is returned. There are three more operands,
4652 ;; the same as the three operands of the `call' instruction (but with numbers
4653 ;; increased by one).
4655 ;; Subroutines that return `BLKmode' objects use the `call' insn.
4657 (define_expand "call_value"
4658 [(use (match_operand 0 "" ""))
4659 (use (match_operand:DI 1 "" ""))
4660 (use (match_operand 2 "" ""))
4661 (use (match_operand 3 "" ""))
4662 (use (match_operand 4 "" ""))]
4665 ia64_expand_call (operands[0], operands[1], operands[3], false);
4669 (define_expand "sibcall_value"
4670 [(use (match_operand 0 "" ""))
4671 (use (match_operand:DI 1 "" ""))
4672 (use (match_operand 2 "" ""))
4673 (use (match_operand 3 "" ""))
4674 (use (match_operand 4 "" ""))]
4677 ia64_expand_call (operands[0], operands[1], operands[3], true);
4681 ;; Call subroutine returning any type.
4683 (define_expand "untyped_call"
4684 [(parallel [(call (match_operand 0 "" "")
4686 (match_operand 1 "" "")
4687 (match_operand 2 "" "")])]
4692 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4694 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4696 rtx set = XVECEXP (operands[2], 0, i);
4697 emit_move_insn (SET_DEST (set), SET_SRC (set));
4700 /* The optimizer does not know that the call sets the function value
4701 registers we stored in the result block. We avoid problems by
4702 claiming that all hard registers are used and clobbered at this
4704 emit_insn (gen_blockage ());
4709 (define_insn "call_nogp"
4710 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
4712 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
4714 "br.call%+.many %1 = %0"
4715 [(set_attr "itanium_class" "br,scall")])
4717 (define_insn "call_value_nogp"
4718 [(set (match_operand 0 "" "")
4719 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
4721 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4723 "br.call%+.many %2 = %1"
4724 [(set_attr "itanium_class" "br,scall")])
4726 (define_insn "sibcall_nogp"
4727 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
4731 [(set_attr "itanium_class" "br,scall")])
4733 (define_insn "call_gp"
4734 [(call (mem:DI (match_operand 0 "call_operand" "?r,i"))
4736 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
4737 (clobber (match_scratch:DI 2 "=&r,X"))
4738 (clobber (match_scratch:DI 3 "=b,X"))]
4741 [(set_attr "itanium_class" "br,scall")])
4743 ;; Irritatingly, we don't have access to INSN within the split body.
4744 ;; See commentary in ia64_split_call as to why these aren't peep2.
4746 [(call (mem (match_operand 0 "call_operand" ""))
4748 (clobber (match_operand:DI 1 "register_operand" ""))
4749 (clobber (match_scratch:DI 2 ""))
4750 (clobber (match_scratch:DI 3 ""))]
4751 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4754 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4755 operands[3], true, false);
4760 [(call (mem (match_operand 0 "call_operand" ""))
4762 (clobber (match_operand:DI 1 "register_operand" ""))
4763 (clobber (match_scratch:DI 2 ""))
4764 (clobber (match_scratch:DI 3 ""))]
4768 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4769 operands[3], false, false);
4773 (define_insn "call_value_gp"
4774 [(set (match_operand 0 "" "")
4775 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
4777 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
4778 (clobber (match_scratch:DI 3 "=&r,X"))
4779 (clobber (match_scratch:DI 4 "=b,X"))]
4782 [(set_attr "itanium_class" "br,scall")])
4785 [(set (match_operand 0 "" "")
4786 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4788 (clobber (match_operand:DI 2 "register_operand" ""))
4789 (clobber (match_scratch:DI 3 ""))
4790 (clobber (match_scratch:DI 4 ""))]
4791 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4794 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4795 operands[4], true, false);
4800 [(set (match_operand 0 "" "")
4801 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4803 (clobber (match_operand:DI 2 "register_operand" ""))
4804 (clobber (match_scratch:DI 3 ""))
4805 (clobber (match_scratch:DI 4 ""))]
4809 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4810 operands[4], false, false);
4814 (define_insn_and_split "sibcall_gp"
4815 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
4817 (clobber (match_scratch:DI 1 "=&r,X"))
4818 (clobber (match_scratch:DI 2 "=b,X"))]
4824 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
4825 operands[2], true, true);
4828 [(set_attr "itanium_class" "br")])
4830 (define_insn "return_internal"
4832 (use (match_operand:DI 0 "register_operand" "b"))]
4834 "br.ret.sptk.many %0"
4835 [(set_attr "itanium_class" "br")])
4837 (define_insn "return"
4839 "ia64_direct_return ()"
4840 "br.ret.sptk.many rp"
4841 [(set_attr "itanium_class" "br")])
4843 (define_insn "*return_true"
4845 (if_then_else (match_operator 0 "predicate_operator"
4846 [(match_operand:BI 1 "register_operand" "c")
4850 "ia64_direct_return ()"
4851 "(%J0) br.ret%+.many rp"
4852 [(set_attr "itanium_class" "br")
4853 (set_attr "predicable" "no")])
4855 (define_insn "*return_false"
4857 (if_then_else (match_operator 0 "predicate_operator"
4858 [(match_operand:BI 1 "register_operand" "c")
4862 "ia64_direct_return ()"
4863 "(%j0) br.ret%+.many rp"
4864 [(set_attr "itanium_class" "br")
4865 (set_attr "predicable" "no")])
4868 [(set (pc) (label_ref (match_operand 0 "" "")))]
4871 [(set_attr "itanium_class" "br")])
4873 (define_insn "indirect_jump"
4874 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
4877 [(set_attr "itanium_class" "br")])
4879 (define_expand "tablejump"
4880 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
4881 (use (label_ref (match_operand 1 "" "")))])]
4884 rtx op0 = operands[0];
4887 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
4888 element into a register without bothering to see whether that
4889 is necessary given the operand predicate. Check for MEM just
4890 in case someone fixes this. */
4891 if (GET_CODE (op0) == MEM)
4892 addr = XEXP (op0, 0);
4895 /* Otherwise, cheat and guess that the previous insn in the
4896 stream was the memory load. Grab the address from that.
4897 Note we have to momentarily pop out of the sequence started
4898 by the insn-emit wrapper in order to grab the last insn. */
4902 last = get_last_insn ();
4904 set = single_set (last);
4906 if (! rtx_equal_p (SET_DEST (set), op0)
4907 || GET_CODE (SET_SRC (set)) != MEM)
4909 addr = XEXP (SET_SRC (set), 0);
4910 if (rtx_equal_p (addr, op0))
4914 /* Jump table elements are stored pc-relative. That is, a displacement
4915 from the entry to the label. Thus to convert to an absolute address
4916 we add the address of the memory from which the value is loaded. */
4917 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
4918 NULL_RTX, 1, OPTAB_DIRECT);
4921 (define_insn "*tablejump_internal"
4922 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
4923 (use (label_ref (match_operand 1 "" "")))]
4926 [(set_attr "itanium_class" "br")])
4929 ;; ::::::::::::::::::::
4931 ;; :: Prologue and Epilogue instructions
4933 ;; ::::::::::::::::::::
4935 (define_expand "prologue"
4939 ia64_expand_prologue ();
4943 (define_expand "epilogue"
4947 ia64_expand_epilogue (0);
4951 (define_expand "sibcall_epilogue"
4955 ia64_expand_epilogue (1);
4959 ;; This prevents the scheduler from moving the SP decrement past FP-relative
4960 ;; stack accesses. This is the same as adddi3 plus the extra set.
4962 (define_insn "prologue_allocate_stack"
4963 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4964 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
4965 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
4966 (set (match_operand:DI 3 "register_operand" "+r,r,r")
4973 [(set_attr "itanium_class" "ialu")])
4975 ;; This prevents the scheduler from moving the SP restore past FP-relative
4976 ;; stack accesses. This is similar to movdi plus the extra set.
4978 (define_insn "epilogue_deallocate_stack"
4979 [(set (match_operand:DI 0 "register_operand" "=r")
4980 (match_operand:DI 1 "register_operand" "+r"))
4981 (set (match_dup 1) (match_dup 1))]
4984 [(set_attr "itanium_class" "ialu")])
4986 ;; As USE insns aren't meaningful after reload, this is used instead
4987 ;; to prevent deleting instructions setting registers for EH handling
4988 (define_insn "prologue_use"
4989 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
4990 UNSPEC_PROLOGUE_USE)]
4993 [(set_attr "itanium_class" "ignore")
4994 (set_attr "predicable" "no")])
4996 ;; Allocate a new register frame.
4998 (define_insn "alloc"
4999 [(set (match_operand:DI 0 "register_operand" "=r")
5000 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
5001 (use (match_operand:DI 1 "const_int_operand" "i"))
5002 (use (match_operand:DI 2 "const_int_operand" "i"))
5003 (use (match_operand:DI 3 "const_int_operand" "i"))
5004 (use (match_operand:DI 4 "const_int_operand" "i"))]
5006 "alloc %0 = ar.pfs, %1, %2, %3, %4"
5007 [(set_attr "itanium_class" "syst_m0")
5008 (set_attr "predicable" "no")])
5011 (define_expand "gr_spill"
5012 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
5013 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5014 (match_operand:DI 2 "const_int_operand" "")]
5016 (clobber (match_dup 3))])]
5018 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5020 (define_insn "gr_spill_internal"
5021 [(set (match_operand:DI 0 "memory_operand" "=m")
5022 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5023 (match_operand:DI 2 "const_int_operand" "")]
5025 (clobber (match_operand:DI 3 "register_operand" ""))]
5028 /* Note that we use a C output pattern here to avoid the predicate
5029 being automatically added before the .mem.offset directive. */
5030 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
5032 [(set_attr "itanium_class" "st")])
5035 (define_expand "gr_restore"
5036 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
5037 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5038 (match_operand:DI 2 "const_int_operand" "")]
5040 (use (match_dup 3))])]
5042 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5044 (define_insn "gr_restore_internal"
5045 [(set (match_operand:DI 0 "register_operand" "=r")
5046 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5047 (match_operand:DI 2 "const_int_operand" "")]
5049 (use (match_operand:DI 3 "register_operand" ""))]
5051 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
5052 [(set_attr "itanium_class" "ld")])
5054 (define_insn "fr_spill"
5055 [(set (match_operand:TF 0 "memory_operand" "=m")
5056 (unspec:TF [(match_operand:TF 1 "register_operand" "f")]
5059 "stf.spill %0 = %1%P0"
5060 [(set_attr "itanium_class" "stf")])
5062 (define_insn "fr_restore"
5063 [(set (match_operand:TF 0 "register_operand" "=f")
5064 (unspec:TF [(match_operand:TF 1 "memory_operand" "m")]
5065 UNSPEC_FR_RESTORE))]
5067 "ldf.fill %0 = %1%P1"
5068 [(set_attr "itanium_class" "fld")])
5070 ;; ??? The explicit stop is not ideal. It would be better if
5071 ;; rtx_needs_barrier took care of this, but this is something that can be
5072 ;; fixed later. This avoids an RSE DV.
5074 (define_insn "bsp_value"
5075 [(set (match_operand:DI 0 "register_operand" "=r")
5076 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
5080 return \";;\;%,mov %0 = ar.bsp\";
5082 [(set_attr "itanium_class" "frar_i")])
5084 (define_insn "set_bsp"
5085 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
5103 [(set_attr "itanium_class" "unknown")
5104 (set_attr "predicable" "no")])
5106 ;; ??? The explicit stops are not ideal. It would be better if
5107 ;; rtx_needs_barrier took care of this, but this is something that can be
5108 ;; fixed later. This avoids an RSE DV.
5110 (define_insn "flushrs"
5111 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
5114 [(set_attr "itanium_class" "rse_m")
5115 (set_attr "predicable" "no")])
5117 ;; ::::::::::::::::::::
5119 ;; :: Miscellaneous instructions
5121 ;; ::::::::::::::::::::
5123 ;; ??? Emiting a NOP instruction isn't very useful. This should probably
5124 ;; be emitting ";;" to force a break in the instruction packing.
5126 ;; No operation, needed in case the user uses -g but not -O.
5131 [(set_attr "itanium_class" "nop")])
5133 (define_insn "nop_m"
5137 [(set_attr "itanium_class" "nop_m")])
5139 (define_insn "nop_i"
5143 [(set_attr "itanium_class" "nop_i")])
5145 (define_insn "nop_f"
5149 [(set_attr "itanium_class" "nop_f")])
5151 (define_insn "nop_b"
5155 [(set_attr "itanium_class" "nop_b")])
5157 (define_insn "nop_x"
5161 [(set_attr "itanium_class" "nop_x")])
5163 ;; The following insn will be never generated. It is used only by
5164 ;; insn scheduler to change state before advancing cycle.
5165 (define_insn "pre_cycle"
5169 [(set_attr "itanium_class" "pre_cycle")])
5171 (define_insn "bundle_selector"
5172 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
5174 { return get_bundle_name (INTVAL (operands[0])); }
5175 [(set_attr "itanium_class" "ignore")
5176 (set_attr "predicable" "no")])
5178 ;; Pseudo instruction that prevents the scheduler from moving code above this
5180 (define_insn "blockage"
5181 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5184 [(set_attr "itanium_class" "ignore")
5185 (set_attr "predicable" "no")])
5187 (define_insn "insn_group_barrier"
5188 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
5189 UNSPECV_INSN_GROUP_BARRIER)]
5192 [(set_attr "itanium_class" "stop_bit")
5193 (set_attr "predicable" "no")])
5195 (define_expand "trap"
5196 [(trap_if (const_int 1) (const_int 0))]
5200 ;; ??? We don't have a match-any slot type. Setting the type to unknown
5201 ;; produces worse code that setting the slot type to A.
5203 (define_insn "*trap"
5204 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
5207 [(set_attr "itanium_class" "chk_s")])
5209 (define_expand "conditional_trap"
5210 [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
5213 operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
5216 (define_insn "*conditional_trap"
5217 [(trap_if (match_operator 0 "predicate_operator"
5218 [(match_operand:BI 1 "register_operand" "c")
5220 (match_operand 2 "const_int_operand" ""))]
5223 [(set_attr "itanium_class" "chk_s")
5224 (set_attr "predicable" "no")])
5226 (define_insn "break_f"
5227 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
5230 [(set_attr "itanium_class" "nop_f")])
5232 (define_insn "prefetch"
5233 [(prefetch (match_operand:DI 0 "address_operand" "p")
5234 (match_operand:DI 1 "const_int_operand" "n")
5235 (match_operand:DI 2 "const_int_operand" "n"))]
5238 static const char * const alt[2][4] = {
5240 "%,lfetch.nta [%0]",
5241 "%,lfetch.nt1 [%0]",
5242 "%,lfetch.nt2 [%0]",
5246 "%,lfetch.excl.nta [%0]",
5247 "%,lfetch.excl.nt1 [%0]",
5248 "%,lfetch.excl.nt2 [%0]",
5249 "%,lfetch.excl [%0]"
5252 int i = (INTVAL (operands[1]));
5253 int j = (INTVAL (operands[2]));
5255 if (i != 0 && i != 1)
5261 [(set_attr "itanium_class" "lfetch")])
5263 ;; Non-local goto support.
5265 (define_expand "save_stack_nonlocal"
5266 [(use (match_operand:OI 0 "memory_operand" ""))
5267 (use (match_operand:DI 1 "register_operand" ""))]
5270 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5271 \"__ia64_save_stack_nonlocal\"),
5272 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
5273 operands[1], Pmode);
5277 (define_expand "nonlocal_goto"
5278 [(use (match_operand 0 "general_operand" ""))
5279 (use (match_operand 1 "general_operand" ""))
5280 (use (match_operand 2 "general_operand" ""))
5281 (use (match_operand 3 "general_operand" ""))]
5284 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
5285 LCT_NORETURN, VOIDmode, 3,
5287 copy_to_reg (XEXP (operands[2], 0)), Pmode,
5288 operands[3], Pmode);
5293 (define_insn_and_split "builtin_setjmp_receiver"
5294 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
5304 (define_expand "eh_epilogue"
5305 [(use (match_operand:DI 0 "register_operand" "r"))
5306 (use (match_operand:DI 1 "register_operand" "r"))
5307 (use (match_operand:DI 2 "register_operand" "r"))]
5310 rtx bsp = gen_rtx_REG (Pmode, 10);
5311 rtx sp = gen_rtx_REG (Pmode, 9);
5313 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5315 emit_move_insn (bsp, operands[0]);
5318 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5320 emit_move_insn (sp, operands[2]);
5323 emit_insn (gen_rtx_USE (VOIDmode, sp));
5324 emit_insn (gen_rtx_USE (VOIDmode, bsp));
5326 cfun->machine->ia64_eh_epilogue_sp = sp;
5327 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5330 ;; Builtin apply support.
5332 (define_expand "restore_stack_nonlocal"
5333 [(use (match_operand:DI 0 "register_operand" ""))
5334 (use (match_operand:OI 1 "memory_operand" ""))]
5337 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5338 "__ia64_restore_stack_nonlocal"),
5340 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5345 ;;; Intrinsics support.
5348 [(set (mem:BLK (match_dup 0))
5349 (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
5352 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
5353 MEM_VOLATILE_P (operands[0]) = 1;
5356 (define_insn "*mf_internal"
5357 [(set (match_operand:BLK 0 "" "")
5358 (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
5361 [(set_attr "itanium_class" "syst_m")])
5363 (define_insn "fetchadd_acq_si"
5364 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5366 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5367 (unspec:SI [(match_dup 1)
5368 (match_operand:SI 2 "fetchadd_operand" "n")]
5369 UNSPEC_FETCHADD_ACQ))]
5371 "fetchadd4.acq %0 = %1, %2"
5372 [(set_attr "itanium_class" "sem")])
5374 (define_insn "fetchadd_acq_di"
5375 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5377 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5378 (unspec:DI [(match_dup 1)
5379 (match_operand:DI 2 "fetchadd_operand" "n")]
5380 UNSPEC_FETCHADD_ACQ))]
5382 "fetchadd8.acq %0 = %1, %2"
5383 [(set_attr "itanium_class" "sem")])
5385 (define_insn "cmpxchg_acq_si"
5386 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5388 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5389 (unspec:SI [(match_dup 1)
5390 (match_operand:SI 2 "gr_register_operand" "r")
5391 (match_operand 3 "ar_ccv_reg_operand" "")]
5392 UNSPEC_CMPXCHG_ACQ))]
5394 "cmpxchg4.acq %0 = %1, %2, %3"
5395 [(set_attr "itanium_class" "sem")])
5397 (define_insn "cmpxchg_acq_di"
5398 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5400 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5401 (unspec:DI [(match_dup 1)
5402 (match_operand:DI 2 "gr_register_operand" "r")
5403 (match_operand:DI 3 "ar_ccv_reg_operand" "")]
5404 UNSPEC_CMPXCHG_ACQ))]
5406 "cmpxchg8.acq %0 = %1, %2, %3"
5407 [(set_attr "itanium_class" "sem")])
5409 (define_insn "xchgsi"
5410 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5411 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
5413 (match_operand:SI 2 "gr_register_operand" "r"))]
5416 [(set_attr "itanium_class" "sem")])
5418 (define_insn "xchgdi"
5419 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5420 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
5422 (match_operand:DI 2 "gr_register_operand" "r"))]
5425 [(set_attr "itanium_class" "sem")])
5430 [(match_operator 0 "predicate_operator"
5431 [(match_operand:BI 1 "register_operand" "c")
5436 (define_insn "pred_rel_mutex"
5437 [(set (match_operand:BI 0 "register_operand" "+c")
5438 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
5440 ".pred.rel.mutex %0, %I0"
5441 [(set_attr "itanium_class" "ignore")
5442 (set_attr "predicable" "no")])
5444 (define_insn "safe_across_calls_all"
5445 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
5447 ".pred.safe_across_calls p1-p63"
5448 [(set_attr "itanium_class" "ignore")
5449 (set_attr "predicable" "no")])
5451 (define_insn "safe_across_calls_normal"
5452 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
5455 emit_safe_across_calls ();
5458 [(set_attr "itanium_class" "ignore")
5459 (set_attr "predicable" "no")])
5461 ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
5462 ;; pointer. This is used by the HP-UX 32 bit mode.
5464 (define_insn "ptr_extend"
5465 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5466 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
5470 [(set_attr "itanium_class" "ialu")])
5473 ;; Optimizations for ptr_extend
5475 (define_insn "*ptr_extend_plus_1"
5476 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5478 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
5479 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
5481 "addp4_optimize_ok (operands[1], operands[2])"
5483 [(set_attr "itanium_class" "ialu")])
5485 (define_insn "*ptr_extend_plus_2"
5486 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5488 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
5489 (match_operand:SI 2 "basereg_operand" "r"))]
5491 "addp4_optimize_ok (operands[1], operands[2])"
5493 [(set_attr "itanium_class" "ialu")])