gcc/config/m32c/bitops.md

   1 ;; Machine Descriptions for R8C/M16C/M32C
   2 ;; Copyright (C) 2005
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Red Hat.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published
  10 ;; by the Free Software Foundation; either version 2, or (at your
  11 ;; option) any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21 ;; 02110-1301, USA.
  22
  23 ;; Bit-wise operations (and, ior, xor, shift)
  24
  25 ; On the R8C and M16C, "address" for bit instructions is usually (but
  26 ; not always!) the *bit* address, not the *byte* address.  This
  27 ; confuses gcc, so we avoid cases where gcc would produce the wrong
  28 ; code.  We're left with absolute addresses and registers, and the odd
  29 ; case of shifting a bit by a variable.
  30
  31 ; On the M32C, "address" for bit instructions is a regular address,
  32 ; and the bit number is stored in a separate field.  Thus, we can let
  33 ; gcc do more interesting things.  However, the M32C cannot set all
  34 ; the bits in a 16 bit register, which the R8C/M16C can do.
  35
  36 ; However, it all means that we end up with two sets of patterns, one
  37 ; for each chip.
  38
  39 ;;----------------------------------------------------------------------
  40
  41 ;; First off, all the ways we can set one bit, other than plain IOR.
  42
  43 (define_insn "bset_qi"
  44   [(set (match_operand:QI 0 "memsym_operand" "+Si")
  45         (ior:QI (subreg:QI (ashift:HI (const_int 1)
  46                                       (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
  47                 (match_operand:QI 2 "" "0")))]
  48   "TARGET_A16"
  49   "bset\t%0[%1]"
  50   [(set_attr "flags" "sz")]
  51   )
  52
  53 (define_insn "bset_hi"
  54   [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
  55                          (const_int 1)
  56                          (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
  57         (const_int 1))]
  58   "TARGET_A16"
  59   "bset\t%0[%1]"
  60   [(set_attr "flags" "sz")]
  61   )
  62
  63 ;;----------------------------------------------------------------------
  64
  65 ;; Now all the ways we can clear one bit, other than plain AND.
  66
  67 ; This is odd because the shift patterns use QI counts, but we can't
  68 ; easily put QI in $aN without causing problems elsewhere.
  69 (define_insn "bclr_qi"
  70   [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
  71                          (const_int 1)
  72                          (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
  73         (const_int 0))]
  74   "TARGET_A16"
  75   "bclr\t%0[%1]"
  76   [(set_attr "flags" "sz")]
  77   )
  78
  79
  80 ;;----------------------------------------------------------------------
  81
  82 ;; Now the generic patterns.
  83
  84 (define_insn "andqi3_16"
  85   [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
  86         (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
  87                 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
  88   "TARGET_A16"
  89   "@
  90    bclr\t%B2,%0
  91    bclr\t%B2,%h0
  92    and.b\t%x2,%0
  93    and.b\t%x2,%0
  94    and.b\t%x2,%0
  95    and.b\t%x2,%0"
  96   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
  97   )
  98
  99 (define_insn "andhi3_16"
 100   [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
 101         (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
 102                 (match_operand:HI 2 "mrai_operand" "Imb,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
 103   "TARGET_A16"
 104   "@
 105
 106    bclr\t%B2,%0
 107    bclr\t%B2-8,1+%0
 108    bclr\t%B2,%0
 109    and.w\t%X2,%0
 110    and.w\t%X2,%0
 111    and.w\t%X2,%0
 112    and.w\t%X2,%0"
 113   [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
 114   )
 115
 116
 117
 118 (define_insn "iorqi3_16"
 119   [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
 120         (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
 121                 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
 122   "TARGET_A16"
 123   "@
 124    bset\t%B2,%0
 125    bset\t%B2,%h0
 126    or.b\t%x2,%0
 127    or.b\t%x2,%0
 128    or.b\t%x2,%0
 129    or.b\t%x2,%0"
 130   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
 131   )
 132
 133 (define_insn "iorhi3_16"
 134   [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
 135         (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
 136                 (match_operand:HI 2 "mrai_operand" "Imb,Imw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
 137   "TARGET_A16"
 138   "@
 139    bset %B2,%0
 140    bset\t%B2-8,1+%0
 141    bset\t%B2,%0
 142    or.w\t%X2,%0
 143    or.w\t%X2,%0
 144    or.w\t%X2,%0
 145    or.w\t%X2,%0"
 146   [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
 147   )
 148
 149 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 150
 151 (define_insn "andqi3_24"
 152   [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
 153         (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
 154                 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
 155   "TARGET_A24"
 156   "@
 157    bclr\t%B2,%0
 158    bclr\t%B2,%0
 159    and.b\t%x2,%0
 160    and.b\t%x2,%0
 161    and.b\t%x2,%0
 162    and.b\t%x2,%0"
 163   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
 164   )
 165
 166 (define_insn "andhi3_24"
 167   [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,??Rmm,RhiSd,??Rmm")
 168         (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
 169                 (match_operand:HI 2 "mrai_operand" "Imb,Imw,Imb,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
 170   "TARGET_A24"
 171   "@
 172    bclr\t%B2,%0
 173    bclr\t%B2-8,1+%0
 174    bclr\t%B2,%h0
 175    bclr\t%B2-8,%H0
 176    and.w\t%X2,%0
 177    and.w\t%X2,%0
 178    and.w\t%X2,%0
 179    and.w\t%X2,%0"
 180   [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
 181   )
 182
 183
 184
 185 (define_insn "iorqi3_24"
 186   [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
 187         (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
 188                 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
 189   "TARGET_A24"
 190   "@
 191    bset\t%B2,%0
 192    bset\t%B2,%0
 193    or.b\t%x2,%0
 194    or.b\t%x2,%0
 195    or.b\t%x2,%0
 196    or.b\t%x2,%0"
 197   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
 198   )
 199
 200 (define_insn "iorhi3_24"
 201   [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,RhiSd,??Rmm,??Rmm")
 202         (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
 203                 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
 204   "TARGET_A24"
 205   "@
 206    bset\t%B2,%0
 207    bset\t%B2-8,1+%0
 208    bset\t%B2,%h0
 209    bset\t%B2-8,%H0
 210    or.w\t%X2,%0
 211    or.w\t%X2,%0
 212    or.w\t%X2,%0
 213    or.w\t%X2,%0"
 214   [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
 215   )
 216
 217
 218 ; ----------------------------------------------------------------------
 219
 220 (define_expand "andqi3"
 221   [(set (match_operand:QI 0 "mra_operand" "")
 222         (and:QI (match_operand:QI 1 "mra_operand" "")
 223                 (match_operand:QI 2 "mrai_operand" "")))]
 224   ""
 225   "if (TARGET_A16)
 226      emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
 227    else
 228      emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
 229    DONE;"
 230   )
 231
 232 (define_expand "andhi3"
 233   [(set (match_operand:HI 0 "mra_operand" "")
 234         (and:HI (match_operand:HI 1 "mra_operand" "")
 235                 (match_operand:HI 2 "mrai_operand" "")))]
 236   ""
 237   "if (TARGET_A16)
 238      emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
 239    else
 240      emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
 241    DONE;"
 242   )
 243
 244 (define_expand "iorqi3"
 245   [(set (match_operand:QI 0 "mra_operand" "")
 246         (ior:QI (match_operand:QI 1 "mra_operand" "")
 247                 (match_operand:QI 2 "mrai_operand" "")))]
 248   ""
 249   "if (TARGET_A16)
 250      emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
 251    else
 252      emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
 253    DONE;"
 254   )
 255
 256 (define_expand "iorhi3"
 257   [(set (match_operand:HI 0 "mra_operand" "")
 258         (ior:HI (match_operand:HI 1 "mra_operand" "")
 259                 (match_operand:HI 2 "mrai_operand" "")))]
 260   ""
 261   "if (TARGET_A16)
 262      emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
 263    else
 264      emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
 265    DONE;"
 266   )
 267
 268 (define_insn "xorqi3"
 269   [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
 270         (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
 271                 (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
 272   ""
 273   "xor.b\t%x2,%0"
 274   [(set_attr "flags" "sz,sz,sz,sz")]
 275   )
 276
 277 (define_insn "xorhi3"
 278   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
 279         (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
 280                 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
 281   ""
 282   "xor.w\t%X2,%0"
 283   [(set_attr "flags" "sz,sz,sz,sz")]
 284   )
 285
 286 (define_insn "one_cmplqi2"
 287   [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
 288         (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
 289   ""
 290   "not.b\t%0"
 291   [(set_attr "flags" "sz,sz")]
 292   )
 293
 294 (define_insn "one_cmplhi2"
 295   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
 296         (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
 297   ""
 298   "not.w\t%0"
 299   [(set_attr "flags" "sz,sz")]
 300   )
 301
 302 ; Optimizations using bit opcodes
 303
 304 ; We need this because combine only looks at three insns at a time,
 305 ; and the bclr_qi pattern uses four - mov, shift, not, and.  GCC
 306 ; should never expand this pattern, because it only shifts a constant
 307 ; by a constant, so gcc should do that itself.
 308 (define_insn "shift1_qi"
 309   [(set (match_operand:QI 0 "mra_operand" "=Rqi")
 310         (ashift:QI (const_int 1)
 311                    (match_operand 1 "const_int_operand" "In4")))]
 312   ""
 313   "mov.b\t#1,%0\n\tshl.b\t%1,%0"
 314   )
 315 (define_insn "shift1_hi"
 316   [(set (match_operand:HI 0 "mra_operand" "=Rhi")
 317         (ashift:HI (const_int 1)
 318                    (match_operand 1 "const_int_operand" "In4")))]
 319   ""
 320   "mov.w\t#1,%0\n\tshl.w\t%1,%0"
 321   )
 322
 323 ; Generic insert-bit expander, needed so that we can use the bit
 324 ; opcodes for volatile bitfields.
 325
 326 (define_expand "insv"
 327   [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
 328                          (match_operand 1 "const_int_operand" "")
 329                          (match_operand 2 "const_int_operand" ""))
 330         (match_operand:HI 3 "const_int_operand" ""))]
 331   ""
 332   "if (m32c_expand_insv (operands))
 333      FAIL;
 334    DONE;"
 335   )