1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Bit-wise operations (and, ior, xor, shift)
24 ; On the R8C and M16C, "address" for bit instructions is usually (but
25 ; not always!) the *bit* address, not the *byte* address. This
26 ; confuses gcc, so we avoid cases where gcc would produce the wrong
27 ; code. We're left with absolute addresses and registers, and the odd
28 ; case of shifting a bit by a variable.
30 ; On the M32C, "address" for bit instructions is a regular address,
31 ; and the bit number is stored in a separate field. Thus, we can let
32 ; gcc do more interesting things. However, the M32C cannot set all
33 ; the bits in a 16-bit register, which the R8C/M16C can do.
35 ; However, it all means that we end up with two sets of patterns, one
38 ;;----------------------------------------------------------------------
40 ;; First off, all the ways we can set one bit, other than plain IOR.
42 (define_insn "bset_qi"
43 [(set (match_operand:QI 0 "memsym_operand" "+Si")
44 (ior:QI (subreg:QI (ashift:HI (const_int 1)
45 (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
46 (match_operand:QI 2 "memsym_operand" "0")))]
49 [(set_attr "flags" "n")]
52 (define_insn "bset_hi"
53 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
55 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
59 [(set_attr "flags" "n")]
62 ;;----------------------------------------------------------------------
64 ;; Now all the ways we can clear one bit, other than plain AND.
66 ; This is odd because the shift patterns use QI counts, but we can't
67 ; easily put QI in $aN without causing problems elsewhere.
68 (define_insn "bclr_qi"
69 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
71 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
75 [(set_attr "flags" "n")]
79 ;;----------------------------------------------------------------------
81 ;; Now the generic patterns.
83 (define_insn "andqi3_16"
84 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
85 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
86 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
95 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
98 (define_insn "andhi3_16"
99 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
100 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
101 (match_operand:HI 2 "mrai_operand" "ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
112 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
115 (define_insn "andsi3"
116 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
117 (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
118 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
121 switch (which_alternative)
124 output_asm_insn (\"and.w %X2,%h0\",operands);
125 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
126 return \"and.w %X2,%H0\";
128 return \"and.w %h2,%h0\;and.w %H2,%H0\";
130 output_asm_insn (\"and.w %X2,%h0\",operands);
131 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
132 return \"and.w %X2,%H0\";
134 return \"and.w %h2,%h0\;and.w %H2,%H0\";
136 return \"and.w %h2,%h0\;and.w %H2,%H0\";
138 return \"and.w %h2,%h0\;and.w %H2,%H0\";
140 [(set_attr "flags" "x,x,x,x,x,x")]
144 (define_insn "iorqi3_16"
145 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
146 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
147 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
156 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
159 (define_insn "iorhi3_16"
160 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
161 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
162 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
172 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
175 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
177 (define_insn "andqi3_24"
178 [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
179 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
180 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
189 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
192 (define_insn "andhi3_24"
193 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
194 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
195 (match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
206 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
211 (define_insn "iorqi3_24"
212 [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
213 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
214 (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
222 [(set_attr "flags" "n,sz,sz,sz,sz")]
225 (define_insn "iorhi3_24"
226 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
227 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
228 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
239 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
243 ; ----------------------------------------------------------------------
245 (define_expand "andqi3"
246 [(set (match_operand:QI 0 "mra_operand" "")
247 (and:QI (match_operand:QI 1 "mra_operand" "")
248 (match_operand:QI 2 "mrai_operand" "")))]
251 emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
253 emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
257 (define_expand "andhi3"
258 [(set (match_operand:HI 0 "mra_operand" "")
259 (and:HI (match_operand:HI 1 "mra_operand" "")
260 (match_operand:HI 2 "mrai_operand" "")))]
263 emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
265 emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
269 (define_expand "iorqi3"
270 [(set (match_operand:QI 0 "mra_operand" "")
271 (ior:QI (match_operand:QI 1 "mra_operand" "")
272 (match_operand:QI 2 "mrai_operand" "")))]
275 emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
277 emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
281 (define_expand "iorhi3"
282 [(set (match_operand:HI 0 "mra_operand" "")
283 (ior:HI (match_operand:HI 1 "mra_operand" "")
284 (match_operand:HI 2 "mrai_operand" "")))]
287 emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
289 emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
293 (define_insn "iorsi3"
294 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
295 (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
296 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
299 switch (which_alternative)
302 output_asm_insn (\"or.w %X2,%h0\",operands);
303 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
304 return \"or.w %X2,%H0\";
306 return \"or.w %h2,%h0\;or.w %H2,%H0\";
308 output_asm_insn (\"or.w %X2,%h0\",operands);
309 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
310 return \"or.w %X2,%H0\";
312 return \"or.w %h2,%h0\;or.w %H2,%H0\";
314 return \"or.w %h2,%h0\;or.w %H2,%H0\";
316 return \"or.w %h2,%h0\;or.w %H2,%H0\";
318 [(set_attr "flags" "x,x,x,x,x,x")]
321 (define_insn "xorqi3"
322 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
323 (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
324 (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
327 [(set_attr "flags" "sz,sz,sz,sz")]
330 (define_insn "xorhi3"
331 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
332 (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
333 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
336 [(set_attr "flags" "sz,sz,sz,sz")]
339 (define_insn "xorsi3"
340 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
341 (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
342 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
345 switch (which_alternative)
348 output_asm_insn (\"xor.w %X2,%h0\",operands);
349 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
350 return \"xor.w %X2,%H0\";
352 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
354 output_asm_insn (\"xor.w %X2,%h0\",operands);
355 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
356 return \"xor.w %X2,%H0\";
358 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
360 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
362 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
364 [(set_attr "flags" "x,x,x,x,x,x")]
367 (define_insn "one_cmplqi2"
368 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
369 (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
372 [(set_attr "flags" "sz,sz")]
375 (define_insn "one_cmplhi2"
376 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
377 (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
380 [(set_attr "flags" "sz,sz")]
383 ; Optimizations using bit opcodes
385 ; We need this because combine only looks at three insns at a time,
386 ; and the bclr_qi pattern uses four - mov, shift, not, and. GCC
387 ; should never expand this pattern, because it only shifts a constant
388 ; by a constant, so gcc should do that itself.
389 (define_insn "shift1_qi"
390 [(set (match_operand:QI 0 "mra_operand" "=Rqi")
391 (ashift:QI (const_int 1)
392 (match_operand 1 "const_int_operand" "In4")))]
394 "mov.b\t#1,%0\n\tshl.b\t%1,%0"
396 (define_insn "shift1_hi"
397 [(set (match_operand:HI 0 "mra_operand" "=Rhi")
398 (ashift:HI (const_int 1)
399 (match_operand 1 "const_int_operand" "In4")))]
401 "mov.w\t#1,%0\n\tshl.w\t%1,%0"
404 ; Generic insert-bit expander, needed so that we can use the bit
405 ; opcodes for volatile bitfields.
407 (define_expand "insv"
408 [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
409 (match_operand 1 "const_int_operand" "")
410 (match_operand 2 "const_int_operand" ""))
411 (match_operand:HI 3 "const_int_operand" ""))]
413 "if (m32c_expand_insv (operands))