gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005, 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_M32C_H
  23 #define GCC_M32C_H
  24
  25 /* Controlling the Compilation Driver, `gcc'.  */
  26
  27 #undef  STARTFILE_SPEC
  28 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  29
  30 /* There are four CPU series we support, but they basically break down
  31    into two families - the R8C/M16C families, with 16-bit address
  32    registers and one set of opcodes, and the M32CM/M32C group, with
  33    24-bit address registers and a different set of opcodes.  The
  34    assembler doesn't care except for which opcode set is needed; the
  35    big difference is in the memory maps, which we cover in
  36    LIB_SPEC.  */
  37
  38 #undef  ASM_SPEC
  39 #define ASM_SPEC "\
  40 %{mcpu=r8c:--m16c} \
  41 %{mcpu=m16c:--m16c} \
  42 %{mcpu=m32cm:--m32c} \
  43 %{mcpu=m32c:--m32c} "
  44
  45 /* The default is R8C hardware.  We support a simulator, which has its
  46    own libgloss and link map, plus one default link map for each chip
  47    family.  Most of the logic here is making sure we do the right
  48    thing when no CPU is specified, which defaults to R8C.  */
  49 #undef  LIB_SPEC
  50 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  51 %{msim*:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
  52         %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
  53 %{!T*:%{!msim*: %{mcpu=m16c:%Tm16c.ld} \
  54                 %{mcpu=m32cm:%Tm32cm.ld} \
  55                 %{mcpu=m32c:%Tm32c.ld} \
  56                 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
  57 "
  58
  59 /* Run-time Target Specification */
  60
  61 /* Nothing unusual here.  */
  62 #define TARGET_CPU_CPP_BUILTINS() \
  63   { \
  64     builtin_assert ("cpu=m32c"); \
  65     builtin_assert ("machine=m32c"); \
  66     builtin_define ("__m32c__=1"); \
  67     if (TARGET_R8C) \
  68       builtin_define ("__r8c_cpu__=1"); \
  69     if (TARGET_M16C) \
  70       builtin_define ("__m16c_cpu__=1"); \
  71     if (TARGET_M32CM) \
  72       builtin_define ("__m32cm_cpu__=1"); \
  73     if (TARGET_M32C) \
  74       builtin_define ("__m32c_cpu__=1"); \
  75   }
  76
  77 /* The pragma handlers need to know if we've started processing
  78    functions yet, as the memregs pragma should only be given at the
  79    beginning of the file.  This variable starts off TRUE and later
  80    becomes FALSE.  */
  81 extern int ok_to_change_target_memregs;
  82 extern int target_memregs;
  83
  84 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  85    use enums or defines for this, this and m32c.opt are the only
  86    places that know (or care) what values are being used.  */
  87 #define TARGET_R8C      (target_cpu == 'r')
  88 #define TARGET_M16C     (target_cpu == '6')
  89 #define TARGET_M32CM    (target_cpu == 'm')
  90 #define TARGET_M32C     (target_cpu == '3')
  91
  92 /* Address register sizes.  Warning: these are used all over the place
  93    to select between the two CPU families in general.  */
  94 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
  95 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
  96
  97 #define TARGET_VERSION fprintf (stderr, " (m32c)");
  98
  99 /* Defining data structures for per-function information */
 100
 101 typedef struct GTY (()) machine_function
 102 {
 103   /* How much we adjust the stack when returning from an exception
 104      handler.  */
 105   rtx eh_stack_adjust;
 106
 107   /* TRUE if the current function is an interrupt handler.  */
 108   int is_interrupt;
 109
 110   /* TRUE if the current function is a leaf function.  Currently, this
 111      only affects saving $a0 in interrupt functions.  */
 112   int is_leaf;
 113
 114   /* Bitmask that keeps track of which registers are used in an
 115      interrupt function, so we know which ones need to be saved and
 116      restored.  */
 117   int intr_pushm;
 118   /* Likewise, one element for each memreg that needs to be saved.  */
 119   char intr_pushmem[16];
 120
 121   /* TRUE if the current function can use a simple RTS to return, instead
 122      of the longer ENTER/EXIT pair.  */
 123   int use_rts;
 124 }
 125 machine_function;
 126
 127 #define INIT_EXPANDERS m32c_init_expanders ()
 128
 129 /* Storage Layout */
 130
 131 #define BITS_BIG_ENDIAN 0
 132 #define BYTES_BIG_ENDIAN 0
 133 #define WORDS_BIG_ENDIAN 0
 134
 135 /* We can do QI, HI, and SI operations pretty much equally well, but
 136    GCC expects us to have a "native" format, so we pick the one that
 137    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 138    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 139    24-bit pointers are stored in 32-bit words.  */
 140 #define BITS_PER_UNIT 8
 141 #define UNITS_PER_WORD 2
 142 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 143 #define POINTERS_EXTEND_UNSIGNED 1
 144 /* We have a problem with libgcc2.  It only defines two versions of
 145    each function, one for "int" and one for "long long".  Ie it assumes
 146    that "sizeof (int) == sizeof (long)".  For the M32C this is not true
 147    and we need a third set of functions.  We explicitly define
 148    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
 149    to get the SI and DI versions from the libgcc2.c sources, and we
 150    provide our own set of HI functions in m32c-lib2.c, which is why this
 151    definition is surrounded by #ifndef..#endif.  */
 152 #ifndef LIBGCC2_UNITS_PER_WORD
 153 #define LIBGCC2_UNITS_PER_WORD 4
 154 #endif
 155
 156 /* These match the alignment enforced by the two types of stack operations.  */
 157 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 158 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 159
 160 /* We do this because we care more about space than about speed.  For
 161    the chips with 16-bit busses, we could set these to 16 if
 162    desired.  */
 163 #define FUNCTION_BOUNDARY 8
 164 #define BIGGEST_ALIGNMENT 8
 165
 166 /* Since we have a maximum structure alignment of 8 there
 167    is no need to enforce any alignment of bitfield types.  */
 168 #undef  PCC_BITFIELD_TYPE_MATTERS
 169 #define PCC_BITFIELD_TYPE_MATTERS 0
 170
 171 #define STRICT_ALIGNMENT 0
 172 #define SLOW_BYTE_ACCESS 1
 173
 174 /* Layout of Source Language Data Types */
 175
 176 #define INT_TYPE_SIZE 16
 177 #define SHORT_TYPE_SIZE 16
 178 #define LONG_TYPE_SIZE 32
 179 #define LONG_LONG_TYPE_SIZE 64
 180
 181 #define FLOAT_TYPE_SIZE 32
 182 #define DOUBLE_TYPE_SIZE 64
 183 #define LONG_DOUBLE_TYPE_SIZE 64
 184
 185 #define DEFAULT_SIGNED_CHAR 1
 186
 187 #undef PTRDIFF_TYPE
 188 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 189
 190 #undef UINTPTR_TYPE
 191 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
 192
 193 /* REGISTER USAGE */
 194
 195 /* Register Basics */
 196
 197 /* Register layout:
 198
 199         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 200         [--------]  $r2  (16 bits)
 201         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 202         [--------]  $r3  (16 bits)
 203    [---][--------]  $a0  (might be 24 bits)
 204    [---][--------]  $a1  (might be 24 bits)
 205    [---][--------]  $sb  (might be 24 bits)
 206    [---][--------]  $fb  (might be 24 bits)
 207    [---][--------]  $sp  (might be 24 bits)
 208    [-------------]  $pc  (20 or 24 bits)
 209              [---]  $flg (CPU flags)
 210    [---][--------]  $argp (virtual)
 211         [--------]  $mem0 (all 16 bits)
 212           . . .
 213         [--------]  $mem14
 214 */
 215
 216 #define FIRST_PSEUDO_REGISTER   20
 217
 218 /* Note that these two tables are modified based on which CPU family
 219    you select; see m32c_conditional_register_usage for details.  */
 220
 221 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 222 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 223                               0, 0, 1, 0, \
 224                               1, 1, 0, 1, \
 225                               0, 0, 0, 0, 0, 0, 0, 0 }
 226 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 227                               1, 1, 1, 0, \
 228                               1, 1, 1, 1, \
 229                               1, 1, 1, 1, 1, 1, 1, 1 }
 230
 231 #define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
 232
 233 /* The *_REGNO theme matches m32c.md and most register number
 234    arguments; the PC_REGNUM is the odd one out.  */
 235 #ifndef PC_REGNO
 236 #define PC_REGNO 9
 237 #endif
 238 #define PC_REGNUM PC_REGNO
 239
 240 /* Order of Allocation of Registers */
 241
 242 #define REG_ALLOC_ORDER { \
 243         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 244         12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
 245         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 246
 247 /* How Values Fit in Registers */
 248
 249 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
 250 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
 251 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
 252 #define AVOID_CCMODE_COPIES
 253
 254 /* Register Classes */
 255
 256 /* Most registers are special purpose in some form or another, so this
 257    table is pretty big.  Class names are used for constraints also;
 258    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 259    See m32c_reg_class_from_constraint for the mapping.  There's some
 260    duplication so that we can better isolate the reason for using
 261    constraints in the md files from the actual registers used; for
 262    example we may want to exclude a1a0 from SI_REGS in the future,
 263    without precluding their use as HImode registers.  */
 264
 265 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 266 /*       mmPAR */
 267 #define REG_CLASS_CONTENTS \
 268 { { 0x00000000 }, /* NO */\
 269   { 0x00000100 }, /* SP  - sp */\
 270   { 0x00000080 }, /* FB  - fb */\
 271   { 0x00000040 }, /* SB  - sb */\
 272   { 0x000001c0 }, /* CR  - sb fb sp */\
 273   { 0x00000001 }, /* R0  - r0 */\
 274   { 0x00000004 }, /* R1  - r1 */\
 275   { 0x00000002 }, /* R2  - r2 */\
 276   { 0x00000008 }, /* R3  - r3 */\
 277   { 0x00000003 }, /* R02 - r0r2 */\
 278   { 0x0000000c }, /* R13 - r1r3 */\
 279   { 0x00000005 }, /* HL  - r0 r1 */\
 280   { 0x00000005 }, /* QI  - r0 r1 */\
 281   { 0x0000000a }, /* R23 - r2 r3 */\
 282   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 283   { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
 284   { 0x00000010 }, /* A0  - a0 */\
 285   { 0x00000020 }, /* A1  - a1 */\
 286   { 0x00000030 }, /* A   - a0 a1 */\
 287   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 288   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 289   { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
 290   { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
 291   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
 292   { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
 293   { 0x0000007f }, /* GENERAL */\
 294   { 0x00000400 }, /* FLG */\
 295   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 296   { 0x000ff000 }, /* MEM */\
 297   { 0x000ff003 }, /* R02_A_MEM */\
 298   { 0x000ff005 }, /* A_HL_MEM */\
 299   { 0x000ff00c }, /* R1_R3_A_MEM */\
 300   { 0x000ff00f }, /* R03_MEM */\
 301   { 0x000ff03f }, /* A_HI_MEM */\
 302   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 303   { 0x000ff1ff }, /* ALL */\
 304 }
 305
 306 enum reg_class
 307 {
 308   NO_REGS,
 309   SP_REGS,
 310   FB_REGS,
 311   SB_REGS,
 312   CR_REGS,
 313   R0_REGS,
 314   R1_REGS,
 315   R2_REGS,
 316   R3_REGS,
 317   R02_REGS,
 318   R13_REGS,
 319   HL_REGS,
 320   QI_REGS,
 321   R23_REGS,
 322   R03_REGS,
 323   DI_REGS,
 324   A0_REGS,
 325   A1_REGS,
 326   A_REGS,
 327   AD_REGS,
 328   PS_REGS,
 329   SI_REGS,
 330   HI_REGS,
 331   R02A_REGS,
 332   RA_REGS,
 333   GENERAL_REGS,
 334   FLG_REGS,
 335   HC_REGS,
 336   MEM_REGS,
 337   R02_A_MEM_REGS,
 338   A_HL_MEM_REGS,
 339   R1_R3_A_MEM_REGS,
 340   R03_MEM_REGS,
 341   A_HI_MEM_REGS,
 342   A_AD_CR_MEM_SI_REGS,
 343   ALL_REGS,
 344   LIM_REG_CLASSES
 345 };
 346
 347 #define N_REG_CLASSES LIM_REG_CLASSES
 348
 349 #define REG_CLASS_NAMES {\
 350 "NO_REGS", \
 351 "SP_REGS", \
 352 "FB_REGS", \
 353 "SB_REGS", \
 354 "CR_REGS", \
 355 "R0_REGS", \
 356 "R1_REGS", \
 357 "R2_REGS", \
 358 "R3_REGS", \
 359 "R02_REGS", \
 360 "R13_REGS", \
 361 "HL_REGS", \
 362 "QI_REGS", \
 363 "R23_REGS", \
 364 "R03_REGS", \
 365 "DI_REGS", \
 366 "A0_REGS", \
 367 "A1_REGS", \
 368 "A_REGS", \
 369 "AD_REGS", \
 370 "PS_REGS", \
 371 "SI_REGS", \
 372 "HI_REGS", \
 373 "R02A_REGS", \
 374 "RA_REGS", \
 375 "GENERAL_REGS", \
 376 "FLG_REGS", \
 377 "HC_REGS", \
 378 "MEM_REGS", \
 379 "R02_A_MEM_REGS", \
 380 "A_HL_MEM_REGS", \
 381 "R1_R3_A_MEM_REGS", \
 382 "R03_MEM_REGS", \
 383 "A_HI_MEM_REGS", \
 384 "A_AD_CR_MEM_SI_REGS", \
 385 "ALL_REGS", \
 386 }
 387
 388 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 389
 390 /* We support simple displacements off address registers, nothing else.  */
 391 #define BASE_REG_CLASS A_REGS
 392 #define INDEX_REG_CLASS NO_REGS
 393
 394 /* We primarily use the new "long" constraint names, with the initial
 395    letter classifying the constraint type and following letters
 396    specifying which.  The types are:
 397
 398    I - integer values
 399    R - register classes
 400    S - memory references (M was used)
 401    A - addresses (currently unused)
 402 */
 403
 404 #define CONSTRAINT_LEN(CHAR,STR) \
 405         ((CHAR) == 'I' ? 3 \
 406          : (CHAR) == 'R' ? 3 \
 407          : (CHAR) == 'S' ? 2 \
 408          : (CHAR) == 'A' ? 2 \
 409          : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
 410 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
 411         (enum reg_class) m32c_reg_class_from_constraint (CHAR, STR)
 412
 413 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 414 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 415
 416 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
 417 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
 418 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \
 419   (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
 420
 421 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
 422   (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
 423
 424 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 425
 426 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
 427
 428 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
 429
 430 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
 431         m32c_const_ok_for_constraint_p (VALUE, C, STR)
 432 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
 433 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
 434         m32c_extra_constraint_p (VALUE, C, STR)
 435 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \
 436         m32c_extra_memory_constraint (C, STR)
 437 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
 438         m32c_extra_address_constraint (C, STR)
 439
 440 /* STACK AND CALLING */
 441
 442 /* Frame Layout */
 443
 444 /* Standard push/pop stack, no surprises here.  */
 445
 446 #define STACK_GROWS_DOWNWARD 1
 447 #define STACK_PUSH_CODE PRE_DEC
 448 #define FRAME_GROWS_DOWNWARD 1
 449
 450 #define STARTING_FRAME_OFFSET 0
 451 #define FIRST_PARM_OFFSET(F) 0
 452
 453 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 454
 455 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 456 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 457
 458 /* Exception Handling Support */
 459
 460 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 461 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 462
 463 /* Registers That Address the Stack Frame */
 464
 465 #ifndef FP_REGNO
 466 #define FP_REGNO 7
 467 #endif
 468 #ifndef SP_REGNO
 469 #define SP_REGNO 8
 470 #endif
 471 #define AP_REGNO 11
 472
 473 #define STACK_POINTER_REGNUM    SP_REGNO
 474 #define FRAME_POINTER_REGNUM    FP_REGNO
 475 #define ARG_POINTER_REGNUM      AP_REGNO
 476
 477 /* The static chain must be pointer-capable.  */
 478 #define STATIC_CHAIN_REGNUM A0_REGNO
 479
 480 #define DWARF_FRAME_REGISTERS 20
 481 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 482 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
 483
 484 #undef ASM_PREFERRED_EH_DATA_FORMAT
 485 /* This is the same as the default in practice, except that by making
 486    it explicit we tell binutils what size pointers to use.  */
 487 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 488   (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
 489
 490 /* Eliminating Frame Pointer and Arg Pointer */
 491
 492 #define ELIMINABLE_REGS \
 493   {{AP_REGNO, SP_REGNO}, \
 494    {AP_REGNO, FB_REGNO}, \
 495    {FB_REGNO, SP_REGNO}}
 496
 497 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 498         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 499
 500 /* Passing Function Arguments on the Stack */
 501
 502 #define PUSH_ARGS 1
 503 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 504 #define CALL_POPS_ARGS(C) 0
 505
 506 /* Passing Arguments in Registers */
 507
 508 typedef struct m32c_cumulative_args
 509 {
 510   /* For address of return value buffer (structures are returned by
 511      passing the address of a buffer as an invisible first argument.
 512      This identifies it).  If set, the current parameter will be put
 513      on the stack, regardless of type.  */
 514   int force_mem;
 515   /* First parm is 1, parm 0 is hidden pointer for returning
 516      aggregates.  */
 517   int parm_num;
 518 } m32c_cumulative_args;
 519
 520 #define CUMULATIVE_ARGS m32c_cumulative_args
 521 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 522         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 523 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
 524 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 525
 526 /* How Large Values Are Returned */
 527
 528 #define DEFAULT_PCC_STRUCT_RETURN 1
 529
 530 /* Function Entry and Exit */
 531
 532 #define EXIT_IGNORE_STACK 0
 533 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 534 #define EH_USES(REGNO) 0        /* FIXME */
 535
 536 /* Generating Code for Profiling */
 537
 538 #define FUNCTION_PROFILER(FILE,LABELNO)
 539
 540 /* Implementing the Varargs Macros */
 541
 542 /* Trampolines for Nested Functions */
 543
 544 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 545 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 546
 547 /* Addressing Modes */
 548
 549 #define HAVE_PRE_DECREMENT 1
 550 #define HAVE_POST_INCREMENT 1
 551 #define MAX_REGS_PER_ADDRESS 1
 552
 553 /* This is passed to the macros below, so that they can be implemented
 554    in m32c.c.  */
 555 #ifdef REG_OK_STRICT
 556 #define REG_OK_STRICT_V 1
 557 #else
 558 #define REG_OK_STRICT_V 0
 559 #endif
 560
 561 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 562 #define REG_OK_FOR_INDEX_P(X) 0
 563
 564 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 565
 566 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 567         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 568           goto WIN;
 569
 570 #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
 571
 572 /* Address spaces.  */
 573 #define ADDR_SPACE_FAR  1
 574
 575
 576 /* Condition Code Status */
 577
 578 #define REVERSIBLE_CC_MODE(MODE) 1
 579
 580 /* Dividing the Output into Sections (Texts, Data, ...) */
 581
 582 #define TEXT_SECTION_ASM_OP ".text"
 583 #define DATA_SECTION_ASM_OP ".data"
 584 #define BSS_SECTION_ASM_OP ".bss"
 585
 586 #define CTOR_LIST_BEGIN
 587 #define CTOR_LIST_END
 588 #define DTOR_LIST_BEGIN
 589 #define DTOR_LIST_END
 590 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 591 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 592 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 593 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 594
 595 /* The Overall Framework of an Assembler File */
 596
 597 #define ASM_COMMENT_START ";"
 598 #define ASM_APP_ON ""
 599 #define ASM_APP_OFF ""
 600
 601 /* Output and Generation of Labels */
 602
 603 #define GLOBAL_ASM_OP "\t.global\t"
 604
 605 /* Output of Assembler Instructions */
 606
 607 #define REGISTER_NAMES {        \
 608   "r0", "r2", "r1", "r3", \
 609   "a0", "a1", "sb", "fb", "sp", \
 610   "pc", "flg", "argp", \
 611   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 612 }
 613
 614 #define ADDITIONAL_REGISTER_NAMES { \
 615   {"r0l", 0}, \
 616   {"r1l", 2}, \
 617   {"r0r2", 0}, \
 618   {"r1r3", 2}, \
 619   {"a0a1", 4}, \
 620   {"r0r2r1r3", 0} }
 621
 622 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
 623 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
 624 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
 625
 626 #undef USER_LABEL_PREFIX
 627 #define USER_LABEL_PREFIX "_"
 628
 629 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 630 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 631
 632 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 633         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
 634
 635 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 636         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
 637
 638
 639 /* Output of Dispatch Tables */
 640
 641 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 642         fprintf (S, "\t.word L%d\n", V)
 643
 644 /* Assembler Commands for Exception Regions */
 645
 646 #define DWARF_CIE_DATA_ALIGNMENT -1
 647
 648 /* Assembler Commands for Alignment */
 649
 650 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 651         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 652
 653 /* Controlling Debugging Information Format */
 654
 655 #define DWARF2_ADDR_SIZE        4
 656
 657 /* Miscellaneous Parameters */
 658
 659 #define HAS_LONG_COND_BRANCH false
 660 #define HAS_LONG_UNCOND_BRANCH true
 661 #define CASE_VECTOR_MODE SImode
 662 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 663
 664 #define MOVE_MAX 4
 665 #define TRULY_NOOP_TRUNCATION(op,ip) 1
 666
 667 #define STORE_FLAG_VALUE 1
 668
 669 /* 16- or 24-bit pointers */
 670 #define Pmode (TARGET_A16 ? HImode : PSImode)
 671 #define FUNCTION_MODE QImode
 672
 673 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 674
 675 #endif