1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
38 #include "m32r-protos.h"
40 /* Save the operands last given to a compare for use when we
41 generate a scc or bcc insn. */
42 rtx m32r_compare_op0
, m32r_compare_op1
;
44 /* Array of valid operand punctuation characters. */
45 char m32r_punct_chars
[256];
47 /* Selected code model. */
48 const char * m32r_model_string
= M32R_MODEL_DEFAULT
;
49 enum m32r_model m32r_model
;
51 /* Selected SDA support. */
52 const char * m32r_sdata_string
= M32R_SDATA_DEFAULT
;
53 enum m32r_sdata m32r_sdata
;
55 /* Scheduler support */
56 int m32r_sched_odd_word_p
;
58 /* Forward declaration. */
59 static void init_reg_tables
PARAMS ((void));
61 /* Called by OVERRIDE_OPTIONS to initialize various things. */
68 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
69 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
70 m32r_punct_chars
['#'] = 1;
71 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
73 /* Provide default value if not specified. */
75 g_switch_value
= SDATA_DEFAULT_SIZE
;
77 if (strcmp (m32r_model_string
, "small") == 0)
78 m32r_model
= M32R_MODEL_SMALL
;
79 else if (strcmp (m32r_model_string
, "medium") == 0)
80 m32r_model
= M32R_MODEL_MEDIUM
;
81 else if (strcmp (m32r_model_string
, "large") == 0)
82 m32r_model
= M32R_MODEL_LARGE
;
84 error ("bad value (%s) for -mmodel switch", m32r_model_string
);
86 if (strcmp (m32r_sdata_string
, "none") == 0)
87 m32r_sdata
= M32R_SDATA_NONE
;
88 else if (strcmp (m32r_sdata_string
, "sdata") == 0)
89 m32r_sdata
= M32R_SDATA_SDATA
;
90 else if (strcmp (m32r_sdata_string
, "use") == 0)
91 m32r_sdata
= M32R_SDATA_USE
;
93 error ("bad value (%s) for -msdata switch", m32r_sdata_string
);
96 /* Vectors to keep interesting information about registers where it can easily
97 be got. We use to use the actual mode value as the bit number, but there
98 is (or may be) more than 32 modes now. Instead we use two tables: one
99 indexed by hard register number, and one indexed by mode. */
101 /* The purpose of m32r_mode_class is to shrink the range of modes so that
102 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
103 mapped into one m32r_mode_class mode. */
108 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
109 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
112 /* Modes for condition codes. */
113 #define C_MODES (1 << (int) C_MODE)
115 /* Modes for single-word and smaller quantities. */
116 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
118 /* Modes for double-word and smaller quantities. */
119 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
121 /* Modes for quad-word and smaller quantities. */
122 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
124 /* Modes for accumulators. */
125 #define A_MODES (1 << (int) A_MODE)
127 /* Value is 1 if register/mode pair is acceptable on arc. */
129 unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
131 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
132 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
133 S_MODES
, C_MODES
, A_MODES
136 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
138 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
145 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
147 switch (GET_MODE_CLASS (i
))
150 case MODE_PARTIAL_INT
:
151 case MODE_COMPLEX_INT
:
152 if (GET_MODE_SIZE (i
) <= 4)
153 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
154 else if (GET_MODE_SIZE (i
) == 8)
155 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
156 else if (GET_MODE_SIZE (i
) == 16)
157 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
158 else if (GET_MODE_SIZE (i
) == 32)
159 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
161 m32r_mode_class
[i
] = 0;
164 case MODE_COMPLEX_FLOAT
:
165 if (GET_MODE_SIZE (i
) <= 4)
166 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
167 else if (GET_MODE_SIZE (i
) == 8)
168 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
169 else if (GET_MODE_SIZE (i
) == 16)
170 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
171 else if (GET_MODE_SIZE (i
) == 32)
172 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
174 m32r_mode_class
[i
] = 0;
178 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
179 we must explicitly check for them here. */
180 if (i
== (int) CCmode
)
181 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
183 m32r_mode_class
[i
] = 0;
188 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
191 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
192 else if (i
== ARG_POINTER_REGNUM
)
193 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
195 m32r_regno_reg_class
[i
] = NO_REGS
;
199 /* M32R specific attribute support.
201 interrupt - for interrupt functions
203 model - select code model used to access object
205 small: addresses use 24 bits, use bl to make calls
206 medium: addresses use 32 bits, use bl to make calls
207 large: addresses use 32 bits, use seth/add3/jl to make calls
209 Grep for MODEL in m32r.h for more info.
212 static tree interrupt_ident1
;
213 static tree interrupt_ident2
;
214 static tree model_ident1
;
215 static tree model_ident2
;
216 static tree small_ident1
;
217 static tree small_ident2
;
218 static tree medium_ident1
;
219 static tree medium_ident2
;
220 static tree large_ident1
;
221 static tree large_ident2
;
224 init_idents
PARAMS ((void))
226 if (interrupt_ident1
== 0)
228 interrupt_ident1
= get_identifier ("interrupt");
229 interrupt_ident2
= get_identifier ("__interrupt__");
230 model_ident1
= get_identifier ("model");
231 model_ident2
= get_identifier ("__model__");
232 small_ident1
= get_identifier ("small");
233 small_ident2
= get_identifier ("__small__");
234 medium_ident1
= get_identifier ("medium");
235 medium_ident2
= get_identifier ("__medium__");
236 large_ident1
= get_identifier ("large");
237 large_ident2
= get_identifier ("__large__");
241 /* Return nonzero if IDENTIFIER is a valid decl attribute. */
244 m32r_valid_machine_decl_attribute (type
, attributes
, identifier
, args
)
245 tree type ATTRIBUTE_UNUSED
;
246 tree attributes ATTRIBUTE_UNUSED
;
252 if ((identifier
== interrupt_ident1
253 || identifier
== interrupt_ident2
)
254 && list_length (args
) == 0)
257 if ((identifier
== model_ident1
258 || identifier
== model_ident2
)
259 && list_length (args
) == 1
260 && (TREE_VALUE (args
) == small_ident1
261 || TREE_VALUE (args
) == small_ident2
262 || TREE_VALUE (args
) == medium_ident1
263 || TREE_VALUE (args
) == medium_ident2
264 || TREE_VALUE (args
) == large_ident1
265 || TREE_VALUE (args
) == large_ident2
))
271 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
272 and two if they are nearly compatible (which causes a warning to be
276 m32r_comp_type_attributes (type1
, type2
)
277 tree type1 ATTRIBUTE_UNUSED
;
278 tree type2 ATTRIBUTE_UNUSED
;
283 /* Set the default attributes for TYPE. */
286 m32r_set_default_type_attributes (type
)
287 tree type ATTRIBUTE_UNUSED
;
291 /* A C statement or statements to switch to the appropriate
292 section for output of DECL. DECL is either a `VAR_DECL' node
293 or a constant of some sort. RELOC indicates whether forming
294 the initial value of DECL requires link-time relocations. */
297 m32r_select_section (decl
, reloc
)
301 if (TREE_CODE (decl
) == STRING_CST
)
303 if (! flag_writable_strings
)
308 else if (TREE_CODE (decl
) == VAR_DECL
)
310 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl
), 0), 0)))
312 else if ((flag_pic
&& reloc
)
313 || !TREE_READONLY (decl
)
314 || TREE_SIDE_EFFECTS (decl
)
315 || !DECL_INITIAL (decl
)
316 || (DECL_INITIAL (decl
) != error_mark_node
317 && !TREE_CONSTANT (DECL_INITIAL (decl
))))
326 /* Encode section information of DECL, which is either a VAR_DECL,
327 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
329 For the M32R we want to record:
331 - whether the object lives in .sdata/.sbss.
332 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
334 - what code model should be used to access the object
335 small: recorded with no flag - for space efficiency since they'll
337 medium: prefixed with MEDIUM_FLAG_CHAR
338 large: prefixed with LARGE_FLAG_CHAR
342 m32r_encode_section_info (decl
)
348 switch (TREE_CODE (decl
))
352 model
= lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl
));
356 /* ??? document all others that can appear here */
361 /* Only mark the object as being small data area addressable if
362 it hasn't been explicitly marked with a code model.
364 The user can explicitly put an object in the small data area with the
365 section attribute. If the object is in sdata/sbss and marked with a
366 code model do both [put the object in .sdata and mark it as being
367 addressed with a specific code model - don't mark it as being addressed
368 with an SDA reloc though]. This is ok and might be useful at times. If
369 the object doesn't fit the linker will give an error. */
373 if (TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd'
374 && DECL_SECTION_NAME (decl
) != NULL_TREE
)
376 char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
377 if (! strcmp (name
, ".sdata") || ! strcmp (name
, ".sbss"))
379 #if 0 /* ??? There's no reason to disallow this, is there? */
380 if (TREE_READONLY (decl
))
381 error_with_decl (decl
, "const objects cannot go in .sdata/.sbss");
383 prefix
= SDATA_FLAG_CHAR
;
388 if (TREE_CODE (decl
) == VAR_DECL
389 && ! TREE_READONLY (decl
)
390 && ! TARGET_SDATA_NONE
)
392 int size
= int_size_in_bytes (TREE_TYPE (decl
));
394 if (size
> 0 && size
<= g_switch_value
)
395 prefix
= SDATA_FLAG_CHAR
;
400 /* If data area not decided yet, check for a code model. */
409 id
= TREE_VALUE (TREE_VALUE (model
));
411 if (id
== small_ident1
|| id
== small_ident2
)
412 ; /* don't mark the symbol specially */
413 else if (id
== medium_ident1
|| id
== medium_ident2
)
414 prefix
= MEDIUM_FLAG_CHAR
;
415 else if (id
== large_ident1
|| id
== large_ident2
)
416 prefix
= LARGE_FLAG_CHAR
;
418 abort (); /* shouldn't happen */
422 if (TARGET_MODEL_SMALL
)
423 ; /* don't mark the symbol specially */
424 else if (TARGET_MODEL_MEDIUM
)
425 prefix
= MEDIUM_FLAG_CHAR
;
426 else if (TARGET_MODEL_LARGE
)
427 prefix
= LARGE_FLAG_CHAR
;
429 abort (); /* shouldn't happen */
435 rtx rtl
= (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
436 ? TREE_CST_RTL (decl
) : DECL_RTL (decl
));
437 const char *str
= XSTR (XEXP (rtl
, 0), 0);
438 int len
= strlen (str
);
439 char *newstr
= ggc_alloc (len
+ 2);
440 strcpy (newstr
+ 1, str
);
442 XSTR (XEXP (rtl
, 0), 0) = newstr
;
446 /* Do anything needed before RTL is emitted for each function. */
449 m32r_init_expanders ()
451 /* ??? At one point there was code here. The function is left in
452 to make it easy to experiment. */
455 /* Acceptable arguments to the call insn. */
458 call_address_operand (op
, mode
)
460 enum machine_mode mode
;
462 return symbolic_operand (op
, mode
);
464 /* Constants and values in registers are not OK, because
465 the m32r BL instruction can only support PC relative branching. */
469 call_operand (op
, mode
)
471 enum machine_mode mode
;
473 if (GET_CODE (op
) != MEM
)
476 return call_address_operand (op
, mode
);
479 /* Returns 1 if OP is a symbol reference. */
482 symbolic_operand (op
, mode
)
484 enum machine_mode mode ATTRIBUTE_UNUSED
;
486 switch (GET_CODE (op
))
498 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
501 small_data_operand (op
, mode
)
503 enum machine_mode mode ATTRIBUTE_UNUSED
;
505 if (! TARGET_SDATA_USE
)
508 if (GET_CODE (op
) == SYMBOL_REF
)
509 return SDATA_NAME_P (XSTR (op
, 0));
511 if (GET_CODE (op
) == CONST
512 && GET_CODE (XEXP (op
, 0)) == PLUS
513 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
514 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
515 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
516 return SDATA_NAME_P (XSTR (XEXP (XEXP (op
, 0), 0), 0));
521 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
524 addr24_operand (op
, mode
)
526 enum machine_mode mode ATTRIBUTE_UNUSED
;
528 if (GET_CODE (op
) == LABEL_REF
)
529 return TARGET_ADDR24
;
531 if (GET_CODE (op
) == SYMBOL_REF
)
532 return (SMALL_NAME_P (XSTR (op
, 0))
534 && (CONSTANT_POOL_ADDRESS_P (op
)
535 || LIT_NAME_P (XSTR (op
, 0)))));
537 if (GET_CODE (op
) == CONST
538 && GET_CODE (XEXP (op
, 0)) == PLUS
539 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
540 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
541 && UINT24_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
543 rtx sym
= XEXP (XEXP (op
, 0), 0);
544 return (SMALL_NAME_P (XSTR (sym
, 0))
546 && (CONSTANT_POOL_ADDRESS_P (op
)
547 || LIT_NAME_P (XSTR (op
, 0)))));
553 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
556 addr32_operand (op
, mode
)
558 enum machine_mode mode
;
560 if (GET_CODE (op
) == LABEL_REF
)
561 return TARGET_ADDR32
;
563 if (GET_CODE (op
) == SYMBOL_REF
)
564 return (! addr24_operand (op
, mode
)
565 && ! small_data_operand (op
, mode
));
567 if (GET_CODE (op
) == CONST
568 && GET_CODE (XEXP (op
, 0)) == PLUS
569 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
570 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
572 return (! addr24_operand (op
, mode
)
573 && ! small_data_operand (op
, mode
));
579 /* Return 1 if OP is a function that can be called with the `bl' insn. */
582 call26_operand (op
, mode
)
584 enum machine_mode mode ATTRIBUTE_UNUSED
;
586 if (GET_CODE (op
) == SYMBOL_REF
)
587 return ! LARGE_NAME_P (XSTR (op
, 0));
589 return TARGET_CALL26
;
592 /* Returns 1 if OP is an acceptable operand for seth/add3. */
595 seth_add3_operand (op
, mode
)
597 enum machine_mode mode ATTRIBUTE_UNUSED
;
599 if (GET_CODE (op
) == SYMBOL_REF
600 || GET_CODE (op
) == LABEL_REF
)
603 if (GET_CODE (op
) == CONST
604 && GET_CODE (XEXP (op
, 0)) == PLUS
605 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
606 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
607 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
613 /* Return true if OP is a signed 8 bit immediate value. */
616 int8_operand (op
, mode
)
618 enum machine_mode mode ATTRIBUTE_UNUSED
;
620 if (GET_CODE (op
) != CONST_INT
)
622 return INT8_P (INTVAL (op
));
625 /* Return true if OP is a signed 16 bit immediate value
626 useful in comparisons. */
629 cmp_int16_operand (op
, mode
)
631 enum machine_mode mode ATTRIBUTE_UNUSED
;
633 if (GET_CODE (op
) != CONST_INT
)
635 return CMP_INT16_P (INTVAL (op
));
638 /* Return true if OP is an unsigned 16 bit immediate value. */
641 uint16_operand (op
, mode
)
643 enum machine_mode mode ATTRIBUTE_UNUSED
;
645 if (GET_CODE (op
) != CONST_INT
)
647 return UINT16_P (INTVAL (op
));
650 /* Return true if OP is a register or signed 16 bit value. */
653 reg_or_int16_operand (op
, mode
)
655 enum machine_mode mode
;
657 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
658 return register_operand (op
, mode
);
659 if (GET_CODE (op
) != CONST_INT
)
661 return INT16_P (INTVAL (op
));
664 /* Return true if OP is a register or an unsigned 16 bit value. */
667 reg_or_uint16_operand (op
, mode
)
669 enum machine_mode mode
;
671 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
672 return register_operand (op
, mode
);
673 if (GET_CODE (op
) != CONST_INT
)
675 return UINT16_P (INTVAL (op
));
678 /* Return true if OP is a register or an integer value that can be
679 used is SEQ/SNE. We can use either XOR of the value or ADD of
680 the negative of the value for the constant. Don't allow 0,
681 because that is special cased. */
684 reg_or_eq_int16_operand (op
, mode
)
686 enum machine_mode mode
;
690 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
691 return register_operand (op
, mode
);
693 if (GET_CODE (op
) != CONST_INT
)
697 return (value
!= 0) && (UINT16_P (value
) || CMP_INT16_P (-value
));
700 /* Return true if OP is a register or signed 16 bit value for compares. */
703 reg_or_cmp_int16_operand (op
, mode
)
705 enum machine_mode mode
;
707 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
708 return register_operand (op
, mode
);
709 if (GET_CODE (op
) != CONST_INT
)
711 return CMP_INT16_P (INTVAL (op
));
714 /* Return true if OP is a const_int requiring two instructions to load. */
717 two_insn_const_operand (op
, mode
)
719 enum machine_mode mode ATTRIBUTE_UNUSED
;
721 if (GET_CODE (op
) != CONST_INT
)
723 if (INT16_P (INTVAL (op
))
724 || UINT24_P (INTVAL (op
))
725 || UPPER16_P (INTVAL (op
)))
730 /* Return true if OP is an acceptable argument for a single word
734 move_src_operand (op
, mode
)
736 enum machine_mode mode
;
738 switch (GET_CODE (op
))
742 return addr24_operand (op
, mode
);
744 /* ??? We allow more cse opportunities if we only allow constants
745 loadable with one insn, and split the rest into two. The instances
746 where this would help should be rare and the current way is
748 return INT32_P (INTVAL (op
));
750 return TARGET_ADDR24
;
754 else if (mode
== SImode
)
756 /* Large unsigned constants are represented as const_double's. */
757 unsigned HOST_WIDE_INT low
, high
;
759 low
= CONST_DOUBLE_LOW (op
);
760 high
= CONST_DOUBLE_HIGH (op
);
761 return high
== 0 && low
<= 0xffffffff;
766 return register_operand (op
, mode
);
768 /* (subreg (mem ...) ...) can occur here if the inner part was once a
769 pseudo-reg and is now a stack slot. */
770 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
771 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
773 return register_operand (op
, mode
);
775 if (GET_CODE (XEXP (op
, 0)) == PRE_INC
776 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
777 return 0; /* loads can't do pre-{inc,dec} */
778 return address_operand (XEXP (op
, 0), mode
);
784 /* Return true if OP is an acceptable argument for a double word
788 move_double_src_operand (op
, mode
)
790 enum machine_mode mode
;
792 switch (GET_CODE (op
))
798 return register_operand (op
, mode
);
800 /* (subreg (mem ...) ...) can occur here if the inner part was once a
801 pseudo-reg and is now a stack slot. */
802 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
803 return move_double_src_operand (SUBREG_REG (op
), mode
);
805 return register_operand (op
, mode
);
807 /* Disallow auto inc/dec for now. */
808 if (GET_CODE (XEXP (op
, 0)) == PRE_DEC
809 || GET_CODE (XEXP (op
, 0)) == PRE_INC
)
811 return address_operand (XEXP (op
, 0), mode
);
817 /* Return true if OP is an acceptable argument for a move destination. */
820 move_dest_operand (op
, mode
)
822 enum machine_mode mode
;
824 switch (GET_CODE (op
))
827 return register_operand (op
, mode
);
829 /* (subreg (mem ...) ...) can occur here if the inner part was once a
830 pseudo-reg and is now a stack slot. */
831 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
832 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
834 return register_operand (op
, mode
);
836 if (GET_CODE (XEXP (op
, 0)) == POST_INC
)
837 return 0; /* stores can't do post inc */
838 return address_operand (XEXP (op
, 0), mode
);
844 /* Return 1 if OP is a DImode const we want to handle inline.
845 This must match the code in the movdi pattern.
846 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
852 rtx high_rtx
, low_rtx
;
853 HOST_WIDE_INT high
, low
;
855 split_double (op
, &high_rtx
, &low_rtx
);
856 high
= INTVAL (high_rtx
);
857 low
= INTVAL (low_rtx
);
858 /* Pick constants loadable with 2 16 bit `ldi' insns. */
859 if (high
>= -128 && high
<= 127
860 && low
>= -128 && low
<= 127)
865 /* Return 1 if OP is a DFmode const we want to handle inline.
866 This must match the code in the movdf pattern.
867 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
876 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
877 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
878 if (l
[0] == 0 && l
[1] == 0)
880 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
885 /* Return 1 if OP is an EQ or NE comparison operator. */
888 eqne_comparison_operator (op
, mode
)
890 enum machine_mode mode ATTRIBUTE_UNUSED
;
892 enum rtx_code code
= GET_CODE (op
);
894 if (GET_RTX_CLASS (code
) != '<')
896 return (code
== EQ
|| code
== NE
);
899 /* Return 1 if OP is a signed comparison operator. */
902 signed_comparison_operator (op
, mode
)
904 enum machine_mode mode ATTRIBUTE_UNUSED
;
906 enum rtx_code code
= GET_CODE (op
);
908 if (GET_RTX_CLASS (code
) != '<')
910 return (code
== EQ
|| code
== NE
911 || code
== LT
|| code
== LE
|| code
== GT
|| code
== GE
);
914 /* Return 1 if OP is (mem (reg ...)).
915 This is used in insn length calcs. */
918 memreg_operand (op
, mode
)
920 enum machine_mode mode ATTRIBUTE_UNUSED
;
922 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == REG
;
925 /* Return true if OP is an acceptable input argument for a zero/sign extend
929 extend_operand (op
, mode
)
931 enum machine_mode mode
;
935 switch (GET_CODE (op
))
939 return register_operand (op
, mode
);
943 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
944 return 0; /* loads can't do pre inc/pre dec */
946 return address_operand (addr
, mode
);
953 /* Return non-zero if the operand is an insn that is a small insn.
954 Allow const_int 0 as well, which is a placeholder for NOP slots. */
957 small_insn_p (op
, mode
)
959 enum machine_mode mode ATTRIBUTE_UNUSED
;
961 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
967 return get_attr_length (op
) == 2;
970 /* Return non-zero if the operand is an insn that is a large insn. */
973 large_insn_p (op
, mode
)
975 enum machine_mode mode ATTRIBUTE_UNUSED
;
980 return get_attr_length (op
) != 2;
986 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
987 return the mode to be used for the comparison. */
990 m32r_select_cc_mode (op
, x
, y
)
991 int op ATTRIBUTE_UNUSED
;
992 rtx x ATTRIBUTE_UNUSED
;
993 rtx y ATTRIBUTE_UNUSED
;
998 /* X and Y are two things to compare using CODE. Emit the compare insn and
999 return the rtx for compare [arg0 of the if_then_else].
1000 If need_compare is true then the comparison insn must be generated, rather
1001 than being susummed into the following branch instruction. */
1004 gen_compare (code
, x
, y
, need_compare
)
1009 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
1010 enum rtx_code compare_code
, branch_code
;
1011 rtx cc_reg
= gen_rtx_REG (mode
, CARRY_REGNUM
);
1016 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
1017 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
1018 case LT
: compare_code
= LT
; branch_code
= NE
; break;
1019 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
1020 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
1021 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
1022 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
1023 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
1024 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
1025 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
1033 switch (compare_code
)
1036 if (GET_CODE (y
) == CONST_INT
1037 && CMP_INT16_P (INTVAL (y
)) /* reg equal to small const. */
1040 rtx tmp
= gen_reg_rtx (SImode
);
1042 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1046 else if (CONSTANT_P (y
)) /* reg equal to const. */
1048 rtx tmp
= force_reg (GET_MODE (x
), y
);
1052 if (register_operand (y
, SImode
) /* reg equal to reg. */
1053 || y
== const0_rtx
) /* req equal to zero. */
1055 emit_insn (gen_cmp_eqsi_insn (x
, y
));
1057 return gen_rtx (code
, mode
, cc_reg
, const0_rtx
);
1062 if (register_operand (y
, SImode
)
1063 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1065 rtx tmp
= gen_reg_rtx (SImode
); /* reg compared to reg. */
1070 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1074 if (y
== const0_rtx
)
1077 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1078 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1082 if (GET_CODE (y
) == CONST_INT
)
1083 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1085 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1086 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1090 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1097 return gen_rtx (code
, mode
, cc_reg
, const0_rtx
);
1102 if (register_operand (y
, SImode
)
1103 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1105 rtx tmp
= gen_reg_rtx (SImode
); /* reg (unsigned) compared to reg. */
1110 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1114 if (y
== const0_rtx
)
1117 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1118 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1122 if (GET_CODE (y
) == CONST_INT
)
1123 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1125 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1126 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1130 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1137 return gen_rtx (code
, mode
, cc_reg
, const0_rtx
);
1147 /* reg/reg equal comparison */
1148 if (compare_code
== EQ
1149 && register_operand (y
, SImode
))
1150 return gen_rtx (code
, mode
, x
, y
);
1152 /* reg/zero signed comparison */
1153 if ((compare_code
== EQ
|| compare_code
== LT
)
1155 return gen_rtx (code
, mode
, x
, y
);
1157 /* reg/smallconst equal comparison */
1158 if (compare_code
== EQ
1159 && GET_CODE (y
) == CONST_INT
1160 && CMP_INT16_P (INTVAL (y
)))
1162 rtx tmp
= gen_reg_rtx (SImode
);
1163 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1164 return gen_rtx (code
, mode
, tmp
, const0_rtx
);
1167 /* reg/const equal comparison */
1168 if (compare_code
== EQ
1171 rtx tmp
= force_reg (GET_MODE (x
), y
);
1172 return gen_rtx (code
, mode
, x
, tmp
);
1179 y
= force_reg (GET_MODE (x
), y
);
1183 (code
== LTU
|| code
== LEU
|| code
== GTU
|| code
== GEU
)
1184 ? uint16_operand (y
, GET_MODE (y
))
1185 : reg_or_cmp_int16_operand (y
, GET_MODE (y
));
1188 y
= force_reg (GET_MODE (x
), y
);
1192 switch (compare_code
)
1195 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1198 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1201 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1208 return gen_rtx (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (mode
));
1211 /* Split a 2 word move (DI or DF) into component parts. */
1214 gen_split_move_double (operands
)
1217 enum machine_mode mode
= GET_MODE (operands
[0]);
1218 rtx dest
= operands
[0];
1219 rtx src
= operands
[1];
1222 /* We might have (SUBREG (MEM)) here, so just get rid of the
1223 subregs to make this code simpler. It is safe to call
1224 alter_subreg any time after reload. */
1225 if (GET_CODE (dest
) == SUBREG
)
1226 dest
= alter_subreg (dest
);
1227 if (GET_CODE (src
) == SUBREG
)
1228 src
= alter_subreg (src
);
1231 if (GET_CODE (dest
) == REG
)
1233 int dregno
= REGNO (dest
);
1236 if (GET_CODE (src
) == REG
)
1238 int sregno
= REGNO (src
);
1240 int reverse
= (dregno
== sregno
+ 1);
1242 /* We normally copy the low-numbered register first. However, if
1243 the first register operand 0 is the same as the second register of
1244 operand 1, we must copy in the opposite order. */
1245 emit_insn (gen_rtx_SET (VOIDmode
,
1246 operand_subword (dest
, reverse
, TRUE
, mode
),
1247 operand_subword (src
, reverse
, TRUE
, mode
)));
1249 emit_insn (gen_rtx_SET (VOIDmode
,
1250 operand_subword (dest
, !reverse
, TRUE
, mode
),
1251 operand_subword (src
, !reverse
, TRUE
, mode
)));
1254 /* reg = constant */
1255 else if (GET_CODE (src
) == CONST_INT
|| GET_CODE (src
) == CONST_DOUBLE
)
1258 split_double (src
, &words
[0], &words
[1]);
1259 emit_insn (gen_rtx_SET (VOIDmode
,
1260 operand_subword (dest
, 0, TRUE
, mode
),
1263 emit_insn (gen_rtx_SET (VOIDmode
,
1264 operand_subword (dest
, 1, TRUE
, mode
),
1269 else if (GET_CODE (src
) == MEM
)
1271 /* If the high-address word is used in the address, we must load it
1272 last. Otherwise, load it first. */
1273 rtx addr
= XEXP (src
, 0);
1274 int reverse
= (refers_to_regno_p (dregno
, dregno
+1, addr
, 0) != 0);
1276 /* We used to optimize loads from single registers as
1280 if r3 were not used subsequently. However, the REG_NOTES aren't
1281 propigated correctly by the reload phase, and it can cause bad
1282 code to be generated. We could still try:
1284 ld r1,r3+; ld r2,r3; addi r3,-4
1286 which saves 2 bytes and doesn't force longword alignment. */
1287 emit_insn (gen_rtx_SET (VOIDmode
,
1288 operand_subword (dest
, reverse
, TRUE
, mode
),
1289 change_address (src
, SImode
,
1290 plus_constant (addr
,
1291 reverse
* UNITS_PER_WORD
))));
1293 emit_insn (gen_rtx_SET (VOIDmode
,
1294 operand_subword (dest
, !reverse
, TRUE
, mode
),
1295 change_address (src
, SImode
,
1296 plus_constant (addr
,
1297 (!reverse
) * UNITS_PER_WORD
))));
1305 /* We used to optimize loads from single registers as
1309 if r3 were not used subsequently. However, the REG_NOTES aren't
1310 propigated correctly by the reload phase, and it can cause bad
1311 code to be generated. We could still try:
1313 st r1,r3; st r2,+r3; addi r3,-4
1315 which saves 2 bytes and doesn't force longword alignment. */
1316 else if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
1318 rtx addr
= XEXP (dest
, 0);
1320 emit_insn (gen_rtx_SET (VOIDmode
,
1321 change_address (dest
, SImode
, addr
),
1322 operand_subword (src
, 0, TRUE
, mode
)));
1324 emit_insn (gen_rtx_SET (VOIDmode
,
1325 change_address (dest
, SImode
,
1326 plus_constant (addr
, UNITS_PER_WORD
)),
1327 operand_subword (src
, 1, TRUE
, mode
)));
1333 val
= gen_sequence ();
1339 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1342 function_arg_partial_nregs (cum
, mode
, type
, named
)
1343 CUMULATIVE_ARGS
*cum
;
1344 enum machine_mode mode
;
1346 int named ATTRIBUTE_UNUSED
;
1349 int size
= (((mode
== BLKmode
&& type
)
1350 ? int_size_in_bytes (type
)
1351 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1353 if (*cum
>= M32R_MAX_PARM_REGS
)
1355 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1356 ret
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1363 /* Do any needed setup for a variadic function. For the M32R, we must
1364 create a register parameter block, and then copy any anonymous arguments
1365 in registers to memory.
1367 CUM has not been updated for the last named argument which has type TYPE
1368 and mode MODE, and we rely on this fact. */
1371 m32r_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
1372 CUMULATIVE_ARGS
*cum
;
1373 enum machine_mode mode
;
1383 /* All BLKmode values are passed by reference. */
1384 if (mode
== BLKmode
)
1387 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1388 if (current_function_varargs
)
1389 first_anon_arg
= *cum
;
1391 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1392 + ROUND_ADVANCE_ARG (mode
, type
));
1394 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1396 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1397 int first_reg_offset
= first_anon_arg
;
1398 /* Size in words to "pretend" allocate. */
1399 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1402 regblock
= gen_rtx_MEM (BLKmode
,
1403 plus_constant (arg_pointer_rtx
,
1404 FIRST_PARM_OFFSET (0)));
1405 MEM_ALIAS_SET (regblock
) = get_varargs_alias_set ();
1406 move_block_from_reg (first_reg_offset
, regblock
,
1407 size
, size
* UNITS_PER_WORD
);
1409 *pretend_size
= (size
* UNITS_PER_WORD
);
1414 /* Implement `va_arg'. */
1417 m32r_va_arg (valist
, type
)
1420 HOST_WIDE_INT size
, rsize
;
1424 size
= int_size_in_bytes (type
);
1425 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
1429 tree type_ptr
, type_ptr_ptr
;
1431 /* Pass by reference. */
1433 type_ptr
= build_pointer_type (type
);
1434 type_ptr_ptr
= build_pointer_type (type_ptr
);
1436 t
= build (POSTINCREMENT_EXPR
, va_list_type_node
, valist
,
1437 build_int_2 (UNITS_PER_WORD
, 0));
1438 TREE_SIDE_EFFECTS (t
) = 1;
1439 t
= build1 (NOP_EXPR
, type_ptr_ptr
, t
);
1440 TREE_SIDE_EFFECTS (t
) = 1;
1441 t
= build1 (INDIRECT_REF
, type_ptr
, t
);
1443 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1447 /* Pass by value. */
1449 if (size
< UNITS_PER_WORD
)
1451 /* Care for bigendian correction on the aligned address. */
1452 t
= build (PLUS_EXPR
, ptr_type_node
, valist
,
1453 build_int_2 (rsize
- size
, 0));
1454 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1455 addr_rtx
= copy_to_reg (addr_rtx
);
1458 t
= build (PLUS_EXPR
, va_list_type_node
, valist
,
1459 build_int_2 (rsize
, 0));
1460 t
= build (MODIFY_EXPR
, va_list_type_node
, valist
, t
);
1461 TREE_SIDE_EFFECTS (t
) = 1;
1462 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1466 t
= build (POSTINCREMENT_EXPR
, va_list_type_node
, valist
,
1467 build_int_2 (rsize
, 0));
1468 TREE_SIDE_EFFECTS (t
) = 1;
1469 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1477 m32r_adjust_cost (insn
, link
, dep_insn
, cost
)
1478 rtx insn ATTRIBUTE_UNUSED
;
1479 rtx link ATTRIBUTE_UNUSED
;
1480 rtx dep_insn ATTRIBUTE_UNUSED
;
1487 /* Return true if INSN is real instruction bearing insn. */
1493 return (INSN_P (insn
)
1494 && GET_CODE (PATTERN (insn
)) != USE
1495 && GET_CODE (PATTERN (insn
)) != CLOBBER
1496 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
);
1499 /* Increase the priority of long instructions so that the
1500 short instructions are scheduled ahead of the long ones. */
1503 m32r_adjust_priority (insn
, priority
)
1507 if (m32r_is_insn (insn
)
1508 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1515 /* Initialize for scheduling a group of instructions. */
1518 m32r_sched_init (stream
, verbose
)
1519 FILE * stream ATTRIBUTE_UNUSED
;
1520 int verbose ATTRIBUTE_UNUSED
;
1522 m32r_sched_odd_word_p
= FALSE
;
1526 /* Reorder the schedulers priority list if needed */
1529 m32r_sched_reorder (stream
, verbose
, ready
, n_ready
)
1543 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1545 (m32r_sched_odd_word_p
) ? "odd" : "even");
1549 rtx
* long_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1550 rtx
* long_tail
= long_head
;
1551 rtx
* short_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1552 rtx
* short_tail
= short_head
;
1553 rtx
* new_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1554 rtx
* new_tail
= new_head
+ (n_ready
- 1);
1557 /* Loop through the instructions, classifing them as short/long. Try
1558 to keep 2 short together and/or 1 long. Note, the ready list is
1559 actually ordered backwards, so keep it in that manner. */
1560 for (i
= n_ready
-1; i
>= 0; i
--)
1562 rtx insn
= ready
[i
];
1565 if (! m32r_is_insn (insn
))
1567 /* Dump all current short/long insns just in case. */
1568 while (long_head
!= long_tail
)
1569 *new_tail
-- = *long_head
++;
1571 while (short_head
!= short_tail
)
1572 *new_tail
-- = *short_head
++;
1577 ";;\t\t::: Skipping non instruction %d\n",
1584 if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1585 *long_tail
++ = insn
;
1588 *short_tail
++ = insn
;
1592 /* If we are on an odd word, emit a single short instruction if
1594 if (m32r_sched_odd_word_p
&& short_head
!= short_tail
)
1595 *new_tail
-- = *short_head
++;
1597 /* Now dump out all of the long instructions */
1598 while (long_head
!= long_tail
)
1599 *new_tail
-- = *long_head
++;
1601 /* Now dump out all of the short instructions */
1602 while (short_head
!= short_tail
)
1603 *new_tail
-- = *short_head
++;
1605 if (new_tail
+1 != new_head
)
1608 bcopy ((char *) new_head
, (char *) ready
, sizeof (rtx
) * n_ready
);
1612 fprintf (stream
, ";;\t\t::: New ready list: ");
1613 debug_ready_list (ready
, n_ready
);
1616 for (i
= 0; i
< n_ready
; i
++)
1618 rtx insn
= ready
[i
];
1621 fprintf (stream
, " %d", INSN_UID (ready
[i
]));
1623 if (! m32r_is_insn (insn
))
1624 fputs ("(?)", stream
);
1626 else if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1627 fputs ("(l)", stream
);
1630 fputs ("(s)", stream
);
1633 fprintf (stream
, "\n");
1640 /* If we have a machine that can issue a variable # of instructions
1641 per cycle, indicate how many more instructions can be issued
1642 after the current one. */
1644 m32r_sched_variable_issue (stream
, verbose
, insn
, how_many
)
1650 int orig_odd_word_p
= m32r_sched_odd_word_p
;
1651 int short_p
= FALSE
;
1654 if (how_many
> 0 && !TARGET_DEBUG
)
1656 if (! m32r_is_insn (insn
))
1659 else if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1662 m32r_sched_odd_word_p
= 0;
1666 m32r_sched_odd_word_p
= !m32r_sched_odd_word_p
;
1671 if (verbose
> 7 && stream
)
1673 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1674 short_p
? "short" : "long",
1676 orig_odd_word_p
? "odd" : "even",
1682 /* Cost functions. */
1684 /* Provide the costs of an addressing mode that contains ADDR.
1685 If ADDR is not a valid address, its cost is irrelevant.
1687 This function is trivial at the moment. This code doesn't live
1688 in m32r.h so it's easy to experiment. */
1691 m32r_address_cost (addr
)
1692 rtx addr ATTRIBUTE_UNUSED
;
1697 /* Type of function DECL.
1699 The result is cached. To reset the cache at the end of a function,
1700 call with DECL = NULL_TREE. */
1702 enum m32r_function_type
1703 m32r_compute_function_type (decl
)
1707 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1708 /* Last function we were called for. */
1709 static tree last_fn
= NULL_TREE
;
1711 /* Resetting the cached value? */
1712 if (decl
== NULL_TREE
)
1714 fn_type
= M32R_FUNCTION_UNKNOWN
;
1715 last_fn
= NULL_TREE
;
1719 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1722 /* Compute function type. */
1723 fn_type
= (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1724 ? M32R_FUNCTION_INTERRUPT
1725 : M32R_FUNCTION_NORMAL
);
1730 \f/* Function prologue/epilogue handlers. */
1732 /* M32R stack frames look like:
1734 Before call After call
1735 +-----------------------+ +-----------------------+
1737 high | local variables, | | local variables, |
1738 mem | reg save area, etc. | | reg save area, etc. |
1740 +-----------------------+ +-----------------------+
1742 | arguments on stack. | | arguments on stack. |
1744 SP+0->+-----------------------+ +-----------------------+
1745 | reg parm save area, |
1746 | only created for |
1747 | variable argument |
1749 +-----------------------+
1750 | previous frame ptr |
1751 +-----------------------+
1753 | register save area |
1755 +-----------------------+
1757 +-----------------------+
1761 +-----------------------+
1763 | alloca allocations |
1765 +-----------------------+
1767 low | arguments on stack |
1769 SP+0->+-----------------------+
1772 1) The "reg parm save area" does not exist for non variable argument fns.
1773 2) The "reg parm save area" can be eliminated completely if we saved regs
1774 containing anonymous args separately but that complicates things too
1775 much (so it's not done).
1776 3) The return address is saved after the register save area so as to have as
1777 many insns as possible between the restoration of `lr' and the `jmp lr'.
1780 /* Structure to be filled in by m32r_compute_frame_size with register
1781 save masks, and offsets for the current function. */
1782 struct m32r_frame_info
1784 unsigned int total_size
; /* # bytes that the entire frame takes up */
1785 unsigned int extra_size
; /* # bytes of extra stuff */
1786 unsigned int pretend_size
; /* # bytes we push and pretend caller did */
1787 unsigned int args_size
; /* # bytes that outgoing arguments take up */
1788 unsigned int reg_size
; /* # bytes needed to store regs */
1789 unsigned int var_size
; /* # bytes that variables take up */
1790 unsigned int gmask
; /* mask of saved gp registers */
1791 unsigned int save_fp
; /* nonzero if fp must be saved */
1792 unsigned int save_lr
; /* nonzero if lr (return addr) must be saved */
1793 int initialized
; /* nonzero if frame size already calculated */
1796 /* Current frame information calculated by m32r_compute_frame_size. */
1797 static struct m32r_frame_info current_frame_info
;
1799 /* Zero structure to initialize current_frame_info. */
1800 static struct m32r_frame_info zero_frame_info
;
1802 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1803 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1805 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1806 The return address and frame pointer are treated separately.
1807 Don't consider them here. */
1808 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1809 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1810 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1812 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1813 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || profile_flag)
1815 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1816 #define LONG_INSN_SIZE 4 /* size of long instructions */
1818 /* Return the bytes needed to compute the frame pointer from the current
1821 SIZE is the size needed for local variables. */
1824 m32r_compute_frame_size (size
)
1825 int size
; /* # of var. bytes allocated. */
1828 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1829 unsigned int reg_size
, frame_size
;
1831 enum m32r_function_type fn_type
;
1834 var_size
= M32R_STACK_ALIGN (size
);
1835 args_size
= M32R_STACK_ALIGN (current_function_outgoing_args_size
);
1836 pretend_size
= current_function_pretend_args_size
;
1837 extra_size
= FIRST_PARM_OFFSET (0);
1838 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1842 /* See if this is an interrupt handler. Call used registers must be saved
1844 fn_type
= m32r_compute_function_type (current_function_decl
);
1845 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1847 /* Calculate space needed for registers. */
1849 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1851 if (MUST_SAVE_REGISTER (regno
, interrupt_p
))
1853 reg_size
+= UNITS_PER_WORD
;
1854 gmask
|= 1 << regno
;
1858 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1859 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
;
1861 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1863 total_size
+= reg_size
;
1865 /* ??? Not sure this is necessary, and I don't think the epilogue
1866 handler will do the right thing if this changes total_size. */
1867 total_size
= M32R_STACK_ALIGN (total_size
);
1869 frame_size
= total_size
- (pretend_size
+ reg_size
);
1871 /* Save computed information. */
1872 current_frame_info
.total_size
= total_size
;
1873 current_frame_info
.extra_size
= extra_size
;
1874 current_frame_info
.pretend_size
= pretend_size
;
1875 current_frame_info
.var_size
= var_size
;
1876 current_frame_info
.args_size
= args_size
;
1877 current_frame_info
.reg_size
= reg_size
;
1878 current_frame_info
.gmask
= gmask
;
1879 current_frame_info
.initialized
= reload_completed
;
1881 /* Ok, we're done. */
1885 /* When the `length' insn attribute is used, this macro specifies the
1886 value to be assigned to the address of the first insn in a
1887 function. If not specified, 0 is used. */
1890 m32r_first_insn_address ()
1892 if (! current_frame_info
.initialized
)
1893 m32r_compute_frame_size (get_frame_size ());
1898 /* Expand the m32r prologue as a series of insns. */
1901 m32r_expand_prologue ()
1907 if (! current_frame_info
.initialized
)
1908 m32r_compute_frame_size (get_frame_size ());
1910 gmask
= current_frame_info
.gmask
;
1912 /* These cases shouldn't happen. Catch them now. */
1913 if (current_frame_info
.total_size
== 0 && gmask
)
1916 /* Allocate space for register arguments if this is a variadic function. */
1917 if (current_frame_info
.pretend_size
!= 0)
1919 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1920 the wrong result on a 64-bit host. */
1921 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1922 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1924 GEN_INT (-pretend_size
)));
1927 /* Save any registers we need to and set up fp. */
1929 if (current_frame_info
.save_fp
)
1930 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1932 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1934 /* Save any needed call-saved regs (and call-used if this is an
1935 interrupt handler). */
1936 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1938 if ((gmask
& (1 << regno
)) != 0)
1939 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1940 gen_rtx_REG (Pmode
, regno
)));
1943 if (current_frame_info
.save_lr
)
1944 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1945 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1947 /* Allocate the stack frame. */
1948 frame_size
= (current_frame_info
.total_size
1949 - (current_frame_info
.pretend_size
1950 + current_frame_info
.reg_size
));
1952 if (frame_size
== 0)
1953 ; /* nothing to do */
1954 else if (frame_size
<= 32768)
1955 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1956 GEN_INT (-frame_size
)));
1959 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1960 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1961 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1964 if (frame_pointer_needed
)
1965 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1967 if (profile_flag
|| profile_block_flag
)
1968 emit_insn (gen_blockage ());
1972 /* Set up the stack and frame pointer (if desired) for the function.
1973 Note, if this is changed, you need to mirror the changes in
1974 m32r_compute_frame_size which calculates the prolog size. */
1977 m32r_output_function_prologue (file
, size
)
1981 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1983 /* If this is an interrupt handler, mark it as such. */
1984 if (M32R_INTERRUPT_P (fn_type
))
1986 fprintf (file
, "\t%s interrupt handler\n",
1990 if (! current_frame_info
.initialized
)
1991 m32r_compute_frame_size (size
);
1993 /* This is only for the human reader. */
1995 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1997 current_frame_info
.var_size
,
1998 current_frame_info
.reg_size
/ 4,
1999 current_frame_info
.args_size
,
2000 current_frame_info
.extra_size
);
2003 /* Do any necessary cleanup after a function to restore stack, frame,
2007 m32r_output_function_epilogue (file
, size
)
2009 int size ATTRIBUTE_UNUSED
;
2012 int noepilogue
= FALSE
;
2014 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
2016 /* This is only for the human reader. */
2017 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
2019 if (!current_frame_info
.initialized
)
2021 total_size
= current_frame_info
.total_size
;
2023 if (total_size
== 0)
2025 rtx insn
= get_last_insn ();
2027 /* If the last insn was a BARRIER, we don't have to write any code
2028 because a jump (aka return) was put there. */
2029 if (GET_CODE (insn
) == NOTE
)
2030 insn
= prev_nonnote_insn (insn
);
2031 if (insn
&& GET_CODE (insn
) == BARRIER
)
2037 unsigned int var_size
= current_frame_info
.var_size
;
2038 unsigned int args_size
= current_frame_info
.args_size
;
2039 unsigned int gmask
= current_frame_info
.gmask
;
2040 int can_trust_sp_p
= !current_function_calls_alloca
;
2041 const char * sp_str
= reg_names
[STACK_POINTER_REGNUM
];
2042 const char * fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
2044 /* The first thing to do is point the sp at the bottom of the register
2048 unsigned int reg_offset
= var_size
+ args_size
;
2049 if (reg_offset
== 0)
2050 ; /* nothing to do */
2051 else if (reg_offset
< 128)
2052 fprintf (file
, "\taddi %s,%s%d\n",
2053 sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2054 else if (reg_offset
< 32768)
2055 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
2056 sp_str
, sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2058 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2059 reg_names
[PROLOGUE_TMP_REGNUM
],
2060 IMMEDIATE_PREFIX
, reg_offset
,
2061 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
2063 else if (frame_pointer_needed
)
2065 unsigned int reg_offset
= var_size
+ args_size
;
2066 if (reg_offset
== 0)
2067 fprintf (file
, "\tmv %s,%s\n", sp_str
, fp_str
);
2068 else if (reg_offset
< 32768)
2069 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
2070 sp_str
, fp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2072 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2073 reg_names
[PROLOGUE_TMP_REGNUM
],
2074 IMMEDIATE_PREFIX
, reg_offset
,
2075 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
2080 if (current_frame_info
.save_lr
)
2081 fprintf (file
, "\tpop %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
2083 /* Restore any saved registers, in reverse order of course. */
2084 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
2085 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
2087 if ((gmask
& (1L << regno
)) != 0)
2088 fprintf (file
, "\tpop %s\n", reg_names
[regno
]);
2091 if (current_frame_info
.save_fp
)
2092 fprintf (file
, "\tpop %s\n", fp_str
);
2094 /* Remove varargs area if present. */
2095 if (current_frame_info
.pretend_size
!= 0)
2096 fprintf (file
, "\taddi %s,%s%d\n",
2097 sp_str
, IMMEDIATE_PREFIX
, current_frame_info
.pretend_size
);
2099 /* Emit the return instruction. */
2100 if (M32R_INTERRUPT_P (fn_type
))
2101 fprintf (file
, "\trte\n");
2103 fprintf (file
, "\tjmp %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
2106 #if 0 /* no longer needed */
2107 /* Ensure the function cleanly ends on a 32 bit boundary. */
2108 fprintf (file
, "\t.fillinsn\n");
2111 /* Reset state info for each function. */
2112 current_frame_info
= zero_frame_info
;
2113 m32r_compute_function_type (NULL_TREE
);
2116 /* Return non-zero if this function is known to have a null or 1 instruction
2122 if (!reload_completed
)
2125 if (! current_frame_info
.initialized
)
2126 m32r_compute_frame_size (get_frame_size ());
2128 return current_frame_info
.total_size
== 0;
2134 /* Emit special PIC prologues and epilogues. */
2137 m32r_finalize_pic ()
2142 /* Nested function support. */
2144 /* Emit RTL insns to initialize the variable parts of a trampoline.
2145 FNADDR is an RTX for the address of the function's pure code.
2146 CXT is an RTX for the static chain value for the function. */
2149 m32r_initialize_trampoline (tramp
, fnaddr
, cxt
)
2150 rtx tramp ATTRIBUTE_UNUSED
;
2151 rtx fnaddr ATTRIBUTE_UNUSED
;
2152 rtx cxt ATTRIBUTE_UNUSED
;
2156 /* Set the cpu type and print out other fancy things,
2157 at the top of the file. */
2160 m32r_asm_file_start (file
)
2163 if (flag_verbose_asm
)
2164 fprintf (file
, "%s M32R/D special options: -G %d\n",
2165 ASM_COMMENT_START
, g_switch_value
);
2168 /* Print operand X (an rtx) in assembler syntax to file FILE.
2169 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2170 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2173 m32r_print_operand (file
, x
, code
)
2182 /* The 's' and 'p' codes are used by output_block_move() to
2183 indicate post-increment 's'tores and 'p're-increment loads. */
2185 if (GET_CODE (x
) == REG
)
2186 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2188 output_operand_lossage ("invalid operand to %s code");
2192 if (GET_CODE (x
) == REG
)
2193 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2195 output_operand_lossage ("invalid operand to %p code");
2199 /* Write second word of DImode or DFmode reference,
2200 register or memory. */
2201 if (GET_CODE (x
) == REG
)
2202 fputs (reg_names
[REGNO (x
)+1], file
);
2203 else if (GET_CODE (x
) == MEM
)
2205 fprintf (file
, "@(");
2206 /* Handle possible auto-increment. Since it is pre-increment and
2207 we have already done it, we can just use an offset of four. */
2208 /* ??? This is taken from rs6000.c I think. I don't think it is
2209 currently necessary, but keep it around. */
2210 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2211 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2212 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
2214 output_address (plus_constant (XEXP (x
, 0), 4));
2218 output_operand_lossage ("invalid operand to %R code");
2221 case 'H' : /* High word */
2222 case 'L' : /* Low word */
2223 if (GET_CODE (x
) == REG
)
2225 /* L = least significant word, H = most significant word */
2226 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2227 fputs (reg_names
[REGNO (x
)], file
);
2229 fputs (reg_names
[REGNO (x
)+1], file
);
2231 else if (GET_CODE (x
) == CONST_INT
2232 || GET_CODE (x
) == CONST_DOUBLE
)
2236 split_double (x
, &first
, &second
);
2237 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2238 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2241 output_operand_lossage ("invalid operand to %H/%L code");
2249 if (GET_CODE (x
) != CONST_DOUBLE
2250 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2251 fatal_insn ("Bad insn for 'A'", x
);
2252 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2253 REAL_VALUE_TO_DECIMAL (d
, "%.20e", str
);
2254 fprintf (file
, "%s", str
);
2258 case 'B' : /* Bottom half */
2259 case 'T' : /* Top half */
2260 /* Output the argument to a `seth' insn (sets the Top half-word).
2261 For constants output arguments to a seth/or3 pair to set Top and
2262 Bottom halves. For symbols output arguments to a seth/add3 pair to
2263 set Top and Bottom halves. The difference exists because for
2264 constants seth/or3 is more readable but for symbols we need to use
2265 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2266 switch (GET_CODE (x
))
2273 split_double (x
, &first
, &second
);
2274 x
= WORDS_BIG_ENDIAN
? second
: first
;
2276 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2282 ? INTVAL (x
) & 0xffff
2283 : (INTVAL (x
) >> 16) & 0xffff));
2289 && small_data_operand (x
, VOIDmode
))
2291 fputs ("sda(", file
);
2292 output_addr_const (file
, x
);
2298 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2299 output_addr_const (file
, x
);
2303 output_operand_lossage ("invalid operand to %T/%B code");
2310 /* Output a load/store with update indicator if appropriate. */
2311 if (GET_CODE (x
) == MEM
)
2313 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2314 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2318 output_operand_lossage ("invalid operand to %U code");
2322 /* Print a constant value negated. */
2323 if (GET_CODE (x
) == CONST_INT
)
2324 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2326 output_operand_lossage ("invalid operand to %N code");
2330 /* Print a const_int in hex. Used in comments. */
2331 if (GET_CODE (x
) == CONST_INT
)
2333 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2342 fputs (IMMEDIATE_PREFIX
, file
);
2345 #if 0 /* ??? no longer used */
2347 fputs (reg_names
[SDA_REGNUM
], file
);
2352 /* Do nothing special. */
2357 output_operand_lossage ("invalid operand output code");
2360 switch (GET_CODE (x
))
2363 fputs (reg_names
[REGNO (x
)], file
);
2368 if (GET_CODE (addr
) == PRE_INC
)
2370 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2371 fatal_insn ("Pre-increment address is not a register", x
);
2373 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2375 else if (GET_CODE (addr
) == PRE_DEC
)
2377 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2378 fatal_insn ("Pre-decrement address is not a register", x
);
2380 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2382 else if (GET_CODE (addr
) == POST_INC
)
2384 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2385 fatal_insn ("Post-increment address is not a register", x
);
2387 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2392 output_address (XEXP (x
, 0));
2398 /* We handle SFmode constants here as output_addr_const doesn't. */
2399 if (GET_MODE (x
) == SFmode
)
2404 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2405 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2406 fprintf (file
, "0x%08lx", l
);
2410 /* Fall through. Let output_addr_const deal with it. */
2413 output_addr_const (file
, x
);
2418 /* Print a memory address as an operand to reference that memory location. */
2421 m32r_print_operand_address (file
, addr
)
2426 register rtx index
= 0;
2429 switch (GET_CODE (addr
))
2432 fputs (reg_names
[REGNO (addr
)], file
);
2436 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
2437 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2438 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2439 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2441 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2442 if (GET_CODE (base
) == REG
)
2444 /* Print the offset first (if present) to conform to the manual. */
2448 fprintf (file
, "%d,", offset
);
2449 fputs (reg_names
[REGNO (base
)], file
);
2451 /* The chip doesn't support this, but left in for generality. */
2452 else if (GET_CODE (index
) == REG
)
2453 fprintf (file
, "%s,%s",
2454 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2455 /* Not sure this can happen, but leave in for now. */
2456 else if (GET_CODE (index
) == SYMBOL_REF
)
2458 output_addr_const (file
, index
);
2460 fputs (reg_names
[REGNO (base
)], file
);
2463 fatal_insn ("Bad address", addr
);
2465 else if (GET_CODE (base
) == LO_SUM
)
2468 || GET_CODE (XEXP (base
, 0)) != REG
)
2470 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2471 fputs ("sda(", file
);
2473 fputs ("low(", file
);
2474 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
2476 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2479 fatal_insn ("Bad address", addr
);
2483 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2484 fatal_insn ("Lo_sum not of register", addr
);
2485 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2486 fputs ("sda(", file
);
2488 fputs ("low(", file
);
2489 output_addr_const (file
, XEXP (addr
, 1));
2491 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2494 case PRE_INC
: /* Assume SImode */
2495 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2498 case PRE_DEC
: /* Assume SImode */
2499 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2502 case POST_INC
: /* Assume SImode */
2503 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2507 output_addr_const (file
, addr
);
2512 /* Return true if the operands are the constants 0 and 1. */
2514 zero_and_one (operand1
, operand2
)
2519 GET_CODE (operand1
) == CONST_INT
2520 && GET_CODE (operand2
) == CONST_INT
2521 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2522 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2525 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2527 conditional_move_operand (operand
, mode
)
2529 enum machine_mode mode
;
2531 /* Only defined for simple integers so far... */
2532 if (mode
!= SImode
&& mode
!= HImode
&& mode
!= QImode
)
2535 /* At the moment we can hanndle moving registers and loading constants. */
2536 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2538 switch (GET_CODE (operand
))
2544 return INT8_P (INTVAL (operand
));
2548 fprintf (stderr
, "Test for cond move op of type: %s\n",
2549 GET_RTX_NAME (GET_CODE (operand
)));
2555 /* Return true if the code is a test of the carry bit */
2557 carry_compare_operand (op
, mode
)
2559 enum machine_mode mode ATTRIBUTE_UNUSED
;
2563 if (GET_MODE (op
) != CCmode
&& GET_MODE (op
) != VOIDmode
)
2566 if (GET_CODE (op
) != NE
&& GET_CODE (op
) != EQ
)
2570 if (GET_CODE (x
) != REG
|| REGNO (x
) != CARRY_REGNUM
)
2574 if (GET_CODE (x
) != CONST_INT
|| INTVAL (x
) != 0)
2580 /* Generate the correct assembler code to handle the conditional loading of a
2581 value into a register. It is known that the operands satisfy the
2582 conditional_move_operand() function above. The destination is operand[0].
2583 The condition is operand [1]. The 'true' value is operand [2] and the
2584 'false' value is operand [3]. */
2586 emit_cond_move (operands
, insn
)
2588 rtx insn ATTRIBUTE_UNUSED
;
2590 static char buffer
[100];
2591 const char * dest
= reg_names
[REGNO (operands
[0])];
2595 /* Destination must be a register. */
2596 if (GET_CODE (operands
[0]) != REG
)
2598 if (! conditional_move_operand (operands
[2], SImode
))
2600 if (! conditional_move_operand (operands
[3], SImode
))
2603 /* Check to see if the test is reversed. */
2604 if (GET_CODE (operands
[1]) == NE
)
2606 rtx tmp
= operands
[2];
2607 operands
[2] = operands
[3];
2611 sprintf (buffer
, "mvfc %s, cbr", dest
);
2613 /* If the true value was '0' then we need to invert the results of the move. */
2614 if (INTVAL (operands
[2]) == 0)
2615 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2621 /* Returns true if the registers contained in the two
2622 rtl expressions are different. */
2624 m32r_not_same_reg (a
, b
)
2631 while (GET_CODE (a
) == SUBREG
)
2634 if (GET_CODE (a
) == REG
)
2637 while (GET_CODE (b
) == SUBREG
)
2640 if (GET_CODE (b
) == REG
)
2643 return reg_a
!= reg_b
;
2647 /* Use a library function to move some bytes. */
2649 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2654 /* We want to pass the size as Pmode, which will normally be SImode
2655 but will be DImode if we are using 64 bit longs and pointers. */
2656 if (GET_MODE (bytes_rtx
) != VOIDmode
2657 && GET_MODE (bytes_rtx
) != Pmode
)
2658 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2660 #ifdef TARGET_MEM_FUNCTIONS
2661 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2662 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2663 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2664 TREE_UNSIGNED (sizetype
)),
2665 TYPE_MODE (sizetype
));
2667 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2668 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
2669 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
2670 TREE_UNSIGNED (integer_type_node
)),
2671 TYPE_MODE (integer_type_node
));
2675 /* The maximum number of bytes to copy using pairs of load/store instructions.
2676 If a block is larger than this then a loop will be generated to copy
2677 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2678 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2679 string copy in it. */
2680 #define MAX_MOVE_BYTES 32
2682 /* Expand string/block move operations.
2684 operands[0] is the pointer to the destination.
2685 operands[1] is the pointer to the source.
2686 operands[2] is the number of bytes to move.
2687 operands[3] is the alignment. */
2690 m32r_expand_block_move (operands
)
2693 rtx orig_dst
= operands
[0];
2694 rtx orig_src
= operands
[1];
2695 rtx bytes_rtx
= operands
[2];
2696 rtx align_rtx
= operands
[3];
2697 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
2698 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2699 int align
= INTVAL (align_rtx
);
2704 if (constp
&& bytes
<= 0)
2707 /* Move the address into scratch registers. */
2708 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2709 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2711 if (align
> UNITS_PER_WORD
)
2712 align
= UNITS_PER_WORD
;
2714 /* If we prefer size over speed, always use a function call.
2715 If we do not know the size, use a function call.
2716 If the blocks are not word aligned, use a function call. */
2717 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2719 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2723 leftover
= bytes
% MAX_MOVE_BYTES
;
2726 /* If necessary, generate a loop to handle the bulk of the copy. */
2731 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2732 rtx rounded_total
= GEN_INT (bytes
);
2734 /* If we are going to have to perform this loop more than
2735 once, then generate a label and compute the address the
2736 source register will contain upon completion of the final
2738 if (bytes
> MAX_MOVE_BYTES
)
2740 final_src
= gen_reg_rtx (Pmode
);
2743 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2746 emit_insn (gen_movsi (final_src
, rounded_total
));
2747 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2750 label
= gen_label_rtx ();
2754 /* It is known that output_block_move() will update src_reg to point
2755 to the word after the end of the source block, and dst_reg to point
2756 to the last word of the destination block, provided that the block
2757 is MAX_MOVE_BYTES long. */
2758 emit_insn (gen_movstrsi_internal (dst_reg
, src_reg
, at_a_time
));
2759 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2761 if (bytes
> MAX_MOVE_BYTES
)
2763 emit_insn (gen_cmpsi (src_reg
, final_src
));
2764 emit_jump_insn (gen_bne (label
));
2769 emit_insn (gen_movstrsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
)));
2773 /* Emit load/stores for a small constant word aligned block_move.
2775 operands[0] is the memory address of the destination.
2776 operands[1] is the memory address of the source.
2777 operands[2] is the number of bytes to move.
2778 operands[3] is a temp register.
2779 operands[4] is a temp register. */
2782 m32r_output_block_move (insn
, operands
)
2783 rtx insn ATTRIBUTE_UNUSED
;
2786 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2790 if (bytes
< 1 || bytes
> MAX_MOVE_BYTES
)
2793 /* We do not have a post-increment store available, so the first set of
2794 stores are done without any increment, then the remaining ones can use
2795 the pre-increment addressing mode.
2797 Note: expand_block_move() also relies upon this behaviour when building
2798 loops to copy large blocks. */
2807 output_asm_insn ("ld\t%3, %p1", operands
);
2808 output_asm_insn ("ld\t%4, %p1", operands
);
2809 output_asm_insn ("st\t%3, @%0", operands
);
2810 output_asm_insn ("st\t%4, %s0", operands
);
2814 output_asm_insn ("ld\t%3, %p1", operands
);
2815 output_asm_insn ("ld\t%4, %p1", operands
);
2816 output_asm_insn ("st\t%3, %s0", operands
);
2817 output_asm_insn ("st\t%4, %s0", operands
);
2822 else if (bytes
>= 4)
2827 output_asm_insn ("ld\t%3, %p1", operands
);
2830 output_asm_insn ("ld\t%4, %p1", operands
);
2833 output_asm_insn ("st\t%3, @%0", operands
);
2835 output_asm_insn ("st\t%3, %s0", operands
);
2841 /* Get the entire next word, even though we do not want all of it.
2842 The saves us from doing several smaller loads, and we assume that
2843 we cannot cause a page fault when at least part of the word is in
2844 valid memory [since we don't get called if things aren't properly
2846 int dst_offset
= first_time
? 0 : 4;
2850 /* If got_extra is true then we have already loaded
2851 the next word as part of loading and storing the previous word. */
2853 output_asm_insn ("ld\t%4, @%1", operands
);
2859 output_asm_insn ("sra3\t%3, %4, #16", operands
);
2860 my_operands
[0] = operands
[3];
2861 my_operands
[1] = GEN_INT (dst_offset
);
2862 my_operands
[2] = operands
[0];
2863 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2865 /* If there is a byte left to store then increment the
2866 destination address and shift the contents of the source
2867 register down by 8 bits. We could not do the address
2868 increment in the store half word instruction, because it does
2869 not have an auto increment mode. */
2870 if (bytes
> 0) /* assert (bytes == 1) */
2881 my_operands
[0] = operands
[4];
2882 my_operands
[1] = GEN_INT (last_shift
);
2883 output_asm_insn ("srai\t%0, #%1", my_operands
);
2884 my_operands
[0] = operands
[4];
2885 my_operands
[1] = GEN_INT (dst_offset
);
2886 my_operands
[2] = operands
[0];
2887 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2899 /* Return true if op is an integer constant, less than or equal to
2902 m32r_block_immediate_operand (op
, mode
)
2904 enum machine_mode mode ATTRIBUTE_UNUSED
;
2906 if (GET_CODE (op
) != CONST_INT
2907 || INTVAL (op
) > MAX_MOVE_BYTES
2908 || INTVAL (op
) <= 0)