1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
37 /* Save the operands last given to a compare for use when we
38 generate a scc or bcc insn. */
39 rtx m32r_compare_op0
, m32r_compare_op1
;
41 /* Array of valid operand punctuation characters. */
42 char m32r_punct_chars
[256];
44 /* Selected code model. */
45 char *m32r_model_string
= M32R_MODEL_DEFAULT
;
46 enum m32r_model m32r_model
;
48 /* Selected SDA support. */
49 char *m32r_sdata_string
= M32R_SDATA_DEFAULT
;
50 enum m32r_sdata m32r_sdata
;
53 /* Forward declaration. */
54 static void init_reg_tables
PROTO((void));
56 /* Called by OVERRIDE_OPTIONS to initialize various things. */
63 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
64 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
65 m32r_punct_chars
['#'] = 1;
66 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
68 /* Provide default value if not specified. */
70 g_switch_value
= SDATA_DEFAULT_SIZE
;
72 if (strcmp (m32r_model_string
, "small") == 0)
73 m32r_model
= M32R_MODEL_SMALL
;
74 else if (strcmp (m32r_model_string
, "medium") == 0)
75 m32r_model
= M32R_MODEL_MEDIUM
;
76 else if (strcmp (m32r_model_string
, "large") == 0)
77 m32r_model
= M32R_MODEL_LARGE
;
79 error ("bad value (%s) for -mmodel switch", m32r_model_string
);
81 if (strcmp (m32r_sdata_string
, "none") == 0)
82 m32r_sdata
= M32R_SDATA_NONE
;
83 else if (strcmp (m32r_sdata_string
, "sdata") == 0)
84 m32r_sdata
= M32R_SDATA_SDATA
;
85 else if (strcmp (m32r_sdata_string
, "use") == 0)
86 m32r_sdata
= M32R_SDATA_USE
;
88 error ("bad value (%s) for -msdata switch", m32r_sdata_string
);
92 /* Vectors to keep interesting information about registers where it can easily
93 be got. We use to use the actual mode value as the bit number, but there
94 is (or may be) more than 32 modes now. Instead we use two tables: one
95 indexed by hard register number, and one indexed by mode. */
97 /* The purpose of m32r_mode_class is to shrink the range of modes so that
98 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
99 mapped into one m32r_mode_class mode. */
104 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
105 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
108 /* Modes for condition codes. */
109 #define C_MODES (1 << (int) C_MODE)
111 /* Modes for single-word and smaller quantities. */
112 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
114 /* Modes for double-word and smaller quantities. */
115 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
117 /* Modes for quad-word and smaller quantities. */
118 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
121 /* Value is 1 if register/mode pair is acceptable on arc. */
123 unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
125 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
126 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
130 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
132 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
139 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
141 switch (GET_MODE_CLASS (i
))
144 case MODE_PARTIAL_INT
:
145 case MODE_COMPLEX_INT
:
146 if (GET_MODE_SIZE (i
) <= 4)
147 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
148 else if (GET_MODE_SIZE (i
) == 8)
149 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
150 else if (GET_MODE_SIZE (i
) == 16)
151 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
152 else if (GET_MODE_SIZE (i
) == 32)
153 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
155 m32r_mode_class
[i
] = 0;
158 case MODE_COMPLEX_FLOAT
:
159 if (GET_MODE_SIZE (i
) <= 4)
160 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
161 else if (GET_MODE_SIZE (i
) == 8)
162 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
163 else if (GET_MODE_SIZE (i
) == 16)
164 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
165 else if (GET_MODE_SIZE (i
) == 32)
166 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
168 m32r_mode_class
[i
] = 0;
172 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
173 we must explicitly check for them here. */
174 if (i
== (int) CCmode
)
175 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
177 m32r_mode_class
[i
] = 0;
182 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
185 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
186 else if (i
== ARG_POINTER_REGNUM
)
187 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
189 m32r_regno_reg_class
[i
] = NO_REGS
;
193 /* M32R specific attribute support.
195 interrupt - for interrupt functions
197 model - select code model used to access object
199 small: addresses use 24 bits, use bl to make calls
200 medium: addresses use 32 bits, use bl to make calls
201 large: addresses use 32 bits, use seth/add3/jl to make calls
203 Grep for MODEL in m32r.h for more info.
206 /* Return nonzero if IDENTIFIER is a valid decl attribute. */
209 m32r_valid_machine_decl_attribute (type
, attributes
, identifier
, args
)
215 static tree interrupt_ident
, model_ident
;
216 static tree small_ident
, medium_ident
, large_ident
;
218 if (interrupt_ident
== 0)
220 interrupt_ident
= get_identifier ("__interrupt__");
221 model_ident
= get_identifier ("__model__");
222 small_ident
= get_identifier ("__small__");
223 medium_ident
= get_identifier ("__medium__");
224 large_ident
= get_identifier ("__large__");
227 if (identifier
== interrupt_ident
228 && list_length (args
) == 0)
231 if (identifier
== model_ident
232 && list_length (args
) == 1
233 && (TREE_VALUE (args
) == small_ident
234 || TREE_VALUE (args
) == medium_ident
235 || TREE_VALUE (args
) == large_ident
))
241 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
242 and two if they are nearly compatible (which causes a warning to be
246 m32r_comp_type_attributes (type1
, type2
)
252 /* Set the default attributes for TYPE. */
255 m32r_set_default_type_attributes (type
)
260 /* A C statement or statements to switch to the appropriate
261 section for output of DECL. DECL is either a `VAR_DECL' node
262 or a constant of some sort. RELOC indicates whether forming
263 the initial value of DECL requires link-time relocations. */
266 m32r_select_section (decl
, reloc
)
270 if (TREE_CODE (decl
) == STRING_CST
)
272 if (! flag_writable_strings
)
277 else if (TREE_CODE (decl
) == VAR_DECL
)
279 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl
), 0), 0)))
281 else if ((flag_pic
&& reloc
)
282 || !TREE_READONLY (decl
)
283 || TREE_SIDE_EFFECTS (decl
)
284 || !DECL_INITIAL (decl
)
285 || (DECL_INITIAL (decl
) != error_mark_node
286 && !TREE_CONSTANT (DECL_INITIAL (decl
))))
295 /* Encode section information of DECL, which is either a VAR_DECL,
296 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
298 For the M32R we want to record:
300 - whether the object lives in .sdata/.sbss.
301 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
303 - what code model should be used to access the object
304 small: recorded with no flag - for space efficiency since they'll
306 medium: prefixed with MEDIUM_FLAG_CHAR
307 large: prefixed with LARGE_FLAG_CHAR
311 m32r_encode_section_info (decl
)
317 switch (TREE_CODE (decl
))
321 model
= lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl
));
325 /* ??? document all others that can appear here */
330 /* Only mark the object as being small data area addressable if
331 it hasn't been explicitly marked with a code model.
333 The user can explicitly put an object in the small data area with the
334 section attribute. If the object is in sdata/sbss and marked with a
335 code model do both [put the object in .sdata and mark it as being
336 addressed with a specific code model - don't mark it as being addressed
337 with an SDA reloc though]. This is ok and might be useful at times. If
338 the object doesn't fit the linker will give an error. */
342 if (TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd'
343 && DECL_SECTION_NAME (decl
) != NULL_TREE
)
345 char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
346 if (! strcmp (name
, ".sdata") || ! strcmp (name
, ".sbss"))
348 #if 0 /* ??? There's no reason to disallow this, is there? */
349 if (TREE_READONLY (decl
))
350 error_with_decl (decl
, "const objects cannot go in .sdata/.sbss");
352 prefix
= SDATA_FLAG_CHAR
;
357 if (TREE_CODE (decl
) == VAR_DECL
358 && ! TREE_READONLY (decl
)
359 && ! TARGET_SDATA_NONE
)
361 int size
= int_size_in_bytes (TREE_TYPE (decl
));
363 if (size
> 0 && size
<= g_switch_value
)
364 prefix
= SDATA_FLAG_CHAR
;
369 /* If data area not decided yet, check for a code model. */
374 if (TREE_VALUE (TREE_VALUE (model
)) == get_identifier ("__small__"))
375 ; /* don't mark the symbol specially */
376 else if (TREE_VALUE (TREE_VALUE (model
)) == get_identifier ("__medium__"))
377 prefix
= MEDIUM_FLAG_CHAR
;
378 else if (TREE_VALUE (TREE_VALUE (model
)) == get_identifier ("__large__"))
379 prefix
= LARGE_FLAG_CHAR
;
381 abort (); /* shouldn't happen */
385 if (TARGET_MODEL_SMALL
)
386 ; /* don't mark the symbol specially */
387 else if (TARGET_MODEL_MEDIUM
)
388 prefix
= MEDIUM_FLAG_CHAR
;
389 else if (TARGET_MODEL_LARGE
)
390 prefix
= LARGE_FLAG_CHAR
;
392 abort (); /* shouldn't happen */
398 rtx rtl
= (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
399 ? TREE_CST_RTL (decl
) : DECL_RTL (decl
));
400 char *str
= XSTR (XEXP (rtl
, 0), 0);
401 int len
= strlen (str
);
402 char *newstr
= savealloc (len
+ 2);
403 strcpy (newstr
+ 1, str
);
405 XSTR (XEXP (rtl
, 0), 0) = newstr
;
409 /* Do anything needed before RTL is emitted for each function. */
412 m32r_init_expanders ()
414 /* ??? At one point there was code here. The function is left in
415 to make it easy to experiment. */
418 /* Acceptable arguments to the call insn. */
421 call_address_operand (op
, int_mode
)
425 return symbolic_operand (op
, int_mode
);
427 /* Constants and values in registers are not OK, because
428 the m32r BL instruction can only support PC relative branching. */
432 call_operand (op
, int_mode
)
436 enum machine_mode mode
= (enum machine_mode
)int_mode
;
438 if (GET_CODE (op
) != MEM
)
441 return call_address_operand (op
, mode
);
444 /* Returns 1 if OP is a symbol reference. */
447 symbolic_operand (op
, int_mode
)
451 switch (GET_CODE (op
))
463 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
466 small_data_operand (op
, int_mode
)
470 if (! TARGET_SDATA_USE
)
473 if (GET_CODE (op
) == SYMBOL_REF
)
474 return SDATA_NAME_P (XSTR (op
, 0));
476 if (GET_CODE (op
) == CONST
477 && GET_CODE (XEXP (op
, 0)) == PLUS
478 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
479 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
480 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
481 return SDATA_NAME_P (XSTR (XEXP (XEXP (op
, 0), 0), 0));
486 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
489 addr24_operand (op
, int_mode
)
493 if (GET_CODE (op
) == LABEL_REF
)
494 return TARGET_ADDR24
;
496 if (GET_CODE (op
) == SYMBOL_REF
)
497 return (SMALL_NAME_P (XSTR (op
, 0))
499 && (CONSTANT_POOL_ADDRESS_P (op
)
500 || LIT_NAME_P (XSTR (op
, 0)))));
502 if (GET_CODE (op
) == CONST
503 && GET_CODE (XEXP (op
, 0)) == PLUS
504 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
505 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
506 && UINT24_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
508 rtx sym
= XEXP (XEXP (op
, 0), 0);
509 return (SMALL_NAME_P (XSTR (sym
, 0))
511 && (CONSTANT_POOL_ADDRESS_P (op
)
512 || LIT_NAME_P (XSTR (op
, 0)))));
518 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
521 addr32_operand (op
, int_mode
)
525 if (GET_CODE (op
) == LABEL_REF
)
526 return TARGET_ADDR32
;
528 if (GET_CODE (op
) == SYMBOL_REF
)
529 return (! addr24_operand (op
, int_mode
)
530 && ! small_data_operand (op
, int_mode
));
532 if (GET_CODE (op
) == CONST
533 && GET_CODE (XEXP (op
, 0)) == PLUS
534 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
535 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
537 return (! addr24_operand (op
, int_mode
)
538 && ! small_data_operand (op
, int_mode
));
544 /* Return 1 if OP is a function that can be called with the `bl' insn. */
547 call26_operand (op
, int_mode
)
551 if (GET_CODE (op
) == SYMBOL_REF
)
552 return ! LARGE_NAME_P (XSTR (op
, 0));
554 return TARGET_CALL26
;
557 /* Returns 1 if OP is an acceptable operand for seth/add3. */
560 seth_add3_operand (op
, int_mode
)
564 if (GET_CODE (op
) == SYMBOL_REF
565 || GET_CODE (op
) == LABEL_REF
)
568 if (GET_CODE (op
) == CONST
569 && GET_CODE (XEXP (op
, 0)) == PLUS
570 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
571 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
572 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
578 /* Return true if OP is a signed 16 bit immediate value
579 useful in comparisons. */
582 cmp_int16_operand (op
, int_mode
)
586 if (GET_CODE (op
) != CONST_INT
)
588 return CMP_INT16_P (INTVAL (op
));
591 /* Return true if OP is an unsigned 16 bit immediate value. */
594 uint16_operand (op
, int_mode
)
598 if (GET_CODE (op
) != CONST_INT
)
600 return UINT16_P (INTVAL (op
));
603 /* Return true if OP is a register or signed 8 bit value. */
606 reg_or_int16_operand (op
, int_mode
)
610 enum machine_mode mode
= (enum machine_mode
)int_mode
;
612 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
613 return register_operand (op
, mode
);
614 if (GET_CODE (op
) != CONST_INT
)
616 return INT16_P (INTVAL (op
));
619 /* Return true if OP is a register or an unsigned 16 bit value. */
622 reg_or_uint16_operand (op
, int_mode
)
626 enum machine_mode mode
= (enum machine_mode
)int_mode
;
628 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
629 return register_operand (op
, mode
);
630 if (GET_CODE (op
) != CONST_INT
)
632 return UINT16_P (INTVAL (op
));
635 /* Return true if OP is a register or signed 16 bit value for compares. */
638 reg_or_cmp_int16_operand (op
, int_mode
)
642 enum machine_mode mode
= (enum machine_mode
)int_mode
;
644 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
645 return register_operand (op
, mode
);
646 if (GET_CODE (op
) != CONST_INT
)
648 return CMP_INT16_P (INTVAL (op
));
651 /* Return true if OP is a const_int requiring two instructions to load. */
654 two_insn_const_operand (op
, int_mode
)
658 if (GET_CODE (op
) != CONST_INT
)
660 if (INT16_P (INTVAL (op
))
661 || UINT24_P (INTVAL (op
))
662 || UPPER16_P (INTVAL (op
)))
667 /* Return true if OP is an acceptable argument for a single word
671 move_src_operand (op
, int_mode
)
675 enum machine_mode mode
= (enum machine_mode
)int_mode
;
676 switch (GET_CODE (op
))
680 return addr24_operand (op
, int_mode
);
682 /* ??? We allow more cse opportunities if we only allow constants
683 loadable with one insn, and split the rest into two. The instances
684 where this would help should be rare and the current way is
686 return INT32_P (INTVAL (op
));
688 return TARGET_ADDR24
;
692 else if (mode
== SImode
)
694 /* Large unsigned constants are represented as const_double's. */
695 unsigned HOST_WIDE_INT low
, high
;
697 low
= CONST_DOUBLE_LOW (op
);
698 high
= CONST_DOUBLE_HIGH (op
);
699 return high
== 0 && low
<= 0xffffffff;
704 return register_operand (op
, mode
);
706 /* (subreg (mem ...) ...) can occur here if the inner part was once a
707 pseudo-reg and is now a stack slot. */
708 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
709 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
711 return register_operand (op
, mode
);
713 return address_operand (XEXP (op
, 0), mode
);
719 /* Return true if OP is an acceptable argument for a double word
723 move_double_src_operand (op
, int_mode
)
727 enum machine_mode mode
= (enum machine_mode
)int_mode
;
728 switch (GET_CODE (op
))
733 return easy_df_const (op
);
735 return easy_di_const (op
);
737 return register_operand (op
, mode
);
739 /* (subreg (mem ...) ...) can occur here if the inner part was once a
740 pseudo-reg and is now a stack slot. */
741 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
742 return move_double_src_operand (SUBREG_REG (op
), int_mode
);
744 return register_operand (op
, mode
);
746 /* Disallow auto inc/dec for now. */
747 if (GET_CODE (XEXP (op
, 0)) == PRE_DEC
748 || GET_CODE (XEXP (op
, 0)) == PRE_INC
)
750 return address_operand (XEXP (op
, 0), mode
);
756 /* Return true if OP is an acceptable argument for a move destination. */
759 move_dest_operand (op
, int_mode
)
763 enum machine_mode mode
= (enum machine_mode
)int_mode
;
764 switch (GET_CODE (op
))
767 return register_operand (op
, mode
);
769 /* (subreg (mem ...) ...) can occur here if the inner part was once a
770 pseudo-reg and is now a stack slot. */
771 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
772 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
774 return register_operand (op
, mode
);
776 return address_operand (XEXP (op
, 0), mode
);
782 /* Return 1 if OP is a DImode const we want to handle inline.
783 This must match the code in the movdi pattern.
784 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
790 rtx high_rtx
, low_rtx
;
791 HOST_WIDE_INT high
, low
;
793 split_double (op
, &high_rtx
, &low_rtx
);
794 high
= INTVAL (high_rtx
);
795 low
= INTVAL (low_rtx
);
796 /* Pick constants loadable with 2 16 bit `ldi' insns. */
797 if (high
>= -128 && high
<= 127
798 && low
>= -128 && low
<= 127)
803 /* Return 1 if OP is a DFmode const we want to handle inline.
804 This must match the code in the movdf pattern.
805 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
814 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
815 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
816 if (l
[0] == 0 && l
[1] == 0)
818 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
823 /* Return 1 if OP is an EQ or NE comparison operator. */
826 eqne_comparison_operator (op
, int_mode
)
830 enum rtx_code code
= GET_CODE (op
);
832 if (GET_RTX_CLASS (code
) != '<')
834 return (code
== EQ
|| code
== NE
);
837 /* Return 1 if OP is a signed comparison operator. */
840 signed_comparison_operator (op
, int_mode
)
844 enum rtx_code code
= GET_CODE (op
);
846 if (GET_RTX_CLASS (code
) != '<')
848 return (code
== EQ
|| code
== NE
849 || code
== LT
|| code
== LE
|| code
== GT
|| code
== GE
);
852 /* Return 1 if OP is (mem (reg ...)).
853 This is used in insn length calcs. */
856 memreg_operand (op
, int_mode
)
860 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == REG
;
863 /* Return non-zero if the operand is an insn that is a small insn.
864 Allow const_int 0 as well, which is a placeholder for NOP slots. */
867 small_insn_p (op
, int_mode
)
871 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
874 if (GET_RTX_CLASS (GET_CODE (op
)) != 'i')
877 return get_attr_length (op
) == 2;
880 /* Return non-zero if the operand is an insn that is a large insn. */
883 large_insn_p (op
, int_mode
)
887 if (GET_RTX_CLASS (GET_CODE (op
)) != 'i')
890 return get_attr_length (op
) != 2;
896 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
897 return the mode to be used for the comparison. */
900 m32r_select_cc_mode (op
, x
, y
)
907 /* X and Y are two things to compare using CODE. Emit the compare insn and
908 return the rtx for compare [arg0 of the if_then_else].
909 If need_compare is true then the comparison insn must be generated, rather
910 than being susummed into the following branch instruction. */
913 gen_compare (int_code
, x
, y
, need_compare
)
919 enum rtx_code code
= (enum rtx_code
)int_code
;
920 enum rtx_code compare_code
;
921 enum rtx_code branch_code
;
922 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
923 rtx cc_reg
= gen_rtx (REG
, mode
, CARRY_REGNUM
);
928 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
929 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
930 case LT
: compare_code
= LT
; branch_code
= NE
; break;
931 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
932 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
933 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
934 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
935 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
936 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
937 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
942 switch (compare_code
)
945 if (GET_CODE (y
) == CONST_INT
946 && CMP_INT16_P (INTVAL (y
)) /* reg equal to small const. */
949 rtx tmp
= gen_reg_rtx (SImode
);
951 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
955 else if (CONSTANT_P (y
)) /* reg equal to const. */
957 rtx tmp
= force_reg (GET_MODE (x
), y
);
961 if (register_operand (y
, SImode
) /* reg equal to reg. */
962 || y
== const0_rtx
) /* req equal to zero. */
964 emit_insn (gen_cmp_eqsi_insn (x
, y
));
966 return gen_rtx (code
, mode
, cc_reg
, const0_rtx
);
971 if (register_operand (y
, SImode
)
972 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
974 rtx tmp
= gen_reg_rtx (SImode
); /* reg compared to reg. */
979 emit_insn (gen_cmp_ltsi_insn (x
, y
));
986 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
987 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
991 if (GET_CODE (y
) == CONST_INT
)
992 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
994 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
995 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
999 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1006 return gen_rtx (code
, mode
, cc_reg
, const0_rtx
);
1011 if (register_operand (y
, SImode
)
1012 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1014 rtx tmp
= gen_reg_rtx (SImode
); /* reg (unsigned) compared to reg. */
1019 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1023 if (y
== const0_rtx
)
1026 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1027 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1031 if (GET_CODE (y
) == CONST_INT
)
1032 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1034 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1035 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1039 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1046 return gen_rtx (code
, mode
, cc_reg
, const0_rtx
);
1055 if (! TARGET_OLD_COMPARE
)
1057 /* reg/reg equal comparison */
1058 if (compare_code
== EQ
1059 && register_operand (y
, SImode
))
1060 return gen_rtx (code
, mode
, x
, y
);
1062 /* reg/zero signed comparison */
1063 if ((compare_code
== EQ
|| compare_code
== LT
)
1065 return gen_rtx (code
, mode
, x
, y
);
1067 /* reg/smallconst equal comparison */
1068 if (compare_code
== EQ
1069 && GET_CODE (y
) == CONST_INT
1070 && CMP_INT16_P (INTVAL (y
)))
1072 rtx tmp
= gen_reg_rtx (SImode
);
1073 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1074 return gen_rtx (code
, mode
, tmp
, const0_rtx
);
1077 /* reg/const equal comparison */
1078 if (compare_code
== EQ
1081 rtx tmp
= force_reg (GET_MODE (x
), y
);
1082 return gen_rtx (code
, mode
, x
, tmp
);
1089 y
= force_reg (GET_MODE (x
), y
);
1093 (code
== LTU
|| code
== LEU
|| code
== GTU
|| code
== GEU
)
1094 ? uint16_operand (y
, GET_MODE (y
))
1095 : reg_or_cmp_int16_operand (y
, GET_MODE (y
));
1098 y
= force_reg (GET_MODE (x
), y
);
1102 switch (compare_code
)
1105 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1108 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1111 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1115 return gen_rtx (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (mode
));
1118 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1121 function_arg_partial_nregs (cum
, int_mode
, type
, named
)
1122 CUMULATIVE_ARGS
*cum
;
1127 enum machine_mode mode
= (enum machine_mode
)int_mode
;
1129 int size
= (((mode
== BLKmode
&& type
)
1130 ? int_size_in_bytes (type
)
1131 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1133 if (*cum
>= M32R_MAX_PARM_REGS
)
1135 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1136 ret
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1143 /* Do any needed setup for a variadic function. For the M32R, we must
1144 create a register parameter block, and then copy any anonymous arguments
1145 in registers to memory.
1147 CUM has not been updated for the last named argument which has type TYPE
1148 and mode MODE, and we rely on this fact. */
1151 m32r_setup_incoming_varargs (cum
, int_mode
, type
, pretend_size
, no_rtl
)
1152 CUMULATIVE_ARGS
*cum
;
1158 enum machine_mode mode
= (enum machine_mode
)int_mode
;
1164 /* All BLKmode values are passed by reference. */
1165 if (mode
== BLKmode
)
1168 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1169 if (current_function_varargs
)
1170 first_anon_arg
= *cum
;
1172 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1173 + ROUND_ADVANCE_ARG (mode
, type
));
1175 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1177 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1178 int first_reg_offset
= first_anon_arg
;
1179 /* Size in words to "pretend" allocate. */
1180 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1183 regblock
= gen_rtx (MEM
, BLKmode
,
1184 plus_constant (arg_pointer_rtx
,
1185 FIRST_PARM_OFFSET (0)));
1186 move_block_from_reg (first_reg_offset
, regblock
,
1187 size
, size
* UNITS_PER_WORD
);
1189 *pretend_size
= (size
* UNITS_PER_WORD
);
1193 /* Cost functions. */
1195 /* Provide the costs of an addressing mode that contains ADDR.
1196 If ADDR is not a valid address, its cost is irrelevant.
1198 This function is trivial at the moment. This code doesn't live
1199 in m32r.h so it's easy to experiment. */
1202 m32r_address_cost (addr
)
1208 /* Type of function DECL.
1210 The result is cached. To reset the cache at the end of a function,
1211 call with DECL = NULL_TREE. */
1213 enum m32r_function_type
1214 m32r_compute_function_type (decl
)
1218 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1219 /* Last function we were called for. */
1220 static tree last_fn
= NULL_TREE
;
1222 /* Resetting the cached value? */
1223 if (decl
== NULL_TREE
)
1225 fn_type
= M32R_FUNCTION_UNKNOWN
;
1226 last_fn
= NULL_TREE
;
1230 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1233 /* Compute function type. */
1234 fn_type
= (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1235 ? M32R_FUNCTION_INTERRUPT
1236 : M32R_FUNCTION_NORMAL
);
1241 \f/* Function prologue/epilogue handlers. */
1243 /* M32R stack frames look like:
1245 Before call After call
1246 +-----------------------+ +-----------------------+
1248 high | local variables, | | local variables, |
1249 mem | reg save area, etc. | | reg save area, etc. |
1251 +-----------------------+ +-----------------------+
1253 | arguments on stack. | | arguments on stack. |
1255 SP+0->+-----------------------+ +-----------------------+
1256 | reg parm save area, |
1257 | only created for |
1258 | variable argument |
1260 +-----------------------+
1261 | previous frame ptr |
1262 +-----------------------+
1264 | register save area |
1266 +-----------------------+
1268 +-----------------------+
1272 +-----------------------+
1274 | alloca allocations |
1276 +-----------------------+
1278 low | arguments on stack |
1280 SP+0->+-----------------------+
1283 1) The "reg parm save area" does not exist for non variable argument fns.
1284 2) The "reg parm save area" can be eliminated completely if we saved regs
1285 containing anonymous args separately but that complicates things too
1286 much (so it's not done).
1287 3) The return address is saved after the register save area so as to have as
1288 many insns as possible between the restoration of `lr' and the `jmp lr'.
1291 /* Structure to be filled in by m32r_compute_frame_size with register
1292 save masks, and offsets for the current function. */
1293 struct m32r_frame_info
1295 unsigned int total_size
; /* # bytes that the entire frame takes up */
1296 unsigned int extra_size
; /* # bytes of extra stuff */
1297 unsigned int pretend_size
; /* # bytes we push and pretend caller did */
1298 unsigned int args_size
; /* # bytes that outgoing arguments take up */
1299 unsigned int reg_size
; /* # bytes needed to store regs */
1300 unsigned int var_size
; /* # bytes that variables take up */
1301 unsigned int prolog_size
; /* # bytes that the prologue takes up */
1302 unsigned int gmask
; /* mask of saved gp registers */
1303 unsigned int save_fp
; /* nonzero if fp must be saved */
1304 unsigned int save_lr
; /* nonzero if lr (return addr) must be saved */
1305 int initialized
; /* nonzero if frame size already calculated */
1308 /* Current frame information calculated by m32r_compute_frame_size. */
1309 static struct m32r_frame_info current_frame_info
;
1311 /* Zero structure to initialize current_frame_info. */
1312 static struct m32r_frame_info zero_frame_info
;
1314 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1315 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1317 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1318 The return address and frame pointer are treated separately.
1319 Don't consider them here. */
1320 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1321 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1322 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1324 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1325 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM])
1327 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1328 #define LONG_INSN_SIZE 4 /* size of long instructions */
1330 /* Return the bytes needed to compute the frame pointer from the current
1333 SIZE is the size needed for local variables. */
1336 m32r_compute_frame_size (size
)
1337 int size
; /* # of var. bytes allocated. */
1340 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1341 unsigned int reg_size
, prolog_size
, frame_size
;
1343 enum m32r_function_type fn_type
;
1346 var_size
= M32R_STACK_ALIGN (size
);
1347 args_size
= M32R_STACK_ALIGN (current_function_outgoing_args_size
);
1348 pretend_size
= current_function_pretend_args_size
;
1349 extra_size
= FIRST_PARM_OFFSET (0);
1350 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1355 /* See if this is an interrupt handler. Call used registers must be saved
1357 fn_type
= m32r_compute_function_type (current_function_decl
);
1358 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1360 /* Calculate space needed for registers. */
1362 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1364 if (MUST_SAVE_REGISTER (regno
, interrupt_p
))
1366 reg_size
+= UNITS_PER_WORD
;
1367 gmask
|= 1 << regno
;
1371 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1372 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
;
1374 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1376 total_size
+= reg_size
;
1378 /* ??? Not sure this is necessary, and I don't think the epilogue
1379 handler will do the right thing if this changes total_size. */
1380 total_size
= M32R_STACK_ALIGN (total_size
);
1382 /* Calculate prologue size. Obviously any changes to
1383 m32r_output_function_prologue must be mirrored here. */
1385 prolog_size
+= SHORT_INSN_SIZE
; /* addi sp,-pretend_size */
1387 prolog_size
+= SHORT_INSN_SIZE
* (reg_size
/ UNITS_PER_WORD
); /* pushes */
1388 frame_size
= total_size
- (pretend_size
+ reg_size
);
1390 if (frame_size
== 0)
1391 ; /* nothing to do */
1392 else if (frame_size
<= 128)
1393 prolog_size
+= SHORT_INSN_SIZE
; /* addi sp,-<frame> */
1396 if ((prolog_size
% LONG_INSN_SIZE
) != 0)
1397 prolog_size
+= SHORT_INSN_SIZE
; /* nop */
1399 if (frame_size
<= 32768)
1400 prolog_size
+= LONG_INSN_SIZE
; /* add3 sp,sp,-<frame> */
1402 prolog_size
+= (LONG_INSN_SIZE
/* ld24 tmp,<frame>/sub sp,tmp */
1406 if (frame_pointer_needed
)
1407 prolog_size
+= SHORT_INSN_SIZE
; /* mv fp,sp */
1409 /* Save computed information. */
1410 current_frame_info
.total_size
= total_size
;
1411 current_frame_info
.extra_size
= extra_size
;
1412 current_frame_info
.pretend_size
= pretend_size
;
1413 current_frame_info
.var_size
= var_size
;
1414 current_frame_info
.args_size
= args_size
;
1415 current_frame_info
.reg_size
= reg_size
;
1416 current_frame_info
.prolog_size
= prolog_size
;
1417 current_frame_info
.gmask
= gmask
;
1418 current_frame_info
.initialized
= reload_completed
;
1420 /* Ok, we're done. */
1424 /* When the `length' insn attribute is used, this macro specifies the
1425 value to be assigned to the address of the first insn in a
1426 function. If not specified, 0 is used. */
1429 m32r_first_insn_address ()
1431 if (! current_frame_info
.initialized
)
1432 m32r_compute_frame_size (get_frame_size ());
1434 return current_frame_info
.prolog_size
;
1437 /* Set up the stack and frame pointer (if desired) for the function.
1438 Note, if this is changed, you need to mirror the changes in
1439 m32r_compute_frame_size which calculates the prolog size. */
1442 m32r_output_function_prologue (file
, size
)
1447 int total_size
, frame_size
;
1448 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
1449 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
1450 unsigned int gmask
= current_frame_info
.gmask
;
1451 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1453 /* If this is an interrupt handler, mark it as such. */
1454 if (M32R_INTERRUPT_P (fn_type
))
1456 fprintf (file
, "\t%s interrupt handler\n",
1460 total_size
= (! current_frame_info
.initialized
1461 ? m32r_compute_frame_size (size
)
1462 : current_frame_info
.total_size
);
1464 /* This is only for the human reader. */
1466 "\t%s BEGIN PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d, prolog= %d\n",
1468 current_frame_info
.var_size
,
1469 current_frame_info
.reg_size
/ 4,
1470 current_frame_info
.args_size
,
1471 current_frame_info
.extra_size
,
1472 current_frame_info
.prolog_size
);
1474 /* These cases shouldn't happen. Catch them now. */
1475 if (total_size
== 0 && gmask
)
1479 /* Allocate space for register arguments if this is a variadic function. */
1480 if (current_frame_info
.pretend_size
!= 0)
1481 fprintf (file
, "\taddi %s,%s%d\n",
1482 sp_str
, IMMEDIATE_PREFIX
,
1483 -current_frame_info
.pretend_size
);
1485 /* If there are unnamed args in registers, save them. */
1486 if (current_function_stdarg
|| current_function_varargs
)
1489 fprintf (file
, "\taddi %s,%s%d\n",
1490 sp_str
, IMMEDIATE_PREFIX
,
1491 - M32R_MAX_PARM_REGS
* UNITS_PER_WORD
);
1492 for (i
= 0; i
< M32R_MAX_PARM_REGS
; ++i
)
1493 fprintf (file
, "\tst %s,@(sp,%d)\n",
1494 reg_names
[i
], i
* UNITS_PER_WORD
);
1498 /* Save any registers we need to and set up fp. */
1500 if (current_frame_info
.save_fp
)
1501 fprintf (file
, "\tpush %s\n", fp_str
);
1503 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1505 /* Save any needed call-saved regs (and call-used if this is an
1506 interrupt handler). */
1507 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1509 if ((gmask
& (1 << regno
)) != 0)
1510 fprintf (file
, "\tpush %s\n", reg_names
[regno
]);
1513 if (current_frame_info
.save_lr
)
1514 fprintf (file
, "\tpush %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1516 /* Allocate the stack frame. */
1517 frame_size
= total_size
- (current_frame_info
.pretend_size
1518 + current_frame_info
.reg_size
);
1519 if (frame_size
== 0)
1520 ; /* nothing to do */
1521 else if (frame_size
<= 128)
1522 fprintf (file
, "\taddi %s,%s%d\n",
1523 sp_str
, IMMEDIATE_PREFIX
, -frame_size
);
1524 else if (frame_size
<= 32768)
1525 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1526 sp_str
, sp_str
, IMMEDIATE_PREFIX
, -frame_size
);
1528 fprintf (file
, "\tld24 %s,%s%d\n\tsub %s,%s\n",
1529 reg_names
[PROLOGUE_TMP_REGNUM
],
1530 IMMEDIATE_PREFIX
, frame_size
,
1531 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1533 if (frame_pointer_needed
)
1534 fprintf (file
, "\tmv %s,%s\n", fp_str
, sp_str
);
1536 fprintf (file
, "\t%s END PROLOGUE\n", ASM_COMMENT_START
);
1539 /* Do any necessary cleanup after a function to restore stack, frame,
1543 m32r_output_function_epilogue (file
, size
)
1548 int noepilogue
= FALSE
;
1550 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1552 /* This is only for the human reader. */
1553 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
1555 if (!current_frame_info
.initialized
)
1557 total_size
= current_frame_info
.total_size
;
1559 if (total_size
== 0)
1561 rtx insn
= get_last_insn ();
1563 /* If the last insn was a BARRIER, we don't have to write any code
1564 because a jump (aka return) was put there. */
1565 if (GET_CODE (insn
) == NOTE
)
1566 insn
= prev_nonnote_insn (insn
);
1567 if (insn
&& GET_CODE (insn
) == BARRIER
)
1573 unsigned int pretend_size
= current_frame_info
.pretend_size
;
1574 unsigned int frame_size
= total_size
- pretend_size
;
1575 unsigned int var_size
= current_frame_info
.var_size
;
1576 unsigned int args_size
= current_frame_info
.args_size
;
1577 unsigned int gmask
= current_frame_info
.gmask
;
1578 int can_trust_sp_p
= !current_function_calls_alloca
;
1579 char * sp_str
= reg_names
[STACK_POINTER_REGNUM
];
1580 char * fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
1582 /* The first thing to do is point the sp at the bottom of the register
1586 unsigned int reg_offset
= var_size
+ args_size
;
1587 if (reg_offset
== 0)
1588 ; /* nothing to do */
1589 else if (reg_offset
< 128)
1590 fprintf (file
, "\taddi %s,%s%d\n",
1591 sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1592 else if (reg_offset
< 32768)
1593 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1594 sp_str
, sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1596 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1597 reg_names
[PROLOGUE_TMP_REGNUM
],
1598 IMMEDIATE_PREFIX
, reg_offset
,
1599 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1601 else if (frame_pointer_needed
)
1603 unsigned int reg_offset
= var_size
+ args_size
;
1604 if (reg_offset
== 0)
1605 fprintf (file
, "\tmv %s,%s\n", sp_str
, fp_str
);
1606 else if (reg_offset
< 32768)
1607 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1608 sp_str
, fp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1610 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1611 reg_names
[PROLOGUE_TMP_REGNUM
],
1612 IMMEDIATE_PREFIX
, reg_offset
,
1613 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1618 if (current_frame_info
.save_lr
)
1619 fprintf (file
, "\tpop %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1621 /* Restore any saved registers, in reverse order of course. */
1622 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1623 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1625 if ((gmask
& (1L << regno
)) != 0)
1626 fprintf (file
, "\tpop %s\n", reg_names
[regno
]);
1629 if (current_frame_info
.save_fp
)
1630 fprintf (file
, "\tpop %s\n", fp_str
);
1632 /* Remove varargs area if present. */
1633 if (current_frame_info
.pretend_size
!= 0)
1634 fprintf (file
, "\taddi %s,%s%d\n",
1635 sp_str
, IMMEDIATE_PREFIX
, current_frame_info
.pretend_size
);
1637 /* Emit the return instruction. */
1638 if (M32R_INTERRUPT_P (fn_type
))
1639 fprintf (file
, "\trte\n");
1641 fprintf (file
, "\tjmp %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1644 #if 0 /* no longer needed */
1645 /* Ensure the function cleanly ends on a 32 bit boundary. */
1646 fprintf (file
, "\t.fillinsn\n");
1649 /* Reset state info for each function. */
1650 current_frame_info
= zero_frame_info
;
1651 m32r_compute_function_type (NULL_TREE
);
1656 /* Emit special PIC prologues and epilogues. */
1659 m32r_finalize_pic ()
1664 /* Nested function support. */
1666 /* Emit RTL insns to initialize the variable parts of a trampoline.
1667 FNADDR is an RTX for the address of the function's pure code.
1668 CXT is an RTX for the static chain value for the function. */
1671 m32r_initialize_trampoline (tramp
, fnaddr
, cxt
)
1672 rtx tramp
, fnaddr
, cxt
;
1676 /* Set the cpu type and print out other fancy things,
1677 at the top of the file. */
1680 m32r_asm_file_start (file
)
1683 if (flag_verbose_asm
)
1684 fprintf (file
, "%s M32R/D special options: -G %d\n",
1685 ASM_COMMENT_START
, g_switch_value
);
1688 /* Print operand X (an rtx) in assembler syntax to file FILE.
1689 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1690 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1693 m32r_print_operand (file
, x
, code
)
1701 /* Write second word of DImode or DFmode reference,
1702 register or memory. */
1703 if (GET_CODE (x
) == REG
)
1704 fputs (reg_names
[REGNO (x
)+1], file
);
1705 else if (GET_CODE (x
) == MEM
)
1707 fprintf (file
, "@(");
1708 /* Handle possible auto-increment. Since it is pre-increment and
1709 we have already done it, we can just use an offset of four. */
1710 /* ??? This is taken from rs6000.c I think. I don't think it is
1711 currently necessary, but keep it around. */
1712 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1713 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1714 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
1716 output_address (plus_constant (XEXP (x
, 0), 4));
1720 output_operand_lossage ("invalid operand to %R code");
1723 case 'H' : /* High word */
1724 case 'L' : /* Low word */
1725 if (GET_CODE (x
) == REG
)
1727 /* L = least significant word, H = most significant word */
1728 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
1729 fputs (reg_names
[REGNO (x
)], file
);
1731 fputs (reg_names
[REGNO (x
)+1], file
);
1733 else if (GET_CODE (x
) == CONST_INT
1734 || GET_CODE (x
) == CONST_DOUBLE
)
1738 split_double (x
, &first
, &second
);
1739 fprintf (file
, "0x%08lx",
1740 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
1743 output_operand_lossage ("invalid operand to %H/%L code");
1751 if (GET_CODE (x
) != CONST_DOUBLE
1752 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
1754 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1755 REAL_VALUE_TO_DECIMAL (d
, "%.20e", str
);
1756 fprintf (file
, "%s", str
);
1760 case 'B' : /* Bottom half */
1761 case 'T' : /* Top half */
1762 /* Output the argument to a `seth' insn (sets the Top half-word).
1763 For constants output arguments to a seth/or3 pair to set Top and
1764 Bottom halves. For symbols output arguments to a seth/add3 pair to
1765 set Top and Bottom halves. The difference exists because for
1766 constants seth/or3 is more readable but for symbols we need to use
1767 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
1768 switch (GET_CODE (x
))
1775 split_double (x
, &first
, &second
);
1776 x
= WORDS_BIG_ENDIAN
? second
: first
;
1778 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
1784 ? INTVAL (x
) & 0xffff
1785 : (INTVAL (x
) >> 16) & 0xffff));
1791 && small_data_operand (x
, VOIDmode
))
1793 fputs ("sda(", file
);
1794 output_addr_const (file
, x
);
1800 fputs (code
== 'T' ? "shigh(" : "low(", file
);
1801 output_addr_const (file
, x
);
1805 output_operand_lossage ("invalid operand to %T/%B code");
1812 /* Output a load/store with update indicator if appropriate. */
1813 if (GET_CODE (x
) == MEM
)
1815 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1816 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1820 output_operand_lossage ("invalid operand to %U code");
1824 /* Print a constant value negated. */
1825 if (GET_CODE (x
) == CONST_INT
)
1826 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
1828 output_operand_lossage ("invalid operand to %N code");
1832 /* Print a const_int in hex. Used in comments. */
1833 if (GET_CODE (x
) == CONST_INT
)
1835 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
1844 fputs (IMMEDIATE_PREFIX
, file
);
1847 #if 0 /* ??? no longer used */
1849 fputs (reg_names
[SDA_REGNUM
], file
);
1854 /* Do nothing special. */
1859 output_operand_lossage ("invalid operand output code");
1862 switch (GET_CODE (x
))
1865 fputs (reg_names
[REGNO (x
)], file
);
1869 fprintf (file
, "@(");
1870 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
1871 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
1872 GET_MODE_SIZE (GET_MODE (x
))));
1873 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1874 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
1875 - GET_MODE_SIZE (GET_MODE (x
))));
1877 output_address (XEXP (x
, 0));
1882 /* We handle SFmode constants here as output_addr_const doesn't. */
1883 if (GET_MODE (x
) == SFmode
)
1888 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1889 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
1890 fprintf (file
, "0x%08lx", l
);
1894 /* Fall through. Let output_addr_const deal with it. */
1897 output_addr_const (file
, x
);
1902 /* Print a memory address as an operand to reference that memory location. */
1905 m32r_print_operand_address (file
, addr
)
1910 register rtx index
= 0;
1913 switch (GET_CODE (addr
))
1916 fputs (reg_names
[REGNO (addr
)], file
);
1920 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
1921 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
1922 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1923 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
1925 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
1926 if (GET_CODE (base
) == REG
)
1928 /* Print the offset first (if present) to conform to the manual. */
1932 fprintf (file
, "%d,", offset
);
1933 fputs (reg_names
[REGNO (base
)], file
);
1935 /* The chip doesn't support this, but left in for generality. */
1936 else if (GET_CODE (index
) == REG
)
1937 fprintf (file
, "%s,%s",
1938 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
1939 /* Not sure this can happen, but leave in for now. */
1940 else if (GET_CODE (index
) == SYMBOL_REF
)
1942 output_addr_const (file
, index
);
1944 fputs (reg_names
[REGNO (base
)], file
);
1949 else if (GET_CODE (base
) == LO_SUM
)
1952 || GET_CODE (XEXP (base
, 0)) != REG
)
1954 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
1955 fputs ("sda(", file
);
1957 fputs ("low(", file
);
1958 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
1960 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
1967 if (GET_CODE (XEXP (addr
, 0)) != REG
)
1969 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
1970 fputs ("sda(", file
);
1972 fputs ("low(", file
);
1973 output_addr_const (file
, XEXP (addr
, 1));
1975 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
1980 /* We shouldn't get here as we've lost the mode of the memory object
1981 (which says how much to inc/dec by). */
1986 output_addr_const (file
, addr
);
1991 /* Return true if the operands are the constants 0 and 1. */
1993 zero_and_one (operand1
, operand2
)
1998 GET_CODE (operand1
) == CONST_INT
1999 && GET_CODE (operand2
) == CONST_INT
2000 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2001 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2004 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2006 conditional_move_operand (operand
, int_mode
)
2010 enum machine_mode mode
= (enum machine_mode
)int_mode
;
2012 /* Only defined for simple integers so far... */
2013 if (mode
!= SImode
&& mode
!= HImode
&& mode
!= QImode
)
2016 /* At the moment we can hanndle moving registers and loading constants. */
2017 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2019 switch (GET_CODE (operand
))
2025 return INT8_P (INTVAL (operand
));
2029 fprintf (stderr
, "Test for cond move op of type: %s\n",
2030 GET_RTX_NAME (GET_CODE (operand
)));
2036 /* Return true if the code is a test of the carry bit */
2038 carry_compare_operand (op
, int_mode
)
2044 if (GET_MODE (op
) != CCmode
&& GET_MODE (op
) != VOIDmode
)
2047 if (GET_CODE (op
) != NE
&& GET_CODE (op
) != EQ
)
2051 if (GET_CODE (x
) != REG
|| REGNO (x
) != CARRY_REGNUM
)
2055 if (GET_CODE (x
) != CONST_INT
|| INTVAL (x
) != 0)
2062 /* Generate the correct assembler code to handle the conditional loading of a
2063 value into a register. It is known that the operands satisfy the
2064 conditional_move_operand() function above. The destination is operand[0].
2065 The condition is operand [1]. The 'true' value is operand [2] and the
2066 'false' value is operand [3]. */
2068 emit_cond_move (operands
, insn
)
2072 static char buffer
[100];
2076 /* Destination must be a register. */
2077 if (GET_CODE (operands
[0]) != REG
)
2079 if (! conditional_move_operand (operands
[2], SImode
))
2081 if (! conditional_move_operand (operands
[3], SImode
))
2085 /* Check to see if the test is reversed. */
2086 if (GET_CODE (operands
[1]) == NE
)
2088 rtx tmp
= operands
[2];
2089 operands
[2] = operands
[3];
2093 /* Catch a special case where 0 or 1 is being loaded into the destination.
2094 Since we already have these values in the C bit we can use a special
2096 if (zero_and_one (operands
[2], operands
[3]))
2098 char * dest
= reg_names
[REGNO (operands
[0])];
2100 sprintf (buffer
, "mvfc %s, cbr", dest
);
2102 /* If the true value was '0' then we need to invert the results of the move. */
2103 if (INTVAL (operands
[2]) == 0)
2104 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",