1 /* Subroutines for code generation on Motorola 68HC11 and 68HC12.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA.
24 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
25 on gcc 2.6.3. I have used it as a starting point for this port.
26 However, this new port is a complete re-write. Its internal
27 design is completely different. The generated code is not
28 compatible with the gcc 2.6.3 port.
30 The gcc 2.6.3 port is available at:
32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
39 #include "coretypes.h"
45 #include "hard-reg-set.h"
47 #include "insn-config.h"
48 #include "conditions.h"
50 #include "insn-attr.h"
56 #include "basic-block.h"
61 #include "target-def.h"
63 static void emit_move_after_reload (rtx
, rtx
, rtx
);
64 static rtx
simplify_logical (enum machine_mode
, int, rtx
, rtx
*);
65 static void m68hc11_emit_logical (enum machine_mode
, int, rtx
*);
66 static void m68hc11_reorg (void);
67 static int go_if_legitimate_address_internal (rtx
, enum machine_mode
, int);
68 static int register_indirect_p (rtx
, enum machine_mode
, int);
69 static rtx
m68hc11_expand_compare (enum rtx_code
, rtx
, rtx
);
70 static int must_parenthesize (rtx
);
71 static int m68hc11_address_cost (rtx
);
72 static int m68hc11_shift_cost (enum machine_mode
, rtx
, int);
73 static int m68hc11_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
74 static bool m68hc11_rtx_costs (rtx
, int, int, int *);
75 static tree
m68hc11_handle_fntype_attribute (tree
*, tree
, tree
, int, bool *);
76 const struct attribute_spec m68hc11_attribute_table
[];
78 void create_regs_rtx (void);
80 static void asm_print_register (FILE *, int);
81 static void m68hc11_output_function_epilogue (FILE *, HOST_WIDE_INT
);
82 static void m68hc11_asm_out_constructor (rtx
, int);
83 static void m68hc11_asm_out_destructor (rtx
, int);
84 static void m68hc11_file_start (void);
85 static void m68hc11_encode_section_info (tree
, rtx
, int);
86 static const char *m68hc11_strip_name_encoding (const char* str
);
87 static unsigned int m68hc11_section_type_flags (tree
, const char*, int);
88 static int autoinc_mode (rtx
);
89 static int m68hc11_make_autoinc_notes (rtx
*, void *);
90 static void m68hc11_init_libfuncs (void);
91 static rtx
m68hc11_struct_value_rtx (tree
, int);
92 static bool m68hc11_return_in_memory (tree
, tree
);
94 /* Must be set to 1 to produce debug messages. */
97 extern FILE *asm_out_file
;
102 rtx m68hc11_soft_tmp_reg
;
103 static GTY(()) rtx stack_push_word
;
104 static GTY(()) rtx stack_pop_word
;
105 static GTY(()) rtx z_reg
;
106 static GTY(()) rtx z_reg_qi
;
107 static int regs_inited
= 0;
109 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
110 int current_function_interrupt
;
112 /* Set to 1 by expand_prologue() when the function is a trap handler. */
113 int current_function_trap
;
115 /* Set to 1 when the current function is placed in 68HC12 banked
116 memory and must return with rtc. */
117 int current_function_far
;
119 /* Min offset that is valid for the indirect addressing mode. */
120 HOST_WIDE_INT m68hc11_min_offset
= 0;
122 /* Max offset that is valid for the indirect addressing mode. */
123 HOST_WIDE_INT m68hc11_max_offset
= 256;
125 /* The class value for base registers. */
126 enum reg_class m68hc11_base_reg_class
= A_REGS
;
128 /* The class value for index registers. This is NO_REGS for 68HC11. */
129 enum reg_class m68hc11_index_reg_class
= NO_REGS
;
131 enum reg_class m68hc11_tmp_regs_class
= NO_REGS
;
133 /* Tables that tell whether a given hard register is valid for
134 a base or an index register. It is filled at init time depending
135 on the target processor. */
136 unsigned char m68hc11_reg_valid_for_base
[FIRST_PSEUDO_REGISTER
];
137 unsigned char m68hc11_reg_valid_for_index
[FIRST_PSEUDO_REGISTER
];
139 /* A correction offset which is applied to the stack pointer.
140 This is 1 for 68HC11 and 0 for 68HC12. */
141 int m68hc11_sp_correction
;
143 #define ADDR_STRICT 0x01 /* Accept only registers in class A_REGS */
144 #define ADDR_INCDEC 0x02 /* Post/Pre inc/dec */
145 #define ADDR_INDEXED 0x04 /* D-reg index */
146 #define ADDR_OFFSET 0x08
147 #define ADDR_INDIRECT 0x10 /* Accept (mem (mem ...)) for [n,X] */
148 #define ADDR_CONST 0x20 /* Accept const and symbol_ref */
150 int m68hc11_addr_mode
;
151 int m68hc11_mov_addr_mode
;
153 /* Comparison operands saved by the "tstxx" and "cmpxx" expand patterns. */
154 rtx m68hc11_compare_op0
;
155 rtx m68hc11_compare_op1
;
158 const struct processor_costs
*m68hc11_cost
;
160 /* Costs for a 68HC11. */
161 static const struct processor_costs m6811_cost
= {
166 /* non-constant shift */
169 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
170 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
171 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
174 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
175 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
176 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
177 COSTS_N_INSNS (2), COSTS_N_INSNS (4),
178 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (10),
179 COSTS_N_INSNS (8), COSTS_N_INSNS (6), COSTS_N_INSNS (4)
184 COSTS_N_INSNS (20 * 4),
186 COSTS_N_INSNS (20 * 16),
195 /* Costs for a 68HC12. */
196 static const struct processor_costs m6812_cost
= {
201 /* non-constant shift */
204 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
205 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
206 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
209 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
210 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
211 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
212 COSTS_N_INSNS (2), COSTS_N_INSNS (4), COSTS_N_INSNS (6),
213 COSTS_N_INSNS (8), COSTS_N_INSNS (10), COSTS_N_INSNS (8),
214 COSTS_N_INSNS (6), COSTS_N_INSNS (4)
221 COSTS_N_INSNS (3 * 4),
230 /* Initialize the GCC target structure. */
231 #undef TARGET_ATTRIBUTE_TABLE
232 #define TARGET_ATTRIBUTE_TABLE m68hc11_attribute_table
234 #undef TARGET_ASM_ALIGNED_HI_OP
235 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE m68hc11_output_function_epilogue
240 #undef TARGET_ASM_FILE_START
241 #define TARGET_ASM_FILE_START m68hc11_file_start
242 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
243 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
245 #undef TARGET_DEFAULT_TARGET_FLAGS
246 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
248 #undef TARGET_ENCODE_SECTION_INFO
249 #define TARGET_ENCODE_SECTION_INFO m68hc11_encode_section_info
251 #undef TARGET_SECTION_TYPE_FLAGS
252 #define TARGET_SECTION_TYPE_FLAGS m68hc11_section_type_flags
254 #undef TARGET_RTX_COSTS
255 #define TARGET_RTX_COSTS m68hc11_rtx_costs
256 #undef TARGET_ADDRESS_COST
257 #define TARGET_ADDRESS_COST m68hc11_address_cost
259 #undef TARGET_MACHINE_DEPENDENT_REORG
260 #define TARGET_MACHINE_DEPENDENT_REORG m68hc11_reorg
262 #undef TARGET_INIT_LIBFUNCS
263 #define TARGET_INIT_LIBFUNCS m68hc11_init_libfuncs
265 #undef TARGET_STRUCT_VALUE_RTX
266 #define TARGET_STRUCT_VALUE_RTX m68hc11_struct_value_rtx
267 #undef TARGET_RETURN_IN_MEMORY
268 #define TARGET_RETURN_IN_MEMORY m68hc11_return_in_memory
269 #undef TARGET_CALLEE_COPIES
270 #define TARGET_CALLEE_COPIES hook_callee_copies_named
272 #undef TARGET_STRIP_NAME_ENCODING
273 #define TARGET_STRIP_NAME_ENCODING m68hc11_strip_name_encoding
275 struct gcc_target targetm
= TARGET_INITIALIZER
;
278 m68hc11_override_options (void)
280 memset (m68hc11_reg_valid_for_index
, 0,
281 sizeof (m68hc11_reg_valid_for_index
));
282 memset (m68hc11_reg_valid_for_base
, 0, sizeof (m68hc11_reg_valid_for_base
));
284 /* Compilation with -fpic generates a wrong code. */
287 warning (0, "-f%s ignored for 68HC11/68HC12 (not supported)",
288 (flag_pic
> 1) ? "PIC" : "pic");
292 /* Do not enable -fweb because it breaks the 32-bit shift patterns
293 by breaking the match_dup of those patterns. The shift patterns
294 will no longer be recognized after that. */
297 /* Configure for a 68hc11 processor. */
300 target_flags
&= ~(TARGET_AUTO_INC_DEC
| TARGET_MIN_MAX
);
301 m68hc11_cost
= &m6811_cost
;
302 m68hc11_min_offset
= 0;
303 m68hc11_max_offset
= 256;
304 m68hc11_index_reg_class
= NO_REGS
;
305 m68hc11_base_reg_class
= A_REGS
;
306 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
307 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
308 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
309 m68hc11_sp_correction
= 1;
310 m68hc11_tmp_regs_class
= D_REGS
;
311 m68hc11_addr_mode
= ADDR_OFFSET
;
312 m68hc11_mov_addr_mode
= 0;
313 if (m68hc11_soft_reg_count
< 0)
314 m68hc11_soft_reg_count
= 4;
317 /* Configure for a 68hc12 processor. */
320 m68hc11_cost
= &m6812_cost
;
321 m68hc11_min_offset
= -65536;
322 m68hc11_max_offset
= 65536;
323 m68hc11_index_reg_class
= D_REGS
;
324 m68hc11_base_reg_class
= A_OR_SP_REGS
;
325 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
326 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
327 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
328 m68hc11_reg_valid_for_base
[HARD_SP_REGNUM
] = 1;
329 m68hc11_reg_valid_for_index
[HARD_D_REGNUM
] = 1;
330 m68hc11_sp_correction
= 0;
331 m68hc11_tmp_regs_class
= TMP_REGS
;
332 m68hc11_addr_mode
= ADDR_INDIRECT
| ADDR_OFFSET
| ADDR_CONST
333 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
334 m68hc11_mov_addr_mode
= ADDR_OFFSET
| ADDR_CONST
335 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
336 target_flags
|= MASK_NO_DIRECT_MODE
;
337 if (m68hc11_soft_reg_count
< 0)
338 m68hc11_soft_reg_count
= 0;
340 if (TARGET_LONG_CALLS
)
341 current_function_far
= 1;
348 m68hc11_conditional_register_usage (void)
352 if (m68hc11_soft_reg_count
> SOFT_REG_LAST
- SOFT_REG_FIRST
)
353 m68hc11_soft_reg_count
= SOFT_REG_LAST
- SOFT_REG_FIRST
;
355 for (i
= SOFT_REG_FIRST
+ m68hc11_soft_reg_count
; i
< SOFT_REG_LAST
; i
++)
358 call_used_regs
[i
] = 1;
361 /* For 68HC12, the Z register emulation is not necessary when the
362 frame pointer is not used. The frame pointer is eliminated and
363 replaced by the stack register (which is a BASE_REG_CLASS). */
364 if (TARGET_M6812
&& flag_omit_frame_pointer
&& optimize
)
366 fixed_regs
[HARD_Z_REGNUM
] = 1;
371 /* Reload and register operations. */
375 create_regs_rtx (void)
377 /* regs_inited = 1; */
378 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
379 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
380 d_reg
= gen_rtx_REG (HImode
, HARD_D_REGNUM
);
381 m68hc11_soft_tmp_reg
= gen_rtx_REG (HImode
, SOFT_TMP_REGNUM
);
383 stack_push_word
= gen_rtx_MEM (HImode
,
384 gen_rtx_PRE_DEC (HImode
,
385 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
386 stack_pop_word
= gen_rtx_MEM (HImode
,
387 gen_rtx_POST_INC (HImode
,
388 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
392 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
393 - 8 bit values are stored anywhere (except the SP register).
394 - 16 bit values can be stored in any register whose mode is 16
395 - 32 bit values can be stored in D, X registers or in a soft register
396 (except the last one because we need 2 soft registers)
397 - Values whose size is > 32 bit are not stored in real hard
398 registers. They may be stored in soft registers if there are
401 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
403 switch (GET_MODE_SIZE (mode
))
406 return S_REGNO_P (regno
) && m68hc11_soft_reg_count
>= 4;
409 return (X_REGNO_P (regno
)
410 || (S_REGNO_P (regno
) && m68hc11_soft_reg_count
>= 2));
413 return G_REGNO_P (regno
);
416 /* We have to accept a QImode in X or Y registers. Otherwise, the
417 reload pass will fail when some (SUBREG:QI (REG:HI X)) are defined
418 in the insns. Reload fails if the insn rejects the register class 'a'
419 as well as if it accepts it. Patterns that failed were
420 zero_extend_qihi2 and iorqi3. */
422 return G_REGNO_P (regno
) && !SP_REGNO_P (regno
);
430 m68hc11_hard_regno_rename_ok (int reg1
, int reg2
)
432 /* Don't accept renaming to Z register. We will replace it to
433 X,Y or D during machine reorg pass. */
434 if (reg2
== HARD_Z_REGNUM
)
437 /* Don't accept renaming D,X to Y register as the code will be bigger. */
438 if (TARGET_M6811
&& reg2
== HARD_Y_REGNUM
439 && (D_REGNO_P (reg1
) || X_REGNO_P (reg1
)))
446 preferred_reload_class (rtx operand
, enum reg_class
class)
448 enum machine_mode mode
;
450 mode
= GET_MODE (operand
);
454 printf ("Preferred reload: (class=%s): ", reg_class_names
[class]);
457 if (class == D_OR_A_OR_S_REGS
&& SP_REG_P (operand
))
458 return m68hc11_base_reg_class
;
460 if (class >= S_REGS
&& (GET_CODE (operand
) == MEM
461 || GET_CODE (operand
) == CONST_INT
))
463 /* S_REGS class must not be used. The movhi template does not
464 work to move a memory to a soft register.
465 Restrict to a hard reg. */
470 case D_OR_A_OR_S_REGS
:
476 case D_OR_SP_OR_S_REGS
:
477 class = D_OR_SP_REGS
;
479 case D_OR_Y_OR_S_REGS
:
482 case D_OR_X_OR_S_REGS
:
498 else if (class == Y_REGS
&& GET_CODE (operand
) == MEM
)
502 else if (class == A_OR_D_REGS
&& GET_MODE_SIZE (mode
) == 4)
506 else if (class >= S_REGS
&& S_REG_P (operand
))
512 case D_OR_A_OR_S_REGS
:
518 case D_OR_SP_OR_S_REGS
:
519 class = D_OR_SP_REGS
;
521 case D_OR_Y_OR_S_REGS
:
524 case D_OR_X_OR_S_REGS
:
540 else if (class >= S_REGS
)
544 printf ("Class = %s for: ", reg_class_names
[class]);
552 printf (" => class=%s\n", reg_class_names
[class]);
560 /* Return 1 if the operand is a valid indexed addressing mode.
561 For 68hc11: n,r with n in [0..255] and r in A_REGS class
562 For 68hc12: n,r no constraint on the constant, r in A_REGS class. */
564 register_indirect_p (rtx operand
, enum machine_mode mode
, int addr_mode
)
568 switch (GET_CODE (operand
))
571 if ((addr_mode
& ADDR_INDIRECT
) && GET_MODE_SIZE (mode
) <= 2)
572 return register_indirect_p (XEXP (operand
, 0), mode
,
573 addr_mode
& (ADDR_STRICT
| ADDR_OFFSET
));
580 if (addr_mode
& ADDR_INCDEC
)
581 return register_indirect_p (XEXP (operand
, 0), mode
,
582 addr_mode
& ADDR_STRICT
);
586 base
= XEXP (operand
, 0);
587 if (GET_CODE (base
) == MEM
)
590 offset
= XEXP (operand
, 1);
591 if (GET_CODE (offset
) == MEM
)
594 /* Indexed addressing mode with 2 registers. */
595 if (GET_CODE (base
) == REG
&& GET_CODE (offset
) == REG
)
597 if (!(addr_mode
& ADDR_INDEXED
))
600 addr_mode
&= ADDR_STRICT
;
601 if (REGNO_OK_FOR_BASE_P2 (REGNO (base
), addr_mode
)
602 && REGNO_OK_FOR_INDEX_P2 (REGNO (offset
), addr_mode
))
605 if (REGNO_OK_FOR_BASE_P2 (REGNO (offset
), addr_mode
)
606 && REGNO_OK_FOR_INDEX_P2 (REGNO (base
), addr_mode
))
612 if (!(addr_mode
& ADDR_OFFSET
))
615 if (GET_CODE (base
) == REG
)
617 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
620 if (!(addr_mode
& ADDR_STRICT
))
623 return REGNO_OK_FOR_BASE_P2 (REGNO (base
), 1);
626 if (GET_CODE (offset
) == REG
)
628 if (!VALID_CONSTANT_OFFSET_P (base
, mode
))
631 if (!(addr_mode
& ADDR_STRICT
))
634 return REGNO_OK_FOR_BASE_P2 (REGNO (offset
), 1);
639 return REGNO_OK_FOR_BASE_P2 (REGNO (operand
), addr_mode
& ADDR_STRICT
);
642 if (addr_mode
& ADDR_CONST
)
643 return VALID_CONSTANT_OFFSET_P (operand
, mode
);
651 /* Returns 1 if the operand fits in a 68HC11 indirect mode or in
652 a 68HC12 1-byte index addressing mode. */
654 m68hc11_small_indexed_indirect_p (rtx operand
, enum machine_mode mode
)
659 if (GET_CODE (operand
) == REG
&& reload_in_progress
660 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
661 && reg_equiv_memory_loc
[REGNO (operand
)])
663 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
664 operand
= eliminate_regs (operand
, 0, NULL_RTX
);
667 if (GET_CODE (operand
) != MEM
)
670 operand
= XEXP (operand
, 0);
671 if (CONSTANT_ADDRESS_P (operand
))
674 if (PUSH_POP_ADDRESS_P (operand
))
677 addr_mode
= m68hc11_mov_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
678 if (!register_indirect_p (operand
, mode
, addr_mode
))
681 if (TARGET_M6812
&& GET_CODE (operand
) == PLUS
682 && (reload_completed
| reload_in_progress
))
684 base
= XEXP (operand
, 0);
685 offset
= XEXP (operand
, 1);
687 /* The offset can be a symbol address and this is too big
688 for the operand constraint. */
689 if (GET_CODE (base
) != CONST_INT
&& GET_CODE (offset
) != CONST_INT
)
692 if (GET_CODE (base
) == CONST_INT
)
695 switch (GET_MODE_SIZE (mode
))
698 if (INTVAL (offset
) < -16 + 6 || INTVAL (offset
) > 15 - 6)
703 if (INTVAL (offset
) < -16 + 2 || INTVAL (offset
) > 15 - 2)
708 if (INTVAL (offset
) < -16 || INTVAL (offset
) > 15)
717 m68hc11_register_indirect_p (rtx operand
, enum machine_mode mode
)
721 if (GET_CODE (operand
) == REG
&& reload_in_progress
722 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
723 && reg_equiv_memory_loc
[REGNO (operand
)])
725 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
726 operand
= eliminate_regs (operand
, 0, NULL_RTX
);
728 if (GET_CODE (operand
) != MEM
)
731 operand
= XEXP (operand
, 0);
732 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
733 return register_indirect_p (operand
, mode
, addr_mode
);
737 go_if_legitimate_address_internal (rtx operand
, enum machine_mode mode
,
742 if (CONSTANT_ADDRESS_P (operand
) && TARGET_M6812
)
744 /* Reject the global variables if they are too wide. This forces
745 a load of their address in a register and generates smaller code. */
746 if (GET_MODE_SIZE (mode
) == 8)
751 addr_mode
= m68hc11_addr_mode
| (strict
? ADDR_STRICT
: 0);
752 if (register_indirect_p (operand
, mode
, addr_mode
))
756 if (PUSH_POP_ADDRESS_P (operand
))
760 if (symbolic_memory_operand (operand
, mode
))
768 m68hc11_go_if_legitimate_address (rtx operand
, enum machine_mode mode
,
775 printf ("Checking: ");
780 result
= go_if_legitimate_address_internal (operand
, mode
, strict
);
784 printf (" -> %s\n", result
== 0 ? "NO" : "YES");
791 printf ("go_if_legitimate%s, ret 0: %d:",
792 (strict
? "_strict" : ""), mode
);
801 m68hc11_legitimize_address (rtx
*operand ATTRIBUTE_UNUSED
,
802 rtx old_operand ATTRIBUTE_UNUSED
,
803 enum machine_mode mode ATTRIBUTE_UNUSED
)
810 m68hc11_reload_operands (rtx operands
[])
812 enum machine_mode mode
;
814 if (regs_inited
== 0)
817 mode
= GET_MODE (operands
[1]);
819 /* Input reload of indirect addressing (MEM (PLUS (REG) (CONST))). */
820 if (A_REG_P (operands
[0]) && memory_reload_operand (operands
[1], mode
))
822 rtx big_offset
= XEXP (XEXP (operands
[1], 0), 1);
823 rtx base
= XEXP (XEXP (operands
[1], 0), 0);
825 if (GET_CODE (base
) != REG
)
832 /* If the offset is out of range, we have to compute the address
833 with a separate add instruction. We try to do with with an 8-bit
834 add on the A register. This is possible only if the lowest part
835 of the offset (i.e., big_offset % 256) is a valid constant offset
836 with respect to the mode. If it's not, we have to generate a
837 16-bit add on the D register. From:
839 (SET (REG X (MEM (PLUS (REG X) (CONST_INT 1000)))))
843 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
844 (SET (REG A) (PLUS (REG A) (CONST_INT 1000 / 256)))
845 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
846 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256)))
848 (SET (REG X) (PLUS (REG X) (CONST_INT 1000 / 256 * 256)))
849 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256))))
852 if (!VALID_CONSTANT_OFFSET_P (big_offset
, mode
))
855 rtx reg
= operands
[0];
857 int val
= INTVAL (big_offset
);
860 /* We use the 'operands[0]' as a scratch register to compute the
861 address. Make sure 'base' is in that register. */
862 if (!rtx_equal_p (base
, operands
[0]))
864 emit_move_insn (reg
, base
);
874 vh
= (val
>> 8) & 0x0FF;
878 /* Create the lowest part offset that still remains to be added.
879 If it's not a valid offset, do a 16-bit add. */
880 offset
= GEN_INT (vl
);
881 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
883 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
884 gen_rtx_PLUS (HImode
, reg
, big_offset
)));
889 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
890 gen_rtx_PLUS (HImode
, reg
,
891 GEN_INT (vh
<< 8))));
893 emit_move_insn (operands
[0],
894 gen_rtx_MEM (GET_MODE (operands
[1]),
895 gen_rtx_PLUS (Pmode
, reg
, offset
)));
900 /* Use the normal gen_movhi pattern. */
905 m68hc11_emit_libcall (const char *name
, enum rtx_code code
,
906 enum machine_mode dmode
, enum machine_mode smode
,
907 int noperands
, rtx
*operands
)
915 libcall
= gen_rtx_SYMBOL_REF (Pmode
, name
);
919 ret
= emit_library_call_value (libcall
, NULL_RTX
, LCT_CONST
,
920 dmode
, 1, operands
[1], smode
);
921 equiv
= gen_rtx_fmt_e (code
, dmode
, operands
[1]);
925 ret
= emit_library_call_value (libcall
, NULL_RTX
,
927 operands
[1], smode
, operands
[2],
929 equiv
= gen_rtx_fmt_ee (code
, dmode
, operands
[1], operands
[2]);
936 insns
= get_insns ();
938 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
941 /* Returns true if X is a PRE/POST increment decrement
942 (same as auto_inc_p() in rtlanal.c but do not take into
943 account the stack). */
945 m68hc11_auto_inc_p (rtx x
)
947 return GET_CODE (x
) == PRE_DEC
948 || GET_CODE (x
) == POST_INC
949 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_INC
;
953 /* Predicates for machine description. */
956 memory_reload_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
958 return GET_CODE (operand
) == MEM
959 && GET_CODE (XEXP (operand
, 0)) == PLUS
960 && ((GET_CODE (XEXP (XEXP (operand
, 0), 0)) == REG
961 && GET_CODE (XEXP (XEXP (operand
, 0), 1)) == CONST_INT
)
962 || (GET_CODE (XEXP (XEXP (operand
, 0), 1)) == REG
963 && GET_CODE (XEXP (XEXP (operand
, 0), 0)) == CONST_INT
));
967 m68hc11_symbolic_p (rtx operand
, enum machine_mode mode
)
969 if (GET_CODE (operand
) == MEM
)
971 rtx op
= XEXP (operand
, 0);
973 if (symbolic_memory_operand (op
, mode
))
980 m68hc11_indirect_p (rtx operand
, enum machine_mode mode
)
982 if (GET_CODE (operand
) == MEM
&& GET_MODE (operand
) == mode
)
984 rtx op
= XEXP (operand
, 0);
987 if (m68hc11_page0_symbol_p (op
))
990 if (symbolic_memory_operand (op
, mode
))
993 if (reload_in_progress
)
996 operand
= XEXP (operand
, 0);
997 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
998 return register_indirect_p (operand
, mode
, addr_mode
);
1004 memory_indexed_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1006 if (GET_CODE (operand
) != MEM
)
1009 operand
= XEXP (operand
, 0);
1010 if (GET_CODE (operand
) == PLUS
)
1012 if (GET_CODE (XEXP (operand
, 0)) == REG
)
1013 operand
= XEXP (operand
, 0);
1014 else if (GET_CODE (XEXP (operand
, 1)) == REG
)
1015 operand
= XEXP (operand
, 1);
1017 return GET_CODE (operand
) == REG
1018 && (REGNO (operand
) >= FIRST_PSEUDO_REGISTER
1019 || A_REGNO_P (REGNO (operand
)));
1023 push_pop_operand_p (rtx operand
)
1025 if (GET_CODE (operand
) != MEM
)
1029 operand
= XEXP (operand
, 0);
1030 return PUSH_POP_ADDRESS_P (operand
);
1033 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1034 reference and a constant. */
1037 symbolic_memory_operand (rtx op
, enum machine_mode mode
)
1039 switch (GET_CODE (op
))
1047 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1048 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1049 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1051 /* ??? This clause seems to be irrelevant. */
1053 return GET_MODE (op
) == mode
;
1056 return symbolic_memory_operand (XEXP (op
, 0), mode
)
1057 && symbolic_memory_operand (XEXP (op
, 1), mode
);
1064 /* Emit the code to build the trampoline used to call a nested function.
1068 ldy #&CXT movw #&CXT,*_.d1
1069 sty *_.d1 jmp FNADDR
1074 m68hc11_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
1076 const char *static_chain_reg
= reg_names
[STATIC_CHAIN_REGNUM
];
1079 if (*static_chain_reg
== '*')
1083 emit_move_insn (gen_rtx_MEM (HImode
, tramp
), GEN_INT (0x18ce));
1084 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 2)), cxt
);
1085 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 4)),
1087 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 6)),
1088 gen_rtx_CONST (QImode
,
1089 gen_rtx_SYMBOL_REF (Pmode
,
1090 static_chain_reg
)));
1091 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 7)),
1093 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 8)), fnaddr
);
1097 emit_move_insn (gen_rtx_MEM (HImode
, tramp
), GEN_INT (0x1803));
1098 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 2)), cxt
);
1099 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 4)),
1100 gen_rtx_CONST (HImode
,
1101 gen_rtx_SYMBOL_REF (Pmode
,
1102 static_chain_reg
)));
1103 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 6)),
1105 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 7)), fnaddr
);
1109 /* Declaration of types. */
1111 /* Handle an "tiny_data" attribute; arguments as in
1112 struct attribute_spec.handler. */
1114 m68hc11_handle_page0_attribute (tree
*node
, tree name
,
1115 tree args ATTRIBUTE_UNUSED
,
1116 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1120 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
1122 DECL_SECTION_NAME (decl
) = build_string (6, ".page0");
1126 warning (0, "%qs attribute ignored", IDENTIFIER_POINTER (name
));
1127 *no_add_attrs
= true;
1133 const struct attribute_spec m68hc11_attribute_table
[] =
1135 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1136 { "interrupt", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1137 { "trap", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1138 { "far", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1139 { "near", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1140 { "page0", 0, 0, false, false, false, m68hc11_handle_page0_attribute
},
1141 { NULL
, 0, 0, false, false, false, NULL
}
1144 /* Keep track of the symbol which has a `trap' attribute and which uses
1145 the `swi' calling convention. Since there is only one trap, we only
1146 record one such symbol. If there are several, a warning is reported. */
1147 static rtx trap_handler_symbol
= 0;
1149 /* Handle an attribute requiring a FUNCTION_TYPE, FIELD_DECL or TYPE_DECL;
1150 arguments as in struct attribute_spec.handler. */
1152 m68hc11_handle_fntype_attribute (tree
*node
, tree name
,
1153 tree args ATTRIBUTE_UNUSED
,
1154 int flags ATTRIBUTE_UNUSED
,
1157 if (TREE_CODE (*node
) != FUNCTION_TYPE
1158 && TREE_CODE (*node
) != METHOD_TYPE
1159 && TREE_CODE (*node
) != FIELD_DECL
1160 && TREE_CODE (*node
) != TYPE_DECL
)
1162 warning (0, "%qs attribute only applies to functions",
1163 IDENTIFIER_POINTER (name
));
1164 *no_add_attrs
= true;
1169 /* Undo the effects of the above. */
1172 m68hc11_strip_name_encoding (const char *str
)
1174 return str
+ (*str
== '*' || *str
== '@' || *str
== '&');
1178 m68hc11_encode_label (tree decl
)
1180 const char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1181 int len
= strlen (str
);
1182 char *newstr
= alloca (len
+ 2);
1185 strcpy (&newstr
[1], str
);
1187 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = ggc_alloc_string (newstr
, len
+ 1);
1190 /* Return 1 if this is a symbol in page0 */
1192 m68hc11_page0_symbol_p (rtx x
)
1194 switch (GET_CODE (x
))
1197 return XSTR (x
, 0) != 0 && XSTR (x
, 0)[0] == '@';
1200 return m68hc11_page0_symbol_p (XEXP (x
, 0));
1203 if (!m68hc11_page0_symbol_p (XEXP (x
, 0)))
1206 return GET_CODE (XEXP (x
, 1)) == CONST_INT
1207 && INTVAL (XEXP (x
, 1)) < 256
1208 && INTVAL (XEXP (x
, 1)) >= 0;
1215 /* We want to recognize trap handlers so that we handle calls to traps
1216 in a special manner (by issuing the trap). This information is stored
1217 in SYMBOL_REF_FLAG. */
1220 m68hc11_encode_section_info (tree decl
, rtx rtl
, int first ATTRIBUTE_UNUSED
)
1226 if (TREE_CODE (decl
) == VAR_DECL
)
1228 if (lookup_attribute ("page0", DECL_ATTRIBUTES (decl
)) != 0)
1229 m68hc11_encode_label (decl
);
1233 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1236 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
1239 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1241 else if (lookup_attribute ("near", func_attr
) == NULL_TREE
)
1242 is_far
= TARGET_LONG_CALLS
!= 0;
1244 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1245 if (trap_handler
&& is_far
)
1247 warning (0, "%<trap%> and %<far%> attributes are not compatible, ignoring %<far%>");
1252 if (trap_handler_symbol
!= 0)
1253 warning (0, "%<trap%> attribute is already used");
1255 trap_handler_symbol
= XEXP (rtl
, 0);
1257 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = is_far
;
1261 m68hc11_section_type_flags (tree decl
, const char *name
, int reloc
)
1263 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
1265 if (strncmp (name
, ".eeprom", 7) == 0)
1267 flags
|= SECTION_WRITE
| SECTION_CODE
| SECTION_OVERRIDE
;
1274 m68hc11_is_far_symbol (rtx sym
)
1276 if (GET_CODE (sym
) == MEM
)
1277 sym
= XEXP (sym
, 0);
1279 return SYMBOL_REF_FLAG (sym
);
1283 m68hc11_is_trap_symbol (rtx sym
)
1285 if (GET_CODE (sym
) == MEM
)
1286 sym
= XEXP (sym
, 0);
1288 return trap_handler_symbol
!= 0 && rtx_equal_p (trap_handler_symbol
, sym
);
1292 /* Argument support functions. */
1294 /* Define the offset between two registers, one to be eliminated, and the
1295 other its replacement, at the start of a routine. */
1297 m68hc11_initial_elimination_offset (int from
, int to
)
1304 /* For a trap handler, we must take into account the registers which
1305 are pushed on the stack during the trap (except the PC). */
1306 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1307 current_function_interrupt
= lookup_attribute ("interrupt",
1308 func_attr
) != NULL_TREE
;
1309 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1311 if (lookup_attribute ("far", func_attr
) != 0)
1312 current_function_far
= 1;
1313 else if (lookup_attribute ("near", func_attr
) != 0)
1314 current_function_far
= 0;
1316 current_function_far
= (TARGET_LONG_CALLS
!= 0
1317 && !current_function_interrupt
1320 if (trap_handler
&& from
== ARG_POINTER_REGNUM
)
1323 /* For a function using 'call/rtc' we must take into account the
1324 page register which is pushed in the call. */
1325 else if (current_function_far
&& from
== ARG_POINTER_REGNUM
)
1330 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1332 /* 2 is for the saved frame.
1333 1 is for the 'sts' correction when creating the frame. */
1334 return get_frame_size () + 2 + m68hc11_sp_correction
+ size
;
1337 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1339 return m68hc11_sp_correction
;
1342 /* Push any 2 byte pseudo hard registers that we need to save. */
1343 for (regno
= SOFT_REG_FIRST
; regno
< SOFT_REG_LAST
; regno
++)
1345 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1351 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1353 return get_frame_size () + size
;
1356 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1363 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1364 for a call to a function whose data type is FNTYPE.
1365 For a library call, FNTYPE is 0. */
1368 m68hc11_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
)
1372 z_replacement_completed
= 0;
1376 /* For a library call, we must find out the type of the return value.
1377 When the return value is bigger than 4 bytes, it is returned in
1378 memory. In that case, the first argument of the library call is a
1379 pointer to the memory location. Because the first argument is passed in
1380 register D, we have to identify this, so that the first function
1381 parameter is not passed in D either. */
1387 if (libname
== 0 || GET_CODE (libname
) != SYMBOL_REF
)
1390 /* If the library ends in 'di' or in 'df', we assume it's
1391 returning some DImode or some DFmode which are 64-bit wide. */
1392 name
= XSTR (libname
, 0);
1393 len
= strlen (name
);
1395 && ((name
[len
- 2] == 'd'
1396 && (name
[len
- 1] == 'f' || name
[len
- 1] == 'i'))
1397 || (name
[len
- 3] == 'd'
1398 && (name
[len
- 2] == 'i' || name
[len
- 2] == 'f'))))
1400 /* We are in. Mark the first parameter register as already used. */
1407 ret_type
= TREE_TYPE (fntype
);
1409 if (ret_type
&& aggregate_value_p (ret_type
, fntype
))
1416 /* Update the data in CUM to advance over an argument
1417 of mode MODE and data type TYPE.
1418 (TYPE is null for libcalls where that information may not be available.) */
1421 m68hc11_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1422 tree type
, int named ATTRIBUTE_UNUSED
)
1424 if (mode
!= BLKmode
)
1426 if (cum
->words
== 0 && GET_MODE_SIZE (mode
) == 4)
1429 cum
->words
= GET_MODE_SIZE (mode
);
1433 cum
->words
+= GET_MODE_SIZE (mode
);
1434 if (cum
->words
<= HARD_REG_SIZE
)
1440 cum
->words
+= int_size_in_bytes (type
);
1445 /* Define where to put the arguments to a function.
1446 Value is zero to push the argument on the stack,
1447 or a hard register in which to store the argument.
1449 MODE is the argument's machine mode.
1450 TYPE is the data type of the argument (as a tree).
1451 This is null for libcalls where that information may
1453 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1454 the preceding args and about the function being called.
1455 NAMED is nonzero if this argument is a named parameter
1456 (otherwise it is an extra parameter matching an ellipsis). */
1459 m68hc11_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1460 tree type ATTRIBUTE_UNUSED
, int named ATTRIBUTE_UNUSED
)
1462 if (cum
->words
!= 0)
1467 if (mode
!= BLKmode
)
1469 if (GET_MODE_SIZE (mode
) == 2 * HARD_REG_SIZE
)
1470 return gen_rtx_REG (mode
, HARD_X_REGNUM
);
1472 if (GET_MODE_SIZE (mode
) > HARD_REG_SIZE
)
1476 return gen_rtx_REG (mode
, HARD_D_REGNUM
);
1481 /* If defined, a C expression which determines whether, and in which direction,
1482 to pad out an argument with extra space. The value should be of type
1483 `enum direction': either `upward' to pad above the argument,
1484 `downward' to pad below, or `none' to inhibit padding.
1486 Structures are stored left shifted in their argument slot. */
1488 m68hc11_function_arg_padding (enum machine_mode mode
, tree type
)
1490 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
1493 /* Fall back to the default. */
1494 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
1498 /* Function prologue and epilogue. */
1500 /* Emit a move after the reload pass has completed. This is used to
1501 emit the prologue and epilogue. */
1503 emit_move_after_reload (rtx to
, rtx from
, rtx scratch
)
1507 if (TARGET_M6812
|| H_REG_P (to
) || H_REG_P (from
))
1509 insn
= emit_move_insn (to
, from
);
1513 emit_move_insn (scratch
, from
);
1514 insn
= emit_move_insn (to
, scratch
);
1517 /* Put a REG_INC note to tell the flow analysis that the instruction
1519 if (IS_STACK_PUSH (to
))
1521 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
,
1522 XEXP (XEXP (to
, 0), 0),
1525 else if (IS_STACK_POP (from
))
1527 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
,
1528 XEXP (XEXP (from
, 0), 0),
1532 /* For 68HC11, put a REG_INC note on `sts _.frame' to prevent the cse-reg
1533 to think that sp == _.frame and later replace a x = sp with x = _.frame.
1534 The problem is that we are lying to gcc and use `txs' for x = sp
1535 (which is not really true because txs is really x = sp + 1). */
1536 else if (TARGET_M6811
&& SP_REG_P (from
))
1538 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
,
1545 m68hc11_total_frame_size (void)
1550 size
= get_frame_size ();
1551 if (current_function_interrupt
)
1553 size
+= 3 * HARD_REG_SIZE
;
1555 if (frame_pointer_needed
)
1556 size
+= HARD_REG_SIZE
;
1558 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1559 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1560 size
+= HARD_REG_SIZE
;
1566 m68hc11_output_function_epilogue (FILE *out ATTRIBUTE_UNUSED
,
1567 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1569 /* We catch the function epilogue generation to have a chance
1570 to clear the z_replacement_completed flag. */
1571 z_replacement_completed
= 0;
1575 expand_prologue (void)
1582 if (reload_completed
!= 1)
1585 size
= get_frame_size ();
1589 /* Generate specific prologue for interrupt handlers. */
1590 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1591 current_function_interrupt
= lookup_attribute ("interrupt",
1592 func_attr
) != NULL_TREE
;
1593 current_function_trap
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1594 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1595 current_function_far
= 1;
1596 else if (lookup_attribute ("near", func_attr
) != NULL_TREE
)
1597 current_function_far
= 0;
1599 current_function_far
= (TARGET_LONG_CALLS
!= 0
1600 && !current_function_interrupt
1601 && !current_function_trap
);
1603 /* Get the scratch register to build the frame and push registers.
1604 If the first argument is a 32-bit quantity, the D+X registers
1605 are used. Use Y to compute the frame. Otherwise, X is cheaper.
1606 For 68HC12, this scratch register is not used. */
1607 if (current_function_args_info
.nregs
== 2)
1612 /* Save current stack frame. */
1613 if (frame_pointer_needed
)
1614 emit_move_after_reload (stack_push_word
, hard_frame_pointer_rtx
, scratch
);
1616 /* For an interrupt handler, we must preserve _.tmp, _.z and _.xy.
1617 Other soft registers in page0 need not to be saved because they
1618 will be restored by C functions. For a trap handler, we don't
1619 need to preserve these registers because this is a synchronous call. */
1620 if (current_function_interrupt
)
1622 emit_move_after_reload (stack_push_word
, m68hc11_soft_tmp_reg
, scratch
);
1623 emit_move_after_reload (stack_push_word
,
1624 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
), scratch
);
1625 emit_move_after_reload (stack_push_word
,
1626 gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1630 /* Allocate local variables. */
1631 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1633 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1634 stack_pointer_rtx
, GEN_INT (-size
)));
1636 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1640 insn
= gen_rtx_PARALLEL
1643 gen_rtx_SET (VOIDmode
,
1645 gen_rtx_PLUS (HImode
,
1648 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1655 /* Allocate by pushing scratch values. */
1656 for (i
= 2; i
<= size
; i
+= 2)
1657 emit_move_after_reload (stack_push_word
, ix_reg
, 0);
1660 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1661 stack_pointer_rtx
, constm1_rtx
));
1664 /* Create the frame pointer. */
1665 if (frame_pointer_needed
)
1666 emit_move_after_reload (hard_frame_pointer_rtx
,
1667 stack_pointer_rtx
, scratch
);
1669 /* Push any 2 byte pseudo hard registers that we need to save. */
1670 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1672 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1674 emit_move_after_reload (stack_push_word
,
1675 gen_rtx_REG (HImode
, regno
), scratch
);
1681 expand_epilogue (void)
1688 if (reload_completed
!= 1)
1691 size
= get_frame_size ();
1693 /* If we are returning a value in two registers, we have to preserve the
1694 X register and use the Y register to restore the stack and the saved
1695 registers. Otherwise, use X because it's faster (and smaller). */
1696 if (current_function_return_rtx
== 0)
1698 else if (GET_CODE (current_function_return_rtx
) == MEM
)
1699 return_size
= HARD_REG_SIZE
;
1701 return_size
= GET_MODE_SIZE (GET_MODE (current_function_return_rtx
));
1703 if (return_size
> HARD_REG_SIZE
&& return_size
<= 2 * HARD_REG_SIZE
)
1708 /* Pop any 2 byte pseudo hard registers that we saved. */
1709 for (regno
= SOFT_REG_LAST
; regno
>= SOFT_REG_FIRST
; regno
--)
1711 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1713 emit_move_after_reload (gen_rtx_REG (HImode
, regno
),
1714 stack_pop_word
, scratch
);
1718 /* de-allocate auto variables */
1719 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1721 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1722 stack_pointer_rtx
, GEN_INT (size
)));
1724 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1728 insn
= gen_rtx_PARALLEL
1731 gen_rtx_SET (VOIDmode
,
1733 gen_rtx_PLUS (HImode
,
1736 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1743 for (i
= 2; i
<= size
; i
+= 2)
1744 emit_move_after_reload (scratch
, stack_pop_word
, scratch
);
1746 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1747 stack_pointer_rtx
, const1_rtx
));
1750 /* For an interrupt handler, restore ZTMP, ZREG and XYREG. */
1751 if (current_function_interrupt
)
1753 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1754 stack_pop_word
, scratch
);
1755 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
1756 stack_pop_word
, scratch
);
1757 emit_move_after_reload (m68hc11_soft_tmp_reg
, stack_pop_word
, scratch
);
1760 /* Restore previous frame pointer. */
1761 if (frame_pointer_needed
)
1762 emit_move_after_reload (hard_frame_pointer_rtx
, stack_pop_word
, scratch
);
1764 /* If the trap handler returns some value, copy the value
1765 in D, X onto the stack so that the rti will pop the return value
1767 else if (current_function_trap
&& return_size
!= 0)
1769 rtx addr_reg
= stack_pointer_rtx
;
1773 emit_move_after_reload (scratch
, stack_pointer_rtx
, 0);
1776 emit_move_after_reload (gen_rtx_MEM (HImode
,
1777 gen_rtx_PLUS (HImode
, addr_reg
,
1778 const1_rtx
)), d_reg
, 0);
1779 if (return_size
> HARD_REG_SIZE
)
1780 emit_move_after_reload (gen_rtx_MEM (HImode
,
1781 gen_rtx_PLUS (HImode
, addr_reg
,
1782 GEN_INT (3))), ix_reg
, 0);
1785 emit_jump_insn (gen_return ());
1789 /* Low and High part extraction for 68HC11. These routines are
1790 similar to gen_lowpart and gen_highpart but they have been
1791 fixed to work for constants and 68HC11 specific registers. */
1794 m68hc11_gen_lowpart (enum machine_mode mode
, rtx x
)
1796 /* We assume that the low part of an auto-inc mode is the same with
1797 the mode changed and that the caller split the larger mode in the
1799 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1801 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1804 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1805 floating-point constant. A CONST_DOUBLE is used whenever the
1806 constant requires more than one word in order to be adequately
1808 if (GET_CODE (x
) == CONST_DOUBLE
)
1812 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1816 if (GET_MODE (x
) == SFmode
)
1818 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1819 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[0]);
1825 split_double (x
, &first
, &second
);
1829 return GEN_INT (l
[0]);
1831 return gen_int_mode (l
[0], HImode
);
1835 l
[0] = CONST_DOUBLE_LOW (x
);
1838 return GEN_INT (l
[0]);
1839 else if (mode
== HImode
&& GET_MODE (x
) == SFmode
)
1840 return gen_int_mode (l
[0], HImode
);
1845 if (mode
== QImode
&& D_REG_P (x
))
1846 return gen_rtx_REG (mode
, HARD_B_REGNUM
);
1848 /* gen_lowpart crashes when it is called with a SUBREG. */
1849 if (GET_CODE (x
) == SUBREG
&& SUBREG_BYTE (x
) != 0)
1852 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 4);
1853 else if (mode
== HImode
)
1854 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 2);
1858 x
= gen_lowpart (mode
, x
);
1860 /* Return a different rtx to avoid to share it in several insns
1861 (when used by a split pattern). Sharing addresses within
1862 a MEM breaks the Z register replacement (and reloading). */
1863 if (GET_CODE (x
) == MEM
)
1869 m68hc11_gen_highpart (enum machine_mode mode
, rtx x
)
1871 /* We assume that the high part of an auto-inc mode is the same with
1872 the mode changed and that the caller split the larger mode in the
1874 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1876 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1879 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1880 floating-point constant. A CONST_DOUBLE is used whenever the
1881 constant requires more than one word in order to be adequately
1883 if (GET_CODE (x
) == CONST_DOUBLE
)
1887 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1891 if (GET_MODE (x
) == SFmode
)
1893 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1894 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[1]);
1900 split_double (x
, &first
, &second
);
1904 return GEN_INT (l
[1]);
1906 return gen_int_mode ((l
[1] >> 16), HImode
);
1910 l
[1] = CONST_DOUBLE_HIGH (x
);
1914 return GEN_INT (l
[1]);
1915 else if (mode
== HImode
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1916 return gen_int_mode ((l
[0] >> 16), HImode
);
1920 if (GET_CODE (x
) == CONST_INT
)
1922 HOST_WIDE_INT val
= INTVAL (x
);
1926 return gen_int_mode (val
>> 8, QImode
);
1928 else if (mode
== HImode
)
1930 return gen_int_mode (val
>> 16, HImode
);
1932 else if (mode
== SImode
)
1934 return gen_int_mode (val
>> 32, SImode
);
1937 if (mode
== QImode
&& D_REG_P (x
))
1938 return gen_rtx_REG (mode
, HARD_A_REGNUM
);
1940 /* There is no way in GCC to represent the upper part of a word register.
1941 To obtain the 8-bit upper part of a soft register, we change the
1942 reg into a mem rtx. This is possible because they are physically
1943 located in memory. There is no offset because we are big-endian. */
1944 if (mode
== QImode
&& S_REG_P (x
))
1948 /* Avoid the '*' for direct addressing mode when this
1949 addressing mode is disabled. */
1950 pos
= TARGET_NO_DIRECT_MODE
? 1 : 0;
1951 return gen_rtx_MEM (QImode
,
1952 gen_rtx_SYMBOL_REF (Pmode
,
1953 ®_names
[REGNO (x
)][pos
]));
1956 /* gen_highpart crashes when it is called with a SUBREG. */
1957 if (GET_CODE (x
) == SUBREG
)
1959 return gen_rtx_SUBREG (mode
, XEXP (x
, 0), XEXP (x
, 1));
1961 if (GET_CODE (x
) == REG
)
1963 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1964 return gen_rtx_REG (mode
, REGNO (x
));
1966 return gen_rtx_SUBREG (mode
, x
, 0);
1969 if (GET_CODE (x
) == MEM
)
1971 x
= change_address (x
, mode
, 0);
1973 /* Return a different rtx to avoid to share it in several insns
1974 (when used by a split pattern). Sharing addresses within
1975 a MEM breaks the Z register replacement (and reloading). */
1976 if (GET_CODE (x
) == MEM
)
1984 /* Obscure register manipulation. */
1986 /* Finds backward in the instructions to see if register 'reg' is
1987 dead. This is used when generating code to see if we can use 'reg'
1988 as a scratch register. This allows us to choose a better generation
1989 of code when we know that some register dies or can be clobbered. */
1992 dead_register_here (rtx x
, rtx reg
)
1998 x_reg
= gen_rtx_REG (SImode
, HARD_X_REGNUM
);
2002 for (p
= PREV_INSN (x
); p
&& GET_CODE (p
) != CODE_LABEL
; p
= PREV_INSN (p
))
2009 if (GET_CODE (body
) == CALL_INSN
)
2011 if (GET_CODE (body
) == JUMP_INSN
)
2014 if (GET_CODE (body
) == SET
)
2016 rtx dst
= XEXP (body
, 0);
2018 if (GET_CODE (dst
) == REG
&& REGNO (dst
) == REGNO (reg
))
2020 if (x_reg
&& rtx_equal_p (dst
, x_reg
))
2023 if (find_regno_note (p
, REG_DEAD
, REGNO (reg
)))
2026 else if (reg_mentioned_p (reg
, p
)
2027 || (x_reg
&& reg_mentioned_p (x_reg
, p
)))
2031 /* Scan forward to see if the register is set in some insns and never
2033 for (p
= x
/*NEXT_INSN (x) */ ; p
; p
= NEXT_INSN (p
))
2037 if (GET_CODE (p
) == CODE_LABEL
2038 || GET_CODE (p
) == JUMP_INSN
2039 || GET_CODE (p
) == CALL_INSN
|| GET_CODE (p
) == BARRIER
)
2042 if (GET_CODE (p
) != INSN
)
2046 if (GET_CODE (body
) == SET
)
2048 rtx src
= XEXP (body
, 1);
2049 rtx dst
= XEXP (body
, 0);
2051 if (GET_CODE (dst
) == REG
2052 && REGNO (dst
) == REGNO (reg
) && !reg_mentioned_p (reg
, src
))
2056 /* Register is used (may be in source or in dest). */
2057 if (reg_mentioned_p (reg
, p
)
2058 || (x_reg
!= 0 && GET_MODE (p
) == SImode
2059 && reg_mentioned_p (x_reg
, p
)))
2062 return p
== 0 ? 1 : 0;
2066 /* Code generation operations called from machine description file. */
2068 /* Print the name of register 'regno' in the assembly file. */
2070 asm_print_register (FILE *file
, int regno
)
2072 const char *name
= reg_names
[regno
];
2074 if (TARGET_NO_DIRECT_MODE
&& name
[0] == '*')
2077 fprintf (file
, "%s", name
);
2080 /* A C compound statement to output to stdio stream STREAM the
2081 assembler syntax for an instruction operand X. X is an RTL
2084 CODE is a value that can be used to specify one of several ways
2085 of printing the operand. It is used when identical operands
2086 must be printed differently depending on the context. CODE
2087 comes from the `%' specification that was used to request
2088 printing of the operand. If the specification was just `%DIGIT'
2089 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2090 is the ASCII code for LTR.
2092 If X is a register, this macro should print the register's name.
2093 The names can be found in an array `reg_names' whose type is
2094 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2096 When the machine description has a specification `%PUNCT' (a `%'
2097 followed by a punctuation character), this macro is called with
2098 a null pointer for X and the punctuation character for CODE.
2100 The M68HC11 specific codes are:
2102 'b' for the low part of the operand.
2103 'h' for the high part of the operand
2104 The 'b' or 'h' modifiers have no effect if the operand has
2105 the QImode and is not a S_REG_P (soft register). If the
2106 operand is a hard register, these two modifiers have no effect.
2107 't' generate the temporary scratch register. The operand is
2109 'T' generate the low-part temporary scratch register. The operand is
2113 print_operand (FILE *file
, rtx op
, int letter
)
2117 asm_print_register (file
, SOFT_TMP_REGNUM
);
2120 else if (letter
== 'T')
2122 asm_print_register (file
, SOFT_TMP_REGNUM
);
2123 fprintf (file
, "+1");
2126 else if (letter
== '#')
2128 asm_fprintf (file
, "%I");
2131 if (GET_CODE (op
) == REG
)
2133 if (letter
== 'b' && S_REG_P (op
))
2135 asm_print_register (file
, REGNO (op
));
2136 fprintf (file
, "+1");
2138 else if (letter
== 'b' && D_REG_P (op
))
2140 asm_print_register (file
, HARD_B_REGNUM
);
2144 asm_print_register (file
, REGNO (op
));
2149 if (GET_CODE (op
) == SYMBOL_REF
&& (letter
== 'b' || letter
== 'h'))
2152 asm_fprintf (file
, "%I%%lo(");
2154 asm_fprintf (file
, "%I%%hi(");
2156 output_addr_const (file
, op
);
2157 fprintf (file
, ")");
2161 /* Get the low or high part of the operand when 'b' or 'h' modifiers
2162 are specified. If we already have a QImode, there is nothing to do. */
2163 if (GET_MODE (op
) == HImode
|| GET_MODE (op
) == VOIDmode
)
2167 op
= m68hc11_gen_lowpart (QImode
, op
);
2169 else if (letter
== 'h')
2171 op
= m68hc11_gen_highpart (QImode
, op
);
2175 if (GET_CODE (op
) == MEM
)
2177 rtx base
= XEXP (op
, 0);
2178 switch (GET_CODE (base
))
2183 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (op
)));
2184 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2193 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2194 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2195 fprintf (file
, "-");
2204 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2205 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2206 fprintf (file
, "+");
2215 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (op
)));
2216 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2225 fprintf (file
, "[");
2226 print_operand_address (file
, XEXP (base
, 0));
2227 fprintf (file
, "]");
2234 if (m68hc11_page0_symbol_p (base
))
2235 fprintf (file
, "*");
2237 output_address (base
);
2241 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2246 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2247 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2248 asm_fprintf (file
, "%I0x%lx", l
);
2250 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2254 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (op
),
2255 sizeof (dstr
), 0, 1);
2256 asm_fprintf (file
, "%I0r%s", dstr
);
2260 int need_parenthesize
= 0;
2263 asm_fprintf (file
, "%I");
2265 need_parenthesize
= must_parenthesize (op
);
2267 if (need_parenthesize
)
2268 fprintf (file
, "(");
2270 output_addr_const (file
, op
);
2271 if (need_parenthesize
)
2272 fprintf (file
, ")");
2276 /* Returns true if the operand 'op' must be printed with parenthesis
2277 around it. This must be done only if there is a symbol whose name
2278 is a processor register. */
2280 must_parenthesize (rtx op
)
2284 switch (GET_CODE (op
))
2287 name
= XSTR (op
, 0);
2288 /* Avoid a conflict between symbol name and a possible
2290 return (strcasecmp (name
, "a") == 0
2291 || strcasecmp (name
, "b") == 0
2292 || strcasecmp (name
, "d") == 0
2293 || strcasecmp (name
, "x") == 0
2294 || strcasecmp (name
, "y") == 0
2295 || strcasecmp (name
, "ix") == 0
2296 || strcasecmp (name
, "iy") == 0
2297 || strcasecmp (name
, "pc") == 0
2298 || strcasecmp (name
, "sp") == 0
2299 || strcasecmp (name
, "ccr") == 0) ? 1 : 0;
2303 return must_parenthesize (XEXP (op
, 0))
2304 || must_parenthesize (XEXP (op
, 1));
2310 return must_parenthesize (XEXP (op
, 0));
2321 /* A C compound statement to output to stdio stream STREAM the
2322 assembler syntax for an instruction operand that is a memory
2323 reference whose address is ADDR. ADDR is an RTL expression. */
2326 print_operand_address (FILE *file
, rtx addr
)
2330 int need_parenthesis
= 0;
2332 switch (GET_CODE (addr
))
2335 if (!REG_P (addr
) || !REG_OK_FOR_BASE_STRICT_P (addr
))
2338 fprintf (file
, "0,");
2339 asm_print_register (file
, REGNO (addr
));
2343 base
= XEXP (addr
, 0);
2344 switch (GET_CODE (base
))
2349 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (addr
)));
2350 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2359 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2360 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2361 fprintf (file
, "-");
2370 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2371 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2372 fprintf (file
, "+");
2381 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (addr
)));
2382 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2389 need_parenthesis
= must_parenthesize (base
);
2390 if (need_parenthesis
)
2391 fprintf (file
, "(");
2393 output_addr_const (file
, base
);
2394 if (need_parenthesis
)
2395 fprintf (file
, ")");
2401 base
= XEXP (addr
, 0);
2402 offset
= XEXP (addr
, 1);
2403 if (!G_REG_P (base
) && G_REG_P (offset
))
2405 base
= XEXP (addr
, 1);
2406 offset
= XEXP (addr
, 0);
2408 if ((CONSTANT_ADDRESS_P (base
)) && (CONSTANT_ADDRESS_P (offset
)))
2410 need_parenthesis
= must_parenthesize (addr
);
2412 if (need_parenthesis
)
2413 fprintf (file
, "(");
2415 output_addr_const (file
, base
);
2416 fprintf (file
, "+");
2417 output_addr_const (file
, offset
);
2418 if (need_parenthesis
)
2419 fprintf (file
, ")");
2421 else if (REG_P (base
) && REG_OK_FOR_BASE_STRICT_P (base
))
2427 asm_print_register (file
, REGNO (offset
));
2428 fprintf (file
, ",");
2429 asm_print_register (file
, REGNO (base
));
2436 need_parenthesis
= must_parenthesize (offset
);
2437 if (need_parenthesis
)
2438 fprintf (file
, "(");
2440 output_addr_const (file
, offset
);
2441 if (need_parenthesis
)
2442 fprintf (file
, ")");
2443 fprintf (file
, ",");
2444 asm_print_register (file
, REGNO (base
));
2454 if (GET_CODE (addr
) == CONST_INT
2455 && INTVAL (addr
) < 0x8000 && INTVAL (addr
) >= -0x8000)
2457 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2461 need_parenthesis
= must_parenthesize (addr
);
2462 if (need_parenthesis
)
2463 fprintf (file
, "(");
2465 output_addr_const (file
, addr
);
2466 if (need_parenthesis
)
2467 fprintf (file
, ")");
2474 /* Splitting of some instructions. */
2477 m68hc11_expand_compare (enum rtx_code code
, rtx op0
, rtx op1
)
2481 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
2485 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
,
2486 gen_rtx_COMPARE (VOIDmode
, op0
, op1
)));
2487 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
2494 m68hc11_expand_compare_and_branch (enum rtx_code code
, rtx op0
, rtx op1
,
2499 switch (GET_MODE (op0
))
2503 tmp
= m68hc11_expand_compare (code
, op0
, op1
);
2504 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2505 gen_rtx_LABEL_REF (VOIDmode
, label
),
2507 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
2511 /* SCz: from i386.c */
2514 /* Don't expand the comparison early, so that we get better code
2515 when jump or whoever decides to reverse the comparison. */
2520 code
= m68hc11_prepare_fp_compare_args (code
, &m68hc11_compare_op0
,
2521 &m68hc11_compare_op1
);
2523 tmp
= gen_rtx_fmt_ee (code
, m68hc11_fp_compare_mode (code
),
2524 m68hc11_compare_op0
, m68hc11_compare_op1
);
2525 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2526 gen_rtx_LABEL_REF (VOIDmode
, label
),
2528 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
2530 use_fcomi
= ix86_use_fcomi_compare (code
);
2531 vec
= rtvec_alloc (3 + !use_fcomi
);
2532 RTVEC_ELT (vec
, 0) = tmp
;
2534 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
2536 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
2539 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
2541 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
2547 /* Expand SImode branch into multiple compare+branch. */
2549 rtx lo
[2], hi
[2], label2
;
2550 enum rtx_code code1
, code2
, code3
;
2552 if (CONSTANT_P (op0
) && !CONSTANT_P (op1
))
2557 code
= swap_condition (code
);
2559 lo
[0] = m68hc11_gen_lowpart (HImode
, op0
);
2560 lo
[1] = m68hc11_gen_lowpart (HImode
, op1
);
2561 hi
[0] = m68hc11_gen_highpart (HImode
, op0
);
2562 hi
[1] = m68hc11_gen_highpart (HImode
, op1
);
2564 /* Otherwise, if we are doing less-than, op1 is a constant and the
2565 low word is zero, then we can just examine the high word. */
2567 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
2568 && (code
== LT
|| code
== LTU
))
2570 return m68hc11_expand_compare_and_branch (code
, hi
[0], hi
[1],
2574 /* Otherwise, we need two or three jumps. */
2576 label2
= gen_label_rtx ();
2579 code2
= swap_condition (code
);
2580 code3
= unsigned_condition (code
);
2621 * if (hi(a) < hi(b)) goto true;
2622 * if (hi(a) > hi(b)) goto false;
2623 * if (lo(a) < lo(b)) goto true;
2626 if (code1
!= UNKNOWN
)
2627 m68hc11_expand_compare_and_branch (code1
, hi
[0], hi
[1], label
);
2628 if (code2
!= UNKNOWN
)
2629 m68hc11_expand_compare_and_branch (code2
, hi
[0], hi
[1], label2
);
2631 m68hc11_expand_compare_and_branch (code3
, lo
[0], lo
[1], label
);
2633 if (code2
!= UNKNOWN
)
2634 emit_label (label2
);
2644 /* Return the increment/decrement mode of a MEM if it is such.
2645 Return CONST if it is anything else. */
2647 autoinc_mode (rtx x
)
2649 if (GET_CODE (x
) != MEM
)
2653 if (GET_CODE (x
) == PRE_INC
2654 || GET_CODE (x
) == PRE_DEC
2655 || GET_CODE (x
) == POST_INC
2656 || GET_CODE (x
) == POST_DEC
)
2657 return GET_CODE (x
);
2663 m68hc11_make_autoinc_notes (rtx
*x
, void *data
)
2667 switch (GET_CODE (*x
))
2674 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_INC
, XEXP (*x
, 0),
2683 /* Split a DI, SI or HI move into several smaller move operations.
2684 The scratch register 'scratch' is used as a temporary to load
2685 store intermediate values. It must be a hard register. */
2687 m68hc11_split_move (rtx to
, rtx from
, rtx scratch
)
2689 rtx low_to
, low_from
;
2690 rtx high_to
, high_from
;
2692 enum machine_mode mode
;
2694 int autoinc_from
= autoinc_mode (from
);
2695 int autoinc_to
= autoinc_mode (to
);
2697 mode
= GET_MODE (to
);
2699 /* If the TO and FROM contain autoinc modes that are not compatible
2700 together (one pop and the other a push), we must change one to
2701 an offsetable operand and generate an appropriate add at the end. */
2702 if (TARGET_M6812
&& GET_MODE_SIZE (mode
) > 2)
2707 /* The source uses an autoinc mode which is not compatible with
2708 a split (this would result in a word swap). */
2709 if (autoinc_from
== PRE_INC
|| autoinc_from
== POST_DEC
)
2711 code
= GET_CODE (XEXP (from
, 0));
2712 reg
= XEXP (XEXP (from
, 0), 0);
2713 offset
= GET_MODE_SIZE (GET_MODE (from
));
2714 if (code
== POST_DEC
)
2717 if (code
== PRE_INC
)
2718 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2720 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2721 if (code
== POST_DEC
)
2722 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2726 /* Likewise for destination. */
2727 if (autoinc_to
== PRE_INC
|| autoinc_to
== POST_DEC
)
2729 code
= GET_CODE (XEXP (to
, 0));
2730 reg
= XEXP (XEXP (to
, 0), 0);
2731 offset
= GET_MODE_SIZE (GET_MODE (to
));
2732 if (code
== POST_DEC
)
2735 if (code
== PRE_INC
)
2736 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2738 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2739 if (code
== POST_DEC
)
2740 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2744 /* The source and destination auto increment modes must be compatible
2745 with each other: same direction. */
2746 if ((autoinc_to
!= autoinc_from
2747 && autoinc_to
!= CONST
&& autoinc_from
!= CONST
)
2748 /* The destination address register must not be used within
2749 the source operand because the source address would change
2750 while doing the copy. */
2751 || (autoinc_to
!= CONST
2752 && reg_mentioned_p (XEXP (XEXP (to
, 0), 0), from
)
2753 && !IS_STACK_PUSH (to
)))
2755 /* Must change the destination. */
2756 code
= GET_CODE (XEXP (to
, 0));
2757 reg
= XEXP (XEXP (to
, 0), 0);
2758 offset
= GET_MODE_SIZE (GET_MODE (to
));
2759 if (code
== PRE_DEC
|| code
== POST_DEC
)
2762 if (code
== PRE_DEC
|| code
== PRE_INC
)
2763 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2764 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2765 if (code
== POST_DEC
|| code
== POST_INC
)
2766 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2771 /* Likewise, the source address register must not be used within
2772 the destination operand. */
2773 if (autoinc_from
!= CONST
2774 && reg_mentioned_p (XEXP (XEXP (from
, 0), 0), to
)
2775 && !IS_STACK_PUSH (to
))
2777 /* Must change the source. */
2778 code
= GET_CODE (XEXP (from
, 0));
2779 reg
= XEXP (XEXP (from
, 0), 0);
2780 offset
= GET_MODE_SIZE (GET_MODE (from
));
2781 if (code
== PRE_DEC
|| code
== POST_DEC
)
2784 if (code
== PRE_DEC
|| code
== PRE_INC
)
2785 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2786 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2787 if (code
== POST_DEC
|| code
== POST_INC
)
2788 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2794 if (GET_MODE_SIZE (mode
) == 8)
2796 else if (GET_MODE_SIZE (mode
) == 4)
2802 && IS_STACK_PUSH (to
)
2803 && reg_mentioned_p (gen_rtx_REG (HImode
, HARD_SP_REGNUM
), from
))
2809 else if (mode
== HImode
)
2817 low_to
= m68hc11_gen_lowpart (mode
, to
);
2818 high_to
= m68hc11_gen_highpart (mode
, to
);
2820 low_from
= m68hc11_gen_lowpart (mode
, from
);
2821 high_from
= m68hc11_gen_highpart (mode
, from
);
2825 high_from
= adjust_address (high_from
, mode
, offset
);
2826 low_from
= high_from
;
2829 /* When copying with a POST_INC mode, we must copy the
2830 high part and then the low part to guarantee a correct
2833 && GET_MODE_SIZE (mode
) >= 2
2834 && autoinc_from
!= autoinc_to
2835 && (autoinc_from
== POST_INC
|| autoinc_to
== POST_INC
))
2844 low_from
= high_from
;
2849 m68hc11_split_move (low_to
, low_from
, scratch
);
2850 m68hc11_split_move (high_to
, high_from
, scratch
);
2852 else if (H_REG_P (to
) || H_REG_P (from
)
2853 || (low_from
== const0_rtx
2854 && high_from
== const0_rtx
2855 && ! push_operand (to
, GET_MODE (to
))
2856 && ! H_REG_P (scratch
))
2858 && (!m68hc11_register_indirect_p (from
, GET_MODE (from
))
2859 || m68hc11_small_indexed_indirect_p (from
,
2861 && (!m68hc11_register_indirect_p (to
, GET_MODE (to
))
2862 || m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
)))))
2864 insn
= emit_move_insn (low_to
, low_from
);
2865 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2867 insn
= emit_move_insn (high_to
, high_from
);
2868 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2872 insn
= emit_move_insn (scratch
, low_from
);
2873 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2874 insn
= emit_move_insn (low_to
, scratch
);
2875 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2877 insn
= emit_move_insn (scratch
, high_from
);
2878 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2879 insn
= emit_move_insn (high_to
, scratch
);
2880 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2885 simplify_logical (enum machine_mode mode
, int code
, rtx operand
, rtx
*result
)
2891 if (GET_CODE (operand
) != CONST_INT
)
2899 val
= INTVAL (operand
);
2903 if ((val
& mask
) == 0)
2905 if ((val
& mask
) == mask
)
2906 *result
= constm1_rtx
;
2910 if ((val
& mask
) == 0)
2911 *result
= const0_rtx
;
2912 if ((val
& mask
) == mask
)
2917 if ((val
& mask
) == 0)
2925 m68hc11_emit_logical (enum machine_mode mode
, int code
, rtx
*operands
)
2930 need_copy
= (rtx_equal_p (operands
[0], operands
[1])
2931 || rtx_equal_p (operands
[0], operands
[2])) ? 0 : 1;
2933 operands
[1] = simplify_logical (mode
, code
, operands
[1], &result
);
2934 operands
[2] = simplify_logical (mode
, code
, operands
[2], &result
);
2936 if (result
&& GET_CODE (result
) == CONST_INT
)
2938 if (!H_REG_P (operands
[0]) && operands
[3]
2939 && (INTVAL (result
) != 0 || IS_STACK_PUSH (operands
[0])))
2941 emit_move_insn (operands
[3], result
);
2942 emit_move_insn (operands
[0], operands
[3]);
2946 emit_move_insn (operands
[0], result
);
2949 else if (operands
[1] != 0 && operands
[2] != 0)
2953 if (!H_REG_P (operands
[0]) && operands
[3])
2955 emit_move_insn (operands
[3], operands
[1]);
2956 emit_insn (gen_rtx_SET (mode
,
2958 gen_rtx_fmt_ee (code
, mode
,
2959 operands
[3], operands
[2])));
2960 insn
= emit_move_insn (operands
[0], operands
[3]);
2964 insn
= emit_insn (gen_rtx_SET (mode
,
2966 gen_rtx_fmt_ee (code
, mode
,
2972 /* The logical operation is similar to a copy. */
2977 if (GET_CODE (operands
[1]) == CONST_INT
)
2982 if (!H_REG_P (operands
[0]) && !H_REG_P (src
))
2984 emit_move_insn (operands
[3], src
);
2985 emit_move_insn (operands
[0], operands
[3]);
2989 emit_move_insn (operands
[0], src
);
2995 m68hc11_split_logical (enum machine_mode mode
, int code
, rtx
*operands
)
3000 low
[0] = m68hc11_gen_lowpart (mode
, operands
[0]);
3001 low
[1] = m68hc11_gen_lowpart (mode
, operands
[1]);
3002 low
[2] = m68hc11_gen_lowpart (mode
, operands
[2]);
3004 high
[0] = m68hc11_gen_highpart (mode
, operands
[0]);
3005 high
[1] = m68hc11_gen_highpart (mode
, operands
[1]);
3006 high
[2] = m68hc11_gen_highpart (mode
, operands
[2]);
3008 low
[3] = operands
[3];
3009 high
[3] = operands
[3];
3012 m68hc11_split_logical (HImode
, code
, low
);
3013 m68hc11_split_logical (HImode
, code
, high
);
3017 m68hc11_emit_logical (mode
, code
, low
);
3018 m68hc11_emit_logical (mode
, code
, high
);
3022 /* Code generation. */
3025 m68hc11_output_swap (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
3027 /* We have to be careful with the cc_status. An address register swap
3028 is generated for some comparison. The comparison is made with D
3029 but the branch really uses the address register. See the split
3030 pattern for compare. The xgdx/xgdy preserve the flags but after
3031 the exchange, the flags will reflect to the value of X and not D.
3032 Tell this by setting the cc_status according to the cc_prev_status. */
3033 if (X_REG_P (operands
[1]) || X_REG_P (operands
[0]))
3035 if (cc_prev_status
.value1
!= 0
3036 && (D_REG_P (cc_prev_status
.value1
)
3037 || X_REG_P (cc_prev_status
.value1
)))
3039 cc_status
= cc_prev_status
;
3040 if (D_REG_P (cc_status
.value1
))
3041 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3044 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3050 output_asm_insn ("xgdx", operands
);
3054 if (cc_prev_status
.value1
!= 0
3055 && (D_REG_P (cc_prev_status
.value1
)
3056 || Y_REG_P (cc_prev_status
.value1
)))
3058 cc_status
= cc_prev_status
;
3059 if (D_REG_P (cc_status
.value1
))
3060 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3063 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3069 output_asm_insn ("xgdy", operands
);
3073 /* Returns 1 if the next insn after 'insn' is a test of the register 'reg'.
3074 This is used to decide whether a move that set flags should be used
3077 next_insn_test_reg (rtx insn
, rtx reg
)
3081 insn
= next_nonnote_insn (insn
);
3082 if (GET_CODE (insn
) != INSN
)
3085 body
= PATTERN (insn
);
3086 if (sets_cc0_p (body
) != 1)
3089 if (rtx_equal_p (XEXP (body
, 1), reg
) == 0)
3095 /* Generate the code to move a 16-bit operand into another one. */
3098 m68hc11_gen_movhi (rtx insn
, rtx
*operands
)
3102 /* Move a register or memory to the same location.
3103 This is possible because such insn can appear
3104 in a non-optimizing mode. */
3105 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3107 cc_status
= cc_prev_status
;
3113 if (IS_STACK_PUSH (operands
[0]) && H_REG_P (operands
[1]))
3115 cc_status
= cc_prev_status
;
3116 switch (REGNO (operands
[1]))
3121 output_asm_insn ("psh%1", operands
);
3123 case HARD_SP_REGNUM
:
3124 output_asm_insn ("sts\t2,-sp", operands
);
3131 if (IS_STACK_POP (operands
[1]) && H_REG_P (operands
[0]))
3133 cc_status
= cc_prev_status
;
3134 switch (REGNO (operands
[0]))
3139 output_asm_insn ("pul%0", operands
);
3146 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3148 m68hc11_notice_keep_cc (operands
[0]);
3149 output_asm_insn ("tfr\t%1,%0", operands
);
3151 else if (H_REG_P (operands
[0]))
3153 if (SP_REG_P (operands
[0]))
3154 output_asm_insn ("lds\t%1", operands
);
3156 output_asm_insn ("ld%0\t%1", operands
);
3158 else if (H_REG_P (operands
[1]))
3160 if (SP_REG_P (operands
[1]))
3161 output_asm_insn ("sts\t%0", operands
);
3163 output_asm_insn ("st%1\t%0", operands
);
3167 rtx from
= operands
[1];
3168 rtx to
= operands
[0];
3170 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3171 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3172 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3173 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3179 ops
[0] = operands
[2];
3182 m68hc11_gen_movhi (insn
, ops
);
3184 ops
[1] = operands
[2];
3185 m68hc11_gen_movhi (insn
, ops
);
3189 /* !!!! SCz wrong here. */
3190 fatal_insn ("move insn not handled", insn
);
3195 if (GET_CODE (from
) == CONST_INT
&& INTVAL (from
) == 0)
3197 output_asm_insn ("clr\t%h0", operands
);
3198 output_asm_insn ("clr\t%b0", operands
);
3202 m68hc11_notice_keep_cc (operands
[0]);
3203 output_asm_insn ("movw\t%1,%0", operands
);
3210 if (IS_STACK_POP (operands
[1]) && H_REG_P (operands
[0]))
3212 cc_status
= cc_prev_status
;
3213 switch (REGNO (operands
[0]))
3217 output_asm_insn ("pul%0", operands
);
3220 output_asm_insn ("pula", operands
);
3221 output_asm_insn ("pulb", operands
);
3228 /* Some moves to a hard register are special. Not all of them
3229 are really supported and we have to use a temporary
3230 location to provide them (either the stack of a temp var). */
3231 if (H_REG_P (operands
[0]))
3233 switch (REGNO (operands
[0]))
3236 if (X_REG_P (operands
[1]))
3238 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3240 m68hc11_output_swap (insn
, operands
);
3242 else if (next_insn_test_reg (insn
, operands
[0]))
3244 output_asm_insn ("stx\t%t0\n\tldd\t%t0", operands
);
3248 m68hc11_notice_keep_cc (operands
[0]);
3249 output_asm_insn ("pshx\n\tpula\n\tpulb", operands
);
3252 else if (Y_REG_P (operands
[1]))
3254 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3256 m68hc11_output_swap (insn
, operands
);
3260 /* %t means *ZTMP scratch register. */
3261 output_asm_insn ("sty\t%t1", operands
);
3262 output_asm_insn ("ldd\t%t1", operands
);
3265 else if (SP_REG_P (operands
[1]))
3270 if (optimize
== 0 || dead_register_here (insn
, ix_reg
) == 0)
3271 output_asm_insn ("xgdx", operands
);
3272 output_asm_insn ("tsx", operands
);
3273 output_asm_insn ("xgdx", operands
);
3275 else if (IS_STACK_POP (operands
[1]))
3277 output_asm_insn ("pula\n\tpulb", operands
);
3279 else if (GET_CODE (operands
[1]) == CONST_INT
3280 && INTVAL (operands
[1]) == 0)
3282 output_asm_insn ("clra\n\tclrb", operands
);
3286 output_asm_insn ("ldd\t%1", operands
);
3291 if (D_REG_P (operands
[1]))
3293 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3295 m68hc11_output_swap (insn
, operands
);
3297 else if (next_insn_test_reg (insn
, operands
[0]))
3299 output_asm_insn ("std\t%t0\n\tldx\t%t0", operands
);
3303 m68hc11_notice_keep_cc (operands
[0]);
3304 output_asm_insn ("pshb", operands
);
3305 output_asm_insn ("psha", operands
);
3306 output_asm_insn ("pulx", operands
);
3309 else if (Y_REG_P (operands
[1]))
3311 /* When both D and Y are dead, use the sequence xgdy, xgdx
3312 to move Y into X. The D and Y registers are modified. */
3313 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
)
3314 && dead_register_here (insn
, d_reg
))
3316 output_asm_insn ("xgdy", operands
);
3317 output_asm_insn ("xgdx", operands
);
3320 else if (!optimize_size
)
3322 output_asm_insn ("sty\t%t1", operands
);
3323 output_asm_insn ("ldx\t%t1", operands
);
3328 output_asm_insn ("pshy", operands
);
3329 output_asm_insn ("pulx", operands
);
3332 else if (SP_REG_P (operands
[1]))
3334 /* tsx, tsy preserve the flags */
3335 cc_status
= cc_prev_status
;
3336 output_asm_insn ("tsx", operands
);
3340 output_asm_insn ("ldx\t%1", operands
);
3345 if (D_REG_P (operands
[1]))
3347 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3349 m68hc11_output_swap (insn
, operands
);
3353 output_asm_insn ("std\t%t1", operands
);
3354 output_asm_insn ("ldy\t%t1", operands
);
3357 else if (X_REG_P (operands
[1]))
3359 /* When both D and X are dead, use the sequence xgdx, xgdy
3360 to move X into Y. The D and X registers are modified. */
3361 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
)
3362 && dead_register_here (insn
, d_reg
))
3364 output_asm_insn ("xgdx", operands
);
3365 output_asm_insn ("xgdy", operands
);
3368 else if (!optimize_size
)
3370 output_asm_insn ("stx\t%t1", operands
);
3371 output_asm_insn ("ldy\t%t1", operands
);
3376 output_asm_insn ("pshx", operands
);
3377 output_asm_insn ("puly", operands
);
3380 else if (SP_REG_P (operands
[1]))
3382 /* tsx, tsy preserve the flags */
3383 cc_status
= cc_prev_status
;
3384 output_asm_insn ("tsy", operands
);
3388 output_asm_insn ("ldy\t%1", operands
);
3392 case HARD_SP_REGNUM
:
3393 if (D_REG_P (operands
[1]))
3395 m68hc11_notice_keep_cc (operands
[0]);
3396 output_asm_insn ("xgdx", operands
);
3397 output_asm_insn ("txs", operands
);
3398 output_asm_insn ("xgdx", operands
);
3400 else if (X_REG_P (operands
[1]))
3402 /* tys, txs preserve the flags */
3403 cc_status
= cc_prev_status
;
3404 output_asm_insn ("txs", operands
);
3406 else if (Y_REG_P (operands
[1]))
3408 /* tys, txs preserve the flags */
3409 cc_status
= cc_prev_status
;
3410 output_asm_insn ("tys", operands
);
3414 /* lds sets the flags but the des does not. */
3416 output_asm_insn ("lds\t%1", operands
);
3417 output_asm_insn ("des", operands
);
3422 fatal_insn ("invalid register in the move instruction", insn
);
3427 if (SP_REG_P (operands
[1]) && REG_P (operands
[0])
3428 && REGNO (operands
[0]) == HARD_FRAME_POINTER_REGNUM
)
3430 output_asm_insn ("sts\t%0", operands
);
3434 if (IS_STACK_PUSH (operands
[0]) && H_REG_P (operands
[1]))
3436 cc_status
= cc_prev_status
;
3437 switch (REGNO (operands
[1]))
3441 output_asm_insn ("psh%1", operands
);
3444 output_asm_insn ("pshb", operands
);
3445 output_asm_insn ("psha", operands
);
3453 /* Operand 1 must be a hard register. */
3454 if (!H_REG_P (operands
[1]))
3456 fatal_insn ("invalid operand in the instruction", insn
);
3459 reg
= REGNO (operands
[1]);
3463 output_asm_insn ("std\t%0", operands
);
3467 output_asm_insn ("stx\t%0", operands
);
3471 output_asm_insn ("sty\t%0", operands
);
3474 case HARD_SP_REGNUM
:
3478 if (REG_P (operands
[0]) && REGNO (operands
[0]) == SOFT_TMP_REGNUM
)
3480 output_asm_insn ("pshx", operands
);
3481 output_asm_insn ("tsx", operands
);
3482 output_asm_insn ("inx", operands
);
3483 output_asm_insn ("inx", operands
);
3484 output_asm_insn ("stx\t%0", operands
);
3485 output_asm_insn ("pulx", operands
);
3488 else if (reg_mentioned_p (ix_reg
, operands
[0]))
3490 output_asm_insn ("sty\t%t0", operands
);
3491 output_asm_insn ("tsy", operands
);
3492 output_asm_insn ("sty\t%0", operands
);
3493 output_asm_insn ("ldy\t%t0", operands
);
3497 output_asm_insn ("stx\t%t0", operands
);
3498 output_asm_insn ("tsx", operands
);
3499 output_asm_insn ("stx\t%0", operands
);
3500 output_asm_insn ("ldx\t%t0", operands
);
3506 fatal_insn ("invalid register in the move instruction", insn
);
3512 m68hc11_gen_movqi (rtx insn
, rtx
*operands
)
3514 /* Move a register or memory to the same location.
3515 This is possible because such insn can appear
3516 in a non-optimizing mode. */
3517 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3519 cc_status
= cc_prev_status
;
3526 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3528 m68hc11_notice_keep_cc (operands
[0]);
3529 output_asm_insn ("tfr\t%1,%0", operands
);
3531 else if (H_REG_P (operands
[0]))
3533 if (Q_REG_P (operands
[0]))
3534 output_asm_insn ("lda%0\t%b1", operands
);
3535 else if (D_REG_P (operands
[0]))
3536 output_asm_insn ("ldab\t%b1", operands
);
3540 else if (H_REG_P (operands
[1]))
3542 if (Q_REG_P (operands
[1]))
3543 output_asm_insn ("sta%1\t%b0", operands
);
3544 else if (D_REG_P (operands
[1]))
3545 output_asm_insn ("stab\t%b0", operands
);
3551 rtx from
= operands
[1];
3552 rtx to
= operands
[0];
3554 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3555 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3556 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3557 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3563 ops
[0] = operands
[2];
3566 m68hc11_gen_movqi (insn
, ops
);
3568 ops
[1] = operands
[2];
3569 m68hc11_gen_movqi (insn
, ops
);
3573 /* !!!! SCz wrong here. */
3574 fatal_insn ("move insn not handled", insn
);
3579 if (GET_CODE (from
) == CONST_INT
&& INTVAL (from
) == 0)
3581 output_asm_insn ("clr\t%b0", operands
);
3585 m68hc11_notice_keep_cc (operands
[0]);
3586 output_asm_insn ("movb\t%b1,%b0", operands
);
3594 if (H_REG_P (operands
[0]))
3596 switch (REGNO (operands
[0]))
3600 if (X_REG_P (operands
[1]))
3602 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3604 m68hc11_output_swap (insn
, operands
);
3608 output_asm_insn ("stx\t%t1", operands
);
3609 output_asm_insn ("ldab\t%T0", operands
);
3612 else if (Y_REG_P (operands
[1]))
3614 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3616 m68hc11_output_swap (insn
, operands
);
3620 output_asm_insn ("sty\t%t1", operands
);
3621 output_asm_insn ("ldab\t%T0", operands
);
3624 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3625 && !DA_REG_P (operands
[1]))
3627 output_asm_insn ("ldab\t%b1", operands
);
3629 else if (DA_REG_P (operands
[1]))
3631 output_asm_insn ("tab", operands
);
3635 cc_status
= cc_prev_status
;
3641 if (X_REG_P (operands
[1]))
3643 output_asm_insn ("stx\t%t1", operands
);
3644 output_asm_insn ("ldaa\t%T0", operands
);
3646 else if (Y_REG_P (operands
[1]))
3648 output_asm_insn ("sty\t%t1", operands
);
3649 output_asm_insn ("ldaa\t%T0", operands
);
3651 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3652 && !DA_REG_P (operands
[1]))
3654 output_asm_insn ("ldaa\t%b1", operands
);
3656 else if (!DA_REG_P (operands
[1]))
3658 output_asm_insn ("tba", operands
);
3662 cc_status
= cc_prev_status
;
3667 if (D_REG_P (operands
[1]))
3669 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3671 m68hc11_output_swap (insn
, operands
);
3675 output_asm_insn ("stab\t%T1", operands
);
3676 output_asm_insn ("ldx\t%t1", operands
);
3680 else if (Y_REG_P (operands
[1]))
3682 output_asm_insn ("sty\t%t0", operands
);
3683 output_asm_insn ("ldx\t%t0", operands
);
3685 else if (GET_CODE (operands
[1]) == CONST_INT
)
3687 output_asm_insn ("ldx\t%1", operands
);
3689 else if (dead_register_here (insn
, d_reg
))
3691 output_asm_insn ("ldab\t%b1", operands
);
3692 output_asm_insn ("xgdx", operands
);
3694 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3696 output_asm_insn ("xgdx", operands
);
3697 output_asm_insn ("ldab\t%b1", operands
);
3698 output_asm_insn ("xgdx", operands
);
3702 output_asm_insn ("pshb", operands
);
3703 output_asm_insn ("ldab\t%b1", operands
);
3704 output_asm_insn ("stab\t%T1", operands
);
3705 output_asm_insn ("ldx\t%t1", operands
);
3706 output_asm_insn ("pulb", operands
);
3712 if (D_REG_P (operands
[1]))
3714 output_asm_insn ("stab\t%T1", operands
);
3715 output_asm_insn ("ldy\t%t1", operands
);
3718 else if (X_REG_P (operands
[1]))
3720 output_asm_insn ("stx\t%t1", operands
);
3721 output_asm_insn ("ldy\t%t1", operands
);
3724 else if (GET_CODE (operands
[1]) == CONST_INT
)
3726 output_asm_insn ("ldy\t%1", operands
);
3728 else if (dead_register_here (insn
, d_reg
))
3730 output_asm_insn ("ldab\t%b1", operands
);
3731 output_asm_insn ("xgdy", operands
);
3733 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3735 output_asm_insn ("xgdy", operands
);
3736 output_asm_insn ("ldab\t%b1", operands
);
3737 output_asm_insn ("xgdy", operands
);
3741 output_asm_insn ("pshb", operands
);
3742 output_asm_insn ("ldab\t%b1", operands
);
3743 output_asm_insn ("stab\t%T1", operands
);
3744 output_asm_insn ("ldy\t%t1", operands
);
3745 output_asm_insn ("pulb", operands
);
3751 fatal_insn ("invalid register in the instruction", insn
);
3755 else if (H_REG_P (operands
[1]))
3757 switch (REGNO (operands
[1]))
3761 output_asm_insn ("stab\t%b0", operands
);
3765 output_asm_insn ("staa\t%b0", operands
);
3769 output_asm_insn ("xgdx\n\tstab\t%b0\n\txgdx", operands
);
3773 output_asm_insn ("xgdy\n\tstab\t%b0\n\txgdy", operands
);
3777 fatal_insn ("invalid register in the move instruction", insn
);
3784 fatal_insn ("operand 1 must be a hard register", insn
);
3788 /* Generate the code for a ROTATE or ROTATERT on a QI or HI mode.
3789 The source and destination must be D or A and the shift must
3792 m68hc11_gen_rotate (enum rtx_code code
, rtx insn
, rtx operands
[])
3796 if (GET_CODE (operands
[2]) != CONST_INT
3797 || (!D_REG_P (operands
[0]) && !DA_REG_P (operands
[0])))
3798 fatal_insn ("invalid rotate insn", insn
);
3800 val
= INTVAL (operands
[2]);
3801 if (code
== ROTATERT
)
3802 val
= GET_MODE_SIZE (GET_MODE (operands
[0])) * BITS_PER_UNIT
- val
;
3804 if (GET_MODE (operands
[0]) != QImode
)
3807 /* Rotate by 8-bits if the shift is within [5..11]. */
3808 if (val
>= 5 && val
<= 11)
3811 output_asm_insn ("exg\ta,b", operands
);
3814 output_asm_insn ("psha", operands
);
3815 output_asm_insn ("tba", operands
);
3816 output_asm_insn ("pulb", operands
);
3821 /* If the shift is big, invert the rotation. */
3831 /* Set the carry to bit-15, but don't change D yet. */
3832 if (GET_MODE (operands
[0]) != QImode
)
3834 output_asm_insn ("asra", operands
);
3835 output_asm_insn ("rola", operands
);
3838 /* Rotate B first to move the carry to bit-0. */
3839 if (D_REG_P (operands
[0]))
3840 output_asm_insn ("rolb", operands
);
3842 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
3843 output_asm_insn ("rola", operands
);
3850 /* Set the carry to bit-8 of D. */
3851 if (GET_MODE (operands
[0]) != QImode
)
3852 output_asm_insn ("tap", operands
);
3854 /* Rotate B first to move the carry to bit-7. */
3855 if (D_REG_P (operands
[0]))
3856 output_asm_insn ("rorb", operands
);
3858 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
3859 output_asm_insn ("rora", operands
);
3866 /* Store in cc_status the expressions that the condition codes will
3867 describe after execution of an instruction whose pattern is EXP.
3868 Do not alter them if the instruction would not alter the cc's. */
3871 m68hc11_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
3873 /* recognize SET insn's. */
3874 if (GET_CODE (exp
) == SET
)
3876 /* Jumps do not alter the cc's. */
3877 if (SET_DEST (exp
) == pc_rtx
)
3880 /* NOTE: most instructions don't affect the carry bit, but the
3881 bhi/bls/bhs/blo instructions use it. This isn't mentioned in
3882 the conditions.h header. */
3884 /* Function calls clobber the cc's. */
3885 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
3890 /* Tests and compares set the cc's in predictable ways. */
3891 else if (SET_DEST (exp
) == cc0_rtx
)
3893 cc_status
.flags
= 0;
3894 cc_status
.value1
= XEXP (exp
, 0);
3895 cc_status
.value2
= XEXP (exp
, 1);
3899 /* All other instructions affect the condition codes. */
3900 cc_status
.flags
= 0;
3901 cc_status
.value1
= XEXP (exp
, 0);
3902 cc_status
.value2
= XEXP (exp
, 1);
3907 /* Default action if we haven't recognized something
3908 and returned earlier. */
3912 if (cc_status
.value2
!= 0)
3913 switch (GET_CODE (cc_status
.value2
))
3915 /* These logical operations can generate several insns.
3916 The flags are setup according to what is generated. */
3922 /* The (not ...) generates several 'com' instructions for
3923 non QImode. We have to invalidate the flags. */
3925 if (GET_MODE (cc_status
.value2
) != QImode
)
3937 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3938 cc_status
.flags
|= CC_NO_OVERFLOW
;
3941 /* The asl sets the overflow bit in such a way that this
3942 makes the flags unusable for a next compare insn. */
3946 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3947 cc_status
.flags
|= CC_NO_OVERFLOW
;
3950 /* A load/store instruction does not affect the carry. */
3955 cc_status
.flags
|= CC_NO_OVERFLOW
;
3961 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3963 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3964 cc_status
.value2
= 0;
3966 else if (cc_status
.value1
&& side_effects_p (cc_status
.value1
))
3967 cc_status
.value1
= 0;
3969 else if (cc_status
.value2
&& side_effects_p (cc_status
.value2
))
3970 cc_status
.value2
= 0;
3973 /* The current instruction does not affect the flags but changes
3974 the register 'reg'. See if the previous flags can be kept for the
3975 next instruction to avoid a comparison. */
3977 m68hc11_notice_keep_cc (rtx reg
)
3980 || cc_prev_status
.value1
== 0
3981 || rtx_equal_p (reg
, cc_prev_status
.value1
)
3982 || (cc_prev_status
.value2
3983 && reg_mentioned_p (reg
, cc_prev_status
.value2
)))
3986 cc_status
= cc_prev_status
;
3991 /* Machine Specific Reorg. */
3993 /* Z register replacement:
3995 GCC treats the Z register as an index base address register like
3996 X or Y. In general, it uses it during reload to compute the address
3997 of some operand. This helps the reload pass to avoid to fall into the
3998 register spill failure.
4000 The Z register is in the A_REGS class. In the machine description,
4001 the 'A' constraint matches it. The 'x' or 'y' constraints do not.
4003 It can appear everywhere an X or Y register can appear, except for
4004 some templates in the clobber section (when a clobber of X or Y is asked).
4005 For a given instruction, the template must ensure that no more than
4006 2 'A' registers are used. Otherwise, the register replacement is not
4009 To replace the Z register, the algorithm is not terrific:
4010 1. Insns that do not use the Z register are not changed
4011 2. When a Z register is used, we scan forward the insns to see
4012 a potential register to use: either X or Y and sometimes D.
4013 We stop when a call, a label or a branch is seen, or when we
4014 detect that both X and Y are used (probably at different times, but it does
4016 3. The register that will be used for the replacement of Z is saved
4017 in a .page0 register or on the stack. If the first instruction that
4018 used Z, uses Z as an input, the value is loaded from another .page0
4019 register. The replacement register is pushed on the stack in the
4020 rare cases where a compare insn uses Z and we couldn't find if X/Y
4022 4. The Z register is replaced in all instructions until we reach
4023 the end of the Z-block, as detected by step 2.
4024 5. If we detect that Z is still alive, its value is saved.
4025 If the replacement register is alive, its old value is loaded.
4027 The Z register can be disabled with -ffixed-z.
4037 int must_restore_reg
;
4048 int save_before_last
;
4049 int z_loaded_with_sp
;
4052 static int m68hc11_check_z_replacement (rtx
, struct replace_info
*);
4053 static void m68hc11_find_z_replacement (rtx
, struct replace_info
*);
4054 static void m68hc11_z_replacement (rtx
);
4055 static void m68hc11_reassign_regs (rtx
);
4057 int z_replacement_completed
= 0;
4059 /* Analyze the insn to find out which replacement register to use and
4060 the boundaries of the replacement.
4061 Returns 0 if we reached the last insn to be replaced, 1 if we can
4062 continue replacement in next insns. */
4065 m68hc11_check_z_replacement (rtx insn
, struct replace_info
*info
)
4067 int this_insn_uses_ix
;
4068 int this_insn_uses_iy
;
4069 int this_insn_uses_z
;
4070 int this_insn_uses_z_in_dst
;
4071 int this_insn_uses_d
;
4075 /* A call is said to clobber the Z register, we don't need
4076 to save the value of Z. We also don't need to restore
4077 the replacement register (unless it is used by the call). */
4078 if (GET_CODE (insn
) == CALL_INSN
)
4080 body
= PATTERN (insn
);
4082 info
->can_use_d
= 0;
4084 /* If the call is an indirect call with Z, we have to use the
4085 Y register because X can be used as an input (D+X).
4086 We also must not save Z nor restore Y. */
4087 if (reg_mentioned_p (z_reg
, body
))
4089 insn
= NEXT_INSN (insn
);
4092 info
->found_call
= 1;
4093 info
->must_restore_reg
= 0;
4094 info
->last
= NEXT_INSN (insn
);
4096 info
->need_save_z
= 0;
4099 if (GET_CODE (insn
) == CODE_LABEL
4100 || GET_CODE (insn
) == BARRIER
|| GET_CODE (insn
) == ASM_INPUT
)
4103 if (GET_CODE (insn
) == JUMP_INSN
)
4105 if (reg_mentioned_p (z_reg
, insn
) == 0)
4108 info
->can_use_d
= 0;
4109 info
->must_save_reg
= 0;
4110 info
->must_restore_reg
= 0;
4111 info
->need_save_z
= 0;
4112 info
->last
= NEXT_INSN (insn
);
4115 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4120 /* Z register dies here. */
4121 z_dies_here
= find_regno_note (insn
, REG_DEAD
, HARD_Z_REGNUM
) != NULL
;
4123 body
= PATTERN (insn
);
4124 if (GET_CODE (body
) == SET
)
4126 rtx src
= XEXP (body
, 1);
4127 rtx dst
= XEXP (body
, 0);
4129 /* Condition code is set here. We have to restore the X/Y and
4130 save into Z before any test/compare insn because once we save/restore
4131 we can change the condition codes. When the compare insn uses Z and
4132 we can't use X/Y, the comparison is made with the *ZREG soft register
4133 (this is supported by cmphi, cmpqi, tsthi, tstqi patterns). */
4136 if ((GET_CODE (src
) == REG
&& REGNO (src
) == HARD_Z_REGNUM
)
4137 || (GET_CODE (src
) == COMPARE
&&
4138 ((rtx_equal_p (XEXP (src
, 0), z_reg
)
4139 && H_REG_P (XEXP (src
, 1)))
4140 || (rtx_equal_p (XEXP (src
, 1), z_reg
)
4141 && H_REG_P (XEXP (src
, 0))))))
4143 if (insn
== info
->first
)
4145 info
->must_load_z
= 0;
4146 info
->must_save_reg
= 0;
4147 info
->must_restore_reg
= 0;
4148 info
->need_save_z
= 0;
4149 info
->found_call
= 1;
4150 info
->regno
= SOFT_Z_REGNUM
;
4151 info
->last
= NEXT_INSN (insn
);
4155 if (reg_mentioned_p (z_reg
, src
) == 0)
4157 info
->can_use_d
= 0;
4161 if (insn
!= info
->first
)
4164 /* Compare insn which uses Z. We have to save/restore the X/Y
4165 register without modifying the condition codes. For this
4166 we have to use a push/pop insn. */
4167 info
->must_push_reg
= 1;
4171 /* Z reg is set to something new. We don't need to load it. */
4174 if (!reg_mentioned_p (z_reg
, src
))
4176 /* Z reg is used before being set. Treat this as
4177 a new sequence of Z register replacement. */
4178 if (insn
!= info
->first
)
4182 info
->must_load_z
= 0;
4184 info
->z_set_count
++;
4185 info
->z_value
= src
;
4187 info
->z_loaded_with_sp
= 1;
4189 else if (reg_mentioned_p (z_reg
, dst
))
4190 info
->can_use_d
= 0;
4192 this_insn_uses_d
= reg_mentioned_p (d_reg
, src
)
4193 | reg_mentioned_p (d_reg
, dst
);
4194 this_insn_uses_ix
= reg_mentioned_p (ix_reg
, src
)
4195 | reg_mentioned_p (ix_reg
, dst
);
4196 this_insn_uses_iy
= reg_mentioned_p (iy_reg
, src
)
4197 | reg_mentioned_p (iy_reg
, dst
);
4198 this_insn_uses_z
= reg_mentioned_p (z_reg
, src
);
4200 /* If z is used as an address operand (like (MEM (reg z))),
4201 we can't replace it with d. */
4202 if (this_insn_uses_z
&& !Z_REG_P (src
)
4203 && !(m68hc11_arith_operator (src
, GET_MODE (src
))
4204 && Z_REG_P (XEXP (src
, 0))
4205 && !reg_mentioned_p (z_reg
, XEXP (src
, 1))
4206 && insn
== info
->first
4207 && dead_register_here (insn
, d_reg
)))
4208 info
->can_use_d
= 0;
4210 this_insn_uses_z_in_dst
= reg_mentioned_p (z_reg
, dst
);
4211 if (TARGET_M6812
&& !z_dies_here
4212 && ((this_insn_uses_z
&& side_effects_p (src
))
4213 || (this_insn_uses_z_in_dst
&& side_effects_p (dst
))))
4215 info
->need_save_z
= 1;
4216 info
->z_set_count
++;
4218 this_insn_uses_z
|= this_insn_uses_z_in_dst
;
4220 if (this_insn_uses_z
&& this_insn_uses_ix
&& this_insn_uses_iy
)
4222 fatal_insn ("registers IX, IY and Z used in the same INSN", insn
);
4225 if (this_insn_uses_d
)
4226 info
->can_use_d
= 0;
4228 /* IX and IY are used at the same time, we have to restore
4229 the value of the scratch register before this insn. */
4230 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4235 if (this_insn_uses_ix
&& X_REG_P (dst
) && GET_MODE (dst
) == SImode
)
4236 info
->can_use_d
= 0;
4238 if (info
->x_used
== 0 && this_insn_uses_ix
)
4242 /* We have a (set (REG:HI X) (REG:HI Z)).
4243 Since we use Z as the replacement register, this insn
4244 is no longer necessary. We turn it into a note. We must
4245 not reload the old value of X. */
4246 if (X_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4250 info
->need_save_z
= 0;
4253 info
->must_save_reg
= 0;
4254 info
->must_restore_reg
= 0;
4255 info
->found_call
= 1;
4256 info
->can_use_d
= 0;
4257 PUT_CODE (insn
, NOTE
);
4258 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4259 NOTE_SOURCE_FILE (insn
) = 0;
4260 info
->last
= NEXT_INSN (insn
);
4265 && (rtx_equal_p (src
, z_reg
)
4266 || (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
))))
4270 info
->need_save_z
= 0;
4273 info
->last
= NEXT_INSN (insn
);
4274 info
->must_save_reg
= 0;
4275 info
->must_restore_reg
= 0;
4277 else if (X_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4278 && !reg_mentioned_p (ix_reg
, src
))
4283 info
->need_save_z
= 0;
4285 else if (TARGET_M6812
&& side_effects_p (src
))
4288 info
->must_restore_reg
= 0;
4293 info
->save_before_last
= 1;
4295 info
->must_restore_reg
= 0;
4296 info
->last
= NEXT_INSN (insn
);
4298 else if (info
->can_use_d
)
4300 info
->last
= NEXT_INSN (insn
);
4306 if (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
)
4307 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_X_REGNUM
)
4309 info
->need_save_z
= 0;
4311 info
->last
= NEXT_INSN (insn
);
4312 info
->regno
= HARD_X_REGNUM
;
4313 info
->must_save_reg
= 0;
4314 info
->must_restore_reg
= 0;
4317 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, ix_reg
))
4319 info
->regno
= HARD_X_REGNUM
;
4320 info
->must_restore_reg
= 0;
4321 info
->must_save_reg
= 0;
4325 if (info
->y_used
== 0 && this_insn_uses_iy
)
4329 if (Y_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4333 info
->need_save_z
= 0;
4336 info
->must_save_reg
= 0;
4337 info
->must_restore_reg
= 0;
4338 info
->found_call
= 1;
4339 info
->can_use_d
= 0;
4340 PUT_CODE (insn
, NOTE
);
4341 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4342 NOTE_SOURCE_FILE (insn
) = 0;
4343 info
->last
= NEXT_INSN (insn
);
4348 && (rtx_equal_p (src
, z_reg
)
4349 || (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
))))
4354 info
->need_save_z
= 0;
4356 info
->last
= NEXT_INSN (insn
);
4357 info
->must_save_reg
= 0;
4358 info
->must_restore_reg
= 0;
4360 else if (Y_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4361 && !reg_mentioned_p (iy_reg
, src
))
4366 info
->need_save_z
= 0;
4368 else if (TARGET_M6812
&& side_effects_p (src
))
4371 info
->must_restore_reg
= 0;
4376 info
->save_before_last
= 1;
4378 info
->must_restore_reg
= 0;
4379 info
->last
= NEXT_INSN (insn
);
4381 else if (info
->can_use_d
)
4383 info
->last
= NEXT_INSN (insn
);
4390 if (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
)
4391 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_Y_REGNUM
)
4393 info
->need_save_z
= 0;
4395 info
->last
= NEXT_INSN (insn
);
4396 info
->regno
= HARD_Y_REGNUM
;
4397 info
->must_save_reg
= 0;
4398 info
->must_restore_reg
= 0;
4401 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, iy_reg
))
4403 info
->regno
= HARD_Y_REGNUM
;
4404 info
->must_restore_reg
= 0;
4405 info
->must_save_reg
= 0;
4411 info
->need_save_z
= 0;
4413 if (info
->last
== 0)
4414 info
->last
= NEXT_INSN (insn
);
4417 return info
->last
!= NULL_RTX
? 0 : 1;
4419 if (GET_CODE (body
) == PARALLEL
)
4422 char ix_clobber
= 0;
4423 char iy_clobber
= 0;
4425 this_insn_uses_iy
= 0;
4426 this_insn_uses_ix
= 0;
4427 this_insn_uses_z
= 0;
4429 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
4432 int uses_ix
, uses_iy
, uses_z
;
4434 x
= XVECEXP (body
, 0, i
);
4436 if (info
->can_use_d
&& reg_mentioned_p (d_reg
, x
))
4437 info
->can_use_d
= 0;
4439 uses_ix
= reg_mentioned_p (ix_reg
, x
);
4440 uses_iy
= reg_mentioned_p (iy_reg
, x
);
4441 uses_z
= reg_mentioned_p (z_reg
, x
);
4442 if (GET_CODE (x
) == CLOBBER
)
4444 ix_clobber
|= uses_ix
;
4445 iy_clobber
|= uses_iy
;
4446 z_clobber
|= uses_z
;
4450 this_insn_uses_ix
|= uses_ix
;
4451 this_insn_uses_iy
|= uses_iy
;
4452 this_insn_uses_z
|= uses_z
;
4454 if (uses_z
&& GET_CODE (x
) == SET
)
4456 rtx dst
= XEXP (x
, 0);
4459 info
->z_set_count
++;
4461 if (TARGET_M6812
&& uses_z
&& side_effects_p (x
))
4462 info
->need_save_z
= 1;
4465 info
->need_save_z
= 0;
4469 printf ("Uses X:%d Y:%d Z:%d CX:%d CY:%d CZ:%d\n",
4470 this_insn_uses_ix
, this_insn_uses_iy
,
4471 this_insn_uses_z
, ix_clobber
, iy_clobber
, z_clobber
);
4474 if (this_insn_uses_z
)
4475 info
->can_use_d
= 0;
4477 if (z_clobber
&& info
->first
!= insn
)
4479 info
->need_save_z
= 0;
4483 if (z_clobber
&& info
->x_used
== 0 && info
->y_used
== 0)
4485 if (this_insn_uses_z
== 0 && insn
== info
->first
)
4487 info
->must_load_z
= 0;
4489 if (dead_register_here (insn
, d_reg
))
4491 info
->regno
= HARD_D_REGNUM
;
4492 info
->must_save_reg
= 0;
4493 info
->must_restore_reg
= 0;
4495 else if (dead_register_here (insn
, ix_reg
))
4497 info
->regno
= HARD_X_REGNUM
;
4498 info
->must_save_reg
= 0;
4499 info
->must_restore_reg
= 0;
4501 else if (dead_register_here (insn
, iy_reg
))
4503 info
->regno
= HARD_Y_REGNUM
;
4504 info
->must_save_reg
= 0;
4505 info
->must_restore_reg
= 0;
4507 if (info
->regno
>= 0)
4509 info
->last
= NEXT_INSN (insn
);
4512 if (this_insn_uses_ix
== 0)
4514 info
->regno
= HARD_X_REGNUM
;
4515 info
->must_save_reg
= 1;
4516 info
->must_restore_reg
= 1;
4518 else if (this_insn_uses_iy
== 0)
4520 info
->regno
= HARD_Y_REGNUM
;
4521 info
->must_save_reg
= 1;
4522 info
->must_restore_reg
= 1;
4526 info
->regno
= HARD_D_REGNUM
;
4527 info
->must_save_reg
= 1;
4528 info
->must_restore_reg
= 1;
4530 info
->last
= NEXT_INSN (insn
);
4534 if (((info
->x_used
|| this_insn_uses_ix
) && iy_clobber
)
4535 || ((info
->y_used
|| this_insn_uses_iy
) && ix_clobber
))
4537 if (this_insn_uses_z
)
4539 if (info
->y_used
== 0 && iy_clobber
)
4541 info
->regno
= HARD_Y_REGNUM
;
4542 info
->must_save_reg
= 0;
4543 info
->must_restore_reg
= 0;
4545 if (info
->first
!= insn
4546 && ((info
->y_used
&& ix_clobber
)
4547 || (info
->x_used
&& iy_clobber
)))
4550 info
->last
= NEXT_INSN (insn
);
4551 info
->save_before_last
= 1;
4555 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4557 if (this_insn_uses_z
)
4559 fatal_insn ("cannot do z-register replacement", insn
);
4563 if (info
->x_used
== 0 && (this_insn_uses_ix
|| ix_clobber
))
4570 if (iy_clobber
|| z_clobber
)
4572 info
->last
= NEXT_INSN (insn
);
4573 info
->save_before_last
= 1;
4578 if (info
->y_used
== 0 && (this_insn_uses_iy
|| iy_clobber
))
4585 if (ix_clobber
|| z_clobber
)
4587 info
->last
= NEXT_INSN (insn
);
4588 info
->save_before_last
= 1;
4595 info
->need_save_z
= 0;
4599 if (GET_CODE (body
) == CLOBBER
)
4602 /* IX and IY are used at the same time, we have to restore
4603 the value of the scratch register before this insn. */
4604 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4608 if (info
->x_used
== 0 && this_insn_uses_ix
)
4616 if (info
->y_used
== 0 && this_insn_uses_iy
)
4630 m68hc11_find_z_replacement (rtx insn
, struct replace_info
*info
)
4634 info
->replace_reg
= NULL_RTX
;
4635 info
->must_load_z
= 1;
4636 info
->need_save_z
= 1;
4637 info
->must_save_reg
= 1;
4638 info
->must_restore_reg
= 1;
4642 info
->can_use_d
= TARGET_M6811
? 1 : 0;
4643 info
->found_call
= 0;
4647 info
->z_set_count
= 0;
4648 info
->z_value
= NULL_RTX
;
4649 info
->must_push_reg
= 0;
4650 info
->save_before_last
= 0;
4651 info
->z_loaded_with_sp
= 0;
4653 /* Scan the insn forward to find an address register that is not used.
4655 - the flow of the program changes,
4656 - when we detect that both X and Y are necessary,
4657 - when the Z register dies,
4658 - when the condition codes are set. */
4660 for (; insn
&& info
->z_died
== 0; insn
= NEXT_INSN (insn
))
4662 if (m68hc11_check_z_replacement (insn
, info
) == 0)
4666 /* May be we can use Y or X if they contain the same value as Z.
4667 This happens very often after the reload. */
4668 if (info
->z_set_count
== 1)
4670 rtx p
= info
->first
;
4675 v
= find_last_value (iy_reg
, &p
, insn
, 1);
4677 else if (info
->y_used
)
4679 v
= find_last_value (ix_reg
, &p
, insn
, 1);
4681 if (v
&& (v
!= iy_reg
&& v
!= ix_reg
) && rtx_equal_p (v
, info
->z_value
))
4684 info
->regno
= HARD_Y_REGNUM
;
4686 info
->regno
= HARD_X_REGNUM
;
4687 info
->must_load_z
= 0;
4688 info
->must_save_reg
= 0;
4689 info
->must_restore_reg
= 0;
4690 info
->found_call
= 1;
4693 if (info
->z_set_count
== 0)
4694 info
->need_save_z
= 0;
4697 info
->need_save_z
= 0;
4699 if (info
->last
== 0)
4702 if (info
->regno
>= 0)
4705 info
->replace_reg
= gen_rtx_REG (HImode
, reg
);
4707 else if (info
->can_use_d
)
4709 reg
= HARD_D_REGNUM
;
4710 info
->replace_reg
= d_reg
;
4712 else if (info
->x_used
)
4714 reg
= HARD_Y_REGNUM
;
4715 info
->replace_reg
= iy_reg
;
4719 reg
= HARD_X_REGNUM
;
4720 info
->replace_reg
= ix_reg
;
4724 if (info
->must_save_reg
&& info
->must_restore_reg
)
4726 if (insn
&& dead_register_here (insn
, info
->replace_reg
))
4728 info
->must_save_reg
= 0;
4729 info
->must_restore_reg
= 0;
4734 /* The insn uses the Z register. Find a replacement register for it
4735 (either X or Y) and replace it in the insn and the next ones until
4736 the flow changes or the replacement register is used. Instructions
4737 are emitted before and after the Z-block to preserve the value of
4738 Z and of the replacement register. */
4741 m68hc11_z_replacement (rtx insn
)
4745 struct replace_info info
;
4747 /* Find trivial case where we only need to replace z with the
4748 equivalent soft register. */
4749 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SET
)
4751 rtx body
= PATTERN (insn
);
4752 rtx src
= XEXP (body
, 1);
4753 rtx dst
= XEXP (body
, 0);
4755 if (Z_REG_P (dst
) && (H_REG_P (src
) && !SP_REG_P (src
)))
4757 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4760 else if (Z_REG_P (src
)
4761 && ((H_REG_P (dst
) && !SP_REG_P (src
)) || dst
== cc0_rtx
))
4763 XEXP (body
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4766 else if (D_REG_P (dst
)
4767 && m68hc11_arith_operator (src
, GET_MODE (src
))
4768 && D_REG_P (XEXP (src
, 0)) && Z_REG_P (XEXP (src
, 1)))
4770 XEXP (src
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4773 else if (Z_REG_P (dst
) && GET_CODE (src
) == CONST_INT
4774 && INTVAL (src
) == 0)
4776 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4777 /* Force it to be re-recognized. */
4778 INSN_CODE (insn
) = -1;
4783 m68hc11_find_z_replacement (insn
, &info
);
4785 replace_reg
= info
.replace_reg
;
4786 replace_reg_qi
= NULL_RTX
;
4788 /* Save the X register in a .page0 location. */
4789 if (info
.must_save_reg
&& !info
.must_push_reg
)
4793 if (info
.must_push_reg
&& 0)
4794 dst
= gen_rtx_MEM (HImode
,
4795 gen_rtx_PRE_DEC (HImode
,
4796 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
4798 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
4800 emit_insn_before (gen_movhi (dst
,
4801 gen_rtx_REG (HImode
, info
.regno
)), insn
);
4803 if (info
.must_load_z
&& !info
.must_push_reg
)
4805 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
4806 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
)),
4811 /* Replace all occurrence of Z by replace_reg.
4812 Stop when the last instruction to replace is reached.
4813 Also stop when we detect a change in the flow (but it's not
4814 necessary; just safeguard). */
4816 for (; insn
&& insn
!= info
.last
; insn
= NEXT_INSN (insn
))
4820 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == BARRIER
)
4823 if (GET_CODE (insn
) != INSN
4824 && GET_CODE (insn
) != CALL_INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4827 body
= PATTERN (insn
);
4828 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
4829 || GET_CODE (body
) == ASM_OPERANDS
4830 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4834 if (debug_m6811
&& reg_mentioned_p (replace_reg
, body
))
4836 printf ("Reg mentioned here...:\n");
4841 /* Stack pointer was decremented by 2 due to the push.
4842 Correct that by adding 2 to the destination. */
4843 if (info
.must_push_reg
4844 && info
.z_loaded_with_sp
&& GET_CODE (body
) == SET
)
4848 src
= SET_SRC (body
);
4849 dst
= SET_DEST (body
);
4850 if (SP_REG_P (src
) && Z_REG_P (dst
))
4851 emit_insn_after (gen_addhi3 (dst
, dst
, const2_rtx
), insn
);
4854 /* Replace any (REG:HI Z) occurrence by either X or Y. */
4855 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
4857 INSN_CODE (insn
) = -1;
4858 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
4859 fatal_insn ("cannot do z-register replacement", insn
);
4862 /* Likewise for (REG:QI Z). */
4863 if (reg_mentioned_p (z_reg
, insn
))
4865 if (replace_reg_qi
== NULL_RTX
)
4866 replace_reg_qi
= gen_rtx_REG (QImode
, REGNO (replace_reg
));
4867 validate_replace_rtx (z_reg_qi
, replace_reg_qi
, insn
);
4870 /* If there is a REG_INC note on Z, replace it with a
4871 REG_INC note on the replacement register. This is necessary
4872 to make sure that the flow pass will identify the change
4873 and it will not remove a possible insn that saves Z. */
4874 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
4876 if (REG_NOTE_KIND (note
) == REG_INC
4877 && GET_CODE (XEXP (note
, 0)) == REG
4878 && REGNO (XEXP (note
, 0)) == REGNO (z_reg
))
4880 XEXP (note
, 0) = replace_reg
;
4884 if (GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4888 /* Save Z before restoring the old value. */
4889 if (insn
&& info
.need_save_z
&& !info
.must_push_reg
)
4891 rtx save_pos_insn
= insn
;
4893 /* If Z is clobber by the last insn, we have to save its value
4894 before the last instruction. */
4895 if (info
.save_before_last
)
4896 save_pos_insn
= PREV_INSN (save_pos_insn
);
4898 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
4899 gen_rtx_REG (HImode
, info
.regno
)),
4903 if (info
.must_push_reg
&& info
.last
)
4907 body
= PATTERN (info
.last
);
4908 new_body
= gen_rtx_PARALLEL (VOIDmode
,
4910 gen_rtx_USE (VOIDmode
,
4912 gen_rtx_USE (VOIDmode
,
4913 gen_rtx_REG (HImode
,
4915 PATTERN (info
.last
) = new_body
;
4917 /* Force recognition on insn since we changed it. */
4918 INSN_CODE (insn
) = -1;
4920 if (!validate_replace_rtx (z_reg
, replace_reg
, info
.last
))
4922 fatal_insn ("invalid Z register replacement for insn", insn
);
4924 insn
= NEXT_INSN (info
.last
);
4927 /* Restore replacement register unless it was died. */
4928 if (insn
&& info
.must_restore_reg
&& !info
.must_push_reg
)
4932 if (info
.must_push_reg
&& 0)
4933 dst
= gen_rtx_MEM (HImode
,
4934 gen_rtx_POST_INC (HImode
,
4935 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
4937 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
4939 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
4946 /* Scan all the insn and re-affects some registers
4947 - The Z register (if it was used), is affected to X or Y depending
4948 on the instruction. */
4951 m68hc11_reassign_regs (rtx first
)
4955 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
4956 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
4957 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
4958 z_reg_qi
= gen_rtx_REG (QImode
, HARD_Z_REGNUM
);
4960 /* Scan all insns to replace Z by X or Y preserving the old value
4961 of X/Y and restoring it afterward. */
4963 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4967 if (GET_CODE (insn
) == CODE_LABEL
4968 || GET_CODE (insn
) == NOTE
|| GET_CODE (insn
) == BARRIER
)
4974 body
= PATTERN (insn
);
4975 if (GET_CODE (body
) == CLOBBER
|| GET_CODE (body
) == USE
)
4978 if (GET_CODE (body
) == CONST_INT
|| GET_CODE (body
) == ASM_INPUT
4979 || GET_CODE (body
) == ASM_OPERANDS
4980 || GET_CODE (body
) == UNSPEC
|| GET_CODE (body
) == UNSPEC_VOLATILE
)
4983 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
4984 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4987 /* If Z appears in this insn, replace it in the current insn
4988 and the next ones until the flow changes or we have to
4989 restore back the replacement register. */
4991 if (reg_mentioned_p (z_reg
, body
))
4993 m68hc11_z_replacement (insn
);
4998 printf ("insn not handled by Z replacement:\n");
5006 /* Machine-dependent reorg pass.
5007 Specific optimizations are defined here:
5008 - this pass changes the Z register into either X or Y
5009 (it preserves X/Y previous values in a memory slot in page0).
5011 When this pass is finished, the global variable
5012 'z_replacement_completed' is set to 2. */
5015 m68hc11_reorg (void)
5020 z_replacement_completed
= 0;
5021 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
5022 first
= get_insns ();
5024 /* Some RTX are shared at this point. This breaks the Z register
5025 replacement, unshare everything. */
5026 unshare_all_rtl_again (first
);
5028 /* Force a split of all splitable insn. This is necessary for the
5029 Z register replacement mechanism because we end up with basic insns. */
5030 split_all_insns_noflow ();
5033 z_replacement_completed
= 1;
5034 m68hc11_reassign_regs (first
);
5037 compute_bb_for_insn ();
5039 /* After some splitting, there are some opportunities for CSE pass.
5040 This happens quite often when 32-bit or above patterns are split. */
5041 if (optimize
> 0 && split_done
)
5043 reload_cse_regs (first
);
5046 /* Re-create the REG_DEAD notes. These notes are used in the machine
5047 description to use the best assembly directives. */
5050 /* Before recomputing the REG_DEAD notes, remove all of them.
5051 This is necessary because the reload_cse_regs() pass can
5052 have replaced some (MEM) with a register. In that case,
5053 the REG_DEAD that could exist for that register may become
5055 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5061 pnote
= ®_NOTES (insn
);
5064 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
)
5065 *pnote
= XEXP (*pnote
, 1);
5067 pnote
= &XEXP (*pnote
, 1);
5072 life_analysis (0, PROP_REG_INFO
| PROP_DEATH_NOTES
);
5075 z_replacement_completed
= 2;
5077 /* If optimizing, then go ahead and split insns that must be
5078 split after Z register replacement. This gives more opportunities
5079 for peephole (in particular for consecutives xgdx/xgdy). */
5081 split_all_insns_noflow ();
5083 /* Once insns are split after the z_replacement_completed == 2,
5084 we must not re-run the life_analysis. The xgdx/xgdy patterns
5085 are not recognized and the life_analysis pass removes some
5086 insns because it thinks some (SETs) are noops or made to dead
5087 stores (which is false due to the swap).
5089 Do a simple pass to eliminate the noop set that the final
5090 split could generate (because it was easier for split definition). */
5094 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5098 if (INSN_DELETED_P (insn
))
5103 /* Remove the (set (R) (R)) insns generated by some splits. */
5104 body
= PATTERN (insn
);
5105 if (GET_CODE (body
) == SET
5106 && rtx_equal_p (SET_SRC (body
), SET_DEST (body
)))
5108 PUT_CODE (insn
, NOTE
);
5109 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
5110 NOTE_SOURCE_FILE (insn
) = 0;
5117 /* Override memcpy */
5120 m68hc11_init_libfuncs (void)
5122 memcpy_libfunc
= init_one_libfunc ("__memcpy");
5123 memcmp_libfunc
= init_one_libfunc ("__memcmp");
5124 memset_libfunc
= init_one_libfunc ("__memset");
5129 /* Cost functions. */
5131 /* Cost of moving memory. */
5133 m68hc11_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
5134 int in ATTRIBUTE_UNUSED
)
5136 if (class <= H_REGS
&& class > NO_REGS
)
5138 if (GET_MODE_SIZE (mode
) <= 2)
5139 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5141 return COSTS_N_INSNS (2) + (reload_completed
| reload_in_progress
);
5145 if (GET_MODE_SIZE (mode
) <= 2)
5146 return COSTS_N_INSNS (3);
5148 return COSTS_N_INSNS (4);
5153 /* Cost of moving data from a register of class 'from' to on in class 'to'.
5154 Reload does not check the constraint of set insns when the two registers
5155 have a move cost of 2. Setting a higher cost will force reload to check
5158 m68hc11_register_move_cost (enum machine_mode mode
, enum reg_class from
,
5161 /* All costs are symmetric, so reduce cases by putting the
5162 lower number class as the destination. */
5165 enum reg_class tmp
= to
;
5166 to
= from
, from
= tmp
;
5169 return m68hc11_memory_move_cost (mode
, S_REGS
, 0);
5170 else if (from
<= S_REGS
)
5171 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5173 return COSTS_N_INSNS (2);
5177 /* Provide the costs of an addressing mode that contains ADDR.
5178 If ADDR is not a valid address, its cost is irrelevant. */
5181 m68hc11_address_cost (rtx addr
)
5185 switch (GET_CODE (addr
))
5188 /* Make the cost of hard registers and specially SP, FP small. */
5189 if (REGNO (addr
) < FIRST_PSEUDO_REGISTER
)
5206 register rtx plus0
= XEXP (addr
, 0);
5207 register rtx plus1
= XEXP (addr
, 1);
5209 if (GET_CODE (plus0
) != REG
)
5212 switch (GET_CODE (plus1
))
5215 if (INTVAL (plus1
) >= 2 * m68hc11_max_offset
5216 || INTVAL (plus1
) < m68hc11_min_offset
)
5218 else if (INTVAL (plus1
) >= m68hc11_max_offset
)
5222 if (REGNO (plus0
) < FIRST_PSEUDO_REGISTER
)
5244 if (SP_REG_P (XEXP (addr
, 0)))
5253 printf ("Address cost: %d for :", cost
);
5262 m68hc11_shift_cost (enum machine_mode mode
, rtx x
, int shift
)
5266 total
= rtx_cost (x
, SET
);
5268 total
+= m68hc11_cost
->shiftQI_const
[shift
% 8];
5269 else if (mode
== HImode
)
5270 total
+= m68hc11_cost
->shiftHI_const
[shift
% 16];
5271 else if (shift
== 8 || shift
== 16 || shift
== 32)
5272 total
+= m68hc11_cost
->shiftHI_const
[8];
5273 else if (shift
!= 0 && shift
!= 16 && shift
!= 32)
5275 total
+= m68hc11_cost
->shiftHI_const
[1] * shift
;
5278 /* For SI and others, the cost is higher. */
5279 if (GET_MODE_SIZE (mode
) > 2 && (shift
% 16) != 0)
5280 total
*= GET_MODE_SIZE (mode
) / 2;
5282 /* When optimizing for size, make shift more costly so that
5283 multiplications are preferred. */
5284 if (optimize_size
&& (shift
% 8) != 0)
5291 m68hc11_rtx_costs_1 (rtx x
, enum rtx_code code
,
5292 enum rtx_code outer_code ATTRIBUTE_UNUSED
)
5294 enum machine_mode mode
= GET_MODE (x
);
5305 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5307 return m68hc11_shift_cost (mode
, XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
5310 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5311 total
+= m68hc11_cost
->shift_var
;
5317 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5318 total
+= m68hc11_cost
->logical
;
5320 /* Logical instructions are byte instructions only. */
5321 total
*= GET_MODE_SIZE (mode
);
5326 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5327 total
+= m68hc11_cost
->add
;
5328 if (GET_MODE_SIZE (mode
) > 2)
5330 total
*= GET_MODE_SIZE (mode
) / 2;
5337 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5341 total
+= m68hc11_cost
->divQI
;
5345 total
+= m68hc11_cost
->divHI
;
5350 total
+= m68hc11_cost
->divSI
;
5356 /* mul instruction produces 16-bit result. */
5357 if (mode
== HImode
&& GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5358 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5359 return m68hc11_cost
->multQI
5360 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
)
5361 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
);
5363 /* emul instruction produces 32-bit result for 68HC12. */
5364 if (TARGET_M6812
&& mode
== SImode
5365 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5366 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5367 return m68hc11_cost
->multHI
5368 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
)
5369 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
);
5371 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5375 total
+= m68hc11_cost
->multQI
;
5379 total
+= m68hc11_cost
->multHI
;
5384 total
+= m68hc11_cost
->multSI
;
5391 extra_cost
= COSTS_N_INSNS (2);
5398 total
= extra_cost
+ rtx_cost (XEXP (x
, 0), code
);
5401 return total
+ COSTS_N_INSNS (1);
5405 return total
+ COSTS_N_INSNS (2);
5409 return total
+ COSTS_N_INSNS (4);
5411 return total
+ COSTS_N_INSNS (8);
5414 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
5415 return COSTS_N_INSNS (1);
5417 return COSTS_N_INSNS (1);
5420 return COSTS_N_INSNS (4);
5425 m68hc11_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5429 /* Constants are cheap. Moving them in registers must be avoided
5430 because most instructions do not handle two register operands. */
5436 /* Logical and arithmetic operations with a constant operand are
5437 better because they are not supported with two registers. */
5439 if (outer_code
== SET
&& x
== const0_rtx
)
5440 /* After reload, the reload_cse pass checks the cost to change
5441 a SET into a PLUS. Make const0 cheap then. */
5442 *total
= 1 - reload_completed
;
5467 *total
= m68hc11_rtx_costs_1 (x
, code
, outer_code
);
5476 /* Worker function for TARGET_ASM_FILE_START. */
5479 m68hc11_file_start (void)
5481 default_file_start ();
5483 fprintf (asm_out_file
, "\t.mode %s\n", TARGET_SHORT
? "mshort" : "mlong");
5487 /* Worker function for TARGET_ASM_CONSTRUCTOR. */
5490 m68hc11_asm_out_constructor (rtx symbol
, int priority
)
5492 default_ctor_section_asm_out_constructor (symbol
, priority
);
5493 fprintf (asm_out_file
, "\t.globl\t__do_global_ctors\n");
5496 /* Worker function for TARGET_ASM_DESTRUCTOR. */
5499 m68hc11_asm_out_destructor (rtx symbol
, int priority
)
5501 default_dtor_section_asm_out_destructor (symbol
, priority
);
5502 fprintf (asm_out_file
, "\t.globl\t__do_global_dtors\n");
5505 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5508 m68hc11_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5509 int incoming ATTRIBUTE_UNUSED
)
5511 return gen_rtx_REG (Pmode
, HARD_D_REGNUM
);
5514 /* Return true if type TYPE should be returned in memory.
5515 Blocks and data types largers than 4 bytes cannot be returned
5516 in the register (D + X = 4). */
5519 m68hc11_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
5521 if (TYPE_MODE (type
) == BLKmode
)
5523 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5524 return (size
== -1 || size
> 4);
5527 return GET_MODE_SIZE (TYPE_MODE (type
)) > 4;
5530 #include "gt-m68hc11.h"