1 /* Subroutines for code generation on Motorola 68HC11 and 68HC12.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA.
24 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
25 on gcc 2.6.3. I have used it as a starting point for this port.
26 However, this new port is a complete re-write. Its internal
27 design is completely different. The generated code is not
28 compatible with the gcc 2.6.3 port.
30 The gcc 2.6.3 port is available at:
32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
39 #include "coretypes.h"
45 #include "hard-reg-set.h"
47 #include "insn-config.h"
48 #include "conditions.h"
50 #include "insn-attr.h"
56 #include "basic-block.h"
61 #include "target-def.h"
63 static void emit_move_after_reload (rtx
, rtx
, rtx
);
64 static rtx
simplify_logical (enum machine_mode
, int, rtx
, rtx
*);
65 static void m68hc11_emit_logical (enum machine_mode
, int, rtx
*);
66 static void m68hc11_reorg (void);
67 static int go_if_legitimate_address_internal (rtx
, enum machine_mode
, int);
68 static int register_indirect_p (rtx
, enum machine_mode
, int);
69 static rtx
m68hc11_expand_compare (enum rtx_code
, rtx
, rtx
);
70 static int must_parenthesize (rtx
);
71 static int m68hc11_address_cost (rtx
);
72 static int m68hc11_shift_cost (enum machine_mode
, rtx
, int);
73 static int m68hc11_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
74 static bool m68hc11_rtx_costs (rtx
, int, int, int *);
75 static int m68hc11_auto_inc_p (rtx
);
76 static tree
m68hc11_handle_fntype_attribute (tree
*, tree
, tree
, int, bool *);
77 const struct attribute_spec m68hc11_attribute_table
[];
79 void create_regs_rtx (void);
81 static void asm_print_register (FILE *, int);
82 static void m68hc11_output_function_epilogue (FILE *, HOST_WIDE_INT
);
83 static void m68hc11_asm_out_constructor (rtx
, int);
84 static void m68hc11_asm_out_destructor (rtx
, int);
85 static void m68hc11_file_start (void);
86 static void m68hc11_encode_section_info (tree
, rtx
, int);
87 static const char *m68hc11_strip_name_encoding (const char* str
);
88 static unsigned int m68hc11_section_type_flags (tree
, const char*, int);
89 static int autoinc_mode (rtx
);
90 static int m68hc11_make_autoinc_notes (rtx
*, void *);
91 static void m68hc11_init_libfuncs (void);
92 static rtx
m68hc11_struct_value_rtx (tree
, int);
93 static bool m68hc11_return_in_memory (tree
, tree
);
95 /* Must be set to 1 to produce debug messages. */
98 extern FILE *asm_out_file
;
103 rtx m68hc11_soft_tmp_reg
;
104 static GTY(()) rtx stack_push_word
;
105 static GTY(()) rtx stack_pop_word
;
106 static GTY(()) rtx z_reg
;
107 static GTY(()) rtx z_reg_qi
;
108 static int regs_inited
= 0;
110 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
111 int current_function_interrupt
;
113 /* Set to 1 by expand_prologue() when the function is a trap handler. */
114 int current_function_trap
;
116 /* Set to 1 when the current function is placed in 68HC12 banked
117 memory and must return with rtc. */
118 int current_function_far
;
120 /* Min offset that is valid for the indirect addressing mode. */
121 HOST_WIDE_INT m68hc11_min_offset
= 0;
123 /* Max offset that is valid for the indirect addressing mode. */
124 HOST_WIDE_INT m68hc11_max_offset
= 256;
126 /* The class value for base registers. */
127 enum reg_class m68hc11_base_reg_class
= A_REGS
;
129 /* The class value for index registers. This is NO_REGS for 68HC11. */
130 enum reg_class m68hc11_index_reg_class
= NO_REGS
;
132 enum reg_class m68hc11_tmp_regs_class
= NO_REGS
;
134 /* Tables that tell whether a given hard register is valid for
135 a base or an index register. It is filled at init time depending
136 on the target processor. */
137 unsigned char m68hc11_reg_valid_for_base
[FIRST_PSEUDO_REGISTER
];
138 unsigned char m68hc11_reg_valid_for_index
[FIRST_PSEUDO_REGISTER
];
140 /* A correction offset which is applied to the stack pointer.
141 This is 1 for 68HC11 and 0 for 68HC12. */
142 int m68hc11_sp_correction
;
144 #define ADDR_STRICT 0x01 /* Accept only registers in class A_REGS */
145 #define ADDR_INCDEC 0x02 /* Post/Pre inc/dec */
146 #define ADDR_INDEXED 0x04 /* D-reg index */
147 #define ADDR_OFFSET 0x08
148 #define ADDR_INDIRECT 0x10 /* Accept (mem (mem ...)) for [n,X] */
149 #define ADDR_CONST 0x20 /* Accept const and symbol_ref */
151 int m68hc11_addr_mode
;
152 int m68hc11_mov_addr_mode
;
154 /* Comparison operands saved by the "tstxx" and "cmpxx" expand patterns. */
155 rtx m68hc11_compare_op0
;
156 rtx m68hc11_compare_op1
;
159 const struct processor_costs
*m68hc11_cost
;
161 /* Costs for a 68HC11. */
162 static const struct processor_costs m6811_cost
= {
167 /* non-constant shift */
170 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
171 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
172 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
175 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
176 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
177 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
178 COSTS_N_INSNS (2), COSTS_N_INSNS (4),
179 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (10),
180 COSTS_N_INSNS (8), COSTS_N_INSNS (6), COSTS_N_INSNS (4)
185 COSTS_N_INSNS (20 * 4),
187 COSTS_N_INSNS (20 * 16),
196 /* Costs for a 68HC12. */
197 static const struct processor_costs m6812_cost
= {
202 /* non-constant shift */
205 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
206 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
207 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
210 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
211 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
212 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
213 COSTS_N_INSNS (2), COSTS_N_INSNS (4), COSTS_N_INSNS (6),
214 COSTS_N_INSNS (8), COSTS_N_INSNS (10), COSTS_N_INSNS (8),
215 COSTS_N_INSNS (6), COSTS_N_INSNS (4)
222 COSTS_N_INSNS (3 * 4),
231 /* Machine specific options */
233 const char *m68hc11_regparm_string
;
234 const char *m68hc11_reg_alloc_order
;
235 const char *m68hc11_soft_reg_count
;
237 static int nb_soft_regs
;
239 /* Initialize the GCC target structure. */
240 #undef TARGET_ATTRIBUTE_TABLE
241 #define TARGET_ATTRIBUTE_TABLE m68hc11_attribute_table
243 #undef TARGET_ASM_ALIGNED_HI_OP
244 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
246 #undef TARGET_ASM_FUNCTION_EPILOGUE
247 #define TARGET_ASM_FUNCTION_EPILOGUE m68hc11_output_function_epilogue
249 #undef TARGET_ASM_FILE_START
250 #define TARGET_ASM_FILE_START m68hc11_file_start
251 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
252 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
254 #undef TARGET_ENCODE_SECTION_INFO
255 #define TARGET_ENCODE_SECTION_INFO m68hc11_encode_section_info
257 #undef TARGET_SECTION_TYPE_FLAGS
258 #define TARGET_SECTION_TYPE_FLAGS m68hc11_section_type_flags
260 #undef TARGET_RTX_COSTS
261 #define TARGET_RTX_COSTS m68hc11_rtx_costs
262 #undef TARGET_ADDRESS_COST
263 #define TARGET_ADDRESS_COST m68hc11_address_cost
265 #undef TARGET_MACHINE_DEPENDENT_REORG
266 #define TARGET_MACHINE_DEPENDENT_REORG m68hc11_reorg
268 #undef TARGET_INIT_LIBFUNCS
269 #define TARGET_INIT_LIBFUNCS m68hc11_init_libfuncs
271 #undef TARGET_STRUCT_VALUE_RTX
272 #define TARGET_STRUCT_VALUE_RTX m68hc11_struct_value_rtx
273 #undef TARGET_RETURN_IN_MEMORY
274 #define TARGET_RETURN_IN_MEMORY m68hc11_return_in_memory
276 #undef TARGET_STRIP_NAME_ENCODING
277 #define TARGET_STRIP_NAME_ENCODING m68hc11_strip_name_encoding
279 struct gcc_target targetm
= TARGET_INITIALIZER
;
282 m68hc11_override_options (void)
284 memset (m68hc11_reg_valid_for_index
, 0,
285 sizeof (m68hc11_reg_valid_for_index
));
286 memset (m68hc11_reg_valid_for_base
, 0, sizeof (m68hc11_reg_valid_for_base
));
288 /* Compilation with -fpic generates a wrong code. */
291 warning ("-f%s ignored for 68HC11/68HC12 (not supported)",
292 (flag_pic
> 1) ? "PIC" : "pic");
296 /* Do not enable -fweb because it breaks the 32-bit shift patterns
297 by breaking the match_dup of those patterns. The shift patterns
298 will no longer be recognized after that. */
301 /* Configure for a 68hc11 processor. */
304 /* If gcc was built for a 68hc12, invalidate that because
305 a -m68hc11 option was specified on the command line. */
306 if (TARGET_DEFAULT
!= MASK_M6811
)
307 target_flags
&= ~TARGET_DEFAULT
;
310 target_flags
&= ~(TARGET_AUTO_INC_DEC
| TARGET_MIN_MAX
);
311 m68hc11_cost
= &m6811_cost
;
312 m68hc11_min_offset
= 0;
313 m68hc11_max_offset
= 256;
314 m68hc11_index_reg_class
= NO_REGS
;
315 m68hc11_base_reg_class
= A_REGS
;
316 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
317 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
318 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
319 m68hc11_sp_correction
= 1;
320 m68hc11_tmp_regs_class
= D_REGS
;
321 m68hc11_addr_mode
= ADDR_OFFSET
;
322 m68hc11_mov_addr_mode
= 0;
323 if (m68hc11_soft_reg_count
== 0 && !TARGET_M6812
)
324 m68hc11_soft_reg_count
= "4";
327 /* Configure for a 68hc12 processor. */
330 m68hc11_cost
= &m6812_cost
;
331 m68hc11_min_offset
= -65536;
332 m68hc11_max_offset
= 65536;
333 m68hc11_index_reg_class
= D_REGS
;
334 m68hc11_base_reg_class
= A_OR_SP_REGS
;
335 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
336 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
337 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
338 m68hc11_reg_valid_for_base
[HARD_SP_REGNUM
] = 1;
339 m68hc11_reg_valid_for_index
[HARD_D_REGNUM
] = 1;
340 m68hc11_sp_correction
= 0;
341 m68hc11_tmp_regs_class
= TMP_REGS
;
342 m68hc11_addr_mode
= ADDR_INDIRECT
| ADDR_OFFSET
| ADDR_CONST
343 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
344 m68hc11_mov_addr_mode
= ADDR_OFFSET
| ADDR_CONST
345 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
346 target_flags
&= ~MASK_M6811
;
347 target_flags
|= MASK_NO_DIRECT_MODE
;
348 if (m68hc11_soft_reg_count
== 0)
349 m68hc11_soft_reg_count
= "0";
351 if (TARGET_LONG_CALLS
)
352 current_function_far
= 1;
359 m68hc11_conditional_register_usage (void)
362 int cnt
= atoi (m68hc11_soft_reg_count
);
366 if (cnt
> SOFT_REG_LAST
- SOFT_REG_FIRST
)
367 cnt
= SOFT_REG_LAST
- SOFT_REG_FIRST
;
370 for (i
= SOFT_REG_FIRST
+ cnt
; i
< SOFT_REG_LAST
; i
++)
373 call_used_regs
[i
] = 1;
376 /* For 68HC12, the Z register emulation is not necessary when the
377 frame pointer is not used. The frame pointer is eliminated and
378 replaced by the stack register (which is a BASE_REG_CLASS). */
379 if (TARGET_M6812
&& flag_omit_frame_pointer
&& optimize
)
381 fixed_regs
[HARD_Z_REGNUM
] = 1;
386 /* Reload and register operations. */
388 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
392 create_regs_rtx (void)
394 /* regs_inited = 1; */
395 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
396 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
397 d_reg
= gen_rtx_REG (HImode
, HARD_D_REGNUM
);
398 m68hc11_soft_tmp_reg
= gen_rtx_REG (HImode
, SOFT_TMP_REGNUM
);
400 stack_push_word
= gen_rtx_MEM (HImode
,
401 gen_rtx_PRE_DEC (HImode
,
402 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
403 stack_pop_word
= gen_rtx_MEM (HImode
,
404 gen_rtx_POST_INC (HImode
,
405 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
409 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
410 - 8 bit values are stored anywhere (except the SP register).
411 - 16 bit values can be stored in any register whose mode is 16
412 - 32 bit values can be stored in D, X registers or in a soft register
413 (except the last one because we need 2 soft registers)
414 - Values whose size is > 32 bit are not stored in real hard
415 registers. They may be stored in soft registers if there are
418 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
420 switch (GET_MODE_SIZE (mode
))
423 return S_REGNO_P (regno
) && nb_soft_regs
>= 4;
426 return X_REGNO_P (regno
) || (S_REGNO_P (regno
) && nb_soft_regs
>= 2);
429 return G_REGNO_P (regno
);
432 /* We have to accept a QImode in X or Y registers. Otherwise, the
433 reload pass will fail when some (SUBREG:QI (REG:HI X)) are defined
434 in the insns. Reload fails if the insn rejects the register class 'a'
435 as well as if it accepts it. Patterns that failed were
436 zero_extend_qihi2 and iorqi3. */
438 return G_REGNO_P (regno
) && !SP_REGNO_P (regno
);
446 m68hc11_hard_regno_rename_ok (int reg1
, int reg2
)
448 /* Don't accept renaming to Z register. We will replace it to
449 X,Y or D during machine reorg pass. */
450 if (reg2
== HARD_Z_REGNUM
)
453 /* Don't accept renaming D,X to Y register as the code will be bigger. */
454 if (TARGET_M6811
&& reg2
== HARD_Y_REGNUM
455 && (D_REGNO_P (reg1
) || X_REGNO_P (reg1
)))
462 preferred_reload_class (rtx operand
, enum reg_class
class)
464 enum machine_mode mode
;
466 mode
= GET_MODE (operand
);
470 printf ("Preferred reload: (class=%s): ", reg_class_names
[class]);
473 if (class == D_OR_A_OR_S_REGS
&& SP_REG_P (operand
))
474 return m68hc11_base_reg_class
;
476 if (class >= S_REGS
&& (GET_CODE (operand
) == MEM
477 || GET_CODE (operand
) == CONST_INT
))
479 /* S_REGS class must not be used. The movhi template does not
480 work to move a memory to a soft register.
481 Restrict to a hard reg. */
486 case D_OR_A_OR_S_REGS
:
492 case D_OR_SP_OR_S_REGS
:
493 class = D_OR_SP_REGS
;
495 case D_OR_Y_OR_S_REGS
:
498 case D_OR_X_OR_S_REGS
:
514 else if (class == Y_REGS
&& GET_CODE (operand
) == MEM
)
518 else if (class == A_OR_D_REGS
&& GET_MODE_SIZE (mode
) == 4)
522 else if (class >= S_REGS
&& S_REG_P (operand
))
528 case D_OR_A_OR_S_REGS
:
534 case D_OR_SP_OR_S_REGS
:
535 class = D_OR_SP_REGS
;
537 case D_OR_Y_OR_S_REGS
:
540 case D_OR_X_OR_S_REGS
:
556 else if (class >= S_REGS
)
560 printf ("Class = %s for: ", reg_class_names
[class]);
568 printf (" => class=%s\n", reg_class_names
[class]);
576 /* Return 1 if the operand is a valid indexed addressing mode.
577 For 68hc11: n,r with n in [0..255] and r in A_REGS class
578 For 68hc12: n,r no constraint on the constant, r in A_REGS class. */
580 register_indirect_p (rtx operand
, enum machine_mode mode
, int addr_mode
)
584 switch (GET_CODE (operand
))
587 if ((addr_mode
& ADDR_INDIRECT
) && GET_MODE_SIZE (mode
) <= 2)
588 return register_indirect_p (XEXP (operand
, 0), mode
,
589 addr_mode
& (ADDR_STRICT
| ADDR_OFFSET
));
596 if (addr_mode
& ADDR_INCDEC
)
597 return register_indirect_p (XEXP (operand
, 0), mode
,
598 addr_mode
& ADDR_STRICT
);
602 base
= XEXP (operand
, 0);
603 if (GET_CODE (base
) == MEM
)
606 offset
= XEXP (operand
, 1);
607 if (GET_CODE (offset
) == MEM
)
610 /* Indexed addressing mode with 2 registers. */
611 if (GET_CODE (base
) == REG
&& GET_CODE (offset
) == REG
)
613 if (!(addr_mode
& ADDR_INDEXED
))
616 addr_mode
&= ADDR_STRICT
;
617 if (REGNO_OK_FOR_BASE_P2 (REGNO (base
), addr_mode
)
618 && REGNO_OK_FOR_INDEX_P2 (REGNO (offset
), addr_mode
))
621 if (REGNO_OK_FOR_BASE_P2 (REGNO (offset
), addr_mode
)
622 && REGNO_OK_FOR_INDEX_P2 (REGNO (base
), addr_mode
))
628 if (!(addr_mode
& ADDR_OFFSET
))
631 if (GET_CODE (base
) == REG
)
633 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
636 if (!(addr_mode
& ADDR_STRICT
))
639 return REGNO_OK_FOR_BASE_P2 (REGNO (base
), 1);
642 if (GET_CODE (offset
) == REG
)
644 if (!VALID_CONSTANT_OFFSET_P (base
, mode
))
647 if (!(addr_mode
& ADDR_STRICT
))
650 return REGNO_OK_FOR_BASE_P2 (REGNO (offset
), 1);
655 return REGNO_OK_FOR_BASE_P2 (REGNO (operand
), addr_mode
& ADDR_STRICT
);
658 if (addr_mode
& ADDR_CONST
)
659 return VALID_CONSTANT_OFFSET_P (operand
, mode
);
667 /* Returns 1 if the operand fits in a 68HC11 indirect mode or in
668 a 68HC12 1-byte index addressing mode. */
670 m68hc11_small_indexed_indirect_p (rtx operand
, enum machine_mode mode
)
675 if (GET_CODE (operand
) == REG
&& reload_in_progress
676 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
677 && reg_equiv_memory_loc
[REGNO (operand
)])
679 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
680 operand
= eliminate_regs (operand
, 0, NULL_RTX
);
683 if (GET_CODE (operand
) != MEM
)
686 operand
= XEXP (operand
, 0);
687 if (CONSTANT_ADDRESS_P (operand
))
690 if (PUSH_POP_ADDRESS_P (operand
))
693 addr_mode
= m68hc11_mov_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
694 if (!register_indirect_p (operand
, mode
, addr_mode
))
697 if (TARGET_M6812
&& GET_CODE (operand
) == PLUS
698 && (reload_completed
| reload_in_progress
))
700 base
= XEXP (operand
, 0);
701 offset
= XEXP (operand
, 1);
703 /* The offset can be a symbol address and this is too big
704 for the operand constraint. */
705 if (GET_CODE (base
) != CONST_INT
&& GET_CODE (offset
) != CONST_INT
)
708 if (GET_CODE (base
) == CONST_INT
)
711 switch (GET_MODE_SIZE (mode
))
714 if (INTVAL (offset
) < -16 + 6 || INTVAL (offset
) > 15 - 6)
719 if (INTVAL (offset
) < -16 + 2 || INTVAL (offset
) > 15 - 2)
724 if (INTVAL (offset
) < -16 || INTVAL (offset
) > 15)
733 m68hc11_register_indirect_p (rtx operand
, enum machine_mode mode
)
737 if (GET_CODE (operand
) == REG
&& reload_in_progress
738 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
739 && reg_equiv_memory_loc
[REGNO (operand
)])
741 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
742 operand
= eliminate_regs (operand
, 0, NULL_RTX
);
744 if (GET_CODE (operand
) != MEM
)
747 operand
= XEXP (operand
, 0);
748 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
749 return register_indirect_p (operand
, mode
, addr_mode
);
753 go_if_legitimate_address_internal (rtx operand
, enum machine_mode mode
,
758 if (CONSTANT_ADDRESS_P (operand
) && TARGET_M6812
)
760 /* Reject the global variables if they are too wide. This forces
761 a load of their address in a register and generates smaller code. */
762 if (GET_MODE_SIZE (mode
) == 8)
767 addr_mode
= m68hc11_addr_mode
| (strict
? ADDR_STRICT
: 0);
768 if (register_indirect_p (operand
, mode
, addr_mode
))
772 if (PUSH_POP_ADDRESS_P (operand
))
776 if (symbolic_memory_operand (operand
, mode
))
784 m68hc11_go_if_legitimate_address (rtx operand
, enum machine_mode mode
,
791 printf ("Checking: ");
796 result
= go_if_legitimate_address_internal (operand
, mode
, strict
);
800 printf (" -> %s\n", result
== 0 ? "NO" : "YES");
807 printf ("go_if_legitimate%s, ret 0: %d:",
808 (strict
? "_strict" : ""), mode
);
817 m68hc11_legitimize_address (rtx
*operand ATTRIBUTE_UNUSED
,
818 rtx old_operand ATTRIBUTE_UNUSED
,
819 enum machine_mode mode ATTRIBUTE_UNUSED
)
826 m68hc11_reload_operands (rtx operands
[])
828 enum machine_mode mode
;
830 if (regs_inited
== 0)
833 mode
= GET_MODE (operands
[1]);
835 /* Input reload of indirect addressing (MEM (PLUS (REG) (CONST))). */
836 if (A_REG_P (operands
[0]) && memory_reload_operand (operands
[1], mode
))
838 rtx big_offset
= XEXP (XEXP (operands
[1], 0), 1);
839 rtx base
= XEXP (XEXP (operands
[1], 0), 0);
841 if (GET_CODE (base
) != REG
)
848 /* If the offset is out of range, we have to compute the address
849 with a separate add instruction. We try to do with with an 8-bit
850 add on the A register. This is possible only if the lowest part
851 of the offset (ie, big_offset % 256) is a valid constant offset
852 with respect to the mode. If it's not, we have to generate a
853 16-bit add on the D register. From:
855 (SET (REG X (MEM (PLUS (REG X) (CONST_INT 1000)))))
859 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
860 (SET (REG A) (PLUS (REG A) (CONST_INT 1000 / 256)))
861 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
862 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256)))
864 (SET (REG X) (PLUS (REG X) (CONST_INT 1000 / 256 * 256)))
865 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256))))
868 if (!VALID_CONSTANT_OFFSET_P (big_offset
, mode
))
871 rtx reg
= operands
[0];
873 int val
= INTVAL (big_offset
);
876 /* We use the 'operands[0]' as a scratch register to compute the
877 address. Make sure 'base' is in that register. */
878 if (!rtx_equal_p (base
, operands
[0]))
880 emit_move_insn (reg
, base
);
890 vh
= (val
>> 8) & 0x0FF;
894 /* Create the lowest part offset that still remains to be added.
895 If it's not a valid offset, do a 16-bit add. */
896 offset
= GEN_INT (vl
);
897 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
899 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
900 gen_rtx_PLUS (HImode
, reg
, big_offset
)));
905 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
906 gen_rtx_PLUS (HImode
, reg
,
907 GEN_INT (vh
<< 8))));
909 emit_move_insn (operands
[0],
910 gen_rtx_MEM (GET_MODE (operands
[1]),
911 gen_rtx_PLUS (Pmode
, reg
, offset
)));
916 /* Use the normal gen_movhi pattern. */
921 m68hc11_emit_libcall (const char *name
, enum rtx_code code
,
922 enum machine_mode dmode
, enum machine_mode smode
,
923 int noperands
, rtx
*operands
)
931 libcall
= gen_rtx_SYMBOL_REF (Pmode
, name
);
935 ret
= emit_library_call_value (libcall
, NULL_RTX
, LCT_CONST
,
936 dmode
, 1, operands
[1], smode
);
937 equiv
= gen_rtx_fmt_e (code
, dmode
, operands
[1]);
941 ret
= emit_library_call_value (libcall
, NULL_RTX
,
943 operands
[1], smode
, operands
[2],
945 equiv
= gen_rtx_fmt_ee (code
, dmode
, operands
[1], operands
[2]);
952 insns
= get_insns ();
954 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
957 /* Returns true if X is a PRE/POST increment decrement
958 (same as auto_inc_p() in rtlanal.c but do not take into
959 account the stack). */
961 m68hc11_auto_inc_p (rtx x
)
963 return GET_CODE (x
) == PRE_DEC
964 || GET_CODE (x
) == POST_INC
965 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_INC
;
969 /* Predicates for machine description. */
972 memory_reload_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
974 return GET_CODE (operand
) == MEM
975 && GET_CODE (XEXP (operand
, 0)) == PLUS
976 && ((GET_CODE (XEXP (XEXP (operand
, 0), 0)) == REG
977 && GET_CODE (XEXP (XEXP (operand
, 0), 1)) == CONST_INT
)
978 || (GET_CODE (XEXP (XEXP (operand
, 0), 1)) == REG
979 && GET_CODE (XEXP (XEXP (operand
, 0), 0)) == CONST_INT
));
983 tst_operand (rtx operand
, enum machine_mode mode
)
985 if (GET_CODE (operand
) == MEM
&& reload_completed
== 0)
987 rtx addr
= XEXP (operand
, 0);
988 if (m68hc11_auto_inc_p (addr
))
991 return nonimmediate_operand (operand
, mode
);
995 cmp_operand (rtx operand
, enum machine_mode mode
)
997 if (GET_CODE (operand
) == MEM
)
999 rtx addr
= XEXP (operand
, 0);
1000 if (m68hc11_auto_inc_p (addr
))
1003 return general_operand (operand
, mode
);
1007 non_push_operand (rtx operand
, enum machine_mode mode
)
1009 if (general_operand (operand
, mode
) == 0)
1012 if (push_operand (operand
, mode
) == 1)
1018 splitable_operand (rtx operand
, enum machine_mode mode
)
1020 if (general_operand (operand
, mode
) == 0)
1023 if (push_operand (operand
, mode
) == 1)
1026 /* Reject a (MEM (MEM X)) because the patterns that use non_push_operand
1027 need to split such addresses to access the low and high part but it
1028 is not possible to express a valid address for the low part. */
1029 if (mode
!= QImode
&& GET_CODE (operand
) == MEM
1030 && GET_CODE (XEXP (operand
, 0)) == MEM
)
1036 reg_or_some_mem_operand (rtx operand
, enum machine_mode mode
)
1038 if (GET_CODE (operand
) == MEM
)
1040 rtx op
= XEXP (operand
, 0);
1042 if (symbolic_memory_operand (op
, mode
))
1045 if (IS_STACK_PUSH (operand
))
1048 if (m68hc11_register_indirect_p (operand
, mode
))
1054 return register_operand (operand
, mode
);
1058 m68hc11_symbolic_p (rtx operand
, enum machine_mode mode
)
1060 if (GET_CODE (operand
) == MEM
)
1062 rtx op
= XEXP (operand
, 0);
1064 if (symbolic_memory_operand (op
, mode
))
1071 m68hc11_indirect_p (rtx operand
, enum machine_mode mode
)
1073 if (GET_CODE (operand
) == MEM
&& GET_MODE (operand
) == mode
)
1075 rtx op
= XEXP (operand
, 0);
1078 if (m68hc11_page0_symbol_p (op
))
1081 if (symbolic_memory_operand (op
, mode
))
1082 return TARGET_M6812
;
1084 if (reload_in_progress
)
1087 operand
= XEXP (operand
, 0);
1088 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
1089 return register_indirect_p (operand
, mode
, addr_mode
);
1095 stack_register_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1097 return SP_REG_P (operand
);
1101 d_register_operand (rtx operand
, enum machine_mode mode
)
1103 if (GET_MODE (operand
) != mode
&& mode
!= VOIDmode
)
1106 if (GET_CODE (operand
) == SUBREG
)
1107 operand
= XEXP (operand
, 0);
1109 return GET_CODE (operand
) == REG
1110 && (REGNO (operand
) >= FIRST_PSEUDO_REGISTER
1111 || REGNO (operand
) == HARD_D_REGNUM
1112 || (mode
== QImode
&& REGNO (operand
) == HARD_B_REGNUM
));
1116 hard_addr_reg_operand (rtx operand
, enum machine_mode mode
)
1118 if (GET_MODE (operand
) != mode
&& mode
!= VOIDmode
)
1121 if (GET_CODE (operand
) == SUBREG
)
1122 operand
= XEXP (operand
, 0);
1124 return GET_CODE (operand
) == REG
1125 && (REGNO (operand
) == HARD_X_REGNUM
1126 || REGNO (operand
) == HARD_Y_REGNUM
1127 || REGNO (operand
) == HARD_Z_REGNUM
);
1131 hard_reg_operand (rtx operand
, enum machine_mode mode
)
1133 if (GET_MODE (operand
) != mode
&& mode
!= VOIDmode
)
1136 if (GET_CODE (operand
) == SUBREG
)
1137 operand
= XEXP (operand
, 0);
1139 return GET_CODE (operand
) == REG
1140 && (REGNO (operand
) >= FIRST_PSEUDO_REGISTER
1141 || H_REGNO_P (REGNO (operand
)));
1145 memory_indexed_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1147 if (GET_CODE (operand
) != MEM
)
1150 operand
= XEXP (operand
, 0);
1151 if (GET_CODE (operand
) == PLUS
)
1153 if (GET_CODE (XEXP (operand
, 0)) == REG
)
1154 operand
= XEXP (operand
, 0);
1155 else if (GET_CODE (XEXP (operand
, 1)) == REG
)
1156 operand
= XEXP (operand
, 1);
1158 return GET_CODE (operand
) == REG
1159 && (REGNO (operand
) >= FIRST_PSEUDO_REGISTER
1160 || A_REGNO_P (REGNO (operand
)));
1164 push_pop_operand_p (rtx operand
)
1166 if (GET_CODE (operand
) != MEM
)
1170 operand
= XEXP (operand
, 0);
1171 return PUSH_POP_ADDRESS_P (operand
);
1174 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1175 reference and a constant. */
1178 symbolic_memory_operand (rtx op
, enum machine_mode mode
)
1180 switch (GET_CODE (op
))
1188 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1189 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1190 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1192 /* ??? This clause seems to be irrelevant. */
1194 return GET_MODE (op
) == mode
;
1197 return symbolic_memory_operand (XEXP (op
, 0), mode
)
1198 && symbolic_memory_operand (XEXP (op
, 1), mode
);
1206 m68hc11_eq_compare_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1208 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
1212 m68hc11_logical_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1214 return GET_CODE (op
) == AND
|| GET_CODE (op
) == IOR
|| GET_CODE (op
) == XOR
;
1218 m68hc11_arith_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1220 return GET_CODE (op
) == AND
|| GET_CODE (op
) == IOR
|| GET_CODE (op
) == XOR
1221 || GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
1222 || GET_CODE (op
) == ASHIFT
|| GET_CODE (op
) == ASHIFTRT
1223 || GET_CODE (op
) == LSHIFTRT
|| GET_CODE (op
) == ROTATE
1224 || GET_CODE (op
) == ROTATERT
;
1228 m68hc11_non_shift_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1230 return GET_CODE (op
) == AND
|| GET_CODE (op
) == IOR
|| GET_CODE (op
) == XOR
1231 || GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
;
1234 /* Return true if op is a shift operator. */
1236 m68hc11_shift_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1238 return GET_CODE (op
) == ROTATE
|| GET_CODE (op
) == ROTATERT
1239 || GET_CODE (op
) == LSHIFTRT
|| GET_CODE (op
) == ASHIFT
1240 || GET_CODE (op
) == ASHIFTRT
;
1244 m68hc11_unary_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1246 return GET_CODE (op
) == NEG
|| GET_CODE (op
) == NOT
1247 || GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
1250 /* Emit the code to build the trampoline used to call a nested function.
1254 ldy #&CXT movw #&CXT,*_.d1
1255 sty *_.d1 jmp FNADDR
1260 m68hc11_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
1262 const char *static_chain_reg
= reg_names
[STATIC_CHAIN_REGNUM
];
1265 if (*static_chain_reg
== '*')
1269 emit_move_insn (gen_rtx_MEM (HImode
, tramp
), GEN_INT (0x18ce));
1270 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 2)), cxt
);
1271 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 4)),
1273 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 6)),
1274 gen_rtx_CONST (QImode
,
1275 gen_rtx_SYMBOL_REF (Pmode
,
1276 static_chain_reg
)));
1277 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 7)),
1279 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 8)), fnaddr
);
1283 emit_move_insn (gen_rtx_MEM (HImode
, tramp
), GEN_INT (0x1803));
1284 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 2)), cxt
);
1285 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 4)),
1286 gen_rtx_CONST (HImode
,
1287 gen_rtx_SYMBOL_REF (Pmode
,
1288 static_chain_reg
)));
1289 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 6)),
1291 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, 7)), fnaddr
);
1295 /* Declaration of types. */
1297 /* Handle an "tiny_data" attribute; arguments as in
1298 struct attribute_spec.handler. */
1300 m68hc11_handle_page0_attribute (tree
*node
, tree name
,
1301 tree args ATTRIBUTE_UNUSED
,
1302 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1306 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
1308 DECL_SECTION_NAME (decl
) = build_string (6, ".page0");
1312 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
1313 *no_add_attrs
= true;
1319 const struct attribute_spec m68hc11_attribute_table
[] =
1321 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1322 { "interrupt", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1323 { "trap", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1324 { "far", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1325 { "near", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
1326 { "page0", 0, 0, false, false, false, m68hc11_handle_page0_attribute
},
1327 { NULL
, 0, 0, false, false, false, NULL
}
1330 /* Keep track of the symbol which has a `trap' attribute and which uses
1331 the `swi' calling convention. Since there is only one trap, we only
1332 record one such symbol. If there are several, a warning is reported. */
1333 static rtx trap_handler_symbol
= 0;
1335 /* Handle an attribute requiring a FUNCTION_TYPE, FIELD_DECL or TYPE_DECL;
1336 arguments as in struct attribute_spec.handler. */
1338 m68hc11_handle_fntype_attribute (tree
*node
, tree name
,
1339 tree args ATTRIBUTE_UNUSED
,
1340 int flags ATTRIBUTE_UNUSED
,
1343 if (TREE_CODE (*node
) != FUNCTION_TYPE
1344 && TREE_CODE (*node
) != METHOD_TYPE
1345 && TREE_CODE (*node
) != FIELD_DECL
1346 && TREE_CODE (*node
) != TYPE_DECL
)
1348 warning ("`%s' attribute only applies to functions",
1349 IDENTIFIER_POINTER (name
));
1350 *no_add_attrs
= true;
1355 /* Undo the effects of the above. */
1358 m68hc11_strip_name_encoding (const char *str
)
1360 return str
+ (*str
== '*' || *str
== '@' || *str
== '&');
1364 m68hc11_encode_label (tree decl
)
1366 const char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1367 int len
= strlen (str
);
1368 char *newstr
= alloca (len
+ 2);
1371 strcpy (&newstr
[1], str
);
1373 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = ggc_alloc_string (newstr
, len
+ 1);
1376 /* Return 1 if this is a symbol in page0 */
1378 m68hc11_page0_symbol_p (rtx x
)
1380 switch (GET_CODE (x
))
1383 return XSTR (x
, 0) != 0 && XSTR (x
, 0)[0] == '@';
1386 return m68hc11_page0_symbol_p (XEXP (x
, 0));
1389 if (!m68hc11_page0_symbol_p (XEXP (x
, 0)))
1392 return GET_CODE (XEXP (x
, 1)) == CONST_INT
1393 && INTVAL (XEXP (x
, 1)) < 256
1394 && INTVAL (XEXP (x
, 1)) >= 0;
1401 /* We want to recognize trap handlers so that we handle calls to traps
1402 in a special manner (by issuing the trap). This information is stored
1403 in SYMBOL_REF_FLAG. */
1406 m68hc11_encode_section_info (tree decl
, rtx rtl
, int first ATTRIBUTE_UNUSED
)
1412 if (TREE_CODE (decl
) == VAR_DECL
)
1414 if (lookup_attribute ("page0", DECL_ATTRIBUTES (decl
)) != 0)
1415 m68hc11_encode_label (decl
);
1419 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1422 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
1425 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1427 else if (lookup_attribute ("near", func_attr
) == NULL_TREE
)
1428 is_far
= TARGET_LONG_CALLS
!= 0;
1430 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1431 if (trap_handler
&& is_far
)
1433 warning ("`trap' and `far' attributes are not compatible, ignoring `far'");
1438 if (trap_handler_symbol
!= 0)
1439 warning ("`trap' attribute is already used");
1441 trap_handler_symbol
= XEXP (rtl
, 0);
1443 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = is_far
;
1447 m68hc11_section_type_flags (tree decl
, const char *name
, int reloc
)
1449 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
1451 if (strncmp (name
, ".eeprom", 7) == 0)
1453 flags
|= SECTION_WRITE
| SECTION_CODE
| SECTION_OVERRIDE
;
1460 m68hc11_is_far_symbol (rtx sym
)
1462 if (GET_CODE (sym
) == MEM
)
1463 sym
= XEXP (sym
, 0);
1465 return SYMBOL_REF_FLAG (sym
);
1469 m68hc11_is_trap_symbol (rtx sym
)
1471 if (GET_CODE (sym
) == MEM
)
1472 sym
= XEXP (sym
, 0);
1474 return trap_handler_symbol
!= 0 && rtx_equal_p (trap_handler_symbol
, sym
);
1478 /* Argument support functions. */
1480 /* Define the offset between two registers, one to be eliminated, and the
1481 other its replacement, at the start of a routine. */
1483 m68hc11_initial_elimination_offset (int from
, int to
)
1490 /* For a trap handler, we must take into account the registers which
1491 are pushed on the stack during the trap (except the PC). */
1492 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1493 current_function_interrupt
= lookup_attribute ("interrupt",
1494 func_attr
) != NULL_TREE
;
1495 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1497 if (lookup_attribute ("far", func_attr
) != 0)
1498 current_function_far
= 1;
1499 else if (lookup_attribute ("near", func_attr
) != 0)
1500 current_function_far
= 0;
1502 current_function_far
= (TARGET_LONG_CALLS
!= 0
1503 && !current_function_interrupt
1506 if (trap_handler
&& from
== ARG_POINTER_REGNUM
)
1509 /* For a function using 'call/rtc' we must take into account the
1510 page register which is pushed in the call. */
1511 else if (current_function_far
&& from
== ARG_POINTER_REGNUM
)
1516 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1518 /* 2 is for the saved frame.
1519 1 is for the 'sts' correction when creating the frame. */
1520 return get_frame_size () + 2 + m68hc11_sp_correction
+ size
;
1523 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1525 return m68hc11_sp_correction
;
1528 /* Push any 2 byte pseudo hard registers that we need to save. */
1529 for (regno
= SOFT_REG_FIRST
; regno
< SOFT_REG_LAST
; regno
++)
1531 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1537 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1539 return get_frame_size () + size
;
1542 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1549 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1550 for a call to a function whose data type is FNTYPE.
1551 For a library call, FNTYPE is 0. */
1554 m68hc11_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
)
1558 z_replacement_completed
= 0;
1562 /* For a library call, we must find out the type of the return value.
1563 When the return value is bigger than 4 bytes, it is returned in
1564 memory. In that case, the first argument of the library call is a
1565 pointer to the memory location. Because the first argument is passed in
1566 register D, we have to identify this, so that the first function
1567 parameter is not passed in D either. */
1573 if (libname
== 0 || GET_CODE (libname
) != SYMBOL_REF
)
1576 /* If the library ends in 'di' or in 'df', we assume it's
1577 returning some DImode or some DFmode which are 64-bit wide. */
1578 name
= XSTR (libname
, 0);
1579 len
= strlen (name
);
1581 && ((name
[len
- 2] == 'd'
1582 && (name
[len
- 1] == 'f' || name
[len
- 1] == 'i'))
1583 || (name
[len
- 3] == 'd'
1584 && (name
[len
- 2] == 'i' || name
[len
- 2] == 'f'))))
1586 /* We are in. Mark the first parameter register as already used. */
1593 ret_type
= TREE_TYPE (fntype
);
1595 if (ret_type
&& aggregate_value_p (ret_type
, fntype
))
1602 /* Update the data in CUM to advance over an argument
1603 of mode MODE and data type TYPE.
1604 (TYPE is null for libcalls where that information may not be available.) */
1607 m68hc11_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1608 tree type
, int named ATTRIBUTE_UNUSED
)
1610 if (mode
!= BLKmode
)
1612 if (cum
->words
== 0 && GET_MODE_SIZE (mode
) == 4)
1615 cum
->words
= GET_MODE_SIZE (mode
);
1619 cum
->words
+= GET_MODE_SIZE (mode
);
1620 if (cum
->words
<= HARD_REG_SIZE
)
1626 cum
->words
+= int_size_in_bytes (type
);
1631 /* Define where to put the arguments to a function.
1632 Value is zero to push the argument on the stack,
1633 or a hard register in which to store the argument.
1635 MODE is the argument's machine mode.
1636 TYPE is the data type of the argument (as a tree).
1637 This is null for libcalls where that information may
1639 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1640 the preceding args and about the function being called.
1641 NAMED is nonzero if this argument is a named parameter
1642 (otherwise it is an extra parameter matching an ellipsis). */
1645 m68hc11_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1646 tree type ATTRIBUTE_UNUSED
, int named ATTRIBUTE_UNUSED
)
1648 if (cum
->words
!= 0)
1653 if (mode
!= BLKmode
)
1655 if (GET_MODE_SIZE (mode
) == 2 * HARD_REG_SIZE
)
1656 return gen_rtx_REG (mode
, HARD_X_REGNUM
);
1658 if (GET_MODE_SIZE (mode
) > HARD_REG_SIZE
)
1662 return gen_rtx_REG (mode
, HARD_D_REGNUM
);
1667 /* If defined, a C expression which determines whether, and in which direction,
1668 to pad out an argument with extra space. The value should be of type
1669 `enum direction': either `upward' to pad above the argument,
1670 `downward' to pad below, or `none' to inhibit padding.
1672 Structures are stored left shifted in their argument slot. */
1674 m68hc11_function_arg_padding (enum machine_mode mode
, tree type
)
1676 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
1679 /* Fall back to the default. */
1680 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
1684 /* Function prologue and epilogue. */
1686 /* Emit a move after the reload pass has completed. This is used to
1687 emit the prologue and epilogue. */
1689 emit_move_after_reload (rtx to
, rtx from
, rtx scratch
)
1693 if (TARGET_M6812
|| H_REG_P (to
) || H_REG_P (from
))
1695 insn
= emit_move_insn (to
, from
);
1699 emit_move_insn (scratch
, from
);
1700 insn
= emit_move_insn (to
, scratch
);
1703 /* Put a REG_INC note to tell the flow analysis that the instruction
1705 if (IS_STACK_PUSH (to
))
1707 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
,
1708 XEXP (XEXP (to
, 0), 0),
1711 else if (IS_STACK_POP (from
))
1713 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
,
1714 XEXP (XEXP (from
, 0), 0),
1718 /* For 68HC11, put a REG_INC note on `sts _.frame' to prevent the cse-reg
1719 to think that sp == _.frame and later replace a x = sp with x = _.frame.
1720 The problem is that we are lying to gcc and use `txs' for x = sp
1721 (which is not really true because txs is really x = sp + 1). */
1722 else if (TARGET_M6811
&& SP_REG_P (from
))
1724 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
,
1731 m68hc11_total_frame_size (void)
1736 size
= get_frame_size ();
1737 if (current_function_interrupt
)
1739 size
+= 3 * HARD_REG_SIZE
;
1741 if (frame_pointer_needed
)
1742 size
+= HARD_REG_SIZE
;
1744 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1745 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1746 size
+= HARD_REG_SIZE
;
1752 m68hc11_output_function_epilogue (FILE *out ATTRIBUTE_UNUSED
,
1753 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1755 /* We catch the function epilogue generation to have a chance
1756 to clear the z_replacement_completed flag. */
1757 z_replacement_completed
= 0;
1761 expand_prologue (void)
1768 if (reload_completed
!= 1)
1771 size
= get_frame_size ();
1775 /* Generate specific prologue for interrupt handlers. */
1776 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1777 current_function_interrupt
= lookup_attribute ("interrupt",
1778 func_attr
) != NULL_TREE
;
1779 current_function_trap
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1780 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1781 current_function_far
= 1;
1782 else if (lookup_attribute ("near", func_attr
) != NULL_TREE
)
1783 current_function_far
= 0;
1785 current_function_far
= (TARGET_LONG_CALLS
!= 0
1786 && !current_function_interrupt
1787 && !current_function_trap
);
1789 /* Get the scratch register to build the frame and push registers.
1790 If the first argument is a 32-bit quantity, the D+X registers
1791 are used. Use Y to compute the frame. Otherwise, X is cheaper.
1792 For 68HC12, this scratch register is not used. */
1793 if (current_function_args_info
.nregs
== 2)
1798 /* Save current stack frame. */
1799 if (frame_pointer_needed
)
1800 emit_move_after_reload (stack_push_word
, hard_frame_pointer_rtx
, scratch
);
1802 /* For an interrupt handler, we must preserve _.tmp, _.z and _.xy.
1803 Other soft registers in page0 need not to be saved because they
1804 will be restored by C functions. For a trap handler, we don't
1805 need to preserve these registers because this is a synchronous call. */
1806 if (current_function_interrupt
)
1808 emit_move_after_reload (stack_push_word
, m68hc11_soft_tmp_reg
, scratch
);
1809 emit_move_after_reload (stack_push_word
,
1810 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
), scratch
);
1811 emit_move_after_reload (stack_push_word
,
1812 gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1816 /* Allocate local variables. */
1817 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1819 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1820 stack_pointer_rtx
, GEN_INT (-size
)));
1822 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1826 insn
= gen_rtx_PARALLEL
1829 gen_rtx_SET (VOIDmode
,
1831 gen_rtx_PLUS (HImode
,
1834 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1841 /* Allocate by pushing scratch values. */
1842 for (i
= 2; i
<= size
; i
+= 2)
1843 emit_move_after_reload (stack_push_word
, ix_reg
, 0);
1846 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1847 stack_pointer_rtx
, constm1_rtx
));
1850 /* Create the frame pointer. */
1851 if (frame_pointer_needed
)
1852 emit_move_after_reload (hard_frame_pointer_rtx
,
1853 stack_pointer_rtx
, scratch
);
1855 /* Push any 2 byte pseudo hard registers that we need to save. */
1856 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1858 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1860 emit_move_after_reload (stack_push_word
,
1861 gen_rtx_REG (HImode
, regno
), scratch
);
1867 expand_epilogue (void)
1874 if (reload_completed
!= 1)
1877 size
= get_frame_size ();
1879 /* If we are returning a value in two registers, we have to preserve the
1880 X register and use the Y register to restore the stack and the saved
1881 registers. Otherwise, use X because it's faster (and smaller). */
1882 if (current_function_return_rtx
== 0)
1884 else if (GET_CODE (current_function_return_rtx
) == MEM
)
1885 return_size
= HARD_REG_SIZE
;
1887 return_size
= GET_MODE_SIZE (GET_MODE (current_function_return_rtx
));
1889 if (return_size
> HARD_REG_SIZE
&& return_size
<= 2 * HARD_REG_SIZE
)
1894 /* Pop any 2 byte pseudo hard registers that we saved. */
1895 for (regno
= SOFT_REG_LAST
; regno
>= SOFT_REG_FIRST
; regno
--)
1897 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1899 emit_move_after_reload (gen_rtx_REG (HImode
, regno
),
1900 stack_pop_word
, scratch
);
1904 /* de-allocate auto variables */
1905 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1907 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1908 stack_pointer_rtx
, GEN_INT (size
)));
1910 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1914 insn
= gen_rtx_PARALLEL
1917 gen_rtx_SET (VOIDmode
,
1919 gen_rtx_PLUS (HImode
,
1922 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1929 for (i
= 2; i
<= size
; i
+= 2)
1930 emit_move_after_reload (scratch
, stack_pop_word
, scratch
);
1932 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1933 stack_pointer_rtx
, const1_rtx
));
1936 /* For an interrupt handler, restore ZTMP, ZREG and XYREG. */
1937 if (current_function_interrupt
)
1939 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1940 stack_pop_word
, scratch
);
1941 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
1942 stack_pop_word
, scratch
);
1943 emit_move_after_reload (m68hc11_soft_tmp_reg
, stack_pop_word
, scratch
);
1946 /* Restore previous frame pointer. */
1947 if (frame_pointer_needed
)
1948 emit_move_after_reload (hard_frame_pointer_rtx
, stack_pop_word
, scratch
);
1950 /* If the trap handler returns some value, copy the value
1951 in D, X onto the stack so that the rti will pop the return value
1953 else if (current_function_trap
&& return_size
!= 0)
1955 rtx addr_reg
= stack_pointer_rtx
;
1959 emit_move_after_reload (scratch
, stack_pointer_rtx
, 0);
1962 emit_move_after_reload (gen_rtx_MEM (HImode
,
1963 gen_rtx_PLUS (HImode
, addr_reg
,
1964 const1_rtx
)), d_reg
, 0);
1965 if (return_size
> HARD_REG_SIZE
)
1966 emit_move_after_reload (gen_rtx_MEM (HImode
,
1967 gen_rtx_PLUS (HImode
, addr_reg
,
1968 GEN_INT (3))), ix_reg
, 0);
1971 emit_jump_insn (gen_return ());
1975 /* Low and High part extraction for 68HC11. These routines are
1976 similar to gen_lowpart and gen_highpart but they have been
1977 fixed to work for constants and 68HC11 specific registers. */
1980 m68hc11_gen_lowpart (enum machine_mode mode
, rtx x
)
1982 /* We assume that the low part of an auto-inc mode is the same with
1983 the mode changed and that the caller split the larger mode in the
1985 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1987 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1990 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1991 floating-point constant. A CONST_DOUBLE is used whenever the
1992 constant requires more than one word in order to be adequately
1994 if (GET_CODE (x
) == CONST_DOUBLE
)
1998 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2002 if (GET_MODE (x
) == SFmode
)
2004 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2005 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[0]);
2011 split_double (x
, &first
, &second
);
2015 return GEN_INT (l
[0]);
2017 return gen_int_mode (l
[0], HImode
);
2021 l
[0] = CONST_DOUBLE_LOW (x
);
2024 return GEN_INT (l
[0]);
2025 else if (mode
== HImode
&& GET_MODE (x
) == SFmode
)
2026 return gen_int_mode (l
[0], HImode
);
2031 if (mode
== QImode
&& D_REG_P (x
))
2032 return gen_rtx_REG (mode
, HARD_B_REGNUM
);
2034 /* gen_lowpart crashes when it is called with a SUBREG. */
2035 if (GET_CODE (x
) == SUBREG
&& SUBREG_BYTE (x
) != 0)
2038 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 4);
2039 else if (mode
== HImode
)
2040 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 2);
2044 x
= gen_lowpart (mode
, x
);
2046 /* Return a different rtx to avoid to share it in several insns
2047 (when used by a split pattern). Sharing addresses within
2048 a MEM breaks the Z register replacement (and reloading). */
2049 if (GET_CODE (x
) == MEM
)
2055 m68hc11_gen_highpart (enum machine_mode mode
, rtx x
)
2057 /* We assume that the high part of an auto-inc mode is the same with
2058 the mode changed and that the caller split the larger mode in the
2060 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
2062 return gen_rtx_MEM (mode
, XEXP (x
, 0));
2065 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
2066 floating-point constant. A CONST_DOUBLE is used whenever the
2067 constant requires more than one word in order to be adequately
2069 if (GET_CODE (x
) == CONST_DOUBLE
)
2073 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2077 if (GET_MODE (x
) == SFmode
)
2079 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2080 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[1]);
2086 split_double (x
, &first
, &second
);
2090 return GEN_INT (l
[1]);
2092 return gen_int_mode ((l
[1] >> 16), HImode
);
2096 l
[1] = CONST_DOUBLE_HIGH (x
);
2100 return GEN_INT (l
[1]);
2101 else if (mode
== HImode
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2102 return gen_int_mode ((l
[0] >> 16), HImode
);
2106 if (GET_CODE (x
) == CONST_INT
)
2108 HOST_WIDE_INT val
= INTVAL (x
);
2112 return gen_int_mode (val
>> 8, QImode
);
2114 else if (mode
== HImode
)
2116 return gen_int_mode (val
>> 16, HImode
);
2119 if (mode
== QImode
&& D_REG_P (x
))
2120 return gen_rtx_REG (mode
, HARD_A_REGNUM
);
2122 /* There is no way in GCC to represent the upper part of a word register.
2123 To obtain the 8-bit upper part of a soft register, we change the
2124 reg into a mem rtx. This is possible because they are physically
2125 located in memory. There is no offset because we are big-endian. */
2126 if (mode
== QImode
&& S_REG_P (x
))
2130 /* Avoid the '*' for direct addressing mode when this
2131 addressing mode is disabled. */
2132 pos
= TARGET_NO_DIRECT_MODE
? 1 : 0;
2133 return gen_rtx_MEM (QImode
,
2134 gen_rtx_SYMBOL_REF (Pmode
,
2135 ®_names
[REGNO (x
)][pos
]));
2138 /* gen_highpart crashes when it is called with a SUBREG. */
2139 if (GET_CODE (x
) == SUBREG
)
2141 return gen_rtx_SUBREG (mode
, XEXP (x
, 0), XEXP (x
, 1));
2143 if (GET_CODE (x
) == REG
)
2145 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2146 return gen_rtx_REG (mode
, REGNO (x
));
2148 return gen_rtx_SUBREG (mode
, x
, 0);
2151 if (GET_CODE (x
) == MEM
)
2153 x
= change_address (x
, mode
, 0);
2155 /* Return a different rtx to avoid to share it in several insns
2156 (when used by a split pattern). Sharing addresses within
2157 a MEM breaks the Z register replacement (and reloading). */
2158 if (GET_CODE (x
) == MEM
)
2166 /* Obscure register manipulation. */
2168 /* Finds backward in the instructions to see if register 'reg' is
2169 dead. This is used when generating code to see if we can use 'reg'
2170 as a scratch register. This allows us to choose a better generation
2171 of code when we know that some register dies or can be clobbered. */
2174 dead_register_here (rtx x
, rtx reg
)
2180 x_reg
= gen_rtx_REG (SImode
, HARD_X_REGNUM
);
2184 for (p
= PREV_INSN (x
); p
&& GET_CODE (p
) != CODE_LABEL
; p
= PREV_INSN (p
))
2191 if (GET_CODE (body
) == CALL_INSN
)
2193 if (GET_CODE (body
) == JUMP_INSN
)
2196 if (GET_CODE (body
) == SET
)
2198 rtx dst
= XEXP (body
, 0);
2200 if (GET_CODE (dst
) == REG
&& REGNO (dst
) == REGNO (reg
))
2202 if (x_reg
&& rtx_equal_p (dst
, x_reg
))
2205 if (find_regno_note (p
, REG_DEAD
, REGNO (reg
)))
2208 else if (reg_mentioned_p (reg
, p
)
2209 || (x_reg
&& reg_mentioned_p (x_reg
, p
)))
2213 /* Scan forward to see if the register is set in some insns and never
2215 for (p
= x
/*NEXT_INSN (x) */ ; p
; p
= NEXT_INSN (p
))
2219 if (GET_CODE (p
) == CODE_LABEL
2220 || GET_CODE (p
) == JUMP_INSN
2221 || GET_CODE (p
) == CALL_INSN
|| GET_CODE (p
) == BARRIER
)
2224 if (GET_CODE (p
) != INSN
)
2228 if (GET_CODE (body
) == SET
)
2230 rtx src
= XEXP (body
, 1);
2231 rtx dst
= XEXP (body
, 0);
2233 if (GET_CODE (dst
) == REG
2234 && REGNO (dst
) == REGNO (reg
) && !reg_mentioned_p (reg
, src
))
2238 /* Register is used (may be in source or in dest). */
2239 if (reg_mentioned_p (reg
, p
)
2240 || (x_reg
!= 0 && GET_MODE (p
) == SImode
2241 && reg_mentioned_p (x_reg
, p
)))
2244 return p
== 0 ? 1 : 0;
2248 /* Code generation operations called from machine description file. */
2250 /* Print the name of register 'regno' in the assembly file. */
2252 asm_print_register (FILE *file
, int regno
)
2254 const char *name
= reg_names
[regno
];
2256 if (TARGET_NO_DIRECT_MODE
&& name
[0] == '*')
2259 fprintf (file
, "%s", name
);
2262 /* A C compound statement to output to stdio stream STREAM the
2263 assembler syntax for an instruction operand X. X is an RTL
2266 CODE is a value that can be used to specify one of several ways
2267 of printing the operand. It is used when identical operands
2268 must be printed differently depending on the context. CODE
2269 comes from the `%' specification that was used to request
2270 printing of the operand. If the specification was just `%DIGIT'
2271 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2272 is the ASCII code for LTR.
2274 If X is a register, this macro should print the register's name.
2275 The names can be found in an array `reg_names' whose type is
2276 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2278 When the machine description has a specification `%PUNCT' (a `%'
2279 followed by a punctuation character), this macro is called with
2280 a null pointer for X and the punctuation character for CODE.
2282 The M68HC11 specific codes are:
2284 'b' for the low part of the operand.
2285 'h' for the high part of the operand
2286 The 'b' or 'h' modifiers have no effect if the operand has
2287 the QImode and is not a S_REG_P (soft register). If the
2288 operand is a hard register, these two modifiers have no effect.
2289 't' generate the temporary scratch register. The operand is
2291 'T' generate the low-part temporary scratch register. The operand is
2295 print_operand (FILE *file
, rtx op
, int letter
)
2299 asm_print_register (file
, SOFT_TMP_REGNUM
);
2302 else if (letter
== 'T')
2304 asm_print_register (file
, SOFT_TMP_REGNUM
);
2305 fprintf (file
, "+1");
2308 else if (letter
== '#')
2310 asm_fprintf (file
, "%I");
2313 if (GET_CODE (op
) == REG
)
2315 if (letter
== 'b' && S_REG_P (op
))
2317 asm_print_register (file
, REGNO (op
));
2318 fprintf (file
, "+1");
2320 else if (letter
== 'b' && D_REG_P (op
))
2322 asm_print_register (file
, HARD_B_REGNUM
);
2326 asm_print_register (file
, REGNO (op
));
2331 if (GET_CODE (op
) == SYMBOL_REF
&& (letter
== 'b' || letter
== 'h'))
2334 asm_fprintf (file
, "%I%%lo(");
2336 asm_fprintf (file
, "%I%%hi(");
2338 output_addr_const (file
, op
);
2339 fprintf (file
, ")");
2343 /* Get the low or high part of the operand when 'b' or 'h' modifiers
2344 are specified. If we already have a QImode, there is nothing to do. */
2345 if (GET_MODE (op
) == HImode
|| GET_MODE (op
) == VOIDmode
)
2349 op
= m68hc11_gen_lowpart (QImode
, op
);
2351 else if (letter
== 'h')
2353 op
= m68hc11_gen_highpart (QImode
, op
);
2357 if (GET_CODE (op
) == MEM
)
2359 rtx base
= XEXP (op
, 0);
2360 switch (GET_CODE (base
))
2365 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (op
)));
2366 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2375 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2376 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2377 fprintf (file
, "-");
2386 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2387 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2388 fprintf (file
, "+");
2397 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (op
)));
2398 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2407 fprintf (file
, "[");
2408 print_operand_address (file
, XEXP (base
, 0));
2409 fprintf (file
, "]");
2416 if (m68hc11_page0_symbol_p (base
))
2417 fprintf (file
, "*");
2419 output_address (base
);
2423 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2428 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2429 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2430 asm_fprintf (file
, "%I0x%lx", l
);
2432 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2436 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (op
),
2437 sizeof (dstr
), 0, 1);
2438 asm_fprintf (file
, "%I0r%s", dstr
);
2442 int need_parenthesize
= 0;
2445 asm_fprintf (file
, "%I");
2447 need_parenthesize
= must_parenthesize (op
);
2449 if (need_parenthesize
)
2450 fprintf (file
, "(");
2452 output_addr_const (file
, op
);
2453 if (need_parenthesize
)
2454 fprintf (file
, ")");
2458 /* Returns true if the operand 'op' must be printed with parenthesis
2459 around it. This must be done only if there is a symbol whose name
2460 is a processor register. */
2462 must_parenthesize (rtx op
)
2466 switch (GET_CODE (op
))
2469 name
= XSTR (op
, 0);
2470 /* Avoid a conflict between symbol name and a possible
2472 return (strcasecmp (name
, "a") == 0
2473 || strcasecmp (name
, "b") == 0
2474 || strcasecmp (name
, "d") == 0
2475 || strcasecmp (name
, "x") == 0
2476 || strcasecmp (name
, "y") == 0
2477 || strcasecmp (name
, "ix") == 0
2478 || strcasecmp (name
, "iy") == 0
2479 || strcasecmp (name
, "pc") == 0
2480 || strcasecmp (name
, "sp") == 0
2481 || strcasecmp (name
, "ccr") == 0) ? 1 : 0;
2485 return must_parenthesize (XEXP (op
, 0))
2486 || must_parenthesize (XEXP (op
, 1));
2492 return must_parenthesize (XEXP (op
, 0));
2503 /* A C compound statement to output to stdio stream STREAM the
2504 assembler syntax for an instruction operand that is a memory
2505 reference whose address is ADDR. ADDR is an RTL expression. */
2508 print_operand_address (FILE *file
, rtx addr
)
2512 int need_parenthesis
= 0;
2514 switch (GET_CODE (addr
))
2517 if (!REG_P (addr
) || !REG_OK_FOR_BASE_STRICT_P (addr
))
2520 fprintf (file
, "0,");
2521 asm_print_register (file
, REGNO (addr
));
2525 base
= XEXP (addr
, 0);
2526 switch (GET_CODE (base
))
2531 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (addr
)));
2532 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2541 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2542 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2543 fprintf (file
, "-");
2552 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2553 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2554 fprintf (file
, "+");
2563 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (addr
)));
2564 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2571 need_parenthesis
= must_parenthesize (base
);
2572 if (need_parenthesis
)
2573 fprintf (file
, "(");
2575 output_addr_const (file
, base
);
2576 if (need_parenthesis
)
2577 fprintf (file
, ")");
2583 base
= XEXP (addr
, 0);
2584 offset
= XEXP (addr
, 1);
2585 if (!G_REG_P (base
) && G_REG_P (offset
))
2587 base
= XEXP (addr
, 1);
2588 offset
= XEXP (addr
, 0);
2590 if ((CONSTANT_ADDRESS_P (base
)) && (CONSTANT_ADDRESS_P (offset
)))
2592 need_parenthesis
= must_parenthesize (addr
);
2594 if (need_parenthesis
)
2595 fprintf (file
, "(");
2597 output_addr_const (file
, base
);
2598 fprintf (file
, "+");
2599 output_addr_const (file
, offset
);
2600 if (need_parenthesis
)
2601 fprintf (file
, ")");
2603 else if (REG_P (base
) && REG_OK_FOR_BASE_STRICT_P (base
))
2609 asm_print_register (file
, REGNO (offset
));
2610 fprintf (file
, ",");
2611 asm_print_register (file
, REGNO (base
));
2618 need_parenthesis
= must_parenthesize (offset
);
2619 if (need_parenthesis
)
2620 fprintf (file
, "(");
2622 output_addr_const (file
, offset
);
2623 if (need_parenthesis
)
2624 fprintf (file
, ")");
2625 fprintf (file
, ",");
2626 asm_print_register (file
, REGNO (base
));
2636 if (GET_CODE (addr
) == CONST_INT
2637 && INTVAL (addr
) < 0x8000 && INTVAL (addr
) >= -0x8000)
2639 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2643 need_parenthesis
= must_parenthesize (addr
);
2644 if (need_parenthesis
)
2645 fprintf (file
, "(");
2647 output_addr_const (file
, addr
);
2648 if (need_parenthesis
)
2649 fprintf (file
, ")");
2656 /* Splitting of some instructions. */
2659 m68hc11_expand_compare (enum rtx_code code
, rtx op0
, rtx op1
)
2663 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
2667 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
,
2668 gen_rtx_COMPARE (VOIDmode
, op0
, op1
)));
2669 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
2676 m68hc11_expand_compare_and_branch (enum rtx_code code
, rtx op0
, rtx op1
,
2681 switch (GET_MODE (op0
))
2685 tmp
= m68hc11_expand_compare (code
, op0
, op1
);
2686 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2687 gen_rtx_LABEL_REF (VOIDmode
, label
),
2689 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
2693 /* SCz: from i386.c */
2696 /* Don't expand the comparison early, so that we get better code
2697 when jump or whoever decides to reverse the comparison. */
2702 code
= m68hc11_prepare_fp_compare_args (code
, &m68hc11_compare_op0
,
2703 &m68hc11_compare_op1
);
2705 tmp
= gen_rtx_fmt_ee (code
, m68hc11_fp_compare_mode (code
),
2706 m68hc11_compare_op0
, m68hc11_compare_op1
);
2707 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2708 gen_rtx_LABEL_REF (VOIDmode
, label
),
2710 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
2712 use_fcomi
= ix86_use_fcomi_compare (code
);
2713 vec
= rtvec_alloc (3 + !use_fcomi
);
2714 RTVEC_ELT (vec
, 0) = tmp
;
2716 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
2718 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
2721 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
2723 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
2729 /* Expand SImode branch into multiple compare+branch. */
2731 rtx lo
[2], hi
[2], label2
;
2732 enum rtx_code code1
, code2
, code3
;
2734 if (CONSTANT_P (op0
) && !CONSTANT_P (op1
))
2739 code
= swap_condition (code
);
2741 lo
[0] = m68hc11_gen_lowpart (HImode
, op0
);
2742 lo
[1] = m68hc11_gen_lowpart (HImode
, op1
);
2743 hi
[0] = m68hc11_gen_highpart (HImode
, op0
);
2744 hi
[1] = m68hc11_gen_highpart (HImode
, op1
);
2746 /* Otherwise, if we are doing less-than, op1 is a constant and the
2747 low word is zero, then we can just examine the high word. */
2749 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
2750 && (code
== LT
|| code
== LTU
))
2752 return m68hc11_expand_compare_and_branch (code
, hi
[0], hi
[1],
2756 /* Otherwise, we need two or three jumps. */
2758 label2
= gen_label_rtx ();
2761 code2
= swap_condition (code
);
2762 code3
= unsigned_condition (code
);
2803 * if (hi(a) < hi(b)) goto true;
2804 * if (hi(a) > hi(b)) goto false;
2805 * if (lo(a) < lo(b)) goto true;
2808 if (code1
!= UNKNOWN
)
2809 m68hc11_expand_compare_and_branch (code1
, hi
[0], hi
[1], label
);
2810 if (code2
!= UNKNOWN
)
2811 m68hc11_expand_compare_and_branch (code2
, hi
[0], hi
[1], label2
);
2813 m68hc11_expand_compare_and_branch (code3
, lo
[0], lo
[1], label
);
2815 if (code2
!= UNKNOWN
)
2816 emit_label (label2
);
2826 /* Return the increment/decrement mode of a MEM if it is such.
2827 Return CONST if it is anything else. */
2829 autoinc_mode (rtx x
)
2831 if (GET_CODE (x
) != MEM
)
2835 if (GET_CODE (x
) == PRE_INC
2836 || GET_CODE (x
) == PRE_DEC
2837 || GET_CODE (x
) == POST_INC
2838 || GET_CODE (x
) == POST_DEC
)
2839 return GET_CODE (x
);
2845 m68hc11_make_autoinc_notes (rtx
*x
, void *data
)
2849 switch (GET_CODE (*x
))
2856 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_INC
, XEXP (*x
, 0),
2865 /* Split a DI, SI or HI move into several smaller move operations.
2866 The scratch register 'scratch' is used as a temporary to load
2867 store intermediate values. It must be a hard register. */
2869 m68hc11_split_move (rtx to
, rtx from
, rtx scratch
)
2871 rtx low_to
, low_from
;
2872 rtx high_to
, high_from
;
2874 enum machine_mode mode
;
2876 int autoinc_from
= autoinc_mode (from
);
2877 int autoinc_to
= autoinc_mode (to
);
2879 mode
= GET_MODE (to
);
2881 /* If the TO and FROM contain autoinc modes that are not compatible
2882 together (one pop and the other a push), we must change one to
2883 an offsetable operand and generate an appropriate add at the end. */
2884 if (TARGET_M6812
&& GET_MODE_SIZE (mode
) > 2)
2889 /* The source uses an autoinc mode which is not compatible with
2890 a split (this would result in a word swap). */
2891 if (autoinc_from
== PRE_INC
|| autoinc_from
== POST_DEC
)
2893 code
= GET_CODE (XEXP (from
, 0));
2894 reg
= XEXP (XEXP (from
, 0), 0);
2895 offset
= GET_MODE_SIZE (GET_MODE (from
));
2896 if (code
== POST_DEC
)
2899 if (code
== PRE_INC
)
2900 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2902 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2903 if (code
== POST_DEC
)
2904 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2908 /* Likewise for destination. */
2909 if (autoinc_to
== PRE_INC
|| autoinc_to
== POST_DEC
)
2911 code
= GET_CODE (XEXP (to
, 0));
2912 reg
= XEXP (XEXP (to
, 0), 0);
2913 offset
= GET_MODE_SIZE (GET_MODE (to
));
2914 if (code
== POST_DEC
)
2917 if (code
== PRE_INC
)
2918 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2920 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2921 if (code
== POST_DEC
)
2922 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2926 /* The source and destination auto increment modes must be compatible
2927 with each other: same direction. */
2928 if ((autoinc_to
!= autoinc_from
2929 && autoinc_to
!= CONST
&& autoinc_from
!= CONST
)
2930 /* The destination address register must not be used within
2931 the source operand because the source address would change
2932 while doing the copy. */
2933 || (autoinc_to
!= CONST
2934 && reg_mentioned_p (XEXP (XEXP (to
, 0), 0), from
)
2935 && !IS_STACK_PUSH (to
)))
2937 /* Must change the destination. */
2938 code
= GET_CODE (XEXP (to
, 0));
2939 reg
= XEXP (XEXP (to
, 0), 0);
2940 offset
= GET_MODE_SIZE (GET_MODE (to
));
2941 if (code
== PRE_DEC
|| code
== POST_DEC
)
2944 if (code
== PRE_DEC
|| code
== PRE_INC
)
2945 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2946 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2947 if (code
== POST_DEC
|| code
== POST_INC
)
2948 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2953 /* Likewise, the source address register must not be used within
2954 the destination operand. */
2955 if (autoinc_from
!= CONST
2956 && reg_mentioned_p (XEXP (XEXP (from
, 0), 0), to
)
2957 && !IS_STACK_PUSH (to
))
2959 /* Must change the source. */
2960 code
= GET_CODE (XEXP (from
, 0));
2961 reg
= XEXP (XEXP (from
, 0), 0);
2962 offset
= GET_MODE_SIZE (GET_MODE (from
));
2963 if (code
== PRE_DEC
|| code
== POST_DEC
)
2966 if (code
== PRE_DEC
|| code
== PRE_INC
)
2967 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2968 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2969 if (code
== POST_DEC
|| code
== POST_INC
)
2970 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2976 if (GET_MODE_SIZE (mode
) == 8)
2978 else if (GET_MODE_SIZE (mode
) == 4)
2984 && IS_STACK_PUSH (to
)
2985 && reg_mentioned_p (gen_rtx_REG (HImode
, HARD_SP_REGNUM
), from
))
2991 else if (mode
== HImode
)
2999 low_to
= m68hc11_gen_lowpart (mode
, to
);
3000 high_to
= m68hc11_gen_highpart (mode
, to
);
3002 low_from
= m68hc11_gen_lowpart (mode
, from
);
3003 if (mode
== SImode
&& GET_CODE (from
) == CONST_INT
)
3005 if (INTVAL (from
) >= 0)
3006 high_from
= const0_rtx
;
3008 high_from
= constm1_rtx
;
3011 high_from
= m68hc11_gen_highpart (mode
, from
);
3015 high_from
= adjust_address (high_from
, mode
, offset
);
3016 low_from
= high_from
;
3019 /* When copying with a POST_INC mode, we must copy the
3020 high part and then the low part to guarantee a correct
3023 && GET_MODE_SIZE (mode
) >= 2
3024 && autoinc_from
!= autoinc_to
3025 && (autoinc_from
== POST_INC
|| autoinc_to
== POST_INC
))
3034 low_from
= high_from
;
3039 m68hc11_split_move (low_to
, low_from
, scratch
);
3040 m68hc11_split_move (high_to
, high_from
, scratch
);
3042 else if (H_REG_P (to
) || H_REG_P (from
)
3043 || (low_from
== const0_rtx
3044 && high_from
== const0_rtx
3045 && ! push_operand (to
, GET_MODE (to
))
3046 && ! H_REG_P (scratch
))
3048 && (!m68hc11_register_indirect_p (from
, GET_MODE (from
))
3049 || m68hc11_small_indexed_indirect_p (from
,
3051 && (!m68hc11_register_indirect_p (to
, GET_MODE (to
))
3052 || m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
)))))
3054 insn
= emit_move_insn (low_to
, low_from
);
3055 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
3057 insn
= emit_move_insn (high_to
, high_from
);
3058 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
3062 insn
= emit_move_insn (scratch
, low_from
);
3063 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
3064 insn
= emit_move_insn (low_to
, scratch
);
3065 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
3067 insn
= emit_move_insn (scratch
, high_from
);
3068 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
3069 insn
= emit_move_insn (high_to
, scratch
);
3070 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
3075 simplify_logical (enum machine_mode mode
, int code
, rtx operand
, rtx
*result
)
3081 if (GET_CODE (operand
) != CONST_INT
)
3089 val
= INTVAL (operand
);
3093 if ((val
& mask
) == 0)
3095 if ((val
& mask
) == mask
)
3096 *result
= constm1_rtx
;
3100 if ((val
& mask
) == 0)
3101 *result
= const0_rtx
;
3102 if ((val
& mask
) == mask
)
3107 if ((val
& mask
) == 0)
3115 m68hc11_emit_logical (enum machine_mode mode
, int code
, rtx
*operands
)
3120 need_copy
= (rtx_equal_p (operands
[0], operands
[1])
3121 || rtx_equal_p (operands
[0], operands
[2])) ? 0 : 1;
3123 operands
[1] = simplify_logical (mode
, code
, operands
[1], &result
);
3124 operands
[2] = simplify_logical (mode
, code
, operands
[2], &result
);
3126 if (result
&& GET_CODE (result
) == CONST_INT
)
3128 if (!H_REG_P (operands
[0]) && operands
[3]
3129 && (INTVAL (result
) != 0 || IS_STACK_PUSH (operands
[0])))
3131 emit_move_insn (operands
[3], result
);
3132 emit_move_insn (operands
[0], operands
[3]);
3136 emit_move_insn (operands
[0], result
);
3139 else if (operands
[1] != 0 && operands
[2] != 0)
3143 if (!H_REG_P (operands
[0]) && operands
[3])
3145 emit_move_insn (operands
[3], operands
[1]);
3146 emit_insn (gen_rtx_SET (mode
,
3148 gen_rtx_fmt_ee (code
, mode
,
3149 operands
[3], operands
[2])));
3150 insn
= emit_move_insn (operands
[0], operands
[3]);
3154 insn
= emit_insn (gen_rtx_SET (mode
,
3156 gen_rtx_fmt_ee (code
, mode
,
3162 /* The logical operation is similar to a copy. */
3167 if (GET_CODE (operands
[1]) == CONST_INT
)
3172 if (!H_REG_P (operands
[0]) && !H_REG_P (src
))
3174 emit_move_insn (operands
[3], src
);
3175 emit_move_insn (operands
[0], operands
[3]);
3179 emit_move_insn (operands
[0], src
);
3185 m68hc11_split_logical (enum machine_mode mode
, int code
, rtx
*operands
)
3190 low
[0] = m68hc11_gen_lowpart (mode
, operands
[0]);
3191 low
[1] = m68hc11_gen_lowpart (mode
, operands
[1]);
3192 low
[2] = m68hc11_gen_lowpart (mode
, operands
[2]);
3194 high
[0] = m68hc11_gen_highpart (mode
, operands
[0]);
3196 if (mode
== SImode
&& GET_CODE (operands
[1]) == CONST_INT
)
3198 if (INTVAL (operands
[1]) >= 0)
3199 high
[1] = const0_rtx
;
3201 high
[1] = constm1_rtx
;
3204 high
[1] = m68hc11_gen_highpart (mode
, operands
[1]);
3206 if (mode
== SImode
&& GET_CODE (operands
[2]) == CONST_INT
)
3208 if (INTVAL (operands
[2]) >= 0)
3209 high
[2] = const0_rtx
;
3211 high
[2] = constm1_rtx
;
3214 high
[2] = m68hc11_gen_highpart (mode
, operands
[2]);
3216 low
[3] = operands
[3];
3217 high
[3] = operands
[3];
3220 m68hc11_split_logical (HImode
, code
, low
);
3221 m68hc11_split_logical (HImode
, code
, high
);
3225 m68hc11_emit_logical (mode
, code
, low
);
3226 m68hc11_emit_logical (mode
, code
, high
);
3230 /* Code generation. */
3233 m68hc11_output_swap (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
3235 /* We have to be careful with the cc_status. An address register swap
3236 is generated for some comparison. The comparison is made with D
3237 but the branch really uses the address register. See the split
3238 pattern for compare. The xgdx/xgdy preserve the flags but after
3239 the exchange, the flags will reflect to the value of X and not D.
3240 Tell this by setting the cc_status according to the cc_prev_status. */
3241 if (X_REG_P (operands
[1]) || X_REG_P (operands
[0]))
3243 if (cc_prev_status
.value1
!= 0
3244 && (D_REG_P (cc_prev_status
.value1
)
3245 || X_REG_P (cc_prev_status
.value1
)))
3247 cc_status
= cc_prev_status
;
3248 if (D_REG_P (cc_status
.value1
))
3249 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3252 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3258 output_asm_insn ("xgdx", operands
);
3262 if (cc_prev_status
.value1
!= 0
3263 && (D_REG_P (cc_prev_status
.value1
)
3264 || Y_REG_P (cc_prev_status
.value1
)))
3266 cc_status
= cc_prev_status
;
3267 if (D_REG_P (cc_status
.value1
))
3268 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3271 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3277 output_asm_insn ("xgdy", operands
);
3281 /* Returns 1 if the next insn after 'insn' is a test of the register 'reg'.
3282 This is used to decide whether a move that set flags should be used
3285 next_insn_test_reg (rtx insn
, rtx reg
)
3289 insn
= next_nonnote_insn (insn
);
3290 if (GET_CODE (insn
) != INSN
)
3293 body
= PATTERN (insn
);
3294 if (sets_cc0_p (body
) != 1)
3297 if (rtx_equal_p (XEXP (body
, 1), reg
) == 0)
3303 /* Generate the code to move a 16-bit operand into another one. */
3306 m68hc11_gen_movhi (rtx insn
, rtx
*operands
)
3310 /* Move a register or memory to the same location.
3311 This is possible because such insn can appear
3312 in a non-optimizing mode. */
3313 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3315 cc_status
= cc_prev_status
;
3321 if (IS_STACK_PUSH (operands
[0]) && H_REG_P (operands
[1]))
3323 cc_status
= cc_prev_status
;
3324 switch (REGNO (operands
[1]))
3329 output_asm_insn ("psh%1", operands
);
3331 case HARD_SP_REGNUM
:
3332 output_asm_insn ("sts\t2,-sp", operands
);
3339 if (IS_STACK_POP (operands
[1]) && H_REG_P (operands
[0]))
3341 cc_status
= cc_prev_status
;
3342 switch (REGNO (operands
[0]))
3347 output_asm_insn ("pul%0", operands
);
3354 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3356 m68hc11_notice_keep_cc (operands
[0]);
3357 output_asm_insn ("tfr\t%1,%0", operands
);
3359 else if (H_REG_P (operands
[0]))
3361 if (SP_REG_P (operands
[0]))
3362 output_asm_insn ("lds\t%1", operands
);
3364 output_asm_insn ("ld%0\t%1", operands
);
3366 else if (H_REG_P (operands
[1]))
3368 if (SP_REG_P (operands
[1]))
3369 output_asm_insn ("sts\t%0", operands
);
3371 output_asm_insn ("st%1\t%0", operands
);
3375 rtx from
= operands
[1];
3376 rtx to
= operands
[0];
3378 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3379 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3380 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3381 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3387 ops
[0] = operands
[2];
3390 m68hc11_gen_movhi (insn
, ops
);
3392 ops
[1] = operands
[2];
3393 m68hc11_gen_movhi (insn
, ops
);
3397 /* !!!! SCz wrong here. */
3398 fatal_insn ("move insn not handled", insn
);
3403 if (GET_CODE (from
) == CONST_INT
&& INTVAL (from
) == 0)
3405 output_asm_insn ("clr\t%h0", operands
);
3406 output_asm_insn ("clr\t%b0", operands
);
3410 m68hc11_notice_keep_cc (operands
[0]);
3411 output_asm_insn ("movw\t%1,%0", operands
);
3418 if (IS_STACK_POP (operands
[1]) && H_REG_P (operands
[0]))
3420 cc_status
= cc_prev_status
;
3421 switch (REGNO (operands
[0]))
3425 output_asm_insn ("pul%0", operands
);
3428 output_asm_insn ("pula", operands
);
3429 output_asm_insn ("pulb", operands
);
3436 /* Some moves to a hard register are special. Not all of them
3437 are really supported and we have to use a temporary
3438 location to provide them (either the stack of a temp var). */
3439 if (H_REG_P (operands
[0]))
3441 switch (REGNO (operands
[0]))
3444 if (X_REG_P (operands
[1]))
3446 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3448 m68hc11_output_swap (insn
, operands
);
3450 else if (next_insn_test_reg (insn
, operands
[0]))
3452 output_asm_insn ("stx\t%t0\n\tldd\t%t0", operands
);
3456 m68hc11_notice_keep_cc (operands
[0]);
3457 output_asm_insn ("pshx\n\tpula\n\tpulb", operands
);
3460 else if (Y_REG_P (operands
[1]))
3462 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3464 m68hc11_output_swap (insn
, operands
);
3468 /* %t means *ZTMP scratch register. */
3469 output_asm_insn ("sty\t%t1", operands
);
3470 output_asm_insn ("ldd\t%t1", operands
);
3473 else if (SP_REG_P (operands
[1]))
3478 if (optimize
== 0 || dead_register_here (insn
, ix_reg
) == 0)
3479 output_asm_insn ("xgdx", operands
);
3480 output_asm_insn ("tsx", operands
);
3481 output_asm_insn ("xgdx", operands
);
3483 else if (IS_STACK_POP (operands
[1]))
3485 output_asm_insn ("pula\n\tpulb", operands
);
3487 else if (GET_CODE (operands
[1]) == CONST_INT
3488 && INTVAL (operands
[1]) == 0)
3490 output_asm_insn ("clra\n\tclrb", operands
);
3494 output_asm_insn ("ldd\t%1", operands
);
3499 if (D_REG_P (operands
[1]))
3501 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3503 m68hc11_output_swap (insn
, operands
);
3505 else if (next_insn_test_reg (insn
, operands
[0]))
3507 output_asm_insn ("std\t%t0\n\tldx\t%t0", operands
);
3511 m68hc11_notice_keep_cc (operands
[0]);
3512 output_asm_insn ("pshb", operands
);
3513 output_asm_insn ("psha", operands
);
3514 output_asm_insn ("pulx", operands
);
3517 else if (Y_REG_P (operands
[1]))
3519 /* When both D and Y are dead, use the sequence xgdy, xgdx
3520 to move Y into X. The D and Y registers are modified. */
3521 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
)
3522 && dead_register_here (insn
, d_reg
))
3524 output_asm_insn ("xgdy", operands
);
3525 output_asm_insn ("xgdx", operands
);
3528 else if (!optimize_size
)
3530 output_asm_insn ("sty\t%t1", operands
);
3531 output_asm_insn ("ldx\t%t1", operands
);
3536 output_asm_insn ("pshy", operands
);
3537 output_asm_insn ("pulx", operands
);
3540 else if (SP_REG_P (operands
[1]))
3542 /* tsx, tsy preserve the flags */
3543 cc_status
= cc_prev_status
;
3544 output_asm_insn ("tsx", operands
);
3548 output_asm_insn ("ldx\t%1", operands
);
3553 if (D_REG_P (operands
[1]))
3555 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3557 m68hc11_output_swap (insn
, operands
);
3561 output_asm_insn ("std\t%t1", operands
);
3562 output_asm_insn ("ldy\t%t1", operands
);
3565 else if (X_REG_P (operands
[1]))
3567 /* When both D and X are dead, use the sequence xgdx, xgdy
3568 to move X into Y. The D and X registers are modified. */
3569 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
)
3570 && dead_register_here (insn
, d_reg
))
3572 output_asm_insn ("xgdx", operands
);
3573 output_asm_insn ("xgdy", operands
);
3576 else if (!optimize_size
)
3578 output_asm_insn ("stx\t%t1", operands
);
3579 output_asm_insn ("ldy\t%t1", operands
);
3584 output_asm_insn ("pshx", operands
);
3585 output_asm_insn ("puly", operands
);
3588 else if (SP_REG_P (operands
[1]))
3590 /* tsx, tsy preserve the flags */
3591 cc_status
= cc_prev_status
;
3592 output_asm_insn ("tsy", operands
);
3596 output_asm_insn ("ldy\t%1", operands
);
3600 case HARD_SP_REGNUM
:
3601 if (D_REG_P (operands
[1]))
3603 m68hc11_notice_keep_cc (operands
[0]);
3604 output_asm_insn ("xgdx", operands
);
3605 output_asm_insn ("txs", operands
);
3606 output_asm_insn ("xgdx", operands
);
3608 else if (X_REG_P (operands
[1]))
3610 /* tys, txs preserve the flags */
3611 cc_status
= cc_prev_status
;
3612 output_asm_insn ("txs", operands
);
3614 else if (Y_REG_P (operands
[1]))
3616 /* tys, txs preserve the flags */
3617 cc_status
= cc_prev_status
;
3618 output_asm_insn ("tys", operands
);
3622 /* lds sets the flags but the des does not. */
3624 output_asm_insn ("lds\t%1", operands
);
3625 output_asm_insn ("des", operands
);
3630 fatal_insn ("invalid register in the move instruction", insn
);
3635 if (SP_REG_P (operands
[1]) && REG_P (operands
[0])
3636 && REGNO (operands
[0]) == HARD_FRAME_POINTER_REGNUM
)
3638 output_asm_insn ("sts\t%0", operands
);
3642 if (IS_STACK_PUSH (operands
[0]) && H_REG_P (operands
[1]))
3644 cc_status
= cc_prev_status
;
3645 switch (REGNO (operands
[1]))
3649 output_asm_insn ("psh%1", operands
);
3652 output_asm_insn ("pshb", operands
);
3653 output_asm_insn ("psha", operands
);
3661 /* Operand 1 must be a hard register. */
3662 if (!H_REG_P (operands
[1]))
3664 fatal_insn ("invalid operand in the instruction", insn
);
3667 reg
= REGNO (operands
[1]);
3671 output_asm_insn ("std\t%0", operands
);
3675 output_asm_insn ("stx\t%0", operands
);
3679 output_asm_insn ("sty\t%0", operands
);
3682 case HARD_SP_REGNUM
:
3686 if (REG_P (operands
[0]) && REGNO (operands
[0]) == SOFT_TMP_REGNUM
)
3688 output_asm_insn ("pshx", operands
);
3689 output_asm_insn ("tsx", operands
);
3690 output_asm_insn ("inx", operands
);
3691 output_asm_insn ("inx", operands
);
3692 output_asm_insn ("stx\t%0", operands
);
3693 output_asm_insn ("pulx", operands
);
3696 else if (reg_mentioned_p (ix_reg
, operands
[0]))
3698 output_asm_insn ("sty\t%t0", operands
);
3699 output_asm_insn ("tsy", operands
);
3700 output_asm_insn ("sty\t%0", operands
);
3701 output_asm_insn ("ldy\t%t0", operands
);
3705 output_asm_insn ("stx\t%t0", operands
);
3706 output_asm_insn ("tsx", operands
);
3707 output_asm_insn ("stx\t%0", operands
);
3708 output_asm_insn ("ldx\t%t0", operands
);
3714 fatal_insn ("invalid register in the move instruction", insn
);
3720 m68hc11_gen_movqi (rtx insn
, rtx
*operands
)
3722 /* Move a register or memory to the same location.
3723 This is possible because such insn can appear
3724 in a non-optimizing mode. */
3725 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3727 cc_status
= cc_prev_status
;
3734 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3736 m68hc11_notice_keep_cc (operands
[0]);
3737 output_asm_insn ("tfr\t%1,%0", operands
);
3739 else if (H_REG_P (operands
[0]))
3741 if (Q_REG_P (operands
[0]))
3742 output_asm_insn ("lda%0\t%b1", operands
);
3743 else if (D_REG_P (operands
[0]))
3744 output_asm_insn ("ldab\t%b1", operands
);
3748 else if (H_REG_P (operands
[1]))
3750 if (Q_REG_P (operands
[1]))
3751 output_asm_insn ("sta%1\t%b0", operands
);
3752 else if (D_REG_P (operands
[1]))
3753 output_asm_insn ("stab\t%b0", operands
);
3759 rtx from
= operands
[1];
3760 rtx to
= operands
[0];
3762 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3763 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3764 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3765 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3771 ops
[0] = operands
[2];
3774 m68hc11_gen_movqi (insn
, ops
);
3776 ops
[1] = operands
[2];
3777 m68hc11_gen_movqi (insn
, ops
);
3781 /* !!!! SCz wrong here. */
3782 fatal_insn ("move insn not handled", insn
);
3787 if (GET_CODE (from
) == CONST_INT
&& INTVAL (from
) == 0)
3789 output_asm_insn ("clr\t%b0", operands
);
3793 m68hc11_notice_keep_cc (operands
[0]);
3794 output_asm_insn ("movb\t%b1,%b0", operands
);
3802 if (H_REG_P (operands
[0]))
3804 switch (REGNO (operands
[0]))
3808 if (X_REG_P (operands
[1]))
3810 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3812 m68hc11_output_swap (insn
, operands
);
3816 output_asm_insn ("stx\t%t1", operands
);
3817 output_asm_insn ("ldab\t%T0", operands
);
3820 else if (Y_REG_P (operands
[1]))
3822 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3824 m68hc11_output_swap (insn
, operands
);
3828 output_asm_insn ("sty\t%t1", operands
);
3829 output_asm_insn ("ldab\t%T0", operands
);
3832 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3833 && !DA_REG_P (operands
[1]))
3835 output_asm_insn ("ldab\t%b1", operands
);
3837 else if (DA_REG_P (operands
[1]))
3839 output_asm_insn ("tab", operands
);
3843 cc_status
= cc_prev_status
;
3849 if (X_REG_P (operands
[1]))
3851 output_asm_insn ("stx\t%t1", operands
);
3852 output_asm_insn ("ldaa\t%T0", operands
);
3854 else if (Y_REG_P (operands
[1]))
3856 output_asm_insn ("sty\t%t1", operands
);
3857 output_asm_insn ("ldaa\t%T0", operands
);
3859 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3860 && !DA_REG_P (operands
[1]))
3862 output_asm_insn ("ldaa\t%b1", operands
);
3864 else if (!DA_REG_P (operands
[1]))
3866 output_asm_insn ("tba", operands
);
3870 cc_status
= cc_prev_status
;
3875 if (D_REG_P (operands
[1]))
3877 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3879 m68hc11_output_swap (insn
, operands
);
3883 output_asm_insn ("stab\t%T1", operands
);
3884 output_asm_insn ("ldx\t%t1", operands
);
3888 else if (Y_REG_P (operands
[1]))
3890 output_asm_insn ("sty\t%t0", operands
);
3891 output_asm_insn ("ldx\t%t0", operands
);
3893 else if (GET_CODE (operands
[1]) == CONST_INT
)
3895 output_asm_insn ("ldx\t%1", operands
);
3897 else if (dead_register_here (insn
, d_reg
))
3899 output_asm_insn ("ldab\t%b1", operands
);
3900 output_asm_insn ("xgdx", operands
);
3902 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3904 output_asm_insn ("xgdx", operands
);
3905 output_asm_insn ("ldab\t%b1", operands
);
3906 output_asm_insn ("xgdx", operands
);
3910 output_asm_insn ("pshb", operands
);
3911 output_asm_insn ("ldab\t%b1", operands
);
3912 output_asm_insn ("stab\t%T1", operands
);
3913 output_asm_insn ("ldx\t%t1", operands
);
3914 output_asm_insn ("pulb", operands
);
3920 if (D_REG_P (operands
[1]))
3922 output_asm_insn ("stab\t%T1", operands
);
3923 output_asm_insn ("ldy\t%t1", operands
);
3926 else if (X_REG_P (operands
[1]))
3928 output_asm_insn ("stx\t%t1", operands
);
3929 output_asm_insn ("ldy\t%t1", operands
);
3932 else if (GET_CODE (operands
[1]) == CONST_INT
)
3934 output_asm_insn ("ldy\t%1", operands
);
3936 else if (dead_register_here (insn
, d_reg
))
3938 output_asm_insn ("ldab\t%b1", operands
);
3939 output_asm_insn ("xgdy", operands
);
3941 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3943 output_asm_insn ("xgdy", operands
);
3944 output_asm_insn ("ldab\t%b1", operands
);
3945 output_asm_insn ("xgdy", operands
);
3949 output_asm_insn ("pshb", operands
);
3950 output_asm_insn ("ldab\t%b1", operands
);
3951 output_asm_insn ("stab\t%T1", operands
);
3952 output_asm_insn ("ldy\t%t1", operands
);
3953 output_asm_insn ("pulb", operands
);
3959 fatal_insn ("invalid register in the instruction", insn
);
3963 else if (H_REG_P (operands
[1]))
3965 switch (REGNO (operands
[1]))
3969 output_asm_insn ("stab\t%b0", operands
);
3973 output_asm_insn ("staa\t%b0", operands
);
3977 output_asm_insn ("xgdx\n\tstab\t%b0\n\txgdx", operands
);
3981 output_asm_insn ("xgdy\n\tstab\t%b0\n\txgdy", operands
);
3985 fatal_insn ("invalid register in the move instruction", insn
);
3992 fatal_insn ("operand 1 must be a hard register", insn
);
3996 /* Generate the code for a ROTATE or ROTATERT on a QI or HI mode.
3997 The source and destination must be D or A and the shift must
4000 m68hc11_gen_rotate (enum rtx_code code
, rtx insn
, rtx operands
[])
4004 if (GET_CODE (operands
[2]) != CONST_INT
4005 || (!D_REG_P (operands
[0]) && !DA_REG_P (operands
[0])))
4006 fatal_insn ("invalid rotate insn", insn
);
4008 val
= INTVAL (operands
[2]);
4009 if (code
== ROTATERT
)
4010 val
= GET_MODE_SIZE (GET_MODE (operands
[0])) * BITS_PER_UNIT
- val
;
4012 if (GET_MODE (operands
[0]) != QImode
)
4015 /* Rotate by 8-bits if the shift is within [5..11]. */
4016 if (val
>= 5 && val
<= 11)
4019 output_asm_insn ("exg\ta,b", operands
);
4022 output_asm_insn ("psha", operands
);
4023 output_asm_insn ("tba", operands
);
4024 output_asm_insn ("pulb", operands
);
4029 /* If the shift is big, invert the rotation. */
4039 /* Set the carry to bit-15, but don't change D yet. */
4040 if (GET_MODE (operands
[0]) != QImode
)
4042 output_asm_insn ("asra", operands
);
4043 output_asm_insn ("rola", operands
);
4046 /* Rotate B first to move the carry to bit-0. */
4047 if (D_REG_P (operands
[0]))
4048 output_asm_insn ("rolb", operands
);
4050 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
4051 output_asm_insn ("rola", operands
);
4058 /* Set the carry to bit-8 of D. */
4059 if (GET_MODE (operands
[0]) != QImode
)
4060 output_asm_insn ("tap", operands
);
4062 /* Rotate B first to move the carry to bit-7. */
4063 if (D_REG_P (operands
[0]))
4064 output_asm_insn ("rorb", operands
);
4066 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
4067 output_asm_insn ("rora", operands
);
4074 /* Store in cc_status the expressions that the condition codes will
4075 describe after execution of an instruction whose pattern is EXP.
4076 Do not alter them if the instruction would not alter the cc's. */
4079 m68hc11_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
4081 /* recognize SET insn's. */
4082 if (GET_CODE (exp
) == SET
)
4084 /* Jumps do not alter the cc's. */
4085 if (SET_DEST (exp
) == pc_rtx
)
4088 /* NOTE: most instructions don't affect the carry bit, but the
4089 bhi/bls/bhs/blo instructions use it. This isn't mentioned in
4090 the conditions.h header. */
4092 /* Function calls clobber the cc's. */
4093 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
4098 /* Tests and compares set the cc's in predictable ways. */
4099 else if (SET_DEST (exp
) == cc0_rtx
)
4101 cc_status
.flags
= 0;
4102 cc_status
.value1
= XEXP (exp
, 0);
4103 cc_status
.value2
= XEXP (exp
, 1);
4107 /* All other instructions affect the condition codes. */
4108 cc_status
.flags
= 0;
4109 cc_status
.value1
= XEXP (exp
, 0);
4110 cc_status
.value2
= XEXP (exp
, 1);
4115 /* Default action if we haven't recognized something
4116 and returned earlier. */
4120 if (cc_status
.value2
!= 0)
4121 switch (GET_CODE (cc_status
.value2
))
4123 /* These logical operations can generate several insns.
4124 The flags are setup according to what is generated. */
4130 /* The (not ...) generates several 'com' instructions for
4131 non QImode. We have to invalidate the flags. */
4133 if (GET_MODE (cc_status
.value2
) != QImode
)
4145 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4146 cc_status
.flags
|= CC_NO_OVERFLOW
;
4149 /* The asl sets the overflow bit in such a way that this
4150 makes the flags unusable for a next compare insn. */
4154 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4155 cc_status
.flags
|= CC_NO_OVERFLOW
;
4158 /* A load/store instruction does not affect the carry. */
4163 cc_status
.flags
|= CC_NO_OVERFLOW
;
4169 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4171 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4172 cc_status
.value2
= 0;
4174 else if (cc_status
.value1
&& side_effects_p (cc_status
.value1
))
4175 cc_status
.value1
= 0;
4177 else if (cc_status
.value2
&& side_effects_p (cc_status
.value2
))
4178 cc_status
.value2
= 0;
4181 /* The current instruction does not affect the flags but changes
4182 the register 'reg'. See if the previous flags can be kept for the
4183 next instruction to avoid a comparison. */
4185 m68hc11_notice_keep_cc (rtx reg
)
4188 || cc_prev_status
.value1
== 0
4189 || rtx_equal_p (reg
, cc_prev_status
.value1
)
4190 || (cc_prev_status
.value2
4191 && reg_mentioned_p (reg
, cc_prev_status
.value2
)))
4194 cc_status
= cc_prev_status
;
4199 /* Machine Specific Reorg. */
4201 /* Z register replacement:
4203 GCC treats the Z register as an index base address register like
4204 X or Y. In general, it uses it during reload to compute the address
4205 of some operand. This helps the reload pass to avoid to fall into the
4206 register spill failure.
4208 The Z register is in the A_REGS class. In the machine description,
4209 the 'A' constraint matches it. The 'x' or 'y' constraints do not.
4211 It can appear everywhere an X or Y register can appear, except for
4212 some templates in the clobber section (when a clobber of X or Y is asked).
4213 For a given instruction, the template must ensure that no more than
4214 2 'A' registers are used. Otherwise, the register replacement is not
4217 To replace the Z register, the algorithm is not terrific:
4218 1. Insns that do not use the Z register are not changed
4219 2. When a Z register is used, we scan forward the insns to see
4220 a potential register to use: either X or Y and sometimes D.
4221 We stop when a call, a label or a branch is seen, or when we
4222 detect that both X and Y are used (probably at different times, but it does
4224 3. The register that will be used for the replacement of Z is saved
4225 in a .page0 register or on the stack. If the first instruction that
4226 used Z, uses Z as an input, the value is loaded from another .page0
4227 register. The replacement register is pushed on the stack in the
4228 rare cases where a compare insn uses Z and we couldn't find if X/Y
4230 4. The Z register is replaced in all instructions until we reach
4231 the end of the Z-block, as detected by step 2.
4232 5. If we detect that Z is still alive, its value is saved.
4233 If the replacement register is alive, its old value is loaded.
4235 The Z register can be disabled with -ffixed-z.
4245 int must_restore_reg
;
4256 int save_before_last
;
4257 int z_loaded_with_sp
;
4260 static int m68hc11_check_z_replacement (rtx
, struct replace_info
*);
4261 static void m68hc11_find_z_replacement (rtx
, struct replace_info
*);
4262 static void m68hc11_z_replacement (rtx
);
4263 static void m68hc11_reassign_regs (rtx
);
4265 int z_replacement_completed
= 0;
4267 /* Analyze the insn to find out which replacement register to use and
4268 the boundaries of the replacement.
4269 Returns 0 if we reached the last insn to be replaced, 1 if we can
4270 continue replacement in next insns. */
4273 m68hc11_check_z_replacement (rtx insn
, struct replace_info
*info
)
4275 int this_insn_uses_ix
;
4276 int this_insn_uses_iy
;
4277 int this_insn_uses_z
;
4278 int this_insn_uses_z_in_dst
;
4279 int this_insn_uses_d
;
4283 /* A call is said to clobber the Z register, we don't need
4284 to save the value of Z. We also don't need to restore
4285 the replacement register (unless it is used by the call). */
4286 if (GET_CODE (insn
) == CALL_INSN
)
4288 body
= PATTERN (insn
);
4290 info
->can_use_d
= 0;
4292 /* If the call is an indirect call with Z, we have to use the
4293 Y register because X can be used as an input (D+X).
4294 We also must not save Z nor restore Y. */
4295 if (reg_mentioned_p (z_reg
, body
))
4297 insn
= NEXT_INSN (insn
);
4300 info
->found_call
= 1;
4301 info
->must_restore_reg
= 0;
4302 info
->last
= NEXT_INSN (insn
);
4304 info
->need_save_z
= 0;
4307 if (GET_CODE (insn
) == CODE_LABEL
4308 || GET_CODE (insn
) == BARRIER
|| GET_CODE (insn
) == ASM_INPUT
)
4311 if (GET_CODE (insn
) == JUMP_INSN
)
4313 if (reg_mentioned_p (z_reg
, insn
) == 0)
4316 info
->can_use_d
= 0;
4317 info
->must_save_reg
= 0;
4318 info
->must_restore_reg
= 0;
4319 info
->need_save_z
= 0;
4320 info
->last
= NEXT_INSN (insn
);
4323 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4328 /* Z register dies here. */
4329 z_dies_here
= find_regno_note (insn
, REG_DEAD
, HARD_Z_REGNUM
) != NULL
;
4331 body
= PATTERN (insn
);
4332 if (GET_CODE (body
) == SET
)
4334 rtx src
= XEXP (body
, 1);
4335 rtx dst
= XEXP (body
, 0);
4337 /* Condition code is set here. We have to restore the X/Y and
4338 save into Z before any test/compare insn because once we save/restore
4339 we can change the condition codes. When the compare insn uses Z and
4340 we can't use X/Y, the comparison is made with the *ZREG soft register
4341 (this is supported by cmphi, cmpqi, tsthi, tstqi patterns). */
4344 if ((GET_CODE (src
) == REG
&& REGNO (src
) == HARD_Z_REGNUM
)
4345 || (GET_CODE (src
) == COMPARE
&&
4346 ((rtx_equal_p (XEXP (src
, 0), z_reg
)
4347 && H_REG_P (XEXP (src
, 1)))
4348 || (rtx_equal_p (XEXP (src
, 1), z_reg
)
4349 && H_REG_P (XEXP (src
, 0))))))
4351 if (insn
== info
->first
)
4353 info
->must_load_z
= 0;
4354 info
->must_save_reg
= 0;
4355 info
->must_restore_reg
= 0;
4356 info
->need_save_z
= 0;
4357 info
->found_call
= 1;
4358 info
->regno
= SOFT_Z_REGNUM
;
4359 info
->last
= NEXT_INSN (insn
);
4363 if (reg_mentioned_p (z_reg
, src
) == 0)
4365 info
->can_use_d
= 0;
4369 if (insn
!= info
->first
)
4372 /* Compare insn which uses Z. We have to save/restore the X/Y
4373 register without modifying the condition codes. For this
4374 we have to use a push/pop insn. */
4375 info
->must_push_reg
= 1;
4379 /* Z reg is set to something new. We don't need to load it. */
4382 if (!reg_mentioned_p (z_reg
, src
))
4384 /* Z reg is used before being set. Treat this as
4385 a new sequence of Z register replacement. */
4386 if (insn
!= info
->first
)
4390 info
->must_load_z
= 0;
4392 info
->z_set_count
++;
4393 info
->z_value
= src
;
4395 info
->z_loaded_with_sp
= 1;
4397 else if (reg_mentioned_p (z_reg
, dst
))
4398 info
->can_use_d
= 0;
4400 this_insn_uses_d
= reg_mentioned_p (d_reg
, src
)
4401 | reg_mentioned_p (d_reg
, dst
);
4402 this_insn_uses_ix
= reg_mentioned_p (ix_reg
, src
)
4403 | reg_mentioned_p (ix_reg
, dst
);
4404 this_insn_uses_iy
= reg_mentioned_p (iy_reg
, src
)
4405 | reg_mentioned_p (iy_reg
, dst
);
4406 this_insn_uses_z
= reg_mentioned_p (z_reg
, src
);
4408 /* If z is used as an address operand (like (MEM (reg z))),
4409 we can't replace it with d. */
4410 if (this_insn_uses_z
&& !Z_REG_P (src
)
4411 && !(m68hc11_arith_operator (src
, GET_MODE (src
))
4412 && Z_REG_P (XEXP (src
, 0))
4413 && !reg_mentioned_p (z_reg
, XEXP (src
, 1))
4414 && insn
== info
->first
4415 && dead_register_here (insn
, d_reg
)))
4416 info
->can_use_d
= 0;
4418 this_insn_uses_z_in_dst
= reg_mentioned_p (z_reg
, dst
);
4419 if (TARGET_M6812
&& !z_dies_here
4420 && ((this_insn_uses_z
&& side_effects_p (src
))
4421 || (this_insn_uses_z_in_dst
&& side_effects_p (dst
))))
4423 info
->need_save_z
= 1;
4424 info
->z_set_count
++;
4426 this_insn_uses_z
|= this_insn_uses_z_in_dst
;
4428 if (this_insn_uses_z
&& this_insn_uses_ix
&& this_insn_uses_iy
)
4430 fatal_insn ("registers IX, IY and Z used in the same INSN", insn
);
4433 if (this_insn_uses_d
)
4434 info
->can_use_d
= 0;
4436 /* IX and IY are used at the same time, we have to restore
4437 the value of the scratch register before this insn. */
4438 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4443 if (this_insn_uses_ix
&& X_REG_P (dst
) && GET_MODE (dst
) == SImode
)
4444 info
->can_use_d
= 0;
4446 if (info
->x_used
== 0 && this_insn_uses_ix
)
4450 /* We have a (set (REG:HI X) (REG:HI Z)).
4451 Since we use Z as the replacement register, this insn
4452 is no longer necessary. We turn it into a note. We must
4453 not reload the old value of X. */
4454 if (X_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4458 info
->need_save_z
= 0;
4461 info
->must_save_reg
= 0;
4462 info
->must_restore_reg
= 0;
4463 info
->found_call
= 1;
4464 info
->can_use_d
= 0;
4465 PUT_CODE (insn
, NOTE
);
4466 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4467 NOTE_SOURCE_FILE (insn
) = 0;
4468 info
->last
= NEXT_INSN (insn
);
4473 && (rtx_equal_p (src
, z_reg
)
4474 || (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
))))
4478 info
->need_save_z
= 0;
4481 info
->last
= NEXT_INSN (insn
);
4482 info
->must_save_reg
= 0;
4483 info
->must_restore_reg
= 0;
4485 else if (X_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4486 && !reg_mentioned_p (ix_reg
, src
))
4491 info
->need_save_z
= 0;
4493 else if (TARGET_M6812
&& side_effects_p (src
))
4496 info
->must_restore_reg
= 0;
4501 info
->save_before_last
= 1;
4503 info
->must_restore_reg
= 0;
4504 info
->last
= NEXT_INSN (insn
);
4506 else if (info
->can_use_d
)
4508 info
->last
= NEXT_INSN (insn
);
4514 if (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
)
4515 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_X_REGNUM
)
4517 info
->need_save_z
= 0;
4519 info
->last
= NEXT_INSN (insn
);
4520 info
->regno
= HARD_X_REGNUM
;
4521 info
->must_save_reg
= 0;
4522 info
->must_restore_reg
= 0;
4525 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, ix_reg
))
4527 info
->regno
= HARD_X_REGNUM
;
4528 info
->must_restore_reg
= 0;
4529 info
->must_save_reg
= 0;
4533 if (info
->y_used
== 0 && this_insn_uses_iy
)
4537 if (Y_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4541 info
->need_save_z
= 0;
4544 info
->must_save_reg
= 0;
4545 info
->must_restore_reg
= 0;
4546 info
->found_call
= 1;
4547 info
->can_use_d
= 0;
4548 PUT_CODE (insn
, NOTE
);
4549 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4550 NOTE_SOURCE_FILE (insn
) = 0;
4551 info
->last
= NEXT_INSN (insn
);
4556 && (rtx_equal_p (src
, z_reg
)
4557 || (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
))))
4562 info
->need_save_z
= 0;
4564 info
->last
= NEXT_INSN (insn
);
4565 info
->must_save_reg
= 0;
4566 info
->must_restore_reg
= 0;
4568 else if (Y_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4569 && !reg_mentioned_p (iy_reg
, src
))
4574 info
->need_save_z
= 0;
4576 else if (TARGET_M6812
&& side_effects_p (src
))
4579 info
->must_restore_reg
= 0;
4584 info
->save_before_last
= 1;
4586 info
->must_restore_reg
= 0;
4587 info
->last
= NEXT_INSN (insn
);
4589 else if (info
->can_use_d
)
4591 info
->last
= NEXT_INSN (insn
);
4598 if (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
)
4599 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_Y_REGNUM
)
4601 info
->need_save_z
= 0;
4603 info
->last
= NEXT_INSN (insn
);
4604 info
->regno
= HARD_Y_REGNUM
;
4605 info
->must_save_reg
= 0;
4606 info
->must_restore_reg
= 0;
4609 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, iy_reg
))
4611 info
->regno
= HARD_Y_REGNUM
;
4612 info
->must_restore_reg
= 0;
4613 info
->must_save_reg
= 0;
4619 info
->need_save_z
= 0;
4621 if (info
->last
== 0)
4622 info
->last
= NEXT_INSN (insn
);
4625 return info
->last
!= NULL_RTX
? 0 : 1;
4627 if (GET_CODE (body
) == PARALLEL
)
4630 char ix_clobber
= 0;
4631 char iy_clobber
= 0;
4633 this_insn_uses_iy
= 0;
4634 this_insn_uses_ix
= 0;
4635 this_insn_uses_z
= 0;
4637 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
4640 int uses_ix
, uses_iy
, uses_z
;
4642 x
= XVECEXP (body
, 0, i
);
4644 if (info
->can_use_d
&& reg_mentioned_p (d_reg
, x
))
4645 info
->can_use_d
= 0;
4647 uses_ix
= reg_mentioned_p (ix_reg
, x
);
4648 uses_iy
= reg_mentioned_p (iy_reg
, x
);
4649 uses_z
= reg_mentioned_p (z_reg
, x
);
4650 if (GET_CODE (x
) == CLOBBER
)
4652 ix_clobber
|= uses_ix
;
4653 iy_clobber
|= uses_iy
;
4654 z_clobber
|= uses_z
;
4658 this_insn_uses_ix
|= uses_ix
;
4659 this_insn_uses_iy
|= uses_iy
;
4660 this_insn_uses_z
|= uses_z
;
4662 if (uses_z
&& GET_CODE (x
) == SET
)
4664 rtx dst
= XEXP (x
, 0);
4667 info
->z_set_count
++;
4669 if (TARGET_M6812
&& uses_z
&& side_effects_p (x
))
4670 info
->need_save_z
= 1;
4673 info
->need_save_z
= 0;
4677 printf ("Uses X:%d Y:%d Z:%d CX:%d CY:%d CZ:%d\n",
4678 this_insn_uses_ix
, this_insn_uses_iy
,
4679 this_insn_uses_z
, ix_clobber
, iy_clobber
, z_clobber
);
4682 if (this_insn_uses_z
)
4683 info
->can_use_d
= 0;
4685 if (z_clobber
&& info
->first
!= insn
)
4687 info
->need_save_z
= 0;
4691 if (z_clobber
&& info
->x_used
== 0 && info
->y_used
== 0)
4693 if (this_insn_uses_z
== 0 && insn
== info
->first
)
4695 info
->must_load_z
= 0;
4697 if (dead_register_here (insn
, d_reg
))
4699 info
->regno
= HARD_D_REGNUM
;
4700 info
->must_save_reg
= 0;
4701 info
->must_restore_reg
= 0;
4703 else if (dead_register_here (insn
, ix_reg
))
4705 info
->regno
= HARD_X_REGNUM
;
4706 info
->must_save_reg
= 0;
4707 info
->must_restore_reg
= 0;
4709 else if (dead_register_here (insn
, iy_reg
))
4711 info
->regno
= HARD_Y_REGNUM
;
4712 info
->must_save_reg
= 0;
4713 info
->must_restore_reg
= 0;
4715 if (info
->regno
>= 0)
4717 info
->last
= NEXT_INSN (insn
);
4720 if (this_insn_uses_ix
== 0)
4722 info
->regno
= HARD_X_REGNUM
;
4723 info
->must_save_reg
= 1;
4724 info
->must_restore_reg
= 1;
4726 else if (this_insn_uses_iy
== 0)
4728 info
->regno
= HARD_Y_REGNUM
;
4729 info
->must_save_reg
= 1;
4730 info
->must_restore_reg
= 1;
4734 info
->regno
= HARD_D_REGNUM
;
4735 info
->must_save_reg
= 1;
4736 info
->must_restore_reg
= 1;
4738 info
->last
= NEXT_INSN (insn
);
4742 if (((info
->x_used
|| this_insn_uses_ix
) && iy_clobber
)
4743 || ((info
->y_used
|| this_insn_uses_iy
) && ix_clobber
))
4745 if (this_insn_uses_z
)
4747 if (info
->y_used
== 0 && iy_clobber
)
4749 info
->regno
= HARD_Y_REGNUM
;
4750 info
->must_save_reg
= 0;
4751 info
->must_restore_reg
= 0;
4753 if (info
->first
!= insn
4754 && ((info
->y_used
&& ix_clobber
)
4755 || (info
->x_used
&& iy_clobber
)))
4758 info
->last
= NEXT_INSN (insn
);
4759 info
->save_before_last
= 1;
4763 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4765 if (this_insn_uses_z
)
4767 fatal_insn ("cannot do z-register replacement", insn
);
4771 if (info
->x_used
== 0 && (this_insn_uses_ix
|| ix_clobber
))
4778 if (iy_clobber
|| z_clobber
)
4780 info
->last
= NEXT_INSN (insn
);
4781 info
->save_before_last
= 1;
4786 if (info
->y_used
== 0 && (this_insn_uses_iy
|| iy_clobber
))
4793 if (ix_clobber
|| z_clobber
)
4795 info
->last
= NEXT_INSN (insn
);
4796 info
->save_before_last
= 1;
4803 info
->need_save_z
= 0;
4807 if (GET_CODE (body
) == CLOBBER
)
4810 /* IX and IY are used at the same time, we have to restore
4811 the value of the scratch register before this insn. */
4812 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4816 if (info
->x_used
== 0 && this_insn_uses_ix
)
4824 if (info
->y_used
== 0 && this_insn_uses_iy
)
4838 m68hc11_find_z_replacement (rtx insn
, struct replace_info
*info
)
4842 info
->replace_reg
= NULL_RTX
;
4843 info
->must_load_z
= 1;
4844 info
->need_save_z
= 1;
4845 info
->must_save_reg
= 1;
4846 info
->must_restore_reg
= 1;
4850 info
->can_use_d
= TARGET_M6811
? 1 : 0;
4851 info
->found_call
= 0;
4855 info
->z_set_count
= 0;
4856 info
->z_value
= NULL_RTX
;
4857 info
->must_push_reg
= 0;
4858 info
->save_before_last
= 0;
4859 info
->z_loaded_with_sp
= 0;
4861 /* Scan the insn forward to find an address register that is not used.
4863 - the flow of the program changes,
4864 - when we detect that both X and Y are necessary,
4865 - when the Z register dies,
4866 - when the condition codes are set. */
4868 for (; insn
&& info
->z_died
== 0; insn
= NEXT_INSN (insn
))
4870 if (m68hc11_check_z_replacement (insn
, info
) == 0)
4874 /* May be we can use Y or X if they contain the same value as Z.
4875 This happens very often after the reload. */
4876 if (info
->z_set_count
== 1)
4878 rtx p
= info
->first
;
4883 v
= find_last_value (iy_reg
, &p
, insn
, 1);
4885 else if (info
->y_used
)
4887 v
= find_last_value (ix_reg
, &p
, insn
, 1);
4889 if (v
&& (v
!= iy_reg
&& v
!= ix_reg
) && rtx_equal_p (v
, info
->z_value
))
4892 info
->regno
= HARD_Y_REGNUM
;
4894 info
->regno
= HARD_X_REGNUM
;
4895 info
->must_load_z
= 0;
4896 info
->must_save_reg
= 0;
4897 info
->must_restore_reg
= 0;
4898 info
->found_call
= 1;
4901 if (info
->z_set_count
== 0)
4902 info
->need_save_z
= 0;
4905 info
->need_save_z
= 0;
4907 if (info
->last
== 0)
4910 if (info
->regno
>= 0)
4913 info
->replace_reg
= gen_rtx_REG (HImode
, reg
);
4915 else if (info
->can_use_d
)
4917 reg
= HARD_D_REGNUM
;
4918 info
->replace_reg
= d_reg
;
4920 else if (info
->x_used
)
4922 reg
= HARD_Y_REGNUM
;
4923 info
->replace_reg
= iy_reg
;
4927 reg
= HARD_X_REGNUM
;
4928 info
->replace_reg
= ix_reg
;
4932 if (info
->must_save_reg
&& info
->must_restore_reg
)
4934 if (insn
&& dead_register_here (insn
, info
->replace_reg
))
4936 info
->must_save_reg
= 0;
4937 info
->must_restore_reg
= 0;
4942 /* The insn uses the Z register. Find a replacement register for it
4943 (either X or Y) and replace it in the insn and the next ones until
4944 the flow changes or the replacement register is used. Instructions
4945 are emitted before and after the Z-block to preserve the value of
4946 Z and of the replacement register. */
4949 m68hc11_z_replacement (rtx insn
)
4953 struct replace_info info
;
4955 /* Find trivial case where we only need to replace z with the
4956 equivalent soft register. */
4957 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SET
)
4959 rtx body
= PATTERN (insn
);
4960 rtx src
= XEXP (body
, 1);
4961 rtx dst
= XEXP (body
, 0);
4963 if (Z_REG_P (dst
) && (H_REG_P (src
) && !SP_REG_P (src
)))
4965 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4968 else if (Z_REG_P (src
)
4969 && ((H_REG_P (dst
) && !SP_REG_P (src
)) || dst
== cc0_rtx
))
4971 XEXP (body
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4974 else if (D_REG_P (dst
)
4975 && m68hc11_arith_operator (src
, GET_MODE (src
))
4976 && D_REG_P (XEXP (src
, 0)) && Z_REG_P (XEXP (src
, 1)))
4978 XEXP (src
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4981 else if (Z_REG_P (dst
) && GET_CODE (src
) == CONST_INT
4982 && INTVAL (src
) == 0)
4984 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4985 /* Force it to be re-recognized. */
4986 INSN_CODE (insn
) = -1;
4991 m68hc11_find_z_replacement (insn
, &info
);
4993 replace_reg
= info
.replace_reg
;
4994 replace_reg_qi
= NULL_RTX
;
4996 /* Save the X register in a .page0 location. */
4997 if (info
.must_save_reg
&& !info
.must_push_reg
)
5001 if (info
.must_push_reg
&& 0)
5002 dst
= gen_rtx_MEM (HImode
,
5003 gen_rtx_PRE_DEC (HImode
,
5004 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
5006 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
5008 emit_insn_before (gen_movhi (dst
,
5009 gen_rtx_REG (HImode
, info
.regno
)), insn
);
5011 if (info
.must_load_z
&& !info
.must_push_reg
)
5013 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
5014 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
)),
5019 /* Replace all occurrence of Z by replace_reg.
5020 Stop when the last instruction to replace is reached.
5021 Also stop when we detect a change in the flow (but it's not
5022 necessary; just safeguard). */
5024 for (; insn
&& insn
!= info
.last
; insn
= NEXT_INSN (insn
))
5028 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == BARRIER
)
5031 if (GET_CODE (insn
) != INSN
5032 && GET_CODE (insn
) != CALL_INSN
&& GET_CODE (insn
) != JUMP_INSN
)
5035 body
= PATTERN (insn
);
5036 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
5037 || GET_CODE (body
) == ASM_OPERANDS
5038 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
5042 if (debug_m6811
&& reg_mentioned_p (replace_reg
, body
))
5044 printf ("Reg mentioned here...:\n");
5049 /* Stack pointer was decremented by 2 due to the push.
5050 Correct that by adding 2 to the destination. */
5051 if (info
.must_push_reg
5052 && info
.z_loaded_with_sp
&& GET_CODE (body
) == SET
)
5056 src
= SET_SRC (body
);
5057 dst
= SET_DEST (body
);
5058 if (SP_REG_P (src
) && Z_REG_P (dst
))
5059 emit_insn_after (gen_addhi3 (dst
, dst
, const2_rtx
), insn
);
5062 /* Replace any (REG:HI Z) occurrence by either X or Y. */
5063 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
5065 INSN_CODE (insn
) = -1;
5066 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
5067 fatal_insn ("cannot do z-register replacement", insn
);
5070 /* Likewise for (REG:QI Z). */
5071 if (reg_mentioned_p (z_reg
, insn
))
5073 if (replace_reg_qi
== NULL_RTX
)
5074 replace_reg_qi
= gen_rtx_REG (QImode
, REGNO (replace_reg
));
5075 validate_replace_rtx (z_reg_qi
, replace_reg_qi
, insn
);
5078 /* If there is a REG_INC note on Z, replace it with a
5079 REG_INC note on the replacement register. This is necessary
5080 to make sure that the flow pass will identify the change
5081 and it will not remove a possible insn that saves Z. */
5082 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
5084 if (REG_NOTE_KIND (note
) == REG_INC
5085 && GET_CODE (XEXP (note
, 0)) == REG
5086 && REGNO (XEXP (note
, 0)) == REGNO (z_reg
))
5088 XEXP (note
, 0) = replace_reg
;
5092 if (GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
5096 /* Save Z before restoring the old value. */
5097 if (insn
&& info
.need_save_z
&& !info
.must_push_reg
)
5099 rtx save_pos_insn
= insn
;
5101 /* If Z is clobber by the last insn, we have to save its value
5102 before the last instruction. */
5103 if (info
.save_before_last
)
5104 save_pos_insn
= PREV_INSN (save_pos_insn
);
5106 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
5107 gen_rtx_REG (HImode
, info
.regno
)),
5111 if (info
.must_push_reg
&& info
.last
)
5115 body
= PATTERN (info
.last
);
5116 new_body
= gen_rtx_PARALLEL (VOIDmode
,
5118 gen_rtx_USE (VOIDmode
,
5120 gen_rtx_USE (VOIDmode
,
5121 gen_rtx_REG (HImode
,
5123 PATTERN (info
.last
) = new_body
;
5125 /* Force recognition on insn since we changed it. */
5126 INSN_CODE (insn
) = -1;
5128 if (!validate_replace_rtx (z_reg
, replace_reg
, info
.last
))
5130 fatal_insn ("invalid Z register replacement for insn", insn
);
5132 insn
= NEXT_INSN (info
.last
);
5135 /* Restore replacement register unless it was died. */
5136 if (insn
&& info
.must_restore_reg
&& !info
.must_push_reg
)
5140 if (info
.must_push_reg
&& 0)
5141 dst
= gen_rtx_MEM (HImode
,
5142 gen_rtx_POST_INC (HImode
,
5143 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
5145 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
5147 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
5154 /* Scan all the insn and re-affects some registers
5155 - The Z register (if it was used), is affected to X or Y depending
5156 on the instruction. */
5159 m68hc11_reassign_regs (rtx first
)
5163 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
5164 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
5165 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
5166 z_reg_qi
= gen_rtx_REG (QImode
, HARD_Z_REGNUM
);
5168 /* Scan all insns to replace Z by X or Y preserving the old value
5169 of X/Y and restoring it afterward. */
5171 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5175 if (GET_CODE (insn
) == CODE_LABEL
5176 || GET_CODE (insn
) == NOTE
|| GET_CODE (insn
) == BARRIER
)
5182 body
= PATTERN (insn
);
5183 if (GET_CODE (body
) == CLOBBER
|| GET_CODE (body
) == USE
)
5186 if (GET_CODE (body
) == CONST_INT
|| GET_CODE (body
) == ASM_INPUT
5187 || GET_CODE (body
) == ASM_OPERANDS
5188 || GET_CODE (body
) == UNSPEC
|| GET_CODE (body
) == UNSPEC_VOLATILE
)
5191 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
5192 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
5195 /* If Z appears in this insn, replace it in the current insn
5196 and the next ones until the flow changes or we have to
5197 restore back the replacement register. */
5199 if (reg_mentioned_p (z_reg
, body
))
5201 m68hc11_z_replacement (insn
);
5206 printf ("insn not handled by Z replacement:\n");
5214 /* Machine-dependent reorg pass.
5215 Specific optimizations are defined here:
5216 - this pass changes the Z register into either X or Y
5217 (it preserves X/Y previous values in a memory slot in page0).
5219 When this pass is finished, the global variable
5220 'z_replacement_completed' is set to 2. */
5223 m68hc11_reorg (void)
5228 z_replacement_completed
= 0;
5229 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
5230 first
= get_insns ();
5232 /* Some RTX are shared at this point. This breaks the Z register
5233 replacement, unshare everything. */
5234 unshare_all_rtl_again (first
);
5236 /* Force a split of all splitable insn. This is necessary for the
5237 Z register replacement mechanism because we end up with basic insns. */
5238 split_all_insns_noflow ();
5241 z_replacement_completed
= 1;
5242 m68hc11_reassign_regs (first
);
5245 compute_bb_for_insn ();
5247 /* After some splitting, there are some opportunities for CSE pass.
5248 This happens quite often when 32-bit or above patterns are split. */
5249 if (optimize
> 0 && split_done
)
5251 reload_cse_regs (first
);
5254 /* Re-create the REG_DEAD notes. These notes are used in the machine
5255 description to use the best assembly directives. */
5258 /* Before recomputing the REG_DEAD notes, remove all of them.
5259 This is necessary because the reload_cse_regs() pass can
5260 have replaced some (MEM) with a register. In that case,
5261 the REG_DEAD that could exist for that register may become
5263 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5269 pnote
= ®_NOTES (insn
);
5272 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
)
5273 *pnote
= XEXP (*pnote
, 1);
5275 pnote
= &XEXP (*pnote
, 1);
5280 life_analysis (0, PROP_REG_INFO
| PROP_DEATH_NOTES
);
5283 z_replacement_completed
= 2;
5285 /* If optimizing, then go ahead and split insns that must be
5286 split after Z register replacement. This gives more opportunities
5287 for peephole (in particular for consecutives xgdx/xgdy). */
5289 split_all_insns_noflow ();
5291 /* Once insns are split after the z_replacement_completed == 2,
5292 we must not re-run the life_analysis. The xgdx/xgdy patterns
5293 are not recognized and the life_analysis pass removes some
5294 insns because it thinks some (SETs) are noops or made to dead
5295 stores (which is false due to the swap).
5297 Do a simple pass to eliminate the noop set that the final
5298 split could generate (because it was easier for split definition). */
5302 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5306 if (INSN_DELETED_P (insn
))
5311 /* Remove the (set (R) (R)) insns generated by some splits. */
5312 body
= PATTERN (insn
);
5313 if (GET_CODE (body
) == SET
5314 && rtx_equal_p (SET_SRC (body
), SET_DEST (body
)))
5316 PUT_CODE (insn
, NOTE
);
5317 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
5318 NOTE_SOURCE_FILE (insn
) = 0;
5325 /* Override memcpy */
5328 m68hc11_init_libfuncs (void)
5330 memcpy_libfunc
= init_one_libfunc ("__memcpy");
5331 memcmp_libfunc
= init_one_libfunc ("__memcmp");
5332 memset_libfunc
= init_one_libfunc ("__memset");
5337 /* Cost functions. */
5339 /* Cost of moving memory. */
5341 m68hc11_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
5342 int in ATTRIBUTE_UNUSED
)
5344 if (class <= H_REGS
&& class > NO_REGS
)
5346 if (GET_MODE_SIZE (mode
) <= 2)
5347 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5349 return COSTS_N_INSNS (2) + (reload_completed
| reload_in_progress
);
5353 if (GET_MODE_SIZE (mode
) <= 2)
5354 return COSTS_N_INSNS (3);
5356 return COSTS_N_INSNS (4);
5361 /* Cost of moving data from a register of class 'from' to on in class 'to'.
5362 Reload does not check the constraint of set insns when the two registers
5363 have a move cost of 2. Setting a higher cost will force reload to check
5366 m68hc11_register_move_cost (enum machine_mode mode
, enum reg_class from
,
5369 /* All costs are symmetric, so reduce cases by putting the
5370 lower number class as the destination. */
5373 enum reg_class tmp
= to
;
5374 to
= from
, from
= tmp
;
5377 return m68hc11_memory_move_cost (mode
, S_REGS
, 0);
5378 else if (from
<= S_REGS
)
5379 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5381 return COSTS_N_INSNS (2);
5385 /* Provide the costs of an addressing mode that contains ADDR.
5386 If ADDR is not a valid address, its cost is irrelevant. */
5389 m68hc11_address_cost (rtx addr
)
5393 switch (GET_CODE (addr
))
5396 /* Make the cost of hard registers and specially SP, FP small. */
5397 if (REGNO (addr
) < FIRST_PSEUDO_REGISTER
)
5414 register rtx plus0
= XEXP (addr
, 0);
5415 register rtx plus1
= XEXP (addr
, 1);
5417 if (GET_CODE (plus0
) != REG
)
5420 switch (GET_CODE (plus1
))
5423 if (INTVAL (plus1
) >= 2 * m68hc11_max_offset
5424 || INTVAL (plus1
) < m68hc11_min_offset
)
5426 else if (INTVAL (plus1
) >= m68hc11_max_offset
)
5430 if (REGNO (plus0
) < FIRST_PSEUDO_REGISTER
)
5452 if (SP_REG_P (XEXP (addr
, 0)))
5461 printf ("Address cost: %d for :", cost
);
5470 m68hc11_shift_cost (enum machine_mode mode
, rtx x
, int shift
)
5474 total
= rtx_cost (x
, SET
);
5476 total
+= m68hc11_cost
->shiftQI_const
[shift
% 8];
5477 else if (mode
== HImode
)
5478 total
+= m68hc11_cost
->shiftHI_const
[shift
% 16];
5479 else if (shift
== 8 || shift
== 16 || shift
== 32)
5480 total
+= m68hc11_cost
->shiftHI_const
[8];
5481 else if (shift
!= 0 && shift
!= 16 && shift
!= 32)
5483 total
+= m68hc11_cost
->shiftHI_const
[1] * shift
;
5486 /* For SI and others, the cost is higher. */
5487 if (GET_MODE_SIZE (mode
) > 2 && (shift
% 16) != 0)
5488 total
*= GET_MODE_SIZE (mode
) / 2;
5490 /* When optimizing for size, make shift more costly so that
5491 multiplications are preferred. */
5492 if (optimize_size
&& (shift
% 8) != 0)
5499 m68hc11_rtx_costs_1 (rtx x
, enum rtx_code code
,
5500 enum rtx_code outer_code ATTRIBUTE_UNUSED
)
5502 enum machine_mode mode
= GET_MODE (x
);
5513 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5515 return m68hc11_shift_cost (mode
, XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
5518 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5519 total
+= m68hc11_cost
->shift_var
;
5525 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5526 total
+= m68hc11_cost
->logical
;
5528 /* Logical instructions are byte instructions only. */
5529 total
*= GET_MODE_SIZE (mode
);
5534 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5535 total
+= m68hc11_cost
->add
;
5536 if (GET_MODE_SIZE (mode
) > 2)
5538 total
*= GET_MODE_SIZE (mode
) / 2;
5545 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5549 total
+= m68hc11_cost
->divQI
;
5553 total
+= m68hc11_cost
->divHI
;
5558 total
+= m68hc11_cost
->divSI
;
5564 /* mul instruction produces 16-bit result. */
5565 if (mode
== HImode
&& GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5566 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5567 return m68hc11_cost
->multQI
5568 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
)
5569 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
);
5571 /* emul instruction produces 32-bit result for 68HC12. */
5572 if (TARGET_M6812
&& mode
== SImode
5573 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5574 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5575 return m68hc11_cost
->multHI
5576 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
)
5577 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
);
5579 total
= rtx_cost (XEXP (x
, 0), code
) + rtx_cost (XEXP (x
, 1), code
);
5583 total
+= m68hc11_cost
->multQI
;
5587 total
+= m68hc11_cost
->multHI
;
5592 total
+= m68hc11_cost
->multSI
;
5599 extra_cost
= COSTS_N_INSNS (2);
5606 total
= extra_cost
+ rtx_cost (XEXP (x
, 0), code
);
5609 return total
+ COSTS_N_INSNS (1);
5613 return total
+ COSTS_N_INSNS (2);
5617 return total
+ COSTS_N_INSNS (4);
5619 return total
+ COSTS_N_INSNS (8);
5622 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
5623 return COSTS_N_INSNS (1);
5625 return COSTS_N_INSNS (1);
5628 return COSTS_N_INSNS (4);
5633 m68hc11_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5637 /* Constants are cheap. Moving them in registers must be avoided
5638 because most instructions do not handle two register operands. */
5644 /* Logical and arithmetic operations with a constant operand are
5645 better because they are not supported with two registers. */
5647 if (outer_code
== SET
&& x
== const0_rtx
)
5648 /* After reload, the reload_cse pass checks the cost to change
5649 a SET into a PLUS. Make const0 cheap then. */
5650 *total
= 1 - reload_completed
;
5675 *total
= m68hc11_rtx_costs_1 (x
, code
, outer_code
);
5684 /* Worker function for TARGET_ASM_FILE_START. */
5687 m68hc11_file_start (void)
5689 default_file_start ();
5691 fprintf (asm_out_file
, "\t.mode %s\n", TARGET_SHORT
? "mshort" : "mlong");
5695 /* Worker function for TARGET_ASM_CONSTRUCTOR. */
5698 m68hc11_asm_out_constructor (rtx symbol
, int priority
)
5700 default_ctor_section_asm_out_constructor (symbol
, priority
);
5701 fprintf (asm_out_file
, "\t.globl\t__do_global_ctors\n");
5704 /* Worker function for TARGET_ASM_DESTRUCTOR. */
5707 m68hc11_asm_out_destructor (rtx symbol
, int priority
)
5709 default_dtor_section_asm_out_destructor (symbol
, priority
);
5710 fprintf (asm_out_file
, "\t.globl\t__do_global_dtors\n");
5713 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5716 m68hc11_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5717 int incoming ATTRIBUTE_UNUSED
)
5719 return gen_rtx_REG (Pmode
, HARD_D_REGNUM
);
5722 /* Return true if type TYPE should be returned in memory.
5723 Blocks and data types largers than 4 bytes cannot be returned
5724 in the register (D + X = 4). */
5727 m68hc11_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
5729 if (TYPE_MODE (type
) == BLKmode
)
5731 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5732 return (size
== -1 || size
> 4);
5735 return GET_MODE_SIZE (TYPE_MODE (type
)) > 4;
5738 #include "gt-m68hc11.h"