1 /* Subroutines for code generation on Motorola 68HC11 and 68HC12.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>.
23 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
24 on gcc 2.6.3. I have used it as a starting point for this port.
25 However, this new port is a complete re-write. Its internal
26 design is completely different. The generated code is not
27 compatible with the gcc 2.6.3 port.
29 The gcc 2.6.3 port is available at:
31 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
38 #include "coretypes.h"
45 #include "hard-reg-set.h"
46 #include "insn-config.h"
47 #include "conditions.h"
49 #include "insn-attr.h"
54 #include "diagnostic-core.h"
56 #include "basic-block.h"
61 #include "target-def.h"
64 static void m68hc11_option_override (void);
65 static void emit_move_after_reload (rtx
, rtx
, rtx
);
66 static rtx
simplify_logical (enum machine_mode
, int, rtx
, rtx
*);
67 static void m68hc11_emit_logical (enum machine_mode
, enum rtx_code
, rtx
*);
68 static void m68hc11_reorg (void);
69 static bool m68hc11_legitimate_address_p_1 (enum machine_mode
, rtx
, bool);
70 static bool m68hc11_legitimate_address_p (enum machine_mode
, rtx
, bool);
71 static rtx
m68hc11_expand_compare (enum rtx_code
, rtx
, rtx
);
72 static int must_parenthesize (rtx
);
73 static int m68hc11_address_cost (rtx
, bool);
74 static int m68hc11_shift_cost (enum machine_mode
, rtx
, int);
75 static int m68hc11_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
76 static bool m68hc11_rtx_costs (rtx
, int, int, int *, bool);
77 static tree
m68hc11_handle_fntype_attribute (tree
*, tree
, tree
, int, bool *);
78 static tree
m68hc11_handle_page0_attribute (tree
*, tree
, tree
, int, bool *);
80 void create_regs_rtx (void);
82 static void asm_print_register (FILE *, int);
83 static void m68hc11_print_operand (FILE *, rtx
, int);
84 static void m68hc11_print_operand_address (FILE *, rtx
);
85 static void m68hc11_output_function_epilogue (FILE *, HOST_WIDE_INT
);
86 static void m68hc11_asm_out_constructor (rtx
, int);
87 static void m68hc11_asm_out_destructor (rtx
, int);
88 static void m68hc11_file_start (void);
89 static void m68hc11_encode_section_info (tree
, rtx
, int);
90 static const char *m68hc11_strip_name_encoding (const char* str
);
91 static unsigned int m68hc11_section_type_flags (tree
, const char*, int);
92 static int autoinc_mode (rtx
);
93 static int m68hc11_make_autoinc_notes (rtx
*, void *);
94 static void m68hc11_init_libfuncs (void);
95 static rtx
m68hc11_struct_value_rtx (tree
, int);
96 static bool m68hc11_return_in_memory (const_tree
, const_tree
);
97 static bool m68hc11_can_eliminate (const int, const int);
98 static void m68hc11_trampoline_init (rtx
, tree
, rtx
);
100 /* Must be set to 1 to produce debug messages. */
103 extern FILE *asm_out_file
;
108 rtx m68hc11_soft_tmp_reg
;
109 static GTY(()) rtx stack_push_word
;
110 static GTY(()) rtx stack_pop_word
;
111 static GTY(()) rtx z_reg
;
112 static GTY(()) rtx z_reg_qi
;
113 static int regs_inited
= 0;
115 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
116 int current_function_interrupt
;
118 /* Set to 1 by expand_prologue() when the function is a trap handler. */
119 int current_function_trap
;
121 /* Set to 1 when the current function is placed in 68HC12 banked
122 memory and must return with rtc. */
123 int current_function_far
;
125 /* Min offset that is valid for the indirect addressing mode. */
126 HOST_WIDE_INT m68hc11_min_offset
= 0;
128 /* Max offset that is valid for the indirect addressing mode. */
129 HOST_WIDE_INT m68hc11_max_offset
= 256;
131 /* The class value for base registers. */
132 enum reg_class m68hc11_base_reg_class
= A_REGS
;
134 /* The class value for index registers. This is NO_REGS for 68HC11. */
135 enum reg_class m68hc11_index_reg_class
= NO_REGS
;
137 enum reg_class m68hc11_tmp_regs_class
= NO_REGS
;
139 /* Tables that tell whether a given hard register is valid for
140 a base or an index register. It is filled at init time depending
141 on the target processor. */
142 unsigned char m68hc11_reg_valid_for_base
[FIRST_PSEUDO_REGISTER
];
143 unsigned char m68hc11_reg_valid_for_index
[FIRST_PSEUDO_REGISTER
];
145 /* A correction offset which is applied to the stack pointer.
146 This is 1 for 68HC11 and 0 for 68HC12. */
147 int m68hc11_sp_correction
;
149 int m68hc11_addr_mode
;
150 int m68hc11_mov_addr_mode
;
153 const struct processor_costs
*m68hc11_cost
;
155 /* Costs for a 68HC11. */
156 static const struct processor_costs m6811_cost
= {
161 /* non-constant shift */
164 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
165 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
166 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
169 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
170 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
171 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
172 COSTS_N_INSNS (2), COSTS_N_INSNS (4),
173 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (10),
174 COSTS_N_INSNS (8), COSTS_N_INSNS (6), COSTS_N_INSNS (4)
179 COSTS_N_INSNS (20 * 4),
181 COSTS_N_INSNS (20 * 16),
190 /* Costs for a 68HC12. */
191 static const struct processor_costs m6812_cost
= {
196 /* non-constant shift */
199 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
200 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
201 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
204 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
205 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
206 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
207 COSTS_N_INSNS (2), COSTS_N_INSNS (4), COSTS_N_INSNS (6),
208 COSTS_N_INSNS (8), COSTS_N_INSNS (10), COSTS_N_INSNS (8),
209 COSTS_N_INSNS (6), COSTS_N_INSNS (4)
216 COSTS_N_INSNS (3 * 4),
225 /* M68HC11 specific attributes. */
227 static const struct attribute_spec m68hc11_attribute_table
[] =
229 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
230 { "interrupt", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
231 { "trap", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
232 { "far", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
233 { "near", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
234 { "page0", 0, 0, false, false, false, m68hc11_handle_page0_attribute
},
235 { NULL
, 0, 0, false, false, false, NULL
}
238 /* Initialize the GCC target structure. */
239 #undef TARGET_ATTRIBUTE_TABLE
240 #define TARGET_ATTRIBUTE_TABLE m68hc11_attribute_table
242 #undef TARGET_ASM_ALIGNED_HI_OP
243 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
245 #undef TARGET_PRINT_OPERAND
246 #define TARGET_PRINT_OPERAND m68hc11_print_operand
247 #undef TARGET_PRINT_OPERAND_ADDRESS
248 #define TARGET_PRINT_OPERAND_ADDRESS m68hc11_print_operand_address
250 #undef TARGET_ASM_FUNCTION_EPILOGUE
251 #define TARGET_ASM_FUNCTION_EPILOGUE m68hc11_output_function_epilogue
253 #undef TARGET_ASM_FILE_START
254 #define TARGET_ASM_FILE_START m68hc11_file_start
255 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
256 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
258 #undef TARGET_DEFAULT_TARGET_FLAGS
259 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
261 #undef TARGET_ENCODE_SECTION_INFO
262 #define TARGET_ENCODE_SECTION_INFO m68hc11_encode_section_info
264 #undef TARGET_SECTION_TYPE_FLAGS
265 #define TARGET_SECTION_TYPE_FLAGS m68hc11_section_type_flags
267 #undef TARGET_RTX_COSTS
268 #define TARGET_RTX_COSTS m68hc11_rtx_costs
269 #undef TARGET_ADDRESS_COST
270 #define TARGET_ADDRESS_COST m68hc11_address_cost
272 #undef TARGET_MACHINE_DEPENDENT_REORG
273 #define TARGET_MACHINE_DEPENDENT_REORG m68hc11_reorg
275 #undef TARGET_INIT_LIBFUNCS
276 #define TARGET_INIT_LIBFUNCS m68hc11_init_libfuncs
278 #undef TARGET_STRUCT_VALUE_RTX
279 #define TARGET_STRUCT_VALUE_RTX m68hc11_struct_value_rtx
280 #undef TARGET_RETURN_IN_MEMORY
281 #define TARGET_RETURN_IN_MEMORY m68hc11_return_in_memory
282 #undef TARGET_CALLEE_COPIES
283 #define TARGET_CALLEE_COPIES hook_callee_copies_named
285 #undef TARGET_STRIP_NAME_ENCODING
286 #define TARGET_STRIP_NAME_ENCODING m68hc11_strip_name_encoding
288 #undef TARGET_LEGITIMATE_ADDRESS_P
289 #define TARGET_LEGITIMATE_ADDRESS_P m68hc11_legitimate_address_p
291 #undef TARGET_CAN_ELIMINATE
292 #define TARGET_CAN_ELIMINATE m68hc11_can_eliminate
294 #undef TARGET_TRAMPOLINE_INIT
295 #define TARGET_TRAMPOLINE_INIT m68hc11_trampoline_init
297 #undef TARGET_OPTION_OVERRIDE
298 #define TARGET_OPTION_OVERRIDE m68hc11_option_override
300 struct gcc_target targetm
= TARGET_INITIALIZER
;
303 m68hc11_option_override (void)
305 memset (m68hc11_reg_valid_for_index
, 0,
306 sizeof (m68hc11_reg_valid_for_index
));
307 memset (m68hc11_reg_valid_for_base
, 0, sizeof (m68hc11_reg_valid_for_base
));
309 /* Compilation with -fpic generates a wrong code. */
312 warning (0, "-f%s ignored for 68HC11/68HC12 (not supported)",
313 (flag_pic
> 1) ? "PIC" : "pic");
317 /* Do not enable -fweb because it breaks the 32-bit shift patterns
318 by breaking the match_dup of those patterns. The shift patterns
319 will no longer be recognized after that. */
322 /* Configure for a 68hc11 processor. */
325 target_flags
&= ~(TARGET_AUTO_INC_DEC
| TARGET_MIN_MAX
);
326 m68hc11_cost
= &m6811_cost
;
327 m68hc11_min_offset
= 0;
328 m68hc11_max_offset
= 256;
329 m68hc11_index_reg_class
= NO_REGS
;
330 m68hc11_base_reg_class
= A_REGS
;
331 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
332 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
333 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
334 m68hc11_sp_correction
= 1;
335 m68hc11_tmp_regs_class
= D_REGS
;
336 m68hc11_addr_mode
= ADDR_OFFSET
;
337 m68hc11_mov_addr_mode
= 0;
338 if (m68hc11_soft_reg_count
< 0)
339 m68hc11_soft_reg_count
= 4;
342 /* Configure for a 68hc12 processor. */
345 m68hc11_cost
= &m6812_cost
;
346 m68hc11_min_offset
= -65536;
347 m68hc11_max_offset
= 65536;
348 m68hc11_index_reg_class
= D_REGS
;
349 m68hc11_base_reg_class
= A_OR_SP_REGS
;
350 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
351 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
352 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
353 m68hc11_reg_valid_for_base
[HARD_SP_REGNUM
] = 1;
354 m68hc11_reg_valid_for_index
[HARD_D_REGNUM
] = 1;
355 m68hc11_sp_correction
= 0;
356 m68hc11_tmp_regs_class
= TMP_REGS
;
357 m68hc11_addr_mode
= ADDR_INDIRECT
| ADDR_OFFSET
| ADDR_CONST
358 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
359 m68hc11_mov_addr_mode
= ADDR_OFFSET
| ADDR_CONST
360 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
361 target_flags
|= MASK_NO_DIRECT_MODE
;
362 if (m68hc11_soft_reg_count
< 0)
363 m68hc11_soft_reg_count
= 0;
365 if (TARGET_LONG_CALLS
)
366 current_function_far
= 1;
372 m68hc11_conditional_register_usage (void)
376 if (m68hc11_soft_reg_count
> SOFT_REG_LAST
- SOFT_REG_FIRST
)
377 m68hc11_soft_reg_count
= SOFT_REG_LAST
- SOFT_REG_FIRST
;
379 for (i
= SOFT_REG_FIRST
+ m68hc11_soft_reg_count
; i
< SOFT_REG_LAST
; i
++)
382 call_used_regs
[i
] = 1;
385 /* For 68HC12, the Z register emulation is not necessary when the
386 frame pointer is not used. The frame pointer is eliminated and
387 replaced by the stack register (which is a BASE_REG_CLASS). */
388 if (TARGET_M6812
&& flag_omit_frame_pointer
&& optimize
)
390 fixed_regs
[HARD_Z_REGNUM
] = 1;
395 /* Reload and register operations. */
399 create_regs_rtx (void)
401 /* regs_inited = 1; */
402 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
403 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
404 d_reg
= gen_rtx_REG (HImode
, HARD_D_REGNUM
);
405 m68hc11_soft_tmp_reg
= gen_rtx_REG (HImode
, SOFT_TMP_REGNUM
);
407 stack_push_word
= gen_rtx_MEM (HImode
,
408 gen_rtx_PRE_DEC (HImode
,
409 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
410 stack_pop_word
= gen_rtx_MEM (HImode
,
411 gen_rtx_POST_INC (HImode
,
412 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
416 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
417 - 8-bit values are stored anywhere (except the SP register).
418 - 16-bit values can be stored in any register whose mode is 16
419 - 32-bit values can be stored in D, X registers or in a soft register
420 (except the last one because we need 2 soft registers)
421 - Values whose size is > 32 bit are not stored in real hard
422 registers. They may be stored in soft registers if there are
425 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
427 switch (GET_MODE_SIZE (mode
))
430 return S_REGNO_P (regno
) && m68hc11_soft_reg_count
>= 4;
433 return (X_REGNO_P (regno
)
434 || (S_REGNO_P (regno
) && m68hc11_soft_reg_count
>= 2));
437 return G_REGNO_P (regno
);
440 /* We have to accept a QImode in X or Y registers. Otherwise, the
441 reload pass will fail when some (SUBREG:QI (REG:HI X)) are defined
442 in the insns. Reload fails if the insn rejects the register class 'a'
443 as well as if it accepts it. Patterns that failed were
444 zero_extend_qihi2 and iorqi3. */
446 return G_REGNO_P (regno
) && !SP_REGNO_P (regno
);
454 m68hc11_hard_regno_rename_ok (int reg1
, int reg2
)
456 /* Don't accept renaming to Z register. We will replace it to
457 X,Y or D during machine reorg pass. */
458 if (reg2
== HARD_Z_REGNUM
)
461 /* Don't accept renaming D,X to Y register as the code will be bigger. */
462 if (TARGET_M6811
&& reg2
== HARD_Y_REGNUM
463 && (D_REGNO_P (reg1
) || X_REGNO_P (reg1
)))
470 preferred_reload_class (rtx operand
, enum reg_class rclass
)
472 enum machine_mode mode
;
474 mode
= GET_MODE (operand
);
478 printf ("Preferred reload: (class=%s): ", reg_class_names
[rclass
]);
481 if (rclass
== D_OR_A_OR_S_REGS
&& SP_REG_P (operand
))
482 return m68hc11_base_reg_class
;
484 if (rclass
>= S_REGS
&& (GET_CODE (operand
) == MEM
485 || GET_CODE (operand
) == CONST_INT
))
487 /* S_REGS class must not be used. The movhi template does not
488 work to move a memory to a soft register.
489 Restrict to a hard reg. */
494 case D_OR_A_OR_S_REGS
:
495 rclass
= A_OR_D_REGS
;
500 case D_OR_SP_OR_S_REGS
:
501 rclass
= D_OR_SP_REGS
;
503 case D_OR_Y_OR_S_REGS
:
504 rclass
= D_OR_Y_REGS
;
506 case D_OR_X_OR_S_REGS
:
507 rclass
= D_OR_X_REGS
;
522 else if (rclass
== Y_REGS
&& GET_CODE (operand
) == MEM
)
526 else if (rclass
== A_OR_D_REGS
&& GET_MODE_SIZE (mode
) == 4)
528 rclass
= D_OR_X_REGS
;
530 else if (rclass
>= S_REGS
&& S_REG_P (operand
))
536 case D_OR_A_OR_S_REGS
:
537 rclass
= A_OR_D_REGS
;
542 case D_OR_SP_OR_S_REGS
:
543 rclass
= D_OR_SP_REGS
;
545 case D_OR_Y_OR_S_REGS
:
546 rclass
= D_OR_Y_REGS
;
548 case D_OR_X_OR_S_REGS
:
549 rclass
= D_OR_X_REGS
;
564 else if (rclass
>= S_REGS
)
568 printf ("Class = %s for: ", reg_class_names
[rclass
]);
576 printf (" => class=%s\n", reg_class_names
[rclass
]);
584 /* Return 1 if the operand is a valid indexed addressing mode.
585 For 68hc11: n,r with n in [0..255] and r in A_REGS class
586 For 68hc12: n,r no constraint on the constant, r in A_REGS class. */
588 m68hc11_valid_addressing_p (rtx operand
, enum machine_mode mode
, int addr_mode
)
592 switch (GET_CODE (operand
))
595 if ((addr_mode
& ADDR_INDIRECT
) && GET_MODE_SIZE (mode
) <= 2)
596 return m68hc11_valid_addressing_p (XEXP (operand
, 0), mode
,
597 addr_mode
& (ADDR_STRICT
| ADDR_OFFSET
));
604 if (addr_mode
& ADDR_INCDEC
)
605 return m68hc11_valid_addressing_p (XEXP (operand
, 0), mode
,
606 addr_mode
& ADDR_STRICT
);
610 base
= XEXP (operand
, 0);
611 if (GET_CODE (base
) == MEM
)
614 offset
= XEXP (operand
, 1);
615 if (GET_CODE (offset
) == MEM
)
618 /* Indexed addressing mode with 2 registers. */
619 if (GET_CODE (base
) == REG
&& GET_CODE (offset
) == REG
)
621 if (!(addr_mode
& ADDR_INDEXED
))
624 addr_mode
&= ADDR_STRICT
;
625 if (REGNO_OK_FOR_BASE_P2 (REGNO (base
), addr_mode
)
626 && REGNO_OK_FOR_INDEX_P2 (REGNO (offset
), addr_mode
))
629 if (REGNO_OK_FOR_BASE_P2 (REGNO (offset
), addr_mode
)
630 && REGNO_OK_FOR_INDEX_P2 (REGNO (base
), addr_mode
))
636 if (!(addr_mode
& ADDR_OFFSET
))
639 if (GET_CODE (base
) == REG
)
641 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
644 if (!(addr_mode
& ADDR_STRICT
))
647 return REGNO_OK_FOR_BASE_P2 (REGNO (base
), 1);
650 if (GET_CODE (offset
) == REG
)
652 if (!VALID_CONSTANT_OFFSET_P (base
, mode
))
655 if (!(addr_mode
& ADDR_STRICT
))
658 return REGNO_OK_FOR_BASE_P2 (REGNO (offset
), 1);
663 return REGNO_OK_FOR_BASE_P2 (REGNO (operand
), addr_mode
& ADDR_STRICT
);
666 if (addr_mode
& ADDR_CONST
)
667 return VALID_CONSTANT_OFFSET_P (operand
, mode
);
675 /* Returns 1 if the operand fits in a 68HC11 indirect mode or in
676 a 68HC12 1-byte index addressing mode. */
678 m68hc11_small_indexed_indirect_p (rtx operand
, enum machine_mode mode
)
683 if (GET_CODE (operand
) == REG
&& reload_in_progress
684 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
685 && reg_equiv_memory_loc
[REGNO (operand
)])
687 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
688 operand
= eliminate_regs (operand
, VOIDmode
, NULL_RTX
);
691 if (GET_CODE (operand
) != MEM
)
694 operand
= XEXP (operand
, 0);
695 if (CONSTANT_ADDRESS_P (operand
))
698 if (PUSH_POP_ADDRESS_P (operand
))
701 addr_mode
= m68hc11_mov_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
702 if (!m68hc11_valid_addressing_p (operand
, mode
, addr_mode
))
705 if (TARGET_M6812
&& GET_CODE (operand
) == PLUS
706 && (reload_completed
| reload_in_progress
))
708 base
= XEXP (operand
, 0);
709 offset
= XEXP (operand
, 1);
711 /* The offset can be a symbol address and this is too big
712 for the operand constraint. */
713 if (GET_CODE (base
) != CONST_INT
&& GET_CODE (offset
) != CONST_INT
)
716 if (GET_CODE (base
) == CONST_INT
)
719 switch (GET_MODE_SIZE (mode
))
722 if (INTVAL (offset
) < -16 + 6 || INTVAL (offset
) > 15 - 6)
727 if (INTVAL (offset
) < -16 + 2 || INTVAL (offset
) > 15 - 2)
732 if (INTVAL (offset
) < -16 || INTVAL (offset
) > 15)
741 m68hc11_register_indirect_p (rtx operand
, enum machine_mode mode
)
745 if (GET_CODE (operand
) == REG
&& reload_in_progress
746 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
747 && reg_equiv_memory_loc
[REGNO (operand
)])
749 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
750 operand
= eliminate_regs (operand
, VOIDmode
, NULL_RTX
);
752 if (GET_CODE (operand
) != MEM
)
755 operand
= XEXP (operand
, 0);
756 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
757 return m68hc11_valid_addressing_p (operand
, mode
, addr_mode
);
761 m68hc11_legitimate_address_p_1 (enum machine_mode mode
, rtx operand
,
766 if (CONSTANT_ADDRESS_P (operand
) && TARGET_M6812
)
768 /* Reject the global variables if they are too wide. This forces
769 a load of their address in a register and generates smaller code. */
770 if (GET_MODE_SIZE (mode
) == 8)
775 addr_mode
= m68hc11_addr_mode
| (strict
? ADDR_STRICT
: 0);
776 if (m68hc11_valid_addressing_p (operand
, mode
, addr_mode
))
780 if (PUSH_POP_ADDRESS_P (operand
))
784 if (symbolic_memory_operand (operand
, mode
))
792 m68hc11_legitimate_address_p (enum machine_mode mode
, rtx operand
,
799 printf ("Checking: ");
804 result
= m68hc11_legitimate_address_p_1 (mode
, operand
, strict
);
808 printf (" -> %s\n", result
== 0 ? "NO" : "YES");
815 printf ("go_if_legitimate%s, ret 0: %d:",
816 (strict
? "_strict" : ""), mode
);
826 m68hc11_reload_operands (rtx operands
[])
828 enum machine_mode mode
;
830 if (regs_inited
== 0)
833 mode
= GET_MODE (operands
[1]);
835 /* Input reload of indirect addressing (MEM (PLUS (REG) (CONST))). */
836 if (A_REG_P (operands
[0]) && memory_reload_operand (operands
[1], mode
))
838 rtx big_offset
= XEXP (XEXP (operands
[1], 0), 1);
839 rtx base
= XEXP (XEXP (operands
[1], 0), 0);
841 if (GET_CODE (base
) != REG
)
848 /* If the offset is out of range, we have to compute the address
849 with a separate add instruction. We try to do this with an 8-bit
850 add on the A register. This is possible only if the lowest part
851 of the offset (i.e., big_offset % 256) is a valid constant offset
852 with respect to the mode. If it's not, we have to generate a
853 16-bit add on the D register. From:
855 (SET (REG X (MEM (PLUS (REG X) (CONST_INT 1000)))))
859 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
860 (SET (REG A) (PLUS (REG A) (CONST_INT 1000 / 256)))
861 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
862 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256)))
864 (SET (REG X) (PLUS (REG X) (CONST_INT 1000 / 256 * 256)))
865 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256))))
868 if (!VALID_CONSTANT_OFFSET_P (big_offset
, mode
))
871 rtx reg
= operands
[0];
873 int val
= INTVAL (big_offset
);
876 /* We use the 'operands[0]' as a scratch register to compute the
877 address. Make sure 'base' is in that register. */
878 if (!rtx_equal_p (base
, operands
[0]))
880 emit_move_insn (reg
, base
);
890 vh
= (val
>> 8) & 0x0FF;
894 /* Create the lowest part offset that still remains to be added.
895 If it's not a valid offset, do a 16-bit add. */
896 offset
= GEN_INT (vl
);
897 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
899 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
900 gen_rtx_PLUS (HImode
, reg
, big_offset
)));
905 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
906 gen_rtx_PLUS (HImode
, reg
,
907 GEN_INT (vh
<< 8))));
909 emit_move_insn (operands
[0],
910 gen_rtx_MEM (GET_MODE (operands
[1]),
911 gen_rtx_PLUS (Pmode
, reg
, offset
)));
916 /* Use the normal gen_movhi pattern. */
921 m68hc11_emit_libcall (const char *name
, enum rtx_code code
,
922 enum machine_mode dmode
, enum machine_mode smode
,
923 int noperands
, rtx
*operands
)
931 libcall
= gen_rtx_SYMBOL_REF (Pmode
, name
);
935 ret
= emit_library_call_value (libcall
, NULL_RTX
, LCT_CONST
,
936 dmode
, 1, operands
[1], smode
);
937 equiv
= gen_rtx_fmt_e (code
, dmode
, operands
[1]);
941 ret
= emit_library_call_value (libcall
, NULL_RTX
,
943 operands
[1], smode
, operands
[2],
945 equiv
= gen_rtx_fmt_ee (code
, dmode
, operands
[1], operands
[2]);
952 insns
= get_insns ();
954 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
957 /* Returns true if X is a PRE/POST increment decrement
958 (same as auto_inc_p() in rtlanal.c but do not take into
959 account the stack). */
961 m68hc11_auto_inc_p (rtx x
)
963 return GET_CODE (x
) == PRE_DEC
964 || GET_CODE (x
) == POST_INC
965 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_INC
;
969 /* Predicates for machine description. */
972 memory_reload_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
974 return GET_CODE (operand
) == MEM
975 && GET_CODE (XEXP (operand
, 0)) == PLUS
976 && ((GET_CODE (XEXP (XEXP (operand
, 0), 0)) == REG
977 && GET_CODE (XEXP (XEXP (operand
, 0), 1)) == CONST_INT
)
978 || (GET_CODE (XEXP (XEXP (operand
, 0), 1)) == REG
979 && GET_CODE (XEXP (XEXP (operand
, 0), 0)) == CONST_INT
));
983 m68hc11_symbolic_p (rtx operand
, enum machine_mode mode
)
985 if (GET_CODE (operand
) == MEM
)
987 rtx op
= XEXP (operand
, 0);
989 if (symbolic_memory_operand (op
, mode
))
996 m68hc11_indirect_p (rtx operand
, enum machine_mode mode
)
998 if (GET_CODE (operand
) == MEM
&& GET_MODE (operand
) == mode
)
1000 rtx op
= XEXP (operand
, 0);
1003 if (m68hc11_page0_symbol_p (op
))
1006 if (symbolic_memory_operand (op
, mode
))
1007 return TARGET_M6812
;
1009 if (reload_in_progress
)
1012 operand
= XEXP (operand
, 0);
1013 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
1014 return m68hc11_valid_addressing_p (operand
, mode
, addr_mode
);
1020 memory_indexed_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1022 if (GET_CODE (operand
) != MEM
)
1025 operand
= XEXP (operand
, 0);
1026 if (GET_CODE (operand
) == PLUS
)
1028 if (GET_CODE (XEXP (operand
, 0)) == REG
)
1029 operand
= XEXP (operand
, 0);
1030 else if (GET_CODE (XEXP (operand
, 1)) == REG
)
1031 operand
= XEXP (operand
, 1);
1033 return GET_CODE (operand
) == REG
1034 && (REGNO (operand
) >= FIRST_PSEUDO_REGISTER
1035 || A_REGNO_P (REGNO (operand
)));
1039 push_pop_operand_p (rtx operand
)
1041 if (GET_CODE (operand
) != MEM
)
1045 operand
= XEXP (operand
, 0);
1046 return PUSH_POP_ADDRESS_P (operand
);
1049 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1050 reference and a constant. */
1053 symbolic_memory_operand (rtx op
, enum machine_mode mode
)
1055 switch (GET_CODE (op
))
1063 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1064 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1065 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1067 /* ??? This clause seems to be irrelevant. */
1069 return GET_MODE (op
) == mode
;
1072 return symbolic_memory_operand (XEXP (op
, 0), mode
)
1073 && symbolic_memory_operand (XEXP (op
, 1), mode
);
1080 /* Emit the code to build the trampoline used to call a nested function.
1084 ldy #&CXT movw #&CXT,*_.d1
1085 sty *_.d1 jmp FNADDR
1090 m68hc11_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
1092 const char *static_chain_reg
= reg_names
[STATIC_CHAIN_REGNUM
];
1093 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1097 if (*static_chain_reg
== '*')
1101 mem
= adjust_address (m_tramp
, HImode
, 0);
1102 emit_move_insn (mem
, GEN_INT (0x18ce));
1103 mem
= adjust_address (m_tramp
, HImode
, 2);
1104 emit_move_insn (mem
, cxt
);
1105 mem
= adjust_address (m_tramp
, HImode
, 4);
1106 emit_move_insn (mem
, GEN_INT (0x18df));
1107 mem
= adjust_address (m_tramp
, QImode
, 6);
1108 emit_move_insn (mem
,
1109 gen_rtx_CONST (QImode
,
1110 gen_rtx_SYMBOL_REF (Pmode
,
1111 static_chain_reg
)));
1112 mem
= adjust_address (m_tramp
, QImode
, 7);
1113 emit_move_insn (mem
, GEN_INT (0x7e));
1114 mem
= adjust_address (m_tramp
, HImode
, 8);
1115 emit_move_insn (mem
, fnaddr
);
1119 mem
= adjust_address (m_tramp
, HImode
, 0);
1120 emit_move_insn (mem
, GEN_INT (0x1803));
1121 mem
= adjust_address (m_tramp
, HImode
, 2);
1122 emit_move_insn (mem
, cxt
);
1123 mem
= adjust_address (m_tramp
, HImode
, 4);
1124 emit_move_insn (mem
,
1125 gen_rtx_CONST (HImode
,
1126 gen_rtx_SYMBOL_REF (Pmode
,
1127 static_chain_reg
)));
1128 mem
= adjust_address (m_tramp
, QImode
, 6);
1129 emit_move_insn (mem
, GEN_INT (0x06));
1130 mem
= adjust_address (m_tramp
, HImode
, 7);
1131 emit_move_insn (mem
, fnaddr
);
1135 /* Declaration of types. */
1137 /* Handle an "tiny_data" attribute; arguments as in
1138 struct attribute_spec.handler. */
1140 m68hc11_handle_page0_attribute (tree
*node
, tree name
,
1141 tree args ATTRIBUTE_UNUSED
,
1142 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1146 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
1148 DECL_SECTION_NAME (decl
) = build_string (6, ".page0");
1152 warning (OPT_Wattributes
, "%qE attribute ignored",
1154 *no_add_attrs
= true;
1160 /* Keep track of the symbol which has a `trap' attribute and which uses
1161 the `swi' calling convention. Since there is only one trap, we only
1162 record one such symbol. If there are several, a warning is reported. */
1163 static rtx trap_handler_symbol
= 0;
1165 /* Handle an attribute requiring a FUNCTION_TYPE, FIELD_DECL or TYPE_DECL;
1166 arguments as in struct attribute_spec.handler. */
1168 m68hc11_handle_fntype_attribute (tree
*node
, tree name
,
1169 tree args ATTRIBUTE_UNUSED
,
1170 int flags ATTRIBUTE_UNUSED
,
1173 if (TREE_CODE (*node
) != FUNCTION_TYPE
1174 && TREE_CODE (*node
) != METHOD_TYPE
1175 && TREE_CODE (*node
) != FIELD_DECL
1176 && TREE_CODE (*node
) != TYPE_DECL
)
1178 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1180 *no_add_attrs
= true;
1185 /* Undo the effects of the above. */
1188 m68hc11_strip_name_encoding (const char *str
)
1190 return str
+ (*str
== '*' || *str
== '@' || *str
== '&');
1194 m68hc11_encode_label (tree decl
)
1196 const char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1197 int len
= strlen (str
);
1198 char *newstr
= XALLOCAVEC (char, len
+ 2);
1201 strcpy (&newstr
[1], str
);
1203 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = ggc_alloc_string (newstr
, len
+ 1);
1206 /* Return 1 if this is a symbol in page0 */
1208 m68hc11_page0_symbol_p (rtx x
)
1210 switch (GET_CODE (x
))
1213 return XSTR (x
, 0) != 0 && XSTR (x
, 0)[0] == '@';
1216 return m68hc11_page0_symbol_p (XEXP (x
, 0));
1219 if (!m68hc11_page0_symbol_p (XEXP (x
, 0)))
1222 return GET_CODE (XEXP (x
, 1)) == CONST_INT
1223 && INTVAL (XEXP (x
, 1)) < 256
1224 && INTVAL (XEXP (x
, 1)) >= 0;
1231 /* We want to recognize trap handlers so that we handle calls to traps
1232 in a special manner (by issuing the trap). This information is stored
1233 in SYMBOL_REF_FLAG. */
1236 m68hc11_encode_section_info (tree decl
, rtx rtl
, int first ATTRIBUTE_UNUSED
)
1242 if (TREE_CODE (decl
) == VAR_DECL
)
1244 if (lookup_attribute ("page0", DECL_ATTRIBUTES (decl
)) != 0)
1245 m68hc11_encode_label (decl
);
1249 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1252 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
1255 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1257 else if (lookup_attribute ("near", func_attr
) == NULL_TREE
)
1258 is_far
= TARGET_LONG_CALLS
!= 0;
1260 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1261 if (trap_handler
&& is_far
)
1263 warning (OPT_Wattributes
, "%<trap%> and %<far%> attributes are "
1264 "not compatible, ignoring %<far%>");
1269 if (trap_handler_symbol
!= 0)
1270 warning (OPT_Wattributes
, "%<trap%> attribute is already used");
1272 trap_handler_symbol
= XEXP (rtl
, 0);
1274 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = is_far
;
1278 m68hc11_section_type_flags (tree decl
, const char *name
, int reloc
)
1280 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
1282 if (strncmp (name
, ".eeprom", 7) == 0)
1284 flags
|= SECTION_WRITE
| SECTION_CODE
| SECTION_OVERRIDE
;
1291 m68hc11_is_far_symbol (rtx sym
)
1293 if (GET_CODE (sym
) == MEM
)
1294 sym
= XEXP (sym
, 0);
1296 return SYMBOL_REF_FLAG (sym
);
1300 m68hc11_is_trap_symbol (rtx sym
)
1302 if (GET_CODE (sym
) == MEM
)
1303 sym
= XEXP (sym
, 0);
1305 return trap_handler_symbol
!= 0 && rtx_equal_p (trap_handler_symbol
, sym
);
1309 /* Argument support functions. */
1311 /* Given FROM and TO register numbers, say whether this elimination is
1312 allowed. Frame pointer elimination is automatically handled.
1314 All other eliminations are valid. */
1317 m68hc11_can_eliminate (const int from
, const int to
)
1319 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1320 ? ! frame_pointer_needed
1324 /* Define the offset between two registers, one to be eliminated, and the
1325 other its replacement, at the start of a routine. */
1327 m68hc11_initial_elimination_offset (int from
, int to
)
1334 /* For a trap handler, we must take into account the registers which
1335 are pushed on the stack during the trap (except the PC). */
1336 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1337 current_function_interrupt
= lookup_attribute ("interrupt",
1338 func_attr
) != NULL_TREE
;
1339 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1341 if (lookup_attribute ("far", func_attr
) != 0)
1342 current_function_far
= 1;
1343 else if (lookup_attribute ("near", func_attr
) != 0)
1344 current_function_far
= 0;
1346 current_function_far
= (TARGET_LONG_CALLS
!= 0
1347 && !current_function_interrupt
1350 if (trap_handler
&& from
== ARG_POINTER_REGNUM
)
1353 /* For a function using 'call/rtc' we must take into account the
1354 page register which is pushed in the call. */
1355 else if (current_function_far
&& from
== ARG_POINTER_REGNUM
)
1360 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1362 /* 2 is for the saved frame.
1363 1 is for the 'sts' correction when creating the frame. */
1364 return get_frame_size () + 2 + m68hc11_sp_correction
+ size
;
1367 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1369 return m68hc11_sp_correction
;
1372 /* Push any 2 byte pseudo hard registers that we need to save. */
1373 for (regno
= SOFT_REG_FIRST
; regno
< SOFT_REG_LAST
; regno
++)
1375 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1381 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1383 return get_frame_size () + size
;
1386 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1393 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1394 for a call to a function whose data type is FNTYPE.
1395 For a library call, FNTYPE is 0. */
1398 m68hc11_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
)
1402 z_replacement_completed
= 0;
1406 /* For a library call, we must find out the type of the return value.
1407 When the return value is bigger than 4 bytes, it is returned in
1408 memory. In that case, the first argument of the library call is a
1409 pointer to the memory location. Because the first argument is passed in
1410 register D, we have to identify this, so that the first function
1411 parameter is not passed in D either. */
1417 if (libname
== 0 || GET_CODE (libname
) != SYMBOL_REF
)
1420 /* If the library ends in 'di' or in 'df', we assume it's
1421 returning some DImode or some DFmode which are 64-bit wide. */
1422 name
= XSTR (libname
, 0);
1423 len
= strlen (name
);
1425 && ((name
[len
- 2] == 'd'
1426 && (name
[len
- 1] == 'f' || name
[len
- 1] == 'i'))
1427 || (name
[len
- 3] == 'd'
1428 && (name
[len
- 2] == 'i' || name
[len
- 2] == 'f'))))
1430 /* We are in. Mark the first parameter register as already used. */
1437 ret_type
= TREE_TYPE (fntype
);
1439 if (ret_type
&& aggregate_value_p (ret_type
, fntype
))
1446 /* Update the data in CUM to advance over an argument
1447 of mode MODE and data type TYPE.
1448 (TYPE is null for libcalls where that information may not be available.) */
1451 m68hc11_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1452 tree type
, int named ATTRIBUTE_UNUSED
)
1454 if (mode
!= BLKmode
)
1456 if (cum
->words
== 0 && GET_MODE_SIZE (mode
) == 4)
1459 cum
->words
= GET_MODE_SIZE (mode
);
1463 cum
->words
+= GET_MODE_SIZE (mode
);
1464 if (cum
->words
<= HARD_REG_SIZE
)
1470 cum
->words
+= int_size_in_bytes (type
);
1475 /* Define where to put the arguments to a function.
1476 Value is zero to push the argument on the stack,
1477 or a hard register in which to store the argument.
1479 MODE is the argument's machine mode.
1480 TYPE is the data type of the argument (as a tree).
1481 This is null for libcalls where that information may
1483 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1484 the preceding args and about the function being called.
1485 NAMED is nonzero if this argument is a named parameter
1486 (otherwise it is an extra parameter matching an ellipsis). */
1489 m68hc11_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1490 tree type ATTRIBUTE_UNUSED
, int named ATTRIBUTE_UNUSED
)
1492 if (cum
->words
!= 0)
1497 if (mode
!= BLKmode
)
1499 if (GET_MODE_SIZE (mode
) == 2 * HARD_REG_SIZE
)
1500 return gen_rtx_REG (mode
, HARD_X_REGNUM
);
1502 if (GET_MODE_SIZE (mode
) > HARD_REG_SIZE
)
1506 return gen_rtx_REG (mode
, HARD_D_REGNUM
);
1511 /* If defined, a C expression which determines whether, and in which direction,
1512 to pad out an argument with extra space. The value should be of type
1513 `enum direction': either `upward' to pad above the argument,
1514 `downward' to pad below, or `none' to inhibit padding.
1516 Structures are stored left shifted in their argument slot. */
1518 m68hc11_function_arg_padding (enum machine_mode mode
, const_tree type
)
1520 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
1523 /* Fall back to the default. */
1524 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
1528 /* Function prologue and epilogue. */
1530 /* Emit a move after the reload pass has completed. This is used to
1531 emit the prologue and epilogue. */
1533 emit_move_after_reload (rtx to
, rtx from
, rtx scratch
)
1537 if (TARGET_M6812
|| H_REG_P (to
) || H_REG_P (from
))
1539 insn
= emit_move_insn (to
, from
);
1543 emit_move_insn (scratch
, from
);
1544 insn
= emit_move_insn (to
, scratch
);
1547 /* Put a REG_INC note to tell the flow analysis that the instruction
1549 if (IS_STACK_PUSH (to
))
1550 add_reg_note (insn
, REG_INC
, XEXP (XEXP (to
, 0), 0));
1551 else if (IS_STACK_POP (from
))
1552 add_reg_note (insn
, REG_INC
, XEXP (XEXP (from
, 0), 0));
1554 /* For 68HC11, put a REG_INC note on `sts _.frame' to prevent the cse-reg
1555 to think that sp == _.frame and later replace a x = sp with x = _.frame.
1556 The problem is that we are lying to gcc and use `txs' for x = sp
1557 (which is not really true because txs is really x = sp + 1). */
1558 else if (TARGET_M6811
&& SP_REG_P (from
))
1559 add_reg_note (insn
, REG_INC
, from
);
1563 m68hc11_total_frame_size (void)
1568 size
= get_frame_size ();
1569 if (current_function_interrupt
)
1571 size
+= 3 * HARD_REG_SIZE
;
1573 if (frame_pointer_needed
)
1574 size
+= HARD_REG_SIZE
;
1576 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1577 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1578 size
+= HARD_REG_SIZE
;
1584 m68hc11_output_function_epilogue (FILE *out ATTRIBUTE_UNUSED
,
1585 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1587 /* We catch the function epilogue generation to have a chance
1588 to clear the z_replacement_completed flag. */
1589 z_replacement_completed
= 0;
1593 expand_prologue (void)
1600 gcc_assert (reload_completed
== 1);
1602 size
= get_frame_size ();
1606 /* Generate specific prologue for interrupt handlers. */
1607 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1608 current_function_interrupt
= lookup_attribute ("interrupt",
1609 func_attr
) != NULL_TREE
;
1610 current_function_trap
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1611 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1612 current_function_far
= 1;
1613 else if (lookup_attribute ("near", func_attr
) != NULL_TREE
)
1614 current_function_far
= 0;
1616 current_function_far
= (TARGET_LONG_CALLS
!= 0
1617 && !current_function_interrupt
1618 && !current_function_trap
);
1620 /* Get the scratch register to build the frame and push registers.
1621 If the first argument is a 32-bit quantity, the D+X registers
1622 are used. Use Y to compute the frame. Otherwise, X is cheaper.
1623 For 68HC12, this scratch register is not used. */
1624 if (crtl
->args
.info
.nregs
== 2)
1629 /* Save current stack frame. */
1630 if (frame_pointer_needed
)
1631 emit_move_after_reload (stack_push_word
, hard_frame_pointer_rtx
, scratch
);
1633 /* For an interrupt handler, we must preserve _.tmp, _.z and _.xy.
1634 Other soft registers in page0 need not to be saved because they
1635 will be restored by C functions. For a trap handler, we don't
1636 need to preserve these registers because this is a synchronous call. */
1637 if (current_function_interrupt
)
1639 emit_move_after_reload (stack_push_word
, m68hc11_soft_tmp_reg
, scratch
);
1640 emit_move_after_reload (stack_push_word
,
1641 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
), scratch
);
1642 emit_move_after_reload (stack_push_word
,
1643 gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1647 /* Allocate local variables. */
1648 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1650 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1651 stack_pointer_rtx
, GEN_INT (-size
)));
1653 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1657 insn
= gen_rtx_PARALLEL
1660 gen_rtx_SET (VOIDmode
,
1662 gen_rtx_PLUS (HImode
,
1665 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1672 /* Allocate by pushing scratch values. */
1673 for (i
= 2; i
<= size
; i
+= 2)
1674 emit_move_after_reload (stack_push_word
, ix_reg
, 0);
1677 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1678 stack_pointer_rtx
, constm1_rtx
));
1681 /* Create the frame pointer. */
1682 if (frame_pointer_needed
)
1683 emit_move_after_reload (hard_frame_pointer_rtx
,
1684 stack_pointer_rtx
, scratch
);
1686 /* Push any 2 byte pseudo hard registers that we need to save. */
1687 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1689 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1691 emit_move_after_reload (stack_push_word
,
1692 gen_rtx_REG (HImode
, regno
), scratch
);
1698 expand_epilogue (void)
1705 gcc_assert (reload_completed
== 1);
1707 size
= get_frame_size ();
1709 /* If we are returning a value in two registers, we have to preserve the
1710 X register and use the Y register to restore the stack and the saved
1711 registers. Otherwise, use X because it's faster (and smaller). */
1712 if (crtl
->return_rtx
== 0)
1714 else if (GET_CODE (crtl
->return_rtx
) == MEM
)
1715 return_size
= HARD_REG_SIZE
;
1717 return_size
= GET_MODE_SIZE (GET_MODE (crtl
->return_rtx
));
1719 if (return_size
> HARD_REG_SIZE
&& return_size
<= 2 * HARD_REG_SIZE
)
1724 /* Pop any 2 byte pseudo hard registers that we saved. */
1725 for (regno
= SOFT_REG_LAST
; regno
>= SOFT_REG_FIRST
; regno
--)
1727 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1729 emit_move_after_reload (gen_rtx_REG (HImode
, regno
),
1730 stack_pop_word
, scratch
);
1734 /* de-allocate auto variables */
1735 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1737 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1738 stack_pointer_rtx
, GEN_INT (size
)));
1740 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1744 insn
= gen_rtx_PARALLEL
1747 gen_rtx_SET (VOIDmode
,
1749 gen_rtx_PLUS (HImode
,
1752 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1759 for (i
= 2; i
<= size
; i
+= 2)
1760 emit_move_after_reload (scratch
, stack_pop_word
, scratch
);
1762 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1763 stack_pointer_rtx
, const1_rtx
));
1766 /* For an interrupt handler, restore ZTMP, ZREG and XYREG. */
1767 if (current_function_interrupt
)
1769 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1770 stack_pop_word
, scratch
);
1771 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
1772 stack_pop_word
, scratch
);
1773 emit_move_after_reload (m68hc11_soft_tmp_reg
, stack_pop_word
, scratch
);
1776 /* Restore previous frame pointer. */
1777 if (frame_pointer_needed
)
1778 emit_move_after_reload (hard_frame_pointer_rtx
, stack_pop_word
, scratch
);
1780 /* If the trap handler returns some value, copy the value
1781 in D, X onto the stack so that the rti will pop the return value
1783 else if (current_function_trap
&& return_size
!= 0)
1785 rtx addr_reg
= stack_pointer_rtx
;
1789 emit_move_after_reload (scratch
, stack_pointer_rtx
, 0);
1792 emit_move_after_reload (gen_rtx_MEM (HImode
,
1793 gen_rtx_PLUS (HImode
, addr_reg
,
1794 const1_rtx
)), d_reg
, 0);
1795 if (return_size
> HARD_REG_SIZE
)
1796 emit_move_after_reload (gen_rtx_MEM (HImode
,
1797 gen_rtx_PLUS (HImode
, addr_reg
,
1798 GEN_INT (3))), ix_reg
, 0);
1801 emit_jump_insn (gen_return ());
1805 /* Low and High part extraction for 68HC11. These routines are
1806 similar to gen_lowpart and gen_highpart but they have been
1807 fixed to work for constants and 68HC11 specific registers. */
1810 m68hc11_gen_lowpart (enum machine_mode mode
, rtx x
)
1812 /* We assume that the low part of an auto-inc mode is the same with
1813 the mode changed and that the caller split the larger mode in the
1815 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1817 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1820 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1821 floating-point constant. A CONST_DOUBLE is used whenever the
1822 constant requires more than one word in order to be adequately
1824 if (GET_CODE (x
) == CONST_DOUBLE
)
1828 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1832 if (GET_MODE (x
) == SFmode
)
1834 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1835 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[0]);
1841 split_double (x
, &first
, &second
);
1845 return GEN_INT (l
[0]);
1847 return gen_int_mode (l
[0], HImode
);
1851 l
[0] = CONST_DOUBLE_LOW (x
);
1856 return GEN_INT (l
[0]);
1858 gcc_assert (GET_MODE (x
) == SFmode
);
1859 return gen_int_mode (l
[0], HImode
);
1865 if (mode
== QImode
&& D_REG_P (x
))
1866 return gen_rtx_REG (mode
, HARD_B_REGNUM
);
1868 /* gen_lowpart crashes when it is called with a SUBREG. */
1869 if (GET_CODE (x
) == SUBREG
&& SUBREG_BYTE (x
) != 0)
1874 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 4);
1876 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 2);
1881 x
= gen_lowpart (mode
, x
);
1883 /* Return a different rtx to avoid to share it in several insns
1884 (when used by a split pattern). Sharing addresses within
1885 a MEM breaks the Z register replacement (and reloading). */
1886 if (GET_CODE (x
) == MEM
)
1892 m68hc11_gen_highpart (enum machine_mode mode
, rtx x
)
1894 /* We assume that the high part of an auto-inc mode is the same with
1895 the mode changed and that the caller split the larger mode in the
1897 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1899 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1902 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1903 floating-point constant. A CONST_DOUBLE is used whenever the
1904 constant requires more than one word in order to be adequately
1906 if (GET_CODE (x
) == CONST_DOUBLE
)
1910 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1914 if (GET_MODE (x
) == SFmode
)
1916 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1917 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[1]);
1923 split_double (x
, &first
, &second
);
1927 return GEN_INT (l
[1]);
1929 return gen_int_mode ((l
[1] >> 16), HImode
);
1933 l
[1] = CONST_DOUBLE_HIGH (x
);
1939 return GEN_INT (l
[1]);
1941 gcc_assert (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
);
1942 return gen_int_mode ((l
[0] >> 16), HImode
);
1947 if (GET_CODE (x
) == CONST_INT
)
1949 HOST_WIDE_INT val
= INTVAL (x
);
1953 return gen_int_mode (val
>> 8, QImode
);
1955 else if (mode
== HImode
)
1957 return gen_int_mode (val
>> 16, HImode
);
1959 else if (mode
== SImode
)
1961 return gen_int_mode (val
>> 32, SImode
);
1964 if (mode
== QImode
&& D_REG_P (x
))
1965 return gen_rtx_REG (mode
, HARD_A_REGNUM
);
1967 /* There is no way in GCC to represent the upper part of a word register.
1968 To obtain the 8-bit upper part of a soft register, we change the
1969 reg into a mem rtx. This is possible because they are physically
1970 located in memory. There is no offset because we are big-endian. */
1971 if (mode
== QImode
&& S_REG_P (x
))
1975 /* Avoid the '*' for direct addressing mode when this
1976 addressing mode is disabled. */
1977 pos
= TARGET_NO_DIRECT_MODE
? 1 : 0;
1978 return gen_rtx_MEM (QImode
,
1979 gen_rtx_SYMBOL_REF (Pmode
,
1980 ®_names
[REGNO (x
)][pos
]));
1983 /* gen_highpart crashes when it is called with a SUBREG. */
1984 switch (GET_CODE (x
))
1987 return gen_rtx_SUBREG (mode
, XEXP (x
, 0), XINT (x
, 1));
1989 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1990 return gen_rtx_REG (mode
, REGNO (x
));
1992 return gen_rtx_SUBREG (mode
, x
, 0);
1994 x
= change_address (x
, mode
, 0);
1996 /* Return a different rtx to avoid to share it in several insns
1997 (when used by a split pattern). Sharing addresses within
1998 a MEM breaks the Z register replacement (and reloading). */
1999 if (GET_CODE (x
) == MEM
)
2009 /* Obscure register manipulation. */
2011 /* Finds backward in the instructions to see if register 'reg' is
2012 dead. This is used when generating code to see if we can use 'reg'
2013 as a scratch register. This allows us to choose a better generation
2014 of code when we know that some register dies or can be clobbered. */
2017 dead_register_here (rtx x
, rtx reg
)
2023 x_reg
= gen_rtx_REG (SImode
, HARD_X_REGNUM
);
2027 for (p
= PREV_INSN (x
); p
&& GET_CODE (p
) != CODE_LABEL
; p
= PREV_INSN (p
))
2034 if (GET_CODE (body
) == CALL_INSN
)
2036 if (GET_CODE (body
) == JUMP_INSN
)
2039 if (GET_CODE (body
) == SET
)
2041 rtx dst
= XEXP (body
, 0);
2043 if (GET_CODE (dst
) == REG
&& REGNO (dst
) == REGNO (reg
))
2045 if (x_reg
&& rtx_equal_p (dst
, x_reg
))
2048 if (find_regno_note (p
, REG_DEAD
, REGNO (reg
)))
2051 else if (reg_mentioned_p (reg
, p
)
2052 || (x_reg
&& reg_mentioned_p (x_reg
, p
)))
2056 /* Scan forward to see if the register is set in some insns and never
2058 for (p
= x
/*NEXT_INSN (x) */ ; p
; p
= NEXT_INSN (p
))
2062 if (GET_CODE (p
) == CODE_LABEL
2063 || GET_CODE (p
) == JUMP_INSN
2064 || GET_CODE (p
) == CALL_INSN
|| GET_CODE (p
) == BARRIER
)
2067 if (GET_CODE (p
) != INSN
)
2071 if (GET_CODE (body
) == SET
)
2073 rtx src
= XEXP (body
, 1);
2074 rtx dst
= XEXP (body
, 0);
2076 if (GET_CODE (dst
) == REG
2077 && REGNO (dst
) == REGNO (reg
) && !reg_mentioned_p (reg
, src
))
2081 /* Register is used (may be in source or in dest). */
2082 if (reg_mentioned_p (reg
, p
)
2083 || (x_reg
!= 0 && GET_MODE (p
) == SImode
2084 && reg_mentioned_p (x_reg
, p
)))
2087 return p
== 0 ? 1 : 0;
2091 /* Code generation operations called from machine description file. */
2093 /* Print the name of register 'regno' in the assembly file. */
2095 asm_print_register (FILE *file
, int regno
)
2097 const char *name
= reg_names
[regno
];
2099 if (TARGET_NO_DIRECT_MODE
&& name
[0] == '*')
2102 fprintf (file
, "%s", name
);
2105 /* A C compound statement to output to stdio stream STREAM the
2106 assembler syntax for an instruction operand X. X is an RTL
2109 CODE is a value that can be used to specify one of several ways
2110 of printing the operand. It is used when identical operands
2111 must be printed differently depending on the context. CODE
2112 comes from the `%' specification that was used to request
2113 printing of the operand. If the specification was just `%DIGIT'
2114 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2115 is the ASCII code for LTR.
2117 If X is a register, this macro should print the register's name.
2118 The names can be found in an array `reg_names' whose type is
2119 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2121 When the machine description has a specification `%PUNCT' (a `%'
2122 followed by a punctuation character), this macro is called with
2123 a null pointer for X and the punctuation character for CODE.
2125 The M68HC11 specific codes are:
2127 'b' for the low part of the operand.
2128 'h' for the high part of the operand
2129 The 'b' or 'h' modifiers have no effect if the operand has
2130 the QImode and is not a S_REG_P (soft register). If the
2131 operand is a hard register, these two modifiers have no effect.
2132 't' generate the temporary scratch register. The operand is
2134 'T' generate the low-part temporary scratch register. The operand is
2138 m68hc11_print_operand (FILE *file
, rtx op
, int letter
)
2142 asm_print_register (file
, SOFT_TMP_REGNUM
);
2145 else if (letter
== 'T')
2147 asm_print_register (file
, SOFT_TMP_REGNUM
);
2148 fprintf (file
, "+1");
2151 else if (letter
== '#')
2153 asm_fprintf (file
, "%I");
2156 if (GET_CODE (op
) == REG
)
2158 if (letter
== 'b' && S_REG_P (op
))
2160 asm_print_register (file
, REGNO (op
));
2161 fprintf (file
, "+1");
2163 else if (letter
== 'b' && D_REG_P (op
))
2165 asm_print_register (file
, HARD_B_REGNUM
);
2169 asm_print_register (file
, REGNO (op
));
2174 if (GET_CODE (op
) == SYMBOL_REF
&& (letter
== 'b' || letter
== 'h'))
2177 asm_fprintf (file
, "%I%%lo(");
2179 asm_fprintf (file
, "%I%%hi(");
2181 output_addr_const (file
, op
);
2182 fprintf (file
, ")");
2186 /* Get the low or high part of the operand when 'b' or 'h' modifiers
2187 are specified. If we already have a QImode, there is nothing to do. */
2188 if (GET_MODE (op
) == HImode
|| GET_MODE (op
) == VOIDmode
)
2192 op
= m68hc11_gen_lowpart (QImode
, op
);
2194 else if (letter
== 'h')
2196 op
= m68hc11_gen_highpart (QImode
, op
);
2200 if (GET_CODE (op
) == MEM
)
2202 rtx base
= XEXP (op
, 0);
2203 switch (GET_CODE (base
))
2206 gcc_assert (TARGET_M6812
);
2207 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (op
)));
2208 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2212 gcc_assert (TARGET_M6812
);
2213 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2214 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2215 fprintf (file
, "-");
2219 gcc_assert (TARGET_M6812
);
2220 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2221 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2222 fprintf (file
, "+");
2226 gcc_assert (TARGET_M6812
);
2227 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (op
)));
2228 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2232 gcc_assert (TARGET_M6812
);
2233 fprintf (file
, "[");
2234 print_operand_address (file
, XEXP (base
, 0));
2235 fprintf (file
, "]");
2239 if (m68hc11_page0_symbol_p (base
))
2240 fprintf (file
, "*");
2242 output_address (base
);
2246 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2251 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2252 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2253 asm_fprintf (file
, "%I0x%lx", l
);
2255 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2259 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (op
),
2260 sizeof (dstr
), 0, 1);
2261 asm_fprintf (file
, "%I0r%s", dstr
);
2265 int need_parenthesize
= 0;
2268 asm_fprintf (file
, "%I");
2270 need_parenthesize
= must_parenthesize (op
);
2272 if (need_parenthesize
)
2273 fprintf (file
, "(");
2275 output_addr_const (file
, op
);
2276 if (need_parenthesize
)
2277 fprintf (file
, ")");
2281 /* Returns true if the operand 'op' must be printed with parenthesis
2282 around it. This must be done only if there is a symbol whose name
2283 is a processor register. */
2285 must_parenthesize (rtx op
)
2289 switch (GET_CODE (op
))
2292 name
= XSTR (op
, 0);
2293 /* Avoid a conflict between symbol name and a possible
2295 return (strcasecmp (name
, "a") == 0
2296 || strcasecmp (name
, "b") == 0
2297 || strcasecmp (name
, "d") == 0
2298 || strcasecmp (name
, "x") == 0
2299 || strcasecmp (name
, "y") == 0
2300 || strcasecmp (name
, "ix") == 0
2301 || strcasecmp (name
, "iy") == 0
2302 || strcasecmp (name
, "pc") == 0
2303 || strcasecmp (name
, "sp") == 0
2304 || strcasecmp (name
, "ccr") == 0) ? 1 : 0;
2308 return must_parenthesize (XEXP (op
, 0))
2309 || must_parenthesize (XEXP (op
, 1));
2315 return must_parenthesize (XEXP (op
, 0));
2326 /* A C compound statement to output to stdio stream STREAM the
2327 assembler syntax for an instruction operand that is a memory
2328 reference whose address is ADDR. ADDR is an RTL expression. */
2331 m68hc11_print_operand_address (FILE *file
, rtx addr
)
2335 int need_parenthesis
= 0;
2337 switch (GET_CODE (addr
))
2340 gcc_assert (REG_P (addr
) && REG_OK_FOR_BASE_STRICT_P (addr
));
2342 fprintf (file
, "0,");
2343 asm_print_register (file
, REGNO (addr
));
2347 base
= XEXP (addr
, 0);
2348 switch (GET_CODE (base
))
2351 gcc_assert (TARGET_M6812
);
2352 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (addr
)));
2353 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2357 gcc_assert (TARGET_M6812
);
2358 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2359 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2360 fprintf (file
, "-");
2364 gcc_assert (TARGET_M6812
);
2365 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2366 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2367 fprintf (file
, "+");
2371 gcc_assert (TARGET_M6812
);
2372 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (addr
)));
2373 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2377 need_parenthesis
= must_parenthesize (base
);
2378 if (need_parenthesis
)
2379 fprintf (file
, "(");
2381 output_addr_const (file
, base
);
2382 if (need_parenthesis
)
2383 fprintf (file
, ")");
2389 base
= XEXP (addr
, 0);
2390 offset
= XEXP (addr
, 1);
2391 if (!G_REG_P (base
) && G_REG_P (offset
))
2393 base
= XEXP (addr
, 1);
2394 offset
= XEXP (addr
, 0);
2396 if (CONSTANT_ADDRESS_P (base
))
2398 need_parenthesis
= must_parenthesize (addr
);
2400 gcc_assert (CONSTANT_ADDRESS_P (offset
));
2401 if (need_parenthesis
)
2402 fprintf (file
, "(");
2404 output_addr_const (file
, base
);
2405 fprintf (file
, "+");
2406 output_addr_const (file
, offset
);
2407 if (need_parenthesis
)
2408 fprintf (file
, ")");
2412 gcc_assert (REG_P (base
) && REG_OK_FOR_BASE_STRICT_P (base
));
2415 gcc_assert (TARGET_M6812
);
2416 asm_print_register (file
, REGNO (offset
));
2417 fprintf (file
, ",");
2418 asm_print_register (file
, REGNO (base
));
2422 need_parenthesis
= must_parenthesize (offset
);
2423 if (need_parenthesis
)
2424 fprintf (file
, "(");
2426 output_addr_const (file
, offset
);
2427 if (need_parenthesis
)
2428 fprintf (file
, ")");
2429 fprintf (file
, ",");
2430 asm_print_register (file
, REGNO (base
));
2436 if (GET_CODE (addr
) == CONST_INT
2437 && INTVAL (addr
) < 0x8000 && INTVAL (addr
) >= -0x8000)
2439 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2443 need_parenthesis
= must_parenthesize (addr
);
2444 if (need_parenthesis
)
2445 fprintf (file
, "(");
2447 output_addr_const (file
, addr
);
2448 if (need_parenthesis
)
2449 fprintf (file
, ")");
2456 /* Splitting of some instructions. */
2459 m68hc11_expand_compare (enum rtx_code code
, rtx op0
, rtx op1
)
2463 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_FLOAT
);
2464 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
,
2465 gen_rtx_COMPARE (VOIDmode
, op0
, op1
)));
2466 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
2472 m68hc11_expand_compare_and_branch (enum rtx_code code
, rtx op0
, rtx op1
,
2477 switch (GET_MODE (op0
))
2481 tmp
= m68hc11_expand_compare (code
, op0
, op1
);
2482 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2483 gen_rtx_LABEL_REF (VOIDmode
, label
),
2485 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
2489 /* SCz: from i386.c */
2492 /* Don't expand the comparison early, so that we get better code
2493 when jump or whoever decides to reverse the comparison. */
2498 code
= m68hc11_prepare_fp_compare_args (code
, &m68hc11_compare_op0
,
2499 &m68hc11_compare_op1
);
2501 tmp
= gen_rtx_fmt_ee (code
, m68hc11_fp_compare_mode (code
),
2502 m68hc11_compare_op0
, m68hc11_compare_op1
);
2503 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2504 gen_rtx_LABEL_REF (VOIDmode
, label
),
2506 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
2508 use_fcomi
= ix86_use_fcomi_compare (code
);
2509 vec
= rtvec_alloc (3 + !use_fcomi
);
2510 RTVEC_ELT (vec
, 0) = tmp
;
2512 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
2514 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
2517 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
2519 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
2525 /* Expand SImode branch into multiple compare+branch. */
2527 rtx lo
[2], hi
[2], label2
;
2528 enum rtx_code code1
, code2
, code3
;
2530 if (CONSTANT_P (op0
) && !CONSTANT_P (op1
))
2535 code
= swap_condition (code
);
2537 lo
[0] = m68hc11_gen_lowpart (HImode
, op0
);
2538 lo
[1] = m68hc11_gen_lowpart (HImode
, op1
);
2539 hi
[0] = m68hc11_gen_highpart (HImode
, op0
);
2540 hi
[1] = m68hc11_gen_highpart (HImode
, op1
);
2542 /* Otherwise, if we are doing less-than, op1 is a constant and the
2543 low word is zero, then we can just examine the high word. */
2545 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
2546 && (code
== LT
|| code
== LTU
))
2548 return m68hc11_expand_compare_and_branch (code
, hi
[0], hi
[1],
2552 /* Otherwise, we need two or three jumps. */
2554 label2
= gen_label_rtx ();
2557 code2
= swap_condition (code
);
2558 code3
= unsigned_condition (code
);
2599 * if (hi(a) < hi(b)) goto true;
2600 * if (hi(a) > hi(b)) goto false;
2601 * if (lo(a) < lo(b)) goto true;
2604 if (code1
!= UNKNOWN
)
2605 m68hc11_expand_compare_and_branch (code1
, hi
[0], hi
[1], label
);
2606 if (code2
!= UNKNOWN
)
2607 m68hc11_expand_compare_and_branch (code2
, hi
[0], hi
[1], label2
);
2609 m68hc11_expand_compare_and_branch (code3
, lo
[0], lo
[1], label
);
2611 if (code2
!= UNKNOWN
)
2612 emit_label (label2
);
2622 /* Return the increment/decrement mode of a MEM if it is such.
2623 Return CONST if it is anything else. */
2625 autoinc_mode (rtx x
)
2627 if (GET_CODE (x
) != MEM
)
2631 if (GET_CODE (x
) == PRE_INC
2632 || GET_CODE (x
) == PRE_DEC
2633 || GET_CODE (x
) == POST_INC
2634 || GET_CODE (x
) == POST_DEC
)
2635 return GET_CODE (x
);
2641 m68hc11_make_autoinc_notes (rtx
*x
, void *data
)
2645 switch (GET_CODE (*x
))
2652 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_INC
, XEXP (*x
, 0),
2661 /* Split a DI, SI or HI move into several smaller move operations.
2662 The scratch register 'scratch' is used as a temporary to load
2663 store intermediate values. It must be a hard register. */
2665 m68hc11_split_move (rtx to
, rtx from
, rtx scratch
)
2667 rtx low_to
, low_from
;
2668 rtx high_to
, high_from
;
2670 enum machine_mode mode
;
2672 int autoinc_from
= autoinc_mode (from
);
2673 int autoinc_to
= autoinc_mode (to
);
2675 mode
= GET_MODE (to
);
2677 /* If the TO and FROM contain autoinc modes that are not compatible
2678 together (one pop and the other a push), we must change one to
2679 an offsetable operand and generate an appropriate add at the end. */
2680 if (TARGET_M6812
&& GET_MODE_SIZE (mode
) > 2)
2685 /* The source uses an autoinc mode which is not compatible with
2686 a split (this would result in a word swap). */
2687 if (autoinc_from
== PRE_INC
|| autoinc_from
== POST_DEC
)
2689 code
= GET_CODE (XEXP (from
, 0));
2690 reg
= XEXP (XEXP (from
, 0), 0);
2691 offset
= GET_MODE_SIZE (GET_MODE (from
));
2692 if (code
== POST_DEC
)
2695 if (code
== PRE_INC
)
2696 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2698 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2699 if (code
== POST_DEC
)
2700 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2704 /* Likewise for destination. */
2705 if (autoinc_to
== PRE_INC
|| autoinc_to
== POST_DEC
)
2707 code
= GET_CODE (XEXP (to
, 0));
2708 reg
= XEXP (XEXP (to
, 0), 0);
2709 offset
= GET_MODE_SIZE (GET_MODE (to
));
2710 if (code
== POST_DEC
)
2713 if (code
== PRE_INC
)
2714 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2716 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2717 if (code
== POST_DEC
)
2718 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2722 /* The source and destination auto increment modes must be compatible
2723 with each other: same direction. */
2724 if ((autoinc_to
!= autoinc_from
2725 && autoinc_to
!= CONST
&& autoinc_from
!= CONST
)
2726 /* The destination address register must not be used within
2727 the source operand because the source address would change
2728 while doing the copy. */
2729 || (autoinc_to
!= CONST
2730 && reg_mentioned_p (XEXP (XEXP (to
, 0), 0), from
)
2731 && !IS_STACK_PUSH (to
)))
2733 /* Must change the destination. */
2734 code
= GET_CODE (XEXP (to
, 0));
2735 reg
= XEXP (XEXP (to
, 0), 0);
2736 offset
= GET_MODE_SIZE (GET_MODE (to
));
2737 if (code
== PRE_DEC
|| code
== POST_DEC
)
2740 if (code
== PRE_DEC
|| code
== PRE_INC
)
2741 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2742 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2743 if (code
== POST_DEC
|| code
== POST_INC
)
2744 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2749 /* Likewise, the source address register must not be used within
2750 the destination operand. */
2751 if (autoinc_from
!= CONST
2752 && reg_mentioned_p (XEXP (XEXP (from
, 0), 0), to
)
2753 && !IS_STACK_PUSH (to
))
2755 /* Must change the source. */
2756 code
= GET_CODE (XEXP (from
, 0));
2757 reg
= XEXP (XEXP (from
, 0), 0);
2758 offset
= GET_MODE_SIZE (GET_MODE (from
));
2759 if (code
== PRE_DEC
|| code
== POST_DEC
)
2762 if (code
== PRE_DEC
|| code
== PRE_INC
)
2763 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2764 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2765 if (code
== POST_DEC
|| code
== POST_INC
)
2766 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2772 if (GET_MODE_SIZE (mode
) == 8)
2774 else if (GET_MODE_SIZE (mode
) == 4)
2780 && IS_STACK_PUSH (to
)
2781 && reg_mentioned_p (gen_rtx_REG (HImode
, HARD_SP_REGNUM
), from
))
2787 else if (mode
== HImode
)
2795 low_to
= m68hc11_gen_lowpart (mode
, to
);
2796 high_to
= m68hc11_gen_highpart (mode
, to
);
2798 low_from
= m68hc11_gen_lowpart (mode
, from
);
2799 high_from
= m68hc11_gen_highpart (mode
, from
);
2803 high_from
= adjust_address (high_from
, mode
, offset
);
2804 low_from
= high_from
;
2807 /* When copying with a POST_INC mode, we must copy the
2808 high part and then the low part to guarantee a correct
2811 && GET_MODE_SIZE (mode
) >= 2
2812 && autoinc_from
!= autoinc_to
2813 && (autoinc_from
== POST_INC
|| autoinc_to
== POST_INC
))
2822 low_from
= high_from
;
2827 m68hc11_split_move (low_to
, low_from
, scratch
);
2828 m68hc11_split_move (high_to
, high_from
, scratch
);
2830 else if (H_REG_P (to
) || H_REG_P (from
)
2831 || (low_from
== const0_rtx
2832 && high_from
== const0_rtx
2833 && ! push_operand (to
, GET_MODE (to
))
2834 && ! H_REG_P (scratch
))
2836 && (!m68hc11_register_indirect_p (from
, GET_MODE (from
))
2837 || m68hc11_small_indexed_indirect_p (from
,
2839 && (!m68hc11_register_indirect_p (to
, GET_MODE (to
))
2840 || m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
)))))
2842 insn
= emit_move_insn (low_to
, low_from
);
2843 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2845 insn
= emit_move_insn (high_to
, high_from
);
2846 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2850 insn
= emit_move_insn (scratch
, low_from
);
2851 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2852 insn
= emit_move_insn (low_to
, scratch
);
2853 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2855 insn
= emit_move_insn (scratch
, high_from
);
2856 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2857 insn
= emit_move_insn (high_to
, scratch
);
2858 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2863 simplify_logical (enum machine_mode mode
, int code
, rtx operand
, rtx
*result
)
2869 if (GET_CODE (operand
) != CONST_INT
)
2877 val
= INTVAL (operand
);
2881 if ((val
& mask
) == 0)
2883 if ((val
& mask
) == mask
)
2884 *result
= constm1_rtx
;
2888 if ((val
& mask
) == 0)
2889 *result
= const0_rtx
;
2890 if ((val
& mask
) == mask
)
2895 if ((val
& mask
) == 0)
2903 m68hc11_emit_logical (enum machine_mode mode
, enum rtx_code code
, rtx
*operands
)
2908 need_copy
= (rtx_equal_p (operands
[0], operands
[1])
2909 || rtx_equal_p (operands
[0], operands
[2])) ? 0 : 1;
2911 operands
[1] = simplify_logical (mode
, code
, operands
[1], &result
);
2912 operands
[2] = simplify_logical (mode
, code
, operands
[2], &result
);
2914 if (result
&& GET_CODE (result
) == CONST_INT
)
2916 if (!H_REG_P (operands
[0]) && operands
[3]
2917 && (INTVAL (result
) != 0 || IS_STACK_PUSH (operands
[0])))
2919 emit_move_insn (operands
[3], result
);
2920 emit_move_insn (operands
[0], operands
[3]);
2924 emit_move_insn (operands
[0], result
);
2927 else if (operands
[1] != 0 && operands
[2] != 0)
2931 if (!H_REG_P (operands
[0]) && operands
[3])
2933 emit_move_insn (operands
[3], operands
[1]);
2934 emit_insn (gen_rtx_SET (mode
,
2936 gen_rtx_fmt_ee (code
, mode
,
2937 operands
[3], operands
[2])));
2938 insn
= emit_move_insn (operands
[0], operands
[3]);
2942 insn
= emit_insn (gen_rtx_SET (mode
,
2944 gen_rtx_fmt_ee (code
, mode
,
2950 /* The logical operation is similar to a copy. */
2955 if (GET_CODE (operands
[1]) == CONST_INT
)
2960 if (!H_REG_P (operands
[0]) && !H_REG_P (src
))
2962 emit_move_insn (operands
[3], src
);
2963 emit_move_insn (operands
[0], operands
[3]);
2967 emit_move_insn (operands
[0], src
);
2973 m68hc11_split_logical (enum machine_mode mode
, enum rtx_code code
,
2979 low
[0] = m68hc11_gen_lowpart (mode
, operands
[0]);
2980 low
[1] = m68hc11_gen_lowpart (mode
, operands
[1]);
2981 low
[2] = m68hc11_gen_lowpart (mode
, operands
[2]);
2983 high
[0] = m68hc11_gen_highpart (mode
, operands
[0]);
2984 high
[1] = m68hc11_gen_highpart (mode
, operands
[1]);
2985 high
[2] = m68hc11_gen_highpart (mode
, operands
[2]);
2987 low
[3] = operands
[3];
2988 high
[3] = operands
[3];
2991 m68hc11_split_logical (HImode
, code
, low
);
2992 m68hc11_split_logical (HImode
, code
, high
);
2996 m68hc11_emit_logical (mode
, code
, low
);
2997 m68hc11_emit_logical (mode
, code
, high
);
3001 /* Code generation. */
3004 m68hc11_output_swap (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
3006 /* We have to be careful with the cc_status. An address register swap
3007 is generated for some comparison. The comparison is made with D
3008 but the branch really uses the address register. See the split
3009 pattern for compare. The xgdx/xgdy preserve the flags but after
3010 the exchange, the flags will reflect to the value of X and not D.
3011 Tell this by setting the cc_status according to the cc_prev_status. */
3012 if (X_REG_P (operands
[1]) || X_REG_P (operands
[0]))
3014 if (cc_prev_status
.value1
!= 0
3015 && (D_REG_P (cc_prev_status
.value1
)
3016 || X_REG_P (cc_prev_status
.value1
)))
3018 cc_status
= cc_prev_status
;
3019 if (D_REG_P (cc_status
.value1
))
3020 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3023 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3029 output_asm_insn ("xgdx", operands
);
3033 if (cc_prev_status
.value1
!= 0
3034 && (D_REG_P (cc_prev_status
.value1
)
3035 || Y_REG_P (cc_prev_status
.value1
)))
3037 cc_status
= cc_prev_status
;
3038 if (D_REG_P (cc_status
.value1
))
3039 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3042 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3048 output_asm_insn ("xgdy", operands
);
3052 /* Returns 1 if the next insn after 'insn' is a test of the register 'reg'.
3053 This is used to decide whether a move that set flags should be used
3056 next_insn_test_reg (rtx insn
, rtx reg
)
3060 insn
= next_nonnote_insn (insn
);
3061 if (GET_CODE (insn
) != INSN
)
3064 body
= PATTERN (insn
);
3065 if (sets_cc0_p (body
) != 1)
3068 if (rtx_equal_p (XEXP (body
, 1), reg
) == 0)
3074 /* Generate the code to move a 16-bit operand into another one. */
3077 m68hc11_gen_movhi (rtx insn
, rtx
*operands
)
3081 /* Move a register or memory to the same location.
3082 This is possible because such insn can appear
3083 in a non-optimizing mode. */
3084 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3086 cc_status
= cc_prev_status
;
3092 rtx from
= operands
[1];
3093 rtx to
= operands
[0];
3095 if (IS_STACK_PUSH (to
) && H_REG_P (from
))
3097 cc_status
= cc_prev_status
;
3098 switch (REGNO (from
))
3103 output_asm_insn ("psh%1", operands
);
3105 case HARD_SP_REGNUM
:
3106 output_asm_insn ("sts\t2,-sp", operands
);
3113 if (IS_STACK_POP (from
) && H_REG_P (to
))
3115 cc_status
= cc_prev_status
;
3121 output_asm_insn ("pul%0", operands
);
3128 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3130 m68hc11_notice_keep_cc (operands
[0]);
3131 output_asm_insn ("tfr\t%1,%0", operands
);
3133 else if (H_REG_P (operands
[0]))
3135 if (SP_REG_P (operands
[0]))
3136 output_asm_insn ("lds\t%1", operands
);
3138 output_asm_insn ("ld%0\t%1", operands
);
3140 else if (H_REG_P (operands
[1]))
3142 if (SP_REG_P (operands
[1]))
3143 output_asm_insn ("sts\t%0", operands
);
3145 output_asm_insn ("st%1\t%0", operands
);
3148 /* The 68hc12 does not support (MEM:HI (MEM:HI)) with the movw
3149 instruction. We have to use a scratch register as temporary location.
3150 Trying to use a specific pattern or constrain failed. */
3151 else if (GET_CODE (to
) == MEM
&& GET_CODE (XEXP (to
, 0)) == MEM
)
3158 if (dead_register_here (insn
, d_reg
))
3160 else if (dead_register_here (insn
, ix_reg
))
3162 else if (dead_register_here (insn
, iy_reg
))
3168 output_asm_insn ("psh%3", ops
);
3173 output_asm_insn ("ld%1\t%2", ops
);
3174 output_asm_insn ("st%1\t%0", ops
);
3176 output_asm_insn ("pul%3", ops
);
3179 /* Use movw for non-null constants or when we are clearing
3180 a volatile memory reference. However, this is possible
3181 only if the memory reference has a small offset or is an
3182 absolute address. */
3183 else if (GET_CODE (from
) == CONST_INT
3184 && INTVAL (from
) == 0
3185 && (MEM_VOLATILE_P (to
) == 0
3186 || m68hc11_small_indexed_indirect_p (to
, HImode
) == 0))
3188 output_asm_insn ("clr\t%h0", operands
);
3189 output_asm_insn ("clr\t%b0", operands
);
3193 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3194 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3195 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3196 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3202 ops
[0] = operands
[2];
3205 m68hc11_gen_movhi (insn
, ops
);
3207 ops
[1] = operands
[2];
3208 m68hc11_gen_movhi (insn
, ops
);
3213 /* !!!! SCz wrong here. */
3214 fatal_insn ("move insn not handled", insn
);
3219 m68hc11_notice_keep_cc (operands
[0]);
3220 output_asm_insn ("movw\t%1,%0", operands
);
3226 if (IS_STACK_POP (operands
[1]) && H_REG_P (operands
[0]))
3228 cc_status
= cc_prev_status
;
3229 switch (REGNO (operands
[0]))
3233 output_asm_insn ("pul%0", operands
);
3236 output_asm_insn ("pula", operands
);
3237 output_asm_insn ("pulb", operands
);
3244 /* Some moves to a hard register are special. Not all of them
3245 are really supported and we have to use a temporary
3246 location to provide them (either the stack of a temp var). */
3247 if (H_REG_P (operands
[0]))
3249 switch (REGNO (operands
[0]))
3252 if (X_REG_P (operands
[1]))
3254 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3256 m68hc11_output_swap (insn
, operands
);
3258 else if (next_insn_test_reg (insn
, operands
[0]))
3260 output_asm_insn ("stx\t%t0\n\tldd\t%t0", operands
);
3264 m68hc11_notice_keep_cc (operands
[0]);
3265 output_asm_insn ("pshx\n\tpula\n\tpulb", operands
);
3268 else if (Y_REG_P (operands
[1]))
3270 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3272 m68hc11_output_swap (insn
, operands
);
3276 /* %t means *ZTMP scratch register. */
3277 output_asm_insn ("sty\t%t1", operands
);
3278 output_asm_insn ("ldd\t%t1", operands
);
3281 else if (SP_REG_P (operands
[1]))
3286 if (optimize
== 0 || dead_register_here (insn
, ix_reg
) == 0)
3287 output_asm_insn ("xgdx", operands
);
3288 output_asm_insn ("tsx", operands
);
3289 output_asm_insn ("xgdx", operands
);
3291 else if (IS_STACK_POP (operands
[1]))
3293 output_asm_insn ("pula\n\tpulb", operands
);
3295 else if (GET_CODE (operands
[1]) == CONST_INT
3296 && INTVAL (operands
[1]) == 0)
3298 output_asm_insn ("clra\n\tclrb", operands
);
3302 output_asm_insn ("ldd\t%1", operands
);
3307 if (D_REG_P (operands
[1]))
3309 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3311 m68hc11_output_swap (insn
, operands
);
3313 else if (next_insn_test_reg (insn
, operands
[0]))
3315 output_asm_insn ("std\t%t0\n\tldx\t%t0", operands
);
3319 m68hc11_notice_keep_cc (operands
[0]);
3320 output_asm_insn ("pshb", operands
);
3321 output_asm_insn ("psha", operands
);
3322 output_asm_insn ("pulx", operands
);
3325 else if (Y_REG_P (operands
[1]))
3327 /* When both D and Y are dead, use the sequence xgdy, xgdx
3328 to move Y into X. The D and Y registers are modified. */
3329 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
)
3330 && dead_register_here (insn
, d_reg
))
3332 output_asm_insn ("xgdy", operands
);
3333 output_asm_insn ("xgdx", operands
);
3336 else if (!optimize_size
)
3338 output_asm_insn ("sty\t%t1", operands
);
3339 output_asm_insn ("ldx\t%t1", operands
);
3344 output_asm_insn ("pshy", operands
);
3345 output_asm_insn ("pulx", operands
);
3348 else if (SP_REG_P (operands
[1]))
3350 /* tsx, tsy preserve the flags */
3351 cc_status
= cc_prev_status
;
3352 output_asm_insn ("tsx", operands
);
3356 output_asm_insn ("ldx\t%1", operands
);
3361 if (D_REG_P (operands
[1]))
3363 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3365 m68hc11_output_swap (insn
, operands
);
3369 output_asm_insn ("std\t%t1", operands
);
3370 output_asm_insn ("ldy\t%t1", operands
);
3373 else if (X_REG_P (operands
[1]))
3375 /* When both D and X are dead, use the sequence xgdx, xgdy
3376 to move X into Y. The D and X registers are modified. */
3377 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
)
3378 && dead_register_here (insn
, d_reg
))
3380 output_asm_insn ("xgdx", operands
);
3381 output_asm_insn ("xgdy", operands
);
3384 else if (!optimize_size
)
3386 output_asm_insn ("stx\t%t1", operands
);
3387 output_asm_insn ("ldy\t%t1", operands
);
3392 output_asm_insn ("pshx", operands
);
3393 output_asm_insn ("puly", operands
);
3396 else if (SP_REG_P (operands
[1]))
3398 /* tsx, tsy preserve the flags */
3399 cc_status
= cc_prev_status
;
3400 output_asm_insn ("tsy", operands
);
3404 output_asm_insn ("ldy\t%1", operands
);
3408 case HARD_SP_REGNUM
:
3409 if (D_REG_P (operands
[1]))
3411 m68hc11_notice_keep_cc (operands
[0]);
3412 output_asm_insn ("xgdx", operands
);
3413 output_asm_insn ("txs", operands
);
3414 output_asm_insn ("xgdx", operands
);
3416 else if (X_REG_P (operands
[1]))
3418 /* tys, txs preserve the flags */
3419 cc_status
= cc_prev_status
;
3420 output_asm_insn ("txs", operands
);
3422 else if (Y_REG_P (operands
[1]))
3424 /* tys, txs preserve the flags */
3425 cc_status
= cc_prev_status
;
3426 output_asm_insn ("tys", operands
);
3430 /* lds sets the flags but the des does not. */
3432 output_asm_insn ("lds\t%1", operands
);
3433 output_asm_insn ("des", operands
);
3438 fatal_insn ("invalid register in the move instruction", insn
);
3443 if (SP_REG_P (operands
[1]) && REG_P (operands
[0])
3444 && REGNO (operands
[0]) == HARD_FRAME_POINTER_REGNUM
)
3446 output_asm_insn ("sts\t%0", operands
);
3450 if (IS_STACK_PUSH (operands
[0]) && H_REG_P (operands
[1]))
3452 cc_status
= cc_prev_status
;
3453 switch (REGNO (operands
[1]))
3457 output_asm_insn ("psh%1", operands
);
3460 output_asm_insn ("pshb", operands
);
3461 output_asm_insn ("psha", operands
);
3469 /* Operand 1 must be a hard register. */
3470 if (!H_REG_P (operands
[1]))
3472 fatal_insn ("invalid operand in the instruction", insn
);
3475 reg
= REGNO (operands
[1]);
3479 output_asm_insn ("std\t%0", operands
);
3483 output_asm_insn ("stx\t%0", operands
);
3487 output_asm_insn ("sty\t%0", operands
);
3490 case HARD_SP_REGNUM
:
3494 if (REG_P (operands
[0]) && REGNO (operands
[0]) == SOFT_TMP_REGNUM
)
3496 output_asm_insn ("pshx", operands
);
3497 output_asm_insn ("tsx", operands
);
3498 output_asm_insn ("inx", operands
);
3499 output_asm_insn ("inx", operands
);
3500 output_asm_insn ("stx\t%0", operands
);
3501 output_asm_insn ("pulx", operands
);
3504 else if (reg_mentioned_p (ix_reg
, operands
[0]))
3506 output_asm_insn ("sty\t%t0", operands
);
3507 output_asm_insn ("tsy", operands
);
3508 output_asm_insn ("sty\t%0", operands
);
3509 output_asm_insn ("ldy\t%t0", operands
);
3513 output_asm_insn ("stx\t%t0", operands
);
3514 output_asm_insn ("tsx", operands
);
3515 output_asm_insn ("stx\t%0", operands
);
3516 output_asm_insn ("ldx\t%t0", operands
);
3522 fatal_insn ("invalid register in the move instruction", insn
);
3528 m68hc11_gen_movqi (rtx insn
, rtx
*operands
)
3530 /* Move a register or memory to the same location.
3531 This is possible because such insn can appear
3532 in a non-optimizing mode. */
3533 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3535 cc_status
= cc_prev_status
;
3542 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3544 m68hc11_notice_keep_cc (operands
[0]);
3545 output_asm_insn ("tfr\t%1,%0", operands
);
3547 else if (H_REG_P (operands
[0]))
3549 if (IS_STACK_POP (operands
[1]))
3550 output_asm_insn ("pul%b0", operands
);
3551 else if (Q_REG_P (operands
[0]))
3552 output_asm_insn ("lda%0\t%b1", operands
);
3553 else if (D_REG_P (operands
[0]))
3554 output_asm_insn ("ldab\t%b1", operands
);
3558 else if (H_REG_P (operands
[1]))
3560 if (Q_REG_P (operands
[1]))
3561 output_asm_insn ("sta%1\t%b0", operands
);
3562 else if (D_REG_P (operands
[1]))
3563 output_asm_insn ("stab\t%b0", operands
);
3569 rtx from
= operands
[1];
3570 rtx to
= operands
[0];
3572 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3573 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3574 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3575 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3581 ops
[0] = operands
[2];
3584 m68hc11_gen_movqi (insn
, ops
);
3586 ops
[1] = operands
[2];
3587 m68hc11_gen_movqi (insn
, ops
);
3591 /* !!!! SCz wrong here. */
3592 fatal_insn ("move insn not handled", insn
);
3597 if (GET_CODE (from
) == CONST_INT
&& INTVAL (from
) == 0)
3599 output_asm_insn ("clr\t%b0", operands
);
3603 m68hc11_notice_keep_cc (operands
[0]);
3604 output_asm_insn ("movb\t%b1,%b0", operands
);
3612 if (H_REG_P (operands
[0]))
3614 switch (REGNO (operands
[0]))
3618 if (X_REG_P (operands
[1]))
3620 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3622 m68hc11_output_swap (insn
, operands
);
3626 output_asm_insn ("stx\t%t1", operands
);
3627 output_asm_insn ("ldab\t%T0", operands
);
3630 else if (Y_REG_P (operands
[1]))
3632 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3634 m68hc11_output_swap (insn
, operands
);
3638 output_asm_insn ("sty\t%t1", operands
);
3639 output_asm_insn ("ldab\t%T0", operands
);
3642 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3643 && !DA_REG_P (operands
[1]))
3645 output_asm_insn ("ldab\t%b1", operands
);
3647 else if (DA_REG_P (operands
[1]))
3649 output_asm_insn ("tab", operands
);
3653 cc_status
= cc_prev_status
;
3659 if (X_REG_P (operands
[1]))
3661 output_asm_insn ("stx\t%t1", operands
);
3662 output_asm_insn ("ldaa\t%T0", operands
);
3664 else if (Y_REG_P (operands
[1]))
3666 output_asm_insn ("sty\t%t1", operands
);
3667 output_asm_insn ("ldaa\t%T0", operands
);
3669 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3670 && !DA_REG_P (operands
[1]))
3672 output_asm_insn ("ldaa\t%b1", operands
);
3674 else if (!DA_REG_P (operands
[1]))
3676 output_asm_insn ("tba", operands
);
3680 cc_status
= cc_prev_status
;
3685 if (D_REG_P (operands
[1]))
3687 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3689 m68hc11_output_swap (insn
, operands
);
3693 output_asm_insn ("stab\t%T1", operands
);
3694 output_asm_insn ("ldx\t%t1", operands
);
3698 else if (Y_REG_P (operands
[1]))
3700 output_asm_insn ("sty\t%t0", operands
);
3701 output_asm_insn ("ldx\t%t0", operands
);
3703 else if (GET_CODE (operands
[1]) == CONST_INT
)
3705 output_asm_insn ("ldx\t%1", operands
);
3707 else if (dead_register_here (insn
, d_reg
))
3709 output_asm_insn ("ldab\t%b1", operands
);
3710 output_asm_insn ("xgdx", operands
);
3712 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3714 output_asm_insn ("xgdx", operands
);
3715 output_asm_insn ("ldab\t%b1", operands
);
3716 output_asm_insn ("xgdx", operands
);
3720 output_asm_insn ("pshb", operands
);
3721 output_asm_insn ("ldab\t%b1", operands
);
3722 output_asm_insn ("stab\t%T1", operands
);
3723 output_asm_insn ("ldx\t%t1", operands
);
3724 output_asm_insn ("pulb", operands
);
3730 if (D_REG_P (operands
[1]))
3732 output_asm_insn ("stab\t%T1", operands
);
3733 output_asm_insn ("ldy\t%t1", operands
);
3736 else if (X_REG_P (operands
[1]))
3738 output_asm_insn ("stx\t%t1", operands
);
3739 output_asm_insn ("ldy\t%t1", operands
);
3742 else if (GET_CODE (operands
[1]) == CONST_INT
)
3744 output_asm_insn ("ldy\t%1", operands
);
3746 else if (dead_register_here (insn
, d_reg
))
3748 output_asm_insn ("ldab\t%b1", operands
);
3749 output_asm_insn ("xgdy", operands
);
3751 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3753 output_asm_insn ("xgdy", operands
);
3754 output_asm_insn ("ldab\t%b1", operands
);
3755 output_asm_insn ("xgdy", operands
);
3759 output_asm_insn ("pshb", operands
);
3760 output_asm_insn ("ldab\t%b1", operands
);
3761 output_asm_insn ("stab\t%T1", operands
);
3762 output_asm_insn ("ldy\t%t1", operands
);
3763 output_asm_insn ("pulb", operands
);
3769 fatal_insn ("invalid register in the instruction", insn
);
3773 else if (H_REG_P (operands
[1]))
3775 switch (REGNO (operands
[1]))
3779 output_asm_insn ("stab\t%b0", operands
);
3783 output_asm_insn ("staa\t%b0", operands
);
3787 output_asm_insn ("xgdx\n\tstab\t%b0\n\txgdx", operands
);
3791 output_asm_insn ("xgdy\n\tstab\t%b0\n\txgdy", operands
);
3795 fatal_insn ("invalid register in the move instruction", insn
);
3802 fatal_insn ("operand 1 must be a hard register", insn
);
3806 /* Generate the code for a ROTATE or ROTATERT on a QI or HI mode.
3807 The source and destination must be D or A and the shift must
3810 m68hc11_gen_rotate (enum rtx_code code
, rtx insn
, rtx operands
[])
3814 if (GET_CODE (operands
[2]) != CONST_INT
3815 || (!D_REG_P (operands
[0]) && !DA_REG_P (operands
[0])))
3816 fatal_insn ("invalid rotate insn", insn
);
3818 val
= INTVAL (operands
[2]);
3819 if (code
== ROTATERT
)
3820 val
= GET_MODE_SIZE (GET_MODE (operands
[0])) * BITS_PER_UNIT
- val
;
3822 if (GET_MODE (operands
[0]) != QImode
)
3825 /* Rotate by 8-bits if the shift is within [5..11]. */
3826 if (val
>= 5 && val
<= 11)
3829 output_asm_insn ("exg\ta,b", operands
);
3832 output_asm_insn ("psha", operands
);
3833 output_asm_insn ("tba", operands
);
3834 output_asm_insn ("pulb", operands
);
3839 /* If the shift is big, invert the rotation. */
3849 /* Set the carry to bit-15, but don't change D yet. */
3850 if (GET_MODE (operands
[0]) != QImode
)
3852 output_asm_insn ("asra", operands
);
3853 output_asm_insn ("rola", operands
);
3856 /* Rotate B first to move the carry to bit-0. */
3857 if (D_REG_P (operands
[0]))
3858 output_asm_insn ("rolb", operands
);
3860 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
3861 output_asm_insn ("rola", operands
);
3868 /* Set the carry to bit-8 of D. */
3869 if (GET_MODE (operands
[0]) != QImode
)
3870 output_asm_insn ("tap", operands
);
3872 /* Rotate B first to move the carry to bit-7. */
3873 if (D_REG_P (operands
[0]))
3874 output_asm_insn ("rorb", operands
);
3876 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
3877 output_asm_insn ("rora", operands
);
3884 /* Store in cc_status the expressions that the condition codes will
3885 describe after execution of an instruction whose pattern is EXP.
3886 Do not alter them if the instruction would not alter the cc's. */
3889 m68hc11_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
3891 /* recognize SET insn's. */
3892 if (GET_CODE (exp
) == SET
)
3894 /* Jumps do not alter the cc's. */
3895 if (SET_DEST (exp
) == pc_rtx
)
3898 /* NOTE: most instructions don't affect the carry bit, but the
3899 bhi/bls/bhs/blo instructions use it. This isn't mentioned in
3900 the conditions.h header. */
3902 /* Function calls clobber the cc's. */
3903 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
3908 /* Tests and compares set the cc's in predictable ways. */
3909 else if (SET_DEST (exp
) == cc0_rtx
)
3911 cc_status
.flags
= 0;
3912 cc_status
.value1
= XEXP (exp
, 0);
3913 if (GET_CODE (XEXP (exp
, 1)) == COMPARE
3914 && XEXP (XEXP (exp
, 1), 1) == CONST0_RTX (GET_MODE (XEXP (XEXP (exp
, 1), 0))))
3915 cc_status
.value2
= XEXP (XEXP (exp
, 1), 0);
3917 cc_status
.value2
= XEXP (exp
, 1);
3921 /* All other instructions affect the condition codes. */
3922 cc_status
.flags
= 0;
3923 cc_status
.value1
= XEXP (exp
, 0);
3924 cc_status
.value2
= XEXP (exp
, 1);
3929 /* Default action if we haven't recognized something
3930 and returned earlier. */
3934 if (cc_status
.value2
!= 0)
3935 switch (GET_CODE (cc_status
.value2
))
3937 /* These logical operations can generate several insns.
3938 The flags are setup according to what is generated. */
3944 /* The (not ...) generates several 'com' instructions for
3945 non QImode. We have to invalidate the flags. */
3947 if (GET_MODE (cc_status
.value2
) != QImode
)
3959 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3960 cc_status
.flags
|= CC_NO_OVERFLOW
;
3963 /* The asl sets the overflow bit in such a way that this
3964 makes the flags unusable for a next compare insn. */
3968 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3969 cc_status
.flags
|= CC_NO_OVERFLOW
;
3972 /* A load/store instruction does not affect the carry. */
3977 cc_status
.flags
|= CC_NO_OVERFLOW
;
3983 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3985 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3986 cc_status
.value2
= 0;
3988 else if (cc_status
.value1
&& side_effects_p (cc_status
.value1
))
3989 cc_status
.value1
= 0;
3991 else if (cc_status
.value2
&& side_effects_p (cc_status
.value2
))
3992 cc_status
.value2
= 0;
3995 /* The current instruction does not affect the flags but changes
3996 the register 'reg'. See if the previous flags can be kept for the
3997 next instruction to avoid a comparison. */
3999 m68hc11_notice_keep_cc (rtx reg
)
4002 || cc_prev_status
.value1
== 0
4003 || rtx_equal_p (reg
, cc_prev_status
.value1
)
4004 || (cc_prev_status
.value2
4005 && reg_mentioned_p (reg
, cc_prev_status
.value2
)))
4008 cc_status
= cc_prev_status
;
4013 /* Machine Specific Reorg. */
4015 /* Z register replacement:
4017 GCC treats the Z register as an index base address register like
4018 X or Y. In general, it uses it during reload to compute the address
4019 of some operand. This helps the reload pass to avoid to fall into the
4020 register spill failure.
4022 The Z register is in the A_REGS class. In the machine description,
4023 the 'A' constraint matches it. The 'x' or 'y' constraints do not.
4025 It can appear everywhere an X or Y register can appear, except for
4026 some templates in the clobber section (when a clobber of X or Y is asked).
4027 For a given instruction, the template must ensure that no more than
4028 2 'A' registers are used. Otherwise, the register replacement is not
4031 To replace the Z register, the algorithm is not terrific:
4032 1. Insns that do not use the Z register are not changed
4033 2. When a Z register is used, we scan forward the insns to see
4034 a potential register to use: either X or Y and sometimes D.
4035 We stop when a call, a label or a branch is seen, or when we
4036 detect that both X and Y are used (probably at different times, but it does
4038 3. The register that will be used for the replacement of Z is saved
4039 in a .page0 register or on the stack. If the first instruction that
4040 used Z, uses Z as an input, the value is loaded from another .page0
4041 register. The replacement register is pushed on the stack in the
4042 rare cases where a compare insn uses Z and we couldn't find if X/Y
4044 4. The Z register is replaced in all instructions until we reach
4045 the end of the Z-block, as detected by step 2.
4046 5. If we detect that Z is still alive, its value is saved.
4047 If the replacement register is alive, its old value is loaded.
4049 The Z register can be disabled with -ffixed-z.
4059 int must_restore_reg
;
4070 int save_before_last
;
4071 int z_loaded_with_sp
;
4074 static int m68hc11_check_z_replacement (rtx
, struct replace_info
*);
4075 static void m68hc11_find_z_replacement (rtx
, struct replace_info
*);
4076 static void m68hc11_z_replacement (rtx
);
4077 static void m68hc11_reassign_regs (rtx
);
4079 int z_replacement_completed
= 0;
4081 /* Analyze the insn to find out which replacement register to use and
4082 the boundaries of the replacement.
4083 Returns 0 if we reached the last insn to be replaced, 1 if we can
4084 continue replacement in next insns. */
4087 m68hc11_check_z_replacement (rtx insn
, struct replace_info
*info
)
4089 int this_insn_uses_ix
;
4090 int this_insn_uses_iy
;
4091 int this_insn_uses_z
;
4092 int this_insn_uses_z_in_dst
;
4093 int this_insn_uses_d
;
4097 /* A call is said to clobber the Z register, we don't need
4098 to save the value of Z. We also don't need to restore
4099 the replacement register (unless it is used by the call). */
4100 if (GET_CODE (insn
) == CALL_INSN
)
4102 body
= PATTERN (insn
);
4104 info
->can_use_d
= 0;
4106 /* If the call is an indirect call with Z, we have to use the
4107 Y register because X can be used as an input (D+X).
4108 We also must not save Z nor restore Y. */
4109 if (reg_mentioned_p (z_reg
, body
))
4111 insn
= NEXT_INSN (insn
);
4114 info
->found_call
= 1;
4115 info
->must_restore_reg
= 0;
4116 info
->last
= NEXT_INSN (insn
);
4118 info
->need_save_z
= 0;
4121 if (GET_CODE (insn
) == CODE_LABEL
4122 || GET_CODE (insn
) == BARRIER
|| GET_CODE (insn
) == ASM_INPUT
)
4125 if (GET_CODE (insn
) == JUMP_INSN
)
4127 if (reg_mentioned_p (z_reg
, insn
) == 0)
4130 info
->can_use_d
= 0;
4131 info
->must_save_reg
= 0;
4132 info
->must_restore_reg
= 0;
4133 info
->need_save_z
= 0;
4134 info
->last
= NEXT_INSN (insn
);
4137 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4142 /* Z register dies here. */
4143 z_dies_here
= find_regno_note (insn
, REG_DEAD
, HARD_Z_REGNUM
) != NULL
;
4145 body
= PATTERN (insn
);
4146 if (GET_CODE (body
) == SET
)
4148 rtx src
= XEXP (body
, 1);
4149 rtx dst
= XEXP (body
, 0);
4151 /* Condition code is set here. We have to restore the X/Y and
4152 save into Z before any test/compare insn because once we save/restore
4153 we can change the condition codes. When the compare insn uses Z and
4154 we can't use X/Y, the comparison is made with the *ZREG soft register
4155 (this is supported by cmphi, cmpqi, tsthi, tstqi patterns). */
4158 if ((GET_CODE (src
) == REG
&& REGNO (src
) == HARD_Z_REGNUM
)
4159 || (GET_CODE (src
) == COMPARE
&&
4160 ((rtx_equal_p (XEXP (src
, 0), z_reg
)
4161 && H_REG_P (XEXP (src
, 1)))
4162 || (rtx_equal_p (XEXP (src
, 1), z_reg
)
4163 && H_REG_P (XEXP (src
, 0))))))
4165 if (insn
== info
->first
)
4167 info
->must_load_z
= 0;
4168 info
->must_save_reg
= 0;
4169 info
->must_restore_reg
= 0;
4170 info
->need_save_z
= 0;
4171 info
->found_call
= 1;
4172 info
->regno
= SOFT_Z_REGNUM
;
4173 info
->last
= NEXT_INSN (insn
);
4177 if (reg_mentioned_p (z_reg
, src
) == 0)
4179 info
->can_use_d
= 0;
4183 if (insn
!= info
->first
)
4186 /* Compare insn which uses Z. We have to save/restore the X/Y
4187 register without modifying the condition codes. For this
4188 we have to use a push/pop insn. */
4189 info
->must_push_reg
= 1;
4193 /* Z reg is set to something new. We don't need to load it. */
4196 if (!reg_mentioned_p (z_reg
, src
))
4198 /* Z reg is used before being set. Treat this as
4199 a new sequence of Z register replacement. */
4200 if (insn
!= info
->first
)
4204 info
->must_load_z
= 0;
4206 info
->z_set_count
++;
4207 info
->z_value
= src
;
4209 info
->z_loaded_with_sp
= 1;
4211 else if (reg_mentioned_p (z_reg
, dst
))
4212 info
->can_use_d
= 0;
4214 this_insn_uses_d
= reg_mentioned_p (d_reg
, src
)
4215 | reg_mentioned_p (d_reg
, dst
);
4216 this_insn_uses_ix
= reg_mentioned_p (ix_reg
, src
)
4217 | reg_mentioned_p (ix_reg
, dst
);
4218 this_insn_uses_iy
= reg_mentioned_p (iy_reg
, src
)
4219 | reg_mentioned_p (iy_reg
, dst
);
4220 this_insn_uses_z
= reg_mentioned_p (z_reg
, src
);
4222 /* If z is used as an address operand (like (MEM (reg z))),
4223 we can't replace it with d. */
4224 if (this_insn_uses_z
&& !Z_REG_P (src
)
4225 && !(m68hc11_arith_operator (src
, GET_MODE (src
))
4226 && Z_REG_P (XEXP (src
, 0))
4227 && !reg_mentioned_p (z_reg
, XEXP (src
, 1))
4228 && insn
== info
->first
4229 && dead_register_here (insn
, d_reg
)))
4230 info
->can_use_d
= 0;
4232 this_insn_uses_z_in_dst
= reg_mentioned_p (z_reg
, dst
);
4233 if (TARGET_M6812
&& !z_dies_here
4234 && ((this_insn_uses_z
&& side_effects_p (src
))
4235 || (this_insn_uses_z_in_dst
&& side_effects_p (dst
))))
4237 info
->need_save_z
= 1;
4238 info
->z_set_count
++;
4240 this_insn_uses_z
|= this_insn_uses_z_in_dst
;
4242 if (this_insn_uses_z
&& this_insn_uses_ix
&& this_insn_uses_iy
)
4244 fatal_insn ("registers IX, IY and Z used in the same INSN", insn
);
4247 if (this_insn_uses_d
)
4248 info
->can_use_d
= 0;
4250 /* IX and IY are used at the same time, we have to restore
4251 the value of the scratch register before this insn. */
4252 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4257 if (this_insn_uses_ix
&& X_REG_P (dst
) && GET_MODE (dst
) == SImode
)
4258 info
->can_use_d
= 0;
4260 if (info
->x_used
== 0 && this_insn_uses_ix
)
4264 /* We have a (set (REG:HI X) (REG:HI Z)).
4265 Since we use Z as the replacement register, this insn
4266 is no longer necessary. We turn it into a note. We must
4267 not reload the old value of X. */
4268 if (X_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4272 info
->need_save_z
= 0;
4275 info
->must_save_reg
= 0;
4276 info
->must_restore_reg
= 0;
4277 info
->found_call
= 1;
4278 info
->can_use_d
= 0;
4279 SET_INSN_DELETED (insn
);
4280 info
->last
= NEXT_INSN (insn
);
4285 && (rtx_equal_p (src
, z_reg
)
4286 || (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
))))
4290 info
->need_save_z
= 0;
4293 info
->last
= NEXT_INSN (insn
);
4294 info
->must_save_reg
= 0;
4295 info
->must_restore_reg
= 0;
4297 else if (X_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4298 && !reg_mentioned_p (ix_reg
, src
))
4303 info
->need_save_z
= 0;
4305 else if (TARGET_M6812
&& side_effects_p (src
))
4308 info
->must_restore_reg
= 0;
4313 info
->save_before_last
= 1;
4315 info
->must_restore_reg
= 0;
4316 info
->last
= NEXT_INSN (insn
);
4318 else if (info
->can_use_d
)
4320 info
->last
= NEXT_INSN (insn
);
4326 if (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
)
4327 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_X_REGNUM
)
4329 info
->need_save_z
= 0;
4331 info
->last
= NEXT_INSN (insn
);
4332 info
->regno
= HARD_X_REGNUM
;
4333 info
->must_save_reg
= 0;
4334 info
->must_restore_reg
= 0;
4337 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, ix_reg
))
4339 info
->regno
= HARD_X_REGNUM
;
4340 info
->must_restore_reg
= 0;
4341 info
->must_save_reg
= 0;
4345 if (info
->y_used
== 0 && this_insn_uses_iy
)
4349 if (Y_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4353 info
->need_save_z
= 0;
4356 info
->must_save_reg
= 0;
4357 info
->must_restore_reg
= 0;
4358 info
->found_call
= 1;
4359 info
->can_use_d
= 0;
4360 SET_INSN_DELETED (insn
);
4361 info
->last
= NEXT_INSN (insn
);
4366 && (rtx_equal_p (src
, z_reg
)
4367 || (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
))))
4372 info
->need_save_z
= 0;
4374 info
->last
= NEXT_INSN (insn
);
4375 info
->must_save_reg
= 0;
4376 info
->must_restore_reg
= 0;
4378 else if (Y_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4379 && !reg_mentioned_p (iy_reg
, src
))
4384 info
->need_save_z
= 0;
4386 else if (TARGET_M6812
&& side_effects_p (src
))
4389 info
->must_restore_reg
= 0;
4394 info
->save_before_last
= 1;
4396 info
->must_restore_reg
= 0;
4397 info
->last
= NEXT_INSN (insn
);
4399 else if (info
->can_use_d
)
4401 info
->last
= NEXT_INSN (insn
);
4408 if (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
)
4409 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_Y_REGNUM
)
4411 info
->need_save_z
= 0;
4413 info
->last
= NEXT_INSN (insn
);
4414 info
->regno
= HARD_Y_REGNUM
;
4415 info
->must_save_reg
= 0;
4416 info
->must_restore_reg
= 0;
4419 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, iy_reg
))
4421 info
->regno
= HARD_Y_REGNUM
;
4422 info
->must_restore_reg
= 0;
4423 info
->must_save_reg
= 0;
4429 info
->need_save_z
= 0;
4431 if (info
->last
== 0)
4432 info
->last
= NEXT_INSN (insn
);
4435 return info
->last
!= NULL_RTX
? 0 : 1;
4437 if (GET_CODE (body
) == PARALLEL
)
4440 char ix_clobber
= 0;
4441 char iy_clobber
= 0;
4443 this_insn_uses_iy
= 0;
4444 this_insn_uses_ix
= 0;
4445 this_insn_uses_z
= 0;
4447 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
4450 int uses_ix
, uses_iy
, uses_z
;
4452 x
= XVECEXP (body
, 0, i
);
4454 if (info
->can_use_d
&& reg_mentioned_p (d_reg
, x
))
4455 info
->can_use_d
= 0;
4457 uses_ix
= reg_mentioned_p (ix_reg
, x
);
4458 uses_iy
= reg_mentioned_p (iy_reg
, x
);
4459 uses_z
= reg_mentioned_p (z_reg
, x
);
4460 if (GET_CODE (x
) == CLOBBER
)
4462 ix_clobber
|= uses_ix
;
4463 iy_clobber
|= uses_iy
;
4464 z_clobber
|= uses_z
;
4468 this_insn_uses_ix
|= uses_ix
;
4469 this_insn_uses_iy
|= uses_iy
;
4470 this_insn_uses_z
|= uses_z
;
4472 if (uses_z
&& GET_CODE (x
) == SET
)
4474 rtx dst
= XEXP (x
, 0);
4477 info
->z_set_count
++;
4479 if (TARGET_M6812
&& uses_z
&& side_effects_p (x
))
4480 info
->need_save_z
= 1;
4483 info
->need_save_z
= 0;
4487 printf ("Uses X:%d Y:%d Z:%d CX:%d CY:%d CZ:%d\n",
4488 this_insn_uses_ix
, this_insn_uses_iy
,
4489 this_insn_uses_z
, ix_clobber
, iy_clobber
, z_clobber
);
4492 if (this_insn_uses_z
)
4493 info
->can_use_d
= 0;
4495 if (z_clobber
&& info
->first
!= insn
)
4497 info
->need_save_z
= 0;
4501 if (z_clobber
&& info
->x_used
== 0 && info
->y_used
== 0)
4503 if (this_insn_uses_z
== 0 && insn
== info
->first
)
4505 info
->must_load_z
= 0;
4507 if (dead_register_here (insn
, d_reg
))
4509 info
->regno
= HARD_D_REGNUM
;
4510 info
->must_save_reg
= 0;
4511 info
->must_restore_reg
= 0;
4513 else if (dead_register_here (insn
, ix_reg
))
4515 info
->regno
= HARD_X_REGNUM
;
4516 info
->must_save_reg
= 0;
4517 info
->must_restore_reg
= 0;
4519 else if (dead_register_here (insn
, iy_reg
))
4521 info
->regno
= HARD_Y_REGNUM
;
4522 info
->must_save_reg
= 0;
4523 info
->must_restore_reg
= 0;
4525 if (info
->regno
>= 0)
4527 info
->last
= NEXT_INSN (insn
);
4530 if (this_insn_uses_ix
== 0)
4532 info
->regno
= HARD_X_REGNUM
;
4533 info
->must_save_reg
= 1;
4534 info
->must_restore_reg
= 1;
4536 else if (this_insn_uses_iy
== 0)
4538 info
->regno
= HARD_Y_REGNUM
;
4539 info
->must_save_reg
= 1;
4540 info
->must_restore_reg
= 1;
4544 info
->regno
= HARD_D_REGNUM
;
4545 info
->must_save_reg
= 1;
4546 info
->must_restore_reg
= 1;
4548 info
->last
= NEXT_INSN (insn
);
4552 if (((info
->x_used
|| this_insn_uses_ix
) && iy_clobber
)
4553 || ((info
->y_used
|| this_insn_uses_iy
) && ix_clobber
))
4555 if (this_insn_uses_z
)
4557 if (info
->y_used
== 0 && iy_clobber
)
4559 info
->regno
= HARD_Y_REGNUM
;
4560 info
->must_save_reg
= 0;
4561 info
->must_restore_reg
= 0;
4563 if (info
->first
!= insn
4564 && ((info
->y_used
&& ix_clobber
)
4565 || (info
->x_used
&& iy_clobber
)))
4568 info
->last
= NEXT_INSN (insn
);
4569 info
->save_before_last
= 1;
4573 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4575 if (this_insn_uses_z
)
4577 fatal_insn ("cannot do z-register replacement", insn
);
4581 if (info
->x_used
== 0 && (this_insn_uses_ix
|| ix_clobber
))
4588 if (iy_clobber
|| z_clobber
)
4590 info
->last
= NEXT_INSN (insn
);
4591 info
->save_before_last
= 1;
4596 if (info
->y_used
== 0 && (this_insn_uses_iy
|| iy_clobber
))
4603 if (ix_clobber
|| z_clobber
)
4605 info
->last
= NEXT_INSN (insn
);
4606 info
->save_before_last
= 1;
4613 info
->need_save_z
= 0;
4617 if (GET_CODE (body
) == CLOBBER
)
4620 /* IX and IY are used at the same time, we have to restore
4621 the value of the scratch register before this insn. */
4622 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4626 if (info
->x_used
== 0 && this_insn_uses_ix
)
4634 if (info
->y_used
== 0 && this_insn_uses_iy
)
4648 m68hc11_find_z_replacement (rtx insn
, struct replace_info
*info
)
4652 info
->replace_reg
= NULL_RTX
;
4653 info
->must_load_z
= 1;
4654 info
->need_save_z
= 1;
4655 info
->must_save_reg
= 1;
4656 info
->must_restore_reg
= 1;
4660 info
->can_use_d
= TARGET_M6811
? 1 : 0;
4661 info
->found_call
= 0;
4665 info
->z_set_count
= 0;
4666 info
->z_value
= NULL_RTX
;
4667 info
->must_push_reg
= 0;
4668 info
->save_before_last
= 0;
4669 info
->z_loaded_with_sp
= 0;
4671 /* Scan the insn forward to find an address register that is not used.
4673 - the flow of the program changes,
4674 - when we detect that both X and Y are necessary,
4675 - when the Z register dies,
4676 - when the condition codes are set. */
4678 for (; insn
&& info
->z_died
== 0; insn
= NEXT_INSN (insn
))
4680 if (m68hc11_check_z_replacement (insn
, info
) == 0)
4684 /* May be we can use Y or X if they contain the same value as Z.
4685 This happens very often after the reload. */
4686 if (info
->z_set_count
== 1)
4688 rtx p
= info
->first
;
4693 v
= find_last_value (iy_reg
, &p
, insn
, 1);
4695 else if (info
->y_used
)
4697 v
= find_last_value (ix_reg
, &p
, insn
, 1);
4699 if (v
&& (v
!= iy_reg
&& v
!= ix_reg
) && rtx_equal_p (v
, info
->z_value
))
4702 info
->regno
= HARD_Y_REGNUM
;
4704 info
->regno
= HARD_X_REGNUM
;
4705 info
->must_load_z
= 0;
4706 info
->must_save_reg
= 0;
4707 info
->must_restore_reg
= 0;
4708 info
->found_call
= 1;
4711 if (info
->z_set_count
== 0)
4712 info
->need_save_z
= 0;
4715 info
->need_save_z
= 0;
4717 if (info
->last
== 0)
4720 if (info
->regno
>= 0)
4723 info
->replace_reg
= gen_rtx_REG (HImode
, reg
);
4725 else if (info
->can_use_d
)
4727 reg
= HARD_D_REGNUM
;
4728 info
->replace_reg
= d_reg
;
4730 else if (info
->x_used
)
4732 reg
= HARD_Y_REGNUM
;
4733 info
->replace_reg
= iy_reg
;
4737 reg
= HARD_X_REGNUM
;
4738 info
->replace_reg
= ix_reg
;
4742 if (info
->must_save_reg
&& info
->must_restore_reg
)
4744 if (insn
&& dead_register_here (insn
, info
->replace_reg
))
4746 info
->must_save_reg
= 0;
4747 info
->must_restore_reg
= 0;
4752 /* The insn uses the Z register. Find a replacement register for it
4753 (either X or Y) and replace it in the insn and the next ones until
4754 the flow changes or the replacement register is used. Instructions
4755 are emitted before and after the Z-block to preserve the value of
4756 Z and of the replacement register. */
4759 m68hc11_z_replacement (rtx insn
)
4763 struct replace_info info
;
4765 /* Find trivial case where we only need to replace z with the
4766 equivalent soft register. */
4767 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SET
)
4769 rtx body
= PATTERN (insn
);
4770 rtx src
= XEXP (body
, 1);
4771 rtx dst
= XEXP (body
, 0);
4773 if (Z_REG_P (dst
) && (H_REG_P (src
) && !SP_REG_P (src
)))
4775 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4778 else if (Z_REG_P (src
)
4779 && ((H_REG_P (dst
) && !SP_REG_P (src
)) || dst
== cc0_rtx
))
4781 XEXP (body
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4784 else if (D_REG_P (dst
)
4785 && m68hc11_arith_operator (src
, GET_MODE (src
))
4786 && D_REG_P (XEXP (src
, 0)) && Z_REG_P (XEXP (src
, 1)))
4788 XEXP (src
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4791 else if (Z_REG_P (dst
) && GET_CODE (src
) == CONST_INT
4792 && INTVAL (src
) == 0)
4794 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4795 /* Force it to be re-recognized. */
4796 INSN_CODE (insn
) = -1;
4801 m68hc11_find_z_replacement (insn
, &info
);
4803 replace_reg
= info
.replace_reg
;
4804 replace_reg_qi
= NULL_RTX
;
4806 /* Save the X register in a .page0 location. */
4807 if (info
.must_save_reg
&& !info
.must_push_reg
)
4811 if (info
.must_push_reg
&& 0)
4812 dst
= gen_rtx_MEM (HImode
,
4813 gen_rtx_PRE_DEC (HImode
,
4814 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
4816 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
4818 emit_insn_before (gen_movhi (dst
,
4819 gen_rtx_REG (HImode
, info
.regno
)), insn
);
4821 if (info
.must_load_z
&& !info
.must_push_reg
)
4823 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
4824 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
)),
4829 /* Replace all occurrence of Z by replace_reg.
4830 Stop when the last instruction to replace is reached.
4831 Also stop when we detect a change in the flow (but it's not
4832 necessary; just safeguard). */
4834 for (; insn
&& insn
!= info
.last
; insn
= NEXT_INSN (insn
))
4838 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == BARRIER
)
4841 if (GET_CODE (insn
) != INSN
4842 && GET_CODE (insn
) != CALL_INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4845 body
= PATTERN (insn
);
4846 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
4847 || GET_CODE (body
) == ASM_OPERANDS
4848 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4852 if (debug_m6811
&& reg_mentioned_p (replace_reg
, body
))
4854 printf ("Reg mentioned here...:\n");
4859 /* Stack pointer was decremented by 2 due to the push.
4860 Correct that by adding 2 to the destination. */
4861 if (info
.must_push_reg
4862 && info
.z_loaded_with_sp
&& GET_CODE (body
) == SET
)
4866 src
= SET_SRC (body
);
4867 dst
= SET_DEST (body
);
4868 if (SP_REG_P (src
) && Z_REG_P (dst
))
4869 emit_insn_after (gen_addhi3 (dst
, dst
, const2_rtx
), insn
);
4872 /* Replace any (REG:HI Z) occurrence by either X or Y. */
4873 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
4875 INSN_CODE (insn
) = -1;
4876 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
4877 fatal_insn ("cannot do z-register replacement", insn
);
4880 /* Likewise for (REG:QI Z). */
4881 if (reg_mentioned_p (z_reg
, insn
))
4883 if (replace_reg_qi
== NULL_RTX
)
4884 replace_reg_qi
= gen_rtx_REG (QImode
, REGNO (replace_reg
));
4885 validate_replace_rtx (z_reg_qi
, replace_reg_qi
, insn
);
4888 /* If there is a REG_INC note on Z, replace it with a
4889 REG_INC note on the replacement register. This is necessary
4890 to make sure that the flow pass will identify the change
4891 and it will not remove a possible insn that saves Z. */
4892 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
4894 if (REG_NOTE_KIND (note
) == REG_INC
4895 && GET_CODE (XEXP (note
, 0)) == REG
4896 && REGNO (XEXP (note
, 0)) == REGNO (z_reg
))
4898 XEXP (note
, 0) = replace_reg
;
4902 if (GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4906 /* Save Z before restoring the old value. */
4907 if (insn
&& info
.need_save_z
&& !info
.must_push_reg
)
4909 rtx save_pos_insn
= insn
;
4911 /* If Z is clobber by the last insn, we have to save its value
4912 before the last instruction. */
4913 if (info
.save_before_last
)
4914 save_pos_insn
= PREV_INSN (save_pos_insn
);
4916 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
4917 gen_rtx_REG (HImode
, info
.regno
)),
4921 if (info
.must_push_reg
&& info
.last
)
4925 body
= PATTERN (info
.last
);
4926 new_body
= gen_rtx_PARALLEL (VOIDmode
,
4928 gen_rtx_USE (VOIDmode
,
4930 gen_rtx_USE (VOIDmode
,
4931 gen_rtx_REG (HImode
,
4933 PATTERN (info
.last
) = new_body
;
4935 /* Force recognition on insn since we changed it. */
4936 INSN_CODE (insn
) = -1;
4938 if (!validate_replace_rtx (z_reg
, replace_reg
, info
.last
))
4940 fatal_insn ("invalid Z register replacement for insn", insn
);
4942 insn
= NEXT_INSN (info
.last
);
4945 /* Restore replacement register unless it was died. */
4946 if (insn
&& info
.must_restore_reg
&& !info
.must_push_reg
)
4950 if (info
.must_push_reg
&& 0)
4951 dst
= gen_rtx_MEM (HImode
,
4952 gen_rtx_POST_INC (HImode
,
4953 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
4955 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
4957 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
4964 /* Scan all the insn and re-affects some registers
4965 - The Z register (if it was used), is affected to X or Y depending
4966 on the instruction. */
4969 m68hc11_reassign_regs (rtx first
)
4973 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
4974 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
4975 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
4976 z_reg_qi
= gen_rtx_REG (QImode
, HARD_Z_REGNUM
);
4978 /* Scan all insns to replace Z by X or Y preserving the old value
4979 of X/Y and restoring it afterward. */
4981 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4985 if (GET_CODE (insn
) == CODE_LABEL
4986 || GET_CODE (insn
) == NOTE
|| GET_CODE (insn
) == BARRIER
)
4992 body
= PATTERN (insn
);
4993 if (GET_CODE (body
) == CLOBBER
|| GET_CODE (body
) == USE
)
4996 if (GET_CODE (body
) == CONST_INT
|| GET_CODE (body
) == ASM_INPUT
4997 || GET_CODE (body
) == ASM_OPERANDS
4998 || GET_CODE (body
) == UNSPEC
|| GET_CODE (body
) == UNSPEC_VOLATILE
)
5001 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
5002 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
5005 /* If Z appears in this insn, replace it in the current insn
5006 and the next ones until the flow changes or we have to
5007 restore back the replacement register. */
5009 if (reg_mentioned_p (z_reg
, body
))
5011 m68hc11_z_replacement (insn
);
5016 printf ("insn not handled by Z replacement:\n");
5024 /* Machine-dependent reorg pass.
5025 Specific optimizations are defined here:
5026 - this pass changes the Z register into either X or Y
5027 (it preserves X/Y previous values in a memory slot in page0).
5029 When this pass is finished, the global variable
5030 'z_replacement_completed' is set to 2. */
5033 m68hc11_reorg (void)
5038 z_replacement_completed
= 0;
5039 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
5040 first
= get_insns ();
5042 /* Some RTX are shared at this point. This breaks the Z register
5043 replacement, unshare everything. */
5044 unshare_all_rtl_again (first
);
5046 /* Force a split of all splittable insn. This is necessary for the
5047 Z register replacement mechanism because we end up with basic insns. */
5048 split_all_insns_noflow ();
5051 z_replacement_completed
= 1;
5052 m68hc11_reassign_regs (first
);
5055 compute_bb_for_insn ();
5057 /* After some splitting, there are some opportunities for CSE pass.
5058 This happens quite often when 32-bit or above patterns are split. */
5059 if (optimize
> 0 && split_done
)
5061 reload_cse_regs (first
);
5064 /* Re-create the REG_DEAD notes. These notes are used in the machine
5065 description to use the best assembly directives. */
5068 df_note_add_problem ();
5070 df_remove_problem (df_note
);
5073 z_replacement_completed
= 2;
5075 /* If optimizing, then go ahead and split insns that must be
5076 split after Z register replacement. This gives more opportunities
5077 for peephole (in particular for consecutives xgdx/xgdy). */
5079 split_all_insns_noflow ();
5081 /* Once insns are split after the z_replacement_completed == 2,
5082 we must not re-run the life_analysis. The xgdx/xgdy patterns
5083 are not recognized and the life_analysis pass removes some
5084 insns because it thinks some (SETs) are noops or made to dead
5085 stores (which is false due to the swap).
5087 Do a simple pass to eliminate the noop set that the final
5088 split could generate (because it was easier for split definition). */
5092 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5096 if (INSN_DELETED_P (insn
))
5101 /* Remove the (set (R) (R)) insns generated by some splits. */
5102 body
= PATTERN (insn
);
5103 if (GET_CODE (body
) == SET
5104 && rtx_equal_p (SET_SRC (body
), SET_DEST (body
)))
5106 SET_INSN_DELETED (insn
);
5113 /* Override memcpy */
5116 m68hc11_init_libfuncs (void)
5118 memcpy_libfunc
= init_one_libfunc ("__memcpy");
5119 memcmp_libfunc
= init_one_libfunc ("__memcmp");
5120 memset_libfunc
= init_one_libfunc ("__memset");
5125 /* Cost functions. */
5127 /* Cost of moving memory. */
5129 m68hc11_memory_move_cost (enum machine_mode mode
, enum reg_class rclass
,
5130 int in ATTRIBUTE_UNUSED
)
5132 if (rclass
<= H_REGS
&& rclass
> NO_REGS
)
5134 if (GET_MODE_SIZE (mode
) <= 2)
5135 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5137 return COSTS_N_INSNS (2) + (reload_completed
| reload_in_progress
);
5141 if (GET_MODE_SIZE (mode
) <= 2)
5142 return COSTS_N_INSNS (3);
5144 return COSTS_N_INSNS (4);
5149 /* Cost of moving data from a register of class 'from' to on in class 'to'.
5150 Reload does not check the constraint of set insns when the two registers
5151 have a move cost of 2. Setting a higher cost will force reload to check
5154 m68hc11_register_move_cost (enum machine_mode mode
, enum reg_class from
,
5157 /* All costs are symmetric, so reduce cases by putting the
5158 lower number class as the destination. */
5161 enum reg_class tmp
= to
;
5162 to
= from
, from
= tmp
;
5165 return m68hc11_memory_move_cost (mode
, S_REGS
, 0);
5166 else if (from
<= S_REGS
)
5167 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5169 return COSTS_N_INSNS (2);
5173 /* Provide the costs of an addressing mode that contains ADDR.
5174 If ADDR is not a valid address, its cost is irrelevant. */
5177 m68hc11_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
5181 switch (GET_CODE (addr
))
5184 /* Make the cost of hard registers and specially SP, FP small. */
5185 if (REGNO (addr
) < FIRST_PSEUDO_REGISTER
)
5202 register rtx plus0
= XEXP (addr
, 0);
5203 register rtx plus1
= XEXP (addr
, 1);
5205 if (GET_CODE (plus0
) != REG
)
5208 switch (GET_CODE (plus1
))
5211 if (INTVAL (plus1
) >= 2 * m68hc11_max_offset
5212 || INTVAL (plus1
) < m68hc11_min_offset
)
5214 else if (INTVAL (plus1
) >= m68hc11_max_offset
)
5218 if (REGNO (plus0
) < FIRST_PSEUDO_REGISTER
)
5240 if (SP_REG_P (XEXP (addr
, 0)))
5249 printf ("Address cost: %d for :", cost
);
5258 m68hc11_shift_cost (enum machine_mode mode
, rtx x
, int shift
)
5262 total
= rtx_cost (x
, SET
, !optimize_size
);
5264 total
+= m68hc11_cost
->shiftQI_const
[shift
% 8];
5265 else if (mode
== HImode
)
5266 total
+= m68hc11_cost
->shiftHI_const
[shift
% 16];
5267 else if (shift
== 8 || shift
== 16 || shift
== 32)
5268 total
+= m68hc11_cost
->shiftHI_const
[8];
5269 else if (shift
!= 0 && shift
!= 16 && shift
!= 32)
5271 total
+= m68hc11_cost
->shiftHI_const
[1] * shift
;
5274 /* For SI and others, the cost is higher. */
5275 if (GET_MODE_SIZE (mode
) > 2 && (shift
% 16) != 0)
5276 total
*= GET_MODE_SIZE (mode
) / 2;
5278 /* When optimizing for size, make shift more costly so that
5279 multiplications are preferred. */
5280 if (optimize_size
&& (shift
% 8) != 0)
5287 m68hc11_rtx_costs_1 (rtx x
, enum rtx_code code
,
5288 enum rtx_code outer_code ATTRIBUTE_UNUSED
)
5290 enum machine_mode mode
= GET_MODE (x
);
5301 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5303 return m68hc11_shift_cost (mode
, XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
5306 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5307 total
+= m68hc11_cost
->shift_var
;
5313 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5314 total
+= m68hc11_cost
->logical
;
5316 /* Logical instructions are byte instructions only. */
5317 total
*= GET_MODE_SIZE (mode
);
5322 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5323 total
+= m68hc11_cost
->add
;
5324 if (GET_MODE_SIZE (mode
) > 2)
5326 total
*= GET_MODE_SIZE (mode
) / 2;
5333 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5337 total
+= m68hc11_cost
->divQI
;
5341 total
+= m68hc11_cost
->divHI
;
5346 total
+= m68hc11_cost
->divSI
;
5352 /* mul instruction produces 16-bit result. */
5353 if (mode
== HImode
&& GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5354 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5355 return m68hc11_cost
->multQI
5356 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
, !optimize_size
)
5357 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
, !optimize_size
);
5359 /* emul instruction produces 32-bit result for 68HC12. */
5360 if (TARGET_M6812
&& mode
== SImode
5361 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5362 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5363 return m68hc11_cost
->multHI
5364 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
, !optimize_size
)
5365 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
, !optimize_size
);
5367 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
)
5368 + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5372 total
+= m68hc11_cost
->multQI
;
5376 total
+= m68hc11_cost
->multHI
;
5381 total
+= m68hc11_cost
->multSI
;
5388 extra_cost
= COSTS_N_INSNS (2);
5396 total
= extra_cost
+ rtx_cost (XEXP (x
, 0), code
, !optimize_size
);
5399 return total
+ COSTS_N_INSNS (1);
5403 return total
+ COSTS_N_INSNS (2);
5407 return total
+ COSTS_N_INSNS (4);
5409 return total
+ COSTS_N_INSNS (8);
5412 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
5413 return COSTS_N_INSNS (1);
5415 return COSTS_N_INSNS (1);
5418 return COSTS_N_INSNS (4);
5423 m68hc11_rtx_costs (rtx x
, int codearg
, int outer_code_arg
, int *total
,
5424 bool speed ATTRIBUTE_UNUSED
)
5426 enum rtx_code code
= (enum rtx_code
) codearg
;
5427 enum rtx_code outer_code
= (enum rtx_code
) outer_code_arg
;
5431 /* Constants are cheap. Moving them in registers must be avoided
5432 because most instructions do not handle two register operands. */
5438 /* Logical and arithmetic operations with a constant operand are
5439 better because they are not supported with two registers. */
5441 if (outer_code
== SET
&& x
== const0_rtx
)
5442 /* After reload, the reload_cse pass checks the cost to change
5443 a SET into a PLUS. Make const0 cheap then. */
5444 *total
= 1 - reload_completed
;
5450 if (outer_code
!= COMPARE
)
5473 *total
= m68hc11_rtx_costs_1 (x
, code
, outer_code
);
5482 /* Worker function for TARGET_ASM_FILE_START. */
5485 m68hc11_file_start (void)
5487 default_file_start ();
5489 fprintf (asm_out_file
, "\t.mode %s\n", TARGET_SHORT
? "mshort" : "mlong");
5493 /* Worker function for TARGET_ASM_CONSTRUCTOR. */
5496 m68hc11_asm_out_constructor (rtx symbol
, int priority
)
5498 default_ctor_section_asm_out_constructor (symbol
, priority
);
5499 fprintf (asm_out_file
, "\t.globl\t__do_global_ctors\n");
5502 /* Worker function for TARGET_ASM_DESTRUCTOR. */
5505 m68hc11_asm_out_destructor (rtx symbol
, int priority
)
5507 default_dtor_section_asm_out_destructor (symbol
, priority
);
5508 fprintf (asm_out_file
, "\t.globl\t__do_global_dtors\n");
5511 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5514 m68hc11_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5515 int incoming ATTRIBUTE_UNUSED
)
5517 return gen_rtx_REG (Pmode
, HARD_D_REGNUM
);
5520 /* Return true if type TYPE should be returned in memory.
5521 Blocks and data types largers than 4 bytes cannot be returned
5522 in the register (D + X = 4). */
5525 m68hc11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5527 if (TYPE_MODE (type
) == BLKmode
)
5529 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5530 return (size
== -1 || size
> 4);
5533 return GET_MODE_SIZE (TYPE_MODE (type
)) > 4;
5536 #include "gt-m68hc11.h"