1 /* Subroutines for code generation on Motorola 68HC11 and 68HC12.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>.
23 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
24 on gcc 2.6.3. I have used it as a starting point for this port.
25 However, this new port is a complete re-write. Its internal
26 design is completely different. The generated code is not
27 compatible with the gcc 2.6.3 port.
29 The gcc 2.6.3 port is available at:
31 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
38 #include "coretypes.h"
45 #include "hard-reg-set.h"
46 #include "insn-config.h"
47 #include "conditions.h"
49 #include "insn-attr.h"
54 #include "diagnostic-core.h"
56 #include "basic-block.h"
61 #include "target-def.h"
64 static void m68hc11_option_override (void);
65 static void emit_move_after_reload (rtx
, rtx
, rtx
);
66 static rtx
simplify_logical (enum machine_mode
, int, rtx
, rtx
*);
67 static void m68hc11_emit_logical (enum machine_mode
, enum rtx_code
, rtx
*);
68 static void m68hc11_reorg (void);
69 static bool m68hc11_legitimate_address_p_1 (enum machine_mode
, rtx
, bool);
70 static bool m68hc11_legitimate_address_p (enum machine_mode
, rtx
, bool);
71 static rtx
m68hc11_expand_compare (enum rtx_code
, rtx
, rtx
);
72 static int must_parenthesize (rtx
);
73 static int m68hc11_address_cost (rtx
, bool);
74 static int m68hc11_shift_cost (enum machine_mode
, rtx
, int);
75 static int m68hc11_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
76 static bool m68hc11_rtx_costs (rtx
, int, int, int *, bool);
77 static tree
m68hc11_handle_fntype_attribute (tree
*, tree
, tree
, int, bool *);
78 static tree
m68hc11_handle_page0_attribute (tree
*, tree
, tree
, int, bool *);
79 static bool m68hc11_class_likely_spilled_p (reg_class_t
);
81 void create_regs_rtx (void);
83 static void asm_print_register (FILE *, int);
84 static void m68hc11_print_operand (FILE *, rtx
, int);
85 static void m68hc11_print_operand_address (FILE *, rtx
);
86 static void m68hc11_output_function_epilogue (FILE *, HOST_WIDE_INT
);
87 static void m68hc11_asm_out_constructor (rtx
, int);
88 static void m68hc11_asm_out_destructor (rtx
, int);
89 static void m68hc11_file_start (void);
90 static void m68hc11_encode_section_info (tree
, rtx
, int);
91 static const char *m68hc11_strip_name_encoding (const char* str
);
92 static unsigned int m68hc11_section_type_flags (tree
, const char*, int);
93 static int autoinc_mode (rtx
);
94 static int m68hc11_make_autoinc_notes (rtx
*, void *);
95 static void m68hc11_init_libfuncs (void);
96 static rtx
m68hc11_struct_value_rtx (tree
, int);
97 static bool m68hc11_return_in_memory (const_tree
, const_tree
);
98 static bool m68hc11_can_eliminate (const int, const int);
99 static void m68hc11_trampoline_init (rtx
, tree
, rtx
);
101 /* Must be set to 1 to produce debug messages. */
104 extern FILE *asm_out_file
;
109 rtx m68hc11_soft_tmp_reg
;
110 static GTY(()) rtx stack_push_word
;
111 static GTY(()) rtx stack_pop_word
;
112 static GTY(()) rtx z_reg
;
113 static GTY(()) rtx z_reg_qi
;
114 static int regs_inited
= 0;
116 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
117 int current_function_interrupt
;
119 /* Set to 1 by expand_prologue() when the function is a trap handler. */
120 int current_function_trap
;
122 /* Set to 1 when the current function is placed in 68HC12 banked
123 memory and must return with rtc. */
124 int current_function_far
;
126 /* Min offset that is valid for the indirect addressing mode. */
127 HOST_WIDE_INT m68hc11_min_offset
= 0;
129 /* Max offset that is valid for the indirect addressing mode. */
130 HOST_WIDE_INT m68hc11_max_offset
= 256;
132 /* The class value for base registers. */
133 enum reg_class m68hc11_base_reg_class
= A_REGS
;
135 /* The class value for index registers. This is NO_REGS for 68HC11. */
136 enum reg_class m68hc11_index_reg_class
= NO_REGS
;
138 enum reg_class m68hc11_tmp_regs_class
= NO_REGS
;
140 /* Tables that tell whether a given hard register is valid for
141 a base or an index register. It is filled at init time depending
142 on the target processor. */
143 unsigned char m68hc11_reg_valid_for_base
[FIRST_PSEUDO_REGISTER
];
144 unsigned char m68hc11_reg_valid_for_index
[FIRST_PSEUDO_REGISTER
];
146 /* A correction offset which is applied to the stack pointer.
147 This is 1 for 68HC11 and 0 for 68HC12. */
148 int m68hc11_sp_correction
;
150 int m68hc11_addr_mode
;
151 int m68hc11_mov_addr_mode
;
154 const struct processor_costs
*m68hc11_cost
;
156 /* Costs for a 68HC11. */
157 static const struct processor_costs m6811_cost
= {
162 /* non-constant shift */
165 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
166 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
167 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
170 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
171 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
172 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
173 COSTS_N_INSNS (2), COSTS_N_INSNS (4),
174 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (10),
175 COSTS_N_INSNS (8), COSTS_N_INSNS (6), COSTS_N_INSNS (4)
180 COSTS_N_INSNS (20 * 4),
182 COSTS_N_INSNS (20 * 16),
191 /* Costs for a 68HC12. */
192 static const struct processor_costs m6812_cost
= {
197 /* non-constant shift */
200 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (2),
201 COSTS_N_INSNS (3), COSTS_N_INSNS (4), COSTS_N_INSNS (3),
202 COSTS_N_INSNS (2), COSTS_N_INSNS (1) },
205 { COSTS_N_INSNS (0), COSTS_N_INSNS (1), COSTS_N_INSNS (4),
206 COSTS_N_INSNS (6), COSTS_N_INSNS (8), COSTS_N_INSNS (6),
207 COSTS_N_INSNS (4), COSTS_N_INSNS (2),
208 COSTS_N_INSNS (2), COSTS_N_INSNS (4), COSTS_N_INSNS (6),
209 COSTS_N_INSNS (8), COSTS_N_INSNS (10), COSTS_N_INSNS (8),
210 COSTS_N_INSNS (6), COSTS_N_INSNS (4)
217 COSTS_N_INSNS (3 * 4),
226 /* M68HC11 specific attributes. */
228 static const struct attribute_spec m68hc11_attribute_table
[] =
230 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
231 { "interrupt", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
232 { "trap", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
233 { "far", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
234 { "near", 0, 0, false, true, true, m68hc11_handle_fntype_attribute
},
235 { "page0", 0, 0, false, false, false, m68hc11_handle_page0_attribute
},
236 { NULL
, 0, 0, false, false, false, NULL
}
239 /* Initialize the GCC target structure. */
240 #undef TARGET_ATTRIBUTE_TABLE
241 #define TARGET_ATTRIBUTE_TABLE m68hc11_attribute_table
243 #undef TARGET_ASM_ALIGNED_HI_OP
244 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
246 #undef TARGET_PRINT_OPERAND
247 #define TARGET_PRINT_OPERAND m68hc11_print_operand
248 #undef TARGET_PRINT_OPERAND_ADDRESS
249 #define TARGET_PRINT_OPERAND_ADDRESS m68hc11_print_operand_address
251 #undef TARGET_ASM_FUNCTION_EPILOGUE
252 #define TARGET_ASM_FUNCTION_EPILOGUE m68hc11_output_function_epilogue
254 #undef TARGET_ASM_FILE_START
255 #define TARGET_ASM_FILE_START m68hc11_file_start
256 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
257 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
259 #undef TARGET_DEFAULT_TARGET_FLAGS
260 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
262 #undef TARGET_ENCODE_SECTION_INFO
263 #define TARGET_ENCODE_SECTION_INFO m68hc11_encode_section_info
265 #undef TARGET_SECTION_TYPE_FLAGS
266 #define TARGET_SECTION_TYPE_FLAGS m68hc11_section_type_flags
268 #undef TARGET_RTX_COSTS
269 #define TARGET_RTX_COSTS m68hc11_rtx_costs
270 #undef TARGET_ADDRESS_COST
271 #define TARGET_ADDRESS_COST m68hc11_address_cost
273 #undef TARGET_MACHINE_DEPENDENT_REORG
274 #define TARGET_MACHINE_DEPENDENT_REORG m68hc11_reorg
276 #undef TARGET_INIT_LIBFUNCS
277 #define TARGET_INIT_LIBFUNCS m68hc11_init_libfuncs
279 #undef TARGET_STRUCT_VALUE_RTX
280 #define TARGET_STRUCT_VALUE_RTX m68hc11_struct_value_rtx
281 #undef TARGET_RETURN_IN_MEMORY
282 #define TARGET_RETURN_IN_MEMORY m68hc11_return_in_memory
283 #undef TARGET_CALLEE_COPIES
284 #define TARGET_CALLEE_COPIES hook_callee_copies_named
286 #undef TARGET_STRIP_NAME_ENCODING
287 #define TARGET_STRIP_NAME_ENCODING m68hc11_strip_name_encoding
289 #undef TARGET_LEGITIMATE_ADDRESS_P
290 #define TARGET_LEGITIMATE_ADDRESS_P m68hc11_legitimate_address_p
292 #undef TARGET_CAN_ELIMINATE
293 #define TARGET_CAN_ELIMINATE m68hc11_can_eliminate
295 #undef TARGET_CLASS_LIKELY_SPILLED_P
296 #define TARGET_CLASS_LIKELY_SPILLED_P m68hc11_class_likely_spilled_p
298 #undef TARGET_TRAMPOLINE_INIT
299 #define TARGET_TRAMPOLINE_INIT m68hc11_trampoline_init
301 #undef TARGET_OPTION_OVERRIDE
302 #define TARGET_OPTION_OVERRIDE m68hc11_option_override
304 struct gcc_target targetm
= TARGET_INITIALIZER
;
307 m68hc11_option_override (void)
309 memset (m68hc11_reg_valid_for_index
, 0,
310 sizeof (m68hc11_reg_valid_for_index
));
311 memset (m68hc11_reg_valid_for_base
, 0, sizeof (m68hc11_reg_valid_for_base
));
313 /* Compilation with -fpic generates a wrong code. */
316 warning (0, "-f%s ignored for 68HC11/68HC12 (not supported)",
317 (flag_pic
> 1) ? "PIC" : "pic");
321 /* Do not enable -fweb because it breaks the 32-bit shift patterns
322 by breaking the match_dup of those patterns. The shift patterns
323 will no longer be recognized after that. */
326 /* Configure for a 68hc11 processor. */
329 target_flags
&= ~(TARGET_AUTO_INC_DEC
| TARGET_MIN_MAX
);
330 m68hc11_cost
= &m6811_cost
;
331 m68hc11_min_offset
= 0;
332 m68hc11_max_offset
= 256;
333 m68hc11_index_reg_class
= NO_REGS
;
334 m68hc11_base_reg_class
= A_REGS
;
335 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
336 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
337 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
338 m68hc11_sp_correction
= 1;
339 m68hc11_tmp_regs_class
= D_REGS
;
340 m68hc11_addr_mode
= ADDR_OFFSET
;
341 m68hc11_mov_addr_mode
= 0;
342 if (m68hc11_soft_reg_count
< 0)
343 m68hc11_soft_reg_count
= 4;
346 /* Configure for a 68hc12 processor. */
349 m68hc11_cost
= &m6812_cost
;
350 m68hc11_min_offset
= -65536;
351 m68hc11_max_offset
= 65536;
352 m68hc11_index_reg_class
= D_REGS
;
353 m68hc11_base_reg_class
= A_OR_SP_REGS
;
354 m68hc11_reg_valid_for_base
[HARD_X_REGNUM
] = 1;
355 m68hc11_reg_valid_for_base
[HARD_Y_REGNUM
] = 1;
356 m68hc11_reg_valid_for_base
[HARD_Z_REGNUM
] = 1;
357 m68hc11_reg_valid_for_base
[HARD_SP_REGNUM
] = 1;
358 m68hc11_reg_valid_for_index
[HARD_D_REGNUM
] = 1;
359 m68hc11_sp_correction
= 0;
360 m68hc11_tmp_regs_class
= TMP_REGS
;
361 m68hc11_addr_mode
= ADDR_INDIRECT
| ADDR_OFFSET
| ADDR_CONST
362 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
363 m68hc11_mov_addr_mode
= ADDR_OFFSET
| ADDR_CONST
364 | (TARGET_AUTO_INC_DEC
? ADDR_INCDEC
: 0);
365 target_flags
|= MASK_NO_DIRECT_MODE
;
366 if (m68hc11_soft_reg_count
< 0)
367 m68hc11_soft_reg_count
= 0;
369 if (TARGET_LONG_CALLS
)
370 current_function_far
= 1;
376 m68hc11_conditional_register_usage (void)
380 if (m68hc11_soft_reg_count
> SOFT_REG_LAST
- SOFT_REG_FIRST
)
381 m68hc11_soft_reg_count
= SOFT_REG_LAST
- SOFT_REG_FIRST
;
383 for (i
= SOFT_REG_FIRST
+ m68hc11_soft_reg_count
; i
< SOFT_REG_LAST
; i
++)
386 call_used_regs
[i
] = 1;
389 /* For 68HC12, the Z register emulation is not necessary when the
390 frame pointer is not used. The frame pointer is eliminated and
391 replaced by the stack register (which is a BASE_REG_CLASS). */
392 if (TARGET_M6812
&& flag_omit_frame_pointer
&& optimize
)
394 fixed_regs
[HARD_Z_REGNUM
] = 1;
399 /* Reload and register operations. */
403 create_regs_rtx (void)
405 /* regs_inited = 1; */
406 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
407 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
408 d_reg
= gen_rtx_REG (HImode
, HARD_D_REGNUM
);
409 m68hc11_soft_tmp_reg
= gen_rtx_REG (HImode
, SOFT_TMP_REGNUM
);
411 stack_push_word
= gen_rtx_MEM (HImode
,
412 gen_rtx_PRE_DEC (HImode
,
413 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
414 stack_pop_word
= gen_rtx_MEM (HImode
,
415 gen_rtx_POST_INC (HImode
,
416 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
420 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
421 - 8-bit values are stored anywhere (except the SP register).
422 - 16-bit values can be stored in any register whose mode is 16
423 - 32-bit values can be stored in D, X registers or in a soft register
424 (except the last one because we need 2 soft registers)
425 - Values whose size is > 32 bit are not stored in real hard
426 registers. They may be stored in soft registers if there are
429 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
431 switch (GET_MODE_SIZE (mode
))
434 return S_REGNO_P (regno
) && m68hc11_soft_reg_count
>= 4;
437 return (X_REGNO_P (regno
)
438 || (S_REGNO_P (regno
) && m68hc11_soft_reg_count
>= 2));
441 return G_REGNO_P (regno
);
444 /* We have to accept a QImode in X or Y registers. Otherwise, the
445 reload pass will fail when some (SUBREG:QI (REG:HI X)) are defined
446 in the insns. Reload fails if the insn rejects the register class 'a'
447 as well as if it accepts it. Patterns that failed were
448 zero_extend_qihi2 and iorqi3. */
450 return G_REGNO_P (regno
) && !SP_REGNO_P (regno
);
458 m68hc11_hard_regno_rename_ok (int reg1
, int reg2
)
460 /* Don't accept renaming to Z register. We will replace it to
461 X,Y or D during machine reorg pass. */
462 if (reg2
== HARD_Z_REGNUM
)
465 /* Don't accept renaming D,X to Y register as the code will be bigger. */
466 if (TARGET_M6811
&& reg2
== HARD_Y_REGNUM
467 && (D_REGNO_P (reg1
) || X_REGNO_P (reg1
)))
474 preferred_reload_class (rtx operand
, enum reg_class rclass
)
476 enum machine_mode mode
;
478 mode
= GET_MODE (operand
);
482 printf ("Preferred reload: (class=%s): ", reg_class_names
[rclass
]);
485 if (rclass
== D_OR_A_OR_S_REGS
&& SP_REG_P (operand
))
486 return m68hc11_base_reg_class
;
488 if (rclass
>= S_REGS
&& (GET_CODE (operand
) == MEM
489 || GET_CODE (operand
) == CONST_INT
))
491 /* S_REGS class must not be used. The movhi template does not
492 work to move a memory to a soft register.
493 Restrict to a hard reg. */
498 case D_OR_A_OR_S_REGS
:
499 rclass
= A_OR_D_REGS
;
504 case D_OR_SP_OR_S_REGS
:
505 rclass
= D_OR_SP_REGS
;
507 case D_OR_Y_OR_S_REGS
:
508 rclass
= D_OR_Y_REGS
;
510 case D_OR_X_OR_S_REGS
:
511 rclass
= D_OR_X_REGS
;
526 else if (rclass
== Y_REGS
&& GET_CODE (operand
) == MEM
)
530 else if (rclass
== A_OR_D_REGS
&& GET_MODE_SIZE (mode
) == 4)
532 rclass
= D_OR_X_REGS
;
534 else if (rclass
>= S_REGS
&& S_REG_P (operand
))
540 case D_OR_A_OR_S_REGS
:
541 rclass
= A_OR_D_REGS
;
546 case D_OR_SP_OR_S_REGS
:
547 rclass
= D_OR_SP_REGS
;
549 case D_OR_Y_OR_S_REGS
:
550 rclass
= D_OR_Y_REGS
;
552 case D_OR_X_OR_S_REGS
:
553 rclass
= D_OR_X_REGS
;
568 else if (rclass
>= S_REGS
)
572 printf ("Class = %s for: ", reg_class_names
[rclass
]);
580 printf (" => class=%s\n", reg_class_names
[rclass
]);
588 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
591 m68hc11_class_likely_spilled_p (reg_class_t rclass
)
614 /* Return 1 if the operand is a valid indexed addressing mode.
615 For 68hc11: n,r with n in [0..255] and r in A_REGS class
616 For 68hc12: n,r no constraint on the constant, r in A_REGS class. */
618 m68hc11_valid_addressing_p (rtx operand
, enum machine_mode mode
, int addr_mode
)
622 switch (GET_CODE (operand
))
625 if ((addr_mode
& ADDR_INDIRECT
) && GET_MODE_SIZE (mode
) <= 2)
626 return m68hc11_valid_addressing_p (XEXP (operand
, 0), mode
,
627 addr_mode
& (ADDR_STRICT
| ADDR_OFFSET
));
634 if (addr_mode
& ADDR_INCDEC
)
635 return m68hc11_valid_addressing_p (XEXP (operand
, 0), mode
,
636 addr_mode
& ADDR_STRICT
);
640 base
= XEXP (operand
, 0);
641 if (GET_CODE (base
) == MEM
)
644 offset
= XEXP (operand
, 1);
645 if (GET_CODE (offset
) == MEM
)
648 /* Indexed addressing mode with 2 registers. */
649 if (GET_CODE (base
) == REG
&& GET_CODE (offset
) == REG
)
651 if (!(addr_mode
& ADDR_INDEXED
))
654 addr_mode
&= ADDR_STRICT
;
655 if (REGNO_OK_FOR_BASE_P2 (REGNO (base
), addr_mode
)
656 && REGNO_OK_FOR_INDEX_P2 (REGNO (offset
), addr_mode
))
659 if (REGNO_OK_FOR_BASE_P2 (REGNO (offset
), addr_mode
)
660 && REGNO_OK_FOR_INDEX_P2 (REGNO (base
), addr_mode
))
666 if (!(addr_mode
& ADDR_OFFSET
))
669 if (GET_CODE (base
) == REG
)
671 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
674 if (!(addr_mode
& ADDR_STRICT
))
677 return REGNO_OK_FOR_BASE_P2 (REGNO (base
), 1);
680 if (GET_CODE (offset
) == REG
)
682 if (!VALID_CONSTANT_OFFSET_P (base
, mode
))
685 if (!(addr_mode
& ADDR_STRICT
))
688 return REGNO_OK_FOR_BASE_P2 (REGNO (offset
), 1);
693 return REGNO_OK_FOR_BASE_P2 (REGNO (operand
), addr_mode
& ADDR_STRICT
);
696 if (addr_mode
& ADDR_CONST
)
697 return VALID_CONSTANT_OFFSET_P (operand
, mode
);
705 /* Returns 1 if the operand fits in a 68HC11 indirect mode or in
706 a 68HC12 1-byte index addressing mode. */
708 m68hc11_small_indexed_indirect_p (rtx operand
, enum machine_mode mode
)
713 if (GET_CODE (operand
) == REG
&& reload_in_progress
714 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
715 && reg_equiv_memory_loc
[REGNO (operand
)])
717 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
718 operand
= eliminate_regs (operand
, VOIDmode
, NULL_RTX
);
721 if (GET_CODE (operand
) != MEM
)
724 operand
= XEXP (operand
, 0);
725 if (CONSTANT_ADDRESS_P (operand
))
728 if (PUSH_POP_ADDRESS_P (operand
))
731 addr_mode
= m68hc11_mov_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
732 if (!m68hc11_valid_addressing_p (operand
, mode
, addr_mode
))
735 if (TARGET_M6812
&& GET_CODE (operand
) == PLUS
736 && (reload_completed
| reload_in_progress
))
738 base
= XEXP (operand
, 0);
739 offset
= XEXP (operand
, 1);
741 /* The offset can be a symbol address and this is too big
742 for the operand constraint. */
743 if (GET_CODE (base
) != CONST_INT
&& GET_CODE (offset
) != CONST_INT
)
746 if (GET_CODE (base
) == CONST_INT
)
749 switch (GET_MODE_SIZE (mode
))
752 if (INTVAL (offset
) < -16 + 6 || INTVAL (offset
) > 15 - 6)
757 if (INTVAL (offset
) < -16 + 2 || INTVAL (offset
) > 15 - 2)
762 if (INTVAL (offset
) < -16 || INTVAL (offset
) > 15)
771 m68hc11_register_indirect_p (rtx operand
, enum machine_mode mode
)
775 if (GET_CODE (operand
) == REG
&& reload_in_progress
776 && REGNO (operand
) >= FIRST_PSEUDO_REGISTER
777 && reg_equiv_memory_loc
[REGNO (operand
)])
779 operand
= reg_equiv_memory_loc
[REGNO (operand
)];
780 operand
= eliminate_regs (operand
, VOIDmode
, NULL_RTX
);
782 if (GET_CODE (operand
) != MEM
)
785 operand
= XEXP (operand
, 0);
786 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
787 return m68hc11_valid_addressing_p (operand
, mode
, addr_mode
);
791 m68hc11_legitimate_address_p_1 (enum machine_mode mode
, rtx operand
,
796 if (CONSTANT_ADDRESS_P (operand
) && TARGET_M6812
)
798 /* Reject the global variables if they are too wide. This forces
799 a load of their address in a register and generates smaller code. */
800 if (GET_MODE_SIZE (mode
) == 8)
805 addr_mode
= m68hc11_addr_mode
| (strict
? ADDR_STRICT
: 0);
806 if (m68hc11_valid_addressing_p (operand
, mode
, addr_mode
))
810 if (PUSH_POP_ADDRESS_P (operand
))
814 if (symbolic_memory_operand (operand
, mode
))
822 m68hc11_legitimate_address_p (enum machine_mode mode
, rtx operand
,
829 printf ("Checking: ");
834 result
= m68hc11_legitimate_address_p_1 (mode
, operand
, strict
);
838 printf (" -> %s\n", result
== 0 ? "NO" : "YES");
845 printf ("go_if_legitimate%s, ret 0: %d:",
846 (strict
? "_strict" : ""), mode
);
856 m68hc11_reload_operands (rtx operands
[])
858 enum machine_mode mode
;
860 if (regs_inited
== 0)
863 mode
= GET_MODE (operands
[1]);
865 /* Input reload of indirect addressing (MEM (PLUS (REG) (CONST))). */
866 if (A_REG_P (operands
[0]) && memory_reload_operand (operands
[1], mode
))
868 rtx big_offset
= XEXP (XEXP (operands
[1], 0), 1);
869 rtx base
= XEXP (XEXP (operands
[1], 0), 0);
871 if (GET_CODE (base
) != REG
)
878 /* If the offset is out of range, we have to compute the address
879 with a separate add instruction. We try to do this with an 8-bit
880 add on the A register. This is possible only if the lowest part
881 of the offset (i.e., big_offset % 256) is a valid constant offset
882 with respect to the mode. If it's not, we have to generate a
883 16-bit add on the D register. From:
885 (SET (REG X (MEM (PLUS (REG X) (CONST_INT 1000)))))
889 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
890 (SET (REG A) (PLUS (REG A) (CONST_INT 1000 / 256)))
891 [(SET (REG D) (REG X)) (SET (REG X) (REG D))]
892 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256)))
894 (SET (REG X) (PLUS (REG X) (CONST_INT 1000 / 256 * 256)))
895 (SET (REG X) (MEM (PLUS (REG X) (CONST_INT 1000 % 256))))
898 if (!VALID_CONSTANT_OFFSET_P (big_offset
, mode
))
901 rtx reg
= operands
[0];
903 int val
= INTVAL (big_offset
);
906 /* We use the 'operands[0]' as a scratch register to compute the
907 address. Make sure 'base' is in that register. */
908 if (!rtx_equal_p (base
, operands
[0]))
910 emit_move_insn (reg
, base
);
920 vh
= (val
>> 8) & 0x0FF;
924 /* Create the lowest part offset that still remains to be added.
925 If it's not a valid offset, do a 16-bit add. */
926 offset
= GEN_INT (vl
);
927 if (!VALID_CONSTANT_OFFSET_P (offset
, mode
))
929 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
930 gen_rtx_PLUS (HImode
, reg
, big_offset
)));
935 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
936 gen_rtx_PLUS (HImode
, reg
,
937 GEN_INT (vh
<< 8))));
939 emit_move_insn (operands
[0],
940 gen_rtx_MEM (GET_MODE (operands
[1]),
941 gen_rtx_PLUS (Pmode
, reg
, offset
)));
946 /* Use the normal gen_movhi pattern. */
951 m68hc11_emit_libcall (const char *name
, enum rtx_code code
,
952 enum machine_mode dmode
, enum machine_mode smode
,
953 int noperands
, rtx
*operands
)
961 libcall
= gen_rtx_SYMBOL_REF (Pmode
, name
);
965 ret
= emit_library_call_value (libcall
, NULL_RTX
, LCT_CONST
,
966 dmode
, 1, operands
[1], smode
);
967 equiv
= gen_rtx_fmt_e (code
, dmode
, operands
[1]);
971 ret
= emit_library_call_value (libcall
, NULL_RTX
,
973 operands
[1], smode
, operands
[2],
975 equiv
= gen_rtx_fmt_ee (code
, dmode
, operands
[1], operands
[2]);
982 insns
= get_insns ();
984 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
987 /* Returns true if X is a PRE/POST increment decrement
988 (same as auto_inc_p() in rtlanal.c but do not take into
989 account the stack). */
991 m68hc11_auto_inc_p (rtx x
)
993 return GET_CODE (x
) == PRE_DEC
994 || GET_CODE (x
) == POST_INC
995 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_INC
;
999 /* Predicates for machine description. */
1002 memory_reload_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1004 return GET_CODE (operand
) == MEM
1005 && GET_CODE (XEXP (operand
, 0)) == PLUS
1006 && ((GET_CODE (XEXP (XEXP (operand
, 0), 0)) == REG
1007 && GET_CODE (XEXP (XEXP (operand
, 0), 1)) == CONST_INT
)
1008 || (GET_CODE (XEXP (XEXP (operand
, 0), 1)) == REG
1009 && GET_CODE (XEXP (XEXP (operand
, 0), 0)) == CONST_INT
));
1013 m68hc11_symbolic_p (rtx operand
, enum machine_mode mode
)
1015 if (GET_CODE (operand
) == MEM
)
1017 rtx op
= XEXP (operand
, 0);
1019 if (symbolic_memory_operand (op
, mode
))
1026 m68hc11_indirect_p (rtx operand
, enum machine_mode mode
)
1028 if (GET_CODE (operand
) == MEM
&& GET_MODE (operand
) == mode
)
1030 rtx op
= XEXP (operand
, 0);
1033 if (m68hc11_page0_symbol_p (op
))
1036 if (symbolic_memory_operand (op
, mode
))
1037 return TARGET_M6812
;
1039 if (reload_in_progress
)
1042 operand
= XEXP (operand
, 0);
1043 addr_mode
= m68hc11_addr_mode
| (reload_completed
? ADDR_STRICT
: 0);
1044 return m68hc11_valid_addressing_p (operand
, mode
, addr_mode
);
1050 memory_indexed_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1052 if (GET_CODE (operand
) != MEM
)
1055 operand
= XEXP (operand
, 0);
1056 if (GET_CODE (operand
) == PLUS
)
1058 if (GET_CODE (XEXP (operand
, 0)) == REG
)
1059 operand
= XEXP (operand
, 0);
1060 else if (GET_CODE (XEXP (operand
, 1)) == REG
)
1061 operand
= XEXP (operand
, 1);
1063 return GET_CODE (operand
) == REG
1064 && (REGNO (operand
) >= FIRST_PSEUDO_REGISTER
1065 || A_REGNO_P (REGNO (operand
)));
1069 push_pop_operand_p (rtx operand
)
1071 if (GET_CODE (operand
) != MEM
)
1075 operand
= XEXP (operand
, 0);
1076 return PUSH_POP_ADDRESS_P (operand
);
1079 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1080 reference and a constant. */
1083 symbolic_memory_operand (rtx op
, enum machine_mode mode
)
1085 switch (GET_CODE (op
))
1093 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1094 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1095 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1097 /* ??? This clause seems to be irrelevant. */
1099 return GET_MODE (op
) == mode
;
1102 return symbolic_memory_operand (XEXP (op
, 0), mode
)
1103 && symbolic_memory_operand (XEXP (op
, 1), mode
);
1110 /* Emit the code to build the trampoline used to call a nested function.
1114 ldy #&CXT movw #&CXT,*_.d1
1115 sty *_.d1 jmp FNADDR
1120 m68hc11_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
1122 const char *static_chain_reg
= reg_names
[STATIC_CHAIN_REGNUM
];
1123 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1127 if (*static_chain_reg
== '*')
1131 mem
= adjust_address (m_tramp
, HImode
, 0);
1132 emit_move_insn (mem
, GEN_INT (0x18ce));
1133 mem
= adjust_address (m_tramp
, HImode
, 2);
1134 emit_move_insn (mem
, cxt
);
1135 mem
= adjust_address (m_tramp
, HImode
, 4);
1136 emit_move_insn (mem
, GEN_INT (0x18df));
1137 mem
= adjust_address (m_tramp
, QImode
, 6);
1138 emit_move_insn (mem
,
1139 gen_rtx_CONST (QImode
,
1140 gen_rtx_SYMBOL_REF (Pmode
,
1141 static_chain_reg
)));
1142 mem
= adjust_address (m_tramp
, QImode
, 7);
1143 emit_move_insn (mem
, GEN_INT (0x7e));
1144 mem
= adjust_address (m_tramp
, HImode
, 8);
1145 emit_move_insn (mem
, fnaddr
);
1149 mem
= adjust_address (m_tramp
, HImode
, 0);
1150 emit_move_insn (mem
, GEN_INT (0x1803));
1151 mem
= adjust_address (m_tramp
, HImode
, 2);
1152 emit_move_insn (mem
, cxt
);
1153 mem
= adjust_address (m_tramp
, HImode
, 4);
1154 emit_move_insn (mem
,
1155 gen_rtx_CONST (HImode
,
1156 gen_rtx_SYMBOL_REF (Pmode
,
1157 static_chain_reg
)));
1158 mem
= adjust_address (m_tramp
, QImode
, 6);
1159 emit_move_insn (mem
, GEN_INT (0x06));
1160 mem
= adjust_address (m_tramp
, HImode
, 7);
1161 emit_move_insn (mem
, fnaddr
);
1165 /* Declaration of types. */
1167 /* Handle an "tiny_data" attribute; arguments as in
1168 struct attribute_spec.handler. */
1170 m68hc11_handle_page0_attribute (tree
*node
, tree name
,
1171 tree args ATTRIBUTE_UNUSED
,
1172 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1176 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
1178 DECL_SECTION_NAME (decl
) = build_string (6, ".page0");
1182 warning (OPT_Wattributes
, "%qE attribute ignored",
1184 *no_add_attrs
= true;
1190 /* Keep track of the symbol which has a `trap' attribute and which uses
1191 the `swi' calling convention. Since there is only one trap, we only
1192 record one such symbol. If there are several, a warning is reported. */
1193 static rtx trap_handler_symbol
= 0;
1195 /* Handle an attribute requiring a FUNCTION_TYPE, FIELD_DECL or TYPE_DECL;
1196 arguments as in struct attribute_spec.handler. */
1198 m68hc11_handle_fntype_attribute (tree
*node
, tree name
,
1199 tree args ATTRIBUTE_UNUSED
,
1200 int flags ATTRIBUTE_UNUSED
,
1203 if (TREE_CODE (*node
) != FUNCTION_TYPE
1204 && TREE_CODE (*node
) != METHOD_TYPE
1205 && TREE_CODE (*node
) != FIELD_DECL
1206 && TREE_CODE (*node
) != TYPE_DECL
)
1208 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1210 *no_add_attrs
= true;
1215 /* Undo the effects of the above. */
1218 m68hc11_strip_name_encoding (const char *str
)
1220 return str
+ (*str
== '*' || *str
== '@' || *str
== '&');
1224 m68hc11_encode_label (tree decl
)
1226 const char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1227 int len
= strlen (str
);
1228 char *newstr
= XALLOCAVEC (char, len
+ 2);
1231 strcpy (&newstr
[1], str
);
1233 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = ggc_alloc_string (newstr
, len
+ 1);
1236 /* Return 1 if this is a symbol in page0 */
1238 m68hc11_page0_symbol_p (rtx x
)
1240 switch (GET_CODE (x
))
1243 return XSTR (x
, 0) != 0 && XSTR (x
, 0)[0] == '@';
1246 return m68hc11_page0_symbol_p (XEXP (x
, 0));
1249 if (!m68hc11_page0_symbol_p (XEXP (x
, 0)))
1252 return GET_CODE (XEXP (x
, 1)) == CONST_INT
1253 && INTVAL (XEXP (x
, 1)) < 256
1254 && INTVAL (XEXP (x
, 1)) >= 0;
1261 /* We want to recognize trap handlers so that we handle calls to traps
1262 in a special manner (by issuing the trap). This information is stored
1263 in SYMBOL_REF_FLAG. */
1266 m68hc11_encode_section_info (tree decl
, rtx rtl
, int first ATTRIBUTE_UNUSED
)
1272 if (TREE_CODE (decl
) == VAR_DECL
)
1274 if (lookup_attribute ("page0", DECL_ATTRIBUTES (decl
)) != 0)
1275 m68hc11_encode_label (decl
);
1279 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1282 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
1285 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1287 else if (lookup_attribute ("near", func_attr
) == NULL_TREE
)
1288 is_far
= TARGET_LONG_CALLS
!= 0;
1290 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1291 if (trap_handler
&& is_far
)
1293 warning (OPT_Wattributes
, "%<trap%> and %<far%> attributes are "
1294 "not compatible, ignoring %<far%>");
1299 if (trap_handler_symbol
!= 0)
1300 warning (OPT_Wattributes
, "%<trap%> attribute is already used");
1302 trap_handler_symbol
= XEXP (rtl
, 0);
1304 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = is_far
;
1308 m68hc11_section_type_flags (tree decl
, const char *name
, int reloc
)
1310 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
1312 if (strncmp (name
, ".eeprom", 7) == 0)
1314 flags
|= SECTION_WRITE
| SECTION_CODE
| SECTION_OVERRIDE
;
1321 m68hc11_is_far_symbol (rtx sym
)
1323 if (GET_CODE (sym
) == MEM
)
1324 sym
= XEXP (sym
, 0);
1326 return SYMBOL_REF_FLAG (sym
);
1330 m68hc11_is_trap_symbol (rtx sym
)
1332 if (GET_CODE (sym
) == MEM
)
1333 sym
= XEXP (sym
, 0);
1335 return trap_handler_symbol
!= 0 && rtx_equal_p (trap_handler_symbol
, sym
);
1339 /* Argument support functions. */
1341 /* Given FROM and TO register numbers, say whether this elimination is
1342 allowed. Frame pointer elimination is automatically handled.
1344 All other eliminations are valid. */
1347 m68hc11_can_eliminate (const int from
, const int to
)
1349 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1350 ? ! frame_pointer_needed
1354 /* Define the offset between two registers, one to be eliminated, and the
1355 other its replacement, at the start of a routine. */
1357 m68hc11_initial_elimination_offset (int from
, int to
)
1364 /* For a trap handler, we must take into account the registers which
1365 are pushed on the stack during the trap (except the PC). */
1366 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1367 current_function_interrupt
= lookup_attribute ("interrupt",
1368 func_attr
) != NULL_TREE
;
1369 trap_handler
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1371 if (lookup_attribute ("far", func_attr
) != 0)
1372 current_function_far
= 1;
1373 else if (lookup_attribute ("near", func_attr
) != 0)
1374 current_function_far
= 0;
1376 current_function_far
= (TARGET_LONG_CALLS
!= 0
1377 && !current_function_interrupt
1380 if (trap_handler
&& from
== ARG_POINTER_REGNUM
)
1383 /* For a function using 'call/rtc' we must take into account the
1384 page register which is pushed in the call. */
1385 else if (current_function_far
&& from
== ARG_POINTER_REGNUM
)
1390 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1392 /* 2 is for the saved frame.
1393 1 is for the 'sts' correction when creating the frame. */
1394 return get_frame_size () + 2 + m68hc11_sp_correction
+ size
;
1397 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1399 return m68hc11_sp_correction
;
1402 /* Push any 2 byte pseudo hard registers that we need to save. */
1403 for (regno
= SOFT_REG_FIRST
; regno
< SOFT_REG_LAST
; regno
++)
1405 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1411 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1413 return get_frame_size () + size
;
1416 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_SP_REGNUM
)
1423 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1424 for a call to a function whose data type is FNTYPE.
1425 For a library call, FNTYPE is 0. */
1428 m68hc11_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
)
1432 z_replacement_completed
= 0;
1436 /* For a library call, we must find out the type of the return value.
1437 When the return value is bigger than 4 bytes, it is returned in
1438 memory. In that case, the first argument of the library call is a
1439 pointer to the memory location. Because the first argument is passed in
1440 register D, we have to identify this, so that the first function
1441 parameter is not passed in D either. */
1447 if (libname
== 0 || GET_CODE (libname
) != SYMBOL_REF
)
1450 /* If the library ends in 'di' or in 'df', we assume it's
1451 returning some DImode or some DFmode which are 64-bit wide. */
1452 name
= XSTR (libname
, 0);
1453 len
= strlen (name
);
1455 && ((name
[len
- 2] == 'd'
1456 && (name
[len
- 1] == 'f' || name
[len
- 1] == 'i'))
1457 || (name
[len
- 3] == 'd'
1458 && (name
[len
- 2] == 'i' || name
[len
- 2] == 'f'))))
1460 /* We are in. Mark the first parameter register as already used. */
1467 ret_type
= TREE_TYPE (fntype
);
1469 if (ret_type
&& aggregate_value_p (ret_type
, fntype
))
1476 /* Update the data in CUM to advance over an argument
1477 of mode MODE and data type TYPE.
1478 (TYPE is null for libcalls where that information may not be available.) */
1481 m68hc11_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1482 tree type
, int named ATTRIBUTE_UNUSED
)
1484 if (mode
!= BLKmode
)
1486 if (cum
->words
== 0 && GET_MODE_SIZE (mode
) == 4)
1489 cum
->words
= GET_MODE_SIZE (mode
);
1493 cum
->words
+= GET_MODE_SIZE (mode
);
1494 if (cum
->words
<= HARD_REG_SIZE
)
1500 cum
->words
+= int_size_in_bytes (type
);
1505 /* Define where to put the arguments to a function.
1506 Value is zero to push the argument on the stack,
1507 or a hard register in which to store the argument.
1509 MODE is the argument's machine mode.
1510 TYPE is the data type of the argument (as a tree).
1511 This is null for libcalls where that information may
1513 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1514 the preceding args and about the function being called.
1515 NAMED is nonzero if this argument is a named parameter
1516 (otherwise it is an extra parameter matching an ellipsis). */
1519 m68hc11_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1520 tree type ATTRIBUTE_UNUSED
, int named ATTRIBUTE_UNUSED
)
1522 if (cum
->words
!= 0)
1527 if (mode
!= BLKmode
)
1529 if (GET_MODE_SIZE (mode
) == 2 * HARD_REG_SIZE
)
1530 return gen_rtx_REG (mode
, HARD_X_REGNUM
);
1532 if (GET_MODE_SIZE (mode
) > HARD_REG_SIZE
)
1536 return gen_rtx_REG (mode
, HARD_D_REGNUM
);
1541 /* If defined, a C expression which determines whether, and in which direction,
1542 to pad out an argument with extra space. The value should be of type
1543 `enum direction': either `upward' to pad above the argument,
1544 `downward' to pad below, or `none' to inhibit padding.
1546 Structures are stored left shifted in their argument slot. */
1548 m68hc11_function_arg_padding (enum machine_mode mode
, const_tree type
)
1550 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
1553 /* Fall back to the default. */
1554 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
1558 /* Function prologue and epilogue. */
1560 /* Emit a move after the reload pass has completed. This is used to
1561 emit the prologue and epilogue. */
1563 emit_move_after_reload (rtx to
, rtx from
, rtx scratch
)
1567 if (TARGET_M6812
|| H_REG_P (to
) || H_REG_P (from
))
1569 insn
= emit_move_insn (to
, from
);
1573 emit_move_insn (scratch
, from
);
1574 insn
= emit_move_insn (to
, scratch
);
1577 /* Put a REG_INC note to tell the flow analysis that the instruction
1579 if (IS_STACK_PUSH (to
))
1580 add_reg_note (insn
, REG_INC
, XEXP (XEXP (to
, 0), 0));
1581 else if (IS_STACK_POP (from
))
1582 add_reg_note (insn
, REG_INC
, XEXP (XEXP (from
, 0), 0));
1584 /* For 68HC11, put a REG_INC note on `sts _.frame' to prevent the cse-reg
1585 to think that sp == _.frame and later replace a x = sp with x = _.frame.
1586 The problem is that we are lying to gcc and use `txs' for x = sp
1587 (which is not really true because txs is really x = sp + 1). */
1588 else if (TARGET_M6811
&& SP_REG_P (from
))
1589 add_reg_note (insn
, REG_INC
, from
);
1593 m68hc11_total_frame_size (void)
1598 size
= get_frame_size ();
1599 if (current_function_interrupt
)
1601 size
+= 3 * HARD_REG_SIZE
;
1603 if (frame_pointer_needed
)
1604 size
+= HARD_REG_SIZE
;
1606 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1607 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1608 size
+= HARD_REG_SIZE
;
1614 m68hc11_output_function_epilogue (FILE *out ATTRIBUTE_UNUSED
,
1615 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1617 /* We catch the function epilogue generation to have a chance
1618 to clear the z_replacement_completed flag. */
1619 z_replacement_completed
= 0;
1623 expand_prologue (void)
1630 gcc_assert (reload_completed
== 1);
1632 size
= get_frame_size ();
1636 /* Generate specific prologue for interrupt handlers. */
1637 func_attr
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1638 current_function_interrupt
= lookup_attribute ("interrupt",
1639 func_attr
) != NULL_TREE
;
1640 current_function_trap
= lookup_attribute ("trap", func_attr
) != NULL_TREE
;
1641 if (lookup_attribute ("far", func_attr
) != NULL_TREE
)
1642 current_function_far
= 1;
1643 else if (lookup_attribute ("near", func_attr
) != NULL_TREE
)
1644 current_function_far
= 0;
1646 current_function_far
= (TARGET_LONG_CALLS
!= 0
1647 && !current_function_interrupt
1648 && !current_function_trap
);
1650 /* Get the scratch register to build the frame and push registers.
1651 If the first argument is a 32-bit quantity, the D+X registers
1652 are used. Use Y to compute the frame. Otherwise, X is cheaper.
1653 For 68HC12, this scratch register is not used. */
1654 if (crtl
->args
.info
.nregs
== 2)
1659 /* Save current stack frame. */
1660 if (frame_pointer_needed
)
1661 emit_move_after_reload (stack_push_word
, hard_frame_pointer_rtx
, scratch
);
1663 /* For an interrupt handler, we must preserve _.tmp, _.z and _.xy.
1664 Other soft registers in page0 need not to be saved because they
1665 will be restored by C functions. For a trap handler, we don't
1666 need to preserve these registers because this is a synchronous call. */
1667 if (current_function_interrupt
)
1669 emit_move_after_reload (stack_push_word
, m68hc11_soft_tmp_reg
, scratch
);
1670 emit_move_after_reload (stack_push_word
,
1671 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
), scratch
);
1672 emit_move_after_reload (stack_push_word
,
1673 gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1677 /* Allocate local variables. */
1678 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1680 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1681 stack_pointer_rtx
, GEN_INT (-size
)));
1683 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1687 insn
= gen_rtx_PARALLEL
1690 gen_rtx_SET (VOIDmode
,
1692 gen_rtx_PLUS (HImode
,
1695 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1702 /* Allocate by pushing scratch values. */
1703 for (i
= 2; i
<= size
; i
+= 2)
1704 emit_move_after_reload (stack_push_word
, ix_reg
, 0);
1707 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1708 stack_pointer_rtx
, constm1_rtx
));
1711 /* Create the frame pointer. */
1712 if (frame_pointer_needed
)
1713 emit_move_after_reload (hard_frame_pointer_rtx
,
1714 stack_pointer_rtx
, scratch
);
1716 /* Push any 2 byte pseudo hard registers that we need to save. */
1717 for (regno
= SOFT_REG_FIRST
; regno
<= SOFT_REG_LAST
; regno
++)
1719 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1721 emit_move_after_reload (stack_push_word
,
1722 gen_rtx_REG (HImode
, regno
), scratch
);
1728 expand_epilogue (void)
1735 gcc_assert (reload_completed
== 1);
1737 size
= get_frame_size ();
1739 /* If we are returning a value in two registers, we have to preserve the
1740 X register and use the Y register to restore the stack and the saved
1741 registers. Otherwise, use X because it's faster (and smaller). */
1742 if (crtl
->return_rtx
== 0)
1744 else if (GET_CODE (crtl
->return_rtx
) == MEM
)
1745 return_size
= HARD_REG_SIZE
;
1747 return_size
= GET_MODE_SIZE (GET_MODE (crtl
->return_rtx
));
1749 if (return_size
> HARD_REG_SIZE
&& return_size
<= 2 * HARD_REG_SIZE
)
1754 /* Pop any 2 byte pseudo hard registers that we saved. */
1755 for (regno
= SOFT_REG_LAST
; regno
>= SOFT_REG_FIRST
; regno
--)
1757 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1759 emit_move_after_reload (gen_rtx_REG (HImode
, regno
),
1760 stack_pop_word
, scratch
);
1764 /* de-allocate auto variables */
1765 if (TARGET_M6812
&& (size
> 4 || size
== 3))
1767 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1768 stack_pointer_rtx
, GEN_INT (size
)));
1770 else if ((!optimize_size
&& size
> 8) || (optimize_size
&& size
> 10))
1774 insn
= gen_rtx_PARALLEL
1777 gen_rtx_SET (VOIDmode
,
1779 gen_rtx_PLUS (HImode
,
1782 gen_rtx_CLOBBER (VOIDmode
, scratch
)));
1789 for (i
= 2; i
<= size
; i
+= 2)
1790 emit_move_after_reload (scratch
, stack_pop_word
, scratch
);
1792 emit_insn (gen_addhi3 (stack_pointer_rtx
,
1793 stack_pointer_rtx
, const1_rtx
));
1796 /* For an interrupt handler, restore ZTMP, ZREG and XYREG. */
1797 if (current_function_interrupt
)
1799 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
),
1800 stack_pop_word
, scratch
);
1801 emit_move_after_reload (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
1802 stack_pop_word
, scratch
);
1803 emit_move_after_reload (m68hc11_soft_tmp_reg
, stack_pop_word
, scratch
);
1806 /* Restore previous frame pointer. */
1807 if (frame_pointer_needed
)
1808 emit_move_after_reload (hard_frame_pointer_rtx
, stack_pop_word
, scratch
);
1810 /* If the trap handler returns some value, copy the value
1811 in D, X onto the stack so that the rti will pop the return value
1813 else if (current_function_trap
&& return_size
!= 0)
1815 rtx addr_reg
= stack_pointer_rtx
;
1819 emit_move_after_reload (scratch
, stack_pointer_rtx
, 0);
1822 emit_move_after_reload (gen_rtx_MEM (HImode
,
1823 gen_rtx_PLUS (HImode
, addr_reg
,
1824 const1_rtx
)), d_reg
, 0);
1825 if (return_size
> HARD_REG_SIZE
)
1826 emit_move_after_reload (gen_rtx_MEM (HImode
,
1827 gen_rtx_PLUS (HImode
, addr_reg
,
1828 GEN_INT (3))), ix_reg
, 0);
1831 emit_jump_insn (gen_return ());
1835 /* Low and High part extraction for 68HC11. These routines are
1836 similar to gen_lowpart and gen_highpart but they have been
1837 fixed to work for constants and 68HC11 specific registers. */
1840 m68hc11_gen_lowpart (enum machine_mode mode
, rtx x
)
1842 /* We assume that the low part of an auto-inc mode is the same with
1843 the mode changed and that the caller split the larger mode in the
1845 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1847 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1850 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1851 floating-point constant. A CONST_DOUBLE is used whenever the
1852 constant requires more than one word in order to be adequately
1854 if (GET_CODE (x
) == CONST_DOUBLE
)
1858 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1862 if (GET_MODE (x
) == SFmode
)
1864 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1865 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[0]);
1871 split_double (x
, &first
, &second
);
1875 return GEN_INT (l
[0]);
1877 return gen_int_mode (l
[0], HImode
);
1881 l
[0] = CONST_DOUBLE_LOW (x
);
1886 return GEN_INT (l
[0]);
1888 gcc_assert (GET_MODE (x
) == SFmode
);
1889 return gen_int_mode (l
[0], HImode
);
1895 if (mode
== QImode
&& D_REG_P (x
))
1896 return gen_rtx_REG (mode
, HARD_B_REGNUM
);
1898 /* gen_lowpart crashes when it is called with a SUBREG. */
1899 if (GET_CODE (x
) == SUBREG
&& SUBREG_BYTE (x
) != 0)
1904 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 4);
1906 return gen_rtx_SUBREG (mode
, SUBREG_REG (x
), SUBREG_BYTE (x
) + 2);
1911 x
= gen_lowpart (mode
, x
);
1913 /* Return a different rtx to avoid to share it in several insns
1914 (when used by a split pattern). Sharing addresses within
1915 a MEM breaks the Z register replacement (and reloading). */
1916 if (GET_CODE (x
) == MEM
)
1922 m68hc11_gen_highpart (enum machine_mode mode
, rtx x
)
1924 /* We assume that the high part of an auto-inc mode is the same with
1925 the mode changed and that the caller split the larger mode in the
1927 if (GET_CODE (x
) == MEM
&& m68hc11_auto_inc_p (XEXP (x
, 0)))
1929 return gen_rtx_MEM (mode
, XEXP (x
, 0));
1932 /* Note that a CONST_DOUBLE rtx could represent either an integer or a
1933 floating-point constant. A CONST_DOUBLE is used whenever the
1934 constant requires more than one word in order to be adequately
1936 if (GET_CODE (x
) == CONST_DOUBLE
)
1940 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1944 if (GET_MODE (x
) == SFmode
)
1946 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1947 REAL_VALUE_TO_TARGET_SINGLE (r
, l
[1]);
1953 split_double (x
, &first
, &second
);
1957 return GEN_INT (l
[1]);
1959 return gen_int_mode ((l
[1] >> 16), HImode
);
1963 l
[1] = CONST_DOUBLE_HIGH (x
);
1969 return GEN_INT (l
[1]);
1971 gcc_assert (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
);
1972 return gen_int_mode ((l
[0] >> 16), HImode
);
1977 if (GET_CODE (x
) == CONST_INT
)
1979 HOST_WIDE_INT val
= INTVAL (x
);
1983 return gen_int_mode (val
>> 8, QImode
);
1985 else if (mode
== HImode
)
1987 return gen_int_mode (val
>> 16, HImode
);
1989 else if (mode
== SImode
)
1991 return gen_int_mode (val
>> 32, SImode
);
1994 if (mode
== QImode
&& D_REG_P (x
))
1995 return gen_rtx_REG (mode
, HARD_A_REGNUM
);
1997 /* There is no way in GCC to represent the upper part of a word register.
1998 To obtain the 8-bit upper part of a soft register, we change the
1999 reg into a mem rtx. This is possible because they are physically
2000 located in memory. There is no offset because we are big-endian. */
2001 if (mode
== QImode
&& S_REG_P (x
))
2005 /* Avoid the '*' for direct addressing mode when this
2006 addressing mode is disabled. */
2007 pos
= TARGET_NO_DIRECT_MODE
? 1 : 0;
2008 return gen_rtx_MEM (QImode
,
2009 gen_rtx_SYMBOL_REF (Pmode
,
2010 ®_names
[REGNO (x
)][pos
]));
2013 /* gen_highpart crashes when it is called with a SUBREG. */
2014 switch (GET_CODE (x
))
2017 return gen_rtx_SUBREG (mode
, XEXP (x
, 0), XINT (x
, 1));
2019 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2020 return gen_rtx_REG (mode
, REGNO (x
));
2022 return gen_rtx_SUBREG (mode
, x
, 0);
2024 x
= change_address (x
, mode
, 0);
2026 /* Return a different rtx to avoid to share it in several insns
2027 (when used by a split pattern). Sharing addresses within
2028 a MEM breaks the Z register replacement (and reloading). */
2029 if (GET_CODE (x
) == MEM
)
2039 /* Obscure register manipulation. */
2041 /* Finds backward in the instructions to see if register 'reg' is
2042 dead. This is used when generating code to see if we can use 'reg'
2043 as a scratch register. This allows us to choose a better generation
2044 of code when we know that some register dies or can be clobbered. */
2047 dead_register_here (rtx x
, rtx reg
)
2053 x_reg
= gen_rtx_REG (SImode
, HARD_X_REGNUM
);
2057 for (p
= PREV_INSN (x
); p
&& GET_CODE (p
) != CODE_LABEL
; p
= PREV_INSN (p
))
2064 if (GET_CODE (body
) == CALL_INSN
)
2066 if (GET_CODE (body
) == JUMP_INSN
)
2069 if (GET_CODE (body
) == SET
)
2071 rtx dst
= XEXP (body
, 0);
2073 if (GET_CODE (dst
) == REG
&& REGNO (dst
) == REGNO (reg
))
2075 if (x_reg
&& rtx_equal_p (dst
, x_reg
))
2078 if (find_regno_note (p
, REG_DEAD
, REGNO (reg
)))
2081 else if (reg_mentioned_p (reg
, p
)
2082 || (x_reg
&& reg_mentioned_p (x_reg
, p
)))
2086 /* Scan forward to see if the register is set in some insns and never
2088 for (p
= x
/*NEXT_INSN (x) */ ; p
; p
= NEXT_INSN (p
))
2092 if (GET_CODE (p
) == CODE_LABEL
2093 || GET_CODE (p
) == JUMP_INSN
2094 || GET_CODE (p
) == CALL_INSN
|| GET_CODE (p
) == BARRIER
)
2097 if (GET_CODE (p
) != INSN
)
2101 if (GET_CODE (body
) == SET
)
2103 rtx src
= XEXP (body
, 1);
2104 rtx dst
= XEXP (body
, 0);
2106 if (GET_CODE (dst
) == REG
2107 && REGNO (dst
) == REGNO (reg
) && !reg_mentioned_p (reg
, src
))
2111 /* Register is used (may be in source or in dest). */
2112 if (reg_mentioned_p (reg
, p
)
2113 || (x_reg
!= 0 && GET_MODE (p
) == SImode
2114 && reg_mentioned_p (x_reg
, p
)))
2117 return p
== 0 ? 1 : 0;
2121 /* Code generation operations called from machine description file. */
2123 /* Print the name of register 'regno' in the assembly file. */
2125 asm_print_register (FILE *file
, int regno
)
2127 const char *name
= reg_names
[regno
];
2129 if (TARGET_NO_DIRECT_MODE
&& name
[0] == '*')
2132 fprintf (file
, "%s", name
);
2135 /* A C compound statement to output to stdio stream STREAM the
2136 assembler syntax for an instruction operand X. X is an RTL
2139 CODE is a value that can be used to specify one of several ways
2140 of printing the operand. It is used when identical operands
2141 must be printed differently depending on the context. CODE
2142 comes from the `%' specification that was used to request
2143 printing of the operand. If the specification was just `%DIGIT'
2144 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2145 is the ASCII code for LTR.
2147 If X is a register, this macro should print the register's name.
2148 The names can be found in an array `reg_names' whose type is
2149 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2151 When the machine description has a specification `%PUNCT' (a `%'
2152 followed by a punctuation character), this macro is called with
2153 a null pointer for X and the punctuation character for CODE.
2155 The M68HC11 specific codes are:
2157 'b' for the low part of the operand.
2158 'h' for the high part of the operand
2159 The 'b' or 'h' modifiers have no effect if the operand has
2160 the QImode and is not a S_REG_P (soft register). If the
2161 operand is a hard register, these two modifiers have no effect.
2162 't' generate the temporary scratch register. The operand is
2164 'T' generate the low-part temporary scratch register. The operand is
2168 m68hc11_print_operand (FILE *file
, rtx op
, int letter
)
2172 asm_print_register (file
, SOFT_TMP_REGNUM
);
2175 else if (letter
== 'T')
2177 asm_print_register (file
, SOFT_TMP_REGNUM
);
2178 fprintf (file
, "+1");
2181 else if (letter
== '#')
2183 asm_fprintf (file
, "%I");
2186 if (GET_CODE (op
) == REG
)
2188 if (letter
== 'b' && S_REG_P (op
))
2190 asm_print_register (file
, REGNO (op
));
2191 fprintf (file
, "+1");
2193 else if (letter
== 'b' && D_REG_P (op
))
2195 asm_print_register (file
, HARD_B_REGNUM
);
2199 asm_print_register (file
, REGNO (op
));
2204 if (GET_CODE (op
) == SYMBOL_REF
&& (letter
== 'b' || letter
== 'h'))
2207 asm_fprintf (file
, "%I%%lo(");
2209 asm_fprintf (file
, "%I%%hi(");
2211 output_addr_const (file
, op
);
2212 fprintf (file
, ")");
2216 /* Get the low or high part of the operand when 'b' or 'h' modifiers
2217 are specified. If we already have a QImode, there is nothing to do. */
2218 if (GET_MODE (op
) == HImode
|| GET_MODE (op
) == VOIDmode
)
2222 op
= m68hc11_gen_lowpart (QImode
, op
);
2224 else if (letter
== 'h')
2226 op
= m68hc11_gen_highpart (QImode
, op
);
2230 if (GET_CODE (op
) == MEM
)
2232 rtx base
= XEXP (op
, 0);
2233 switch (GET_CODE (base
))
2236 gcc_assert (TARGET_M6812
);
2237 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (op
)));
2238 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2242 gcc_assert (TARGET_M6812
);
2243 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2244 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2245 fprintf (file
, "-");
2249 gcc_assert (TARGET_M6812
);
2250 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (op
)));
2251 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2252 fprintf (file
, "+");
2256 gcc_assert (TARGET_M6812
);
2257 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (op
)));
2258 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2262 gcc_assert (TARGET_M6812
);
2263 fprintf (file
, "[");
2264 m68hc11_print_operand_address (file
, XEXP (base
, 0));
2265 fprintf (file
, "]");
2269 if (m68hc11_page0_symbol_p (base
))
2270 fprintf (file
, "*");
2272 output_address (base
);
2276 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2281 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2282 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2283 asm_fprintf (file
, "%I0x%lx", l
);
2285 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2289 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (op
),
2290 sizeof (dstr
), 0, 1);
2291 asm_fprintf (file
, "%I0r%s", dstr
);
2295 int need_parenthesize
= 0;
2298 asm_fprintf (file
, "%I");
2300 need_parenthesize
= must_parenthesize (op
);
2302 if (need_parenthesize
)
2303 fprintf (file
, "(");
2305 output_addr_const (file
, op
);
2306 if (need_parenthesize
)
2307 fprintf (file
, ")");
2311 /* Returns true if the operand 'op' must be printed with parenthesis
2312 around it. This must be done only if there is a symbol whose name
2313 is a processor register. */
2315 must_parenthesize (rtx op
)
2319 switch (GET_CODE (op
))
2322 name
= XSTR (op
, 0);
2323 /* Avoid a conflict between symbol name and a possible
2325 return (strcasecmp (name
, "a") == 0
2326 || strcasecmp (name
, "b") == 0
2327 || strcasecmp (name
, "d") == 0
2328 || strcasecmp (name
, "x") == 0
2329 || strcasecmp (name
, "y") == 0
2330 || strcasecmp (name
, "ix") == 0
2331 || strcasecmp (name
, "iy") == 0
2332 || strcasecmp (name
, "pc") == 0
2333 || strcasecmp (name
, "sp") == 0
2334 || strcasecmp (name
, "ccr") == 0) ? 1 : 0;
2338 return must_parenthesize (XEXP (op
, 0))
2339 || must_parenthesize (XEXP (op
, 1));
2345 return must_parenthesize (XEXP (op
, 0));
2356 /* A C compound statement to output to stdio stream STREAM the
2357 assembler syntax for an instruction operand that is a memory
2358 reference whose address is ADDR. ADDR is an RTL expression. */
2361 m68hc11_print_operand_address (FILE *file
, rtx addr
)
2365 int need_parenthesis
= 0;
2367 switch (GET_CODE (addr
))
2370 gcc_assert (REG_P (addr
) && REG_OK_FOR_BASE_STRICT_P (addr
));
2372 fprintf (file
, "0,");
2373 asm_print_register (file
, REGNO (addr
));
2377 base
= XEXP (addr
, 0);
2378 switch (GET_CODE (base
))
2381 gcc_assert (TARGET_M6812
);
2382 fprintf (file
, "%u,-", GET_MODE_SIZE (GET_MODE (addr
)));
2383 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2387 gcc_assert (TARGET_M6812
);
2388 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2389 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2390 fprintf (file
, "-");
2394 gcc_assert (TARGET_M6812
);
2395 fprintf (file
, "%u,", GET_MODE_SIZE (GET_MODE (addr
)));
2396 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2397 fprintf (file
, "+");
2401 gcc_assert (TARGET_M6812
);
2402 fprintf (file
, "%u,+", GET_MODE_SIZE (GET_MODE (addr
)));
2403 asm_print_register (file
, REGNO (XEXP (base
, 0)));
2407 need_parenthesis
= must_parenthesize (base
);
2408 if (need_parenthesis
)
2409 fprintf (file
, "(");
2411 output_addr_const (file
, base
);
2412 if (need_parenthesis
)
2413 fprintf (file
, ")");
2419 base
= XEXP (addr
, 0);
2420 offset
= XEXP (addr
, 1);
2421 if (!G_REG_P (base
) && G_REG_P (offset
))
2423 base
= XEXP (addr
, 1);
2424 offset
= XEXP (addr
, 0);
2426 if (CONSTANT_ADDRESS_P (base
))
2428 need_parenthesis
= must_parenthesize (addr
);
2430 gcc_assert (CONSTANT_ADDRESS_P (offset
));
2431 if (need_parenthesis
)
2432 fprintf (file
, "(");
2434 output_addr_const (file
, base
);
2435 fprintf (file
, "+");
2436 output_addr_const (file
, offset
);
2437 if (need_parenthesis
)
2438 fprintf (file
, ")");
2442 gcc_assert (REG_P (base
) && REG_OK_FOR_BASE_STRICT_P (base
));
2445 gcc_assert (TARGET_M6812
);
2446 asm_print_register (file
, REGNO (offset
));
2447 fprintf (file
, ",");
2448 asm_print_register (file
, REGNO (base
));
2452 need_parenthesis
= must_parenthesize (offset
);
2453 if (need_parenthesis
)
2454 fprintf (file
, "(");
2456 output_addr_const (file
, offset
);
2457 if (need_parenthesis
)
2458 fprintf (file
, ")");
2459 fprintf (file
, ",");
2460 asm_print_register (file
, REGNO (base
));
2466 if (GET_CODE (addr
) == CONST_INT
2467 && INTVAL (addr
) < 0x8000 && INTVAL (addr
) >= -0x8000)
2469 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2473 need_parenthesis
= must_parenthesize (addr
);
2474 if (need_parenthesis
)
2475 fprintf (file
, "(");
2477 output_addr_const (file
, addr
);
2478 if (need_parenthesis
)
2479 fprintf (file
, ")");
2486 /* Splitting of some instructions. */
2489 m68hc11_expand_compare (enum rtx_code code
, rtx op0
, rtx op1
)
2493 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_FLOAT
);
2494 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
,
2495 gen_rtx_COMPARE (VOIDmode
, op0
, op1
)));
2496 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
2502 m68hc11_expand_compare_and_branch (enum rtx_code code
, rtx op0
, rtx op1
,
2507 switch (GET_MODE (op0
))
2511 tmp
= m68hc11_expand_compare (code
, op0
, op1
);
2512 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2513 gen_rtx_LABEL_REF (VOIDmode
, label
),
2515 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
2519 /* SCz: from i386.c */
2522 /* Don't expand the comparison early, so that we get better code
2523 when jump or whoever decides to reverse the comparison. */
2528 code
= m68hc11_prepare_fp_compare_args (code
, &m68hc11_compare_op0
,
2529 &m68hc11_compare_op1
);
2531 tmp
= gen_rtx_fmt_ee (code
, m68hc11_fp_compare_mode (code
),
2532 m68hc11_compare_op0
, m68hc11_compare_op1
);
2533 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
2534 gen_rtx_LABEL_REF (VOIDmode
, label
),
2536 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
2538 use_fcomi
= ix86_use_fcomi_compare (code
);
2539 vec
= rtvec_alloc (3 + !use_fcomi
);
2540 RTVEC_ELT (vec
, 0) = tmp
;
2542 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
2544 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
2547 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
2549 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
2555 /* Expand SImode branch into multiple compare+branch. */
2557 rtx lo
[2], hi
[2], label2
;
2558 enum rtx_code code1
, code2
, code3
;
2560 if (CONSTANT_P (op0
) && !CONSTANT_P (op1
))
2565 code
= swap_condition (code
);
2567 lo
[0] = m68hc11_gen_lowpart (HImode
, op0
);
2568 lo
[1] = m68hc11_gen_lowpart (HImode
, op1
);
2569 hi
[0] = m68hc11_gen_highpart (HImode
, op0
);
2570 hi
[1] = m68hc11_gen_highpart (HImode
, op1
);
2572 /* Otherwise, if we are doing less-than, op1 is a constant and the
2573 low word is zero, then we can just examine the high word. */
2575 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
2576 && (code
== LT
|| code
== LTU
))
2578 return m68hc11_expand_compare_and_branch (code
, hi
[0], hi
[1],
2582 /* Otherwise, we need two or three jumps. */
2584 label2
= gen_label_rtx ();
2587 code2
= swap_condition (code
);
2588 code3
= unsigned_condition (code
);
2629 * if (hi(a) < hi(b)) goto true;
2630 * if (hi(a) > hi(b)) goto false;
2631 * if (lo(a) < lo(b)) goto true;
2634 if (code1
!= UNKNOWN
)
2635 m68hc11_expand_compare_and_branch (code1
, hi
[0], hi
[1], label
);
2636 if (code2
!= UNKNOWN
)
2637 m68hc11_expand_compare_and_branch (code2
, hi
[0], hi
[1], label2
);
2639 m68hc11_expand_compare_and_branch (code3
, lo
[0], lo
[1], label
);
2641 if (code2
!= UNKNOWN
)
2642 emit_label (label2
);
2652 /* Return the increment/decrement mode of a MEM if it is such.
2653 Return CONST if it is anything else. */
2655 autoinc_mode (rtx x
)
2657 if (GET_CODE (x
) != MEM
)
2661 if (GET_CODE (x
) == PRE_INC
2662 || GET_CODE (x
) == PRE_DEC
2663 || GET_CODE (x
) == POST_INC
2664 || GET_CODE (x
) == POST_DEC
)
2665 return GET_CODE (x
);
2671 m68hc11_make_autoinc_notes (rtx
*x
, void *data
)
2675 switch (GET_CODE (*x
))
2682 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_INC
, XEXP (*x
, 0),
2691 /* Split a DI, SI or HI move into several smaller move operations.
2692 The scratch register 'scratch' is used as a temporary to load
2693 store intermediate values. It must be a hard register. */
2695 m68hc11_split_move (rtx to
, rtx from
, rtx scratch
)
2697 rtx low_to
, low_from
;
2698 rtx high_to
, high_from
;
2700 enum machine_mode mode
;
2702 int autoinc_from
= autoinc_mode (from
);
2703 int autoinc_to
= autoinc_mode (to
);
2705 mode
= GET_MODE (to
);
2707 /* If the TO and FROM contain autoinc modes that are not compatible
2708 together (one pop and the other a push), we must change one to
2709 an offsetable operand and generate an appropriate add at the end. */
2710 if (TARGET_M6812
&& GET_MODE_SIZE (mode
) > 2)
2715 /* The source uses an autoinc mode which is not compatible with
2716 a split (this would result in a word swap). */
2717 if (autoinc_from
== PRE_INC
|| autoinc_from
== POST_DEC
)
2719 code
= GET_CODE (XEXP (from
, 0));
2720 reg
= XEXP (XEXP (from
, 0), 0);
2721 offset
= GET_MODE_SIZE (GET_MODE (from
));
2722 if (code
== POST_DEC
)
2725 if (code
== PRE_INC
)
2726 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2728 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2729 if (code
== POST_DEC
)
2730 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2734 /* Likewise for destination. */
2735 if (autoinc_to
== PRE_INC
|| autoinc_to
== POST_DEC
)
2737 code
= GET_CODE (XEXP (to
, 0));
2738 reg
= XEXP (XEXP (to
, 0), 0);
2739 offset
= GET_MODE_SIZE (GET_MODE (to
));
2740 if (code
== POST_DEC
)
2743 if (code
== PRE_INC
)
2744 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2746 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2747 if (code
== POST_DEC
)
2748 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2752 /* The source and destination auto increment modes must be compatible
2753 with each other: same direction. */
2754 if ((autoinc_to
!= autoinc_from
2755 && autoinc_to
!= CONST
&& autoinc_from
!= CONST
)
2756 /* The destination address register must not be used within
2757 the source operand because the source address would change
2758 while doing the copy. */
2759 || (autoinc_to
!= CONST
2760 && reg_mentioned_p (XEXP (XEXP (to
, 0), 0), from
)
2761 && !IS_STACK_PUSH (to
)))
2763 /* Must change the destination. */
2764 code
= GET_CODE (XEXP (to
, 0));
2765 reg
= XEXP (XEXP (to
, 0), 0);
2766 offset
= GET_MODE_SIZE (GET_MODE (to
));
2767 if (code
== PRE_DEC
|| code
== POST_DEC
)
2770 if (code
== PRE_DEC
|| code
== PRE_INC
)
2771 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2772 m68hc11_split_move (gen_rtx_MEM (GET_MODE (to
), reg
), from
, scratch
);
2773 if (code
== POST_DEC
|| code
== POST_INC
)
2774 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2779 /* Likewise, the source address register must not be used within
2780 the destination operand. */
2781 if (autoinc_from
!= CONST
2782 && reg_mentioned_p (XEXP (XEXP (from
, 0), 0), to
)
2783 && !IS_STACK_PUSH (to
))
2785 /* Must change the source. */
2786 code
= GET_CODE (XEXP (from
, 0));
2787 reg
= XEXP (XEXP (from
, 0), 0);
2788 offset
= GET_MODE_SIZE (GET_MODE (from
));
2789 if (code
== PRE_DEC
|| code
== POST_DEC
)
2792 if (code
== PRE_DEC
|| code
== PRE_INC
)
2793 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2794 m68hc11_split_move (to
, gen_rtx_MEM (GET_MODE (from
), reg
), scratch
);
2795 if (code
== POST_DEC
|| code
== POST_INC
)
2796 emit_insn (gen_addhi3 (reg
, reg
, GEN_INT (offset
)));
2802 if (GET_MODE_SIZE (mode
) == 8)
2804 else if (GET_MODE_SIZE (mode
) == 4)
2810 && IS_STACK_PUSH (to
)
2811 && reg_mentioned_p (gen_rtx_REG (HImode
, HARD_SP_REGNUM
), from
))
2817 else if (mode
== HImode
)
2825 low_to
= m68hc11_gen_lowpart (mode
, to
);
2826 high_to
= m68hc11_gen_highpart (mode
, to
);
2828 low_from
= m68hc11_gen_lowpart (mode
, from
);
2829 high_from
= m68hc11_gen_highpart (mode
, from
);
2833 high_from
= adjust_address (high_from
, mode
, offset
);
2834 low_from
= high_from
;
2837 /* When copying with a POST_INC mode, we must copy the
2838 high part and then the low part to guarantee a correct
2841 && GET_MODE_SIZE (mode
) >= 2
2842 && autoinc_from
!= autoinc_to
2843 && (autoinc_from
== POST_INC
|| autoinc_to
== POST_INC
))
2852 low_from
= high_from
;
2857 m68hc11_split_move (low_to
, low_from
, scratch
);
2858 m68hc11_split_move (high_to
, high_from
, scratch
);
2860 else if (H_REG_P (to
) || H_REG_P (from
)
2861 || (low_from
== const0_rtx
2862 && high_from
== const0_rtx
2863 && ! push_operand (to
, GET_MODE (to
))
2864 && ! H_REG_P (scratch
))
2866 && (!m68hc11_register_indirect_p (from
, GET_MODE (from
))
2867 || m68hc11_small_indexed_indirect_p (from
,
2869 && (!m68hc11_register_indirect_p (to
, GET_MODE (to
))
2870 || m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
)))))
2872 insn
= emit_move_insn (low_to
, low_from
);
2873 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2875 insn
= emit_move_insn (high_to
, high_from
);
2876 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2880 insn
= emit_move_insn (scratch
, low_from
);
2881 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2882 insn
= emit_move_insn (low_to
, scratch
);
2883 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2885 insn
= emit_move_insn (scratch
, high_from
);
2886 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2887 insn
= emit_move_insn (high_to
, scratch
);
2888 for_each_rtx (&PATTERN (insn
), m68hc11_make_autoinc_notes
, insn
);
2893 simplify_logical (enum machine_mode mode
, int code
, rtx operand
, rtx
*result
)
2899 if (GET_CODE (operand
) != CONST_INT
)
2907 val
= INTVAL (operand
);
2911 if ((val
& mask
) == 0)
2913 if ((val
& mask
) == mask
)
2914 *result
= constm1_rtx
;
2918 if ((val
& mask
) == 0)
2919 *result
= const0_rtx
;
2920 if ((val
& mask
) == mask
)
2925 if ((val
& mask
) == 0)
2933 m68hc11_emit_logical (enum machine_mode mode
, enum rtx_code code
, rtx
*operands
)
2938 need_copy
= (rtx_equal_p (operands
[0], operands
[1])
2939 || rtx_equal_p (operands
[0], operands
[2])) ? 0 : 1;
2941 operands
[1] = simplify_logical (mode
, code
, operands
[1], &result
);
2942 operands
[2] = simplify_logical (mode
, code
, operands
[2], &result
);
2944 if (result
&& GET_CODE (result
) == CONST_INT
)
2946 if (!H_REG_P (operands
[0]) && operands
[3]
2947 && (INTVAL (result
) != 0 || IS_STACK_PUSH (operands
[0])))
2949 emit_move_insn (operands
[3], result
);
2950 emit_move_insn (operands
[0], operands
[3]);
2954 emit_move_insn (operands
[0], result
);
2957 else if (operands
[1] != 0 && operands
[2] != 0)
2961 if (!H_REG_P (operands
[0]) && operands
[3])
2963 emit_move_insn (operands
[3], operands
[1]);
2964 emit_insn (gen_rtx_SET (mode
,
2966 gen_rtx_fmt_ee (code
, mode
,
2967 operands
[3], operands
[2])));
2968 insn
= emit_move_insn (operands
[0], operands
[3]);
2972 insn
= emit_insn (gen_rtx_SET (mode
,
2974 gen_rtx_fmt_ee (code
, mode
,
2980 /* The logical operation is similar to a copy. */
2985 if (GET_CODE (operands
[1]) == CONST_INT
)
2990 if (!H_REG_P (operands
[0]) && !H_REG_P (src
))
2992 emit_move_insn (operands
[3], src
);
2993 emit_move_insn (operands
[0], operands
[3]);
2997 emit_move_insn (operands
[0], src
);
3003 m68hc11_split_logical (enum machine_mode mode
, enum rtx_code code
,
3009 low
[0] = m68hc11_gen_lowpart (mode
, operands
[0]);
3010 low
[1] = m68hc11_gen_lowpart (mode
, operands
[1]);
3011 low
[2] = m68hc11_gen_lowpart (mode
, operands
[2]);
3013 high
[0] = m68hc11_gen_highpart (mode
, operands
[0]);
3014 high
[1] = m68hc11_gen_highpart (mode
, operands
[1]);
3015 high
[2] = m68hc11_gen_highpart (mode
, operands
[2]);
3017 low
[3] = operands
[3];
3018 high
[3] = operands
[3];
3021 m68hc11_split_logical (HImode
, code
, low
);
3022 m68hc11_split_logical (HImode
, code
, high
);
3026 m68hc11_emit_logical (mode
, code
, low
);
3027 m68hc11_emit_logical (mode
, code
, high
);
3031 /* Code generation. */
3034 m68hc11_output_swap (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
3036 /* We have to be careful with the cc_status. An address register swap
3037 is generated for some comparison. The comparison is made with D
3038 but the branch really uses the address register. See the split
3039 pattern for compare. The xgdx/xgdy preserve the flags but after
3040 the exchange, the flags will reflect to the value of X and not D.
3041 Tell this by setting the cc_status according to the cc_prev_status. */
3042 if (X_REG_P (operands
[1]) || X_REG_P (operands
[0]))
3044 if (cc_prev_status
.value1
!= 0
3045 && (D_REG_P (cc_prev_status
.value1
)
3046 || X_REG_P (cc_prev_status
.value1
)))
3048 cc_status
= cc_prev_status
;
3049 if (D_REG_P (cc_status
.value1
))
3050 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3053 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3059 output_asm_insn ("xgdx", operands
);
3063 if (cc_prev_status
.value1
!= 0
3064 && (D_REG_P (cc_prev_status
.value1
)
3065 || Y_REG_P (cc_prev_status
.value1
)))
3067 cc_status
= cc_prev_status
;
3068 if (D_REG_P (cc_status
.value1
))
3069 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3072 cc_status
.value1
= gen_rtx_REG (GET_MODE (cc_status
.value1
),
3078 output_asm_insn ("xgdy", operands
);
3082 /* Returns 1 if the next insn after 'insn' is a test of the register 'reg'.
3083 This is used to decide whether a move that set flags should be used
3086 next_insn_test_reg (rtx insn
, rtx reg
)
3090 insn
= next_nonnote_insn (insn
);
3091 if (GET_CODE (insn
) != INSN
)
3094 body
= PATTERN (insn
);
3095 if (sets_cc0_p (body
) != 1)
3098 if (rtx_equal_p (XEXP (body
, 1), reg
) == 0)
3104 /* Generate the code to move a 16-bit operand into another one. */
3107 m68hc11_gen_movhi (rtx insn
, rtx
*operands
)
3111 /* Move a register or memory to the same location.
3112 This is possible because such insn can appear
3113 in a non-optimizing mode. */
3114 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3116 cc_status
= cc_prev_status
;
3122 rtx from
= operands
[1];
3123 rtx to
= operands
[0];
3125 if (IS_STACK_PUSH (to
) && H_REG_P (from
))
3127 cc_status
= cc_prev_status
;
3128 switch (REGNO (from
))
3133 output_asm_insn ("psh%1", operands
);
3135 case HARD_SP_REGNUM
:
3136 output_asm_insn ("sts\t2,-sp", operands
);
3143 if (IS_STACK_POP (from
) && H_REG_P (to
))
3145 cc_status
= cc_prev_status
;
3151 output_asm_insn ("pul%0", operands
);
3158 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3160 m68hc11_notice_keep_cc (operands
[0]);
3161 output_asm_insn ("tfr\t%1,%0", operands
);
3163 else if (H_REG_P (operands
[0]))
3165 if (SP_REG_P (operands
[0]))
3166 output_asm_insn ("lds\t%1", operands
);
3168 output_asm_insn ("ld%0\t%1", operands
);
3170 else if (H_REG_P (operands
[1]))
3172 if (SP_REG_P (operands
[1]))
3173 output_asm_insn ("sts\t%0", operands
);
3175 output_asm_insn ("st%1\t%0", operands
);
3178 /* The 68hc12 does not support (MEM:HI (MEM:HI)) with the movw
3179 instruction. We have to use a scratch register as temporary location.
3180 Trying to use a specific pattern or constrain failed. */
3181 else if (GET_CODE (to
) == MEM
&& GET_CODE (XEXP (to
, 0)) == MEM
)
3188 if (dead_register_here (insn
, d_reg
))
3190 else if (dead_register_here (insn
, ix_reg
))
3192 else if (dead_register_here (insn
, iy_reg
))
3198 output_asm_insn ("psh%3", ops
);
3203 output_asm_insn ("ld%1\t%2", ops
);
3204 output_asm_insn ("st%1\t%0", ops
);
3206 output_asm_insn ("pul%3", ops
);
3209 /* Use movw for non-null constants or when we are clearing
3210 a volatile memory reference. However, this is possible
3211 only if the memory reference has a small offset or is an
3212 absolute address. */
3213 else if (GET_CODE (from
) == CONST_INT
3214 && INTVAL (from
) == 0
3215 && (MEM_VOLATILE_P (to
) == 0
3216 || m68hc11_small_indexed_indirect_p (to
, HImode
) == 0))
3218 output_asm_insn ("clr\t%h0", operands
);
3219 output_asm_insn ("clr\t%b0", operands
);
3223 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3224 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3225 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3226 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3232 ops
[0] = operands
[2];
3235 m68hc11_gen_movhi (insn
, ops
);
3237 ops
[1] = operands
[2];
3238 m68hc11_gen_movhi (insn
, ops
);
3243 /* !!!! SCz wrong here. */
3244 fatal_insn ("move insn not handled", insn
);
3249 m68hc11_notice_keep_cc (operands
[0]);
3250 output_asm_insn ("movw\t%1,%0", operands
);
3256 if (IS_STACK_POP (operands
[1]) && H_REG_P (operands
[0]))
3258 cc_status
= cc_prev_status
;
3259 switch (REGNO (operands
[0]))
3263 output_asm_insn ("pul%0", operands
);
3266 output_asm_insn ("pula", operands
);
3267 output_asm_insn ("pulb", operands
);
3274 /* Some moves to a hard register are special. Not all of them
3275 are really supported and we have to use a temporary
3276 location to provide them (either the stack of a temp var). */
3277 if (H_REG_P (operands
[0]))
3279 switch (REGNO (operands
[0]))
3282 if (X_REG_P (operands
[1]))
3284 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3286 m68hc11_output_swap (insn
, operands
);
3288 else if (next_insn_test_reg (insn
, operands
[0]))
3290 output_asm_insn ("stx\t%t0\n\tldd\t%t0", operands
);
3294 m68hc11_notice_keep_cc (operands
[0]);
3295 output_asm_insn ("pshx\n\tpula\n\tpulb", operands
);
3298 else if (Y_REG_P (operands
[1]))
3300 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3302 m68hc11_output_swap (insn
, operands
);
3306 /* %t means *ZTMP scratch register. */
3307 output_asm_insn ("sty\t%t1", operands
);
3308 output_asm_insn ("ldd\t%t1", operands
);
3311 else if (SP_REG_P (operands
[1]))
3316 if (optimize
== 0 || dead_register_here (insn
, ix_reg
) == 0)
3317 output_asm_insn ("xgdx", operands
);
3318 output_asm_insn ("tsx", operands
);
3319 output_asm_insn ("xgdx", operands
);
3321 else if (IS_STACK_POP (operands
[1]))
3323 output_asm_insn ("pula\n\tpulb", operands
);
3325 else if (GET_CODE (operands
[1]) == CONST_INT
3326 && INTVAL (operands
[1]) == 0)
3328 output_asm_insn ("clra\n\tclrb", operands
);
3332 output_asm_insn ("ldd\t%1", operands
);
3337 if (D_REG_P (operands
[1]))
3339 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3341 m68hc11_output_swap (insn
, operands
);
3343 else if (next_insn_test_reg (insn
, operands
[0]))
3345 output_asm_insn ("std\t%t0\n\tldx\t%t0", operands
);
3349 m68hc11_notice_keep_cc (operands
[0]);
3350 output_asm_insn ("pshb", operands
);
3351 output_asm_insn ("psha", operands
);
3352 output_asm_insn ("pulx", operands
);
3355 else if (Y_REG_P (operands
[1]))
3357 /* When both D and Y are dead, use the sequence xgdy, xgdx
3358 to move Y into X. The D and Y registers are modified. */
3359 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
)
3360 && dead_register_here (insn
, d_reg
))
3362 output_asm_insn ("xgdy", operands
);
3363 output_asm_insn ("xgdx", operands
);
3366 else if (!optimize_size
)
3368 output_asm_insn ("sty\t%t1", operands
);
3369 output_asm_insn ("ldx\t%t1", operands
);
3374 output_asm_insn ("pshy", operands
);
3375 output_asm_insn ("pulx", operands
);
3378 else if (SP_REG_P (operands
[1]))
3380 /* tsx, tsy preserve the flags */
3381 cc_status
= cc_prev_status
;
3382 output_asm_insn ("tsx", operands
);
3386 output_asm_insn ("ldx\t%1", operands
);
3391 if (D_REG_P (operands
[1]))
3393 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3395 m68hc11_output_swap (insn
, operands
);
3399 output_asm_insn ("std\t%t1", operands
);
3400 output_asm_insn ("ldy\t%t1", operands
);
3403 else if (X_REG_P (operands
[1]))
3405 /* When both D and X are dead, use the sequence xgdx, xgdy
3406 to move X into Y. The D and X registers are modified. */
3407 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
)
3408 && dead_register_here (insn
, d_reg
))
3410 output_asm_insn ("xgdx", operands
);
3411 output_asm_insn ("xgdy", operands
);
3414 else if (!optimize_size
)
3416 output_asm_insn ("stx\t%t1", operands
);
3417 output_asm_insn ("ldy\t%t1", operands
);
3422 output_asm_insn ("pshx", operands
);
3423 output_asm_insn ("puly", operands
);
3426 else if (SP_REG_P (operands
[1]))
3428 /* tsx, tsy preserve the flags */
3429 cc_status
= cc_prev_status
;
3430 output_asm_insn ("tsy", operands
);
3434 output_asm_insn ("ldy\t%1", operands
);
3438 case HARD_SP_REGNUM
:
3439 if (D_REG_P (operands
[1]))
3441 m68hc11_notice_keep_cc (operands
[0]);
3442 output_asm_insn ("xgdx", operands
);
3443 output_asm_insn ("txs", operands
);
3444 output_asm_insn ("xgdx", operands
);
3446 else if (X_REG_P (operands
[1]))
3448 /* tys, txs preserve the flags */
3449 cc_status
= cc_prev_status
;
3450 output_asm_insn ("txs", operands
);
3452 else if (Y_REG_P (operands
[1]))
3454 /* tys, txs preserve the flags */
3455 cc_status
= cc_prev_status
;
3456 output_asm_insn ("tys", operands
);
3460 /* lds sets the flags but the des does not. */
3462 output_asm_insn ("lds\t%1", operands
);
3463 output_asm_insn ("des", operands
);
3468 fatal_insn ("invalid register in the move instruction", insn
);
3473 if (SP_REG_P (operands
[1]) && REG_P (operands
[0])
3474 && REGNO (operands
[0]) == HARD_FRAME_POINTER_REGNUM
)
3476 output_asm_insn ("sts\t%0", operands
);
3480 if (IS_STACK_PUSH (operands
[0]) && H_REG_P (operands
[1]))
3482 cc_status
= cc_prev_status
;
3483 switch (REGNO (operands
[1]))
3487 output_asm_insn ("psh%1", operands
);
3490 output_asm_insn ("pshb", operands
);
3491 output_asm_insn ("psha", operands
);
3499 /* Operand 1 must be a hard register. */
3500 if (!H_REG_P (operands
[1]))
3502 fatal_insn ("invalid operand in the instruction", insn
);
3505 reg
= REGNO (operands
[1]);
3509 output_asm_insn ("std\t%0", operands
);
3513 output_asm_insn ("stx\t%0", operands
);
3517 output_asm_insn ("sty\t%0", operands
);
3520 case HARD_SP_REGNUM
:
3524 if (REG_P (operands
[0]) && REGNO (operands
[0]) == SOFT_TMP_REGNUM
)
3526 output_asm_insn ("pshx", operands
);
3527 output_asm_insn ("tsx", operands
);
3528 output_asm_insn ("inx", operands
);
3529 output_asm_insn ("inx", operands
);
3530 output_asm_insn ("stx\t%0", operands
);
3531 output_asm_insn ("pulx", operands
);
3534 else if (reg_mentioned_p (ix_reg
, operands
[0]))
3536 output_asm_insn ("sty\t%t0", operands
);
3537 output_asm_insn ("tsy", operands
);
3538 output_asm_insn ("sty\t%0", operands
);
3539 output_asm_insn ("ldy\t%t0", operands
);
3543 output_asm_insn ("stx\t%t0", operands
);
3544 output_asm_insn ("tsx", operands
);
3545 output_asm_insn ("stx\t%0", operands
);
3546 output_asm_insn ("ldx\t%t0", operands
);
3552 fatal_insn ("invalid register in the move instruction", insn
);
3558 m68hc11_gen_movqi (rtx insn
, rtx
*operands
)
3560 /* Move a register or memory to the same location.
3561 This is possible because such insn can appear
3562 in a non-optimizing mode. */
3563 if (operands
[0] == operands
[1] || rtx_equal_p (operands
[0], operands
[1]))
3565 cc_status
= cc_prev_status
;
3572 if (H_REG_P (operands
[0]) && H_REG_P (operands
[1]))
3574 m68hc11_notice_keep_cc (operands
[0]);
3575 output_asm_insn ("tfr\t%1,%0", operands
);
3577 else if (H_REG_P (operands
[0]))
3579 if (IS_STACK_POP (operands
[1]))
3580 output_asm_insn ("pul%b0", operands
);
3581 else if (Q_REG_P (operands
[0]))
3582 output_asm_insn ("lda%0\t%b1", operands
);
3583 else if (D_REG_P (operands
[0]))
3584 output_asm_insn ("ldab\t%b1", operands
);
3588 else if (H_REG_P (operands
[1]))
3590 if (Q_REG_P (operands
[1]))
3591 output_asm_insn ("sta%1\t%b0", operands
);
3592 else if (D_REG_P (operands
[1]))
3593 output_asm_insn ("stab\t%b0", operands
);
3599 rtx from
= operands
[1];
3600 rtx to
= operands
[0];
3602 if ((m68hc11_register_indirect_p (from
, GET_MODE (from
))
3603 && !m68hc11_small_indexed_indirect_p (from
, GET_MODE (from
)))
3604 || (m68hc11_register_indirect_p (to
, GET_MODE (to
))
3605 && !m68hc11_small_indexed_indirect_p (to
, GET_MODE (to
))))
3611 ops
[0] = operands
[2];
3614 m68hc11_gen_movqi (insn
, ops
);
3616 ops
[1] = operands
[2];
3617 m68hc11_gen_movqi (insn
, ops
);
3621 /* !!!! SCz wrong here. */
3622 fatal_insn ("move insn not handled", insn
);
3627 if (GET_CODE (from
) == CONST_INT
&& INTVAL (from
) == 0)
3629 output_asm_insn ("clr\t%b0", operands
);
3633 m68hc11_notice_keep_cc (operands
[0]);
3634 output_asm_insn ("movb\t%b1,%b0", operands
);
3642 if (H_REG_P (operands
[0]))
3644 switch (REGNO (operands
[0]))
3648 if (X_REG_P (operands
[1]))
3650 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_X_REGNUM
))
3652 m68hc11_output_swap (insn
, operands
);
3656 output_asm_insn ("stx\t%t1", operands
);
3657 output_asm_insn ("ldab\t%T0", operands
);
3660 else if (Y_REG_P (operands
[1]))
3662 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_Y_REGNUM
))
3664 m68hc11_output_swap (insn
, operands
);
3668 output_asm_insn ("sty\t%t1", operands
);
3669 output_asm_insn ("ldab\t%T0", operands
);
3672 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3673 && !DA_REG_P (operands
[1]))
3675 output_asm_insn ("ldab\t%b1", operands
);
3677 else if (DA_REG_P (operands
[1]))
3679 output_asm_insn ("tab", operands
);
3683 cc_status
= cc_prev_status
;
3689 if (X_REG_P (operands
[1]))
3691 output_asm_insn ("stx\t%t1", operands
);
3692 output_asm_insn ("ldaa\t%T0", operands
);
3694 else if (Y_REG_P (operands
[1]))
3696 output_asm_insn ("sty\t%t1", operands
);
3697 output_asm_insn ("ldaa\t%T0", operands
);
3699 else if (!DB_REG_P (operands
[1]) && !D_REG_P (operands
[1])
3700 && !DA_REG_P (operands
[1]))
3702 output_asm_insn ("ldaa\t%b1", operands
);
3704 else if (!DA_REG_P (operands
[1]))
3706 output_asm_insn ("tba", operands
);
3710 cc_status
= cc_prev_status
;
3715 if (D_REG_P (operands
[1]))
3717 if (optimize
&& find_regno_note (insn
, REG_DEAD
, HARD_D_REGNUM
))
3719 m68hc11_output_swap (insn
, operands
);
3723 output_asm_insn ("stab\t%T1", operands
);
3724 output_asm_insn ("ldx\t%t1", operands
);
3728 else if (Y_REG_P (operands
[1]))
3730 output_asm_insn ("sty\t%t0", operands
);
3731 output_asm_insn ("ldx\t%t0", operands
);
3733 else if (GET_CODE (operands
[1]) == CONST_INT
)
3735 output_asm_insn ("ldx\t%1", operands
);
3737 else if (dead_register_here (insn
, d_reg
))
3739 output_asm_insn ("ldab\t%b1", operands
);
3740 output_asm_insn ("xgdx", operands
);
3742 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3744 output_asm_insn ("xgdx", operands
);
3745 output_asm_insn ("ldab\t%b1", operands
);
3746 output_asm_insn ("xgdx", operands
);
3750 output_asm_insn ("pshb", operands
);
3751 output_asm_insn ("ldab\t%b1", operands
);
3752 output_asm_insn ("stab\t%T1", operands
);
3753 output_asm_insn ("ldx\t%t1", operands
);
3754 output_asm_insn ("pulb", operands
);
3760 if (D_REG_P (operands
[1]))
3762 output_asm_insn ("stab\t%T1", operands
);
3763 output_asm_insn ("ldy\t%t1", operands
);
3766 else if (X_REG_P (operands
[1]))
3768 output_asm_insn ("stx\t%t1", operands
);
3769 output_asm_insn ("ldy\t%t1", operands
);
3772 else if (GET_CODE (operands
[1]) == CONST_INT
)
3774 output_asm_insn ("ldy\t%1", operands
);
3776 else if (dead_register_here (insn
, d_reg
))
3778 output_asm_insn ("ldab\t%b1", operands
);
3779 output_asm_insn ("xgdy", operands
);
3781 else if (!reg_mentioned_p (operands
[0], operands
[1]))
3783 output_asm_insn ("xgdy", operands
);
3784 output_asm_insn ("ldab\t%b1", operands
);
3785 output_asm_insn ("xgdy", operands
);
3789 output_asm_insn ("pshb", operands
);
3790 output_asm_insn ("ldab\t%b1", operands
);
3791 output_asm_insn ("stab\t%T1", operands
);
3792 output_asm_insn ("ldy\t%t1", operands
);
3793 output_asm_insn ("pulb", operands
);
3799 fatal_insn ("invalid register in the instruction", insn
);
3803 else if (H_REG_P (operands
[1]))
3805 switch (REGNO (operands
[1]))
3809 output_asm_insn ("stab\t%b0", operands
);
3813 output_asm_insn ("staa\t%b0", operands
);
3817 output_asm_insn ("xgdx\n\tstab\t%b0\n\txgdx", operands
);
3821 output_asm_insn ("xgdy\n\tstab\t%b0\n\txgdy", operands
);
3825 fatal_insn ("invalid register in the move instruction", insn
);
3832 fatal_insn ("operand 1 must be a hard register", insn
);
3836 /* Generate the code for a ROTATE or ROTATERT on a QI or HI mode.
3837 The source and destination must be D or A and the shift must
3840 m68hc11_gen_rotate (enum rtx_code code
, rtx insn
, rtx operands
[])
3844 if (GET_CODE (operands
[2]) != CONST_INT
3845 || (!D_REG_P (operands
[0]) && !DA_REG_P (operands
[0])))
3846 fatal_insn ("invalid rotate insn", insn
);
3848 val
= INTVAL (operands
[2]);
3849 if (code
== ROTATERT
)
3850 val
= GET_MODE_SIZE (GET_MODE (operands
[0])) * BITS_PER_UNIT
- val
;
3852 if (GET_MODE (operands
[0]) != QImode
)
3855 /* Rotate by 8-bits if the shift is within [5..11]. */
3856 if (val
>= 5 && val
<= 11)
3859 output_asm_insn ("exg\ta,b", operands
);
3862 output_asm_insn ("psha", operands
);
3863 output_asm_insn ("tba", operands
);
3864 output_asm_insn ("pulb", operands
);
3869 /* If the shift is big, invert the rotation. */
3879 /* Set the carry to bit-15, but don't change D yet. */
3880 if (GET_MODE (operands
[0]) != QImode
)
3882 output_asm_insn ("asra", operands
);
3883 output_asm_insn ("rola", operands
);
3886 /* Rotate B first to move the carry to bit-0. */
3887 if (D_REG_P (operands
[0]))
3888 output_asm_insn ("rolb", operands
);
3890 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
3891 output_asm_insn ("rola", operands
);
3898 /* Set the carry to bit-8 of D. */
3899 if (GET_MODE (operands
[0]) != QImode
)
3900 output_asm_insn ("tap", operands
);
3902 /* Rotate B first to move the carry to bit-7. */
3903 if (D_REG_P (operands
[0]))
3904 output_asm_insn ("rorb", operands
);
3906 if (GET_MODE (operands
[0]) != QImode
|| DA_REG_P (operands
[0]))
3907 output_asm_insn ("rora", operands
);
3914 /* Store in cc_status the expressions that the condition codes will
3915 describe after execution of an instruction whose pattern is EXP.
3916 Do not alter them if the instruction would not alter the cc's. */
3919 m68hc11_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
3921 /* recognize SET insn's. */
3922 if (GET_CODE (exp
) == SET
)
3924 /* Jumps do not alter the cc's. */
3925 if (SET_DEST (exp
) == pc_rtx
)
3928 /* NOTE: most instructions don't affect the carry bit, but the
3929 bhi/bls/bhs/blo instructions use it. This isn't mentioned in
3930 the conditions.h header. */
3932 /* Function calls clobber the cc's. */
3933 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
3938 /* Tests and compares set the cc's in predictable ways. */
3939 else if (SET_DEST (exp
) == cc0_rtx
)
3941 cc_status
.flags
= 0;
3942 cc_status
.value1
= XEXP (exp
, 0);
3943 if (GET_CODE (XEXP (exp
, 1)) == COMPARE
3944 && XEXP (XEXP (exp
, 1), 1) == CONST0_RTX (GET_MODE (XEXP (XEXP (exp
, 1), 0))))
3945 cc_status
.value2
= XEXP (XEXP (exp
, 1), 0);
3947 cc_status
.value2
= XEXP (exp
, 1);
3951 /* All other instructions affect the condition codes. */
3952 cc_status
.flags
= 0;
3953 cc_status
.value1
= XEXP (exp
, 0);
3954 cc_status
.value2
= XEXP (exp
, 1);
3959 /* Default action if we haven't recognized something
3960 and returned earlier. */
3964 if (cc_status
.value2
!= 0)
3965 switch (GET_CODE (cc_status
.value2
))
3967 /* These logical operations can generate several insns.
3968 The flags are setup according to what is generated. */
3974 /* The (not ...) generates several 'com' instructions for
3975 non QImode. We have to invalidate the flags. */
3977 if (GET_MODE (cc_status
.value2
) != QImode
)
3989 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3990 cc_status
.flags
|= CC_NO_OVERFLOW
;
3993 /* The asl sets the overflow bit in such a way that this
3994 makes the flags unusable for a next compare insn. */
3998 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3999 cc_status
.flags
|= CC_NO_OVERFLOW
;
4002 /* A load/store instruction does not affect the carry. */
4007 cc_status
.flags
|= CC_NO_OVERFLOW
;
4013 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4015 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4016 cc_status
.value2
= 0;
4018 else if (cc_status
.value1
&& side_effects_p (cc_status
.value1
))
4019 cc_status
.value1
= 0;
4021 else if (cc_status
.value2
&& side_effects_p (cc_status
.value2
))
4022 cc_status
.value2
= 0;
4025 /* The current instruction does not affect the flags but changes
4026 the register 'reg'. See if the previous flags can be kept for the
4027 next instruction to avoid a comparison. */
4029 m68hc11_notice_keep_cc (rtx reg
)
4032 || cc_prev_status
.value1
== 0
4033 || rtx_equal_p (reg
, cc_prev_status
.value1
)
4034 || (cc_prev_status
.value2
4035 && reg_mentioned_p (reg
, cc_prev_status
.value2
)))
4038 cc_status
= cc_prev_status
;
4043 /* Machine Specific Reorg. */
4045 /* Z register replacement:
4047 GCC treats the Z register as an index base address register like
4048 X or Y. In general, it uses it during reload to compute the address
4049 of some operand. This helps the reload pass to avoid to fall into the
4050 register spill failure.
4052 The Z register is in the A_REGS class. In the machine description,
4053 the 'A' constraint matches it. The 'x' or 'y' constraints do not.
4055 It can appear everywhere an X or Y register can appear, except for
4056 some templates in the clobber section (when a clobber of X or Y is asked).
4057 For a given instruction, the template must ensure that no more than
4058 2 'A' registers are used. Otherwise, the register replacement is not
4061 To replace the Z register, the algorithm is not terrific:
4062 1. Insns that do not use the Z register are not changed
4063 2. When a Z register is used, we scan forward the insns to see
4064 a potential register to use: either X or Y and sometimes D.
4065 We stop when a call, a label or a branch is seen, or when we
4066 detect that both X and Y are used (probably at different times, but it does
4068 3. The register that will be used for the replacement of Z is saved
4069 in a .page0 register or on the stack. If the first instruction that
4070 used Z, uses Z as an input, the value is loaded from another .page0
4071 register. The replacement register is pushed on the stack in the
4072 rare cases where a compare insn uses Z and we couldn't find if X/Y
4074 4. The Z register is replaced in all instructions until we reach
4075 the end of the Z-block, as detected by step 2.
4076 5. If we detect that Z is still alive, its value is saved.
4077 If the replacement register is alive, its old value is loaded.
4079 The Z register can be disabled with -ffixed-z.
4089 int must_restore_reg
;
4100 int save_before_last
;
4101 int z_loaded_with_sp
;
4104 static int m68hc11_check_z_replacement (rtx
, struct replace_info
*);
4105 static void m68hc11_find_z_replacement (rtx
, struct replace_info
*);
4106 static void m68hc11_z_replacement (rtx
);
4107 static void m68hc11_reassign_regs (rtx
);
4109 int z_replacement_completed
= 0;
4111 /* Analyze the insn to find out which replacement register to use and
4112 the boundaries of the replacement.
4113 Returns 0 if we reached the last insn to be replaced, 1 if we can
4114 continue replacement in next insns. */
4117 m68hc11_check_z_replacement (rtx insn
, struct replace_info
*info
)
4119 int this_insn_uses_ix
;
4120 int this_insn_uses_iy
;
4121 int this_insn_uses_z
;
4122 int this_insn_uses_z_in_dst
;
4123 int this_insn_uses_d
;
4127 /* A call is said to clobber the Z register, we don't need
4128 to save the value of Z. We also don't need to restore
4129 the replacement register (unless it is used by the call). */
4130 if (GET_CODE (insn
) == CALL_INSN
)
4132 body
= PATTERN (insn
);
4134 info
->can_use_d
= 0;
4136 /* If the call is an indirect call with Z, we have to use the
4137 Y register because X can be used as an input (D+X).
4138 We also must not save Z nor restore Y. */
4139 if (reg_mentioned_p (z_reg
, body
))
4141 insn
= NEXT_INSN (insn
);
4144 info
->found_call
= 1;
4145 info
->must_restore_reg
= 0;
4146 info
->last
= NEXT_INSN (insn
);
4148 info
->need_save_z
= 0;
4151 if (GET_CODE (insn
) == CODE_LABEL
4152 || GET_CODE (insn
) == BARRIER
|| GET_CODE (insn
) == ASM_INPUT
)
4155 if (GET_CODE (insn
) == JUMP_INSN
)
4157 if (reg_mentioned_p (z_reg
, insn
) == 0)
4160 info
->can_use_d
= 0;
4161 info
->must_save_reg
= 0;
4162 info
->must_restore_reg
= 0;
4163 info
->need_save_z
= 0;
4164 info
->last
= NEXT_INSN (insn
);
4167 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4172 /* Z register dies here. */
4173 z_dies_here
= find_regno_note (insn
, REG_DEAD
, HARD_Z_REGNUM
) != NULL
;
4175 body
= PATTERN (insn
);
4176 if (GET_CODE (body
) == SET
)
4178 rtx src
= XEXP (body
, 1);
4179 rtx dst
= XEXP (body
, 0);
4181 /* Condition code is set here. We have to restore the X/Y and
4182 save into Z before any test/compare insn because once we save/restore
4183 we can change the condition codes. When the compare insn uses Z and
4184 we can't use X/Y, the comparison is made with the *ZREG soft register
4185 (this is supported by cmphi, cmpqi, tsthi, tstqi patterns). */
4188 if ((GET_CODE (src
) == REG
&& REGNO (src
) == HARD_Z_REGNUM
)
4189 || (GET_CODE (src
) == COMPARE
&&
4190 ((rtx_equal_p (XEXP (src
, 0), z_reg
)
4191 && H_REG_P (XEXP (src
, 1)))
4192 || (rtx_equal_p (XEXP (src
, 1), z_reg
)
4193 && H_REG_P (XEXP (src
, 0))))))
4195 if (insn
== info
->first
)
4197 info
->must_load_z
= 0;
4198 info
->must_save_reg
= 0;
4199 info
->must_restore_reg
= 0;
4200 info
->need_save_z
= 0;
4201 info
->found_call
= 1;
4202 info
->regno
= SOFT_Z_REGNUM
;
4203 info
->last
= NEXT_INSN (insn
);
4207 if (reg_mentioned_p (z_reg
, src
) == 0)
4209 info
->can_use_d
= 0;
4213 if (insn
!= info
->first
)
4216 /* Compare insn which uses Z. We have to save/restore the X/Y
4217 register without modifying the condition codes. For this
4218 we have to use a push/pop insn. */
4219 info
->must_push_reg
= 1;
4223 /* Z reg is set to something new. We don't need to load it. */
4226 if (!reg_mentioned_p (z_reg
, src
))
4228 /* Z reg is used before being set. Treat this as
4229 a new sequence of Z register replacement. */
4230 if (insn
!= info
->first
)
4234 info
->must_load_z
= 0;
4236 info
->z_set_count
++;
4237 info
->z_value
= src
;
4239 info
->z_loaded_with_sp
= 1;
4241 else if (reg_mentioned_p (z_reg
, dst
))
4242 info
->can_use_d
= 0;
4244 this_insn_uses_d
= reg_mentioned_p (d_reg
, src
)
4245 | reg_mentioned_p (d_reg
, dst
);
4246 this_insn_uses_ix
= reg_mentioned_p (ix_reg
, src
)
4247 | reg_mentioned_p (ix_reg
, dst
);
4248 this_insn_uses_iy
= reg_mentioned_p (iy_reg
, src
)
4249 | reg_mentioned_p (iy_reg
, dst
);
4250 this_insn_uses_z
= reg_mentioned_p (z_reg
, src
);
4252 /* If z is used as an address operand (like (MEM (reg z))),
4253 we can't replace it with d. */
4254 if (this_insn_uses_z
&& !Z_REG_P (src
)
4255 && !(m68hc11_arith_operator (src
, GET_MODE (src
))
4256 && Z_REG_P (XEXP (src
, 0))
4257 && !reg_mentioned_p (z_reg
, XEXP (src
, 1))
4258 && insn
== info
->first
4259 && dead_register_here (insn
, d_reg
)))
4260 info
->can_use_d
= 0;
4262 this_insn_uses_z_in_dst
= reg_mentioned_p (z_reg
, dst
);
4263 if (TARGET_M6812
&& !z_dies_here
4264 && ((this_insn_uses_z
&& side_effects_p (src
))
4265 || (this_insn_uses_z_in_dst
&& side_effects_p (dst
))))
4267 info
->need_save_z
= 1;
4268 info
->z_set_count
++;
4270 this_insn_uses_z
|= this_insn_uses_z_in_dst
;
4272 if (this_insn_uses_z
&& this_insn_uses_ix
&& this_insn_uses_iy
)
4274 fatal_insn ("registers IX, IY and Z used in the same INSN", insn
);
4277 if (this_insn_uses_d
)
4278 info
->can_use_d
= 0;
4280 /* IX and IY are used at the same time, we have to restore
4281 the value of the scratch register before this insn. */
4282 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4287 if (this_insn_uses_ix
&& X_REG_P (dst
) && GET_MODE (dst
) == SImode
)
4288 info
->can_use_d
= 0;
4290 if (info
->x_used
== 0 && this_insn_uses_ix
)
4294 /* We have a (set (REG:HI X) (REG:HI Z)).
4295 Since we use Z as the replacement register, this insn
4296 is no longer necessary. We turn it into a note. We must
4297 not reload the old value of X. */
4298 if (X_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4302 info
->need_save_z
= 0;
4305 info
->must_save_reg
= 0;
4306 info
->must_restore_reg
= 0;
4307 info
->found_call
= 1;
4308 info
->can_use_d
= 0;
4309 SET_INSN_DELETED (insn
);
4310 info
->last
= NEXT_INSN (insn
);
4315 && (rtx_equal_p (src
, z_reg
)
4316 || (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
))))
4320 info
->need_save_z
= 0;
4323 info
->last
= NEXT_INSN (insn
);
4324 info
->must_save_reg
= 0;
4325 info
->must_restore_reg
= 0;
4327 else if (X_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4328 && !reg_mentioned_p (ix_reg
, src
))
4333 info
->need_save_z
= 0;
4335 else if (TARGET_M6812
&& side_effects_p (src
))
4338 info
->must_restore_reg
= 0;
4343 info
->save_before_last
= 1;
4345 info
->must_restore_reg
= 0;
4346 info
->last
= NEXT_INSN (insn
);
4348 else if (info
->can_use_d
)
4350 info
->last
= NEXT_INSN (insn
);
4356 if (z_dies_here
&& !reg_mentioned_p (ix_reg
, src
)
4357 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_X_REGNUM
)
4359 info
->need_save_z
= 0;
4361 info
->last
= NEXT_INSN (insn
);
4362 info
->regno
= HARD_X_REGNUM
;
4363 info
->must_save_reg
= 0;
4364 info
->must_restore_reg
= 0;
4367 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, ix_reg
))
4369 info
->regno
= HARD_X_REGNUM
;
4370 info
->must_restore_reg
= 0;
4371 info
->must_save_reg
= 0;
4375 if (info
->y_used
== 0 && this_insn_uses_iy
)
4379 if (Y_REG_P (dst
) && rtx_equal_p (src
, z_reg
))
4383 info
->need_save_z
= 0;
4386 info
->must_save_reg
= 0;
4387 info
->must_restore_reg
= 0;
4388 info
->found_call
= 1;
4389 info
->can_use_d
= 0;
4390 SET_INSN_DELETED (insn
);
4391 info
->last
= NEXT_INSN (insn
);
4396 && (rtx_equal_p (src
, z_reg
)
4397 || (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
))))
4402 info
->need_save_z
= 0;
4404 info
->last
= NEXT_INSN (insn
);
4405 info
->must_save_reg
= 0;
4406 info
->must_restore_reg
= 0;
4408 else if (Y_REG_P (dst
) && reg_mentioned_p (z_reg
, src
)
4409 && !reg_mentioned_p (iy_reg
, src
))
4414 info
->need_save_z
= 0;
4416 else if (TARGET_M6812
&& side_effects_p (src
))
4419 info
->must_restore_reg
= 0;
4424 info
->save_before_last
= 1;
4426 info
->must_restore_reg
= 0;
4427 info
->last
= NEXT_INSN (insn
);
4429 else if (info
->can_use_d
)
4431 info
->last
= NEXT_INSN (insn
);
4438 if (z_dies_here
&& !reg_mentioned_p (iy_reg
, src
)
4439 && GET_CODE (dst
) == REG
&& REGNO (dst
) == HARD_Y_REGNUM
)
4441 info
->need_save_z
= 0;
4443 info
->last
= NEXT_INSN (insn
);
4444 info
->regno
= HARD_Y_REGNUM
;
4445 info
->must_save_reg
= 0;
4446 info
->must_restore_reg
= 0;
4449 if (rtx_equal_p (src
, z_reg
) && rtx_equal_p (dst
, iy_reg
))
4451 info
->regno
= HARD_Y_REGNUM
;
4452 info
->must_restore_reg
= 0;
4453 info
->must_save_reg
= 0;
4459 info
->need_save_z
= 0;
4461 if (info
->last
== 0)
4462 info
->last
= NEXT_INSN (insn
);
4465 return info
->last
!= NULL_RTX
? 0 : 1;
4467 if (GET_CODE (body
) == PARALLEL
)
4470 char ix_clobber
= 0;
4471 char iy_clobber
= 0;
4473 this_insn_uses_iy
= 0;
4474 this_insn_uses_ix
= 0;
4475 this_insn_uses_z
= 0;
4477 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
4480 int uses_ix
, uses_iy
, uses_z
;
4482 x
= XVECEXP (body
, 0, i
);
4484 if (info
->can_use_d
&& reg_mentioned_p (d_reg
, x
))
4485 info
->can_use_d
= 0;
4487 uses_ix
= reg_mentioned_p (ix_reg
, x
);
4488 uses_iy
= reg_mentioned_p (iy_reg
, x
);
4489 uses_z
= reg_mentioned_p (z_reg
, x
);
4490 if (GET_CODE (x
) == CLOBBER
)
4492 ix_clobber
|= uses_ix
;
4493 iy_clobber
|= uses_iy
;
4494 z_clobber
|= uses_z
;
4498 this_insn_uses_ix
|= uses_ix
;
4499 this_insn_uses_iy
|= uses_iy
;
4500 this_insn_uses_z
|= uses_z
;
4502 if (uses_z
&& GET_CODE (x
) == SET
)
4504 rtx dst
= XEXP (x
, 0);
4507 info
->z_set_count
++;
4509 if (TARGET_M6812
&& uses_z
&& side_effects_p (x
))
4510 info
->need_save_z
= 1;
4513 info
->need_save_z
= 0;
4517 printf ("Uses X:%d Y:%d Z:%d CX:%d CY:%d CZ:%d\n",
4518 this_insn_uses_ix
, this_insn_uses_iy
,
4519 this_insn_uses_z
, ix_clobber
, iy_clobber
, z_clobber
);
4522 if (this_insn_uses_z
)
4523 info
->can_use_d
= 0;
4525 if (z_clobber
&& info
->first
!= insn
)
4527 info
->need_save_z
= 0;
4531 if (z_clobber
&& info
->x_used
== 0 && info
->y_used
== 0)
4533 if (this_insn_uses_z
== 0 && insn
== info
->first
)
4535 info
->must_load_z
= 0;
4537 if (dead_register_here (insn
, d_reg
))
4539 info
->regno
= HARD_D_REGNUM
;
4540 info
->must_save_reg
= 0;
4541 info
->must_restore_reg
= 0;
4543 else if (dead_register_here (insn
, ix_reg
))
4545 info
->regno
= HARD_X_REGNUM
;
4546 info
->must_save_reg
= 0;
4547 info
->must_restore_reg
= 0;
4549 else if (dead_register_here (insn
, iy_reg
))
4551 info
->regno
= HARD_Y_REGNUM
;
4552 info
->must_save_reg
= 0;
4553 info
->must_restore_reg
= 0;
4555 if (info
->regno
>= 0)
4557 info
->last
= NEXT_INSN (insn
);
4560 if (this_insn_uses_ix
== 0)
4562 info
->regno
= HARD_X_REGNUM
;
4563 info
->must_save_reg
= 1;
4564 info
->must_restore_reg
= 1;
4566 else if (this_insn_uses_iy
== 0)
4568 info
->regno
= HARD_Y_REGNUM
;
4569 info
->must_save_reg
= 1;
4570 info
->must_restore_reg
= 1;
4574 info
->regno
= HARD_D_REGNUM
;
4575 info
->must_save_reg
= 1;
4576 info
->must_restore_reg
= 1;
4578 info
->last
= NEXT_INSN (insn
);
4582 if (((info
->x_used
|| this_insn_uses_ix
) && iy_clobber
)
4583 || ((info
->y_used
|| this_insn_uses_iy
) && ix_clobber
))
4585 if (this_insn_uses_z
)
4587 if (info
->y_used
== 0 && iy_clobber
)
4589 info
->regno
= HARD_Y_REGNUM
;
4590 info
->must_save_reg
= 0;
4591 info
->must_restore_reg
= 0;
4593 if (info
->first
!= insn
4594 && ((info
->y_used
&& ix_clobber
)
4595 || (info
->x_used
&& iy_clobber
)))
4598 info
->last
= NEXT_INSN (insn
);
4599 info
->save_before_last
= 1;
4603 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4605 if (this_insn_uses_z
)
4607 fatal_insn ("cannot do z-register replacement", insn
);
4611 if (info
->x_used
== 0 && (this_insn_uses_ix
|| ix_clobber
))
4618 if (iy_clobber
|| z_clobber
)
4620 info
->last
= NEXT_INSN (insn
);
4621 info
->save_before_last
= 1;
4626 if (info
->y_used
== 0 && (this_insn_uses_iy
|| iy_clobber
))
4633 if (ix_clobber
|| z_clobber
)
4635 info
->last
= NEXT_INSN (insn
);
4636 info
->save_before_last
= 1;
4643 info
->need_save_z
= 0;
4647 if (GET_CODE (body
) == CLOBBER
)
4650 /* IX and IY are used at the same time, we have to restore
4651 the value of the scratch register before this insn. */
4652 if (this_insn_uses_ix
&& this_insn_uses_iy
)
4656 if (info
->x_used
== 0 && this_insn_uses_ix
)
4664 if (info
->y_used
== 0 && this_insn_uses_iy
)
4678 m68hc11_find_z_replacement (rtx insn
, struct replace_info
*info
)
4682 info
->replace_reg
= NULL_RTX
;
4683 info
->must_load_z
= 1;
4684 info
->need_save_z
= 1;
4685 info
->must_save_reg
= 1;
4686 info
->must_restore_reg
= 1;
4690 info
->can_use_d
= TARGET_M6811
? 1 : 0;
4691 info
->found_call
= 0;
4695 info
->z_set_count
= 0;
4696 info
->z_value
= NULL_RTX
;
4697 info
->must_push_reg
= 0;
4698 info
->save_before_last
= 0;
4699 info
->z_loaded_with_sp
= 0;
4701 /* Scan the insn forward to find an address register that is not used.
4703 - the flow of the program changes,
4704 - when we detect that both X and Y are necessary,
4705 - when the Z register dies,
4706 - when the condition codes are set. */
4708 for (; insn
&& info
->z_died
== 0; insn
= NEXT_INSN (insn
))
4710 if (m68hc11_check_z_replacement (insn
, info
) == 0)
4714 /* May be we can use Y or X if they contain the same value as Z.
4715 This happens very often after the reload. */
4716 if (info
->z_set_count
== 1)
4718 rtx p
= info
->first
;
4723 v
= find_last_value (iy_reg
, &p
, insn
, 1);
4725 else if (info
->y_used
)
4727 v
= find_last_value (ix_reg
, &p
, insn
, 1);
4729 if (v
&& (v
!= iy_reg
&& v
!= ix_reg
) && rtx_equal_p (v
, info
->z_value
))
4732 info
->regno
= HARD_Y_REGNUM
;
4734 info
->regno
= HARD_X_REGNUM
;
4735 info
->must_load_z
= 0;
4736 info
->must_save_reg
= 0;
4737 info
->must_restore_reg
= 0;
4738 info
->found_call
= 1;
4741 if (info
->z_set_count
== 0)
4742 info
->need_save_z
= 0;
4745 info
->need_save_z
= 0;
4747 if (info
->last
== 0)
4750 if (info
->regno
>= 0)
4753 info
->replace_reg
= gen_rtx_REG (HImode
, reg
);
4755 else if (info
->can_use_d
)
4757 reg
= HARD_D_REGNUM
;
4758 info
->replace_reg
= d_reg
;
4760 else if (info
->x_used
)
4762 reg
= HARD_Y_REGNUM
;
4763 info
->replace_reg
= iy_reg
;
4767 reg
= HARD_X_REGNUM
;
4768 info
->replace_reg
= ix_reg
;
4772 if (info
->must_save_reg
&& info
->must_restore_reg
)
4774 if (insn
&& dead_register_here (insn
, info
->replace_reg
))
4776 info
->must_save_reg
= 0;
4777 info
->must_restore_reg
= 0;
4782 /* The insn uses the Z register. Find a replacement register for it
4783 (either X or Y) and replace it in the insn and the next ones until
4784 the flow changes or the replacement register is used. Instructions
4785 are emitted before and after the Z-block to preserve the value of
4786 Z and of the replacement register. */
4789 m68hc11_z_replacement (rtx insn
)
4793 struct replace_info info
;
4795 /* Find trivial case where we only need to replace z with the
4796 equivalent soft register. */
4797 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SET
)
4799 rtx body
= PATTERN (insn
);
4800 rtx src
= XEXP (body
, 1);
4801 rtx dst
= XEXP (body
, 0);
4803 if (Z_REG_P (dst
) && (H_REG_P (src
) && !SP_REG_P (src
)))
4805 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4808 else if (Z_REG_P (src
)
4809 && ((H_REG_P (dst
) && !SP_REG_P (src
)) || dst
== cc0_rtx
))
4811 XEXP (body
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4814 else if (D_REG_P (dst
)
4815 && m68hc11_arith_operator (src
, GET_MODE (src
))
4816 && D_REG_P (XEXP (src
, 0)) && Z_REG_P (XEXP (src
, 1)))
4818 XEXP (src
, 1) = gen_rtx_REG (GET_MODE (src
), SOFT_Z_REGNUM
);
4821 else if (Z_REG_P (dst
) && GET_CODE (src
) == CONST_INT
4822 && INTVAL (src
) == 0)
4824 XEXP (body
, 0) = gen_rtx_REG (GET_MODE (dst
), SOFT_Z_REGNUM
);
4825 /* Force it to be re-recognized. */
4826 INSN_CODE (insn
) = -1;
4831 m68hc11_find_z_replacement (insn
, &info
);
4833 replace_reg
= info
.replace_reg
;
4834 replace_reg_qi
= NULL_RTX
;
4836 /* Save the X register in a .page0 location. */
4837 if (info
.must_save_reg
&& !info
.must_push_reg
)
4841 if (info
.must_push_reg
&& 0)
4842 dst
= gen_rtx_MEM (HImode
,
4843 gen_rtx_PRE_DEC (HImode
,
4844 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
4846 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
4848 emit_insn_before (gen_movhi (dst
,
4849 gen_rtx_REG (HImode
, info
.regno
)), insn
);
4851 if (info
.must_load_z
&& !info
.must_push_reg
)
4853 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
4854 gen_rtx_REG (HImode
, SOFT_Z_REGNUM
)),
4859 /* Replace all occurrence of Z by replace_reg.
4860 Stop when the last instruction to replace is reached.
4861 Also stop when we detect a change in the flow (but it's not
4862 necessary; just safeguard). */
4864 for (; insn
&& insn
!= info
.last
; insn
= NEXT_INSN (insn
))
4868 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == BARRIER
)
4871 if (GET_CODE (insn
) != INSN
4872 && GET_CODE (insn
) != CALL_INSN
&& GET_CODE (insn
) != JUMP_INSN
)
4875 body
= PATTERN (insn
);
4876 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
4877 || GET_CODE (body
) == ASM_OPERANDS
4878 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4882 if (debug_m6811
&& reg_mentioned_p (replace_reg
, body
))
4884 printf ("Reg mentioned here...:\n");
4889 /* Stack pointer was decremented by 2 due to the push.
4890 Correct that by adding 2 to the destination. */
4891 if (info
.must_push_reg
4892 && info
.z_loaded_with_sp
&& GET_CODE (body
) == SET
)
4896 src
= SET_SRC (body
);
4897 dst
= SET_DEST (body
);
4898 if (SP_REG_P (src
) && Z_REG_P (dst
))
4899 emit_insn_after (gen_addhi3 (dst
, dst
, const2_rtx
), insn
);
4902 /* Replace any (REG:HI Z) occurrence by either X or Y. */
4903 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
4905 INSN_CODE (insn
) = -1;
4906 if (!validate_replace_rtx (z_reg
, replace_reg
, insn
))
4907 fatal_insn ("cannot do z-register replacement", insn
);
4910 /* Likewise for (REG:QI Z). */
4911 if (reg_mentioned_p (z_reg
, insn
))
4913 if (replace_reg_qi
== NULL_RTX
)
4914 replace_reg_qi
= gen_rtx_REG (QImode
, REGNO (replace_reg
));
4915 validate_replace_rtx (z_reg_qi
, replace_reg_qi
, insn
);
4918 /* If there is a REG_INC note on Z, replace it with a
4919 REG_INC note on the replacement register. This is necessary
4920 to make sure that the flow pass will identify the change
4921 and it will not remove a possible insn that saves Z. */
4922 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
4924 if (REG_NOTE_KIND (note
) == REG_INC
4925 && GET_CODE (XEXP (note
, 0)) == REG
4926 && REGNO (XEXP (note
, 0)) == REGNO (z_reg
))
4928 XEXP (note
, 0) = replace_reg
;
4932 if (GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
4936 /* Save Z before restoring the old value. */
4937 if (insn
&& info
.need_save_z
&& !info
.must_push_reg
)
4939 rtx save_pos_insn
= insn
;
4941 /* If Z is clobber by the last insn, we have to save its value
4942 before the last instruction. */
4943 if (info
.save_before_last
)
4944 save_pos_insn
= PREV_INSN (save_pos_insn
);
4946 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, SOFT_Z_REGNUM
),
4947 gen_rtx_REG (HImode
, info
.regno
)),
4951 if (info
.must_push_reg
&& info
.last
)
4955 body
= PATTERN (info
.last
);
4956 new_body
= gen_rtx_PARALLEL (VOIDmode
,
4958 gen_rtx_USE (VOIDmode
,
4960 gen_rtx_USE (VOIDmode
,
4961 gen_rtx_REG (HImode
,
4963 PATTERN (info
.last
) = new_body
;
4965 /* Force recognition on insn since we changed it. */
4966 INSN_CODE (insn
) = -1;
4968 if (!validate_replace_rtx (z_reg
, replace_reg
, info
.last
))
4970 fatal_insn ("invalid Z register replacement for insn", insn
);
4972 insn
= NEXT_INSN (info
.last
);
4975 /* Restore replacement register unless it was died. */
4976 if (insn
&& info
.must_restore_reg
&& !info
.must_push_reg
)
4980 if (info
.must_push_reg
&& 0)
4981 dst
= gen_rtx_MEM (HImode
,
4982 gen_rtx_POST_INC (HImode
,
4983 gen_rtx_REG (HImode
, HARD_SP_REGNUM
)));
4985 dst
= gen_rtx_REG (HImode
, SOFT_SAVED_XY_REGNUM
);
4987 emit_insn_before (gen_movhi (gen_rtx_REG (HImode
, info
.regno
),
4994 /* Scan all the insn and re-affects some registers
4995 - The Z register (if it was used), is affected to X or Y depending
4996 on the instruction. */
4999 m68hc11_reassign_regs (rtx first
)
5003 ix_reg
= gen_rtx_REG (HImode
, HARD_X_REGNUM
);
5004 iy_reg
= gen_rtx_REG (HImode
, HARD_Y_REGNUM
);
5005 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
5006 z_reg_qi
= gen_rtx_REG (QImode
, HARD_Z_REGNUM
);
5008 /* Scan all insns to replace Z by X or Y preserving the old value
5009 of X/Y and restoring it afterward. */
5011 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5015 if (GET_CODE (insn
) == CODE_LABEL
5016 || GET_CODE (insn
) == NOTE
|| GET_CODE (insn
) == BARRIER
)
5022 body
= PATTERN (insn
);
5023 if (GET_CODE (body
) == CLOBBER
|| GET_CODE (body
) == USE
)
5026 if (GET_CODE (body
) == CONST_INT
|| GET_CODE (body
) == ASM_INPUT
5027 || GET_CODE (body
) == ASM_OPERANDS
5028 || GET_CODE (body
) == UNSPEC
|| GET_CODE (body
) == UNSPEC_VOLATILE
)
5031 if (GET_CODE (body
) == SET
|| GET_CODE (body
) == PARALLEL
5032 || GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
)
5035 /* If Z appears in this insn, replace it in the current insn
5036 and the next ones until the flow changes or we have to
5037 restore back the replacement register. */
5039 if (reg_mentioned_p (z_reg
, body
))
5041 m68hc11_z_replacement (insn
);
5046 printf ("insn not handled by Z replacement:\n");
5054 /* Machine-dependent reorg pass.
5055 Specific optimizations are defined here:
5056 - this pass changes the Z register into either X or Y
5057 (it preserves X/Y previous values in a memory slot in page0).
5059 When this pass is finished, the global variable
5060 'z_replacement_completed' is set to 2. */
5063 m68hc11_reorg (void)
5068 z_replacement_completed
= 0;
5069 z_reg
= gen_rtx_REG (HImode
, HARD_Z_REGNUM
);
5070 first
= get_insns ();
5072 /* Some RTX are shared at this point. This breaks the Z register
5073 replacement, unshare everything. */
5074 unshare_all_rtl_again (first
);
5076 /* Force a split of all splittable insn. This is necessary for the
5077 Z register replacement mechanism because we end up with basic insns. */
5078 split_all_insns_noflow ();
5081 z_replacement_completed
= 1;
5082 m68hc11_reassign_regs (first
);
5085 compute_bb_for_insn ();
5087 /* After some splitting, there are some opportunities for CSE pass.
5088 This happens quite often when 32-bit or above patterns are split. */
5089 if (optimize
> 0 && split_done
)
5091 reload_cse_regs (first
);
5094 /* Re-create the REG_DEAD notes. These notes are used in the machine
5095 description to use the best assembly directives. */
5098 df_note_add_problem ();
5100 df_remove_problem (df_note
);
5103 z_replacement_completed
= 2;
5105 /* If optimizing, then go ahead and split insns that must be
5106 split after Z register replacement. This gives more opportunities
5107 for peephole (in particular for consecutives xgdx/xgdy). */
5109 split_all_insns_noflow ();
5111 /* Once insns are split after the z_replacement_completed == 2,
5112 we must not re-run the life_analysis. The xgdx/xgdy patterns
5113 are not recognized and the life_analysis pass removes some
5114 insns because it thinks some (SETs) are noops or made to dead
5115 stores (which is false due to the swap).
5117 Do a simple pass to eliminate the noop set that the final
5118 split could generate (because it was easier for split definition). */
5122 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5126 if (INSN_DELETED_P (insn
))
5131 /* Remove the (set (R) (R)) insns generated by some splits. */
5132 body
= PATTERN (insn
);
5133 if (GET_CODE (body
) == SET
5134 && rtx_equal_p (SET_SRC (body
), SET_DEST (body
)))
5136 SET_INSN_DELETED (insn
);
5143 /* Override memcpy */
5146 m68hc11_init_libfuncs (void)
5148 memcpy_libfunc
= init_one_libfunc ("__memcpy");
5149 memcmp_libfunc
= init_one_libfunc ("__memcmp");
5150 memset_libfunc
= init_one_libfunc ("__memset");
5155 /* Cost functions. */
5157 /* Cost of moving memory. */
5159 m68hc11_memory_move_cost (enum machine_mode mode
, enum reg_class rclass
,
5160 int in ATTRIBUTE_UNUSED
)
5162 if (rclass
<= H_REGS
&& rclass
> NO_REGS
)
5164 if (GET_MODE_SIZE (mode
) <= 2)
5165 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5167 return COSTS_N_INSNS (2) + (reload_completed
| reload_in_progress
);
5171 if (GET_MODE_SIZE (mode
) <= 2)
5172 return COSTS_N_INSNS (3);
5174 return COSTS_N_INSNS (4);
5179 /* Cost of moving data from a register of class 'from' to on in class 'to'.
5180 Reload does not check the constraint of set insns when the two registers
5181 have a move cost of 2. Setting a higher cost will force reload to check
5184 m68hc11_register_move_cost (enum machine_mode mode
, enum reg_class from
,
5187 /* All costs are symmetric, so reduce cases by putting the
5188 lower number class as the destination. */
5191 enum reg_class tmp
= to
;
5192 to
= from
, from
= tmp
;
5195 return m68hc11_memory_move_cost (mode
, S_REGS
, 0);
5196 else if (from
<= S_REGS
)
5197 return COSTS_N_INSNS (1) + (reload_completed
| reload_in_progress
);
5199 return COSTS_N_INSNS (2);
5203 /* Provide the costs of an addressing mode that contains ADDR.
5204 If ADDR is not a valid address, its cost is irrelevant. */
5207 m68hc11_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
5211 switch (GET_CODE (addr
))
5214 /* Make the cost of hard registers and specially SP, FP small. */
5215 if (REGNO (addr
) < FIRST_PSEUDO_REGISTER
)
5232 register rtx plus0
= XEXP (addr
, 0);
5233 register rtx plus1
= XEXP (addr
, 1);
5235 if (GET_CODE (plus0
) != REG
)
5238 switch (GET_CODE (plus1
))
5241 if (INTVAL (plus1
) >= 2 * m68hc11_max_offset
5242 || INTVAL (plus1
) < m68hc11_min_offset
)
5244 else if (INTVAL (plus1
) >= m68hc11_max_offset
)
5248 if (REGNO (plus0
) < FIRST_PSEUDO_REGISTER
)
5270 if (SP_REG_P (XEXP (addr
, 0)))
5279 printf ("Address cost: %d for :", cost
);
5288 m68hc11_shift_cost (enum machine_mode mode
, rtx x
, int shift
)
5292 total
= rtx_cost (x
, SET
, !optimize_size
);
5294 total
+= m68hc11_cost
->shiftQI_const
[shift
% 8];
5295 else if (mode
== HImode
)
5296 total
+= m68hc11_cost
->shiftHI_const
[shift
% 16];
5297 else if (shift
== 8 || shift
== 16 || shift
== 32)
5298 total
+= m68hc11_cost
->shiftHI_const
[8];
5299 else if (shift
!= 0 && shift
!= 16 && shift
!= 32)
5301 total
+= m68hc11_cost
->shiftHI_const
[1] * shift
;
5304 /* For SI and others, the cost is higher. */
5305 if (GET_MODE_SIZE (mode
) > 2 && (shift
% 16) != 0)
5306 total
*= GET_MODE_SIZE (mode
) / 2;
5308 /* When optimizing for size, make shift more costly so that
5309 multiplications are preferred. */
5310 if (optimize_size
&& (shift
% 8) != 0)
5317 m68hc11_rtx_costs_1 (rtx x
, enum rtx_code code
,
5318 enum rtx_code outer_code ATTRIBUTE_UNUSED
)
5320 enum machine_mode mode
= GET_MODE (x
);
5331 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5333 return m68hc11_shift_cost (mode
, XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
5336 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5337 total
+= m68hc11_cost
->shift_var
;
5343 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5344 total
+= m68hc11_cost
->logical
;
5346 /* Logical instructions are byte instructions only. */
5347 total
*= GET_MODE_SIZE (mode
);
5352 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5353 total
+= m68hc11_cost
->add
;
5354 if (GET_MODE_SIZE (mode
) > 2)
5356 total
*= GET_MODE_SIZE (mode
) / 2;
5363 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
) + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5367 total
+= m68hc11_cost
->divQI
;
5371 total
+= m68hc11_cost
->divHI
;
5376 total
+= m68hc11_cost
->divSI
;
5382 /* mul instruction produces 16-bit result. */
5383 if (mode
== HImode
&& GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5384 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5385 return m68hc11_cost
->multQI
5386 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
, !optimize_size
)
5387 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
, !optimize_size
);
5389 /* emul instruction produces 32-bit result for 68HC12. */
5390 if (TARGET_M6812
&& mode
== SImode
5391 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5392 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
5393 return m68hc11_cost
->multHI
5394 + rtx_cost (XEXP (XEXP (x
, 0), 0), code
, !optimize_size
)
5395 + rtx_cost (XEXP (XEXP (x
, 1), 0), code
, !optimize_size
);
5397 total
= rtx_cost (XEXP (x
, 0), code
, !optimize_size
)
5398 + rtx_cost (XEXP (x
, 1), code
, !optimize_size
);
5402 total
+= m68hc11_cost
->multQI
;
5406 total
+= m68hc11_cost
->multHI
;
5411 total
+= m68hc11_cost
->multSI
;
5418 extra_cost
= COSTS_N_INSNS (2);
5426 total
= extra_cost
+ rtx_cost (XEXP (x
, 0), code
, !optimize_size
);
5429 return total
+ COSTS_N_INSNS (1);
5433 return total
+ COSTS_N_INSNS (2);
5437 return total
+ COSTS_N_INSNS (4);
5439 return total
+ COSTS_N_INSNS (8);
5442 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
5443 return COSTS_N_INSNS (1);
5445 return COSTS_N_INSNS (1);
5448 return COSTS_N_INSNS (4);
5453 m68hc11_rtx_costs (rtx x
, int codearg
, int outer_code_arg
, int *total
,
5454 bool speed ATTRIBUTE_UNUSED
)
5456 enum rtx_code code
= (enum rtx_code
) codearg
;
5457 enum rtx_code outer_code
= (enum rtx_code
) outer_code_arg
;
5461 /* Constants are cheap. Moving them in registers must be avoided
5462 because most instructions do not handle two register operands. */
5468 /* Logical and arithmetic operations with a constant operand are
5469 better because they are not supported with two registers. */
5471 if (outer_code
== SET
&& x
== const0_rtx
)
5472 /* After reload, the reload_cse pass checks the cost to change
5473 a SET into a PLUS. Make const0 cheap then. */
5474 *total
= 1 - reload_completed
;
5480 if (outer_code
!= COMPARE
)
5503 *total
= m68hc11_rtx_costs_1 (x
, code
, outer_code
);
5512 /* Worker function for TARGET_ASM_FILE_START. */
5515 m68hc11_file_start (void)
5517 default_file_start ();
5519 fprintf (asm_out_file
, "\t.mode %s\n", TARGET_SHORT
? "mshort" : "mlong");
5523 /* Worker function for TARGET_ASM_CONSTRUCTOR. */
5526 m68hc11_asm_out_constructor (rtx symbol
, int priority
)
5528 default_ctor_section_asm_out_constructor (symbol
, priority
);
5529 fprintf (asm_out_file
, "\t.globl\t__do_global_ctors\n");
5532 /* Worker function for TARGET_ASM_DESTRUCTOR. */
5535 m68hc11_asm_out_destructor (rtx symbol
, int priority
)
5537 default_dtor_section_asm_out_destructor (symbol
, priority
);
5538 fprintf (asm_out_file
, "\t.globl\t__do_global_dtors\n");
5541 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5544 m68hc11_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5545 int incoming ATTRIBUTE_UNUSED
)
5547 return gen_rtx_REG (Pmode
, HARD_D_REGNUM
);
5550 /* Return true if type TYPE should be returned in memory.
5551 Blocks and data types largers than 4 bytes cannot be returned
5552 in the register (D + X = 4). */
5555 m68hc11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5557 if (TYPE_MODE (type
) == BLKmode
)
5559 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5560 return (size
== -1 || size
> 4);
5563 return GET_MODE_SIZE (TYPE_MODE (type
)) > 4;
5566 #include "gt-m68hc11.h"