1 /* Definitions of target machine for GNU compiler.
2 Motorola 68HC11 and 68HC12.
3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA.
24 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
25 on gcc 2.6.3. I have used it as a starting point for this port.
26 However, this new port is a complete re-write. Its internal
27 design is completely different. The generated code is not
28 compatible with the gcc 2.6.3 port.
30 The gcc 2.6.3 port is available at:
32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
36 /*****************************************************************************
38 ** Controlling the Compilation Driver, `gcc'
40 *****************************************************************************/
44 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */
47 "%{m68hc12:-m68hc12}" \
48 "%{m68hcs12:-m68hcs12}" \
49 "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \
50 "%{mshort:-mshort}%{!mshort:-mlong} " \
51 "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}"
54 /* We need to tell the linker the target elf format. Just pass an
55 emulation option. This can be overridden by -Wl option of gcc. */
58 "%{m68hc12:-m m68hc12elf}" \
59 "%{m68hcs12:-m m68hc12elf}" \
60 "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \
61 "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}"
74 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\
75 %{!mshort:-D__INT__=32}\
76 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\
77 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\
78 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\
79 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\
80 %{mlong-calls:-D__USE_RTC__}"
84 #define STARTFILE_SPEC "crt1%O%s"
86 /* Names to predefine in the preprocessor for this target machine. */
87 #define TARGET_CPU_CPP_BUILTINS() \
90 builtin_define_std ("mc68hc1x"); \
94 /* As an embedded target, we have no libc. */
97 /* Forward type declaration for prototypes definitions.
98 rtx_ptr is equivalent to rtx. Can't use the same name. */
100 typedef struct rtx_def
*rtx_ptr
;
103 typedef union tree_node
*tree_ptr
;
105 /* We can't declare enum machine_mode forward nor include 'machmode.h' here.
106 Prototypes defined here will use an int instead. It's better than no
108 typedef int enum_machine_mode
;
110 /*****************************************************************************
112 ** Run-time Target Specification
114 *****************************************************************************/
116 /* Run-time compilation parameters selecting different hardware subsets. */
118 extern int target_flags
;
120 extern short *reg_renumber
; /* def in local_alloc.c */
122 /* Macros used in the machine description to test the flags. */
124 /* 6811 specific options
126 * For 68HC12, the auto inc/dec mode is disabled by default. The reason
127 * is that for most programs, the reload pass will fail because it needs
128 * more registers to save the value of the indexed register after the
129 * memory access. For simple programs, you can enable this
130 * with -mauto-incdec.
133 #define MASK_SHORT 0002 /* Compile with 16-bit `int' */
134 #define MASK_AUTO_INC_DEC 0004
135 #define MASK_M6811 0010
136 #define MASK_M6812 0020
137 #define MASK_M68S12 0040
138 #define MASK_NO_DIRECT_MODE 0100
139 #define MASK_MIN_MAX 0200
140 #define MASK_LONG_CALLS 0400
142 #define TARGET_OP_TIME (optimize && optimize_size == 0)
143 #define TARGET_SHORT (target_flags & MASK_SHORT)
144 #define TARGET_M6811 (target_flags & MASK_M6811)
145 #define TARGET_M6812 (target_flags & MASK_M6812)
146 #define TARGET_M68S12 (target_flags & MASK_M68S12)
147 #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC)
148 #define TARGET_MIN_MAX (target_flags & MASK_MIN_MAX)
149 #define TARGET_NO_DIRECT_MODE (target_flags & MASK_NO_DIRECT_MODE)
150 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE)
151 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
153 /* Default target_flags if no switches specified. */
154 #ifndef TARGET_DEFAULT
155 # define TARGET_DEFAULT (MASK_M6811)
158 /* Define this macro as a C expression for the initializer of an
159 array of string to tell the driver program which options are
160 defaults for this target and thus do not need to be handled
161 specially when using `MULTILIB_OPTIONS'. */
162 #ifndef MULTILIB_DEFAULTS
163 # if TARGET_DEFAULT & MASK_M6811
164 # define MULTILIB_DEFAULTS { "m68hc11" }
166 # define MULTILIB_DEFAULTS { "m68hc12" }
170 /* Macro to define tables used to set the flags. This is a list in braces of
171 pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits
172 to set or minus the bits to clear. An empty string NAME is used to
173 identify the default VALUE. */
175 #define TARGET_SWITCHES \
176 { { "short", MASK_SHORT, \
177 N_("Compile with 16-bit integer mode")}, \
178 { "noshort", - MASK_SHORT, \
179 N_("Compile with 32-bit integer mode")}, \
180 { "auto-incdec", MASK_AUTO_INC_DEC, \
181 N_("Auto pre/post decrement increment allowed")}, \
182 { "noauto-incdec", - MASK_AUTO_INC_DEC, \
183 N_("Auto pre/post decrement increment not allowed")}, \
184 { "inmax", MASK_MIN_MAX, \
185 N_("Min/max instructions allowed")}, \
186 { "nominmax", - MASK_MIN_MAX, \
187 N_("Min/max instructions not allowed")}, \
188 { "long-calls", MASK_LONG_CALLS, \
189 N_("Use call and rtc for function calls and returns")}, \
190 { "nolong-calls", - MASK_LONG_CALLS, \
191 N_("Use jsr and rts for function calls and returns")}, \
192 { "relax", MASK_NO_DIRECT_MODE, \
193 N_("Do not use direct addressing mode for soft registers")},\
194 { "norelax", -MASK_NO_DIRECT_MODE, \
195 N_("Use direct addressing mode for soft registers")}, \
196 { "68hc11", MASK_M6811, \
197 N_("Compile for a 68HC11")}, \
198 { "68hc12", MASK_M6812, \
199 N_("Compile for a 68HC12")}, \
200 { "68hcs12", MASK_M6812 | MASK_M68S12, \
201 N_("Compile for a 68HCS12")}, \
202 { "6811", MASK_M6811, \
203 N_("Compile for a 68HC11")}, \
204 { "6812", MASK_M6812, \
205 N_("Compile for a 68HC12")}, \
206 { "68S12", MASK_M6812 | MASK_M68S12, \
207 N_("Compile for a 68HCS12")}, \
208 { "", TARGET_DEFAULT, 0 }}
210 /* This macro is similar to `TARGET_SWITCHES' but defines names of
211 command options that have values. Its definition is an
212 initializer with a subgrouping for each command option.
214 Each subgrouping contains a string constant, that defines the
215 fixed part of the option name, and the address of a variable. The
216 variable, type `char *', is set to the variable part of the given
217 option if the fixed part matches. The actual option name is made
218 by appending `-m' to the specified name. */
219 #define TARGET_OPTIONS \
220 { { "reg-alloc=", &m68hc11_reg_alloc_order, \
221 N_("Specify the register allocation order"), 0}, \
222 { "soft-reg-count=", &m68hc11_soft_reg_count, \
223 N_("Indicate the number of soft registers available"), 0}, \
227 /* These are meant to be redefined in the host dependent files */
228 #define SUBTARGET_SWITCHES
229 #define SUBTARGET_OPTIONS
231 extern const char *m68hc11_regparm_string
;
232 extern const char *m68hc11_reg_alloc_order
;
233 extern const char *m68hc11_soft_reg_count
;
235 #ifndef TARGET_M68HC12
236 # define TARGET_M68HC11 1
239 /* Print subsidiary information on the compiler version in use. */
240 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)")
242 /* Sometimes certain combinations of command options do not make
243 sense on a particular target machine. You can define a macro
244 `OVERRIDE_OPTIONS' to take account of this. This macro, if
245 defined, is executed once just after all the command options have
248 Don't use this macro to turn on various extra optimizations for
249 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
251 #define OVERRIDE_OPTIONS m68hc11_override_options ();
254 /* Define cost parameters for a given processor variant. */
255 struct processor_costs
{
256 const int add
; /* cost of an add instruction */
257 const int logical
; /* cost of a logical instruction */
259 const int shiftQI_const
[8];
260 const int shiftHI_const
[16];
269 /* Costs for the current processor. */
270 extern const struct processor_costs
*m68hc11_cost
;
273 /* target machine storage layout */
275 /* Define this if most significant byte of a word is the lowest numbered. */
276 #define BYTES_BIG_ENDIAN 1
278 /* Define this if most significant bit is lowest numbered
279 in instructions that operate on numbered bit-fields. */
280 #define BITS_BIG_ENDIAN 0
282 /* Define this if most significant word of a multiword number is numbered. */
283 #define WORDS_BIG_ENDIAN 1
285 /* Width of a word, in units (bytes). */
286 #define UNITS_PER_WORD 2
288 /* Definition of size_t. This is really an unsigned short as the
289 68hc11 only handles a 64K address space. */
290 #define SIZE_TYPE "short unsigned int"
292 /* A C expression for a string describing the name of the data type
293 to use for the result of subtracting two pointers. The typedef
294 name `ptrdiff_t' is defined using the contents of the string.
295 The 68hc11 only has a 64K address space. */
296 #define PTRDIFF_TYPE "short int"
298 /* Allocation boundary (bits) for storing pointers in memory. */
299 #define POINTER_BOUNDARY 8
301 /* Normal alignment required for function parameters on the stack, in bits.
302 This can't be less than BITS_PER_WORD */
303 #define PARM_BOUNDARY (BITS_PER_WORD)
305 /* Boundary (bits) on which stack pointer should be aligned. */
306 #define STACK_BOUNDARY 8
308 /* Allocation boundary (bits) for the code of a function. */
309 #define FUNCTION_BOUNDARY 8
311 #define BIGGEST_ALIGNMENT 8
313 /* Alignment of field after `int : 0' in a structure. */
314 #define EMPTY_FIELD_BOUNDARY 8
316 /* Every structure's size must be a multiple of this. */
317 #define STRUCTURE_SIZE_BOUNDARY 8
319 /* Define this if instructions will fail to work if given data not
320 on the nominal alignment. If instructions will merely go slower
321 in that case, do not define this macro. */
322 #define STRICT_ALIGNMENT 0
324 /* An integer expression for the size in bits of the largest integer
325 machine mode that should actually be used. All integer machine modes of
326 this size or smaller can be used for structures and unions with the
327 appropriate sizes. */
328 #define MAX_FIXED_MODE_SIZE 64
330 /* target machine storage layout */
332 /* Size (bits) of the type "int" on target machine
333 (If undefined, default is BITS_PER_WORD). */
334 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
336 /* Size (bits) of the type "short" on target machine */
337 #define SHORT_TYPE_SIZE 16
339 /* Size (bits) of the type "long" on target machine */
340 #define LONG_TYPE_SIZE 32
342 /* Size (bits) of the type "long long" on target machine */
343 #define LONG_LONG_TYPE_SIZE 64
345 /* A C expression for the size in bits of the type `float' on the
346 target machine. If you don't define this, the default is one word.
347 Don't use default: a word is only 16. */
348 #define FLOAT_TYPE_SIZE 32
350 /* A C expression for the size in bits of the type double on the target
351 machine. If you don't define this, the default is two words.
352 Be IEEE compliant. */
353 #define DOUBLE_TYPE_SIZE 64
355 #define LONG_DOUBLE_TYPE_SIZE 64
357 /* Define this as 1 if `char' should by default be signed; else as 0. */
358 #define DEFAULT_SIGNED_CHAR 0
360 /* Define these to avoid dependence on meaning of `int'.
361 Note that WCHAR_TYPE_SIZE is used in cexp.y,
362 where TARGET_SHORT is not available. */
363 #define WCHAR_TYPE "short int"
364 #define WCHAR_TYPE_SIZE 16
367 /* Standard register usage. */
369 #define HARD_REG_SIZE (UNITS_PER_WORD)
371 /* Assign names to real MC68HC11 registers.
372 A and B registers are not really used (A+B = D)
373 X register is first so that GCC allocates X+D for 32-bit integers and
374 the lowpart of that integer will be D. Having the lower part in D is
375 better for 32<->16bit conversions and for many arithmetic operations. */
376 #define HARD_X_REGNUM 0
377 #define HARD_D_REGNUM 1
378 #define HARD_Y_REGNUM 2
379 #define HARD_SP_REGNUM 3
380 #define HARD_PC_REGNUM 4
381 #define HARD_A_REGNUM 5
382 #define HARD_B_REGNUM 6
383 #define HARD_CCR_REGNUM 7
385 /* The Z register does not really exist in the 68HC11. This a fake register
386 for GCC. It is treated exactly as an index register (X or Y). It is only
387 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this
388 register helps the reload pass of GCC. Otherwise, the reload often aborts
389 with register spill failures.
391 The Z register is replaced by either X or Y during the machine specific
392 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register
393 when this is necessary.
395 It's possible to tell GCC not to use this register with -ffixed-z. */
396 #define HARD_Z_REGNUM 8
398 /* The frame pointer is a soft-register. It's treated as such by GCC:
399 it is not and must not be part of the BASE_REG_CLASS. */
400 #define DEFAULT_HARD_FP_REGNUM (9)
401 #define HARD_FP_REGNUM (9)
402 #define HARD_AP_REGNUM (HARD_FP_REGNUM)
404 /* Temporary soft-register used in some cases when an operand came
405 up into a bad register class (D, X, Y, SP) and gcc failed to
406 recognize this. This register is never allocated by GCC. */
407 #define SOFT_TMP_REGNUM 10
409 /* The soft-register which is used to save the Z register
410 (see Z register replacement notes in m68hc11.c). */
411 #define SOFT_Z_REGNUM 11
413 /* The soft-register which is used to save either X or Y. */
414 #define SOFT_SAVED_XY_REGNUM 12
416 /* A fake clobber register for 68HC12 patterns. */
417 #define FAKE_CLOBBER_REGNUM (13)
419 /* Define 32 soft-registers of 16-bit each. By default,
420 only 12 of them are enabled and can be used by GCC. The
421 -msoft-reg-count=<n> option allows to control the number of valid
422 soft-registers. GCC can put 32-bit values in them
423 by allocating consecutive registers. The first 3 soft-registers
424 are never allocated by GCC. They are used in case the insn template needs
425 a temporary register, or for the Z register replacement. */
427 #define MAX_SOFT_REG_COUNT (32)
428 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \
429 0, 0, 0, 0, 1, 1, 1, 1, \
430 1, 1, 1, 1, 1, 1, 1, 1, \
431 1, 1, 1, 1, 1, 1, 1, 1
432 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \
433 0, 0, 0, 0, 1, 1, 1, 1, \
434 1, 1, 1, 1, 1, 1, 1, 1, \
435 1, 1, 1, 1, 1, 1, 1, 1
436 #define SOFT_REG_ORDER \
437 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\
438 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\
439 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\
440 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\
441 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\
442 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\
443 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\
444 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31
446 #define SOFT_REG_NAMES \
447 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \
448 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \
449 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \
450 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \
451 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \
452 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \
453 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \
454 "*_.d29", "*_.d30", "*_.d31", "*_.d32"
456 /* First available soft-register for GCC. */
457 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2)
459 /* Last available soft-register for GCC. */
460 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)
461 #define SOFT_FP_REGNUM (SOFT_REG_LAST)
462 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1)
464 /* Number of actual hardware registers. The hardware registers are assigned
465 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER.
466 All registers that the compiler knows about must be given numbers, even
467 those that are not normally considered general registers. */
468 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2)
470 /* 1 for registers that have pervasive standard uses and are not available
471 for the register allocator. */
472 #define FIXED_REGISTERS \
473 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1}
474 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */
476 /* 1 for registers not available across function calls. For our pseudo
477 registers, all are available. */
478 #define CALL_USED_REGISTERS \
479 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1}
480 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */
483 /* Define this macro to change register usage conditional on target flags.
485 The soft-registers are disabled or enabled according to the
486 -msoft-reg-count=<n> option. */
489 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())
491 /* List the order in which to allocate registers. Each register must be
492 listed once, even those in FIXED_REGISTERS. */
493 #define REG_ALLOC_ORDER \
494 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \
495 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \
496 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \
497 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \
498 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM }
500 /* A C expression for the number of consecutive hard registers,
501 starting at register number REGNO, required to hold a value of
503 #define HARD_REGNO_NREGS(REGNO, MODE) \
504 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \
505 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))
507 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
508 - 8 bit values are stored anywhere (except the SP register).
509 - 16 bit values can be stored in any register whose mode is 16
510 - 32 bit values can be stored in D, X registers or in a soft register
511 (except the last one because we need 2 soft registers)
512 - Values whose size is > 32 bit are not stored in real hard
513 registers. They may be stored in soft registers if there are
515 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
516 hard_regno_mode_ok (REGNO,MODE)
518 /* Value is 1 if it is a good idea to tie two pseudo registers when one has
519 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce
520 different values for MODE1 and MODE2, for any hard reg, then this must be
521 0 for correct output.
523 All modes are tieable except QImode. */
524 #define MODES_TIEABLE_P(MODE1, MODE2) \
525 (((MODE1) == (MODE2)) \
526 || ((MODE1) != QImode && (MODE2) != QImode))
529 /* Define the classes of registers for register constraints in the
530 machine description. Also define ranges of constants.
532 One of the classes must always be named ALL_REGS and include all hard regs.
533 If there is more than one class, another class must be named NO_REGS
534 and contain no registers.
536 The name GENERAL_REGS must be the name of a class (or an alias for
537 another name such as ALL_REGS). This is the class of registers
538 that is allowed by "g" or "r" in a register constraint.
539 Also, registers outside this class are allocated only when
540 instructions express preferences for them.
542 The classes must be numbered in nondecreasing order; that is,
543 a larger-numbered class must never be contained completely
544 in a smaller-numbered class.
546 For any two classes, it is very desirable that there be another
547 class that represents their union. */
549 /* The M68hc11 has so fiew registers that it's not possible for GCC to
550 do any register allocation without breaking. We extend the processor
551 registers by having soft registers. These registers are treated as
552 hard registers by GCC but they are located in memory and accessed by page0
553 accesses (IND mode). */
557 D_REGS
, /* 16-bit data register */
558 X_REGS
, /* 16-bit X register */
559 Y_REGS
, /* 16-bit Y register */
560 SP_REGS
, /* 16 bit stack pointer */
561 DA_REGS
, /* 8-bit A reg. */
562 DB_REGS
, /* 8-bit B reg. */
563 Z_REGS
, /* 16-bit fake Z register */
564 D8_REGS
, /* 8-bit A or B reg. */
565 Q_REGS
, /* 8-bit (byte (QI)) data (A, B or D) */
566 D_OR_X_REGS
, /* D or X register */
567 D_OR_Y_REGS
, /* D or Y register */
568 D_OR_SP_REGS
, /* D or SP register */
569 X_OR_Y_REGS
, /* IX or Y register */
570 A_REGS
, /* 16-bit address register (X, Y, Z) */
571 X_OR_SP_REGS
, /* X or SP register */
572 Y_OR_SP_REGS
, /* Y or SP register */
573 X_OR_Y_OR_D_REGS
, /* X, Y or D */
574 A_OR_D_REGS
, /* X, Y, Z or D */
575 A_OR_SP_REGS
, /* X, Y, Z or SP */
576 H_REGS
, /* 16-bit hard register (D, X, Y, Z, SP) */
577 S_REGS
, /* 16-bit soft register */
578 D_OR_S_REGS
, /* 16-bit soft register or D register */
579 X_OR_S_REGS
, /* 16-bit soft register or X register */
580 Y_OR_S_REGS
, /* 16-bit soft register or Y register */
581 Z_OR_S_REGS
, /* 16-bit soft register or Z register */
582 SP_OR_S_REGS
, /* 16-bit soft register or SP register */
583 D_OR_X_OR_S_REGS
, /* 16-bit soft register or D or X register */
584 D_OR_Y_OR_S_REGS
, /* 16-bit soft register or D or Y register */
585 D_OR_SP_OR_S_REGS
, /* 16-bit soft register or D or SP register */
586 A_OR_S_REGS
, /* 16-bit soft register or X, Y registers */
587 D_OR_A_OR_S_REGS
, /* 16-bit soft register or D, X, Y registers */
588 TMP_REGS
, /* 16 bit fake scratch register */
589 D_OR_A_OR_TMP_REGS
, /* General scratch register */
590 G_REGS
, /* 16-bit general register
591 (H_REGS + soft registers) */
596 /* alias GENERAL_REGS to G_REGS. */
597 #define GENERAL_REGS G_REGS
599 #define N_REG_CLASSES (int) LIM_REG_CLASSES
601 /* Give names of register classes as strings for dump file. */
602 #define REG_CLASS_NAMES \
620 "X_OR_Y_OR_D_REGS", \
630 "D_OR_X_OR_S_REGS", \
631 "D_OR_Y_OR_S_REGS", \
632 "D_OR_SP_OR_S_REGS", \
634 "D_OR_A_OR_S_REGS", \
636 "D_OR_A_OR_TMP_REGS", \
640 /* An initializer containing the contents of the register classes,
641 as integers which are bit masks. The Nth integer specifies the
642 contents of class N. The way the integer MASK is interpreted is
643 that register R is in the class if `MASK & (1 << R)' is 1. */
645 /*--------------------------------------------------------------
660 Di 0xFFFFc000, 0x03FFF
661 SFRAME 0x00000000, 0x04000
662 AP 0x00000000, 0x08000
664 D_OR_X_REGS represents D+X. It is used for 32-bits numbers.
665 A_REGS represents a valid base register for indexing. It represents
666 X,Y and the Z register.
667 S_REGS represents the soft-registers. This includes the hard frame
668 and soft frame registers.
669 --------------------------------------------------------------*/
671 #define REG_CLASS_CONTENTS \
672 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \
673 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \
674 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \
675 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \
676 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \
677 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \
678 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \
679 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \
680 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \
681 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \
682 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \
683 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \
684 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \
685 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \
686 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \
687 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \
688 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \
689 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \
690 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \
691 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \
692 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \
693 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \
694 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \
695 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \
696 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \
697 /* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \
698 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \
699 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \
700 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \
701 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \
702 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \
703 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \
704 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \
705 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \
706 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \
707 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }}
710 /* set up a C expression whose value is a register class containing hard
712 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \
713 || (REGNO) == HARD_B_REGNUM)
714 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X)))
716 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM)
717 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
719 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM)
720 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X)))
721 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM)
722 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X)))
724 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM)
725 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X)))
727 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM)
728 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X)))
730 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
731 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
733 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM)
734 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X)))
736 /* Address register. */
737 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \
738 || (REGNO) == HARD_Y_REGNUM \
739 || (REGNO) == HARD_Z_REGNUM)
740 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
742 /* M68hc11 hard registers. */
743 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \
744 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO))
745 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X)))
747 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM)
748 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X)))
750 /* Soft registers (or register emulation for gcc). The temporary register
751 used by insn template must be part of the S_REGS class so that it
752 matches the 'u' constraint. */
753 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \
754 && (REGNO) <= SOFT_REG_LAST \
755 && (REGNO) != FAKE_CLOBBER_REGNUM)
756 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
758 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
759 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
761 /* General register. */
762 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \
763 || ((REGNO) == HARD_PC_REGNUM) \
764 || ((REGNO) == HARD_FP_REGNUM) \
765 || ((REGNO) == SOFT_FP_REGNUM) \
766 || ((REGNO) == FAKE_CLOBBER_REGNUM) \
767 || ((REGNO) == SOFT_AP_REGNUM))
769 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X)))
771 #define REGNO_REG_CLASS(REGNO) \
772 (D_REGNO_P (REGNO) ? D_REGS : \
773 (X_REGNO_P (REGNO) ? X_REGS : \
774 (Y_REGNO_P (REGNO) ? Y_REGS : \
775 (SP_REGNO_P (REGNO) ? SP_REGS : \
776 (Z_REGNO_P (REGNO) ? Z_REGS : \
777 (H_REGNO_P (REGNO) ? H_REGS : \
778 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \
779 (S_REGNO_P (REGNO) ? S_REGS : \
780 (DA_REGNO_P (REGNO) ? DA_REGS: \
781 (DB_REGNO_P (REGNO) ? DB_REGS: \
782 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS)))))))))))
785 /* Get reg_class from a letter in the machine description. */
787 extern enum reg_class m68hc11_tmp_regs_class
;
788 #define REG_CLASS_FROM_LETTER(C) \
789 ((C) == 'a' ? DA_REGS : \
790 (C) == 'A' ? A_REGS : \
791 (C) == 'b' ? DB_REGS : \
792 (C) == 'B' ? X_OR_Y_REGS : \
793 (C) == 'd' ? D_REGS : \
794 (C) == 'D' ? D_OR_X_REGS : \
795 (C) == 'q' ? Q_REGS : \
796 (C) == 'h' ? H_REGS : \
797 (C) == 't' ? TMP_REGS : \
798 (C) == 'u' ? S_REGS : \
799 (C) == 'v' ? m68hc11_tmp_regs_class : \
800 (C) == 'w' ? SP_REGS : \
801 (C) == 'x' ? X_REGS : \
802 (C) == 'y' ? Y_REGS : \
803 (C) == 'z' ? Z_REGS : NO_REGS)
805 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS)
807 #define SMALL_REGISTER_CLASSES 1
809 /* A C expression that is nonzero if hard register number REGNO2 can be
810 considered for use as a rename register for REGNO1 */
812 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
813 m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2))
815 /* A C expression whose value is nonzero if pseudos that have been
816 assigned to registers of class CLASS would likely be spilled
817 because registers of CLASS are needed for spill registers.
819 The default value of this macro returns 1 if CLASS has exactly one
820 register and zero otherwise. On most machines, this default
821 should be used. Only define this macro to some other expression
822 if pseudo allocated by `local-alloc.c' end up in memory because
823 their hard registers were needed for spill registers. If this
824 macro returns nonzero for those classes, those pseudos will only
825 be allocated by `global.c', which knows how to reallocate the
826 pseudo to another register. If there would not be another
827 register available for reallocation, you should not change the
828 definition of this macro since the only effect of such a
829 definition would be to slow down register allocation. */
831 #define CLASS_LIKELY_SPILLED_P(CLASS) \
832 (((CLASS) == D_REGS) \
833 || ((CLASS) == X_REGS) \
834 || ((CLASS) == Y_REGS) \
835 || ((CLASS) == A_REGS) \
836 || ((CLASS) == SP_REGS) \
837 || ((CLASS) == D_OR_X_REGS) \
838 || ((CLASS) == D_OR_Y_REGS) \
839 || ((CLASS) == X_OR_SP_REGS) \
840 || ((CLASS) == Y_OR_SP_REGS) \
841 || ((CLASS) == D_OR_SP_REGS))
843 /* Return the maximum number of consecutive registers needed to represent
844 mode MODE in a register of class CLASS. */
845 #define CLASS_MAX_NREGS(CLASS, MODE) \
846 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \
847 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \
848 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
850 /* The letters I, J, K, L and M in a register constraint string
851 can be used to stand for particular ranges of immediate operands.
852 This macro defines what the ranges are.
853 C is the letter, and VALUE is a constant value.
854 Return 1 if VALUE is in the range specified by C.
857 `L' is for range -65536 to 65536
858 `M' is for values whose 16-bit low part is 0
860 'O' is for 16 (for rotate using swap).
861 'P' is for range -8 to 2 (used by addhi_sp)
863 'I', 'J' are not used. */
865 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
866 ((C) == 'K' ? (VALUE) == 0 : \
867 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \
868 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \
869 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \
870 (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \
871 (C) == 'O' ? (VALUE) == 16 : \
872 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0)
874 /* Similar, but for floating constants, and defining letters G and H.
877 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
878 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
879 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0)
881 /* 'U' represents certain kind of memory indexed operand for 68HC12.
882 and any memory operand for 68HC11.
883 'R' represents indexed addressing mode or access to page0 for 68HC11.
884 For 68HC12, it represents any memory operand. */
885 #define EXTRA_CONSTRAINT(OP, C) \
886 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \
887 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \
888 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \
889 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \
890 && non_push_operand (OP, GET_MODE (OP))) : 0)
893 /* Stack layout; function entry, exit and calling. */
895 /* Define this if pushing a word on the stack
896 makes the stack pointer a smaller address. */
897 #define STACK_GROWS_DOWNWARD
899 /* Define this if the nominal address of the stack frame
900 is at the high-address end of the local variables;
901 that is, each additional local variable allocated
902 goes at a more negative offset in the frame.
904 Don't define for 68HC11, the frame pointer is the bottom
905 of local variables. */
906 /* #define FRAME_GROWS_DOWNWARD */
908 /* Define this if successive arguments to a function occupy decreasing
909 addresses in the stack. */
910 /* #define ARGS_GROW_DOWNWARD */
912 /* Offset within stack frame to start allocating local variables at.
913 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
914 first local allocated. Otherwise, it is the offset to the BEGINNING
915 of the first local allocated. */
916 #define STARTING_FRAME_OFFSET 0
918 /* Offset of first parameter from the argument pointer register value. */
920 #define FIRST_PARM_OFFSET(FNDECL) 2
922 /* After the prologue, RA is at 0(AP) in the current frame. */
923 #define RETURN_ADDR_RTX(COUNT, FRAME) \
925 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
928 /* Before the prologue, the top of the frame is at 2(sp). */
929 #define INCOMING_FRAME_SP_OFFSET 2
931 /* Define this if functions should assume that stack space has been
932 allocated for arguments even when their values are passed in
935 The value of this macro is the size, in bytes, of the area reserved for
936 arguments passed in registers.
938 This space can either be allocated by the caller or be a part of the
939 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
941 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */
943 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack
944 parameters don't skip the area specified by REG_PARM_STACK_SPACE.
945 Normally, when a parameter is not passed in registers, it is placed on
946 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro
947 suppresses this behavior and causes the parameter to be passed on the
948 stack in its natural location. */
949 /* #define STACK_PARMS_IN_REG_PARM_AREA */
951 /* Register to use for pushing function arguments. */
952 #define STACK_POINTER_REGNUM HARD_SP_REGNUM
954 /* Base register for access to local variables of the function. */
955 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM
957 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM
959 /* Base register for access to arguments of the function. */
960 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM
962 /* Register in which static-chain is passed to a function. */
963 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM
966 /* Definitions for register eliminations.
968 This is an array of structures. Each structure initializes one pair
969 of eliminable registers. The "from" register number is given first,
970 followed by "to". Eliminations of the same "from" register are listed
971 in order of preference.
973 We have two registers that are eliminated on the 6811. The pseudo arg
974 pointer and pseudo frame pointer registers can always be eliminated;
975 they are replaced with either the stack or the real frame pointer. */
977 #define ELIMINABLE_REGS \
978 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
979 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
980 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
981 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
983 /* Value should be nonzero if functions must have frame pointers.
984 Zero means the frame pointer need not be set up (and parms may be
985 accessed via the stack pointer) in functions that seem suitable.
986 This is computed in `reload', in reload1.c. */
987 #define FRAME_POINTER_REQUIRED 0
989 /* Given FROM and TO register numbers, say whether this elimination is allowed.
990 Frame pointer elimination is automatically handled.
992 All other eliminations are valid. */
994 #define CAN_ELIMINATE(FROM, TO) \
995 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
996 ? ! frame_pointer_needed \
1000 /* Define the offset between two registers, one to be eliminated, and the other
1001 its replacement, at the start of a routine. */
1003 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1004 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); }
1007 /* Passing Function Arguments on the Stack. */
1009 /* If we generate an insn to push BYTES bytes, this says how many the
1010 stack pointer really advances by. No rounding or alignment needed
1012 #define PUSH_ROUNDING(BYTES) (BYTES)
1014 /* Value is 1 if returning from a function call automatically pops the
1015 arguments described by the number-of-args field in the call. FUNTYPE is
1016 the data type of the function (as a tree), or for a library call it is
1017 an identifier node for the subroutine name.
1019 The standard MC6811 call, with arg count word, includes popping the
1020 args as part of the call template. */
1021 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1023 /* Passing Arguments in Registers. */
1025 /* Define a data type for recording info about an argument list
1026 during the scan of that argument list. This data type should
1027 hold all necessary information about the function itself
1028 and about the args processed so far, enough to enable macros
1029 such as FUNCTION_ARG to determine where the next arg should go. */
1031 typedef struct m68hc11_args
1037 /* A C expression that indicates when an argument must be passed by reference.
1038 If nonzero for an argument, a copy of that argument is made in memory and a
1039 pointer to the argument is passed instead of the argument itself.
1040 The pointer is passed in whatever way is appropriate for passing a pointer
1043 64-bit numbers are passed by reference. */
1044 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1045 m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1048 /* If defined, a C expression which determines whether, and in which direction,
1049 to pad out an argument with extra space. The value should be of type
1050 `enum direction': either `upward' to pad above the argument,
1051 `downward' to pad below, or `none' to inhibit padding.
1053 Structures are stored left shifted in their argument slot. */
1054 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1055 m68hc11_function_arg_padding ((MODE), (TYPE))
1057 #undef PAD_VARARGS_DOWN
1058 #define PAD_VARARGS_DOWN \
1059 (m68hc11_function_arg_padding (TYPE_MODE (type), type) == downward)
1061 /* A C expression that indicates when it is the called function's
1062 responsibility to make a copy of arguments passed by invisible
1063 reference. Normally, the caller makes a copy and passes the
1064 address of the copy to the routine being called. When
1065 FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
1066 does not make a copy. Instead, it passes a pointer to the "live"
1067 value. The called function must not modify this value. If it can
1068 be determined that the value won't be modified, it need not make a
1069 copy; otherwise a copy must be made. */
1070 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1071 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
1073 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
1074 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */
1075 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1076 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1078 /* Update the data in CUM to advance over an argument of mode MODE and data
1079 type TYPE. (TYPE is null for libcalls where that information may not be
1081 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1082 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1084 /* Define where to put the arguments to a function.
1085 Value is zero to push the argument on the stack,
1086 or a hard register in which to store the argument.
1088 MODE is the argument's machine mode.
1089 TYPE is the data type of the argument (as a tree).
1090 This is null for libcalls where that information may
1092 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1093 the preceding args and about the function being called.
1094 NAMED is nonzero if this argument is a named parameter
1095 (otherwise it is an extra parameter matching an ellipsis). */
1096 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1097 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED))
1099 /* Define the profitability of saving registers around calls.
1101 Disable this because the saving instructions generated by
1102 caller-save need a reload and the way it is implemented,
1103 it forbids all spill registers at that point. Enabling
1104 caller saving results in spill failure. */
1105 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1107 /* For an arg passed partly in registers and partly in memory,
1108 this is the number of registers used.
1109 For args passed entirely in registers or entirely in memory, zero.
1111 Passing an arg partly in register and memory does not work at all.
1113 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
1115 /* 1 if N is a possible register number for function argument passing.
1116 D is for 16-bit values, X is for 32-bit (X+D). */
1117 #define FUNCTION_ARG_REGNO_P(N) \
1118 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM))
1120 /* All return values are in the D or X+D registers:
1121 - 8 and 16-bit values are returned in D.
1122 BLKmode are passed in D as pointer.
1123 - 32-bit values are returned in X + D.
1124 The high part is passed in X and the low part in D.
1125 For GCC, the register number must be HARD_X_REGNUM. */
1126 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1127 gen_rtx_REG (TYPE_MODE (VALTYPE), \
1128 ((TYPE_MODE (VALTYPE) == BLKmode \
1129 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \
1130 ? HARD_D_REGNUM : HARD_X_REGNUM))
1132 #define LIBCALL_VALUE(MODE) \
1133 gen_rtx_REG (MODE, \
1134 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \
1135 ? HARD_D_REGNUM : HARD_X_REGNUM))
1137 /* 1 if N is a possible register number for a function value. */
1138 #define FUNCTION_VALUE_REGNO_P(N) \
1139 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM)
1141 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1142 the stack pointer does not matter. The value is tested only in functions
1143 that have frame pointers. No definition is equivalent to always zero. */
1144 #define EXIT_IGNORE_STACK 0
1147 /* Generating Code for Profiling. */
1149 /* Output assembler code to FILE to increment profiler label # LABELNO
1150 for profiling a function entry. */
1151 #define FUNCTION_PROFILER(FILE, LABELNO) \
1152 fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO))
1153 /* Length in units of the trampoline for entering a nested function. */
1154 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9)
1156 /* A C statement to initialize the variable parts of a trampoline.
1157 ADDR is an RTX for the address of the trampoline; FNADDR is an
1158 RTX for the address of the nested function; STATIC_CHAIN is an
1159 RTX for the static chain value that should be passed to the
1160 function when it is called. */
1161 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1162 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1165 /* Addressing modes, and classification of registers for them. */
1167 /* The 68HC12 has all the post/pre increment/decrement modes. */
1168 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1169 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1170 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1171 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1173 /* The class value for base registers. This depends on the target:
1174 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value
1175 is stored at init time. */
1176 extern enum reg_class m68hc11_base_reg_class
;
1177 #define BASE_REG_CLASS m68hc11_base_reg_class
1179 /* The class value for index registers. This is NO_REGS for 68HC11. */
1181 extern enum reg_class m68hc11_index_reg_class
;
1182 #define INDEX_REG_CLASS m68hc11_index_reg_class
1184 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero
1185 only if REGNO is a hard reg of the suitable class or a pseudo reg currently
1186 allocated to a suitable hard reg. Since they use reg_renumber, they are
1187 safe only once reg_renumber has been allocated, which happens in
1191 /* Internal macro, return 1 if REGNO is a valid base register. */
1192 #define REG_VALID_P(REGNO) (1) /* ? */
1194 extern unsigned char m68hc11_reg_valid_for_base
[FIRST_PSEUDO_REGISTER
];
1195 #define REG_VALID_FOR_BASE_P(REGNO) \
1196 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \
1197 && m68hc11_reg_valid_for_base[REGNO])
1199 /* Internal macro, return 1 if REGNO is a valid index register. */
1200 extern unsigned char m68hc11_reg_valid_for_index
[FIRST_PSEUDO_REGISTER
];
1201 #define REG_VALID_FOR_INDEX_P(REGNO) \
1202 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \
1203 && m68hc11_reg_valid_for_index[REGNO])
1205 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */
1206 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
1207 ((REGNO) >= FIRST_PSEUDO_REGISTER \
1208 || REG_VALID_FOR_BASE_P (REGNO) \
1209 || (REGNO) == FRAME_POINTER_REGNUM \
1210 || (REGNO) == HARD_FRAME_POINTER_REGNUM \
1211 || (REGNO) == ARG_POINTER_REGNUM \
1212 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1214 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */
1215 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
1217 && ((REGNO) >= FIRST_PSEUDO_REGISTER \
1218 || REG_VALID_FOR_INDEX_P (REGNO) \
1219 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1221 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */
1222 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \
1223 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \
1224 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1226 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */
1227 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \
1229 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \
1230 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1232 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \
1233 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \
1234 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO)))
1236 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \
1237 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \
1238 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO)))
1240 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO)
1241 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO)
1243 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X))
1244 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X))
1245 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X))
1246 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X))
1248 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */
1249 #define IS_STACK_PUSH(operand) \
1250 ((GET_CODE (operand) == MEM) \
1251 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \
1252 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1254 #define IS_STACK_POP(operand) \
1255 ((GET_CODE (operand) == MEM) \
1256 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \
1257 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1259 /* 1 if X is an rtx for a constant that is a valid address. */
1260 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1262 /* Maximum number of registers that can appear in a valid memory address */
1263 #define MAX_REGS_PER_ADDRESS 2
1265 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1266 valid memory address for an instruction. The MODE argument is the
1267 machine mode for the MEM expression that wants to use this address. */
1269 /*--------------------------------------------------------------
1270 Valid addresses are either direct or indirect (MEM) versions
1271 of the following forms:
1275 --------------------------------------------------------------*/
1277 /* The range of index that is allowed by indirect addressing. */
1279 #define VALID_MIN_OFFSET m68hc11_min_offset
1280 #define VALID_MAX_OFFSET m68hc11_max_offset
1282 /* The offset values which are allowed by the n,x and n,y addressing modes.
1283 Take into account the size of the mode because we may have to add
1284 a mode offset to access the lowest part of the data.
1285 (For example, for an SImode, the last valid offset is 252.) */
1286 #define VALID_CONSTANT_OFFSET_P(X,MODE) \
1287 (((GET_CODE (X) == CONST_INT) && \
1288 ((INTVAL (X) >= VALID_MIN_OFFSET) \
1289 && ((INTVAL (X) <= VALID_MAX_OFFSET \
1290 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \
1292 && ((GET_CODE (X) == SYMBOL_REF) \
1293 || GET_CODE (X) == LABEL_REF \
1294 || GET_CODE (X) == CONST)))
1296 /* This is included to allow stack push/pop operations. Special hacks in the
1297 md and m6811.c files exist to support this. */
1298 #define PUSH_POP_ADDRESS_P(X) \
1299 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \
1300 && SP_REG_P (XEXP (X, 0)))
1302 /* Go to ADDR if X is a valid address. */
1303 #ifndef REG_OK_STRICT
1304 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1306 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \
1309 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1311 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \
1315 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its
1316 validity for a certain class. We have two alternate definitions for each
1317 of them. The usual definition accepts all pseudo regs; the other rejects
1318 them unless they have been allocated suitable hard regs. The symbol
1319 REG_OK_STRICT causes the latter definition to be used.
1321 Most source files want to accept pseudo regs in the hope that they will
1322 get allocated to the class that the insn wants them to be in. Source files
1323 for reload pass need to be strict. After reload, it makes no difference,
1324 since pseudo regs have been eliminated by then. */
1326 #ifndef REG_OK_STRICT
1327 /* Nonzero if X is a hard reg that can be used as a base reg. */
1328 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1330 /* Nonzero if X is a hard reg that can be used as an index. */
1331 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1333 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1334 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1338 /* Try machine-dependent ways of modifying an illegitimate address
1339 to be legitimate. If we find one, return the new, valid address.
1340 This macro is used in only one place: `memory_address' in explow.c.
1342 OLDX is the address as it was before break_out_memory_refs was called.
1343 In some cases it is useful to look at this to decide what needs to be done.
1345 MODE and WIN are passed so that this macro can use
1346 GO_IF_LEGITIMATE_ADDRESS.
1348 It is always safe for this macro to do nothing.
1349 It exists to recognize opportunities to optimize the output. */
1351 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1352 { rtx operand = (X); \
1353 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \
1356 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \
1360 /* Go to LABEL if ADDR (a legitimate address expression)
1361 has an effect that depends on the machine mode it is used for. */
1362 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1364 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
1365 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
1369 /* Nonzero if the constant value X is a legitimate general operand.
1370 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1372 #define LEGITIMATE_CONSTANT_P(X) 1
1375 /* Tell final.c how to eliminate redundant test instructions. */
1377 #define NOTICE_UPDATE_CC(EXP, INSN) \
1378 m68hc11_notice_update_cc ((EXP), (INSN))
1380 /* Move costs between classes of registers */
1381 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1382 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2))
1384 /* Move cost between register and memory.
1385 - Move to a 16-bit register is reasonable,
1386 - Move to a soft register can be expensive. */
1387 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1388 m68hc11_memory_move_cost ((MODE),(CLASS),(IN))
1390 /* A C expression for the cost of a branch instruction. A value of 1
1391 is the default; other values are interpreted relative to that.
1393 Pretend branches are cheap because GCC generates sub-optimal code
1394 for the default value. */
1395 #define BRANCH_COST 0
1397 /* Nonzero if access to memory by bytes is slow and undesirable. */
1398 #define SLOW_BYTE_ACCESS 0
1400 /* It is as good to call a constant function address as to call an address
1401 kept in a register. */
1402 #define NO_FUNCTION_CSE
1404 /* Try a machine-dependent way of reloading an illegitimate address
1405 operand. If we find one, push the reload and jump to WIN. This
1406 macro is used in only one place: `find_reloads_address' in reload.c.
1408 For M68HC11, we handle large displacements of a base register
1409 by splitting the addend across an addhi3 insn.
1411 For M68HC12, the 64K offset range is available.
1414 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1416 /* We must recognize output that we have already generated ourselves. */ \
1417 if (GET_CODE (X) == PLUS \
1418 && GET_CODE (XEXP (X, 0)) == PLUS \
1419 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1420 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1421 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1423 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1424 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1428 if (GET_CODE (X) == PLUS \
1429 && GET_CODE (XEXP (X, 0)) == REG \
1430 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1431 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \
1433 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1434 HOST_WIDE_INT low, high; \
1435 high = val & (~0x0FF); \
1436 low = val & 0x00FF; \
1437 if (low >= 256-15) { high += 16; low -= 16; } \
1438 /* Reload the high part into a base reg; leave the low part \
1439 in the mem directly. */ \
1441 X = gen_rtx_PLUS (Pmode, \
1442 gen_rtx_PLUS (Pmode, XEXP (X, 0), \
1446 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1447 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1454 /* Defining the Output Assembler Language. */
1456 /* A default list of other sections which we might be "in" at any given
1457 time. For targets that use additional sections (e.g. .tdesc) you
1458 should override this definition in the target-specific file which
1459 includes this file. */
1461 /* Output before read-only data. */
1462 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text")
1464 /* Output before writable data. */
1465 #define DATA_SECTION_ASM_OP ("\t.sect\t.data")
1467 /* Output before uninitialized data. */
1468 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss")
1470 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
1472 Same as config/elfos.h but don't mark these section SHF_WRITE since
1473 there is no shared library problem. */
1474 #undef CTORS_SECTION_ASM_OP
1475 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
1477 #undef DTORS_SECTION_ASM_OP
1478 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
1480 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor
1481 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor
1483 /* Comment character */
1484 #define ASM_COMMENT_START ";"
1486 /* Output to assembler file text saying following lines
1487 may contain character constants, extra white space, comments, etc. */
1488 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n"
1490 /* Output to assembler file text saying following lines
1491 no longer contain unusual constructs. */
1492 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n"
1494 /* Write the extra assembler code needed to declare a function properly.
1495 Some svr4 assemblers need to also have something extra said about the
1496 function's return value. We allow for that here.
1498 For 68HC12 we mark functions that return with 'rtc'. The linker
1499 will ensure that a 'call' is really made (instead of 'jsr').
1500 The debugger needs this information to correctly compute the stack frame.
1502 For 68HC11/68HC12 we also mark interrupt handlers for gdb to
1503 compute the correct stack frame. */
1505 #undef ASM_DECLARE_FUNCTION_NAME
1506 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1509 fprintf (FILE, "%s", TYPE_ASM_OP); \
1510 assemble_name (FILE, NAME); \
1512 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \
1513 putc ('\n', FILE); \
1515 if (current_function_far) \
1517 fprintf (FILE, "\t.far\t"); \
1518 assemble_name (FILE, NAME); \
1519 putc ('\n', FILE); \
1521 else if (current_function_interrupt \
1522 || current_function_trap) \
1524 fprintf (FILE, "\t.interrupt\t"); \
1525 assemble_name (FILE, NAME); \
1526 putc ('\n', FILE); \
1528 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1529 ASM_OUTPUT_LABEL(FILE, NAME); \
1533 /* Output #ident as a .ident. */
1535 /* output external reference */
1536 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \
1537 {fputs ("\t; extern\t", FILE); \
1538 assemble_name (FILE, NAME); \
1539 fputs ("\n", FILE);}
1541 /* How to refer to registers in assembler output. This sequence is indexed
1542 by compiler's hard-register-number (see above). */
1543 #define REGISTER_NAMES \
1544 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \
1545 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \
1546 SOFT_REG_NAMES, "*sframe", "*ap"}
1548 /* Print an instruction operand X on file FILE. CODE is the code from the
1549 %-spec for printing this operand. If `%z3' was used to print operand
1550 3, then CODE is 'z'. */
1552 #define PRINT_OPERAND(FILE, X, CODE) \
1553 print_operand (FILE, X, CODE)
1555 /* Print a memory operand whose address is X, on file FILE. */
1556 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1557 print_operand_address (FILE, ADDR)
1559 /* This is how to output an insn to push/pop a register on the stack.
1560 It need not be very fast code.
1562 Don't define because we don't know how to handle that with
1563 the STATIC_CHAIN_REGNUM (soft register). Saving the static
1564 chain must be made inside FUNCTION_PROFILER. */
1566 #undef ASM_OUTPUT_REG_PUSH
1567 #undef ASM_OUTPUT_REG_POP
1569 /* This is how to output an element of a case-vector that is relative. */
1571 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1572 fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL)
1574 /* This is how to output an element of a case-vector that is absolute. */
1575 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1576 fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE)
1578 /* This is how to output an assembler line that says to advance the
1579 location counter to a multiple of 2**LOG bytes. */
1580 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1583 fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \
1587 /* Assembler Commands for Exception Regions. */
1589 /* Default values provided by GCC should be ok. Assuming that DWARF-2
1590 frame unwind info is ok for this platform. */
1592 #undef PREFERRED_DEBUGGING_TYPE
1593 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1595 /* For the support of memory banks we need addresses that indicate
1597 #define DWARF2_ADDR_SIZE 4
1599 /* SCz 2003-07-08: Don't use as dwarf2 .file/.loc directives because
1600 the linker is doing relaxation and it does not adjust the debug_line
1601 sections when it shrinks the code. This results in invalid addresses
1602 when debugging. This does not bless too much the HC11/HC12 as most
1603 applications are embedded and small, hence a reasonable debug info.
1604 This problem is known for binutils 2.13, 2.14 and mainline. */
1605 #undef HAVE_AS_DWARF2_DEBUG_LINE
1607 /* The prefix for local labels. You should be able to define this as
1608 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1609 without having to make any other changes to account for the specific
1610 definition. Note it is a string literal, not interpreted by printf
1612 #define LOCAL_LABEL_PREFIX "."
1614 /* The prefix for immediate operands. */
1615 #define IMMEDIATE_PREFIX "#"
1616 #define GLOBAL_ASM_OP "\t.globl\t"
1619 /* Miscellaneous Parameters. */
1621 /* Define the codes that are matched by predicates in m68hc11.c. */
1622 #define PREDICATE_CODES \
1623 {"stack_register_operand", {SUBREG, REG}}, \
1624 {"d_register_operand", {SUBREG, REG}}, \
1625 {"hard_addr_reg_operand", {SUBREG, REG}}, \
1626 {"hard_reg_operand", {SUBREG, REG}}, \
1627 {"m68hc11_logical_operator", {AND, IOR, XOR}}, \
1628 {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \
1629 ASHIFT, ASHIFTRT, LSHIFTRT, \
1630 ROTATE, ROTATERT }}, \
1631 {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \
1632 {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \
1633 {"m68hc11_shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT}},\
1634 {"m68hc11_eq_compare_operator", {EQ, NE}}, \
1635 {"non_push_operand", {SUBREG, REG, MEM}}, \
1636 {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \
1637 {"tst_operand", {SUBREG, REG, MEM}}, \
1638 {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \
1639 CONST_INT, CONST_DOUBLE}},
1641 /* Specify the machine mode that this machine uses
1642 for the index in the tablejump instruction. */
1643 #define CASE_VECTOR_MODE Pmode
1645 /* This flag, if defined, says the same insns that convert to a signed fixnum
1646 also convert validly to an unsigned one. */
1647 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1649 /* Max number of bytes we can move from memory to memory in one
1650 reasonably fast instruction. */
1653 /* MOVE_RATIO is the number of move instructions that is better than a
1654 block move. Make this small on 6811, since the code size grows very
1655 large with each move. */
1656 #define MOVE_RATIO 3
1658 /* Define if shifts truncate the shift count which implies one can omit
1659 a sign-extension or zero-extension of a shift count. */
1660 #define SHIFT_COUNT_TRUNCATED 1
1662 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1663 is done just by pretending it is already truncated. */
1664 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1666 /* Specify the machine mode that pointers have. After generation of rtl, the
1667 compiler makes no further distinction between pointers and any other
1668 objects of this machine mode. */
1669 #define Pmode HImode
1671 /* A function address in a call instruction is a byte address (for indexing
1672 purposes) so give the MEM rtx a byte's mode. */
1673 #define FUNCTION_MODE QImode
1675 extern int debug_m6811
;
1676 extern int z_replacement_completed
;
1677 extern int current_function_interrupt
;
1678 extern int current_function_trap
;
1679 extern int current_function_far
;
1681 extern GTY(()) rtx m68hc11_compare_op0
;
1682 extern GTY(()) rtx m68hc11_compare_op1
;
1683 extern GTY(()) rtx m68hc11_soft_tmp_reg
;
1684 extern GTY(()) rtx ix_reg
;
1685 extern GTY(()) rtx iy_reg
;
1686 extern GTY(()) rtx d_reg
;