1 /* Definitions of target machine for GNU compiler.
2 Motorola 68HC11 and 68HC12.
3 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA.
24 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
25 on gcc 2.6.3. I have used it as a starting point for this port.
26 However, this new port is a complete re-write. Its internal
27 design is completely different. The generated code is not
28 compatible with the gcc 2.6.3 port.
30 The gcc 2.6.3 port is available at:
32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
36 /*****************************************************************************
38 ** Controlling the Compilation Driver, `gcc'
40 *****************************************************************************/
44 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */
46 #define ASM_SPEC "%{m68hc12:-m68hc12}%{!m68hc12:-m68hc11}"
49 /* We need to tell the linker the target elf format. Just pass an
50 emulation option. This can be overriden by -Wl option of gcc. */
52 #define LINK_SPEC "%{m68hc12:-m m68hc12elf}%{!m68hc12:-m m68hc11elf}"
65 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\
66 %{!mshort:-D__INT__=32}\
67 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\
68 %{!m68hc12:-Dmc6811 -DMC6811 -Dmc68hc11}\
69 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\
70 %{mlong-calls:-D__USE_RTC__}"
74 #define STARTFILE_SPEC "crt1%O%s"
76 /* Names to predefine in the preprocessor for this target machine. */
77 #define CPP_PREDEFINES "-Dmc68hc1x"
79 /* As an embedded target, we have no libc. */
82 /* Forward type declaration for prototypes definitions.
83 rtx_ptr is equivalent to rtx. Can't use the same name. */
85 typedef struct rtx_def
*rtx_ptr
;
88 typedef union tree_node
*tree_ptr
;
90 /* We can't declare enum machine_mode forward nor include 'machmode.h' here.
91 Prototypes defined here will use an int instead. It's better than no
93 typedef int enum_machine_mode
;
95 /*****************************************************************************
97 ** Run-time Target Specification
99 *****************************************************************************/
101 /* Run-time compilation parameters selecting different hardware subsets. */
103 extern int target_flags
;
105 extern short *reg_renumber
; /* def in local_alloc.c */
107 /* Macros used in the machine description to test the flags. */
109 /* 6811 specific options
111 * For 68HC12, the auto inc/dec mode is disabled by default. The reason
112 * is that for most programs, the reload pass will fail because it needs
113 * more registers to save the value of the indexed register after the
114 * memory access. For simple programs, you can enable this
115 * with -mauto-incdec.
118 #define MASK_SHORT 0002 /* Compile with 16-bit `int' */
119 #define MASK_AUTO_INC_DEC 0004
120 #define MASK_M6811 0010
121 #define MASK_M6812 0020
122 #define MASK_NO_DIRECT_MODE 0040
123 #define MASK_MIN_MAX 0100
124 #define MASK_LONG_CALLS 0200
126 #define TARGET_OP_TIME (optimize && optimize_size == 0)
127 #define TARGET_SHORT (target_flags & MASK_SHORT)
128 #define TARGET_M6811 (target_flags & MASK_M6811)
129 #define TARGET_M6812 (target_flags & MASK_M6812)
130 #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC)
131 #define TARGET_MIN_MAX (target_flags & MASK_MIN_MAX)
132 #define TARGET_NO_DIRECT_MODE (target_flags & MASK_NO_DIRECT_MODE)
133 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE)
134 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
136 /* Default target_flags if no switches specified. */
137 #ifndef TARGET_DEFAULT
138 # define TARGET_DEFAULT (MASK_M6811)
141 /* Define this macro as a C expression for the initializer of an
142 array of string to tell the driver program which options are
143 defaults for this target and thus do not need to be handled
144 specially when using `MULTILIB_OPTIONS'. */
145 #ifndef MULTILIB_DEFAULTS
146 # if TARGET_DEFAULT & MASK_M6811
147 # define MULTILIB_DEFAULTS { "m68hc11" }
149 # define MULTILIB_DEFAULTS { "m68hc12" }
153 /* Macro to define tables used to set the flags. This is a list in braces of
154 pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits
155 to set or minus the bits to clear. An empty string NAME is used to
156 identify the default VALUE. */
158 #define TARGET_SWITCHES \
159 { { "short", MASK_SHORT, \
160 N_("Compile with 16-bit integer mode")}, \
161 { "noshort", - MASK_SHORT, \
162 N_("Compile with 32-bit integer mode")}, \
163 { "auto-incdec", MASK_AUTO_INC_DEC, \
164 N_("Auto pre/post decrement increment allowed")}, \
165 { "noauto-incdec", - MASK_AUTO_INC_DEC, \
166 N_("Auto pre/post decrement increment not allowed")}, \
167 { "inmax", MASK_MIN_MAX, \
168 N_("Min/max instructions allowed")}, \
169 { "nominmax", MASK_MIN_MAX, \
170 N_("Min/max instructions not allowed")}, \
171 { "long-calls", MASK_LONG_CALLS, \
172 N_("Use call and rtc for function calls and returns")}, \
173 { "nolong-calls", - MASK_LONG_CALLS, \
174 N_("Use jsr and rts for function calls and returns")}, \
175 { "relax", MASK_NO_DIRECT_MODE, \
176 N_("Do not use direct addressing mode for soft registers")},\
177 { "68hc11", MASK_M6811, \
178 N_("Compile for a 68HC11")}, \
179 { "68hc12", MASK_M6812, \
180 N_("Compile for a 68HC12")}, \
181 { "6811", MASK_M6811, \
182 N_("Compile for a 68HC11")}, \
183 { "6812", MASK_M6812, \
184 N_("Compile for a 68HC12")}, \
185 { "", TARGET_DEFAULT, 0 }}
187 /* This macro is similar to `TARGET_SWITCHES' but defines names of
188 command options that have values. Its definition is an
189 initializer with a subgrouping for each command option.
191 Each subgrouping contains a string constant, that defines the
192 fixed part of the option name, and the address of a variable. The
193 variable, type `char *', is set to the variable part of the given
194 option if the fixed part matches. The actual option name is made
195 by appending `-m' to the specified name. */
196 #define TARGET_OPTIONS \
197 { { "reg-alloc=", &m68hc11_reg_alloc_order, \
198 N_("Specify the register allocation order")}, \
199 { "soft-reg-count=", &m68hc11_soft_reg_count, \
200 N_("Indicate the number of soft registers available") }, \
204 /* These are meant to be redefined in the host dependent files */
205 #define SUBTARGET_SWITCHES
206 #define SUBTARGET_OPTIONS
208 extern const char *m68hc11_regparm_string
;
209 extern const char *m68hc11_reg_alloc_order
;
210 extern const char *m68hc11_soft_reg_count
;
212 #ifndef TARGET_M68HC12
213 # define TARGET_M68HC11 1
216 /* Print subsidiary information on the compiler version in use. */
217 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12)")
219 /* Sometimes certain combinations of command options do not make
220 sense on a particular target machine. You can define a macro
221 `OVERRIDE_OPTIONS' to take account of this. This macro, if
222 defined, is executed once just after all the command options have
225 Don't use this macro to turn on various extra optimizations for
226 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
228 #define OVERRIDE_OPTIONS m68hc11_override_options ();
231 /* Define cost parameters for a given processor variant. */
232 struct processor_costs
{
233 const int add
; /* cost of an add instruction */
234 const int logical
; /* cost of a logical instruction */
236 const int shiftQI_const
[8];
237 const int shiftHI_const
[16];
246 /* Costs for the current processor. */
247 extern const struct processor_costs
*m68hc11_cost
;
250 /* target machine storage layout */
252 /* Define this if most significant byte of a word is the lowest numbered. */
253 #define BYTES_BIG_ENDIAN 1
255 /* Define this if most significant bit is lowest numbered
256 in instructions that operate on numbered bit-fields. */
257 #define BITS_BIG_ENDIAN 0
259 /* Define this if most significant word of a multiword number is numbered. */
260 #define WORDS_BIG_ENDIAN 1
262 /* Width of a word, in units (bytes). */
263 #define UNITS_PER_WORD 2
265 /* Definition of size_t. This is really an unsigned short as the
266 68hc11 only handles a 64K address space. */
267 #define SIZE_TYPE "short unsigned int"
269 /* A C expression for a string describing the name of the data type
270 to use for the result of subtracting two pointers. The typedef
271 name `ptrdiff_t' is defined using the contents of the string.
272 The 68hc11 only has a 64K address space. */
273 #define PTRDIFF_TYPE "short int"
275 /* Allocation boundary (bits) for storing pointers in memory. */
276 #define POINTER_BOUNDARY 8
278 /* Normal alignment required for function parameters on the stack, in bits.
279 This can't be less than BITS_PER_WORD */
280 #define PARM_BOUNDARY (BITS_PER_WORD)
282 /* Boundary (bits) on which stack pointer should be aligned. */
283 #define STACK_BOUNDARY 8
285 /* Allocation boundary (bits) for the code of a function. */
286 #define FUNCTION_BOUNDARY 8
288 #define BIGGEST_ALIGNMENT 8
290 /* Alignment of field after `int : 0' in a structure. */
291 #define EMPTY_FIELD_BOUNDARY 8
293 /* Every structure's size must be a multiple of this. */
294 #define STRUCTURE_SIZE_BOUNDARY 8
296 /* Define this if instructions will fail to work if given data not
297 on the nominal alignment. If instructions will merely go slower
298 in that case, do not define this macro. */
299 #define STRICT_ALIGNMENT 0
301 /* An integer expression for the size in bits of the largest integer
302 machine mode that should actually be used. All integer machine modes of
303 this size or smaller can be used for structures and unions with the
304 appropriate sizes. */
305 #define MAX_FIXED_MODE_SIZE 64
307 /* Floats are checked in a generic way. */
308 /* #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) */
312 /* target machine storage layout */
314 /* Size (bits) of the type "int" on target machine
315 (If undefined, default is BITS_PER_WORD). */
316 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
318 /* Size (bits) of the type "short" on target machine */
319 #define SHORT_TYPE_SIZE 16
321 /* Size (bits) of the type "long" on target machine */
322 #define LONG_TYPE_SIZE 32
324 /* Size (bits) of the type "long long" on target machine */
325 #define LONG_LONG_TYPE_SIZE 64
327 /* A C expression for the size in bits of the type `float' on the
328 target machine. If you don't define this, the default is one word.
329 Don't use default: a word is only 16. */
330 #define FLOAT_TYPE_SIZE 32
332 /* A C expression for the size in bits of the type double on the target
333 machine. If you don't define this, the default is two words.
334 Be IEEE compliant. */
335 #define DOUBLE_TYPE_SIZE 64
337 #define LONG_DOUBLE_TYPE_SIZE 64
339 /* Define this as 1 if `char' should by default be signed; else as 0. */
340 #define DEFAULT_SIGNED_CHAR 0
342 /* Define these to avoid dependence on meaning of `int'.
343 Note that WCHAR_TYPE_SIZE is used in cexp.y,
344 where TARGET_SHORT is not available. */
345 #define WCHAR_TYPE "short int"
346 #define WCHAR_TYPE_SIZE 16
349 /* Standard register usage. */
351 #define HARD_REG_SIZE (UNITS_PER_WORD)
353 /* Assign names to real MC68HC11 registers.
354 A and B registers are not really used (A+B = D)
355 X register is first so that GCC allocates X+D for 32-bit integers and
356 the lowpart of that integer will be D. Having the lower part in D is
357 better for 32<->16bit conversions and for many arithmetic operations. */
358 #define HARD_X_REGNUM 0
359 #define HARD_D_REGNUM 1
360 #define HARD_Y_REGNUM 2
361 #define HARD_SP_REGNUM 3
362 #define HARD_PC_REGNUM 4
363 #define HARD_A_REGNUM 5
364 #define HARD_B_REGNUM 6
365 #define HARD_CCR_REGNUM 7
367 /* The Z register does not really exist in the 68HC11. This a fake register
368 for GCC. It is treated exactly as an index register (X or Y). It is only
369 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this
370 register helps the reload pass of GCC. Otherwise, the reload often aborts
371 with register spill failures.
373 The Z register is replaced by either X or Y during the machine specific
374 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register
375 when this is necessary.
377 It's possible to tell GCC not to use this register with -ffixed-z. */
378 #define HARD_Z_REGNUM 8
380 /* The frame pointer is a soft-register. It's treated as such by GCC:
381 it is not and must not be part of the BASE_REG_CLASS. */
382 #define DEFAULT_HARD_FP_REGNUM (9)
383 #define HARD_FP_REGNUM (9)
384 #define HARD_AP_REGNUM (HARD_FP_REGNUM)
386 /* Temporary soft-register used in some cases when an operand came
387 up into a bad register class (D, X, Y, SP) and gcc failed to
388 recognize this. This register is never allocated by GCC. */
389 #define SOFT_TMP_REGNUM 10
391 /* The soft-register which is used to save the Z register
392 (see Z register replacement notes in m68hc11.c). */
393 #define SOFT_Z_REGNUM 11
395 /* The soft-register which is used to save either X or Y. */
396 #define SOFT_SAVED_XY_REGNUM 12
398 /* A fake clobber register for 68HC12 patterns. */
399 #define FAKE_CLOBBER_REGNUM (13)
401 /* Define 32 soft-registers of 16-bit each. By default,
402 only 12 of them are enabled and can be used by GCC. The
403 -msoft-reg-count=<n> option allows to control the number of valid
404 soft-registers. GCC can put 32-bit values in them
405 by allocating consecutive registers. The first 3 soft-registers
406 are never allocated by GCC. They are used in case the insn template needs
407 a temporary register, or for the Z register replacement. */
409 #define MAX_SOFT_REG_COUNT (32)
410 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \
411 0, 0, 0, 0, 1, 1, 1, 1, \
412 1, 1, 1, 1, 1, 1, 1, 1, \
413 1, 1, 1, 1, 1, 1, 1, 1
414 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \
415 0, 0, 0, 0, 1, 1, 1, 1, \
416 1, 1, 1, 1, 1, 1, 1, 1, \
417 1, 1, 1, 1, 1, 1, 1, 1
418 #define SOFT_REG_ORDER \
419 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\
420 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\
421 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\
422 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\
423 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\
424 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\
425 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\
426 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31
428 #define SOFT_REG_NAMES \
429 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \
430 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \
431 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \
432 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \
433 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \
434 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \
435 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \
436 "*_.d29", "*_.d30", "*_.d31", "*_.d32"
438 /* First available soft-register for GCC. */
439 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2)
441 /* Last available soft-register for GCC. */
442 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)
443 #define SOFT_FP_REGNUM (SOFT_REG_LAST)
444 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1)
446 /* Number of actual hardware registers. The hardware registers are assigned
447 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER.
448 All registers that the compiler knows about must be given numbers, even
449 those that are not normally considered general registers. */
450 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2)
452 /* 1 for registers that have pervasive standard uses and are not available
453 for the register allocator. */
454 #define FIXED_REGISTERS \
455 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1}
456 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */
458 /* 1 for registers not available across function calls. For our pseudo
459 registers, all are available. */
460 #define CALL_USED_REGISTERS \
461 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1}
462 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */
465 /* Define this macro to change register usage conditional on target flags.
467 The soft-registers are disabled or enabled according to the
468 -msoft-reg-count=<n> option. */
471 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())
473 /* List the order in which to allocate registers. Each register must be
474 listed once, even those in FIXED_REGISTERS. */
475 #define REG_ALLOC_ORDER \
476 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \
477 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \
478 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \
479 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \
480 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM }
482 /* A C expression for the number of consecutive hard registers,
483 starting at register number REGNO, required to hold a value of
485 #define HARD_REGNO_NREGS(REGNO, MODE) \
486 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \
487 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))
489 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
490 - 8 bit values are stored anywhere (except the SP register).
491 - 16 bit values can be stored in any register whose mode is 16
492 - 32 bit values can be stored in D, X registers or in a soft register
493 (except the last one because we need 2 soft registers)
494 - Values whose size is > 32 bit are not stored in real hard
495 registers. They may be stored in soft registers if there are
497 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
498 hard_regno_mode_ok (REGNO,MODE)
500 /* Value is 1 if it is a good idea to tie two pseudo registers when one has
501 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce
502 different values for MODE1 and MODE2, for any hard reg, then this must be
503 0 for correct output.
505 All modes are tieable except QImode. */
506 #define MODES_TIEABLE_P(MODE1, MODE2) \
507 (((MODE1) == (MODE2)) \
508 || ((MODE1) != QImode && (MODE2) != QImode))
511 /* Define the classes of registers for register constraints in the
512 machine description. Also define ranges of constants.
514 One of the classes must always be named ALL_REGS and include all hard regs.
515 If there is more than one class, another class must be named NO_REGS
516 and contain no registers.
518 The name GENERAL_REGS must be the name of a class (or an alias for
519 another name such as ALL_REGS). This is the class of registers
520 that is allowed by "g" or "r" in a register constraint.
521 Also, registers outside this class are allocated only when
522 instructions express preferences for them.
524 The classes must be numbered in nondecreasing order; that is,
525 a larger-numbered class must never be contained completely
526 in a smaller-numbered class.
528 For any two classes, it is very desirable that there be another
529 class that represents their union. */
531 /* The M68hc11 has so fiew registers that it's not possible for GCC to
532 do any register allocation without breaking. We extend the processor
533 registers by having soft registers. These registers are treated as
534 hard registers by GCC but they are located in memory and accessed by page0
535 accesses (IND mode). */
539 D_REGS
, /* 16-bit data register */
540 X_REGS
, /* 16-bit X register */
541 Y_REGS
, /* 16-bit Y register */
542 SP_REGS
, /* 16 bit stack pointer */
543 DA_REGS
, /* 8-bit A reg. */
544 DB_REGS
, /* 8-bit B reg. */
545 Z_REGS
, /* 16-bit fake Z register */
546 D8_REGS
, /* 8-bit A or B reg. */
547 Q_REGS
, /* 8-bit (byte (QI)) data (A, B or D) */
548 D_OR_X_REGS
, /* D or X register */
549 D_OR_Y_REGS
, /* D or Y register */
550 D_OR_SP_REGS
, /* D or SP register */
551 X_OR_Y_REGS
, /* IX or Y register */
552 A_REGS
, /* 16-bit address register (X, Y, Z) */
553 X_OR_SP_REGS
, /* X or SP register */
554 Y_OR_SP_REGS
, /* Y or SP register */
555 X_OR_Y_OR_D_REGS
, /* X, Y or D */
556 A_OR_D_REGS
, /* X, Y, Z or D */
557 A_OR_SP_REGS
, /* X, Y, Z or SP */
558 H_REGS
, /* 16-bit hard register (D, X, Y, Z, SP) */
559 S_REGS
, /* 16-bit soft register */
560 D_OR_S_REGS
, /* 16-bit soft register or D register */
561 X_OR_S_REGS
, /* 16-bit soft register or X register */
562 Y_OR_S_REGS
, /* 16-bit soft register or Y register */
563 SP_OR_S_REGS
, /* 16-bit soft register or SP register */
564 D_OR_X_OR_S_REGS
, /* 16-bit soft register or D or X register */
565 D_OR_Y_OR_S_REGS
, /* 16-bit soft register or D or Y register */
566 D_OR_SP_OR_S_REGS
, /* 16-bit soft register or D or SP register */
567 A_OR_S_REGS
, /* 16-bit soft register or X, Y registers */
568 D_OR_A_OR_S_REGS
, /* 16-bit soft register or D, X, Y registers */
569 TMP_REGS
, /* 16 bit fake scratch register */
570 D_OR_A_OR_TMP_REGS
, /* General scratch register */
571 G_REGS
, /* 16-bit general register
572 (H_REGS + soft registers) */
577 /* alias GENERAL_REGS to G_REGS. */
578 #define GENERAL_REGS G_REGS
580 #define N_REG_CLASSES (int) LIM_REG_CLASSES
582 /* Give names of register classes as strings for dump file. */
583 #define REG_CLASS_NAMES \
601 "X_OR_Y_OR_D_REGS", \
610 "D_OR_X_OR_S_REGS", \
611 "D_OR_Y_OR_S_REGS", \
612 "D_OR_SP_OR_S_REGS", \
614 "D_OR_A_OR_S_REGS", \
616 "D_OR_A_OR_TMP_REGS", \
620 /* An initializer containing the contents of the register classes,
621 as integers which are bit masks. The Nth integer specifies the
622 contents of class N. The way the integer MASK is interpreted is
623 that register R is in the class if `MASK & (1 << R)' is 1. */
625 /*--------------------------------------------------------------
640 Di 0xFFFFc000, 0x03FFF
641 SFRAME 0x00000000, 0x04000
642 AP 0x00000000, 0x08000
644 D_OR_X_REGS represents D+X. It is used for 32-bits numbers.
645 A_REGS represents a valid base register for indexing. It represents
646 X,Y and the Z register.
647 S_REGS represents the soft-registers. This includes the hard frame
648 and soft frame registers.
649 --------------------------------------------------------------*/
651 #define REG_CLASS_CONTENTS \
652 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \
653 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \
654 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \
655 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \
656 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \
657 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \
658 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \
659 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \
660 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \
661 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \
662 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \
663 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \
664 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \
665 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \
666 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \
667 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \
668 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \
669 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \
670 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \
671 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \
672 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \
673 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \
674 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \
675 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \
676 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \
677 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \
678 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \
679 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \
680 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \
681 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \
682 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \
683 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \
684 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \
685 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \
686 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }}
689 /* set up a C expression whose value is a register class containing hard
691 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \
692 || (REGNO) == HARD_B_REGNUM)
693 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X)))
695 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM)
696 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
698 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM)
699 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X)))
700 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM)
701 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X)))
703 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM)
704 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X)))
706 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM)
707 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X)))
709 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
710 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
712 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM)
713 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X)))
715 /* Address register. */
716 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \
717 || (REGNO) == HARD_Y_REGNUM \
718 || (REGNO) == HARD_Z_REGNUM)
719 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
721 /* M68hc11 hard registers. */
722 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \
723 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO))
724 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X)))
726 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM)
727 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X)))
729 /* Soft registers (or register emulation for gcc). The temporary register
730 used by insn template must be part of the S_REGS class so that it
731 matches the 'u' constraint. */
732 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \
733 && (REGNO) <= SOFT_REG_LAST \
734 && (REGNO) != FAKE_CLOBBER_REGNUM)
735 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
737 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
738 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
740 /* General register. */
741 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \
742 || ((REGNO) == HARD_PC_REGNUM) \
743 || ((REGNO) == HARD_FP_REGNUM) \
744 || ((REGNO) == SOFT_FP_REGNUM) \
745 || ((REGNO) == FAKE_CLOBBER_REGNUM) \
746 || ((REGNO) == SOFT_AP_REGNUM))
748 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X)))
750 #define REGNO_REG_CLASS(REGNO) \
751 (D_REGNO_P (REGNO) ? D_REGS : \
752 (X_REGNO_P (REGNO) ? X_REGS : \
753 (Y_REGNO_P (REGNO) ? Y_REGS : \
754 (SP_REGNO_P (REGNO) ? SP_REGS : \
755 (Z_REGNO_P (REGNO) ? Z_REGS : \
756 (H_REGNO_P (REGNO) ? H_REGS : \
757 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \
758 (S_REGNO_P (REGNO) ? S_REGS : \
759 (DA_REGNO_P (REGNO) ? DA_REGS: \
760 (DB_REGNO_P (REGNO) ? DB_REGS: \
761 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS)))))))))))
764 /* Get reg_class from a letter in the machine description. */
766 extern enum reg_class m68hc11_tmp_regs_class
;
767 #define REG_CLASS_FROM_LETTER(C) \
768 ((C) == 'a' ? DA_REGS : \
769 (C) == 'A' ? A_REGS : \
770 (C) == 'b' ? DB_REGS : \
771 (C) == 'B' ? X_OR_Y_REGS : \
772 (C) == 'd' ? D_REGS : \
773 (C) == 'D' ? D_OR_X_REGS : \
774 (C) == 'q' ? Q_REGS : \
775 (C) == 'h' ? H_REGS : \
776 (C) == 't' ? TMP_REGS : \
777 (C) == 'u' ? S_REGS : \
778 (C) == 'v' ? m68hc11_tmp_regs_class : \
779 (C) == 'w' ? SP_REGS : \
780 (C) == 'x' ? X_REGS : \
781 (C) == 'y' ? Y_REGS : \
782 (C) == 'z' ? Z_REGS : NO_REGS)
784 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS)
786 #define SMALL_REGISTER_CLASSES 1
788 /* A C expression whose value is nonzero if pseudos that have been
789 assigned to registers of class CLASS would likely be spilled
790 because registers of CLASS are needed for spill registers.
792 The default value of this macro returns 1 if CLASS has exactly one
793 register and zero otherwise. On most machines, this default
794 should be used. Only define this macro to some other expression
795 if pseudo allocated by `local-alloc.c' end up in memory because
796 their hard registers were needed for spill registers. If this
797 macro returns nonzero for those classes, those pseudos will only
798 be allocated by `global.c', which knows how to reallocate the
799 pseudo to another register. If there would not be another
800 register available for reallocation, you should not change the
801 definition of this macro since the only effect of such a
802 definition would be to slow down register allocation. */
804 #define CLASS_LIKELY_SPILLED_P(CLASS) \
805 (((CLASS) == D_REGS) \
806 || ((CLASS) == X_REGS) \
807 || ((CLASS) == Y_REGS) \
808 || ((CLASS) == A_REGS) \
809 || ((CLASS) == SP_REGS) \
810 || ((CLASS) == D_OR_X_REGS) \
811 || ((CLASS) == D_OR_Y_REGS) \
812 || ((CLASS) == X_OR_SP_REGS) \
813 || ((CLASS) == Y_OR_SP_REGS) \
814 || ((CLASS) == D_OR_SP_REGS))
816 /* Return the maximum number of consecutive registers needed to represent
817 mode MODE in a register of class CLASS. */
818 #define CLASS_MAX_NREGS(CLASS, MODE) \
819 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \
820 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \
821 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
823 /* The letters I, J, K, L and M in a register constraint string
824 can be used to stand for particular ranges of immediate operands.
825 This macro defines what the ranges are.
826 C is the letter, and VALUE is a constant value.
827 Return 1 if VALUE is in the range specified by C.
830 `L' is for range -65536 to 65536
831 `M' is for values whose 16-bit low part is 0
833 'O' is for 16 (for rotate using swap).
834 'P' is for range -8 to 2 (used by addhi_sp)
836 'I', 'J' are not used. */
838 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
839 ((C) == 'K' ? (VALUE) == 0 : \
840 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \
841 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \
842 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \
843 (C) == 'O' ? (VALUE) == 16 : \
844 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0)
846 /* Similar, but for floating constants, and defining letters G and H.
849 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
850 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
851 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0)
853 /* 'U' represents certain kind of memory indexed operand for 68HC12.
854 and any memory operand for 68HC11. */
855 #define EXTRA_CONSTRAINT(OP, C) \
856 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \
857 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \
858 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \
859 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \
860 && non_push_operand (OP, GET_MODE (OP))) : 0)
863 /* Stack layout; function entry, exit and calling. */
865 /* Define this if pushing a word on the stack
866 makes the stack pointer a smaller address. */
867 #define STACK_GROWS_DOWNWARD
869 /* Define this if the nominal address of the stack frame
870 is at the high-address end of the local variables;
871 that is, each additional local variable allocated
872 goes at a more negative offset in the frame.
874 Don't define for 68HC11, the frame pointer is the bottom
875 of local variables. */
876 /* #define FRAME_GROWS_DOWNWARD */
878 /* Define this if successive arguments to a function occupy decreasing
879 addresses in the stack. */
880 /* #define ARGS_GROW_DOWNWARD */
882 /* Offset within stack frame to start allocating local variables at.
883 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
884 first local allocated. Otherwise, it is the offset to the BEGINNING
885 of the first local allocated. */
886 #define STARTING_FRAME_OFFSET 0
888 /* Offset of first parameter from the argument pointer register value. */
890 #define FIRST_PARM_OFFSET(FNDECL) 2
892 /* After the prologue, RA is at 0(AP) in the current frame. */
893 #define RETURN_ADDR_RTX(COUNT, FRAME) \
895 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
898 /* Before the prologue, the top of the frame is at 2(sp). */
899 #define INCOMING_FRAME_SP_OFFSET 2
901 /* Define this if functions should assume that stack space has been
902 allocated for arguments even when their values are passed in
905 The value of this macro is the size, in bytes, of the area reserved for
906 arguments passed in registers.
908 This space can either be allocated by the caller or be a part of the
909 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
911 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */
913 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack
914 parameters don't skip the area specified by REG_PARM_STACK_SPACE.
915 Normally, when a parameter is not passed in registers, it is placed on
916 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro
917 suppresses this behavior and causes the parameter to be passed on the
918 stack in its natural location. */
919 /* #define STACK_PARMS_IN_REG_PARM_AREA */
921 /* Register to use for pushing function arguments. */
922 #define STACK_POINTER_REGNUM HARD_SP_REGNUM
924 /* Base register for access to local variables of the function. */
925 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM
927 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM
929 /* Base register for access to arguments of the function. */
930 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM
932 /* Register in which static-chain is passed to a function. */
933 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM
936 /* Definitions for register eliminations.
938 This is an array of structures. Each structure initializes one pair
939 of eliminable registers. The "from" register number is given first,
940 followed by "to". Eliminations of the same "from" register are listed
941 in order of preference.
943 We have two registers that are eliminated on the 6811. The psuedo arg
944 pointer and pseudo frame pointer registers can always be eliminated;
945 they are replaced with either the stack or the real frame pointer. */
947 #define ELIMINABLE_REGS \
948 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
949 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
950 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
951 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
953 /* Value should be nonzero if functions must have frame pointers.
954 Zero means the frame pointer need not be set up (and parms may be
955 accessed via the stack pointer) in functions that seem suitable.
956 This is computed in `reload', in reload1.c. */
957 #define FRAME_POINTER_REQUIRED 0
959 /* Given FROM and TO register numbers, say whether this elimination is allowed.
960 Frame pointer elimination is automatically handled.
962 All other eliminations are valid. */
964 #define CAN_ELIMINATE(FROM, TO) \
965 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
966 ? ! frame_pointer_needed \
970 /* Define the offset between two registers, one to be eliminated, and the other
971 its replacement, at the start of a routine. */
973 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
974 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); }
977 /* Passing Function Arguments on the Stack. */
979 /* When a prototype says `char' or `short', really pass an `int'. */
980 /* #define PROMOTE_PROTOTYPES */
982 /* If we generate an insn to push BYTES bytes, this says how many the
983 stack pointer really advances by. No rounding or alignment needed
985 #define PUSH_ROUNDING(BYTES) (BYTES)
987 /* Value is 1 if returning from a function call automatically pops the
988 arguments described by the number-of-args field in the call. FUNTYPE is
989 the data type of the function (as a tree), or for a library call it is
990 an identifier node for the subroutine name.
992 The standard MC6811 call, with arg count word, includes popping the
993 args as part of the call template. */
994 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
996 /* Nonzero if type TYPE should be returned in memory.
997 Blocks and data types largers than 4 bytes cannot be returned
998 in the register (D + X = 4). */
999 #define RETURN_IN_MEMORY(TYPE) \
1000 ((TYPE_MODE (TYPE) == BLKmode) \
1001 ? (int_size_in_bytes (TYPE) > 4) \
1002 : (GET_MODE_SIZE (TYPE_MODE (TYPE)) > 4))
1005 /* Passing Arguments in Registers. */
1007 /* Define a data type for recording info about an argument list
1008 during the scan of that argument list. This data type should
1009 hold all necessary information about the function itself
1010 and about the args processed so far, enough to enable macros
1011 such as FUNCTION_ARG to determine where the next arg should go. */
1013 typedef struct m68hc11_args
1019 /* A C expression that indicates when an argument must be passed by reference.
1020 If nonzero for an argument, a copy of that argument is made in memory and a
1021 pointer to the argument is passed instead of the argument itself.
1022 The pointer is passed in whatever way is appropriate for passing a pointer
1025 64-bit numbers are passed by reference. */
1026 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1027 m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1030 /* If defined, a C expression which determines whether, and in which direction,
1031 to pad out an argument with extra space. The value should be of type
1032 `enum direction': either `upward' to pad above the argument,
1033 `downward' to pad below, or `none' to inhibit padding.
1035 Structures are stored left shifted in their argument slot. */
1036 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1037 m68hc11_function_arg_padding ((MODE), (TYPE))
1039 /* A C expression that indicates when it is the called function's
1040 responsibility to make a copy of arguments passed by invisible
1041 reference. Normally, the caller makes a copy and passes the
1042 address of the copy to the routine being called. When
1043 FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
1044 does not make a copy. Instead, it passes a pointer to the "live"
1045 value. The called function must not modify this value. If it can
1046 be determined that the value won't be modified, it need not make a
1047 copy; otherwise a copy must be made. */
1048 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1049 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
1051 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
1052 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */
1053 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1054 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1056 /* Update the data in CUM to advance over an argument of mode MODE and data
1057 type TYPE. (TYPE is null for libcalls where that information may not be
1059 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1060 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1062 /* Define where to put the arguments to a function.
1063 Value is zero to push the argument on the stack,
1064 or a hard register in which to store the argument.
1066 MODE is the argument's machine mode.
1067 TYPE is the data type of the argument (as a tree).
1068 This is null for libcalls where that information may
1070 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1071 the preceding args and about the function being called.
1072 NAMED is nonzero if this argument is a named parameter
1073 (otherwise it is an extra parameter matching an ellipsis). */
1074 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1075 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED))
1077 /* Define the profitability of saving registers around calls.
1079 Disable this because the saving instructions generated by
1080 caller-save need a reload and the way it is implemented,
1081 it forbids all spill registers at that point. Enabling
1082 caller saving results in spill failure. */
1083 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1085 /* Implement `va_arg'. */
1086 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1087 m68hc11_va_arg (valist, type)
1089 /* For an arg passed partly in registers and partly in memory,
1090 this is the number of registers used.
1091 For args passed entirely in registers or entirely in memory, zero.
1093 Passing an arg partly in register and memory does not work at all.
1095 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
1097 /* 1 if N is a possible register number for function argument passing.
1098 D is for 16-bit values, X is for 32-bit (X+D). */
1099 #define FUNCTION_ARG_REGNO_P(N) \
1100 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM))
1102 /* All return values are in the D or X+D registers:
1103 - 8 and 16-bit values are returned in D.
1104 BLKmode are passed in D as pointer.
1105 - 32-bit values are returned in X + D.
1106 The high part is passed in X and the low part in D.
1107 For GCC, the register number must be HARD_X_REGNUM. */
1108 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1109 gen_rtx (REG, TYPE_MODE (VALTYPE), \
1110 ((TYPE_MODE (VALTYPE) == BLKmode \
1111 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \
1112 ? HARD_D_REGNUM : HARD_X_REGNUM))
1114 #define LIBCALL_VALUE(MODE) \
1115 gen_rtx (REG, MODE, \
1116 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \
1117 ? HARD_D_REGNUM : HARD_X_REGNUM))
1119 /* 1 if N is a possible register number for a function value. */
1120 #define FUNCTION_VALUE_REGNO_P(N) \
1121 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM)
1123 /* Register in which address to store a structure value is passed to a
1125 #define STRUCT_VALUE_REGNUM HARD_D_REGNUM
1127 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1128 the stack pointer does not matter. The value is tested only in functions
1129 that have frame pointers. No definition is equivalent to always zero. */
1130 #define EXIT_IGNORE_STACK 0
1133 /* Generating Code for Profiling. */
1135 /* Output assembler code to FILE to increment profiler label # LABELNO
1136 for profiling a function entry. */
1137 #define FUNCTION_PROFILER(FILE, LABELNO) \
1138 asm_fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO))
1139 /* Length in units of the trampoline for entering a nested function. */
1140 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9)
1142 /* A C statement to initialize the variable parts of a trampoline.
1143 ADDR is an RTX for the address of the trampoline; FNADDR is an
1144 RTX for the address of the nested function; STATIC_CHAIN is an
1145 RTX for the static chain value that should be passed to the
1146 function when it is called. */
1147 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1148 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1151 /* `INIT_TARGET_OPTABS'
1152 Define this macro as a C statement that declares additional library
1153 routines renames existing ones. `init_optabs' calls this macro
1154 after initializing all the normal library routines.
1156 Overrides the memcpy */
1158 #define INIT_TARGET_OPTABS \
1161 memcpy_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcpy"); \
1162 memcmp_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcmp"); \
1163 memset_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memset"); \
1168 /* Addressing modes, and classification of registers for them. */
1170 /* The 68HC12 has all the post/pre increment/decrement modes. */
1171 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1172 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1173 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1174 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1176 /* The class value for base registers. This depends on the target:
1177 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value
1178 is stored at init time. */
1179 extern enum reg_class m68hc11_base_reg_class
;
1180 #define BASE_REG_CLASS m68hc11_base_reg_class
1182 /* The class value for index registers. This is NO_REGS for 68HC11. */
1184 extern enum reg_class m68hc11_index_reg_class
;
1185 #define INDEX_REG_CLASS m68hc11_index_reg_class
1187 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero
1188 only if REGNO is a hard reg of the suitable class or a pseudo reg currently
1189 allocated to a suitable hard reg. Since they use reg_renumber, they are
1190 safe only once reg_renumber has been allocated, which happens in
1194 /* Internal macro, return 1 if REGNO is a valid base register. */
1195 #define REG_VALID_P(REGNO) (1) /* ? */
1197 extern unsigned char m68hc11_reg_valid_for_base
[FIRST_PSEUDO_REGISTER
];
1198 #define REG_VALID_FOR_BASE_P(REGNO) \
1199 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \
1200 && m68hc11_reg_valid_for_base[REGNO])
1202 /* Internal macro, return 1 if REGNO is a valid index register. */
1203 extern unsigned char m68hc11_reg_valid_for_index
[FIRST_PSEUDO_REGISTER
];
1204 #define REG_VALID_FOR_INDEX_P(REGNO) \
1205 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \
1206 && m68hc11_reg_valid_for_index[REGNO])
1208 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */
1209 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
1210 ((REGNO) >= FIRST_PSEUDO_REGISTER \
1211 || REG_VALID_FOR_BASE_P (REGNO) \
1212 || (REGNO) == FRAME_POINTER_REGNUM \
1213 || (REGNO) == HARD_FRAME_POINTER_REGNUM \
1214 || (REGNO) == ARG_POINTER_REGNUM \
1215 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1217 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */
1218 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
1220 && ((REGNO) >= FIRST_PSEUDO_REGISTER \
1221 || REG_VALID_FOR_INDEX_P (REGNO) \
1222 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1224 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */
1225 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \
1226 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \
1227 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1229 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */
1230 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \
1232 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \
1233 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1235 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \
1236 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \
1237 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO)))
1239 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \
1240 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \
1241 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO)))
1243 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO)
1244 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO)
1246 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X))
1247 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X))
1248 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X))
1249 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X))
1251 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */
1252 #define IS_STACK_PUSH(operand) \
1253 ((GET_CODE (operand) == MEM) \
1254 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \
1255 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1257 #define IS_STACK_POP(operand) \
1258 ((GET_CODE (operand) == MEM) \
1259 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \
1260 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1262 /* 1 if X is an rtx for a constant that is a valid address. */
1263 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1265 /* Maximum number of registers that can appear in a valid memory address */
1266 #define MAX_REGS_PER_ADDRESS 2
1268 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1269 valid memory address for an instruction. The MODE argument is the
1270 machine mode for the MEM expression that wants to use this address. */
1272 /*--------------------------------------------------------------
1273 Valid addresses are either direct or indirect (MEM) versions
1274 of the following forms:
1278 --------------------------------------------------------------*/
1280 /* The range of index that is allowed by indirect addressing. */
1282 #define VALID_MIN_OFFSET m68hc11_min_offset
1283 #define VALID_MAX_OFFSET m68hc11_max_offset
1285 /* The offset values which are allowed by the n,x and n,y addressing modes.
1286 Take into account the size of the mode because we may have to add
1287 a mode offset to access the lowest part of the data.
1288 (For example, for an SImode, the last valid offset is 252.) */
1289 #define VALID_CONSTANT_OFFSET_P(X,MODE) \
1290 (((GET_CODE (X) == CONST_INT) && \
1291 ((INTVAL (X) >= VALID_MIN_OFFSET) \
1292 && ((INTVAL (X) <= VALID_MAX_OFFSET \
1293 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \
1295 && ((GET_CODE (X) == SYMBOL_REF) \
1296 || GET_CODE (X) == LABEL_REF \
1297 || GET_CODE (X) == CONST)))
1299 /* This is included to allow stack push/pop operations. Special hacks in the
1300 md and m6811.c files exist to support this. */
1301 #define PUSH_POP_ADDRESS_P(X) \
1302 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \
1303 && SP_REG_P (XEXP (X, 0)))
1305 /* Go to ADDR if X is a valid address. */
1306 #ifndef REG_OK_STRICT
1307 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1309 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \
1312 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1314 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \
1318 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its
1319 validity for a certain class. We have two alternate definitions for each
1320 of them. The usual definition accepts all pseudo regs; the other rejects
1321 them unless they have been allocated suitable hard regs. The symbol
1322 REG_OK_STRICT causes the latter definition to be used.
1324 Most source files want to accept pseudo regs in the hope that they will
1325 get allocated to the class that the insn wants them to be in. Source files
1326 for reload pass need to be strict. After reload, it makes no difference,
1327 since pseudo regs have been eliminated by then. */
1329 #ifndef REG_OK_STRICT
1330 /* Nonzero if X is a hard reg that can be used as a base reg. */
1331 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1333 /* Nonzero if X is a hard reg that can be used as an index. */
1334 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1336 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1337 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1341 /* Try machine-dependent ways of modifying an illegitimate address
1342 to be legitimate. If we find one, return the new, valid address.
1343 This macro is used in only one place: `memory_address' in explow.c.
1345 OLDX is the address as it was before break_out_memory_refs was called.
1346 In some cases it is useful to look at this to decide what needs to be done.
1348 MODE and WIN are passed so that this macro can use
1349 GO_IF_LEGITIMATE_ADDRESS.
1351 It is always safe for this macro to do nothing.
1352 It exists to recognize opportunities to optimize the output. */
1354 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1355 { rtx operand = (X); \
1356 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \
1359 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \
1363 /* Go to LABEL if ADDR (a legitimate address expression)
1364 has an effect that depends on the machine mode it is used for. */
1365 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1367 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
1368 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
1372 /* Nonzero if the constant value X is a legitimate general operand.
1373 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1375 #define LEGITIMATE_CONSTANT_P(X) 1
1378 /* Tell final.c how to eliminate redundant test instructions. */
1380 #define NOTICE_UPDATE_CC(EXP, INSN) \
1381 m68hc11_notice_update_cc ((EXP), (INSN))
1383 /* Compute the cost of computing a constant rtl expression RTX whose rtx-code
1384 is CODE. The body of this macro is a portion of a switch statement. If
1385 the code is computed here, return it with a return statement. Otherwise,
1386 break from the switch.
1388 Constants are cheap. Moving them in registers must be avoided
1389 because most instructions do not handle two register operands. */
1390 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1392 /* Logical and arithmetic operations with a constant */ \
1393 /* operand are better because they are not supported */ \
1394 /* with two registers. */ \
1395 /* 'clr' is slow */ \
1396 if ((OUTER_CODE) == SET && (RTX) == const0_rtx) \
1397 /* After reload, the reload_cse pass checks the cost */ \
1398 /* to change a SET into a PLUS. Make const0 cheap. */ \
1399 return 1 - reload_completed; \
1405 if ((OUTER_CODE) == SET) \
1406 return 1 - reload_completed; \
1408 case CONST_DOUBLE: \
1411 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1431 case IF_THEN_ELSE: \
1432 return m68hc11_rtx_costs (X, CODE, OUTER_CODE);
1434 /* An expression giving the cost of an addressing mode that contains
1435 ADDRESS. If not defined, the cost is computed from the ADDRESS
1436 expression and the `CONST_COSTS' values. */
1438 #define ADDRESS_COST(RTX) m68hc11_address_cost (RTX)
1440 /* Move costs between classes of registers */
1441 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1442 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2))
1444 /* Move cost between register and memory.
1445 - Move to a 16-bit register is reasonable,
1446 - Move to a soft register can be expensive. */
1447 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1448 m68hc11_memory_move_cost ((MODE),(CLASS),(IN))
1450 /* A C expression for the cost of a branch instruction. A value of 1
1451 is the default; other values are interpreted relative to that.
1453 Pretend branches are cheap because GCC generates sub-optimal code
1454 for the default value. */
1455 #define BRANCH_COST 0
1457 /* Nonzero if access to memory by bytes is slow and undesirable. */
1458 #define SLOW_BYTE_ACCESS 0
1460 /* It is as good to call a constant function address as to call an address
1461 kept in a register. */
1462 #define NO_FUNCTION_CSE
1464 /* Try a machine-dependent way of reloading an illegitimate address
1465 operand. If we find one, push the reload and jump to WIN. This
1466 macro is used in only one place: `find_reloads_address' in reload.c.
1468 For M68HC11, we handle large displacements of a base register
1469 by splitting the addend accors an addhi3 insn.
1471 For M68HC12, the 64K offset range is available.
1474 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1476 /* We must recognize output that we have already generated ourselves. */ \
1477 if (GET_CODE (X) == PLUS \
1478 && GET_CODE (XEXP (X, 0)) == PLUS \
1479 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1480 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1481 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1483 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1484 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1488 if (GET_CODE (X) == PLUS \
1489 && GET_CODE (XEXP (X, 0)) == REG \
1490 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1491 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \
1493 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1494 HOST_WIDE_INT low, high; \
1495 high = val & (~0x0FF); \
1496 low = val & 0x00FF; \
1497 if (low >= 256-15) { high += 16; low -= 16; } \
1498 /* Reload the high part into a base reg; leave the low part \
1499 in the mem directly. */ \
1501 X = gen_rtx_PLUS (Pmode, \
1502 gen_rtx_PLUS (Pmode, XEXP (X, 0), \
1506 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1507 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1514 /* Defining the Output Assembler Language. */
1516 /* A default list of other sections which we might be "in" at any given
1517 time. For targets that use additional sections (e.g. .tdesc) you
1518 should override this definition in the target-specific file which
1519 includes this file. */
1521 /* Output before read-only data. */
1522 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text")
1524 /* Output before writable data. */
1525 #define DATA_SECTION_ASM_OP ("\t.sect\t.data")
1527 /* Output before uninitialized data. */
1528 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss")
1530 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
1532 Same as config/elfos.h but don't mark these section SHF_WRITE since
1533 there is no shared library problem. */
1534 #undef CTORS_SECTION_ASM_OP
1535 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
1537 #undef DTORS_SECTION_ASM_OP
1538 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
1540 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor
1541 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor
1543 /* This is how to begin an assembly language file. Most svr4 assemblers want
1544 at least a .file directive to come first, and some want to see a .version
1545 directive come right after that. Here we just establish a default
1546 which generates only the .file directive. If you need a .version
1547 directive for any specific target, you should override this definition
1548 in the target-specific file which includes this one. */
1550 #undef ASM_FILE_START
1551 #define ASM_FILE_START(FILE) \
1552 m68hc11_asm_file_start ((FILE), main_input_filename)
1554 /* Comment character */
1555 #define ASM_COMMENT_START ";"
1557 /* Output to assembler file text saying following lines
1558 may contain character constants, extra white space, comments, etc. */
1559 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n"
1561 /* Output to assembler file text saying following lines
1562 no longer contain unusual constructs. */
1563 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n"
1565 /* Write the extra assembler code needed to declare a function properly.
1566 Some svr4 assemblers need to also have something extra said about the
1567 function's return value. We allow for that here.
1569 For 68HC12 we mark functions that return with 'rtc'. The linker
1570 will ensure that a 'call' is really made (instead of 'jsr').
1571 The debugger needs this information to correctly compute the stack frame.
1573 For 68HC11/68HC12 we also mark interrupt handlers for gdb to
1574 compute the correct stack frame. */
1576 #undef ASM_DECLARE_FUNCTION_NAME
1577 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1580 fprintf (FILE, "%s", TYPE_ASM_OP); \
1581 assemble_name (FILE, NAME); \
1583 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \
1584 putc ('\n', FILE); \
1586 if (TARGET_M6812 && current_function_far) \
1588 fprintf (FILE, "\t.far\t"); \
1589 assemble_name (FILE, NAME); \
1590 putc ('\n', FILE); \
1592 else if (current_function_interrupt \
1593 || current_function_trap) \
1595 fprintf (FILE, "\t.interrupt\t"); \
1596 assemble_name (FILE, NAME); \
1597 putc ('\b', FILE); \
1599 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1600 ASM_OUTPUT_LABEL(FILE, NAME); \
1604 /* Output #ident as a .ident. */
1606 /* output external reference */
1607 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \
1608 {fputs ("\t; extern\t", FILE); \
1609 assemble_name (FILE, NAME); \
1610 fputs ("\n", FILE);}
1614 /* Store in OUTPUT a string (made with alloca) containing
1615 an assembler-name for a local static variable named NAME.
1616 LABELNO is an integer which is different for each call. */
1618 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1619 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1620 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1622 /* How to refer to registers in assembler output. This sequence is indexed
1623 by compiler's hard-register-number (see above). */
1624 #define REGISTER_NAMES \
1625 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \
1626 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \
1627 SOFT_REG_NAMES, "*sframe", "*ap"}
1629 /* Print an instruction operand X on file FILE. CODE is the code from the
1630 %-spec for printing this operand. If `%z3' was used to print operand
1631 3, then CODE is 'z'. */
1633 #define PRINT_OPERAND(FILE, X, CODE) \
1634 print_operand (FILE, X, CODE)
1636 /* Print a memory operand whose address is X, on file FILE. */
1637 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1638 print_operand_address (FILE, ADDR)
1640 /* This is how to output an insn to push/pop a register on the stack.
1641 It need not be very fast code.
1643 Don't define because we don't know how to handle that with
1644 the STATIC_CHAIN_REGNUM (soft register). Saving the static
1645 chain must be made inside FUNCTION_PROFILER. */
1647 #undef ASM_OUTPUT_REG_PUSH
1648 #undef ASM_OUTPUT_REG_POP
1650 /* This is how to output an element of a case-vector that is relative. */
1652 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1653 asm_fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL)
1655 /* This is how to output an element of a case-vector that is absolute. */
1656 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1657 asm_fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE)
1659 /* This is how to output an assembler line that says to advance the
1660 location counter to a multiple of 2**LOG bytes. */
1661 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1664 asm_fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \
1668 /* Assembler Commands for Exception Regions. */
1670 /* Default values provided by GCC should be ok. Assumming that DWARF-2
1671 frame unwind info is ok for this platform. */
1673 #undef PREFERRED_DEBUGGING_TYPE
1674 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1676 /* The prefix for local labels. You should be able to define this as
1677 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1678 without having to make any other changes to account for the specific
1679 definition. Note it is a string literal, not interpreted by printf
1681 #define LOCAL_LABEL_PREFIX "."
1683 /* The prefix for immediate operands. */
1684 #define IMMEDIATE_PREFIX "#"
1685 #define GLOBAL_ASM_OP "\t.globl\t"
1688 /* Miscellaneous Parameters. */
1690 /* Define the codes that are matched by predicates in m68hc11.c. */
1691 #define PREDICATE_CODES \
1692 {"stack_register_operand", {SUBREG, REG}}, \
1693 {"d_register_operand", {SUBREG, REG}}, \
1694 {"hard_addr_reg_operand", {SUBREG, REG}}, \
1695 {"hard_reg_operand", {SUBREG, REG}}, \
1696 {"m68hc11_logical_operator", {AND, IOR, XOR}}, \
1697 {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \
1698 ASHIFT, ASHIFTRT, LSHIFTRT, \
1699 ROTATE, ROTATERT }}, \
1700 {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \
1701 {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \
1702 {"non_push_operand", {SUBREG, REG, MEM}}, \
1703 {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \
1704 {"tst_operand", {SUBREG, REG, MEM}}, \
1705 {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \
1706 CONST_INT, CONST_DOUBLE}},
1708 /* Specify the machine mode that this machine uses
1709 for the index in the tablejump instruction. */
1710 #define CASE_VECTOR_MODE Pmode
1712 /* This flag, if defined, says the same insns that convert to a signed fixnum
1713 also convert validly to an unsigned one. */
1714 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1716 /* Max number of bytes we can move from memory to memory in one
1717 reasonably fast instruction. */
1720 /* MOVE_RATIO is the number of move instructions that is better than a
1721 block move. Make this small on 6811, since the code size grows very
1722 large with each move. */
1723 #define MOVE_RATIO 3
1725 /* Define if shifts truncate the shift count which implies one can omit
1726 a sign-extension or zero-extension of a shift count. */
1727 #define SHIFT_COUNT_TRUNCATED 1
1729 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1730 is done just by pretending it is already truncated. */
1731 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1733 /* Specify the machine mode that pointers have. After generation of rtl, the
1734 compiler makes no further distinction between pointers and any other
1735 objects of this machine mode. */
1736 #define Pmode HImode
1738 /* A function address in a call instruction is a byte address (for indexing
1739 purposes) so give the MEM rtx a byte's mode. */
1740 #define FUNCTION_MODE QImode
1742 /* Allow $ in identifiers */
1743 #define DOLLARS_IN_IDENTIFIERS 1
1745 /* Machine-dependent reorg pass.
1746 Specific optimizations are defined here:
1747 - this pass changes the Z register into either X or Y
1748 (it preserves X/Y previous values in a memory slot in page0).
1750 When this pass is finished, the global variable
1751 'z_replacement_completed' is set to 2. */
1752 #define MACHINE_DEPENDENT_REORG(X) m68hc11_reorg (X)
1754 extern int debug_m6811
;
1755 extern int z_replacement_completed
;
1756 extern int current_function_interrupt
;
1757 extern int current_function_trap
;
1758 extern int current_function_far
;