projects / gcc.git / blob
? search:


28237e1408fc3a2b12cdef53fe9cea28c49f727c
[gcc.git] / gcc / config / m68k / m68k.c
1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3
4 This file is part of GNU CC.
5
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21
22 /* Some output-actions in m68k.md need these. */
23 #include <stdio.h>
24 #include "config.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "real.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
32 #include "output.h"
33 #include "insn-attr.h"
34
35 /* Needed for use_return_insn. */
36 #include "flags.h"
37
38 #ifdef SUPPORT_SUN_FPA
39
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class[]
43 = { DATA_REGS, ADDR_REGS, FP_REGS,
44 LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
45
46 #endif /* defined SUPPORT_SUN_FPA */
47
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag;
51
52 static rtx find_addr_reg ();
53 rtx legitimize_pic_address ();
54 \f
55
56 /* Alignment to use for loops and jumps */
57 /* Specify power of two alignment used for loops. */
58 char *m68k_align_loops_string;
59 /* Specify power of two alignment used for non-loop jumps. */
60 char *m68k_align_jumps_string;
61 /* Specify power of two alignment used for functions. */
62 char *m68k_align_funcs_string;
63
64 /* Specify power of two alignment used for loops. */
65 int m68k_align_loops;
66 /* Specify power of two alignment used for non-loop jumps. */
67 int m68k_align_jumps;
68 /* Specify power of two alignment used for functions. */
69 int m68k_align_funcs;
70
71
72 /* Sometimes certain combinations of command options do not make
73 sense on a particular target machine. You can define a macro
74 `OVERRIDE_OPTIONS' to take account of this. This macro, if
75 defined, is executed once just after all the command options have
76 been parsed.
77
78 Don't use this macro to turn on various extra optimizations for
79 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
80
81 void
82 override_options ()
83 {
84 int def_align;
85
86 def_align = 1;
87
88 /* Validate -malign-loops= value, or provide default */
89 if (m68k_align_loops_string)
90 {
91 m68k_align_loops = atoi (m68k_align_loops_string);
92 if (m68k_align_loops < 1 || m68k_align_loops > MAX_CODE_ALIGN)
93 fatal ("-malign-loops=%d is not between 1 and %d",
94 m68k_align_loops, MAX_CODE_ALIGN);
95 }
96 else
97 m68k_align_loops = def_align;
98
99 /* Validate -malign-jumps= value, or provide default */
100 if (m68k_align_jumps_string)
101 {
102 m68k_align_jumps = atoi (m68k_align_jumps_string);
103 if (m68k_align_jumps < 1 || m68k_align_jumps > MAX_CODE_ALIGN)
104 fatal ("-malign-jumps=%d is not between 1 and %d",
105 m68k_align_jumps, MAX_CODE_ALIGN);
106 }
107 else
108 m68k_align_jumps = def_align;
109
110 /* Validate -malign-functions= value, or provide default */
111 if (m68k_align_funcs_string)
112 {
113 m68k_align_funcs = atoi (m68k_align_funcs_string);
114 if (m68k_align_funcs < 1 || m68k_align_funcs > MAX_CODE_ALIGN)
115 fatal ("-malign-functions=%d is not between 1 and %d",
116 m68k_align_funcs, MAX_CODE_ALIGN);
117 }
118 else
119 m68k_align_funcs = def_align;
120 }
121 \f
122 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
123 function at any time during the compilation process. In the future
124 we should try and eliminate the USE if we can easily determine that
125 all PIC references were deleted from the current function. That would
126 save an address register */
127
128 void
129 finalize_pic ()
130 {
131 if (flag_pic && current_function_uses_pic_offset_table)
132 {
133 rtx insn = gen_rtx (USE, VOIDmode, pic_offset_table_rtx);
134 emit_insn_after (insn, get_insns ());
135 emit_insn (insn);
136 }
137 }
138
139 \f
140 /* This function generates the assembly code for function entry.
141 STREAM is a stdio stream to output the code to.
142 SIZE is an int: how many units of temporary storage to allocate.
143 Refer to the array `regs_ever_live' to determine which registers
144 to save; `regs_ever_live[I]' is nonzero if register number I
145 is ever used in the function. This function is responsible for
146 knowing which registers should not be saved even if used. */
147
148
149 /* Note that the order of the bit mask for fmovem is the opposite
150 of the order for movem! */
151
152
153 void
154 output_function_prologue (stream, size)
155 FILE *stream;
156 int size;
157 {
158 register int regno;
159 register int mask = 0;
160 int num_saved_regs = 0;
161 extern char call_used_regs[];
162 int fsize = (size + 3) & -4;
163
164
165 if (frame_pointer_needed)
166 {
167 if (fsize == 0 && TARGET_68040)
168 {
169 /* on the 68040, pea + move is faster than link.w 0 */
170 #ifdef MOTOROLA
171 asm_fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
172 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
173 reg_names[FRAME_POINTER_REGNUM]);
174 #else
175 asm_fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
176 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
177 reg_names[FRAME_POINTER_REGNUM]);
178 #endif
179 }
180 else if (fsize < 0x8000)
181 {
182 #ifdef MOTOROLA
183 asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
184 reg_names[FRAME_POINTER_REGNUM], -fsize);
185 #else
186 asm_fprintf (stream, "\tlink %s,%0I%d\n",
187 reg_names[FRAME_POINTER_REGNUM], -fsize);
188 #endif
189 }
190 else if (TARGET_68020)
191 {
192 #ifdef MOTOROLA
193 asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
194 reg_names[FRAME_POINTER_REGNUM], -fsize);
195 #else
196 asm_fprintf (stream, "\tlink %s,%0I%d\n",
197 reg_names[FRAME_POINTER_REGNUM], -fsize);
198 #endif
199 }
200 else
201 {
202 /* Adding negative number is faster on the 68040. */
203 #ifdef MOTOROLA
204 asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
205 reg_names[FRAME_POINTER_REGNUM], -fsize);
206 #else
207 asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
208 reg_names[FRAME_POINTER_REGNUM], -fsize);
209 #endif
210 }
211 }
212 else if (fsize)
213 {
214 if (fsize + 4 < 0x8000)
215 {
216 #ifdef NO_ADDSUB_Q
217 if (fsize + 4 <= 8)
218 {
219 if (!TARGET_5200)
220 {
221 /* asm_fprintf() cannot handle %. */
222 #ifdef MOTOROLA
223 asm_fprintf (stream, "\tsubq.w %OI%d,%Rsp\n", fsize + 4);
224 #else
225 asm_fprintf (stream, "\tsubqw %OI%d,%Rsp\n", fsize + 4);
226 #endif
227 }
228 else
229 {
230 /* asm_fprintf() cannot handle %. */
231 #ifdef MOTOROLA
232 asm_fprintf (stream, "\tsubq.l %OI%d,%Rsp\n", fsize + 4);
233 #else
234 asm_fprintf (stream, "\tsubql %OI%d,%Rsp\n", fsize + 4);
235 #endif
236 }
237 }
238 else if (fsize + 4 <= 16 && TARGET_CPU32)
239 {
240 /* On the CPU32 it is faster to use two subqw instructions to
241 subtract a small integer (8 < N <= 16) to a register. */
242 /* asm_fprintf() cannot handle %. */
243 #ifdef MOTOROLA
244 asm_fprintf (stream, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
245 fsize + 4);
246 #else
247 asm_fprintf (stream, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
248 fsize + 4);
249 #endif
250 }
251 else
252 #endif /* NO_ADDSUB_Q */
253 if (TARGET_68040)
254 {
255 /* Adding negative number is faster on the 68040. */
256 /* asm_fprintf() cannot handle %. */
257 #ifdef MOTOROLA
258 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
259 #else
260 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
261 #endif
262 }
263 else
264 {
265 #ifdef MOTOROLA
266 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
267 #else
268 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
269 #endif
270 }
271 }
272 else
273 {
274 /* asm_fprintf() cannot handle %. */
275 #ifdef MOTOROLA
276 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
277 #else
278 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
279 #endif
280 }
281 }
282 #ifdef SUPPORT_SUN_FPA
283 for (regno = 24; regno < 56; regno++)
284 if (regs_ever_live[regno] && ! call_used_regs[regno])
285 {
286 #ifdef MOTOROLA
287 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
288 reg_names[regno]);
289 #else
290 asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
291 reg_names[regno]);
292 #endif
293 }
294 #endif
295 if (TARGET_68881)
296 {
297 for (regno = 16; regno < 24; regno++)
298 if (regs_ever_live[regno] && ! call_used_regs[regno])
299 mask |= 1 << (regno - 16);
300 if ((mask & 0xff) != 0)
301 {
302 #ifdef MOTOROLA
303 asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
304 #else
305 asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
306 #endif
307 }
308 mask = 0;
309 }
310 for (regno = 0; regno < 16; regno++)
311 if (regs_ever_live[regno] && ! call_used_regs[regno])
312 {
313 mask |= 1 << (15 - regno);
314 num_saved_regs++;
315 }
316 if (frame_pointer_needed)
317 {
318 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
319 num_saved_regs--;
320 }
321
322 #if NEED_PROBE
323 #ifdef MOTOROLA
324 #ifdef CRDS
325 asm_fprintf (stream, "\ttstl %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
326 #else
327 asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
328 #endif
329 #else
330 asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
331 #endif
332 #endif
333
334 if (num_saved_regs <= 2)
335 {
336 /* Store each separately in the same order moveml uses.
337 Using two movel instructions instead of a single moveml
338 is about 15% faster for the 68020 and 68030 at no expense
339 in code size */
340
341 int i;
342
343 /* Undo the work from above. */
344 for (i = 0; i< 16; i++)
345 if (mask & (1 << i))
346 asm_fprintf (stream,
347 #ifdef MOTOROLA
348 "\t%Omove.l %s,-(%Rsp)\n",
349 #else
350 "\tmovel %s,%Rsp@-\n",
351 #endif
352 reg_names[15 - i]);
353 }
354 else if (mask)
355 {
356 if (TARGET_5200)
357 {
358 /* The coldfire does not support the predecrement form of the
359 movml instruction, so we must adjust the stack pointer and
360 then use the plain address register indirect mode. We also
361 have to invert the register save mask to use the new mode.
362
363 FIXME: if num_saved_regs was calculated earlier, we could
364 combine the stack pointer adjustment with any adjustment
365 done when the initial stack frame is created. This would
366 save an instruction */
367
368 int newmask = 0;
369 int i;
370
371 for (i = 0; i < 16; i++)
372 if (mask & (1 << i))
373 newmask |= (1 << (15-i));
374
375 #ifdef MOTOROLA
376 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
377 asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
378 #else
379 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
380 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
381 #endif
382 }
383 else
384 {
385 #ifdef MOTOROLA
386 asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
387 #else
388 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
389 #endif
390 }
391 }
392 if (flag_pic && current_function_uses_pic_offset_table)
393 {
394 #ifdef MOTOROLA
395 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
396 reg_names[PIC_OFFSET_TABLE_REGNUM]);
397 #else
398 asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
399 reg_names[PIC_OFFSET_TABLE_REGNUM]);
400 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
401 reg_names[PIC_OFFSET_TABLE_REGNUM],
402 reg_names[PIC_OFFSET_TABLE_REGNUM]);
403 #endif
404 }
405 }
406 \f
407 /* Return true if this function's epilogue can be output as RTL. */
408
409 int
410 use_return_insn ()
411 {
412 int regno;
413
414 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
415 return 0;
416
417 /* Copied from output_function_epilogue (). We should probably create a
418 separate layout routine to perform the common work. */
419
420 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
421 if (regs_ever_live[regno] && ! call_used_regs[regno])
422 return 0;
423
424 return 1;
425 }
426
427 /* This function generates the assembly code for function exit,
428 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
429
430 The function epilogue should not depend on the current stack pointer!
431 It should use the frame pointer only, if there is a frame pointer.
432 This is mandatory because of alloca; we also take advantage of it to
433 omit stack adjustments before returning. */
434
435 void
436 output_function_epilogue (stream, size)
437 FILE *stream;
438 int size;
439 {
440 register int regno;
441 register int mask, fmask;
442 register int nregs;
443 int offset, foffset, fpoffset;
444 extern char call_used_regs[];
445 int fsize = (size + 3) & -4;
446 int big = 0;
447 rtx insn = get_last_insn ();
448 int restore_from_sp = 0;
449
450 /* If the last insn was a BARRIER, we don't have to write any code. */
451 if (GET_CODE (insn) == NOTE)
452 insn = prev_nonnote_insn (insn);
453 if (insn && GET_CODE (insn) == BARRIER)
454 {
455 /* Output just a no-op so that debuggers don't get confused
456 about which function the pc is in at this address. */
457 asm_fprintf (stream, "\tnop\n");
458 return;
459 }
460
461 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
462 if (profile_block_flag == 2)
463 {
464 FUNCTION_BLOCK_PROFILER_EXIT (stream);
465 }
466 #endif
467
468 #ifdef FUNCTION_EXTRA_EPILOGUE
469 FUNCTION_EXTRA_EPILOGUE (stream, size);
470 #endif
471 nregs = 0; fmask = 0; fpoffset = 0;
472 #ifdef SUPPORT_SUN_FPA
473 for (regno = 24 ; regno < 56 ; regno++)
474 if (regs_ever_live[regno] && ! call_used_regs[regno])
475 nregs++;
476 fpoffset = nregs * 8;
477 #endif
478 nregs = 0;
479 if (TARGET_68881)
480 {
481 for (regno = 16; regno < 24; regno++)
482 if (regs_ever_live[regno] && ! call_used_regs[regno])
483 {
484 nregs++;
485 fmask |= 1 << (23 - regno);
486 }
487 }
488 foffset = fpoffset + nregs * 12;
489 nregs = 0; mask = 0;
490 if (frame_pointer_needed)
491 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
492 for (regno = 0; regno < 16; regno++)
493 if (regs_ever_live[regno] && ! call_used_regs[regno])
494 {
495 nregs++;
496 mask |= 1 << regno;
497 }
498 offset = foffset + nregs * 4;
499 /* FIXME : leaf_function_p below is too strong.
500 What we really need to know there is if there could be pending
501 stack adjustment needed at that point. */
502 restore_from_sp = ! frame_pointer_needed
503 || (! current_function_calls_alloca && leaf_function_p ());
504 if (offset + fsize >= 0x8000
505 && ! restore_from_sp
506 && (mask || fmask || fpoffset))
507 {
508 #ifdef MOTOROLA
509 asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
510 #else
511 asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
512 #endif
513 fsize = 0, big = 1;
514 }
515 if (TARGET_5200 || nregs <= 2)
516 {
517 /* Restore each separately in the same order moveml does.
518 Using two movel instructions instead of a single moveml
519 is about 15% faster for the 68020 and 68030 at no expense
520 in code size. */
521
522 int i;
523
524 /* Undo the work from above. */
525 for (i = 0; i< 16; i++)
526 if (mask & (1 << i))
527 {
528 if (big)
529 {
530 #ifdef MOTOROLA
531 asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
532 offset + fsize,
533 reg_names[FRAME_POINTER_REGNUM],
534 reg_names[i]);
535 #else
536 asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
537 reg_names[FRAME_POINTER_REGNUM],
538 offset + fsize, reg_names[i]);
539 #endif
540 }
541 else if (restore_from_sp)
542 {
543 #ifdef MOTOROLA
544 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
545 reg_names[i]);
546 #else
547 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
548 reg_names[i]);
549 #endif
550 }
551 else
552 {
553 #ifdef MOTOROLA
554 asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
555 offset + fsize,
556 reg_names[FRAME_POINTER_REGNUM],
557 reg_names[i]);
558 #else
559 asm_fprintf (stream, "\tmovel %s@(-%d),%s\n",
560 reg_names[FRAME_POINTER_REGNUM],
561 offset + fsize, reg_names[i]);
562 #endif
563 }
564 offset = offset - 4;
565 }
566 }
567 else if (mask)
568 {
569 if (big)
570 {
571 #ifdef MOTOROLA
572 asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
573 offset + fsize,
574 reg_names[FRAME_POINTER_REGNUM],
575 mask);
576 #else
577 asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
578 reg_names[FRAME_POINTER_REGNUM],
579 offset + fsize, mask);
580 #endif
581 }
582 else if (restore_from_sp)
583 {
584 #ifdef MOTOROLA
585 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
586 #else
587 asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
588 #endif
589 }
590 else
591 {
592 #ifdef MOTOROLA
593 asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
594 offset + fsize,
595 reg_names[FRAME_POINTER_REGNUM],
596 mask);
597 #else
598 asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
599 reg_names[FRAME_POINTER_REGNUM],
600 offset + fsize, mask);
601 #endif
602 }
603 }
604 if (fmask)
605 {
606 if (big)
607 {
608 #ifdef MOTOROLA
609 asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
610 foffset + fsize,
611 reg_names[FRAME_POINTER_REGNUM],
612 fmask);
613 #else
614 asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
615 reg_names[FRAME_POINTER_REGNUM],
616 foffset + fsize, fmask);
617 #endif
618 }
619 else if (restore_from_sp)
620 {
621 #ifdef MOTOROLA
622 asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
623 #else
624 asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
625 #endif
626 }
627 else
628 {
629 #ifdef MOTOROLA
630 asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
631 foffset + fsize,
632 reg_names[FRAME_POINTER_REGNUM],
633 fmask);
634 #else
635 asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
636 reg_names[FRAME_POINTER_REGNUM],
637 foffset + fsize, fmask);
638 #endif
639 }
640 }
641 if (fpoffset != 0)
642 for (regno = 55; regno >= 24; regno--)
643 if (regs_ever_live[regno] && ! call_used_regs[regno])
644 {
645 if (big)
646 {
647 #ifdef MOTOROLA
648 asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
649 fpoffset + fsize,
650 reg_names[FRAME_POINTER_REGNUM],
651 reg_names[regno]);
652 #else
653 asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
654 reg_names[FRAME_POINTER_REGNUM],
655 fpoffset + fsize, reg_names[regno]);
656 #endif
657 }
658 else if (restore_from_sp)
659 {
660 #ifdef MOTOROLA
661 asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
662 reg_names[regno]);
663 #else
664 asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
665 reg_names[regno]);
666 #endif
667 }
668 else
669 {
670 #ifdef MOTOROLA
671 asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n",
672 fpoffset + fsize,
673 reg_names[FRAME_POINTER_REGNUM],
674 reg_names[regno]);
675 #else
676 asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
677 reg_names[FRAME_POINTER_REGNUM],
678 fpoffset + fsize, reg_names[regno]);
679 #endif
680 }
681 fpoffset -= 8;
682 }
683 if (frame_pointer_needed)
684 fprintf (stream, "\tunlk %s\n",
685 reg_names[FRAME_POINTER_REGNUM]);
686 else if (fsize)
687 {
688 #ifdef NO_ADDSUB_Q
689 if (fsize + 4 <= 8)
690 {
691 if (!TARGET_5200)
692 {
693 #ifdef MOTOROLA
694 asm_fprintf (stream, "\taddq.w %OI%d,%Rsp\n", fsize + 4);
695 #else
696 asm_fprintf (stream, "\taddqw %OI%d,%Rsp\n", fsize + 4);
697 #endif
698 }
699 else
700 {
701 #ifdef MOTOROLA
702 asm_fprintf (stream, "\taddq.l %OI%d,%Rsp\n", fsize + 4);
703 #else
704 asm_fprintf (stream, "\taddql %OI%d,%Rsp\n", fsize + 4);
705 #endif
706 }
707 }
708 else if (fsize + 4 <= 16 && TARGET_CPU32)
709 {
710 /* On the CPU32 it is faster to use two addqw instructions to
711 add a small integer (8 < N <= 16) to a register. */
712 /* asm_fprintf() cannot handle %. */
713 #ifdef MOTOROLA
714 asm_fprintf (stream, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
715 fsize + 4);
716 #else
717 asm_fprintf (stream, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
718 fsize + 4);
719 #endif
720 }
721 else
722 #endif /* NO_ADDSUB_Q */
723 if (fsize + 4 < 0x8000)
724 {
725 if (TARGET_68040)
726 {
727 /* asm_fprintf() cannot handle %. */
728 #ifdef MOTOROLA
729 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
730 #else
731 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
732 #endif
733 }
734 else
735 {
736 #ifdef MOTOROLA
737 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
738 #else
739 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
740 #endif
741 }
742 }
743 else
744 {
745 /* asm_fprintf() cannot handle %. */
746 #ifdef MOTOROLA
747 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
748 #else
749 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
750 #endif
751 }
752 }
753 if (current_function_pops_args)
754 asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
755 else
756 fprintf (stream, "\trts\n");
757 }
758 \f
759 /* Similar to general_operand, but exclude stack_pointer_rtx. */
760
761 int
762 not_sp_operand (op, mode)
763 register rtx op;
764 enum machine_mode mode;
765 {
766 return op != stack_pointer_rtx && general_operand (op, mode);
767 }
768
769 /* Return TRUE if X is a valid comparison operator for the dbcc
770 instruction.
771
772 Note it rejects floating point comparison operators.
773 (In the future we could use Fdbcc).
774
775 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
776
777 int
778 valid_dbcc_comparison_p (x, mode)
779 rtx x;
780 enum machine_mode mode;
781 {
782 switch (GET_CODE (x))
783 {
784 case EQ: case NE: case GTU: case LTU:
785 case GEU: case LEU:
786 return 1;
787
788 /* Reject some when CC_NO_OVERFLOW is set. This may be over
789 conservative */
790 case GT: case LT: case GE: case LE:
791 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
792 default:
793 return 0;
794 }
795 }
796
797 /* Return non-zero if flags are currently in the 68881 flag register. */
798 int
799 flags_in_68881 ()
800 {
801 /* We could add support for these in the future */
802 return cc_status.flags & CC_IN_68881;
803 }
804
805 /* Output a dbCC; jCC sequence. Note we do not handle the
806 floating point version of this sequence (Fdbcc). We also
807 do not handle alternative conditions when CC_NO_OVERFLOW is
808 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
809 kick those out before we get here. */
810
811 output_dbcc_and_branch (operands)
812 rtx *operands;
813 {
814 switch (GET_CODE (operands[3]))
815 {
816 case EQ:
817 #ifdef MOTOROLA
818 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
819 #else
820 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
821 #endif
822 break;
823
824 case NE:
825 #ifdef MOTOROLA
826 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
827 #else
828 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
829 #endif
830 break;
831
832 case GT:
833 #ifdef MOTOROLA
834 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
835 #else
836 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
837 #endif
838 break;
839
840 case GTU:
841 #ifdef MOTOROLA
842 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
843 #else
844 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
845 #endif
846 break;
847
848 case LT:
849 #ifdef MOTOROLA
850 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
851 #else
852 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
853 #endif
854 break;
855
856 case LTU:
857 #ifdef MOTOROLA
858 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
859 #else
860 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
861 #endif
862 break;
863
864 case GE:
865 #ifdef MOTOROLA
866 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
867 #else
868 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
869 #endif
870 break;
871
872 case GEU:
873 #ifdef MOTOROLA
874 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
875 #else
876 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
877 #endif
878 break;
879
880 case LE:
881 #ifdef MOTOROLA
882 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
883 #else
884 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
885 #endif
886 break;
887
888 case LEU:
889 #ifdef MOTOROLA
890 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
891 #else
892 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
893 #endif
894 break;
895
896 default:
897 abort ();
898 }
899
900 /* If the decrement is to be done in SImode, then we have
901 to compensate for the fact that dbcc decrements in HImode. */
902 switch (GET_MODE (operands[0]))
903 {
904 case SImode:
905 #ifdef MOTOROLA
906 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
907 #else
908 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
909 #endif
910 break;
911
912 case HImode:
913 break;
914
915 default:
916 abort ();
917 }
918 }
919
920 char *
921 output_scc_di(op, operand1, operand2, dest)
922 rtx op;
923 rtx operand1;
924 rtx operand2;
925 rtx dest;
926 {
927 rtx loperands[7];
928 enum rtx_code op_code = GET_CODE (op);
929
930 /* This does not produce a usefull cc. */
931 CC_STATUS_INIT;
932
933 /* The m68k cmp.l instruction requires operand1 to be a reg as used
934 below. Swap the operands and change the op if these requirements
935 are not fulfilled. */
936 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
937 {
938 rtx tmp = operand1;
939
940 operand1 = operand2;
941 operand2 = tmp;
942 op_code = swap_condition (op_code);
943 }
944 loperands[0] = operand1;
945 if (GET_CODE (operand1) == REG)
946 loperands[1] = gen_rtx (REG, SImode, REGNO (operand1) + 1);
947 else
948 loperands[1] = adj_offsettable_operand (operand1, 4);
949 if (operand2 != const0_rtx)
950 {
951 loperands[2] = operand2;
952 if (GET_CODE (operand2) == REG)
953 loperands[3] = gen_rtx (REG, SImode, REGNO (operand2) + 1);
954 else
955 loperands[3] = adj_offsettable_operand (operand2, 4);
956 }
957 loperands[4] = gen_label_rtx();
958 if (operand2 != const0_rtx)
959 #ifdef MOTOROLA
960 #ifdef SGS_CMP_ORDER
961 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
962 #else
963 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
964 #endif
965 #else
966 #ifdef SGS_CMP_ORDER
967 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
968 #else
969 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
970 #endif
971 #endif
972 else
973 #ifdef MOTOROLA
974 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands);
975 #else
976 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands);
977 #endif
978 loperands[5] = dest;
979
980 switch (op_code)
981 {
982 case EQ:
983 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
984 CODE_LABEL_NUMBER (loperands[4]));
985 output_asm_insn ("seq %5", loperands);
986 break;
987
988 case NE:
989 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
990 CODE_LABEL_NUMBER (loperands[4]));
991 output_asm_insn ("sne %5", loperands);
992 break;
993
994 case GT:
995 loperands[6] = gen_label_rtx();
996 #ifdef MOTOROLA
997 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
998 #else
999 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1000 #endif
1001 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1002 CODE_LABEL_NUMBER (loperands[4]));
1003 output_asm_insn ("sgt %5", loperands);
1004 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1005 CODE_LABEL_NUMBER (loperands[6]));
1006 break;
1007
1008 case GTU:
1009 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1010 CODE_LABEL_NUMBER (loperands[4]));
1011 output_asm_insn ("shi %5", loperands);
1012 break;
1013
1014 case LT:
1015 loperands[6] = gen_label_rtx();
1016 #ifdef MOTOROLA
1017 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1018 #else
1019 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1020 #endif
1021 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1022 CODE_LABEL_NUMBER (loperands[4]));
1023 output_asm_insn ("slt %5", loperands);
1024 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1025 CODE_LABEL_NUMBER (loperands[6]));
1026 break;
1027
1028 case LTU:
1029 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1030 CODE_LABEL_NUMBER (loperands[4]));
1031 output_asm_insn ("scs %5", loperands);
1032 break;
1033
1034 case GE:
1035 loperands[6] = gen_label_rtx();
1036 #ifdef MOTOROLA
1037 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1038 #else
1039 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1040 #endif
1041 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1042 CODE_LABEL_NUMBER (loperands[4]));
1043 output_asm_insn ("sge %5", loperands);
1044 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1045 CODE_LABEL_NUMBER (loperands[6]));
1046 break;
1047
1048 case GEU:
1049 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1050 CODE_LABEL_NUMBER (loperands[4]));
1051 output_asm_insn ("scc %5", loperands);
1052 break;
1053
1054 case LE:
1055 loperands[6] = gen_label_rtx();
1056 #ifdef MOTOROLA
1057 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1058 #else
1059 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1060 #endif
1061 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1062 CODE_LABEL_NUMBER (loperands[4]));
1063 output_asm_insn ("sle %5", loperands);
1064 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1065 CODE_LABEL_NUMBER (loperands[6]));
1066 break;
1067
1068 case LEU:
1069 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1070 CODE_LABEL_NUMBER (loperands[4]));
1071 output_asm_insn ("sls %5", loperands);
1072 break;
1073
1074 default:
1075 abort ();
1076 }
1077 return "";
1078 }
1079
1080 char *
1081 output_btst (operands, countop, dataop, insn, signpos)
1082 rtx *operands;
1083 rtx countop, dataop;
1084 rtx insn;
1085 int signpos;
1086 {
1087 operands[0] = countop;
1088 operands[1] = dataop;
1089
1090 if (GET_CODE (countop) == CONST_INT)
1091 {
1092 register int count = INTVAL (countop);
1093 /* If COUNT is bigger than size of storage unit in use,
1094 advance to the containing unit of same size. */
1095 if (count > signpos)
1096 {
1097 int offset = (count & ~signpos) / 8;
1098 count = count & signpos;
1099 operands[1] = dataop = adj_offsettable_operand (dataop, offset);
1100 }
1101 if (count == signpos)
1102 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1103 else
1104 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1105
1106 /* These three statements used to use next_insns_test_no...
1107 but it appears that this should do the same job. */
1108 if (count == 31
1109 && next_insn_tests_no_inequality (insn))
1110 return "tst%.l %1";
1111 if (count == 15
1112 && next_insn_tests_no_inequality (insn))
1113 return "tst%.w %1";
1114 if (count == 7
1115 && next_insn_tests_no_inequality (insn))
1116 return "tst%.b %1";
1117
1118 cc_status.flags = CC_NOT_NEGATIVE;
1119 }
1120 return "btst %0,%1";
1121 }
1122 \f
1123 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1124 reference and a constant. */
1125
1126 int
1127 symbolic_operand (op, mode)
1128 register rtx op;
1129 enum machine_mode mode;
1130 {
1131 switch (GET_CODE (op))
1132 {
1133 case SYMBOL_REF:
1134 case LABEL_REF:
1135 return 1;
1136
1137 case CONST:
1138 op = XEXP (op, 0);
1139 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1140 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1141 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1142
1143 #if 0 /* Deleted, with corresponding change in m68k.h,
1144 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1145 case CONST_DOUBLE:
1146 return GET_MODE (op) == mode;
1147 #endif
1148
1149 default:
1150 return 0;
1151 }
1152 }
1153 \f
1154 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1155
1156 int
1157 extend_operator(x, mode)
1158 rtx x;
1159 enum machine_mode mode;
1160 {
1161 if (mode != VOIDmode && GET_MODE(x) != mode)
1162 return 0;
1163 switch (GET_CODE(x))
1164 {
1165 case SIGN_EXTEND :
1166 case ZERO_EXTEND :
1167 return 1;
1168 default :
1169 return 0;
1170 }
1171 }
1172
1173 \f
1174 /* Legitimize PIC addresses. If the address is already
1175 position-independent, we return ORIG. Newly generated
1176 position-independent addresses go to REG. If we need more
1177 than one register, we lose.
1178
1179 An address is legitimized by making an indirect reference
1180 through the Global Offset Table with the name of the symbol
1181 used as an offset.
1182
1183 The assembler and linker are responsible for placing the
1184 address of the symbol in the GOT. The function prologue
1185 is responsible for initializing a5 to the starting address
1186 of the GOT.
1187
1188 The assembler is also responsible for translating a symbol name
1189 into a constant displacement from the start of the GOT.
1190
1191 A quick example may make things a little clearer:
1192
1193 When not generating PIC code to store the value 12345 into _foo
1194 we would generate the following code:
1195
1196 movel #12345, _foo
1197
1198 When generating PIC two transformations are made. First, the compiler
1199 loads the address of foo into a register. So the first transformation makes:
1200
1201 lea _foo, a0
1202 movel #12345, a0@
1203
1204 The code in movsi will intercept the lea instruction and call this
1205 routine which will transform the instructions into:
1206
1207 movel a5@(_foo:w), a0
1208 movel #12345, a0@
1209
1210
1211 That (in a nutshell) is how *all* symbol and label references are
1212 handled. */
1213
1214 rtx
1215 legitimize_pic_address (orig, mode, reg)
1216 rtx orig, reg;
1217 enum machine_mode mode;
1218 {
1219 rtx pic_ref = orig;
1220
1221 /* First handle a simple SYMBOL_REF or LABEL_REF */
1222 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1223 {
1224 if (reg == 0)
1225 abort ();
1226
1227 pic_ref = gen_rtx (MEM, Pmode,
1228 gen_rtx (PLUS, Pmode,
1229 pic_offset_table_rtx, orig));
1230 current_function_uses_pic_offset_table = 1;
1231 RTX_UNCHANGING_P (pic_ref) = 1;
1232 emit_move_insn (reg, pic_ref);
1233 return reg;
1234 }
1235 else if (GET_CODE (orig) == CONST)
1236 {
1237 rtx base, offset;
1238
1239 /* Make sure this is CONST has not already been legitimized */
1240 if (GET_CODE (XEXP (orig, 0)) == PLUS
1241 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1242 return orig;
1243
1244 if (reg == 0)
1245 abort ();
1246
1247 /* legitimize both operands of the PLUS */
1248 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1249 {
1250 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1251 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1252 base == reg ? 0 : reg);
1253 }
1254 else abort ();
1255
1256 if (GET_CODE (orig) == CONST_INT)
1257 return plus_constant_for_output (base, INTVAL (orig));
1258 pic_ref = gen_rtx (PLUS, Pmode, base, orig);
1259 /* Likewise, should we set special REG_NOTEs here? */
1260 }
1261 return pic_ref;
1262 }
1263
1264 \f
1265 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1266
1267 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1268
1269 CONST_METHOD
1270 const_method (constant)
1271 rtx constant;
1272 {
1273 int i;
1274 unsigned u;
1275
1276 i = INTVAL (constant);
1277 if (USE_MOVQ (i))
1278 return MOVQ;
1279
1280 /* The Coldfire doesn't have byte or word operations. */
1281 /* FIXME: This may not be useful for the m68060 either */
1282 if (!TARGET_5200)
1283 {
1284 /* if -256 < N < 256 but N is not in range for a moveq
1285 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1286 if (USE_MOVQ (i ^ 0xff))
1287 return NOTB;
1288 /* Likewise, try with not.w */
1289 if (USE_MOVQ (i ^ 0xffff))
1290 return NOTW;
1291 /* This is the only value where neg.w is useful */
1292 if (i == -65408)
1293 return NEGW;
1294 /* Try also with swap */
1295 u = i;
1296 if (USE_MOVQ ((u >> 16) | (u << 16)))
1297 return SWAP;
1298 }
1299 /* Otherwise, use move.l */
1300 return MOVL;
1301 }
1302
1303 const_int_cost (constant)
1304 rtx constant;
1305 {
1306 switch (const_method (constant))
1307 {
1308 case MOVQ :
1309 /* Constants between -128 and 127 are cheap due to moveq */
1310 return 0;
1311 case NOTB :
1312 case NOTW :
1313 case NEGW :
1314 case SWAP :
1315 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1316 return 1;
1317 case MOVL :
1318 return 2;
1319 default :
1320 abort ();
1321 }
1322 }
1323
1324 char *
1325 output_move_const_into_data_reg (operands)
1326 rtx *operands;
1327 {
1328 int i;
1329
1330 i = INTVAL (operands[1]);
1331 switch (const_method (operands[1]))
1332 {
1333 case MOVQ :
1334 #if defined (MOTOROLA) && !defined (CRDS)
1335 return "moveq%.l %1,%0";
1336 #else
1337 return "moveq %1,%0";
1338 #endif
1339 case NOTB :
1340 operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xff);
1341 #if defined (MOTOROLA) && !defined (CRDS)
1342 return "moveq%.l %1,%0\n\tnot%.b %0";
1343 #else
1344 return "moveq %1,%0\n\tnot%.b %0";
1345 #endif
1346 case NOTW :
1347 operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xffff);
1348 #if defined (MOTOROLA) && !defined (CRDS)
1349 return "moveq%.l %1,%0\n\tnot%.w %0";
1350 #else
1351 return "moveq %1,%0\n\tnot%.w %0";
1352 #endif
1353 case NEGW :
1354 #if defined (MOTOROLA) && !defined (CRDS)
1355 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1356 #else
1357 return "moveq %#-128,%0\n\tneg%.w %0";
1358 #endif
1359 case SWAP :
1360 {
1361 unsigned u = i;
1362
1363 operands[1] = gen_rtx (CONST_INT, VOIDmode, (u << 16) | (u >> 16));
1364 #if defined (MOTOROLA) && !defined (CRDS)
1365 return "moveq%.l %1,%0\n\tswap %0";
1366 #else
1367 return "moveq %1,%0\n\tswap %0";
1368 #endif
1369 }
1370 case MOVL :
1371 return "move%.l %1,%0";
1372 default :
1373 abort ();
1374 }
1375 }
1376
1377 char *
1378 output_move_simode_const (operands)
1379 rtx *operands;
1380 {
1381 if (operands[1] == const0_rtx
1382 && (DATA_REG_P (operands[0])
1383 || GET_CODE (operands[0]) == MEM)
1384 /* clr insns on 68000 read before writing.
1385 This isn't so on the 68010, but we have no TARGET_68010. */
1386 && ((TARGET_68020 || TARGET_5200)
1387 || !(GET_CODE (operands[0]) == MEM
1388 && MEM_VOLATILE_P (operands[0]))))
1389 return "clr%.l %0";
1390 else if (DATA_REG_P (operands[0]))
1391 return output_move_const_into_data_reg (operands);
1392 else if (ADDRESS_REG_P (operands[0])
1393 && INTVAL (operands[1]) < 0x8000
1394 && INTVAL (operands[1]) >= -0x8000)
1395 return "move%.w %1,%0";
1396 else if (GET_CODE (operands[0]) == MEM
1397 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1398 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1399 && INTVAL (operands[1]) < 0x8000
1400 && INTVAL (operands[1]) >= -0x8000)
1401 return "pea %a1";
1402 return "move%.l %1,%0";
1403 }
1404
1405 /* Return the best assembler insn template
1406 for moving operands[1] into operands[0] as a fullword. */
1407
1408 static char *
1409 singlemove_string (operands)
1410 rtx *operands;
1411 {
1412 #ifdef SUPPORT_SUN_FPA
1413 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1414 return "fpmoves %1,%0";
1415 #endif
1416 if (GET_CODE (operands[1]) == CONST_INT)
1417 return output_move_simode_const (operands);
1418 return "move%.l %1,%0";
1419 }
1420
1421
1422 /* Output assembler code to perform a doubleword move insn
1423 with operands OPERANDS. */
1424
1425 char *
1426 output_move_double (operands)
1427 rtx *operands;
1428 {
1429 enum
1430 {
1431 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1432 } optype0, optype1;
1433 rtx latehalf[2];
1434 rtx middlehalf[2];
1435 rtx xops[2];
1436 rtx addreg0 = 0, addreg1 = 0;
1437 int dest_overlapped_low = 0;
1438 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1439
1440 middlehalf[0] = 0;
1441 middlehalf[1] = 0;
1442
1443 /* First classify both operands. */
1444
1445 if (REG_P (operands[0]))
1446 optype0 = REGOP;
1447 else if (offsettable_memref_p (operands[0]))
1448 optype0 = OFFSOP;
1449 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1450 optype0 = POPOP;
1451 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1452 optype0 = PUSHOP;
1453 else if (GET_CODE (operands[0]) == MEM)
1454 optype0 = MEMOP;
1455 else
1456 optype0 = RNDOP;
1457
1458 if (REG_P (operands[1]))
1459 optype1 = REGOP;
1460 else if (CONSTANT_P (operands[1]))
1461 optype1 = CNSTOP;
1462 else if (offsettable_memref_p (operands[1]))
1463 optype1 = OFFSOP;
1464 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1465 optype1 = POPOP;
1466 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1467 optype1 = PUSHOP;
1468 else if (GET_CODE (operands[1]) == MEM)
1469 optype1 = MEMOP;
1470 else
1471 optype1 = RNDOP;
1472
1473 /* Check for the cases that the operand constraints are not
1474 supposed to allow to happen. Abort if we get one,
1475 because generating code for these cases is painful. */
1476
1477 if (optype0 == RNDOP || optype1 == RNDOP)
1478 abort ();
1479
1480 /* If one operand is decrementing and one is incrementing
1481 decrement the former register explicitly
1482 and change that operand into ordinary indexing. */
1483
1484 if (optype0 == PUSHOP && optype1 == POPOP)
1485 {
1486 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1487 if (size == 12)
1488 output_asm_insn ("sub%.l %#12,%0", operands);
1489 else
1490 output_asm_insn ("subq%.l %#8,%0", operands);
1491 if (GET_MODE (operands[1]) == XFmode)
1492 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
1493 else if (GET_MODE (operands[0]) == DFmode)
1494 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
1495 else
1496 operands[0] = gen_rtx (MEM, DImode, operands[0]);
1497 optype0 = OFFSOP;
1498 }
1499 if (optype0 == POPOP && optype1 == PUSHOP)
1500 {
1501 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1502 if (size == 12)
1503 output_asm_insn ("sub%.l %#12,%1", operands);
1504 else
1505 output_asm_insn ("subq%.l %#8,%1", operands);
1506 if (GET_MODE (operands[1]) == XFmode)
1507 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
1508 else if (GET_MODE (operands[1]) == DFmode)
1509 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
1510 else
1511 operands[1] = gen_rtx (MEM, DImode, operands[1]);
1512 optype1 = OFFSOP;
1513 }
1514
1515 /* If an operand is an unoffsettable memory ref, find a register
1516 we can increment temporarily to make it refer to the second word. */
1517
1518 if (optype0 == MEMOP)
1519 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1520
1521 if (optype1 == MEMOP)
1522 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1523
1524 /* Ok, we can do one word at a time.
1525 Normally we do the low-numbered word first,
1526 but if either operand is autodecrementing then we
1527 do the high-numbered word first.
1528
1529 In either case, set up in LATEHALF the operands to use
1530 for the high-numbered word and in some cases alter the
1531 operands in OPERANDS to be suitable for the low-numbered word. */
1532
1533 if (size == 12)
1534 {
1535 if (optype0 == REGOP)
1536 {
1537 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
1538 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1539 }
1540 else if (optype0 == OFFSOP)
1541 {
1542 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1543 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1544 }
1545 else
1546 {
1547 middlehalf[0] = operands[0];
1548 latehalf[0] = operands[0];
1549 }
1550
1551 if (optype1 == REGOP)
1552 {
1553 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1554 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1555 }
1556 else if (optype1 == OFFSOP)
1557 {
1558 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1559 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1560 }
1561 else if (optype1 == CNSTOP)
1562 {
1563 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1564 {
1565 REAL_VALUE_TYPE r;
1566 long l[3];
1567
1568 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1569 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1570 operands[1] = GEN_INT (l[0]);
1571 middlehalf[1] = GEN_INT (l[1]);
1572 latehalf[1] = GEN_INT (l[2]);
1573 }
1574 else if (CONSTANT_P (operands[1]))
1575 {
1576 /* actually, no non-CONST_DOUBLE constant should ever
1577 appear here. */
1578 abort ();
1579 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
1580 latehalf[1] = constm1_rtx;
1581 else
1582 latehalf[1] = const0_rtx;
1583 }
1584 }
1585 else
1586 {
1587 middlehalf[1] = operands[1];
1588 latehalf[1] = operands[1];
1589 }
1590 }
1591 else
1592 /* size is not 12: */
1593 {
1594 if (optype0 == REGOP)
1595 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1596 else if (optype0 == OFFSOP)
1597 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1598 else
1599 latehalf[0] = operands[0];
1600
1601 if (optype1 == REGOP)
1602 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1603 else if (optype1 == OFFSOP)
1604 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1605 else if (optype1 == CNSTOP)
1606 split_double (operands[1], &operands[1], &latehalf[1]);
1607 else
1608 latehalf[1] = operands[1];
1609 }
1610
1611 /* If insn is effectively movd N(sp),-(sp) then we will do the
1612 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1613 for the low word as well, to compensate for the first decrement of sp. */
1614 if (optype0 == PUSHOP
1615 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1616 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1617 operands[1] = middlehalf[1] = latehalf[1];
1618
1619 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1620 if the upper part of reg N does not appear in the MEM, arrange to
1621 emit the move late-half first. Otherwise, compute the MEM address
1622 into the upper part of N and use that as a pointer to the memory
1623 operand. */
1624 if (optype0 == REGOP
1625 && (optype1 == OFFSOP || optype1 == MEMOP))
1626 {
1627 rtx testlow = gen_rtx (REG, SImode, REGNO (operands[0]));
1628
1629 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
1630 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1631 {
1632 /* If both halves of dest are used in the src memory address,
1633 compute the address into latehalf of dest.
1634 Note that this can't happen if the dest is two data regs. */
1635 compadr:
1636 xops[0] = latehalf[0];
1637 xops[1] = XEXP (operands[1], 0);
1638 output_asm_insn ("lea %a1,%0", xops);
1639 if( GET_MODE (operands[1]) == XFmode )
1640 {
1641 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
1642 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1643 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1644 }
1645 else
1646 {
1647 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
1648 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1649 }
1650 }
1651 else if (size == 12
1652 && reg_overlap_mentioned_p (middlehalf[0],
1653 XEXP (operands[1], 0)))
1654 {
1655 /* Check for two regs used by both source and dest.
1656 Note that this can't happen if the dest is all data regs.
1657 It can happen if the dest is d6, d7, a0.
1658 But in that case, latehalf is an addr reg, so
1659 the code at compadr does ok. */
1660
1661 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
1662 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1663 goto compadr;
1664
1665 /* JRV says this can't happen: */
1666 if (addreg0 || addreg1)
1667 abort ();
1668
1669 /* Only the middle reg conflicts; simply put it last. */
1670 output_asm_insn (singlemove_string (operands), operands);
1671 output_asm_insn (singlemove_string (latehalf), latehalf);
1672 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1673 return "";
1674 }
1675 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
1676 /* If the low half of dest is mentioned in the source memory
1677 address, the arrange to emit the move late half first. */
1678 dest_overlapped_low = 1;
1679 }
1680
1681 /* If one or both operands autodecrementing,
1682 do the two words, high-numbered first. */
1683
1684 /* Likewise, the first move would clobber the source of the second one,
1685 do them in the other order. This happens only for registers;
1686 such overlap can't happen in memory unless the user explicitly
1687 sets it up, and that is an undefined circumstance. */
1688
1689 if (optype0 == PUSHOP || optype1 == PUSHOP
1690 || (optype0 == REGOP && optype1 == REGOP
1691 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1692 || REGNO (operands[0]) == REGNO (latehalf[1])))
1693 || dest_overlapped_low)
1694 {
1695 /* Make any unoffsettable addresses point at high-numbered word. */
1696 if (addreg0)
1697 {
1698 if (size == 12)
1699 output_asm_insn ("addq%.l %#8,%0", &addreg0);
1700 else
1701 output_asm_insn ("addq%.l %#4,%0", &addreg0);
1702 }
1703 if (addreg1)
1704 {
1705 if (size == 12)
1706 output_asm_insn ("addq%.l %#8,%0", &addreg1);
1707 else
1708 output_asm_insn ("addq%.l %#4,%0", &addreg1);
1709 }
1710
1711 /* Do that word. */
1712 output_asm_insn (singlemove_string (latehalf), latehalf);
1713
1714 /* Undo the adds we just did. */
1715 if (addreg0)
1716 output_asm_insn ("subq%.l %#4,%0", &addreg0);
1717 if (addreg1)
1718 output_asm_insn ("subq%.l %#4,%0", &addreg1);
1719
1720 if (size == 12)
1721 {
1722 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1723 if (addreg0)
1724 output_asm_insn ("subq%.l %#4,%0", &addreg0);
1725 if (addreg1)
1726 output_asm_insn ("subq%.l %#4,%0", &addreg1);
1727 }
1728
1729 /* Do low-numbered word. */
1730 return singlemove_string (operands);
1731 }
1732
1733 /* Normal case: do the two words, low-numbered first. */
1734
1735 output_asm_insn (singlemove_string (operands), operands);
1736
1737 /* Do the middle one of the three words for long double */
1738 if (size == 12)
1739 {
1740 if (addreg0)
1741 output_asm_insn ("addq%.l %#4,%0", &addreg0);
1742 if (addreg1)
1743 output_asm_insn ("addq%.l %#4,%0", &addreg1);
1744
1745 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1746 }
1747
1748 /* Make any unoffsettable addresses point at high-numbered word. */
1749 if (addreg0)
1750 output_asm_insn ("addq%.l %#4,%0", &addreg0);
1751 if (addreg1)
1752 output_asm_insn ("addq%.l %#4,%0", &addreg1);
1753
1754 /* Do that word. */
1755 output_asm_insn (singlemove_string (latehalf), latehalf);
1756
1757 /* Undo the adds we just did. */
1758 if (addreg0)
1759 {
1760 if (size == 12)
1761 output_asm_insn ("subq%.l %#8,%0", &addreg0);
1762 else
1763 output_asm_insn ("subq%.l %#4,%0", &addreg0);
1764 }
1765 if (addreg1)
1766 {
1767 if (size == 12)
1768 output_asm_insn ("subq%.l %#8,%0", &addreg1);
1769 else
1770 output_asm_insn ("subq%.l %#4,%0", &addreg1);
1771 }
1772
1773 return "";
1774 }
1775
1776 /* Return a REG that occurs in ADDR with coefficient 1.
1777 ADDR can be effectively incremented by incrementing REG. */
1778
1779 static rtx
1780 find_addr_reg (addr)
1781 rtx addr;
1782 {
1783 while (GET_CODE (addr) == PLUS)
1784 {
1785 if (GET_CODE (XEXP (addr, 0)) == REG)
1786 addr = XEXP (addr, 0);
1787 else if (GET_CODE (XEXP (addr, 1)) == REG)
1788 addr = XEXP (addr, 1);
1789 else if (CONSTANT_P (XEXP (addr, 0)))
1790 addr = XEXP (addr, 1);
1791 else if (CONSTANT_P (XEXP (addr, 1)))
1792 addr = XEXP (addr, 0);
1793 else
1794 abort ();
1795 }
1796 if (GET_CODE (addr) == REG)
1797 return addr;
1798 abort ();
1799 }
1800 \f
1801 /* Store in cc_status the expressions that the condition codes will
1802 describe after execution of an instruction whose pattern is EXP.
1803 Do not alter them if the instruction would not alter the cc's. */
1804
1805 /* On the 68000, all the insns to store in an address register fail to
1806 set the cc's. However, in some cases these instructions can make it
1807 possibly invalid to use the saved cc's. In those cases we clear out
1808 some or all of the saved cc's so they won't be used. */
1809
1810 notice_update_cc (exp, insn)
1811 rtx exp;
1812 rtx insn;
1813 {
1814 /* If the cc is being set from the fpa and the expression is not an
1815 explicit floating point test instruction (which has code to deal with
1816 this), reinit the CC. */
1817 if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
1818 || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
1819 && !(GET_CODE (exp) == PARALLEL
1820 && GET_CODE (XVECEXP (exp, 0, 0)) == SET
1821 && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
1822 {
1823 CC_STATUS_INIT;
1824 }
1825 else if (GET_CODE (exp) == SET)
1826 {
1827 if (GET_CODE (SET_SRC (exp)) == CALL)
1828 {
1829 CC_STATUS_INIT;
1830 }
1831 else if (ADDRESS_REG_P (SET_DEST (exp)))
1832 {
1833 if (cc_status.value1
1834 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
1835 cc_status.value1 = 0;
1836 if (cc_status.value2
1837 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
1838 cc_status.value2 = 0;
1839 }
1840 else if (!FP_REG_P (SET_DEST (exp))
1841 && SET_DEST (exp) != cc0_rtx
1842 && (FP_REG_P (SET_SRC (exp))
1843 || GET_CODE (SET_SRC (exp)) == FIX
1844 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
1845 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
1846 {
1847 CC_STATUS_INIT;
1848 }
1849 /* A pair of move insns doesn't produce a useful overall cc. */
1850 else if (!FP_REG_P (SET_DEST (exp))
1851 && !FP_REG_P (SET_SRC (exp))
1852 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
1853 && (GET_CODE (SET_SRC (exp)) == REG
1854 || GET_CODE (SET_SRC (exp)) == MEM
1855 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
1856 {
1857 CC_STATUS_INIT;
1858 }
1859 else if (GET_CODE (SET_SRC (exp)) == CALL)
1860 {
1861 CC_STATUS_INIT;
1862 }
1863 else if (XEXP (exp, 0) != pc_rtx)
1864 {
1865 cc_status.flags = 0;
1866 cc_status.value1 = XEXP (exp, 0);
1867 cc_status.value2 = XEXP (exp, 1);
1868 }
1869 }
1870 else if (GET_CODE (exp) == PARALLEL
1871 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
1872 {
1873 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1874 CC_STATUS_INIT;
1875 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
1876 {
1877 cc_status.flags = 0;
1878 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1879 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
1880 }
1881 }
1882 else
1883 CC_STATUS_INIT;
1884 if (cc_status.value2 != 0
1885 && ADDRESS_REG_P (cc_status.value2)
1886 && GET_MODE (cc_status.value2) == QImode)
1887 CC_STATUS_INIT;
1888 if (cc_status.value2 != 0
1889 && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
1890 switch (GET_CODE (cc_status.value2))
1891 {
1892 case PLUS: case MINUS: case MULT:
1893 case DIV: case UDIV: case MOD: case UMOD: case NEG:
1894 #if 0 /* These instructions always clear the overflow bit */
1895 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
1896 case ROTATE: case ROTATERT:
1897 #endif
1898 if (GET_MODE (cc_status.value2) != VOIDmode)
1899 cc_status.flags |= CC_NO_OVERFLOW;
1900 break;
1901 case ZERO_EXTEND:
1902 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1903 ends with a move insn moving r2 in r2's mode.
1904 Thus, the cc's are set for r2.
1905 This can set N bit spuriously. */
1906 cc_status.flags |= CC_NOT_NEGATIVE;
1907 }
1908 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
1909 && cc_status.value2
1910 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
1911 cc_status.value2 = 0;
1912 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
1913 || (cc_status.value2 && FP_REG_P (cc_status.value2)))
1914 && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
1915 || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
1916 cc_status.flags = CC_IN_68881;
1917 }
1918 \f
1919 char *
1920 output_move_const_double (operands)
1921 rtx *operands;
1922 {
1923 #ifdef SUPPORT_SUN_FPA
1924 if (TARGET_FPA && FPA_REG_P (operands[0]))
1925 {
1926 int code = standard_sun_fpa_constant_p (operands[1]);
1927
1928 if (code != 0)
1929 {
1930 static char buf[40];
1931
1932 sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
1933 return buf;
1934 }
1935 return "fpmove%.d %1,%0";
1936 }
1937 else
1938 #endif
1939 {
1940 int code = standard_68881_constant_p (operands[1]);
1941
1942 if (code != 0)
1943 {
1944 static char buf[40];
1945
1946 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
1947 return buf;
1948 }
1949 return "fmove%.d %1,%0";
1950 }
1951 }
1952
1953 char *
1954 output_move_const_single (operands)
1955 rtx *operands;
1956 {
1957 #ifdef SUPPORT_SUN_FPA
1958 if (TARGET_FPA)
1959 {
1960 int code = standard_sun_fpa_constant_p (operands[1]);
1961
1962 if (code != 0)
1963 {
1964 static char buf[40];
1965
1966 sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
1967 return buf;
1968 }
1969 return "fpmove%.s %1,%0";
1970 }
1971 else
1972 #endif /* defined SUPPORT_SUN_FPA */
1973 {
1974 int code = standard_68881_constant_p (operands[1]);
1975
1976 if (code != 0)
1977 {
1978 static char buf[40];
1979
1980 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
1981 return buf;
1982 }
1983 return "fmove%.s %f1,%0";
1984 }
1985 }
1986
1987 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1988 from the "fmovecr" instruction.
1989 The value, anded with 0xff, gives the code to use in fmovecr
1990 to get the desired constant. */
1991
1992 /* This code has been fixed for cross-compilation. */
1993
1994 static int inited_68881_table = 0;
1995
1996 char *strings_68881[7] = {
1997 "0.0",
1998 "1.0",
1999 "10.0",
2000 "100.0",
2001 "10000.0",
2002 "1e8",
2003 "1e16"
2004 };
2005
2006 int codes_68881[7] = {
2007 0x0f,
2008 0x32,
2009 0x33,
2010 0x34,
2011 0x35,
2012 0x36,
2013 0x37
2014 };
2015
2016 REAL_VALUE_TYPE values_68881[7];
2017
2018 /* Set up values_68881 array by converting the decimal values
2019 strings_68881 to binary. */
2020
2021 void
2022 init_68881_table ()
2023 {
2024 int i;
2025 REAL_VALUE_TYPE r;
2026 enum machine_mode mode;
2027
2028 mode = SFmode;
2029 for (i = 0; i < 7; i++)
2030 {
2031 if (i == 6)
2032 mode = DFmode;
2033 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2034 values_68881[i] = r;
2035 }
2036 inited_68881_table = 1;
2037 }
2038
2039 int
2040 standard_68881_constant_p (x)
2041 rtx x;
2042 {
2043 REAL_VALUE_TYPE r;
2044 int i;
2045 enum machine_mode mode;
2046
2047 #ifdef NO_ASM_FMOVECR
2048 return 0;
2049 #endif
2050
2051 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2052 if (TARGET_68040)
2053 return 0;
2054
2055 #ifndef REAL_ARITHMETIC
2056 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2057 if (! flag_pretend_float)
2058 return 0;
2059 #endif
2060 #endif
2061
2062 if (! inited_68881_table)
2063 init_68881_table ();
2064
2065 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2066
2067 for (i = 0; i < 6; i++)
2068 {
2069 if (REAL_VALUES_EQUAL (r, values_68881[i]))
2070 return (codes_68881[i]);
2071 }
2072
2073 if (GET_MODE (x) == SFmode)
2074 return 0;
2075
2076 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2077 return (codes_68881[6]);
2078
2079 /* larger powers of ten in the constants ram are not used
2080 because they are not equal to a `double' C constant. */
2081 return 0;
2082 }
2083
2084 /* If X is a floating-point constant, return the logarithm of X base 2,
2085 or 0 if X is not a power of 2. */
2086
2087 int
2088 floating_exact_log2 (x)
2089 rtx x;
2090 {
2091 REAL_VALUE_TYPE r, r1;
2092 int i;
2093
2094 #ifndef REAL_ARITHMETIC
2095 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2096 if (! flag_pretend_float)
2097 return 0;
2098 #endif
2099 #endif
2100
2101 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2102
2103 if (REAL_VALUES_LESS (r, dconst0))
2104 return 0;
2105
2106 r1 = dconst1;
2107 i = 0;
2108 while (REAL_VALUES_LESS (r1, r))
2109 {
2110 r1 = REAL_VALUE_LDEXP (dconst1, i);
2111 if (REAL_VALUES_EQUAL (r1, r))
2112 return i;
2113 i = i + 1;
2114 }
2115 return 0;
2116 }
2117 \f
2118 #ifdef SUPPORT_SUN_FPA
2119 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2120 from the Sun FPA's constant RAM.
2121 The value returned, anded with 0x1ff, gives the code to use in fpmove
2122 to get the desired constant. */
2123
2124 static int inited_FPA_table = 0;
2125
2126 char *strings_FPA[38] = {
2127 /* small rationals */
2128 "0.0",
2129 "1.0",
2130 "0.5",
2131 "-1.0",
2132 "2.0",
2133 "3.0",
2134 "4.0",
2135 "8.0",
2136 "0.25",
2137 "0.125",
2138 "10.0",
2139 "-0.5",
2140 /* Decimal equivalents of double precision values */
2141 "2.718281828459045091", /* D_E */
2142 "6.283185307179586477", /* 2 pi */
2143 "3.141592653589793116", /* D_PI */
2144 "1.570796326794896619", /* pi/2 */
2145 "1.414213562373095145", /* D_SQRT2 */
2146 "0.7071067811865475244", /* 1/sqrt(2) */
2147 "-1.570796326794896619", /* -pi/2 */
2148 "1.442695040888963387", /* D_LOG2ofE */
2149 "3.321928024887362182", /* D_LOG2of10 */
2150 "0.6931471805599452862", /* D_LOGEof2 */
2151 "2.302585092994045901", /* D_LOGEof10 */
2152 "0.3010299956639811980", /* D_LOG10of2 */
2153 "0.4342944819032518167", /* D_LOG10ofE */
2154 /* Decimal equivalents of single precision values */
2155 "2.718281745910644531", /* S_E */
2156 "6.283185307179586477", /* 2 pi */
2157 "3.141592741012573242", /* S_PI */
2158 "1.570796326794896619", /* pi/2 */
2159 "1.414213538169860840", /* S_SQRT2 */
2160 "0.7071067811865475244", /* 1/sqrt(2) */
2161 "-1.570796326794896619", /* -pi/2 */
2162 "1.442695021629333496", /* S_LOG2ofE */
2163 "3.321928024291992188", /* S_LOG2of10 */
2164 "0.6931471824645996094", /* S_LOGEof2 */
2165 "2.302585124969482442", /* S_LOGEof10 */
2166 "0.3010300099849700928", /* S_LOG10of2 */
2167 "0.4342944920063018799", /* S_LOG10ofE */
2168 };
2169
2170
2171 int codes_FPA[38] = {
2172 /* small rationals */
2173 0x200,
2174 0xe,
2175 0xf,
2176 0x10,
2177 0x11,
2178 0xb1,
2179 0x12,
2180 0x13,
2181 0x15,
2182 0x16,
2183 0x17,
2184 0x2e,
2185 /* double precision */
2186 0x8,
2187 0x9,
2188 0xa,
2189 0xb,
2190 0xc,
2191 0xd,
2192 0x27,
2193 0x28,
2194 0x29,
2195 0x2a,
2196 0x2b,
2197 0x2c,
2198 0x2d,
2199 /* single precision */
2200 0x8,
2201 0x9,
2202 0xa,
2203 0xb,
2204 0xc,
2205 0xd,
2206 0x27,
2207 0x28,
2208 0x29,
2209 0x2a,
2210 0x2b,
2211 0x2c,
2212 0x2d
2213 };
2214
2215 REAL_VALUE_TYPE values_FPA[38];
2216
2217 /* This code has been fixed for cross-compilation. */
2218
2219 void
2220 init_FPA_table ()
2221 {
2222 enum machine_mode mode;
2223 int i;
2224 REAL_VALUE_TYPE r;
2225
2226 mode = DFmode;
2227 for (i = 0; i < 38; i++)
2228 {
2229 if (i == 25)
2230 mode = SFmode;
2231 r = REAL_VALUE_ATOF (strings_FPA[i], mode);
2232 values_FPA[i] = r;
2233 }
2234 inited_FPA_table = 1;
2235 }
2236
2237
2238 int
2239 standard_sun_fpa_constant_p (x)
2240 rtx x;
2241 {
2242 REAL_VALUE_TYPE r;
2243 int i;
2244
2245 #ifndef REAL_ARITHMETIC
2246 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2247 if (! flag_pretend_float)
2248 return 0;
2249 #endif
2250 #endif
2251
2252 if (! inited_FPA_table)
2253 init_FPA_table ();
2254
2255 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2256
2257 for (i=0; i<12; i++)
2258 {
2259 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2260 return (codes_FPA[i]);
2261 }
2262
2263 if (GET_MODE (x) == SFmode)
2264 {
2265 for (i=25; i<38; i++)
2266 {
2267 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2268 return (codes_FPA[i]);
2269 }
2270 }
2271 else
2272 {
2273 for (i=12; i<25; i++)
2274 {
2275 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2276 return (codes_FPA[i]);
2277 }
2278 }
2279 return 0x0;
2280 }
2281 #endif /* define SUPPORT_SUN_FPA */
2282 \f
2283 /* A C compound statement to output to stdio stream STREAM the
2284 assembler syntax for an instruction operand X. X is an RTL
2285 expression.
2286
2287 CODE is a value that can be used to specify one of several ways
2288 of printing the operand. It is used when identical operands
2289 must be printed differently depending on the context. CODE
2290 comes from the `%' specification that was used to request
2291 printing of the operand. If the specification was just `%DIGIT'
2292 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2293 is the ASCII code for LTR.
2294
2295 If X is a register, this macro should print the register's name.
2296 The names can be found in an array `reg_names' whose type is
2297 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2298
2299 When the machine description has a specification `%PUNCT' (a `%'
2300 followed by a punctuation character), this macro is called with
2301 a null pointer for X and the punctuation character for CODE.
2302
2303 The m68k specific codes are:
2304
2305 '.' for dot needed in Motorola-style opcode names.
2306 '-' for an operand pushing on the stack:
2307 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2308 '+' for an operand pushing on the stack:
2309 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2310 '@' for a reference to the top word on the stack:
2311 sp@, (sp) or (%sp) depending on the style of syntax.
2312 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2313 but & in SGS syntax, $ in CRDS/UNOS syntax).
2314 '!' for the cc register (used in an `and to cc' insn).
2315 '$' for the letter `s' in an op code, but only on the 68040.
2316 '&' for the letter `d' in an op code, but only on the 68040.
2317 '/' for register prefix needed by longlong.h.
2318
2319 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2320 'd' to force memory addressing to be absolute, not relative.
2321 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2322 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2323 than directly). Second part of 'y' below.
2324 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2325 or print pair of registers as rx:ry.
2326 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2327 CONST_DOUBLE's as SunFPA constant RAM registers if
2328 possible, so it should not be used except for the SunFPA.
2329
2330 */
2331
2332 void
2333 print_operand (file, op, letter)
2334 FILE *file; /* file to write to */
2335 rtx op; /* operand to print */
2336 int letter; /* %<letter> or 0 */
2337 {
2338 int i;
2339
2340 if (letter == '.')
2341 {
2342 #if defined (MOTOROLA) && !defined (CRDS)
2343 asm_fprintf (file, ".");
2344 #endif
2345 }
2346 else if (letter == '#')
2347 {
2348 asm_fprintf (file, "%0I");
2349 }
2350 else if (letter == '-')
2351 {
2352 #ifdef MOTOROLA
2353 asm_fprintf (file, "-(%Rsp)");
2354 #else
2355 asm_fprintf (file, "%Rsp@-");
2356 #endif
2357 }
2358 else if (letter == '+')
2359 {
2360 #ifdef MOTOROLA
2361 asm_fprintf (file, "(%Rsp)+");
2362 #else
2363 asm_fprintf (file, "%Rsp@+");
2364 #endif
2365 }
2366 else if (letter == '@')
2367 {
2368 #ifdef MOTOROLA
2369 asm_fprintf (file, "(%Rsp)");
2370 #else
2371 asm_fprintf (file, "%Rsp@");
2372 #endif
2373 }
2374 else if (letter == '!')
2375 {
2376 asm_fprintf (file, "%Rfpcr");
2377 }
2378 else if (letter == '$')
2379 {
2380 if (TARGET_68040_ONLY)
2381 {
2382 fprintf (file, "s");
2383 }
2384 }
2385 else if (letter == '&')
2386 {
2387 if (TARGET_68040_ONLY)
2388 {
2389 fprintf (file, "d");
2390 }
2391 }
2392 else if (letter == '/')
2393 {
2394 asm_fprintf (file, "%R");
2395 }
2396 else if (GET_CODE (op) == REG)
2397 {
2398 #ifdef SUPPORT_SUN_FPA
2399 if (REGNO (op) < 16
2400 && (letter == 'y' || letter == 'x')
2401 && GET_MODE (op) == DFmode)
2402 {
2403 fprintf (file, "%s:%s", reg_names[REGNO (op)],
2404 reg_names[REGNO (op)+1]);
2405 }
2406 else
2407 #endif
2408 {
2409 if (letter == 'R')
2410 /* Print out the second register name of a register pair.
2411 I.e., R (6) => 7. */
2412 fputs (reg_names[REGNO (op) + 1], file);
2413 else
2414 fputs (reg_names[REGNO (op)], file);
2415 }
2416 }
2417 else if (GET_CODE (op) == MEM)
2418 {
2419 output_address (XEXP (op, 0));
2420 if (letter == 'd' && ! TARGET_68020
2421 && CONSTANT_ADDRESS_P (XEXP (op, 0))
2422 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
2423 && INTVAL (XEXP (op, 0)) < 0x8000
2424 && INTVAL (XEXP (op, 0)) >= -0x8000))
2425 {
2426 #ifdef MOTOROLA
2427 fprintf (file, ".l");
2428 #else
2429 fprintf (file, ":l");
2430 #endif
2431 }
2432 }
2433 #ifdef SUPPORT_SUN_FPA
2434 else if ((letter == 'y' || letter == 'w')
2435 && GET_CODE (op) == CONST_DOUBLE
2436 && (i = standard_sun_fpa_constant_p (op)))
2437 {
2438 fprintf (file, "%%%d", i & 0x1ff);
2439 }
2440 #endif
2441 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
2442 {
2443 REAL_VALUE_TYPE r;
2444 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2445 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
2446 }
2447 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
2448 {
2449 REAL_VALUE_TYPE r;
2450 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2451 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
2452 }
2453 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
2454 {
2455 REAL_VALUE_TYPE r;
2456 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2457 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
2458 }
2459 else
2460 {
2461 asm_fprintf (file, "%0I"); output_addr_const (file, op);
2462 }
2463 }
2464
2465 \f
2466 /* A C compound statement to output to stdio stream STREAM the
2467 assembler syntax for an instruction operand that is a memory
2468 reference whose address is ADDR. ADDR is an RTL expression.
2469
2470 Note that this contains a kludge that knows that the only reason
2471 we have an address (plus (label_ref...) (reg...)) when not generating
2472 PIC code is in the insn before a tablejump, and we know that m68k.md
2473 generates a label LInnn: on such an insn.
2474
2475 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2476 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2477
2478 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2479 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2480 we want. This difference can be accommodated by using an assembler
2481 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2482 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2483 macro. See m68k/sgs.h for an example; for versions without the bug.
2484 Some assemblers refuse all the above solutions. The workaround is to
2485 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2486 right behaviour.
2487
2488 They also do not like things like "pea 1.w", so we simple leave off
2489 the .w on small constants.
2490
2491 This routine is responsible for distinguishing between -fpic and -fPIC
2492 style relocations in an address. When generating -fpic code the
2493 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2494 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2495
2496 #ifndef ASM_OUTPUT_CASE_FETCH
2497 #ifdef MOTOROLA
2498 #ifdef SGS
2499 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2500 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2501 #else
2502 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2503 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2504 #endif
2505 #else
2506 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2507 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2508 #endif
2509 #endif /* ASM_OUTPUT_CASE_FETCH */
2510
2511 void
2512 print_operand_address (file, addr)
2513 FILE *file;
2514 rtx addr;
2515 {
2516 register rtx reg1, reg2, breg, ireg;
2517 rtx offset;
2518
2519 switch (GET_CODE (addr))
2520 {
2521 case REG:
2522 #ifdef MOTOROLA
2523 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
2524 #else
2525 fprintf (file, "%s@", reg_names[REGNO (addr)]);
2526 #endif
2527 break;
2528 case PRE_DEC:
2529 #ifdef MOTOROLA
2530 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
2531 #else
2532 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
2533 #endif
2534 break;
2535 case POST_INC:
2536 #ifdef MOTOROLA
2537 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
2538 #else
2539 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
2540 #endif
2541 break;
2542 case PLUS:
2543 reg1 = reg2 = ireg = breg = offset = 0;
2544 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2545 {
2546 offset = XEXP (addr, 0);
2547 addr = XEXP (addr, 1);
2548 }
2549 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2550 {
2551 offset = XEXP (addr, 1);
2552 addr = XEXP (addr, 0);
2553 }
2554 if (GET_CODE (addr) != PLUS)
2555 {
2556 ;
2557 }
2558 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
2559 {
2560 reg1 = XEXP (addr, 0);
2561 addr = XEXP (addr, 1);
2562 }
2563 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
2564 {
2565 reg1 = XEXP (addr, 1);
2566 addr = XEXP (addr, 0);
2567 }
2568 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2569 {
2570 reg1 = XEXP (addr, 0);
2571 addr = XEXP (addr, 1);
2572 }
2573 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2574 {
2575 reg1 = XEXP (addr, 1);
2576 addr = XEXP (addr, 0);
2577 }
2578 else if (GET_CODE (XEXP (addr, 0)) == REG)
2579 {
2580 reg1 = XEXP (addr, 0);
2581 addr = XEXP (addr, 1);
2582 }
2583 else if (GET_CODE (XEXP (addr, 1)) == REG)
2584 {
2585 reg1 = XEXP (addr, 1);
2586 addr = XEXP (addr, 0);
2587 }
2588 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
2589 || GET_CODE (addr) == SIGN_EXTEND)
2590 {
2591 if (reg1 == 0)
2592 {
2593 reg1 = addr;
2594 }
2595 else
2596 {
2597 reg2 = addr;
2598 }
2599 addr = 0;
2600 }
2601 #if 0 /* for OLD_INDEXING */
2602 else if (GET_CODE (addr) == PLUS)
2603 {
2604 if (GET_CODE (XEXP (addr, 0)) == REG)
2605 {
2606 reg2 = XEXP (addr, 0);
2607 addr = XEXP (addr, 1);
2608 }
2609 else if (GET_CODE (XEXP (addr, 1)) == REG)
2610 {
2611 reg2 = XEXP (addr, 1);
2612 addr = XEXP (addr, 0);
2613 }
2614 }
2615 #endif
2616 if (offset != 0)
2617 {
2618 if (addr != 0)
2619 {
2620 abort ();
2621 }
2622 addr = offset;
2623 }
2624 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
2625 || GET_CODE (reg1) == MULT))
2626 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2627 {
2628 breg = reg2;
2629 ireg = reg1;
2630 }
2631 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
2632 {
2633 breg = reg1;
2634 ireg = reg2;
2635 }
2636 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
2637 && ! (flag_pic && ireg == pic_offset_table_rtx))
2638 {
2639 int scale = 1;
2640 if (GET_CODE (ireg) == MULT)
2641 {
2642 scale = INTVAL (XEXP (ireg, 1));
2643 ireg = XEXP (ireg, 0);
2644 }
2645 if (GET_CODE (ireg) == SIGN_EXTEND)
2646 {
2647 ASM_OUTPUT_CASE_FETCH (file,
2648 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2649 reg_names[REGNO (XEXP (ireg, 0))]);
2650 fprintf (file, "w");
2651 }
2652 else
2653 {
2654 ASM_OUTPUT_CASE_FETCH (file,
2655 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2656 reg_names[REGNO (ireg)]);
2657 fprintf (file, "l");
2658 }
2659 if (scale != 1)
2660 {
2661 #ifdef MOTOROLA
2662 fprintf (file, "*%d", scale);
2663 #else
2664 fprintf (file, ":%d", scale);
2665 #endif
2666 }
2667 putc (')', file);
2668 break;
2669 }
2670 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
2671 && ! (flag_pic && breg == pic_offset_table_rtx))
2672 {
2673 ASM_OUTPUT_CASE_FETCH (file,
2674 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2675 reg_names[REGNO (breg)]);
2676 fprintf (file, "l)");
2677 break;
2678 }
2679 if (ireg != 0 || breg != 0)
2680 {
2681 int scale = 1;
2682 if (breg == 0)
2683 {
2684 abort ();
2685 }
2686 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
2687 {
2688 abort ();
2689 }
2690 #ifdef MOTOROLA
2691 if (addr != 0)
2692 {
2693 output_addr_const (file, addr);
2694 if (flag_pic && (breg == pic_offset_table_rtx))
2695 fprintf (file, "@GOT");
2696 }
2697 fprintf (file, "(%s", reg_names[REGNO (breg)]);
2698 if (ireg != 0)
2699 {
2700 putc (',', file);
2701 }
2702 #else
2703 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
2704 if (addr != 0)
2705 {
2706 output_addr_const (file, addr);
2707 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
2708 fprintf (file, ":w");
2709 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
2710 fprintf (file, ":l");
2711 }
2712 if (addr != 0 && ireg != 0)
2713 {
2714 putc (',', file);
2715 }
2716 #endif
2717 if (ireg != 0 && GET_CODE (ireg) == MULT)
2718 {
2719 scale = INTVAL (XEXP (ireg, 1));
2720 ireg = XEXP (ireg, 0);
2721 }
2722 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
2723 {
2724 #ifdef MOTOROLA
2725 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
2726 #else
2727 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
2728 #endif
2729 }
2730 else if (ireg != 0)
2731 {
2732 #ifdef MOTOROLA
2733 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
2734 #else
2735 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
2736 #endif
2737 }
2738 if (scale != 1)
2739 {
2740 #ifdef MOTOROLA
2741 fprintf (file, "*%d", scale);
2742 #else
2743 fprintf (file, ":%d", scale);
2744 #endif
2745 }
2746 putc (')', file);
2747 break;
2748 }
2749 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
2750 && ! (flag_pic && reg1 == pic_offset_table_rtx))
2751 {
2752 ASM_OUTPUT_CASE_FETCH (file,
2753 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2754 reg_names[REGNO (reg1)]);
2755 fprintf (file, "l)");
2756 break;
2757 }
2758 /* FALL-THROUGH (is this really what we want? */
2759 default:
2760 if (GET_CODE (addr) == CONST_INT
2761 && INTVAL (addr) < 0x8000
2762 && INTVAL (addr) >= -0x8000)
2763 {
2764 #ifdef MOTOROLA
2765 #ifdef SGS
2766 /* Many SGS assemblers croak on size specifiers for constants. */
2767 fprintf (file, "%d", INTVAL (addr));
2768 #else
2769 fprintf (file, "%d.w", INTVAL (addr));
2770 #endif
2771 #else
2772 fprintf (file, "%d:w", INTVAL (addr));
2773 #endif
2774 }
2775 else
2776 {
2777 output_addr_const (file, addr);
2778 }
2779 break;
2780 }
2781 }
2782 \f
2783 /* Check for cases where a clr insns can be omitted from code using
2784 strict_low_part sets. For example, the second clrl here is not needed:
2785 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2786
2787 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2788 insn we are checking for redundancy. TARGET is the register set by the
2789 clear insn. */
2790
2791 int
2792 strict_low_part_peephole_ok (mode, first_insn, target)
2793 enum machine_mode mode;
2794 rtx first_insn;
2795 rtx target;
2796 {
2797 rtx p;
2798
2799 p = prev_nonnote_insn (first_insn);
2800
2801 while (p)
2802 {
2803 /* If it isn't an insn, then give up. */
2804 if (GET_CODE (p) != INSN)
2805 return 0;
2806
2807 if (reg_set_p (target, p))
2808 {
2809 rtx set = single_set (p);
2810 rtx dest;
2811
2812 /* If it isn't an easy to recognize insn, then give up. */
2813 if (! set)
2814 return 0;
2815
2816 dest = SET_DEST (set);
2817
2818 /* If this sets the entire target register to zero, then our
2819 first_insn is redundant. */
2820 if (rtx_equal_p (dest, target)
2821 && SET_SRC (set) == const0_rtx)
2822 return 1;
2823 else if (GET_CODE (dest) == STRICT_LOW_PART
2824 && GET_CODE (XEXP (dest, 0)) == REG
2825 && REGNO (XEXP (dest, 0)) == REGNO (target)
2826 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
2827 <= GET_MODE_SIZE (mode)))
2828 /* This is a strict low part set which modifies less than
2829 we are using, so it is safe. */
2830 ;
2831 else
2832 return 0;
2833 }
2834
2835 p = prev_nonnote_insn (p);
2836
2837 }
2838
2839 return 0;
2840 }
2841
2842 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2843 range carefully since this predicate is used in DImode contexts. Also, we
2844 need some extra crud to make it work when hosted on 64-bit machines. */
2845
2846 int
2847 const_uint32_operand (op, mode)
2848 rtx op;
2849 enum machine_mode mode;
2850 {
2851 #if HOST_BITS_PER_WIDE_INT > 32
2852 /* All allowed constants will fit a CONST_INT. */
2853 return (GET_CODE (op) == CONST_INT
2854 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
2855 #else
2856 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
2857 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
2858 #endif
2859 }
2860
2861 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
2862 to check the range carefully since this predicate is used in DImode
2863 contexts. */
2864
2865 int
2866 const_sint32_operand (op, mode)
2867 rtx op;
2868 enum machine_mode mode;
2869 {
2870 /* All allowed constants will fit a CONST_INT. */
2871 return (GET_CODE (op) == CONST_INT
2872 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
2873 }