1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
35 /* Needed for use_return_insn. */
38 #ifdef SUPPORT_SUN_FPA
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class
[]
43 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
44 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
46 #endif /* defined SUPPORT_SUN_FPA */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg ();
53 rtx
legitimize_pic_address ();
56 /* Alignment to use for loops and jumps */
57 /* Specify power of two alignment used for loops. */
58 char *m68k_align_loops_string
;
59 /* Specify power of two alignment used for non-loop jumps. */
60 char *m68k_align_jumps_string
;
61 /* Specify power of two alignment used for functions. */
62 char *m68k_align_funcs_string
;
64 /* Specify power of two alignment used for loops. */
66 /* Specify power of two alignment used for non-loop jumps. */
68 /* Specify power of two alignment used for functions. */
72 /* Sometimes certain combinations of command options do not make
73 sense on a particular target machine. You can define a macro
74 `OVERRIDE_OPTIONS' to take account of this. This macro, if
75 defined, is executed once just after all the command options have
78 Don't use this macro to turn on various extra optimizations for
79 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
88 /* Validate -malign-loops= value, or provide default */
89 if (m68k_align_loops_string
)
91 m68k_align_loops
= atoi (m68k_align_loops_string
);
92 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
93 fatal ("-malign-loops=%d is not between 1 and %d",
94 m68k_align_loops
, MAX_CODE_ALIGN
);
97 m68k_align_loops
= def_align
;
99 /* Validate -malign-jumps= value, or provide default */
100 if (m68k_align_jumps_string
)
102 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
103 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
104 fatal ("-malign-jumps=%d is not between 1 and %d",
105 m68k_align_jumps
, MAX_CODE_ALIGN
);
108 m68k_align_jumps
= def_align
;
110 /* Validate -malign-functions= value, or provide default */
111 if (m68k_align_funcs_string
)
113 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
114 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
115 fatal ("-malign-functions=%d is not between 1 and %d",
116 m68k_align_funcs
, MAX_CODE_ALIGN
);
119 m68k_align_funcs
= def_align
;
122 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
123 function at any time during the compilation process. In the future
124 we should try and eliminate the USE if we can easily determine that
125 all PIC references were deleted from the current function. That would
126 save an address register */
131 if (flag_pic
&& current_function_uses_pic_offset_table
)
133 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
134 emit_insn_after (insn
, get_insns ());
140 /* This function generates the assembly code for function entry.
141 STREAM is a stdio stream to output the code to.
142 SIZE is an int: how many units of temporary storage to allocate.
143 Refer to the array `regs_ever_live' to determine which registers
144 to save; `regs_ever_live[I]' is nonzero if register number I
145 is ever used in the function. This function is responsible for
146 knowing which registers should not be saved even if used. */
149 /* Note that the order of the bit mask for fmovem is the opposite
150 of the order for movem! */
154 output_function_prologue (stream
, size
)
159 register int mask
= 0;
160 int num_saved_regs
= 0;
161 extern char call_used_regs
[];
162 int fsize
= (size
+ 3) & -4;
165 if (frame_pointer_needed
)
167 if (fsize
== 0 && TARGET_68040
)
169 /* on the 68040, pea + move is faster than link.w 0 */
171 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
172 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
173 reg_names
[FRAME_POINTER_REGNUM
]);
175 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
176 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
177 reg_names
[FRAME_POINTER_REGNUM
]);
180 else if (fsize
< 0x8000)
183 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
184 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
186 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
187 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
190 else if (TARGET_68020
)
193 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
194 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
196 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
197 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
202 /* Adding negative number is faster on the 68040. */
204 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
205 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
207 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
208 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
214 if (fsize
+ 4 < 0x8000)
221 /* asm_fprintf() cannot handle %. */
223 asm_fprintf (stream
, "\tsubq.w %OI%d,%Rsp\n", fsize
+ 4);
225 asm_fprintf (stream
, "\tsubqw %OI%d,%Rsp\n", fsize
+ 4);
230 /* asm_fprintf() cannot handle %. */
232 asm_fprintf (stream
, "\tsubq.l %OI%d,%Rsp\n", fsize
+ 4);
234 asm_fprintf (stream
, "\tsubql %OI%d,%Rsp\n", fsize
+ 4);
238 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
240 /* On the CPU32 it is faster to use two subqw instructions to
241 subtract a small integer (8 < N <= 16) to a register. */
242 /* asm_fprintf() cannot handle %. */
244 asm_fprintf (stream
, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
247 asm_fprintf (stream
, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
252 #endif /* NO_ADDSUB_Q */
255 /* Adding negative number is faster on the 68040. */
256 /* asm_fprintf() cannot handle %. */
258 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
260 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
266 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
268 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
274 /* asm_fprintf() cannot handle %. */
276 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
278 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
282 #ifdef SUPPORT_SUN_FPA
283 for (regno
= 24; regno
< 56; regno
++)
284 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
287 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
290 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
297 for (regno
= 16; regno
< 24; regno
++)
298 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
299 mask
|= 1 << (regno
- 16);
300 if ((mask
& 0xff) != 0)
303 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
305 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
310 for (regno
= 0; regno
< 16; regno
++)
311 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
313 mask
|= 1 << (15 - regno
);
316 if (frame_pointer_needed
)
318 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
325 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
327 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
330 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
334 if (num_saved_regs
<= 2)
336 /* Store each separately in the same order moveml uses.
337 Using two movel instructions instead of a single moveml
338 is about 15% faster for the 68020 and 68030 at no expense
343 /* Undo the work from above. */
344 for (i
= 0; i
< 16; i
++)
348 "\t%Omove.l %s,-(%Rsp)\n",
350 "\tmovel %s,%Rsp@-\n",
358 /* The coldfire does not support the predecrement form of the
359 movml instruction, so we must adjust the stack pointer and
360 then use the plain address register indirect mode. We also
361 have to invert the register save mask to use the new mode.
363 FIXME: if num_saved_regs was calculated earlier, we could
364 combine the stack pointer adjustment with any adjustment
365 done when the initial stack frame is created. This would
366 save an instruction */
371 for (i
= 0; i
< 16; i
++)
373 newmask
|= (1 << (15-i
));
376 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
377 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
379 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
380 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
386 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
388 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
392 if (flag_pic
&& current_function_uses_pic_offset_table
)
395 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
396 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
398 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
399 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
400 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
401 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
402 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
407 /* Return true if this function's epilogue can be output as RTL. */
414 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
417 /* Copied from output_function_epilogue (). We should probably create a
418 separate layout routine to perform the common work. */
420 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
421 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
427 /* This function generates the assembly code for function exit,
428 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
430 The function epilogue should not depend on the current stack pointer!
431 It should use the frame pointer only, if there is a frame pointer.
432 This is mandatory because of alloca; we also take advantage of it to
433 omit stack adjustments before returning. */
436 output_function_epilogue (stream
, size
)
441 register int mask
, fmask
;
443 int offset
, foffset
, fpoffset
;
444 extern char call_used_regs
[];
445 int fsize
= (size
+ 3) & -4;
447 rtx insn
= get_last_insn ();
448 int restore_from_sp
= 0;
450 /* If the last insn was a BARRIER, we don't have to write any code. */
451 if (GET_CODE (insn
) == NOTE
)
452 insn
= prev_nonnote_insn (insn
);
453 if (insn
&& GET_CODE (insn
) == BARRIER
)
455 /* Output just a no-op so that debuggers don't get confused
456 about which function the pc is in at this address. */
457 asm_fprintf (stream
, "\tnop\n");
461 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
462 if (profile_block_flag
== 2)
464 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
468 #ifdef FUNCTION_EXTRA_EPILOGUE
469 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
471 nregs
= 0; fmask
= 0; fpoffset
= 0;
472 #ifdef SUPPORT_SUN_FPA
473 for (regno
= 24 ; regno
< 56 ; regno
++)
474 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
476 fpoffset
= nregs
* 8;
481 for (regno
= 16; regno
< 24; regno
++)
482 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
485 fmask
|= 1 << (23 - regno
);
488 foffset
= fpoffset
+ nregs
* 12;
490 if (frame_pointer_needed
)
491 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
492 for (regno
= 0; regno
< 16; regno
++)
493 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
498 offset
= foffset
+ nregs
* 4;
499 /* FIXME : leaf_function_p below is too strong.
500 What we really need to know there is if there could be pending
501 stack adjustment needed at that point. */
502 restore_from_sp
= ! frame_pointer_needed
503 || (! current_function_calls_alloca
&& leaf_function_p ());
504 if (offset
+ fsize
>= 0x8000
506 && (mask
|| fmask
|| fpoffset
))
509 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
511 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
515 if (TARGET_5200
|| nregs
<= 2)
517 /* Restore each separately in the same order moveml does.
518 Using two movel instructions instead of a single moveml
519 is about 15% faster for the 68020 and 68030 at no expense
524 /* Undo the work from above. */
525 for (i
= 0; i
< 16; i
++)
531 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
533 reg_names
[FRAME_POINTER_REGNUM
],
536 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
537 reg_names
[FRAME_POINTER_REGNUM
],
538 offset
+ fsize
, reg_names
[i
]);
541 else if (restore_from_sp
)
544 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
547 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
554 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
556 reg_names
[FRAME_POINTER_REGNUM
],
559 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
560 reg_names
[FRAME_POINTER_REGNUM
],
561 offset
+ fsize
, reg_names
[i
]);
572 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
574 reg_names
[FRAME_POINTER_REGNUM
],
577 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
578 reg_names
[FRAME_POINTER_REGNUM
],
579 offset
+ fsize
, mask
);
582 else if (restore_from_sp
)
585 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
587 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
593 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
595 reg_names
[FRAME_POINTER_REGNUM
],
598 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
599 reg_names
[FRAME_POINTER_REGNUM
],
600 offset
+ fsize
, mask
);
609 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
611 reg_names
[FRAME_POINTER_REGNUM
],
614 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
615 reg_names
[FRAME_POINTER_REGNUM
],
616 foffset
+ fsize
, fmask
);
619 else if (restore_from_sp
)
622 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
624 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
630 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
632 reg_names
[FRAME_POINTER_REGNUM
],
635 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
636 reg_names
[FRAME_POINTER_REGNUM
],
637 foffset
+ fsize
, fmask
);
642 for (regno
= 55; regno
>= 24; regno
--)
643 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
648 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
650 reg_names
[FRAME_POINTER_REGNUM
],
653 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
654 reg_names
[FRAME_POINTER_REGNUM
],
655 fpoffset
+ fsize
, reg_names
[regno
]);
658 else if (restore_from_sp
)
661 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
664 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
671 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
673 reg_names
[FRAME_POINTER_REGNUM
],
676 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
677 reg_names
[FRAME_POINTER_REGNUM
],
678 fpoffset
+ fsize
, reg_names
[regno
]);
683 if (frame_pointer_needed
)
684 fprintf (stream
, "\tunlk %s\n",
685 reg_names
[FRAME_POINTER_REGNUM
]);
694 asm_fprintf (stream
, "\taddq.w %OI%d,%Rsp\n", fsize
+ 4);
696 asm_fprintf (stream
, "\taddqw %OI%d,%Rsp\n", fsize
+ 4);
702 asm_fprintf (stream
, "\taddq.l %OI%d,%Rsp\n", fsize
+ 4);
704 asm_fprintf (stream
, "\taddql %OI%d,%Rsp\n", fsize
+ 4);
708 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
710 /* On the CPU32 it is faster to use two addqw instructions to
711 add a small integer (8 < N <= 16) to a register. */
712 /* asm_fprintf() cannot handle %. */
714 asm_fprintf (stream
, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
717 asm_fprintf (stream
, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
722 #endif /* NO_ADDSUB_Q */
723 if (fsize
+ 4 < 0x8000)
727 /* asm_fprintf() cannot handle %. */
729 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
731 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
737 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
739 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
745 /* asm_fprintf() cannot handle %. */
747 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
749 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
753 if (current_function_pops_args
)
754 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
756 fprintf (stream
, "\trts\n");
759 /* Similar to general_operand, but exclude stack_pointer_rtx. */
762 not_sp_operand (op
, mode
)
764 enum machine_mode mode
;
766 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
769 /* Return TRUE if X is a valid comparison operator for the dbcc
772 Note it rejects floating point comparison operators.
773 (In the future we could use Fdbcc).
775 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
778 valid_dbcc_comparison_p (x
, mode
)
780 enum machine_mode mode
;
782 switch (GET_CODE (x
))
784 case EQ
: case NE
: case GTU
: case LTU
:
788 /* Reject some when CC_NO_OVERFLOW is set. This may be over
790 case GT
: case LT
: case GE
: case LE
:
791 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
797 /* Return non-zero if flags are currently in the 68881 flag register. */
801 /* We could add support for these in the future */
802 return cc_status
.flags
& CC_IN_68881
;
805 /* Output a dbCC; jCC sequence. Note we do not handle the
806 floating point version of this sequence (Fdbcc). We also
807 do not handle alternative conditions when CC_NO_OVERFLOW is
808 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
809 kick those out before we get here. */
811 output_dbcc_and_branch (operands
)
814 switch (GET_CODE (operands
[3]))
818 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
820 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
826 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
828 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
834 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
836 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
842 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
844 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
850 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
852 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
858 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
860 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
866 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
868 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
874 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
876 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
882 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
884 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
890 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
892 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
900 /* If the decrement is to be done in SImode, then we have
901 to compensate for the fact that dbcc decrements in HImode. */
902 switch (GET_MODE (operands
[0]))
906 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
908 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
921 output_scc_di(op
, operand1
, operand2
, dest
)
928 enum rtx_code op_code
= GET_CODE (op
);
930 /* This does not produce a usefull cc. */
933 /* The m68k cmp.l instruction requires operand1 to be a reg as used
934 below. Swap the operands and change the op if these requirements
935 are not fulfilled. */
936 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
942 op_code
= swap_condition (op_code
);
944 loperands
[0] = operand1
;
945 if (GET_CODE (operand1
) == REG
)
946 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
948 loperands
[1] = adj_offsettable_operand (operand1
, 4);
949 if (operand2
!= const0_rtx
)
951 loperands
[2] = operand2
;
952 if (GET_CODE (operand2
) == REG
)
953 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
955 loperands
[3] = adj_offsettable_operand (operand2
, 4);
957 loperands
[4] = gen_label_rtx();
958 if (operand2
!= const0_rtx
)
961 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
963 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
967 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
969 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
974 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
976 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
983 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
984 CODE_LABEL_NUMBER (loperands
[4]));
985 output_asm_insn ("seq %5", loperands
);
989 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
990 CODE_LABEL_NUMBER (loperands
[4]));
991 output_asm_insn ("sne %5", loperands
);
995 loperands
[6] = gen_label_rtx();
997 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
999 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1001 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1002 CODE_LABEL_NUMBER (loperands
[4]));
1003 output_asm_insn ("sgt %5", loperands
);
1004 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1005 CODE_LABEL_NUMBER (loperands
[6]));
1009 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1010 CODE_LABEL_NUMBER (loperands
[4]));
1011 output_asm_insn ("shi %5", loperands
);
1015 loperands
[6] = gen_label_rtx();
1017 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1019 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1021 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1022 CODE_LABEL_NUMBER (loperands
[4]));
1023 output_asm_insn ("slt %5", loperands
);
1024 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1025 CODE_LABEL_NUMBER (loperands
[6]));
1029 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1030 CODE_LABEL_NUMBER (loperands
[4]));
1031 output_asm_insn ("scs %5", loperands
);
1035 loperands
[6] = gen_label_rtx();
1037 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1039 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1041 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1042 CODE_LABEL_NUMBER (loperands
[4]));
1043 output_asm_insn ("sge %5", loperands
);
1044 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1045 CODE_LABEL_NUMBER (loperands
[6]));
1049 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1050 CODE_LABEL_NUMBER (loperands
[4]));
1051 output_asm_insn ("scc %5", loperands
);
1055 loperands
[6] = gen_label_rtx();
1057 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1059 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1061 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1062 CODE_LABEL_NUMBER (loperands
[4]));
1063 output_asm_insn ("sle %5", loperands
);
1064 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1065 CODE_LABEL_NUMBER (loperands
[6]));
1069 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1070 CODE_LABEL_NUMBER (loperands
[4]));
1071 output_asm_insn ("sls %5", loperands
);
1081 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1083 rtx countop
, dataop
;
1087 operands
[0] = countop
;
1088 operands
[1] = dataop
;
1090 if (GET_CODE (countop
) == CONST_INT
)
1092 register int count
= INTVAL (countop
);
1093 /* If COUNT is bigger than size of storage unit in use,
1094 advance to the containing unit of same size. */
1095 if (count
> signpos
)
1097 int offset
= (count
& ~signpos
) / 8;
1098 count
= count
& signpos
;
1099 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1101 if (count
== signpos
)
1102 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1104 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1106 /* These three statements used to use next_insns_test_no...
1107 but it appears that this should do the same job. */
1109 && next_insn_tests_no_inequality (insn
))
1112 && next_insn_tests_no_inequality (insn
))
1115 && next_insn_tests_no_inequality (insn
))
1118 cc_status
.flags
= CC_NOT_NEGATIVE
;
1120 return "btst %0,%1";
1123 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1124 reference and a constant. */
1127 symbolic_operand (op
, mode
)
1129 enum machine_mode mode
;
1131 switch (GET_CODE (op
))
1139 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1140 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1141 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1143 #if 0 /* Deleted, with corresponding change in m68k.h,
1144 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1146 return GET_MODE (op
) == mode
;
1154 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1157 extend_operator(x
, mode
)
1159 enum machine_mode mode
;
1161 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1163 switch (GET_CODE(x
))
1174 /* Legitimize PIC addresses. If the address is already
1175 position-independent, we return ORIG. Newly generated
1176 position-independent addresses go to REG. If we need more
1177 than one register, we lose.
1179 An address is legitimized by making an indirect reference
1180 through the Global Offset Table with the name of the symbol
1183 The assembler and linker are responsible for placing the
1184 address of the symbol in the GOT. The function prologue
1185 is responsible for initializing a5 to the starting address
1188 The assembler is also responsible for translating a symbol name
1189 into a constant displacement from the start of the GOT.
1191 A quick example may make things a little clearer:
1193 When not generating PIC code to store the value 12345 into _foo
1194 we would generate the following code:
1198 When generating PIC two transformations are made. First, the compiler
1199 loads the address of foo into a register. So the first transformation makes:
1204 The code in movsi will intercept the lea instruction and call this
1205 routine which will transform the instructions into:
1207 movel a5@(_foo:w), a0
1211 That (in a nutshell) is how *all* symbol and label references are
1215 legitimize_pic_address (orig
, mode
, reg
)
1217 enum machine_mode mode
;
1221 /* First handle a simple SYMBOL_REF or LABEL_REF */
1222 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1227 pic_ref
= gen_rtx (MEM
, Pmode
,
1228 gen_rtx (PLUS
, Pmode
,
1229 pic_offset_table_rtx
, orig
));
1230 current_function_uses_pic_offset_table
= 1;
1231 RTX_UNCHANGING_P (pic_ref
) = 1;
1232 emit_move_insn (reg
, pic_ref
);
1235 else if (GET_CODE (orig
) == CONST
)
1239 /* Make sure this is CONST has not already been legitimized */
1240 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1241 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1247 /* legitimize both operands of the PLUS */
1248 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1250 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1251 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1252 base
== reg
? 0 : reg
);
1256 if (GET_CODE (orig
) == CONST_INT
)
1257 return plus_constant_for_output (base
, INTVAL (orig
));
1258 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1259 /* Likewise, should we set special REG_NOTEs here? */
1265 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1267 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1270 const_method (constant
)
1276 i
= INTVAL (constant
);
1280 /* The Coldfire doesn't have byte or word operations. */
1281 /* FIXME: This may not be useful for the m68060 either */
1284 /* if -256 < N < 256 but N is not in range for a moveq
1285 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1286 if (USE_MOVQ (i
^ 0xff))
1288 /* Likewise, try with not.w */
1289 if (USE_MOVQ (i
^ 0xffff))
1291 /* This is the only value where neg.w is useful */
1294 /* Try also with swap */
1296 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1299 /* Otherwise, use move.l */
1303 const_int_cost (constant
)
1306 switch (const_method (constant
))
1309 /* Constants between -128 and 127 are cheap due to moveq */
1315 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1325 output_move_const_into_data_reg (operands
)
1330 i
= INTVAL (operands
[1]);
1331 switch (const_method (operands
[1]))
1334 #if defined (MOTOROLA) && !defined (CRDS)
1335 return "moveq%.l %1,%0";
1337 return "moveq %1,%0";
1340 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1341 #if defined (MOTOROLA) && !defined (CRDS)
1342 return "moveq%.l %1,%0\n\tnot%.b %0";
1344 return "moveq %1,%0\n\tnot%.b %0";
1347 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1348 #if defined (MOTOROLA) && !defined (CRDS)
1349 return "moveq%.l %1,%0\n\tnot%.w %0";
1351 return "moveq %1,%0\n\tnot%.w %0";
1354 #if defined (MOTOROLA) && !defined (CRDS)
1355 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1357 return "moveq %#-128,%0\n\tneg%.w %0";
1363 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1364 #if defined (MOTOROLA) && !defined (CRDS)
1365 return "moveq%.l %1,%0\n\tswap %0";
1367 return "moveq %1,%0\n\tswap %0";
1371 return "move%.l %1,%0";
1378 output_move_simode_const (operands
)
1381 if (operands
[1] == const0_rtx
1382 && (DATA_REG_P (operands
[0])
1383 || GET_CODE (operands
[0]) == MEM
)
1384 /* clr insns on 68000 read before writing.
1385 This isn't so on the 68010, but we have no TARGET_68010. */
1386 && ((TARGET_68020
|| TARGET_5200
)
1387 || !(GET_CODE (operands
[0]) == MEM
1388 && MEM_VOLATILE_P (operands
[0]))))
1390 else if (DATA_REG_P (operands
[0]))
1391 return output_move_const_into_data_reg (operands
);
1392 else if (ADDRESS_REG_P (operands
[0])
1393 && INTVAL (operands
[1]) < 0x8000
1394 && INTVAL (operands
[1]) >= -0x8000)
1395 return "move%.w %1,%0";
1396 else if (GET_CODE (operands
[0]) == MEM
1397 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1398 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1399 && INTVAL (operands
[1]) < 0x8000
1400 && INTVAL (operands
[1]) >= -0x8000)
1402 return "move%.l %1,%0";
1405 /* Return the best assembler insn template
1406 for moving operands[1] into operands[0] as a fullword. */
1409 singlemove_string (operands
)
1412 #ifdef SUPPORT_SUN_FPA
1413 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1414 return "fpmoves %1,%0";
1416 if (GET_CODE (operands
[1]) == CONST_INT
)
1417 return output_move_simode_const (operands
);
1418 return "move%.l %1,%0";
1422 /* Output assembler code to perform a doubleword move insn
1423 with operands OPERANDS. */
1426 output_move_double (operands
)
1431 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1436 rtx addreg0
= 0, addreg1
= 0;
1437 int dest_overlapped_low
= 0;
1438 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1443 /* First classify both operands. */
1445 if (REG_P (operands
[0]))
1447 else if (offsettable_memref_p (operands
[0]))
1449 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1451 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1453 else if (GET_CODE (operands
[0]) == MEM
)
1458 if (REG_P (operands
[1]))
1460 else if (CONSTANT_P (operands
[1]))
1462 else if (offsettable_memref_p (operands
[1]))
1464 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1466 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1468 else if (GET_CODE (operands
[1]) == MEM
)
1473 /* Check for the cases that the operand constraints are not
1474 supposed to allow to happen. Abort if we get one,
1475 because generating code for these cases is painful. */
1477 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1480 /* If one operand is decrementing and one is incrementing
1481 decrement the former register explicitly
1482 and change that operand into ordinary indexing. */
1484 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1486 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1488 output_asm_insn ("sub%.l %#12,%0", operands
);
1490 output_asm_insn ("subq%.l %#8,%0", operands
);
1491 if (GET_MODE (operands
[1]) == XFmode
)
1492 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1493 else if (GET_MODE (operands
[0]) == DFmode
)
1494 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1496 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1499 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1501 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1503 output_asm_insn ("sub%.l %#12,%1", operands
);
1505 output_asm_insn ("subq%.l %#8,%1", operands
);
1506 if (GET_MODE (operands
[1]) == XFmode
)
1507 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1508 else if (GET_MODE (operands
[1]) == DFmode
)
1509 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1511 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1515 /* If an operand is an unoffsettable memory ref, find a register
1516 we can increment temporarily to make it refer to the second word. */
1518 if (optype0
== MEMOP
)
1519 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1521 if (optype1
== MEMOP
)
1522 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1524 /* Ok, we can do one word at a time.
1525 Normally we do the low-numbered word first,
1526 but if either operand is autodecrementing then we
1527 do the high-numbered word first.
1529 In either case, set up in LATEHALF the operands to use
1530 for the high-numbered word and in some cases alter the
1531 operands in OPERANDS to be suitable for the low-numbered word. */
1535 if (optype0
== REGOP
)
1537 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1538 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1540 else if (optype0
== OFFSOP
)
1542 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1543 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1547 middlehalf
[0] = operands
[0];
1548 latehalf
[0] = operands
[0];
1551 if (optype1
== REGOP
)
1553 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1554 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1556 else if (optype1
== OFFSOP
)
1558 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1559 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1561 else if (optype1
== CNSTOP
)
1563 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1568 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1569 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1570 operands
[1] = GEN_INT (l
[0]);
1571 middlehalf
[1] = GEN_INT (l
[1]);
1572 latehalf
[1] = GEN_INT (l
[2]);
1574 else if (CONSTANT_P (operands
[1]))
1576 /* actually, no non-CONST_DOUBLE constant should ever
1579 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1580 latehalf
[1] = constm1_rtx
;
1582 latehalf
[1] = const0_rtx
;
1587 middlehalf
[1] = operands
[1];
1588 latehalf
[1] = operands
[1];
1592 /* size is not 12: */
1594 if (optype0
== REGOP
)
1595 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1596 else if (optype0
== OFFSOP
)
1597 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1599 latehalf
[0] = operands
[0];
1601 if (optype1
== REGOP
)
1602 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1603 else if (optype1
== OFFSOP
)
1604 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1605 else if (optype1
== CNSTOP
)
1606 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1608 latehalf
[1] = operands
[1];
1611 /* If insn is effectively movd N(sp),-(sp) then we will do the
1612 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1613 for the low word as well, to compensate for the first decrement of sp. */
1614 if (optype0
== PUSHOP
1615 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1616 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1617 operands
[1] = middlehalf
[1] = latehalf
[1];
1619 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1620 if the upper part of reg N does not appear in the MEM, arrange to
1621 emit the move late-half first. Otherwise, compute the MEM address
1622 into the upper part of N and use that as a pointer to the memory
1624 if (optype0
== REGOP
1625 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1627 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1629 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1630 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1632 /* If both halves of dest are used in the src memory address,
1633 compute the address into latehalf of dest.
1634 Note that this can't happen if the dest is two data regs. */
1636 xops
[0] = latehalf
[0];
1637 xops
[1] = XEXP (operands
[1], 0);
1638 output_asm_insn ("lea %a1,%0", xops
);
1639 if( GET_MODE (operands
[1]) == XFmode
)
1641 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1642 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1643 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1647 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1648 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1652 && reg_overlap_mentioned_p (middlehalf
[0],
1653 XEXP (operands
[1], 0)))
1655 /* Check for two regs used by both source and dest.
1656 Note that this can't happen if the dest is all data regs.
1657 It can happen if the dest is d6, d7, a0.
1658 But in that case, latehalf is an addr reg, so
1659 the code at compadr does ok. */
1661 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1662 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1665 /* JRV says this can't happen: */
1666 if (addreg0
|| addreg1
)
1669 /* Only the middle reg conflicts; simply put it last. */
1670 output_asm_insn (singlemove_string (operands
), operands
);
1671 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1672 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1675 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1676 /* If the low half of dest is mentioned in the source memory
1677 address, the arrange to emit the move late half first. */
1678 dest_overlapped_low
= 1;
1681 /* If one or both operands autodecrementing,
1682 do the two words, high-numbered first. */
1684 /* Likewise, the first move would clobber the source of the second one,
1685 do them in the other order. This happens only for registers;
1686 such overlap can't happen in memory unless the user explicitly
1687 sets it up, and that is an undefined circumstance. */
1689 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1690 || (optype0
== REGOP
&& optype1
== REGOP
1691 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1692 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1693 || dest_overlapped_low
)
1695 /* Make any unoffsettable addresses point at high-numbered word. */
1699 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1701 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1706 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1708 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1712 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1714 /* Undo the adds we just did. */
1716 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1718 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1722 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1724 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1726 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1729 /* Do low-numbered word. */
1730 return singlemove_string (operands
);
1733 /* Normal case: do the two words, low-numbered first. */
1735 output_asm_insn (singlemove_string (operands
), operands
);
1737 /* Do the middle one of the three words for long double */
1741 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1743 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1745 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1748 /* Make any unoffsettable addresses point at high-numbered word. */
1750 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1752 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1755 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1757 /* Undo the adds we just did. */
1761 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
1763 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1768 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
1770 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1776 /* Return a REG that occurs in ADDR with coefficient 1.
1777 ADDR can be effectively incremented by incrementing REG. */
1780 find_addr_reg (addr
)
1783 while (GET_CODE (addr
) == PLUS
)
1785 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1786 addr
= XEXP (addr
, 0);
1787 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1788 addr
= XEXP (addr
, 1);
1789 else if (CONSTANT_P (XEXP (addr
, 0)))
1790 addr
= XEXP (addr
, 1);
1791 else if (CONSTANT_P (XEXP (addr
, 1)))
1792 addr
= XEXP (addr
, 0);
1796 if (GET_CODE (addr
) == REG
)
1801 /* Store in cc_status the expressions that the condition codes will
1802 describe after execution of an instruction whose pattern is EXP.
1803 Do not alter them if the instruction would not alter the cc's. */
1805 /* On the 68000, all the insns to store in an address register fail to
1806 set the cc's. However, in some cases these instructions can make it
1807 possibly invalid to use the saved cc's. In those cases we clear out
1808 some or all of the saved cc's so they won't be used. */
1810 notice_update_cc (exp
, insn
)
1814 /* If the cc is being set from the fpa and the expression is not an
1815 explicit floating point test instruction (which has code to deal with
1816 this), reinit the CC. */
1817 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1818 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1819 && !(GET_CODE (exp
) == PARALLEL
1820 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1821 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1825 else if (GET_CODE (exp
) == SET
)
1827 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1831 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1833 if (cc_status
.value1
1834 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1835 cc_status
.value1
= 0;
1836 if (cc_status
.value2
1837 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1838 cc_status
.value2
= 0;
1840 else if (!FP_REG_P (SET_DEST (exp
))
1841 && SET_DEST (exp
) != cc0_rtx
1842 && (FP_REG_P (SET_SRC (exp
))
1843 || GET_CODE (SET_SRC (exp
)) == FIX
1844 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1845 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1849 /* A pair of move insns doesn't produce a useful overall cc. */
1850 else if (!FP_REG_P (SET_DEST (exp
))
1851 && !FP_REG_P (SET_SRC (exp
))
1852 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1853 && (GET_CODE (SET_SRC (exp
)) == REG
1854 || GET_CODE (SET_SRC (exp
)) == MEM
1855 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
1859 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1863 else if (XEXP (exp
, 0) != pc_rtx
)
1865 cc_status
.flags
= 0;
1866 cc_status
.value1
= XEXP (exp
, 0);
1867 cc_status
.value2
= XEXP (exp
, 1);
1870 else if (GET_CODE (exp
) == PARALLEL
1871 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1873 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1875 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
1877 cc_status
.flags
= 0;
1878 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1879 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
1884 if (cc_status
.value2
!= 0
1885 && ADDRESS_REG_P (cc_status
.value2
)
1886 && GET_MODE (cc_status
.value2
) == QImode
)
1888 if (cc_status
.value2
!= 0
1889 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
1890 switch (GET_CODE (cc_status
.value2
))
1892 case PLUS
: case MINUS
: case MULT
:
1893 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
1894 #if 0 /* These instructions always clear the overflow bit */
1895 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
1896 case ROTATE
: case ROTATERT
:
1898 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
1899 cc_status
.flags
|= CC_NO_OVERFLOW
;
1902 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1903 ends with a move insn moving r2 in r2's mode.
1904 Thus, the cc's are set for r2.
1905 This can set N bit spuriously. */
1906 cc_status
.flags
|= CC_NOT_NEGATIVE
;
1908 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1910 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1911 cc_status
.value2
= 0;
1912 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
1913 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
1914 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1915 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
1916 cc_status
.flags
= CC_IN_68881
;
1920 output_move_const_double (operands
)
1923 #ifdef SUPPORT_SUN_FPA
1924 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
1926 int code
= standard_sun_fpa_constant_p (operands
[1]);
1930 static char buf
[40];
1932 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
1935 return "fpmove%.d %1,%0";
1940 int code
= standard_68881_constant_p (operands
[1]);
1944 static char buf
[40];
1946 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1949 return "fmove%.d %1,%0";
1954 output_move_const_single (operands
)
1957 #ifdef SUPPORT_SUN_FPA
1960 int code
= standard_sun_fpa_constant_p (operands
[1]);
1964 static char buf
[40];
1966 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
1969 return "fpmove%.s %1,%0";
1972 #endif /* defined SUPPORT_SUN_FPA */
1974 int code
= standard_68881_constant_p (operands
[1]);
1978 static char buf
[40];
1980 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1983 return "fmove%.s %f1,%0";
1987 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1988 from the "fmovecr" instruction.
1989 The value, anded with 0xff, gives the code to use in fmovecr
1990 to get the desired constant. */
1992 /* This code has been fixed for cross-compilation. */
1994 static int inited_68881_table
= 0;
1996 char *strings_68881
[7] = {
2006 int codes_68881
[7] = {
2016 REAL_VALUE_TYPE values_68881
[7];
2018 /* Set up values_68881 array by converting the decimal values
2019 strings_68881 to binary. */
2026 enum machine_mode mode
;
2029 for (i
= 0; i
< 7; i
++)
2033 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2034 values_68881
[i
] = r
;
2036 inited_68881_table
= 1;
2040 standard_68881_constant_p (x
)
2045 enum machine_mode mode
;
2047 #ifdef NO_ASM_FMOVECR
2051 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2055 #ifndef REAL_ARITHMETIC
2056 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2057 if (! flag_pretend_float
)
2062 if (! inited_68881_table
)
2063 init_68881_table ();
2065 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2067 for (i
= 0; i
< 6; i
++)
2069 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
2070 return (codes_68881
[i
]);
2073 if (GET_MODE (x
) == SFmode
)
2076 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2077 return (codes_68881
[6]);
2079 /* larger powers of ten in the constants ram are not used
2080 because they are not equal to a `double' C constant. */
2084 /* If X is a floating-point constant, return the logarithm of X base 2,
2085 or 0 if X is not a power of 2. */
2088 floating_exact_log2 (x
)
2091 REAL_VALUE_TYPE r
, r1
;
2094 #ifndef REAL_ARITHMETIC
2095 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2096 if (! flag_pretend_float
)
2101 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2103 if (REAL_VALUES_LESS (r
, dconst0
))
2108 while (REAL_VALUES_LESS (r1
, r
))
2110 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2111 if (REAL_VALUES_EQUAL (r1
, r
))
2118 #ifdef SUPPORT_SUN_FPA
2119 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2120 from the Sun FPA's constant RAM.
2121 The value returned, anded with 0x1ff, gives the code to use in fpmove
2122 to get the desired constant. */
2124 static int inited_FPA_table
= 0;
2126 char *strings_FPA
[38] = {
2127 /* small rationals */
2140 /* Decimal equivalents of double precision values */
2141 "2.718281828459045091", /* D_E */
2142 "6.283185307179586477", /* 2 pi */
2143 "3.141592653589793116", /* D_PI */
2144 "1.570796326794896619", /* pi/2 */
2145 "1.414213562373095145", /* D_SQRT2 */
2146 "0.7071067811865475244", /* 1/sqrt(2) */
2147 "-1.570796326794896619", /* -pi/2 */
2148 "1.442695040888963387", /* D_LOG2ofE */
2149 "3.321928024887362182", /* D_LOG2of10 */
2150 "0.6931471805599452862", /* D_LOGEof2 */
2151 "2.302585092994045901", /* D_LOGEof10 */
2152 "0.3010299956639811980", /* D_LOG10of2 */
2153 "0.4342944819032518167", /* D_LOG10ofE */
2154 /* Decimal equivalents of single precision values */
2155 "2.718281745910644531", /* S_E */
2156 "6.283185307179586477", /* 2 pi */
2157 "3.141592741012573242", /* S_PI */
2158 "1.570796326794896619", /* pi/2 */
2159 "1.414213538169860840", /* S_SQRT2 */
2160 "0.7071067811865475244", /* 1/sqrt(2) */
2161 "-1.570796326794896619", /* -pi/2 */
2162 "1.442695021629333496", /* S_LOG2ofE */
2163 "3.321928024291992188", /* S_LOG2of10 */
2164 "0.6931471824645996094", /* S_LOGEof2 */
2165 "2.302585124969482442", /* S_LOGEof10 */
2166 "0.3010300099849700928", /* S_LOG10of2 */
2167 "0.4342944920063018799", /* S_LOG10ofE */
2171 int codes_FPA
[38] = {
2172 /* small rationals */
2185 /* double precision */
2199 /* single precision */
2215 REAL_VALUE_TYPE values_FPA
[38];
2217 /* This code has been fixed for cross-compilation. */
2222 enum machine_mode mode
;
2227 for (i
= 0; i
< 38; i
++)
2231 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2234 inited_FPA_table
= 1;
2239 standard_sun_fpa_constant_p (x
)
2245 #ifndef REAL_ARITHMETIC
2246 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2247 if (! flag_pretend_float
)
2252 if (! inited_FPA_table
)
2255 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2257 for (i
=0; i
<12; i
++)
2259 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2260 return (codes_FPA
[i
]);
2263 if (GET_MODE (x
) == SFmode
)
2265 for (i
=25; i
<38; i
++)
2267 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2268 return (codes_FPA
[i
]);
2273 for (i
=12; i
<25; i
++)
2275 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2276 return (codes_FPA
[i
]);
2281 #endif /* define SUPPORT_SUN_FPA */
2283 /* A C compound statement to output to stdio stream STREAM the
2284 assembler syntax for an instruction operand X. X is an RTL
2287 CODE is a value that can be used to specify one of several ways
2288 of printing the operand. It is used when identical operands
2289 must be printed differently depending on the context. CODE
2290 comes from the `%' specification that was used to request
2291 printing of the operand. If the specification was just `%DIGIT'
2292 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2293 is the ASCII code for LTR.
2295 If X is a register, this macro should print the register's name.
2296 The names can be found in an array `reg_names' whose type is
2297 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2299 When the machine description has a specification `%PUNCT' (a `%'
2300 followed by a punctuation character), this macro is called with
2301 a null pointer for X and the punctuation character for CODE.
2303 The m68k specific codes are:
2305 '.' for dot needed in Motorola-style opcode names.
2306 '-' for an operand pushing on the stack:
2307 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2308 '+' for an operand pushing on the stack:
2309 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2310 '@' for a reference to the top word on the stack:
2311 sp@, (sp) or (%sp) depending on the style of syntax.
2312 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2313 but & in SGS syntax, $ in CRDS/UNOS syntax).
2314 '!' for the cc register (used in an `and to cc' insn).
2315 '$' for the letter `s' in an op code, but only on the 68040.
2316 '&' for the letter `d' in an op code, but only on the 68040.
2317 '/' for register prefix needed by longlong.h.
2319 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2320 'd' to force memory addressing to be absolute, not relative.
2321 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2322 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2323 than directly). Second part of 'y' below.
2324 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2325 or print pair of registers as rx:ry.
2326 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2327 CONST_DOUBLE's as SunFPA constant RAM registers if
2328 possible, so it should not be used except for the SunFPA.
2333 print_operand (file
, op
, letter
)
2334 FILE *file
; /* file to write to */
2335 rtx op
; /* operand to print */
2336 int letter
; /* %<letter> or 0 */
2342 #if defined (MOTOROLA) && !defined (CRDS)
2343 asm_fprintf (file
, ".");
2346 else if (letter
== '#')
2348 asm_fprintf (file
, "%0I");
2350 else if (letter
== '-')
2353 asm_fprintf (file
, "-(%Rsp)");
2355 asm_fprintf (file
, "%Rsp@-");
2358 else if (letter
== '+')
2361 asm_fprintf (file
, "(%Rsp)+");
2363 asm_fprintf (file
, "%Rsp@+");
2366 else if (letter
== '@')
2369 asm_fprintf (file
, "(%Rsp)");
2371 asm_fprintf (file
, "%Rsp@");
2374 else if (letter
== '!')
2376 asm_fprintf (file
, "%Rfpcr");
2378 else if (letter
== '$')
2380 if (TARGET_68040_ONLY
)
2382 fprintf (file
, "s");
2385 else if (letter
== '&')
2387 if (TARGET_68040_ONLY
)
2389 fprintf (file
, "d");
2392 else if (letter
== '/')
2394 asm_fprintf (file
, "%R");
2396 else if (GET_CODE (op
) == REG
)
2398 #ifdef SUPPORT_SUN_FPA
2400 && (letter
== 'y' || letter
== 'x')
2401 && GET_MODE (op
) == DFmode
)
2403 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2404 reg_names
[REGNO (op
)+1]);
2410 /* Print out the second register name of a register pair.
2411 I.e., R (6) => 7. */
2412 fputs (reg_names
[REGNO (op
) + 1], file
);
2414 fputs (reg_names
[REGNO (op
)], file
);
2417 else if (GET_CODE (op
) == MEM
)
2419 output_address (XEXP (op
, 0));
2420 if (letter
== 'd' && ! TARGET_68020
2421 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2422 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2423 && INTVAL (XEXP (op
, 0)) < 0x8000
2424 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2427 fprintf (file
, ".l");
2429 fprintf (file
, ":l");
2433 #ifdef SUPPORT_SUN_FPA
2434 else if ((letter
== 'y' || letter
== 'w')
2435 && GET_CODE (op
) == CONST_DOUBLE
2436 && (i
= standard_sun_fpa_constant_p (op
)))
2438 fprintf (file
, "%%%d", i
& 0x1ff);
2441 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2444 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2445 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2447 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2450 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2451 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2453 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2456 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2457 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2461 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2466 /* A C compound statement to output to stdio stream STREAM the
2467 assembler syntax for an instruction operand that is a memory
2468 reference whose address is ADDR. ADDR is an RTL expression.
2470 Note that this contains a kludge that knows that the only reason
2471 we have an address (plus (label_ref...) (reg...)) when not generating
2472 PIC code is in the insn before a tablejump, and we know that m68k.md
2473 generates a label LInnn: on such an insn.
2475 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2476 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2478 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2479 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2480 we want. This difference can be accommodated by using an assembler
2481 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2482 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2483 macro. See m68k/sgs.h for an example; for versions without the bug.
2484 Some assemblers refuse all the above solutions. The workaround is to
2485 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2488 They also do not like things like "pea 1.w", so we simple leave off
2489 the .w on small constants.
2491 This routine is responsible for distinguishing between -fpic and -fPIC
2492 style relocations in an address. When generating -fpic code the
2493 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2494 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2496 #ifndef ASM_OUTPUT_CASE_FETCH
2499 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2500 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2502 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2503 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2506 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2507 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2509 #endif /* ASM_OUTPUT_CASE_FETCH */
2512 print_operand_address (file
, addr
)
2516 register rtx reg1
, reg2
, breg
, ireg
;
2519 switch (GET_CODE (addr
))
2523 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2525 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2530 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2532 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2537 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2539 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2543 reg1
= reg2
= ireg
= breg
= offset
= 0;
2544 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2546 offset
= XEXP (addr
, 0);
2547 addr
= XEXP (addr
, 1);
2549 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2551 offset
= XEXP (addr
, 1);
2552 addr
= XEXP (addr
, 0);
2554 if (GET_CODE (addr
) != PLUS
)
2558 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2560 reg1
= XEXP (addr
, 0);
2561 addr
= XEXP (addr
, 1);
2563 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2565 reg1
= XEXP (addr
, 1);
2566 addr
= XEXP (addr
, 0);
2568 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2570 reg1
= XEXP (addr
, 0);
2571 addr
= XEXP (addr
, 1);
2573 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2575 reg1
= XEXP (addr
, 1);
2576 addr
= XEXP (addr
, 0);
2578 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2580 reg1
= XEXP (addr
, 0);
2581 addr
= XEXP (addr
, 1);
2583 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2585 reg1
= XEXP (addr
, 1);
2586 addr
= XEXP (addr
, 0);
2588 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2589 || GET_CODE (addr
) == SIGN_EXTEND
)
2601 #if 0 /* for OLD_INDEXING */
2602 else if (GET_CODE (addr
) == PLUS
)
2604 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2606 reg2
= XEXP (addr
, 0);
2607 addr
= XEXP (addr
, 1);
2609 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2611 reg2
= XEXP (addr
, 1);
2612 addr
= XEXP (addr
, 0);
2624 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2625 || GET_CODE (reg1
) == MULT
))
2626 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2631 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2636 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2637 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2640 if (GET_CODE (ireg
) == MULT
)
2642 scale
= INTVAL (XEXP (ireg
, 1));
2643 ireg
= XEXP (ireg
, 0);
2645 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2647 ASM_OUTPUT_CASE_FETCH (file
,
2648 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2649 reg_names
[REGNO (XEXP (ireg
, 0))]);
2650 fprintf (file
, "w");
2654 ASM_OUTPUT_CASE_FETCH (file
,
2655 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2656 reg_names
[REGNO (ireg
)]);
2657 fprintf (file
, "l");
2662 fprintf (file
, "*%d", scale
);
2664 fprintf (file
, ":%d", scale
);
2670 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2671 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2673 ASM_OUTPUT_CASE_FETCH (file
,
2674 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2675 reg_names
[REGNO (breg
)]);
2676 fprintf (file
, "l)");
2679 if (ireg
!= 0 || breg
!= 0)
2686 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2693 output_addr_const (file
, addr
);
2694 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2695 fprintf (file
, "@GOT");
2697 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2703 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2706 output_addr_const (file
, addr
);
2707 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2708 fprintf (file
, ":w");
2709 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2710 fprintf (file
, ":l");
2712 if (addr
!= 0 && ireg
!= 0)
2717 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2719 scale
= INTVAL (XEXP (ireg
, 1));
2720 ireg
= XEXP (ireg
, 0);
2722 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2725 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2727 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2733 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2735 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2741 fprintf (file
, "*%d", scale
);
2743 fprintf (file
, ":%d", scale
);
2749 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2750 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2752 ASM_OUTPUT_CASE_FETCH (file
,
2753 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2754 reg_names
[REGNO (reg1
)]);
2755 fprintf (file
, "l)");
2758 /* FALL-THROUGH (is this really what we want? */
2760 if (GET_CODE (addr
) == CONST_INT
2761 && INTVAL (addr
) < 0x8000
2762 && INTVAL (addr
) >= -0x8000)
2766 /* Many SGS assemblers croak on size specifiers for constants. */
2767 fprintf (file
, "%d", INTVAL (addr
));
2769 fprintf (file
, "%d.w", INTVAL (addr
));
2772 fprintf (file
, "%d:w", INTVAL (addr
));
2777 output_addr_const (file
, addr
);
2783 /* Check for cases where a clr insns can be omitted from code using
2784 strict_low_part sets. For example, the second clrl here is not needed:
2785 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2787 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2788 insn we are checking for redundancy. TARGET is the register set by the
2792 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2793 enum machine_mode mode
;
2799 p
= prev_nonnote_insn (first_insn
);
2803 /* If it isn't an insn, then give up. */
2804 if (GET_CODE (p
) != INSN
)
2807 if (reg_set_p (target
, p
))
2809 rtx set
= single_set (p
);
2812 /* If it isn't an easy to recognize insn, then give up. */
2816 dest
= SET_DEST (set
);
2818 /* If this sets the entire target register to zero, then our
2819 first_insn is redundant. */
2820 if (rtx_equal_p (dest
, target
)
2821 && SET_SRC (set
) == const0_rtx
)
2823 else if (GET_CODE (dest
) == STRICT_LOW_PART
2824 && GET_CODE (XEXP (dest
, 0)) == REG
2825 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2826 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2827 <= GET_MODE_SIZE (mode
)))
2828 /* This is a strict low part set which modifies less than
2829 we are using, so it is safe. */
2835 p
= prev_nonnote_insn (p
);
2842 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2843 range carefully since this predicate is used in DImode contexts. Also, we
2844 need some extra crud to make it work when hosted on 64-bit machines. */
2847 const_uint32_operand (op
, mode
)
2849 enum machine_mode mode
;
2851 #if HOST_BITS_PER_WIDE_INT > 32
2852 /* All allowed constants will fit a CONST_INT. */
2853 return (GET_CODE (op
) == CONST_INT
2854 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
2856 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
2857 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
2861 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
2862 to check the range carefully since this predicate is used in DImode
2866 const_sint32_operand (op
, mode
)
2868 enum machine_mode mode
;
2870 /* All allowed constants will fit a CONST_INT. */
2871 return (GET_CODE (op
) == CONST_INT
2872 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));