1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* The minimum number of integer registers that we want to save with the
74 movem instruction. Using two movel instructions instead of a single
75 moveml is about 15% faster for the 68020 and 68030 at no expense in
77 #define MIN_MOVEM_REGS 3
79 /* The minimum number of floating point registers that we want to save
80 with the fmovem instruction. */
81 #define MIN_FMOVEM_REGS 1
83 /* Structure describing stack frame layout. */
86 /* Stack pointer to frame pointer offset. */
89 /* Offset of FPU registers. */
90 HOST_WIDE_INT foffset
;
92 /* Frame size in bytes (rounded up). */
95 /* Data and address register. */
97 unsigned int reg_mask
;
101 unsigned int fpu_mask
;
103 /* Offsets relative to ARG_POINTER. */
104 HOST_WIDE_INT frame_pointer_offset
;
105 HOST_WIDE_INT stack_pointer_offset
;
107 /* Function which the above information refers to. */
111 /* Current frame information calculated by m68k_compute_frame_layout(). */
112 static struct m68k_frame current_frame
;
114 /* Structure describing an m68k address.
116 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
117 with null fields evaluating to 0. Here:
119 - BASE satisfies m68k_legitimate_base_reg_p
120 - INDEX satisfies m68k_legitimate_index_reg_p
121 - OFFSET satisfies m68k_legitimate_constant_address_p
123 INDEX is either HImode or SImode. The other fields are SImode.
125 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
126 the address is (BASE)+. */
127 struct m68k_address
{
135 static bool m68k_handle_option (size_t, const char *, int);
136 static rtx
find_addr_reg (rtx
);
137 static const char *singlemove_string (rtx
*);
138 #ifdef M68K_TARGET_COFF
139 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
140 #endif /* M68K_TARGET_COFF */
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_ok_for_sibcall_p (tree
, tree
);
150 static bool m68k_rtx_costs (rtx
, int, int, int *);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands
;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_DEFAULT_TARGET_FLAGS
200 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
201 #undef TARGET_HANDLE_OPTION
202 #define TARGET_HANDLE_OPTION m68k_handle_option
204 #undef TARGET_RTX_COSTS
205 #define TARGET_RTX_COSTS m68k_rtx_costs
207 #undef TARGET_ATTRIBUTE_TABLE
208 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
210 #undef TARGET_PROMOTE_PROTOTYPES
211 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
213 #undef TARGET_STRUCT_VALUE_RTX
214 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
216 #undef TARGET_CANNOT_FORCE_CONST_MEM
217 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
219 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
220 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
222 static const struct attribute_spec m68k_attribute_table
[] =
224 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
225 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
226 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
227 { NULL
, 0, 0, false, false, false, NULL
}
230 struct gcc_target targetm
= TARGET_INITIALIZER
;
232 /* Base flags for 68k ISAs. */
233 #define FL_FOR_isa_00 FL_ISA_68000
234 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
235 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
236 generated 68881 code for 68020 and 68030 targets unless explicitly told
238 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
239 | FL_BITFIELD | FL_68881)
240 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
241 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
243 /* Base flags for ColdFire ISAs. */
244 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
245 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
246 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
247 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
248 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
252 /* Traditional 68000 instruction sets. */
258 /* ColdFire instruction set variants. */
266 /* Information about one of the -march, -mcpu or -mtune arguments. */
267 struct m68k_target_selection
269 /* The argument being described. */
272 /* For -mcpu, this is the device selected by the option.
273 For -mtune and -march, it is a representative device
274 for the microarchitecture or ISA respectively. */
275 enum target_device device
;
277 /* The M68K_DEVICE fields associated with DEVICE. See the comment
278 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
280 enum uarch_type microarch
;
285 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
286 static const struct m68k_target_selection all_devices
[] =
288 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
289 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
290 #include "m68k-devices.def"
292 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
295 /* A list of all ISAs, mapping each one to a representative device.
296 Used for -march selection. */
297 static const struct m68k_target_selection all_isas
[] =
299 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
300 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
301 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
302 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
303 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
304 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
305 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
306 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
308 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
310 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
311 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
314 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
317 /* A list of all microarchitectures, mapping each one to a representative
318 device. Used for -mtune selection. */
319 static const struct m68k_target_selection all_microarchs
[] =
321 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
322 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
323 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
324 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
325 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
326 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
327 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
328 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
329 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
330 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
331 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
333 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
334 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
338 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
341 /* The entries associated with the -mcpu, -march and -mtune settings,
342 or null for options that have not been used. */
343 const struct m68k_target_selection
*m68k_cpu_entry
;
344 const struct m68k_target_selection
*m68k_arch_entry
;
345 const struct m68k_target_selection
*m68k_tune_entry
;
347 /* Which CPU we are generating code for. */
348 enum target_device m68k_cpu
;
350 /* Which microarchitecture to tune for. */
351 enum uarch_type m68k_tune
;
353 /* Which FPU to use. */
354 enum fpu_type m68k_fpu
;
356 /* The set of FL_* flags that apply to the target processor. */
357 unsigned int m68k_cpu_flags
;
359 /* Asm templates for calling or jumping to an arbitrary symbolic address,
360 or NULL if such calls or jumps are not supported. The address is held
362 const char *m68k_symbolic_call
;
363 const char *m68k_symbolic_jump
;
365 /* See whether TABLE has an entry with name NAME. Return true and
366 store the entry in *ENTRY if so, otherwise return false and
367 leave *ENTRY alone. */
370 m68k_find_selection (const struct m68k_target_selection
**entry
,
371 const struct m68k_target_selection
*table
,
376 for (i
= 0; table
[i
].name
; i
++)
377 if (strcmp (table
[i
].name
, name
) == 0)
385 /* Implement TARGET_HANDLE_OPTION. */
388 m68k_handle_option (size_t code
, const char *arg
, int value
)
393 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
396 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
399 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
402 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
405 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
408 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
411 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
414 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
417 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
421 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
424 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
428 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
431 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
433 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
436 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
438 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
441 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
444 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
447 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
450 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
454 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
456 case OPT_mshared_library_id_
:
457 if (value
> MAX_LIBRARY_ID
)
458 error ("-mshared-library-id=%s is not between 0 and %d",
459 arg
, MAX_LIBRARY_ID
);
461 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
469 /* Sometimes certain combinations of command options do not make
470 sense on a particular target machine. You can define a macro
471 `OVERRIDE_OPTIONS' to take account of this. This macro, if
472 defined, is executed once just after all the command options have
475 Don't use this macro to turn on various extra optimizations for
476 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
479 override_options (void)
481 const struct m68k_target_selection
*entry
;
482 unsigned long target_mask
;
490 -march=ARCH should generate code that runs any processor
491 implementing architecture ARCH. -mcpu=CPU should override -march
492 and should generate code that runs on processor CPU, making free
493 use of any instructions that CPU understands. -mtune=UARCH applies
494 on top of -mcpu or -march and optimizes the code for UARCH. It does
495 not change the target architecture. */
498 /* Complain if the -march setting is for a different microarchitecture,
499 or includes flags that the -mcpu setting doesn't. */
501 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
502 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
503 warning (0, "-mcpu=%s conflicts with -march=%s",
504 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
506 entry
= m68k_cpu_entry
;
509 entry
= m68k_arch_entry
;
512 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
514 m68k_cpu_flags
= entry
->flags
;
516 /* Use the architecture setting to derive default values for
519 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
520 target_mask
|= MASK_BITFIELD
;
521 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
522 target_mask
|= MASK_CF_HWDIV
;
523 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
524 target_mask
|= MASK_HARD_FLOAT
;
525 target_flags
|= target_mask
& ~target_flags_explicit
;
527 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
528 m68k_cpu
= entry
->device
;
530 m68k_tune
= m68k_tune_entry
->microarch
;
531 #ifdef M68K_DEFAULT_TUNE
532 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
533 m68k_tune
= M68K_DEFAULT_TUNE
;
536 m68k_tune
= entry
->microarch
;
538 /* Set the type of FPU. */
539 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
540 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
543 if (TARGET_COLDFIRE_FPU
)
545 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
546 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
549 /* Sanity check to ensure that msep-data and mid-sahred-library are not
550 * both specified together. Doing so simply doesn't make sense.
552 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
553 error ("cannot specify both -msep-data and -mid-shared-library");
555 /* If we're generating code for a separate A5 relative data segment,
556 * we've got to enable -fPIC as well. This might be relaxable to
557 * -fpic but it hasn't been tested properly.
559 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
562 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
563 error if the target does not support them. */
564 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
565 error ("-mpcrel -fPIC is not currently supported on selected cpu");
567 /* ??? A historic way of turning on pic, or is this intended to
568 be an embedded thing that doesn't have the same name binding
569 significance that it does on hosted ELF systems? */
570 if (TARGET_PCREL
&& flag_pic
== 0)
575 #if MOTOROLA && !defined (USE_GAS)
576 m68k_symbolic_call
= "jsr %a0";
577 m68k_symbolic_jump
= "jmp %a0";
579 m68k_symbolic_call
= "jbsr %a0";
580 m68k_symbolic_jump
= "jra %a0";
583 else if (TARGET_ID_SHARED_LIBRARY
)
584 /* All addresses must be loaded from the GOT. */
586 else if (TARGET_68020
|| TARGET_ISAB
)
590 m68k_symbolic_call
= "bsr.l %c0";
591 m68k_symbolic_jump
= "bra.l %c0";
596 m68k_symbolic_call
= "bsr.l %p0";
597 m68k_symbolic_jump
= "bra.l %p0";
599 m68k_symbolic_call
= "bsr %p0";
600 m68k_symbolic_jump
= "bra %p0";
603 /* Turn off function cse if we are doing PIC. We always want
604 function call to be done as `bsr foo@PLTPC'. */
605 /* ??? It's traditional to do this for -mpcrel too, but it isn't
606 clear how intentional that is. */
607 flag_no_function_cse
= 1;
610 SUBTARGET_OVERRIDE_OPTIONS
;
613 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
614 given argument and NAME is the argument passed to -mcpu. Return NULL
615 if -mcpu was not passed. */
618 m68k_cpp_cpu_ident (const char *prefix
)
622 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
625 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
626 given argument and NAME is the name of the representative device for
627 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
630 m68k_cpp_cpu_family (const char *prefix
)
634 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
637 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt_handler"
638 attribute and interrupt_thread if FUNC has an "interrupt_thread"
639 attribute. Otherwise, return m68k_fk_normal_function. */
641 enum m68k_function_kind
642 m68k_get_function_kind (tree func
)
646 if (TREE_CODE (func
) != FUNCTION_DECL
)
649 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
651 return m68k_fk_interrupt_handler
;
653 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
655 return m68k_fk_interrupt_thread
;
657 return m68k_fk_normal_function
;
660 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
661 struct attribute_spec.handler. */
663 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
664 tree args ATTRIBUTE_UNUSED
,
665 int flags ATTRIBUTE_UNUSED
,
668 if (TREE_CODE (*node
) != FUNCTION_DECL
)
670 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
671 IDENTIFIER_POINTER (name
));
672 *no_add_attrs
= true;
675 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
677 error ("multiple interrupt attributes not allowed");
678 *no_add_attrs
= true;
682 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
684 error ("interrupt_thread is available only on fido");
685 *no_add_attrs
= true;
692 m68k_compute_frame_layout (void)
696 enum m68k_function_kind func_kind
=
697 m68k_get_function_kind (current_function_decl
);
698 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
699 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
701 /* Only compute the frame once per function.
702 Don't cache information until reload has been completed. */
703 if (current_frame
.funcdef_no
== current_function_funcdef_no
707 current_frame
.size
= (get_frame_size () + 3) & -4;
711 /* Interrupt thread does not need to save any register. */
712 if (!interrupt_thread
)
713 for (regno
= 0; regno
< 16; regno
++)
714 if (m68k_save_reg (regno
, interrupt_handler
))
716 mask
|= 1 << (regno
- D0_REG
);
719 current_frame
.offset
= saved
* 4;
720 current_frame
.reg_no
= saved
;
721 current_frame
.reg_mask
= mask
;
723 current_frame
.foffset
= 0;
725 if (TARGET_HARD_FLOAT
)
727 /* Interrupt thread does not need to save any register. */
728 if (!interrupt_thread
)
729 for (regno
= 16; regno
< 24; regno
++)
730 if (m68k_save_reg (regno
, interrupt_handler
))
732 mask
|= 1 << (regno
- FP0_REG
);
735 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
736 current_frame
.offset
+= current_frame
.foffset
;
738 current_frame
.fpu_no
= saved
;
739 current_frame
.fpu_mask
= mask
;
741 /* Remember what function this frame refers to. */
742 current_frame
.funcdef_no
= current_function_funcdef_no
;
746 m68k_initial_elimination_offset (int from
, int to
)
749 /* The arg pointer points 8 bytes before the start of the arguments,
750 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
751 frame pointer in most frames. */
752 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
753 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
754 return argptr_offset
;
756 m68k_compute_frame_layout ();
758 gcc_assert (to
== STACK_POINTER_REGNUM
);
761 case ARG_POINTER_REGNUM
:
762 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
763 case FRAME_POINTER_REGNUM
:
764 return current_frame
.offset
+ current_frame
.size
;
770 /* Refer to the array `regs_ever_live' to determine which registers
771 to save; `regs_ever_live[I]' is nonzero if register number I
772 is ever used in the function. This function is responsible for
773 knowing which registers should not be saved even if used.
774 Return true if we need to save REGNO. */
777 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
779 if (flag_pic
&& regno
== PIC_REG
)
781 /* A function that receives a nonlocal goto must save all call-saved
783 if (current_function_has_nonlocal_label
)
785 if (current_function_uses_pic_offset_table
)
787 /* Reload may introduce constant pool references into a function
788 that thitherto didn't need a PIC register. Note that the test
789 above will not catch that case because we will only set
790 current_function_uses_pic_offset_table when emitting
791 the address reloads. */
792 if (current_function_uses_const_pool
)
796 if (current_function_calls_eh_return
)
801 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
802 if (test
== INVALID_REGNUM
)
809 /* Fixed regs we never touch. */
810 if (fixed_regs
[regno
])
813 /* The frame pointer (if it is such) is handled specially. */
814 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
817 /* Interrupt handlers must also save call_used_regs
818 if they are live or when calling nested functions. */
819 if (interrupt_handler
)
821 if (regs_ever_live
[regno
])
824 if (!current_function_is_leaf
&& call_used_regs
[regno
])
828 /* Never need to save registers that aren't touched. */
829 if (!regs_ever_live
[regno
])
832 /* Otherwise save everything that isn't call-clobbered. */
833 return !call_used_regs
[regno
];
836 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
837 the lowest memory address. COUNT is the number of registers to be
838 moved, with register REGNO + I being moved if bit I of MASK is set.
839 STORE_P specifies the direction of the move and ADJUST_STACK_P says
840 whether or not this is pre-decrement (if STORE_P) or post-increment
841 (if !STORE_P) operation. */
844 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
845 unsigned int count
, unsigned int regno
,
846 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
849 rtx body
, addr
, src
, operands
[2];
850 enum machine_mode mode
;
852 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
853 mode
= reg_raw_mode
[regno
];
858 src
= plus_constant (base
, (count
859 * GET_MODE_SIZE (mode
)
860 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
861 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
864 for (; mask
!= 0; mask
>>= 1, regno
++)
867 addr
= plus_constant (base
, offset
);
868 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
869 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
870 XVECEXP (body
, 0, i
++)
871 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
872 offset
+= GET_MODE_SIZE (mode
);
874 gcc_assert (i
== XVECLEN (body
, 0));
876 return emit_insn (body
);
879 /* Make INSN a frame-related instruction. */
882 m68k_set_frame_related (rtx insn
)
887 RTX_FRAME_RELATED_P (insn
) = 1;
888 body
= PATTERN (insn
);
889 if (GET_CODE (body
) == PARALLEL
)
890 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
891 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
894 /* Emit RTL for the "prologue" define_expand. */
897 m68k_expand_prologue (void)
899 HOST_WIDE_INT fsize_with_regs
;
900 rtx limit
, src
, dest
, insn
;
902 m68k_compute_frame_layout ();
904 /* If the stack limit is a symbol, we can check it here,
905 before actually allocating the space. */
906 if (current_function_limit_stack
907 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
909 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
910 if (!LEGITIMATE_CONSTANT_P (limit
))
912 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
913 limit
= gen_rtx_REG (Pmode
, D0_REG
);
915 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
916 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
917 cc0_rtx
, const0_rtx
),
921 fsize_with_regs
= current_frame
.size
;
924 /* ColdFire's move multiple instructions do not allow pre-decrement
925 addressing. Add the size of movem saves to the initial stack
926 allocation instead. */
927 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
928 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
929 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
930 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
933 if (frame_pointer_needed
)
935 if (fsize_with_regs
== 0 && TUNE_68040
)
937 /* On the 68040, two separate moves are faster than link.w 0. */
938 dest
= gen_frame_mem (Pmode
,
939 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
940 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
941 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
944 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
945 m68k_set_frame_related
946 (emit_insn (gen_link (frame_pointer_rtx
,
947 GEN_INT (-4 - fsize_with_regs
))));
950 m68k_set_frame_related
951 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
952 m68k_set_frame_related
953 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
955 GEN_INT (-fsize_with_regs
))));
958 else if (fsize_with_regs
!= 0)
959 m68k_set_frame_related
960 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
962 GEN_INT (-fsize_with_regs
))));
964 if (current_frame
.fpu_mask
)
966 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
968 m68k_set_frame_related
969 (m68k_emit_movem (stack_pointer_rtx
,
970 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
971 current_frame
.fpu_no
, FP0_REG
,
972 current_frame
.fpu_mask
, true, true));
977 /* If we're using moveml to save the integer registers,
978 the stack pointer will point to the bottom of the moveml
979 save area. Find the stack offset of the first FP register. */
980 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
983 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
984 m68k_set_frame_related
985 (m68k_emit_movem (stack_pointer_rtx
, offset
,
986 current_frame
.fpu_no
, FP0_REG
,
987 current_frame
.fpu_mask
, true, false));
991 /* If the stack limit is not a symbol, check it here.
992 This has the disadvantage that it may be too late... */
993 if (current_function_limit_stack
)
995 if (REG_P (stack_limit_rtx
))
997 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
998 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
999 cc0_rtx
, const0_rtx
),
1002 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1003 warning (0, "stack limit expression is not supported");
1006 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1008 /* Store each register separately in the same order moveml does. */
1011 for (i
= 16; i
-- > 0; )
1012 if (current_frame
.reg_mask
& (1 << i
))
1014 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1015 dest
= gen_frame_mem (SImode
,
1016 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1017 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1022 if (TARGET_COLDFIRE
)
1023 /* The required register save space has already been allocated.
1024 The first register should be stored at (%sp). */
1025 m68k_set_frame_related
1026 (m68k_emit_movem (stack_pointer_rtx
, 0,
1027 current_frame
.reg_no
, D0_REG
,
1028 current_frame
.reg_mask
, true, false));
1030 m68k_set_frame_related
1031 (m68k_emit_movem (stack_pointer_rtx
,
1032 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1033 current_frame
.reg_no
, D0_REG
,
1034 current_frame
.reg_mask
, true, true));
1039 && current_function_uses_pic_offset_table
)
1041 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
1042 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
1048 /* Return true if a simple (return) instruction is sufficient for this
1049 instruction (i.e. if no epilogue is needed). */
1052 m68k_use_return_insn (void)
1054 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1057 m68k_compute_frame_layout ();
1058 return current_frame
.offset
== 0;
1061 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1062 SIBCALL_P says which.
1064 The function epilogue should not depend on the current stack pointer!
1065 It should use the frame pointer only, if there is a frame pointer.
1066 This is mandatory because of alloca; we also take advantage of it to
1067 omit stack adjustments before returning. */
1070 m68k_expand_epilogue (bool sibcall_p
)
1072 HOST_WIDE_INT fsize
, fsize_with_regs
;
1073 bool big
, restore_from_sp
;
1075 m68k_compute_frame_layout ();
1077 fsize
= current_frame
.size
;
1079 restore_from_sp
= false;
1081 /* FIXME : current_function_is_leaf below is too strong.
1082 What we really need to know there is if there could be pending
1083 stack adjustment needed at that point. */
1084 restore_from_sp
= (!frame_pointer_needed
1085 || (!current_function_calls_alloca
1086 && current_function_is_leaf
));
1088 /* fsize_with_regs is the size we need to adjust the sp when
1089 popping the frame. */
1090 fsize_with_regs
= fsize
;
1091 if (TARGET_COLDFIRE
&& restore_from_sp
)
1093 /* ColdFire's move multiple instructions do not allow post-increment
1094 addressing. Add the size of movem loads to the final deallocation
1096 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1097 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1098 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1099 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1102 if (current_frame
.offset
+ fsize
>= 0x8000
1104 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1107 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1108 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1110 /* ColdFire's move multiple instructions do not support the
1111 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1112 stack-based restore. */
1113 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1114 GEN_INT (-(current_frame
.offset
+ fsize
)));
1115 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1116 gen_rtx_REG (Pmode
, A1_REG
),
1117 frame_pointer_rtx
));
1118 restore_from_sp
= true;
1122 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1128 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1130 /* Restore each register separately in the same order moveml does. */
1132 HOST_WIDE_INT offset
;
1134 offset
= current_frame
.offset
+ fsize
;
1135 for (i
= 0; i
< 16; i
++)
1136 if (current_frame
.reg_mask
& (1 << i
))
1142 /* Generate the address -OFFSET(%fp,%a1.l). */
1143 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1144 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1145 addr
= plus_constant (addr
, -offset
);
1147 else if (restore_from_sp
)
1148 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1150 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1151 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1152 gen_frame_mem (SImode
, addr
));
1153 offset
-= GET_MODE_SIZE (SImode
);
1156 else if (current_frame
.reg_mask
)
1159 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1160 gen_rtx_REG (Pmode
, A1_REG
),
1162 -(current_frame
.offset
+ fsize
),
1163 current_frame
.reg_no
, D0_REG
,
1164 current_frame
.reg_mask
, false, false);
1165 else if (restore_from_sp
)
1166 m68k_emit_movem (stack_pointer_rtx
, 0,
1167 current_frame
.reg_no
, D0_REG
,
1168 current_frame
.reg_mask
, false,
1171 m68k_emit_movem (frame_pointer_rtx
,
1172 -(current_frame
.offset
+ fsize
),
1173 current_frame
.reg_no
, D0_REG
,
1174 current_frame
.reg_mask
, false, false);
1177 if (current_frame
.fpu_no
> 0)
1180 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1181 gen_rtx_REG (Pmode
, A1_REG
),
1183 -(current_frame
.foffset
+ fsize
),
1184 current_frame
.fpu_no
, FP0_REG
,
1185 current_frame
.fpu_mask
, false, false);
1186 else if (restore_from_sp
)
1188 if (TARGET_COLDFIRE
)
1192 /* If we used moveml to restore the integer registers, the
1193 stack pointer will still point to the bottom of the moveml
1194 save area. Find the stack offset of the first FP
1196 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1199 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1200 m68k_emit_movem (stack_pointer_rtx
, offset
,
1201 current_frame
.fpu_no
, FP0_REG
,
1202 current_frame
.fpu_mask
, false, false);
1205 m68k_emit_movem (stack_pointer_rtx
, 0,
1206 current_frame
.fpu_no
, FP0_REG
,
1207 current_frame
.fpu_mask
, false, true);
1210 m68k_emit_movem (frame_pointer_rtx
,
1211 -(current_frame
.foffset
+ fsize
),
1212 current_frame
.fpu_no
, FP0_REG
,
1213 current_frame
.fpu_mask
, false, false);
1216 if (frame_pointer_needed
)
1217 emit_insn (gen_unlink (frame_pointer_rtx
));
1218 else if (fsize_with_regs
)
1219 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1221 GEN_INT (fsize_with_regs
)));
1223 if (current_function_calls_eh_return
)
1224 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1226 EH_RETURN_STACKADJ_RTX
));
1229 emit_insn (gen_rtx_RETURN (VOIDmode
));
1232 /* Return true if X is a valid comparison operator for the dbcc
1235 Note it rejects floating point comparison operators.
1236 (In the future we could use Fdbcc).
1238 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1241 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1243 switch (GET_CODE (x
))
1245 case EQ
: case NE
: case GTU
: case LTU
:
1249 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1251 case GT
: case LT
: case GE
: case LE
:
1252 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1258 /* Return nonzero if flags are currently in the 68881 flag register. */
1260 flags_in_68881 (void)
1262 /* We could add support for these in the future */
1263 return cc_status
.flags
& CC_IN_68881
;
1266 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. We cannot use sibcalls
1267 for nested functions because we use the static chain register for
1271 m68k_ok_for_sibcall_p (tree decl ATTRIBUTE_UNUSED
, tree exp
)
1273 return TREE_OPERAND (exp
, 2) == NULL
;
1276 /* Convert X to a legitimate function call memory reference and return the
1280 m68k_legitimize_call_address (rtx x
)
1282 gcc_assert (MEM_P (x
));
1283 if (call_operand (XEXP (x
, 0), VOIDmode
))
1285 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1288 /* Likewise for sibling calls. */
1291 m68k_legitimize_sibcall_address (rtx x
)
1293 gcc_assert (MEM_P (x
));
1294 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1297 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1298 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1301 /* Output a dbCC; jCC sequence. Note we do not handle the
1302 floating point version of this sequence (Fdbcc). We also
1303 do not handle alternative conditions when CC_NO_OVERFLOW is
1304 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1305 kick those out before we get here. */
1308 output_dbcc_and_branch (rtx
*operands
)
1310 switch (GET_CODE (operands
[3]))
1313 output_asm_insn (MOTOROLA
1314 ? "dbeq %0,%l1\n\tjbeq %l2"
1315 : "dbeq %0,%l1\n\tjeq %l2",
1320 output_asm_insn (MOTOROLA
1321 ? "dbne %0,%l1\n\tjbne %l2"
1322 : "dbne %0,%l1\n\tjne %l2",
1327 output_asm_insn (MOTOROLA
1328 ? "dbgt %0,%l1\n\tjbgt %l2"
1329 : "dbgt %0,%l1\n\tjgt %l2",
1334 output_asm_insn (MOTOROLA
1335 ? "dbhi %0,%l1\n\tjbhi %l2"
1336 : "dbhi %0,%l1\n\tjhi %l2",
1341 output_asm_insn (MOTOROLA
1342 ? "dblt %0,%l1\n\tjblt %l2"
1343 : "dblt %0,%l1\n\tjlt %l2",
1348 output_asm_insn (MOTOROLA
1349 ? "dbcs %0,%l1\n\tjbcs %l2"
1350 : "dbcs %0,%l1\n\tjcs %l2",
1355 output_asm_insn (MOTOROLA
1356 ? "dbge %0,%l1\n\tjbge %l2"
1357 : "dbge %0,%l1\n\tjge %l2",
1362 output_asm_insn (MOTOROLA
1363 ? "dbcc %0,%l1\n\tjbcc %l2"
1364 : "dbcc %0,%l1\n\tjcc %l2",
1369 output_asm_insn (MOTOROLA
1370 ? "dble %0,%l1\n\tjble %l2"
1371 : "dble %0,%l1\n\tjle %l2",
1376 output_asm_insn (MOTOROLA
1377 ? "dbls %0,%l1\n\tjbls %l2"
1378 : "dbls %0,%l1\n\tjls %l2",
1386 /* If the decrement is to be done in SImode, then we have
1387 to compensate for the fact that dbcc decrements in HImode. */
1388 switch (GET_MODE (operands
[0]))
1391 output_asm_insn (MOTOROLA
1392 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1393 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1406 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1409 enum rtx_code op_code
= GET_CODE (op
);
1411 /* This does not produce a useful cc. */
1414 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1415 below. Swap the operands and change the op if these requirements
1416 are not fulfilled. */
1417 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1421 operand1
= operand2
;
1423 op_code
= swap_condition (op_code
);
1425 loperands
[0] = operand1
;
1426 if (GET_CODE (operand1
) == REG
)
1427 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1429 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1430 if (operand2
!= const0_rtx
)
1432 loperands
[2] = operand2
;
1433 if (GET_CODE (operand2
) == REG
)
1434 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1436 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1438 loperands
[4] = gen_label_rtx ();
1439 if (operand2
!= const0_rtx
)
1441 output_asm_insn (MOTOROLA
1442 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1443 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1448 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1449 output_asm_insn ("tst%.l %0", loperands
);
1451 output_asm_insn ("cmp%.w #0,%0", loperands
);
1453 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1455 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1456 output_asm_insn ("tst%.l %1", loperands
);
1458 output_asm_insn ("cmp%.w #0,%1", loperands
);
1461 loperands
[5] = dest
;
1466 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1467 CODE_LABEL_NUMBER (loperands
[4]));
1468 output_asm_insn ("seq %5", loperands
);
1472 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1473 CODE_LABEL_NUMBER (loperands
[4]));
1474 output_asm_insn ("sne %5", loperands
);
1478 loperands
[6] = gen_label_rtx ();
1479 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1481 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1482 CODE_LABEL_NUMBER (loperands
[4]));
1483 output_asm_insn ("sgt %5", loperands
);
1484 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1485 CODE_LABEL_NUMBER (loperands
[6]));
1489 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1490 CODE_LABEL_NUMBER (loperands
[4]));
1491 output_asm_insn ("shi %5", loperands
);
1495 loperands
[6] = gen_label_rtx ();
1496 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1498 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1499 CODE_LABEL_NUMBER (loperands
[4]));
1500 output_asm_insn ("slt %5", loperands
);
1501 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1502 CODE_LABEL_NUMBER (loperands
[6]));
1506 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1507 CODE_LABEL_NUMBER (loperands
[4]));
1508 output_asm_insn ("scs %5", loperands
);
1512 loperands
[6] = gen_label_rtx ();
1513 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1515 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1516 CODE_LABEL_NUMBER (loperands
[4]));
1517 output_asm_insn ("sge %5", loperands
);
1518 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1519 CODE_LABEL_NUMBER (loperands
[6]));
1523 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1524 CODE_LABEL_NUMBER (loperands
[4]));
1525 output_asm_insn ("scc %5", loperands
);
1529 loperands
[6] = gen_label_rtx ();
1530 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1532 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1533 CODE_LABEL_NUMBER (loperands
[4]));
1534 output_asm_insn ("sle %5", loperands
);
1535 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1536 CODE_LABEL_NUMBER (loperands
[6]));
1540 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1541 CODE_LABEL_NUMBER (loperands
[4]));
1542 output_asm_insn ("sls %5", loperands
);
1552 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1554 operands
[0] = countop
;
1555 operands
[1] = dataop
;
1557 if (GET_CODE (countop
) == CONST_INT
)
1559 register int count
= INTVAL (countop
);
1560 /* If COUNT is bigger than size of storage unit in use,
1561 advance to the containing unit of same size. */
1562 if (count
> signpos
)
1564 int offset
= (count
& ~signpos
) / 8;
1565 count
= count
& signpos
;
1566 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1568 if (count
== signpos
)
1569 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1571 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1573 /* These three statements used to use next_insns_test_no...
1574 but it appears that this should do the same job. */
1576 && next_insn_tests_no_inequality (insn
))
1579 && next_insn_tests_no_inequality (insn
))
1582 && next_insn_tests_no_inequality (insn
))
1584 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1585 On some m68k variants unfortunately that's slower than btst.
1586 On 68000 and higher, that should also work for all HImode operands. */
1587 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1589 if (count
== 3 && DATA_REG_P (operands
[1])
1590 && next_insn_tests_no_inequality (insn
))
1592 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1593 return "move%.w %1,%%ccr";
1595 if (count
== 2 && DATA_REG_P (operands
[1])
1596 && next_insn_tests_no_inequality (insn
))
1598 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1599 return "move%.w %1,%%ccr";
1601 /* count == 1 followed by bvc/bvs and
1602 count == 0 followed by bcc/bcs are also possible, but need
1603 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1606 cc_status
.flags
= CC_NOT_NEGATIVE
;
1608 return "btst %0,%1";
1611 /* Return true if X is a legitimate base register. STRICT_P says
1612 whether we need strict checking. */
1615 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1617 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1618 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1623 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1624 : !DATA_REGNO_P (REGNO (x
)) && !FP_REGNO_P (REGNO (x
))));
1627 /* Return true if X is a legitimate index register. STRICT_P says
1628 whether we need strict checking. */
1631 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1633 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1638 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1639 : !FP_REGNO_P (REGNO (x
))));
1642 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1643 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1644 ADDRESS if so. STRICT_P says whether we need strict checking. */
1647 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1651 /* Check for a scale factor. */
1653 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1654 && GET_CODE (x
) == MULT
1655 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1656 && (INTVAL (XEXP (x
, 1)) == 2
1657 || INTVAL (XEXP (x
, 1)) == 4
1658 || (INTVAL (XEXP (x
, 1)) == 8
1659 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1661 scale
= INTVAL (XEXP (x
, 1));
1665 /* Check for a word extension. */
1666 if (!TARGET_COLDFIRE
1667 && GET_CODE (x
) == SIGN_EXTEND
1668 && GET_MODE (XEXP (x
, 0)) == HImode
)
1671 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1673 address
->scale
= scale
;
1681 /* Return true if X is an illegitimate symbolic constant. */
1684 m68k_illegitimate_symbolic_constant_p (rtx x
)
1688 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1690 split_const (x
, &base
, &offset
);
1691 if (GET_CODE (base
) == SYMBOL_REF
1692 && !offset_within_block_p (base
, INTVAL (offset
)))
1698 /* Return true if X is a legitimate constant address that can reach
1699 bytes in the range [X, X + REACH). STRICT_P says whether we need
1703 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1707 if (!CONSTANT_ADDRESS_P (x
))
1711 && !(strict_p
&& TARGET_PCREL
)
1712 && symbolic_operand (x
, VOIDmode
))
1715 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1717 split_const (x
, &base
, &offset
);
1718 if (GET_CODE (base
) == SYMBOL_REF
1719 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1726 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1727 labels will become jump tables. */
1730 m68k_jump_table_ref_p (rtx x
)
1732 if (GET_CODE (x
) != LABEL_REF
)
1736 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1739 x
= next_nonnote_insn (x
);
1740 return x
&& JUMP_TABLE_DATA_P (x
);
1743 /* Return true if X is a legitimate address for values of mode MODE.
1744 STRICT_P says whether strict checking is needed. If the address
1745 is valid, describe its components in *ADDRESS. */
1748 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1749 bool strict_p
, struct m68k_address
*address
)
1753 memset (address
, 0, sizeof (*address
));
1755 if (mode
== BLKmode
)
1758 reach
= GET_MODE_SIZE (mode
);
1760 /* Check for (An) (mode 2). */
1761 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1767 /* Check for -(An) and (An)+ (modes 3 and 4). */
1768 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1769 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1771 address
->code
= GET_CODE (x
);
1772 address
->base
= XEXP (x
, 0);
1776 /* Check for (d16,An) (mode 5). */
1777 if (GET_CODE (x
) == PLUS
1778 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1779 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1780 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1782 address
->base
= XEXP (x
, 0);
1783 address
->offset
= XEXP (x
, 1);
1787 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1788 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1791 && GET_CODE (x
) == PLUS
1792 && XEXP (x
, 0) == pic_offset_table_rtx
1793 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1794 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1796 address
->base
= XEXP (x
, 0);
1797 address
->offset
= XEXP (x
, 1);
1801 /* The ColdFire FPU only accepts addressing modes 2-5. */
1802 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1805 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1806 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1807 All these modes are variations of mode 7. */
1808 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1810 address
->offset
= x
;
1814 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1817 ??? do_tablejump creates these addresses before placing the target
1818 label, so we have to assume that unplaced labels are jump table
1819 references. It seems unlikely that we would ever generate indexed
1820 accesses to unplaced labels in other cases. */
1821 if (GET_CODE (x
) == PLUS
1822 && m68k_jump_table_ref_p (XEXP (x
, 1))
1823 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1825 address
->offset
= XEXP (x
, 1);
1829 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1830 (bd,An,Xn.SIZE*SCALE) addresses. */
1834 /* Check for a nonzero base displacement. */
1835 if (GET_CODE (x
) == PLUS
1836 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1838 address
->offset
= XEXP (x
, 1);
1842 /* Check for a suppressed index register. */
1843 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1849 /* Check for a suppressed base register. Do not allow this case
1850 for non-symbolic offsets as it effectively gives gcc freedom
1851 to treat data registers as base registers, which can generate
1854 && symbolic_operand (address
->offset
, VOIDmode
)
1855 && m68k_decompose_index (x
, strict_p
, address
))
1860 /* Check for a nonzero base displacement. */
1861 if (GET_CODE (x
) == PLUS
1862 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1863 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1865 address
->offset
= XEXP (x
, 1);
1870 /* We now expect the sum of a base and an index. */
1871 if (GET_CODE (x
) == PLUS
)
1873 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1874 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1876 address
->base
= XEXP (x
, 0);
1880 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1881 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1883 address
->base
= XEXP (x
, 1);
1890 /* Return true if X is a legitimate address for values of mode MODE.
1891 STRICT_P says whether strict checking is needed. */
1894 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1896 struct m68k_address address
;
1898 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1901 /* Return true if X is a memory, describing its address in ADDRESS if so.
1902 Apply strict checking if called during or after reload. */
1905 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1908 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1909 reload_in_progress
|| reload_completed
,
1913 /* Return true if X matches the 'Q' constraint. It must be a memory
1914 with a base address and no constant offset or index. */
1917 m68k_matches_q_p (rtx x
)
1919 struct m68k_address address
;
1921 return (m68k_legitimate_mem_p (x
, &address
)
1922 && address
.code
== UNKNOWN
1928 /* Return true if X matches the 'U' constraint. It must be a base address
1929 with a constant offset and no index. */
1932 m68k_matches_u_p (rtx x
)
1934 struct m68k_address address
;
1936 return (m68k_legitimate_mem_p (x
, &address
)
1937 && address
.code
== UNKNOWN
1943 /* Legitimize PIC addresses. If the address is already
1944 position-independent, we return ORIG. Newly generated
1945 position-independent addresses go to REG. If we need more
1946 than one register, we lose.
1948 An address is legitimized by making an indirect reference
1949 through the Global Offset Table with the name of the symbol
1952 The assembler and linker are responsible for placing the
1953 address of the symbol in the GOT. The function prologue
1954 is responsible for initializing a5 to the starting address
1957 The assembler is also responsible for translating a symbol name
1958 into a constant displacement from the start of the GOT.
1960 A quick example may make things a little clearer:
1962 When not generating PIC code to store the value 12345 into _foo
1963 we would generate the following code:
1967 When generating PIC two transformations are made. First, the compiler
1968 loads the address of foo into a register. So the first transformation makes:
1973 The code in movsi will intercept the lea instruction and call this
1974 routine which will transform the instructions into:
1976 movel a5@(_foo:w), a0
1980 That (in a nutshell) is how *all* symbol and label references are
1984 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1989 /* First handle a simple SYMBOL_REF or LABEL_REF */
1990 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1994 pic_ref
= gen_rtx_MEM (Pmode
,
1995 gen_rtx_PLUS (Pmode
,
1996 pic_offset_table_rtx
, orig
));
1997 current_function_uses_pic_offset_table
= 1;
1998 MEM_READONLY_P (pic_ref
) = 1;
1999 emit_move_insn (reg
, pic_ref
);
2002 else if (GET_CODE (orig
) == CONST
)
2006 /* Make sure this has not already been legitimized. */
2007 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2008 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2013 /* legitimize both operands of the PLUS */
2014 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2016 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2017 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2018 base
== reg
? 0 : reg
);
2020 if (GET_CODE (orig
) == CONST_INT
)
2021 return plus_constant (base
, INTVAL (orig
));
2022 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2023 /* Likewise, should we set special REG_NOTEs here? */
2029 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
2031 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2033 /* Return the type of move that should be used for integer I. */
2036 const_method (HOST_WIDE_INT i
)
2043 /* The ColdFire doesn't have byte or word operations. */
2044 /* FIXME: This may not be useful for the m68060 either. */
2045 if (!TARGET_COLDFIRE
)
2047 /* if -256 < N < 256 but N is not in range for a moveq
2048 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2049 if (USE_MOVQ (i
^ 0xff))
2051 /* Likewise, try with not.w */
2052 if (USE_MOVQ (i
^ 0xffff))
2054 /* This is the only value where neg.w is useful */
2059 /* Try also with swap. */
2061 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2066 /* Try using MVZ/MVS with an immediate value to load constants. */
2067 if (i
>= 0 && i
<= 65535)
2069 if (i
>= -32768 && i
<= 32767)
2073 /* Otherwise, use move.l */
2077 /* Return the cost of moving constant I into a data register. */
2080 const_int_cost (HOST_WIDE_INT i
)
2082 switch (const_method (i
))
2085 /* Constants between -128 and 127 are cheap due to moveq. */
2093 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2103 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2108 /* Constant zero is super cheap due to clr instruction. */
2109 if (x
== const0_rtx
)
2112 *total
= const_int_cost (INTVAL (x
));
2122 /* Make 0.0 cheaper than other floating constants to
2123 encourage creating tstsf and tstdf insns. */
2124 if (outer_code
== COMPARE
2125 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2131 /* These are vaguely right for a 68020. */
2132 /* The costs for long multiply have been adjusted to work properly
2133 in synth_mult on the 68020, relative to an average of the time
2134 for add and the time for shift, taking away a little more because
2135 sometimes move insns are needed. */
2136 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2142 : TARGET_COLDFIRE ? 3 : 13)
2147 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2148 : TARGET_COLDFIRE ? 2 : 8)
2151 (TARGET_CF_HWDIV ? 11 \
2152 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2155 /* An lea costs about three times as much as a simple add. */
2156 if (GET_MODE (x
) == SImode
2157 && GET_CODE (XEXP (x
, 1)) == REG
2158 && GET_CODE (XEXP (x
, 0)) == MULT
2159 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2160 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2161 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2162 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2163 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2165 /* lea an@(dx:l:i),am */
2166 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2176 *total
= COSTS_N_INSNS(1);
2181 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2183 if (INTVAL (XEXP (x
, 1)) < 16)
2184 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2186 /* We're using clrw + swap for these cases. */
2187 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2190 *total
= COSTS_N_INSNS (10); /* Worst case. */
2193 /* A shift by a big integer takes an extra instruction. */
2194 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2195 && (INTVAL (XEXP (x
, 1)) == 16))
2197 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2200 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2201 && !(INTVAL (XEXP (x
, 1)) > 0
2202 && INTVAL (XEXP (x
, 1)) <= 8))
2204 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2210 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2211 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2212 && GET_MODE (x
) == SImode
)
2213 *total
= COSTS_N_INSNS (MULW_COST
);
2214 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2215 *total
= COSTS_N_INSNS (MULW_COST
);
2217 *total
= COSTS_N_INSNS (MULL_COST
);
2224 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2225 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2226 else if (TARGET_CF_HWDIV
)
2227 *total
= COSTS_N_INSNS (18);
2229 *total
= COSTS_N_INSNS (43); /* div.l */
2237 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2241 output_move_const_into_data_reg (rtx
*operands
)
2245 i
= INTVAL (operands
[1]);
2246 switch (const_method (i
))
2249 return "mvzw %1,%0";
2251 return "mvsw %1,%0";
2253 return "moveq %1,%0";
2256 operands
[1] = GEN_INT (i
^ 0xff);
2257 return "moveq %1,%0\n\tnot%.b %0";
2260 operands
[1] = GEN_INT (i
^ 0xffff);
2261 return "moveq %1,%0\n\tnot%.w %0";
2264 return "moveq #-128,%0\n\tneg%.w %0";
2269 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2270 return "moveq %1,%0\n\tswap %0";
2273 return "move%.l %1,%0";
2279 /* Return true if I can be handled by ISA B's mov3q instruction. */
2282 valid_mov3q_const (HOST_WIDE_INT i
)
2284 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2287 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2288 I is the value of OPERANDS[1]. */
2291 output_move_simode_const (rtx
*operands
)
2297 src
= INTVAL (operands
[1]);
2299 && (DATA_REG_P (dest
) || MEM_P (dest
))
2300 /* clr insns on 68000 read before writing. */
2301 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2302 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2304 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2305 return "mov3q%.l %1,%0";
2306 else if (src
== 0 && ADDRESS_REG_P (dest
))
2307 return "sub%.l %0,%0";
2308 else if (DATA_REG_P (dest
))
2309 return output_move_const_into_data_reg (operands
);
2310 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2312 if (valid_mov3q_const (src
))
2313 return "mov3q%.l %1,%0";
2314 return "move%.w %1,%0";
2316 else if (MEM_P (dest
)
2317 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2318 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2319 && IN_RANGE (src
, -0x8000, 0x7fff))
2321 if (valid_mov3q_const (src
))
2322 return "mov3q%.l %1,%-";
2325 return "move%.l %1,%0";
2329 output_move_simode (rtx
*operands
)
2331 if (GET_CODE (operands
[1]) == CONST_INT
)
2332 return output_move_simode_const (operands
);
2333 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2334 || GET_CODE (operands
[1]) == CONST
)
2335 && push_operand (operands
[0], SImode
))
2337 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2338 || GET_CODE (operands
[1]) == CONST
)
2339 && ADDRESS_REG_P (operands
[0]))
2340 return "lea %a1,%0";
2341 return "move%.l %1,%0";
2345 output_move_himode (rtx
*operands
)
2347 if (GET_CODE (operands
[1]) == CONST_INT
)
2349 if (operands
[1] == const0_rtx
2350 && (DATA_REG_P (operands
[0])
2351 || GET_CODE (operands
[0]) == MEM
)
2352 /* clr insns on 68000 read before writing. */
2353 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2354 || !(GET_CODE (operands
[0]) == MEM
2355 && MEM_VOLATILE_P (operands
[0]))))
2357 else if (operands
[1] == const0_rtx
2358 && ADDRESS_REG_P (operands
[0]))
2359 return "sub%.l %0,%0";
2360 else if (DATA_REG_P (operands
[0])
2361 && INTVAL (operands
[1]) < 128
2362 && INTVAL (operands
[1]) >= -128)
2363 return "moveq %1,%0";
2364 else if (INTVAL (operands
[1]) < 0x8000
2365 && INTVAL (operands
[1]) >= -0x8000)
2366 return "move%.w %1,%0";
2368 else if (CONSTANT_P (operands
[1]))
2369 return "move%.l %1,%0";
2370 /* Recognize the insn before a tablejump, one that refers
2371 to a table of offsets. Such an insn will need to refer
2372 to a label on the insn. So output one. Use the label-number
2373 of the table of offsets to generate this label. This code,
2374 and similar code below, assumes that there will be at most one
2375 reference to each table. */
2376 if (GET_CODE (operands
[1]) == MEM
2377 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2378 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2379 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2381 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2383 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2384 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2386 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2387 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2389 return "move%.w %1,%0";
2393 output_move_qimode (rtx
*operands
)
2395 /* 68k family always modifies the stack pointer by at least 2, even for
2396 byte pushes. The 5200 (ColdFire) does not do this. */
2398 /* This case is generated by pushqi1 pattern now. */
2399 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2400 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2401 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2402 && ! ADDRESS_REG_P (operands
[1])
2403 && ! TARGET_COLDFIRE
));
2405 /* clr and st insns on 68000 read before writing. */
2406 if (!ADDRESS_REG_P (operands
[0])
2407 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2408 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2410 if (operands
[1] == const0_rtx
)
2412 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2413 && GET_CODE (operands
[1]) == CONST_INT
2414 && (INTVAL (operands
[1]) & 255) == 255)
2420 if (GET_CODE (operands
[1]) == CONST_INT
2421 && DATA_REG_P (operands
[0])
2422 && INTVAL (operands
[1]) < 128
2423 && INTVAL (operands
[1]) >= -128)
2424 return "moveq %1,%0";
2425 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2426 return "sub%.l %0,%0";
2427 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2428 return "move%.l %1,%0";
2429 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2430 from address registers. */
2431 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2432 return "move%.w %1,%0";
2433 return "move%.b %1,%0";
2437 output_move_stricthi (rtx
*operands
)
2439 if (operands
[1] == const0_rtx
2440 /* clr insns on 68000 read before writing. */
2441 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2442 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2444 return "move%.w %1,%0";
2448 output_move_strictqi (rtx
*operands
)
2450 if (operands
[1] == const0_rtx
2451 /* clr insns on 68000 read before writing. */
2452 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2453 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2455 return "move%.b %1,%0";
2458 /* Return the best assembler insn template
2459 for moving operands[1] into operands[0] as a fullword. */
2462 singlemove_string (rtx
*operands
)
2464 if (GET_CODE (operands
[1]) == CONST_INT
)
2465 return output_move_simode_const (operands
);
2466 return "move%.l %1,%0";
2470 /* Output assembler code to perform a doubleword move insn
2471 with operands OPERANDS. */
2474 output_move_double (rtx
*operands
)
2478 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2483 rtx addreg0
= 0, addreg1
= 0;
2484 int dest_overlapped_low
= 0;
2485 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2490 /* First classify both operands. */
2492 if (REG_P (operands
[0]))
2494 else if (offsettable_memref_p (operands
[0]))
2496 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2498 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2500 else if (GET_CODE (operands
[0]) == MEM
)
2505 if (REG_P (operands
[1]))
2507 else if (CONSTANT_P (operands
[1]))
2509 else if (offsettable_memref_p (operands
[1]))
2511 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2513 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2515 else if (GET_CODE (operands
[1]) == MEM
)
2520 /* Check for the cases that the operand constraints are not supposed
2521 to allow to happen. Generating code for these cases is
2523 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2525 /* If one operand is decrementing and one is incrementing
2526 decrement the former register explicitly
2527 and change that operand into ordinary indexing. */
2529 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2531 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2533 output_asm_insn ("sub%.l #12,%0", operands
);
2535 output_asm_insn ("subq%.l #8,%0", operands
);
2536 if (GET_MODE (operands
[1]) == XFmode
)
2537 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2538 else if (GET_MODE (operands
[0]) == DFmode
)
2539 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2541 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2544 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2546 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2548 output_asm_insn ("sub%.l #12,%1", operands
);
2550 output_asm_insn ("subq%.l #8,%1", operands
);
2551 if (GET_MODE (operands
[1]) == XFmode
)
2552 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2553 else if (GET_MODE (operands
[1]) == DFmode
)
2554 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2556 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2560 /* If an operand is an unoffsettable memory ref, find a register
2561 we can increment temporarily to make it refer to the second word. */
2563 if (optype0
== MEMOP
)
2564 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2566 if (optype1
== MEMOP
)
2567 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2569 /* Ok, we can do one word at a time.
2570 Normally we do the low-numbered word first,
2571 but if either operand is autodecrementing then we
2572 do the high-numbered word first.
2574 In either case, set up in LATEHALF the operands to use
2575 for the high-numbered word and in some cases alter the
2576 operands in OPERANDS to be suitable for the low-numbered word. */
2580 if (optype0
== REGOP
)
2582 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2583 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2585 else if (optype0
== OFFSOP
)
2587 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2588 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2592 middlehalf
[0] = operands
[0];
2593 latehalf
[0] = operands
[0];
2596 if (optype1
== REGOP
)
2598 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2599 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2601 else if (optype1
== OFFSOP
)
2603 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2604 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2606 else if (optype1
== CNSTOP
)
2608 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2613 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2614 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2615 operands
[1] = GEN_INT (l
[0]);
2616 middlehalf
[1] = GEN_INT (l
[1]);
2617 latehalf
[1] = GEN_INT (l
[2]);
2621 /* No non-CONST_DOUBLE constant should ever appear
2623 gcc_assert (!CONSTANT_P (operands
[1]));
2628 middlehalf
[1] = operands
[1];
2629 latehalf
[1] = operands
[1];
2633 /* size is not 12: */
2635 if (optype0
== REGOP
)
2636 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2637 else if (optype0
== OFFSOP
)
2638 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2640 latehalf
[0] = operands
[0];
2642 if (optype1
== REGOP
)
2643 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2644 else if (optype1
== OFFSOP
)
2645 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2646 else if (optype1
== CNSTOP
)
2647 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2649 latehalf
[1] = operands
[1];
2652 /* If insn is effectively movd N(sp),-(sp) then we will do the
2653 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2654 for the low word as well, to compensate for the first decrement of sp. */
2655 if (optype0
== PUSHOP
2656 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2657 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2658 operands
[1] = middlehalf
[1] = latehalf
[1];
2660 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2661 if the upper part of reg N does not appear in the MEM, arrange to
2662 emit the move late-half first. Otherwise, compute the MEM address
2663 into the upper part of N and use that as a pointer to the memory
2665 if (optype0
== REGOP
2666 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2668 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2670 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2671 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2673 /* If both halves of dest are used in the src memory address,
2674 compute the address into latehalf of dest.
2675 Note that this can't happen if the dest is two data regs. */
2677 xops
[0] = latehalf
[0];
2678 xops
[1] = XEXP (operands
[1], 0);
2679 output_asm_insn ("lea %a1,%0", xops
);
2680 if (GET_MODE (operands
[1]) == XFmode
)
2682 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2683 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2684 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2688 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2689 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2693 && reg_overlap_mentioned_p (middlehalf
[0],
2694 XEXP (operands
[1], 0)))
2696 /* Check for two regs used by both source and dest.
2697 Note that this can't happen if the dest is all data regs.
2698 It can happen if the dest is d6, d7, a0.
2699 But in that case, latehalf is an addr reg, so
2700 the code at compadr does ok. */
2702 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2703 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2706 /* JRV says this can't happen: */
2707 gcc_assert (!addreg0
&& !addreg1
);
2709 /* Only the middle reg conflicts; simply put it last. */
2710 output_asm_insn (singlemove_string (operands
), operands
);
2711 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2712 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2715 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2716 /* If the low half of dest is mentioned in the source memory
2717 address, the arrange to emit the move late half first. */
2718 dest_overlapped_low
= 1;
2721 /* If one or both operands autodecrementing,
2722 do the two words, high-numbered first. */
2724 /* Likewise, the first move would clobber the source of the second one,
2725 do them in the other order. This happens only for registers;
2726 such overlap can't happen in memory unless the user explicitly
2727 sets it up, and that is an undefined circumstance. */
2729 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2730 || (optype0
== REGOP
&& optype1
== REGOP
2731 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2732 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2733 || dest_overlapped_low
)
2735 /* Make any unoffsettable addresses point at high-numbered word. */
2739 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2741 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2746 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2748 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2752 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2754 /* Undo the adds we just did. */
2756 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2758 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2762 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2764 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2766 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2769 /* Do low-numbered word. */
2770 return singlemove_string (operands
);
2773 /* Normal case: do the two words, low-numbered first. */
2775 output_asm_insn (singlemove_string (operands
), operands
);
2777 /* Do the middle one of the three words for long double */
2781 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2783 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2785 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2788 /* Make any unoffsettable addresses point at high-numbered word. */
2790 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2792 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2795 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2797 /* Undo the adds we just did. */
2801 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2803 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2808 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2810 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2817 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2818 new rtx with the correct mode. */
2821 force_mode (enum machine_mode mode
, rtx orig
)
2823 if (mode
== GET_MODE (orig
))
2826 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2829 return gen_rtx_REG (mode
, REGNO (orig
));
2833 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2835 return reg_renumber
&& FP_REG_P (op
);
2838 /* Emit insns to move operands[1] into operands[0].
2840 Return 1 if we have written out everything that needs to be done to
2841 do the move. Otherwise, return 0 and the caller will emit the move
2844 Note SCRATCH_REG may not be in the proper mode depending on how it
2845 will be used. This routine is responsible for creating a new copy
2846 of SCRATCH_REG in the proper mode. */
2849 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2851 register rtx operand0
= operands
[0];
2852 register rtx operand1
= operands
[1];
2856 && reload_in_progress
&& GET_CODE (operand0
) == REG
2857 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2858 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2859 else if (scratch_reg
2860 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2861 && GET_CODE (SUBREG_REG (operand0
)) == REG
2862 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2864 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2865 the code which tracks sets/uses for delete_output_reload. */
2866 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2867 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2868 SUBREG_BYTE (operand0
));
2869 operand0
= alter_subreg (&temp
);
2873 && reload_in_progress
&& GET_CODE (operand1
) == REG
2874 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2875 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2876 else if (scratch_reg
2877 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2878 && GET_CODE (SUBREG_REG (operand1
)) == REG
2879 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2881 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2882 the code which tracks sets/uses for delete_output_reload. */
2883 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2884 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2885 SUBREG_BYTE (operand1
));
2886 operand1
= alter_subreg (&temp
);
2889 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2890 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2891 != XEXP (operand0
, 0)))
2892 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2893 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2894 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2895 != XEXP (operand1
, 0)))
2896 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2898 /* Handle secondary reloads for loads/stores of FP registers where
2899 the address is symbolic by using the scratch register */
2900 if (fp_reg_operand (operand0
, mode
)
2901 && ((GET_CODE (operand1
) == MEM
2902 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2903 || ((GET_CODE (operand1
) == SUBREG
2904 && GET_CODE (XEXP (operand1
, 0)) == MEM
2905 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2908 if (GET_CODE (operand1
) == SUBREG
)
2909 operand1
= XEXP (operand1
, 0);
2911 /* SCRATCH_REG will hold an address. We want
2912 it in SImode regardless of what mode it was originally given
2914 scratch_reg
= force_mode (SImode
, scratch_reg
);
2916 /* D might not fit in 14 bits either; for such cases load D into
2918 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2920 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2921 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2923 XEXP (XEXP (operand1
, 0), 0),
2927 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2928 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2929 gen_rtx_MEM (mode
, scratch_reg
)));
2932 else if (fp_reg_operand (operand1
, mode
)
2933 && ((GET_CODE (operand0
) == MEM
2934 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2935 || ((GET_CODE (operand0
) == SUBREG
)
2936 && GET_CODE (XEXP (operand0
, 0)) == MEM
2937 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2940 if (GET_CODE (operand0
) == SUBREG
)
2941 operand0
= XEXP (operand0
, 0);
2943 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2944 it in SIMODE regardless of what mode it was originally given
2946 scratch_reg
= force_mode (SImode
, scratch_reg
);
2948 /* D might not fit in 14 bits either; for such cases load D into
2950 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2952 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2953 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2956 XEXP (XEXP (operand0
, 0),
2961 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2962 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2966 /* Handle secondary reloads for loads of FP registers from constant
2967 expressions by forcing the constant into memory.
2969 use scratch_reg to hold the address of the memory location.
2971 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2972 NO_REGS when presented with a const_int and an register class
2973 containing only FP registers. Doing so unfortunately creates
2974 more problems than it solves. Fix this for 2.5. */
2975 else if (fp_reg_operand (operand0
, mode
)
2976 && CONSTANT_P (operand1
)
2981 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2982 it in SIMODE regardless of what mode it was originally given
2984 scratch_reg
= force_mode (SImode
, scratch_reg
);
2986 /* Force the constant into memory and put the address of the
2987 memory location into scratch_reg. */
2988 xoperands
[0] = scratch_reg
;
2989 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2990 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2992 /* Now load the destination register. */
2993 emit_insn (gen_rtx_SET (mode
, operand0
,
2994 gen_rtx_MEM (mode
, scratch_reg
)));
2998 /* Now have insn-emit do whatever it normally does. */
3002 /* Split one or more DImode RTL references into pairs of SImode
3003 references. The RTL can be REG, offsettable MEM, integer constant, or
3004 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3005 split and "num" is its length. lo_half and hi_half are output arrays
3006 that parallel "operands". */
3009 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3013 rtx op
= operands
[num
];
3015 /* simplify_subreg refuses to split volatile memory addresses,
3016 but we still have to handle it. */
3017 if (GET_CODE (op
) == MEM
)
3019 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3020 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3024 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3025 GET_MODE (op
) == VOIDmode
3026 ? DImode
: GET_MODE (op
), 4);
3027 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3028 GET_MODE (op
) == VOIDmode
3029 ? DImode
: GET_MODE (op
), 0);
3034 /* Split X into a base and a constant offset, storing them in *BASE
3035 and *OFFSET respectively. */
3038 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3041 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3043 *offset
+= INTVAL (XEXP (x
, 1));
3049 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3050 instruction. STORE_P says whether the move is a load or store.
3052 If the instruction uses post-increment or pre-decrement addressing,
3053 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3054 adjustment. This adjustment will be made by the first element of
3055 PARALLEL, with the loads or stores starting at element 1. If the
3056 instruction does not use post-increment or pre-decrement addressing,
3057 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3058 start at element 0. */
3061 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3062 HOST_WIDE_INT automod_offset
, bool store_p
)
3064 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3065 HOST_WIDE_INT offset
, mem_offset
;
3067 enum reg_class rclass
;
3069 len
= XVECLEN (pattern
, 0);
3070 first
= (automod_base
!= NULL
);
3074 /* Stores must be pre-decrement and loads must be post-increment. */
3075 if (store_p
!= (automod_offset
< 0))
3078 /* Work out the base and offset for lowest memory location. */
3079 base
= automod_base
;
3080 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3084 /* Allow any valid base and offset in the first access. */
3091 for (i
= first
; i
< len
; i
++)
3093 /* We need a plain SET. */
3094 set
= XVECEXP (pattern
, 0, i
);
3095 if (GET_CODE (set
) != SET
)
3098 /* Check that we have a memory location... */
3099 mem
= XEXP (set
, !store_p
);
3100 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3103 /* ...with the right address. */
3106 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3107 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3108 There are no mode restrictions for 680x0 besides the
3109 automodification rules enforced above. */
3111 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3116 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3117 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3121 /* Check that we have a register of the required mode and class. */
3122 reg
= XEXP (set
, store_p
);
3124 || !HARD_REGISTER_P (reg
)
3125 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3130 /* The register must belong to RCLASS and have a higher number
3131 than the register in the previous SET. */
3132 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3133 || REGNO (last_reg
) >= REGNO (reg
))
3138 /* Work out which register class we need. */
3139 if (INT_REGNO_P (REGNO (reg
)))
3140 rclass
= GENERAL_REGS
;
3141 else if (FP_REGNO_P (REGNO (reg
)))
3148 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3151 /* If we have an automodification, check whether the final offset is OK. */
3152 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3155 /* Reject unprofitable cases. */
3156 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3162 /* Return the assembly code template for a movem or fmovem instruction
3163 whose pattern is given by PATTERN. Store the template's operands
3166 If the instruction uses post-increment or pre-decrement addressing,
3167 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3168 is true if this is a store instruction. */
3171 m68k_output_movem (rtx
*operands
, rtx pattern
,
3172 HOST_WIDE_INT automod_offset
, bool store_p
)
3177 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3179 first
= (automod_offset
!= 0);
3180 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3182 /* When using movem with pre-decrement addressing, register X + D0_REG
3183 is controlled by bit 15 - X. For all other addressing modes,
3184 register X + D0_REG is controlled by bit X. Confusingly, the
3185 register mask for fmovem is in the opposite order to that for
3189 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3190 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3191 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3192 if (automod_offset
< 0)
3194 if (FP_REGNO_P (regno
))
3195 mask
|= 1 << (regno
- FP0_REG
);
3197 mask
|= 1 << (15 - (regno
- D0_REG
));
3201 if (FP_REGNO_P (regno
))
3202 mask
|= 1 << (7 - (regno
- FP0_REG
));
3204 mask
|= 1 << (regno
- D0_REG
);
3209 if (automod_offset
== 0)
3210 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3211 else if (automod_offset
< 0)
3212 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3214 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3215 operands
[1] = GEN_INT (mask
);
3216 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3219 return MOTOROLA
? "fmovm %1,%a0" : "fmovem %1,%a0";
3221 return MOTOROLA
? "fmovm %a0,%1" : "fmovem %a0,%1";
3226 return MOTOROLA
? "movm.l %1,%a0" : "moveml %1,%a0";
3228 return MOTOROLA
? "movm.l %a0,%1" : "moveml %a0,%1";
3232 /* Return a REG that occurs in ADDR with coefficient 1.
3233 ADDR can be effectively incremented by incrementing REG. */
3236 find_addr_reg (rtx addr
)
3238 while (GET_CODE (addr
) == PLUS
)
3240 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3241 addr
= XEXP (addr
, 0);
3242 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3243 addr
= XEXP (addr
, 1);
3244 else if (CONSTANT_P (XEXP (addr
, 0)))
3245 addr
= XEXP (addr
, 1);
3246 else if (CONSTANT_P (XEXP (addr
, 1)))
3247 addr
= XEXP (addr
, 0);
3251 gcc_assert (GET_CODE (addr
) == REG
);
3255 /* Output assembler code to perform a 32-bit 3-operand add. */
3258 output_addsi3 (rtx
*operands
)
3260 if (! operands_match_p (operands
[0], operands
[1]))
3262 if (!ADDRESS_REG_P (operands
[1]))
3264 rtx tmp
= operands
[1];
3266 operands
[1] = operands
[2];
3270 /* These insns can result from reloads to access
3271 stack slots over 64k from the frame pointer. */
3272 if (GET_CODE (operands
[2]) == CONST_INT
3273 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3274 return "move%.l %2,%0\n\tadd%.l %1,%0";
3275 if (GET_CODE (operands
[2]) == REG
)
3276 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3277 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3279 if (GET_CODE (operands
[2]) == CONST_INT
)
3281 if (INTVAL (operands
[2]) > 0
3282 && INTVAL (operands
[2]) <= 8)
3283 return "addq%.l %2,%0";
3284 if (INTVAL (operands
[2]) < 0
3285 && INTVAL (operands
[2]) >= -8)
3287 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3288 return "subq%.l %2,%0";
3290 /* On the CPU32 it is faster to use two addql instructions to
3291 add a small integer (8 < N <= 16) to a register.
3292 Likewise for subql. */
3293 if (TUNE_CPU32
&& REG_P (operands
[0]))
3295 if (INTVAL (operands
[2]) > 8
3296 && INTVAL (operands
[2]) <= 16)
3298 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3299 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3301 if (INTVAL (operands
[2]) < -8
3302 && INTVAL (operands
[2]) >= -16)
3304 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3305 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3308 if (ADDRESS_REG_P (operands
[0])
3309 && INTVAL (operands
[2]) >= -0x8000
3310 && INTVAL (operands
[2]) < 0x8000)
3313 return "add%.w %2,%0";
3315 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3318 return "add%.l %2,%0";
3321 /* Store in cc_status the expressions that the condition codes will
3322 describe after execution of an instruction whose pattern is EXP.
3323 Do not alter them if the instruction would not alter the cc's. */
3325 /* On the 68000, all the insns to store in an address register fail to
3326 set the cc's. However, in some cases these instructions can make it
3327 possibly invalid to use the saved cc's. In those cases we clear out
3328 some or all of the saved cc's so they won't be used. */
3331 notice_update_cc (rtx exp
, rtx insn
)
3333 if (GET_CODE (exp
) == SET
)
3335 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3337 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3339 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3340 cc_status
.value1
= 0;
3341 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3342 cc_status
.value2
= 0;
3344 /* fmoves to memory or data registers do not set the condition
3345 codes. Normal moves _do_ set the condition codes, but not in
3346 a way that is appropriate for comparison with 0, because -0.0
3347 would be treated as a negative nonzero number. Note that it
3348 isn't appropriate to conditionalize this restriction on
3349 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3350 we care about the difference between -0.0 and +0.0. */
3351 else if (!FP_REG_P (SET_DEST (exp
))
3352 && SET_DEST (exp
) != cc0_rtx
3353 && (FP_REG_P (SET_SRC (exp
))
3354 || GET_CODE (SET_SRC (exp
)) == FIX
3355 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3357 /* A pair of move insns doesn't produce a useful overall cc. */
3358 else if (!FP_REG_P (SET_DEST (exp
))
3359 && !FP_REG_P (SET_SRC (exp
))
3360 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3361 && (GET_CODE (SET_SRC (exp
)) == REG
3362 || GET_CODE (SET_SRC (exp
)) == MEM
3363 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3365 else if (SET_DEST (exp
) != pc_rtx
)
3367 cc_status
.flags
= 0;
3368 cc_status
.value1
= SET_DEST (exp
);
3369 cc_status
.value2
= SET_SRC (exp
);
3372 else if (GET_CODE (exp
) == PARALLEL
3373 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3375 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3376 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3378 if (ADDRESS_REG_P (dest
))
3380 else if (dest
!= pc_rtx
)
3382 cc_status
.flags
= 0;
3383 cc_status
.value1
= dest
;
3384 cc_status
.value2
= src
;
3389 if (cc_status
.value2
!= 0
3390 && ADDRESS_REG_P (cc_status
.value2
)
3391 && GET_MODE (cc_status
.value2
) == QImode
)
3393 if (cc_status
.value2
!= 0)
3394 switch (GET_CODE (cc_status
.value2
))
3396 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3397 case ROTATE
: case ROTATERT
:
3398 /* These instructions always clear the overflow bit, and set
3399 the carry to the bit shifted out. */
3400 /* ??? We don't currently have a way to signal carry not valid,
3401 nor do we check for it in the branch insns. */
3405 case PLUS
: case MINUS
: case MULT
:
3406 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3407 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3408 cc_status
.flags
|= CC_NO_OVERFLOW
;
3411 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3412 ends with a move insn moving r2 in r2's mode.
3413 Thus, the cc's are set for r2.
3414 This can set N bit spuriously. */
3415 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3420 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3422 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3423 cc_status
.value2
= 0;
3424 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3425 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3426 cc_status
.flags
= CC_IN_68881
;
3430 output_move_const_double (rtx
*operands
)
3432 int code
= standard_68881_constant_p (operands
[1]);
3436 static char buf
[40];
3438 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3441 return "fmove%.d %1,%0";
3445 output_move_const_single (rtx
*operands
)
3447 int code
= standard_68881_constant_p (operands
[1]);
3451 static char buf
[40];
3453 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3456 return "fmove%.s %f1,%0";
3459 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3460 from the "fmovecr" instruction.
3461 The value, anded with 0xff, gives the code to use in fmovecr
3462 to get the desired constant. */
3464 /* This code has been fixed for cross-compilation. */
3466 static int inited_68881_table
= 0;
3468 static const char *const strings_68881
[7] = {
3478 static const int codes_68881
[7] = {
3488 REAL_VALUE_TYPE values_68881
[7];
3490 /* Set up values_68881 array by converting the decimal values
3491 strings_68881 to binary. */
3494 init_68881_table (void)
3498 enum machine_mode mode
;
3501 for (i
= 0; i
< 7; i
++)
3505 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3506 values_68881
[i
] = r
;
3508 inited_68881_table
= 1;
3512 standard_68881_constant_p (rtx x
)
3517 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3518 used at all on those chips. */
3522 if (! inited_68881_table
)
3523 init_68881_table ();
3525 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3527 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3529 for (i
= 0; i
< 6; i
++)
3531 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3532 return (codes_68881
[i
]);
3535 if (GET_MODE (x
) == SFmode
)
3538 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3539 return (codes_68881
[6]);
3541 /* larger powers of ten in the constants ram are not used
3542 because they are not equal to a `double' C constant. */
3546 /* If X is a floating-point constant, return the logarithm of X base 2,
3547 or 0 if X is not a power of 2. */
3550 floating_exact_log2 (rtx x
)
3552 REAL_VALUE_TYPE r
, r1
;
3555 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3557 if (REAL_VALUES_LESS (r
, dconst1
))
3560 exp
= real_exponent (&r
);
3561 real_2expN (&r1
, exp
);
3562 if (REAL_VALUES_EQUAL (r1
, r
))
3568 /* A C compound statement to output to stdio stream STREAM the
3569 assembler syntax for an instruction operand X. X is an RTL
3572 CODE is a value that can be used to specify one of several ways
3573 of printing the operand. It is used when identical operands
3574 must be printed differently depending on the context. CODE
3575 comes from the `%' specification that was used to request
3576 printing of the operand. If the specification was just `%DIGIT'
3577 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3578 is the ASCII code for LTR.
3580 If X is a register, this macro should print the register's name.
3581 The names can be found in an array `reg_names' whose type is
3582 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3584 When the machine description has a specification `%PUNCT' (a `%'
3585 followed by a punctuation character), this macro is called with
3586 a null pointer for X and the punctuation character for CODE.
3588 The m68k specific codes are:
3590 '.' for dot needed in Motorola-style opcode names.
3591 '-' for an operand pushing on the stack:
3592 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3593 '+' for an operand pushing on the stack:
3594 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3595 '@' for a reference to the top word on the stack:
3596 sp@, (sp) or (%sp) depending on the style of syntax.
3597 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3598 but & in SGS syntax).
3599 '!' for the cc register (used in an `and to cc' insn).
3600 '$' for the letter `s' in an op code, but only on the 68040.
3601 '&' for the letter `d' in an op code, but only on the 68040.
3602 '/' for register prefix needed by longlong.h.
3603 '?' for m68k_library_id_string
3605 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3606 'd' to force memory addressing to be absolute, not relative.
3607 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3608 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3609 or print pair of registers as rx:ry.
3610 'p' print an address with @PLTPC attached, but only if the operand
3611 is not locally-bound. */
3614 print_operand (FILE *file
, rtx op
, int letter
)
3619 fprintf (file
, ".");
3621 else if (letter
== '#')
3622 asm_fprintf (file
, "%I");
3623 else if (letter
== '-')
3624 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3625 else if (letter
== '+')
3626 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3627 else if (letter
== '@')
3628 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3629 else if (letter
== '!')
3630 asm_fprintf (file
, "%Rfpcr");
3631 else if (letter
== '$')
3634 fprintf (file
, "s");
3636 else if (letter
== '&')
3639 fprintf (file
, "d");
3641 else if (letter
== '/')
3642 asm_fprintf (file
, "%R");
3643 else if (letter
== '?')
3644 asm_fprintf (file
, m68k_library_id_string
);
3645 else if (letter
== 'p')
3647 output_addr_const (file
, op
);
3648 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3649 fprintf (file
, "@PLTPC");
3651 else if (GET_CODE (op
) == REG
)
3654 /* Print out the second register name of a register pair.
3655 I.e., R (6) => 7. */
3656 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3658 fputs (M68K_REGNAME(REGNO (op
)), file
);
3660 else if (GET_CODE (op
) == MEM
)
3662 output_address (XEXP (op
, 0));
3663 if (letter
== 'd' && ! TARGET_68020
3664 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3665 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3666 && INTVAL (XEXP (op
, 0)) < 0x8000
3667 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3668 fprintf (file
, MOTOROLA
? ".l" : ":l");
3670 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3673 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3674 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3676 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3679 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3680 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3682 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3685 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3686 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3690 /* Use `print_operand_address' instead of `output_addr_const'
3691 to ensure that we print relevant PIC stuff. */
3692 asm_fprintf (file
, "%I");
3694 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3695 print_operand_address (file
, op
);
3697 output_addr_const (file
, op
);
3702 /* A C compound statement to output to stdio stream STREAM the
3703 assembler syntax for an instruction operand that is a memory
3704 reference whose address is ADDR. ADDR is an RTL expression.
3706 Note that this contains a kludge that knows that the only reason
3707 we have an address (plus (label_ref...) (reg...)) when not generating
3708 PIC code is in the insn before a tablejump, and we know that m68k.md
3709 generates a label LInnn: on such an insn.
3711 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3712 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3714 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3715 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3716 we want. This difference can be accommodated by using an assembler
3717 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3718 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3719 macro. See m68k/sgs.h for an example; for versions without the bug.
3720 Some assemblers refuse all the above solutions. The workaround is to
3721 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3724 They also do not like things like "pea 1.w", so we simple leave off
3725 the .w on small constants.
3727 This routine is responsible for distinguishing between -fpic and -fPIC
3728 style relocations in an address. When generating -fpic code the
3729 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3730 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3733 print_operand_address (FILE *file
, rtx addr
)
3735 struct m68k_address address
;
3737 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3740 if (address
.code
== PRE_DEC
)
3741 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3742 M68K_REGNAME (REGNO (address
.base
)));
3743 else if (address
.code
== POST_INC
)
3744 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3745 M68K_REGNAME (REGNO (address
.base
)));
3746 else if (!address
.base
&& !address
.index
)
3748 /* A constant address. */
3749 gcc_assert (address
.offset
== addr
);
3750 if (GET_CODE (addr
) == CONST_INT
)
3752 /* (xxx).w or (xxx).l. */
3753 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3754 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3756 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3758 else if (TARGET_PCREL
)
3760 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3762 output_addr_const (file
, addr
);
3763 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3767 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3768 name ends in `.<letter>', as the last 2 characters can be
3769 mistaken as a size suffix. Put the name in parentheses. */
3770 if (GET_CODE (addr
) == SYMBOL_REF
3771 && strlen (XSTR (addr
, 0)) > 2
3772 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3775 output_addr_const (file
, addr
);
3779 output_addr_const (file
, addr
);
3786 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3787 label being accessed, otherwise it is -1. */
3788 labelno
= (address
.offset
3790 && GET_CODE (address
.offset
) == LABEL_REF
3791 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3795 /* Print the "offset(base" component. */
3797 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,", labelno
, labelno
);
3802 output_addr_const (file
, address
.offset
);
3803 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3805 fprintf (file
, "@GOT");
3806 if (flag_pic
== 1 && TARGET_68020
)
3807 fprintf (file
, ".w");
3812 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3814 /* Print the ",index" component, if any. */
3819 fprintf (file
, "%s.%c",
3820 M68K_REGNAME (REGNO (address
.index
)),
3821 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3822 if (address
.scale
!= 1)
3823 fprintf (file
, "*%d", address
.scale
);
3827 else /* !MOTOROLA */
3829 if (!address
.offset
&& !address
.index
)
3830 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3833 /* Print the "base@(offset" component. */
3835 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b", labelno
, labelno
);
3839 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3840 fprintf (file
, "@(");
3843 output_addr_const (file
, address
.offset
);
3844 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
3848 fprintf (file
, ":w"); break;
3850 fprintf (file
, ":l"); break;
3856 /* Print the ",index" component, if any. */
3859 fprintf (file
, ",%s:%c",
3860 M68K_REGNAME (REGNO (address
.index
)),
3861 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3862 if (address
.scale
!= 1)
3863 fprintf (file
, ":%d", address
.scale
);
3871 /* Check for cases where a clr insns can be omitted from code using
3872 strict_low_part sets. For example, the second clrl here is not needed:
3873 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3875 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3876 insn we are checking for redundancy. TARGET is the register set by the
3880 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3885 p
= prev_nonnote_insn (first_insn
);
3889 /* If it isn't an insn, then give up. */
3890 if (GET_CODE (p
) != INSN
)
3893 if (reg_set_p (target
, p
))
3895 rtx set
= single_set (p
);
3898 /* If it isn't an easy to recognize insn, then give up. */
3902 dest
= SET_DEST (set
);
3904 /* If this sets the entire target register to zero, then our
3905 first_insn is redundant. */
3906 if (rtx_equal_p (dest
, target
)
3907 && SET_SRC (set
) == const0_rtx
)
3909 else if (GET_CODE (dest
) == STRICT_LOW_PART
3910 && GET_CODE (XEXP (dest
, 0)) == REG
3911 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3912 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3913 <= GET_MODE_SIZE (mode
)))
3914 /* This is a strict low part set which modifies less than
3915 we are using, so it is safe. */
3921 p
= prev_nonnote_insn (p
);
3927 /* Operand predicates for implementing asymmetric pc-relative addressing
3928 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3929 when used as a source operand, but not as a destination operand.
3931 We model this by restricting the meaning of the basic predicates
3932 (general_operand, memory_operand, etc) to forbid the use of this
3933 addressing mode, and then define the following predicates that permit
3934 this addressing mode. These predicates can then be used for the
3935 source operands of the appropriate instructions.
3937 n.b. While it is theoretically possible to change all machine patterns
3938 to use this addressing more where permitted by the architecture,
3939 it has only been implemented for "common" cases: SImode, HImode, and
3940 QImode operands, and only for the principle operations that would
3941 require this addressing mode: data movement and simple integer operations.
3943 In parallel with these new predicates, two new constraint letters
3944 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3945 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3946 In the pcrel case 's' is only valid in combination with 'a' registers.
3947 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3948 of how these constraints are used.
3950 The use of these predicates is strictly optional, though patterns that
3951 don't will cause an extra reload register to be allocated where one
3954 lea (abc:w,%pc),%a0 ; need to reload address
3955 moveq &1,%d1 ; since write to pc-relative space
3956 movel %d1,%a0@ ; is not allowed
3958 lea (abc:w,%pc),%a1 ; no need to reload address here
3959 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3961 For more info, consult tiemann@cygnus.com.
3964 All of the ugliness with predicates and constraints is due to the
3965 simple fact that the m68k does not allow a pc-relative addressing
3966 mode as a destination. gcc does not distinguish between source and
3967 destination addresses. Hence, if we claim that pc-relative address
3968 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3969 end up with invalid code. To get around this problem, we left
3970 pc-relative modes as invalid addresses, and then added special
3971 predicates and constraints to accept them.
3973 A cleaner way to handle this is to modify gcc to distinguish
3974 between source and destination addresses. We can then say that
3975 pc-relative is a valid source address but not a valid destination
3976 address, and hopefully avoid a lot of the predicate and constraint
3977 hackery. Unfortunately, this would be a pretty big change. It would
3978 be a useful change for a number of ports, but there aren't any current
3979 plans to undertake this.
3981 ***************************************************************************/
3985 output_andsi3 (rtx
*operands
)
3988 if (GET_CODE (operands
[2]) == CONST_INT
3989 && (INTVAL (operands
[2]) | 0xffff) == -1
3990 && (DATA_REG_P (operands
[0])
3991 || offsettable_memref_p (operands
[0]))
3992 && !TARGET_COLDFIRE
)
3994 if (GET_CODE (operands
[0]) != REG
)
3995 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3996 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3997 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3999 if (operands
[2] == const0_rtx
)
4001 return "and%.w %2,%0";
4003 if (GET_CODE (operands
[2]) == CONST_INT
4004 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
4005 && (DATA_REG_P (operands
[0])
4006 || offsettable_memref_p (operands
[0])))
4008 if (DATA_REG_P (operands
[0]))
4009 operands
[1] = GEN_INT (logval
);
4012 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4013 operands
[1] = GEN_INT (logval
% 8);
4015 /* This does not set condition codes in a standard way. */
4017 return "bclr %1,%0";
4019 return "and%.l %2,%0";
4023 output_iorsi3 (rtx
*operands
)
4025 register int logval
;
4026 if (GET_CODE (operands
[2]) == CONST_INT
4027 && INTVAL (operands
[2]) >> 16 == 0
4028 && (DATA_REG_P (operands
[0])
4029 || offsettable_memref_p (operands
[0]))
4030 && !TARGET_COLDFIRE
)
4032 if (GET_CODE (operands
[0]) != REG
)
4033 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4034 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4036 if (INTVAL (operands
[2]) == 0xffff)
4037 return "mov%.w %2,%0";
4038 return "or%.w %2,%0";
4040 if (GET_CODE (operands
[2]) == CONST_INT
4041 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4042 && (DATA_REG_P (operands
[0])
4043 || offsettable_memref_p (operands
[0])))
4045 if (DATA_REG_P (operands
[0]))
4046 operands
[1] = GEN_INT (logval
);
4049 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4050 operands
[1] = GEN_INT (logval
% 8);
4053 return "bset %1,%0";
4055 return "or%.l %2,%0";
4059 output_xorsi3 (rtx
*operands
)
4061 register int logval
;
4062 if (GET_CODE (operands
[2]) == CONST_INT
4063 && INTVAL (operands
[2]) >> 16 == 0
4064 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4065 && !TARGET_COLDFIRE
)
4067 if (! DATA_REG_P (operands
[0]))
4068 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4069 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4071 if (INTVAL (operands
[2]) == 0xffff)
4073 return "eor%.w %2,%0";
4075 if (GET_CODE (operands
[2]) == CONST_INT
4076 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4077 && (DATA_REG_P (operands
[0])
4078 || offsettable_memref_p (operands
[0])))
4080 if (DATA_REG_P (operands
[0]))
4081 operands
[1] = GEN_INT (logval
);
4084 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4085 operands
[1] = GEN_INT (logval
% 8);
4088 return "bchg %1,%0";
4090 return "eor%.l %2,%0";
4093 /* Return the instruction that should be used for a call to address X,
4094 which is known to be in operand 0. */
4099 if (symbolic_operand (x
, VOIDmode
))
4100 return m68k_symbolic_call
;
4105 /* Likewise sibling calls. */
4108 output_sibcall (rtx x
)
4110 if (symbolic_operand (x
, VOIDmode
))
4111 return m68k_symbolic_jump
;
4116 #ifdef M68K_TARGET_COFF
4118 /* Output assembly to switch to section NAME with attribute FLAGS. */
4121 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
4122 tree decl ATTRIBUTE_UNUSED
)
4126 if (flags
& SECTION_WRITE
)
4131 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4134 #endif /* M68K_TARGET_COFF */
4137 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4138 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4141 rtx this_slot
, offset
, addr
, mem
, insn
;
4143 /* Pretend to be a post-reload pass while generating rtl. */
4145 reload_completed
= 1;
4146 allocate_reg_info (FIRST_PSEUDO_REGISTER
, true, true);
4148 /* The "this" pointer is stored at 4(%sp). */
4149 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
4151 /* Add DELTA to THIS. */
4154 /* Make the offset a legitimate operand for memory addition. */
4155 offset
= GEN_INT (delta
);
4156 if ((delta
< -8 || delta
> 8)
4157 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
4159 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
4160 offset
= gen_rtx_REG (Pmode
, D0_REG
);
4162 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
4163 copy_rtx (this_slot
), offset
));
4166 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4167 if (vcall_offset
!= 0)
4169 /* Set the static chain register to *THIS. */
4170 emit_move_insn (static_chain_rtx
, this_slot
);
4171 emit_move_insn (static_chain_rtx
, gen_rtx_MEM (Pmode
, static_chain_rtx
));
4173 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4174 addr
= plus_constant (static_chain_rtx
, vcall_offset
);
4175 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
4177 emit_insn (gen_rtx_SET (VOIDmode
, static_chain_rtx
, addr
));
4178 addr
= static_chain_rtx
;
4181 /* Load the offset into %d0 and add it to THIS. */
4182 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
4183 gen_rtx_MEM (Pmode
, addr
));
4184 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
4185 copy_rtx (this_slot
),
4186 gen_rtx_REG (Pmode
, D0_REG
)));
4189 /* Jump to the target function. Use a sibcall if direct jumps are
4190 allowed, otherwise load the address into a register first. */
4191 mem
= DECL_RTL (function
);
4192 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
4194 gcc_assert (flag_pic
);
4196 if (!TARGET_SEP_DATA
)
4198 /* Use the static chain register as a temporary (call-clobbered)
4199 GOT pointer for this function. We can use the static chain
4200 register because it isn't live on entry to the thunk. */
4201 REGNO (pic_offset_table_rtx
) = STATIC_CHAIN_REGNUM
;
4202 emit_insn (gen_load_got (pic_offset_table_rtx
));
4204 legitimize_pic_address (XEXP (mem
, 0), Pmode
, static_chain_rtx
);
4205 mem
= replace_equiv_address (mem
, static_chain_rtx
);
4207 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
4208 SIBLING_CALL_P (insn
) = 1;
4210 /* Run just enough of rest_of_compilation. */
4211 insn
= get_insns ();
4212 split_all_insns_noflow ();
4213 final_start_function (insn
, file
, 1);
4214 final (insn
, file
, 1);
4215 final_end_function ();
4217 /* Clean up the vars set above. */
4218 reload_completed
= 0;
4221 /* Restore the original PIC register. */
4223 REGNO (pic_offset_table_rtx
) = PIC_REG
;
4226 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4229 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4230 int incoming ATTRIBUTE_UNUSED
)
4232 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4235 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4237 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4238 unsigned int new_reg
)
4241 /* Interrupt functions can only use registers that have already been
4242 saved by the prologue, even if they would normally be
4245 if ((m68k_get_function_kind (current_function_decl
)
4246 == m68k_fk_interrupt_handler
)
4247 && !regs_ever_live
[new_reg
])
4253 /* Value is true if hard register REGNO can hold a value of machine-mode
4254 MODE. On the 68000, we let the cpu registers can hold any mode, but
4255 restrict the 68881 registers to floating-point modes. */
4258 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4260 if (DATA_REGNO_P (regno
))
4262 /* Data Registers, can hold aggregate if fits in. */
4263 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4266 else if (ADDRESS_REGNO_P (regno
))
4268 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4271 else if (FP_REGNO_P (regno
))
4273 /* FPU registers, hold float or complex float of long double or
4275 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4276 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4277 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4283 /* Implement SECONDARY_RELOAD_CLASS. */
4286 m68k_secondary_reload_class (enum reg_class rclass
,
4287 enum machine_mode mode
, rtx x
)
4291 regno
= true_regnum (x
);
4293 /* If one operand of a movqi is an address register, the other
4294 operand must be a general register or constant. Other types
4295 of operand must be reloaded through a data register. */
4296 if (GET_MODE_SIZE (mode
) == 1
4297 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
4298 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
4301 /* PC-relative addresses must be loaded into an address register first. */
4303 && !reg_class_subset_p (rclass
, ADDR_REGS
)
4304 && symbolic_operand (x
, VOIDmode
))
4310 /* Implement PREFERRED_RELOAD_CLASS. */
4313 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
4315 enum reg_class secondary_class
;
4317 /* If RCLASS might need a secondary reload, try restricting it to
4318 a class that doesn't. */
4319 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
4320 if (secondary_class
!= NO_REGS
4321 && reg_class_subset_p (secondary_class
, rclass
))
4322 return secondary_class
;
4324 /* Prefer to use moveq for in-range constants. */
4325 if (GET_CODE (x
) == CONST_INT
4326 && reg_class_subset_p (DATA_REGS
, rclass
)
4327 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
4330 /* ??? Do we really need this now? */
4331 if (GET_CODE (x
) == CONST_DOUBLE
4332 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4334 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
4343 /* Return floating point values in a 68881 register. This makes 68881 code
4344 a little bit faster. It also makes -msoft-float code incompatible with
4345 hard-float code, so people have to be careful not to mix the two.
4346 For ColdFire it was decided the ABI incompatibility is undesirable.
4347 If there is need for a hard-float ABI it is probably worth doing it
4348 properly and also passing function arguments in FP registers. */
4350 m68k_libcall_value (enum machine_mode mode
)
4357 return gen_rtx_REG (mode
, FP0_REG
);
4362 return gen_rtx_REG (mode
, D0_REG
);
4366 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4368 enum machine_mode mode
;
4370 mode
= TYPE_MODE (valtype
);
4376 return gen_rtx_REG (mode
, FP0_REG
);
4382 /* If the function returns a pointer, push that into %a0. */
4383 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4384 /* For compatibility with the large body of existing code which
4385 does not always properly declare external functions returning
4386 pointer types, the m68k/SVR4 convention is to copy the value
4387 returned for pointer functions from a0 to d0 in the function
4388 epilogue, so that callers that have neglected to properly
4389 declare the callee can still find the correct return value in
4391 return gen_rtx_PARALLEL
4394 gen_rtx_EXPR_LIST (VOIDmode
,
4395 gen_rtx_REG (mode
, A0_REG
),
4397 gen_rtx_EXPR_LIST (VOIDmode
,
4398 gen_rtx_REG (mode
, D0_REG
),
4400 else if (POINTER_TYPE_P (valtype
))
4401 return gen_rtx_REG (mode
, A0_REG
);
4403 return gen_rtx_REG (mode
, D0_REG
);